mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 01:28:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
576
arch/x86/kvm/pmu.c
Normal file
576
arch/x86/kvm/pmu.c
Normal file
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@ -0,0 +1,576 @@
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/*
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* Kernel-based Virtual Machine -- Performance Monitoring Unit support
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*
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* Copyright 2011 Red Hat, Inc. and/or its affiliates.
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*
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* Authors:
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* Avi Kivity <avi@redhat.com>
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* Gleb Natapov <gleb@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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*/
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#include <linux/types.h>
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#include <linux/kvm_host.h>
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#include <linux/perf_event.h>
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#include <asm/perf_event.h>
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#include "x86.h"
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#include "cpuid.h"
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#include "lapic.h"
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static struct kvm_arch_event_perf_mapping {
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u8 eventsel;
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u8 unit_mask;
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unsigned event_type;
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bool inexact;
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} arch_events[] = {
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/* Index must match CPUID 0x0A.EBX bit vector */
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[0] = { 0x3c, 0x00, PERF_COUNT_HW_CPU_CYCLES },
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[1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
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[2] = { 0x3c, 0x01, PERF_COUNT_HW_BUS_CYCLES },
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[3] = { 0x2e, 0x4f, PERF_COUNT_HW_CACHE_REFERENCES },
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[4] = { 0x2e, 0x41, PERF_COUNT_HW_CACHE_MISSES },
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[5] = { 0xc4, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
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[6] = { 0xc5, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
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[7] = { 0x00, 0x30, PERF_COUNT_HW_REF_CPU_CYCLES },
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};
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/* mapping between fixed pmc index and arch_events array */
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int fixed_pmc_events[] = {1, 0, 7};
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static bool pmc_is_gp(struct kvm_pmc *pmc)
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{
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return pmc->type == KVM_PMC_GP;
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}
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static inline u64 pmc_bitmask(struct kvm_pmc *pmc)
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{
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struct kvm_pmu *pmu = &pmc->vcpu->arch.pmu;
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return pmu->counter_bitmask[pmc->type];
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}
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static inline bool pmc_enabled(struct kvm_pmc *pmc)
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{
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struct kvm_pmu *pmu = &pmc->vcpu->arch.pmu;
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return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
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}
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static inline struct kvm_pmc *get_gp_pmc(struct kvm_pmu *pmu, u32 msr,
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u32 base)
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{
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if (msr >= base && msr < base + pmu->nr_arch_gp_counters)
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return &pmu->gp_counters[msr - base];
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return NULL;
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}
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static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr)
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{
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int base = MSR_CORE_PERF_FIXED_CTR0;
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if (msr >= base && msr < base + pmu->nr_arch_fixed_counters)
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return &pmu->fixed_counters[msr - base];
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return NULL;
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}
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static inline struct kvm_pmc *get_fixed_pmc_idx(struct kvm_pmu *pmu, int idx)
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{
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return get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + idx);
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}
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static struct kvm_pmc *global_idx_to_pmc(struct kvm_pmu *pmu, int idx)
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{
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if (idx < INTEL_PMC_IDX_FIXED)
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return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + idx, MSR_P6_EVNTSEL0);
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else
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return get_fixed_pmc_idx(pmu, idx - INTEL_PMC_IDX_FIXED);
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}
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void kvm_deliver_pmi(struct kvm_vcpu *vcpu)
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{
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if (vcpu->arch.apic)
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kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTPC);
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}
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static void trigger_pmi(struct irq_work *irq_work)
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{
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struct kvm_pmu *pmu = container_of(irq_work, struct kvm_pmu,
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irq_work);
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struct kvm_vcpu *vcpu = container_of(pmu, struct kvm_vcpu,
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arch.pmu);
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kvm_deliver_pmi(vcpu);
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}
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static void kvm_perf_overflow(struct perf_event *perf_event,
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struct perf_sample_data *data,
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struct pt_regs *regs)
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{
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struct kvm_pmc *pmc = perf_event->overflow_handler_context;
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struct kvm_pmu *pmu = &pmc->vcpu->arch.pmu;
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if (!test_and_set_bit(pmc->idx, (unsigned long *)&pmu->reprogram_pmi)) {
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__set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
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kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
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}
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}
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static void kvm_perf_overflow_intr(struct perf_event *perf_event,
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struct perf_sample_data *data, struct pt_regs *regs)
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{
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struct kvm_pmc *pmc = perf_event->overflow_handler_context;
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struct kvm_pmu *pmu = &pmc->vcpu->arch.pmu;
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if (!test_and_set_bit(pmc->idx, (unsigned long *)&pmu->reprogram_pmi)) {
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__set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
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kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
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/*
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* Inject PMI. If vcpu was in a guest mode during NMI PMI
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* can be ejected on a guest mode re-entry. Otherwise we can't
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* be sure that vcpu wasn't executing hlt instruction at the
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* time of vmexit and is not going to re-enter guest mode until,
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* woken up. So we should wake it, but this is impossible from
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* NMI context. Do it from irq work instead.
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*/
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if (!kvm_is_in_guest())
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irq_work_queue(&pmc->vcpu->arch.pmu.irq_work);
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else
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kvm_make_request(KVM_REQ_PMI, pmc->vcpu);
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}
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}
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static u64 read_pmc(struct kvm_pmc *pmc)
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{
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u64 counter, enabled, running;
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counter = pmc->counter;
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if (pmc->perf_event)
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counter += perf_event_read_value(pmc->perf_event,
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&enabled, &running);
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/* FIXME: Scaling needed? */
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return counter & pmc_bitmask(pmc);
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}
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static void stop_counter(struct kvm_pmc *pmc)
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{
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if (pmc->perf_event) {
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pmc->counter = read_pmc(pmc);
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perf_event_release_kernel(pmc->perf_event);
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pmc->perf_event = NULL;
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}
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}
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static void reprogram_counter(struct kvm_pmc *pmc, u32 type,
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unsigned config, bool exclude_user, bool exclude_kernel,
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bool intr, bool in_tx, bool in_tx_cp)
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{
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struct perf_event *event;
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struct perf_event_attr attr = {
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.type = type,
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.size = sizeof(attr),
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.pinned = true,
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.exclude_idle = true,
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.exclude_host = 1,
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.exclude_user = exclude_user,
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.exclude_kernel = exclude_kernel,
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.config = config,
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};
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if (in_tx)
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attr.config |= HSW_IN_TX;
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if (in_tx_cp)
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attr.config |= HSW_IN_TX_CHECKPOINTED;
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attr.sample_period = (-pmc->counter) & pmc_bitmask(pmc);
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event = perf_event_create_kernel_counter(&attr, -1, current,
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intr ? kvm_perf_overflow_intr :
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kvm_perf_overflow, pmc);
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if (IS_ERR(event)) {
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printk_once("kvm: pmu event creation failed %ld\n",
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PTR_ERR(event));
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return;
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}
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pmc->perf_event = event;
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clear_bit(pmc->idx, (unsigned long*)&pmc->vcpu->arch.pmu.reprogram_pmi);
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}
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static unsigned find_arch_event(struct kvm_pmu *pmu, u8 event_select,
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u8 unit_mask)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(arch_events); i++)
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if (arch_events[i].eventsel == event_select
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&& arch_events[i].unit_mask == unit_mask
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&& (pmu->available_event_types & (1 << i)))
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break;
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if (i == ARRAY_SIZE(arch_events))
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return PERF_COUNT_HW_MAX;
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return arch_events[i].event_type;
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}
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static void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
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{
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unsigned config, type = PERF_TYPE_RAW;
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u8 event_select, unit_mask;
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if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL)
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printk_once("kvm pmu: pin control bit is ignored\n");
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pmc->eventsel = eventsel;
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stop_counter(pmc);
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if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_enabled(pmc))
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return;
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event_select = eventsel & ARCH_PERFMON_EVENTSEL_EVENT;
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unit_mask = (eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
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if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE |
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ARCH_PERFMON_EVENTSEL_INV |
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ARCH_PERFMON_EVENTSEL_CMASK |
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HSW_IN_TX |
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HSW_IN_TX_CHECKPOINTED))) {
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config = find_arch_event(&pmc->vcpu->arch.pmu, event_select,
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unit_mask);
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if (config != PERF_COUNT_HW_MAX)
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type = PERF_TYPE_HARDWARE;
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}
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if (type == PERF_TYPE_RAW)
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config = eventsel & X86_RAW_EVENT_MASK;
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reprogram_counter(pmc, type, config,
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!(eventsel & ARCH_PERFMON_EVENTSEL_USR),
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!(eventsel & ARCH_PERFMON_EVENTSEL_OS),
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eventsel & ARCH_PERFMON_EVENTSEL_INT,
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(eventsel & HSW_IN_TX),
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(eventsel & HSW_IN_TX_CHECKPOINTED));
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}
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static void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 en_pmi, int idx)
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{
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unsigned en = en_pmi & 0x3;
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bool pmi = en_pmi & 0x8;
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stop_counter(pmc);
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if (!en || !pmc_enabled(pmc))
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return;
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reprogram_counter(pmc, PERF_TYPE_HARDWARE,
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arch_events[fixed_pmc_events[idx]].event_type,
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!(en & 0x2), /* exclude user */
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!(en & 0x1), /* exclude kernel */
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pmi, false, false);
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}
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static inline u8 fixed_en_pmi(u64 ctrl, int idx)
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{
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return (ctrl >> (idx * 4)) & 0xf;
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}
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static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)
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{
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int i;
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for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
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u8 en_pmi = fixed_en_pmi(data, i);
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struct kvm_pmc *pmc = get_fixed_pmc_idx(pmu, i);
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if (fixed_en_pmi(pmu->fixed_ctr_ctrl, i) == en_pmi)
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continue;
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reprogram_fixed_counter(pmc, en_pmi, i);
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}
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pmu->fixed_ctr_ctrl = data;
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}
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static void reprogram_idx(struct kvm_pmu *pmu, int idx)
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{
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struct kvm_pmc *pmc = global_idx_to_pmc(pmu, idx);
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if (!pmc)
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return;
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if (pmc_is_gp(pmc))
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reprogram_gp_counter(pmc, pmc->eventsel);
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else {
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int fidx = idx - INTEL_PMC_IDX_FIXED;
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reprogram_fixed_counter(pmc,
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fixed_en_pmi(pmu->fixed_ctr_ctrl, fidx), fidx);
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}
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}
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static void global_ctrl_changed(struct kvm_pmu *pmu, u64 data)
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{
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int bit;
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u64 diff = pmu->global_ctrl ^ data;
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pmu->global_ctrl = data;
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for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX)
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reprogram_idx(pmu, bit);
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}
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bool kvm_pmu_msr(struct kvm_vcpu *vcpu, u32 msr)
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{
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struct kvm_pmu *pmu = &vcpu->arch.pmu;
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int ret;
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switch (msr) {
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case MSR_CORE_PERF_FIXED_CTR_CTRL:
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case MSR_CORE_PERF_GLOBAL_STATUS:
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case MSR_CORE_PERF_GLOBAL_CTRL:
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case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
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ret = pmu->version > 1;
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break;
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default:
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ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)
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|| get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0)
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|| get_fixed_pmc(pmu, msr);
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break;
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}
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return ret;
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}
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int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
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{
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struct kvm_pmu *pmu = &vcpu->arch.pmu;
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struct kvm_pmc *pmc;
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switch (index) {
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case MSR_CORE_PERF_FIXED_CTR_CTRL:
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*data = pmu->fixed_ctr_ctrl;
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return 0;
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case MSR_CORE_PERF_GLOBAL_STATUS:
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*data = pmu->global_status;
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return 0;
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case MSR_CORE_PERF_GLOBAL_CTRL:
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*data = pmu->global_ctrl;
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return 0;
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case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
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*data = pmu->global_ovf_ctrl;
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return 0;
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default:
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if ((pmc = get_gp_pmc(pmu, index, MSR_IA32_PERFCTR0)) ||
|
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(pmc = get_fixed_pmc(pmu, index))) {
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*data = read_pmc(pmc);
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return 0;
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} else if ((pmc = get_gp_pmc(pmu, index, MSR_P6_EVNTSEL0))) {
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*data = pmc->eventsel;
|
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return 0;
|
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}
|
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}
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return 1;
|
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}
|
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|
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int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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{
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struct kvm_pmu *pmu = &vcpu->arch.pmu;
|
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struct kvm_pmc *pmc;
|
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u32 index = msr_info->index;
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u64 data = msr_info->data;
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switch (index) {
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case MSR_CORE_PERF_FIXED_CTR_CTRL:
|
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if (pmu->fixed_ctr_ctrl == data)
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return 0;
|
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if (!(data & 0xfffffffffffff444ull)) {
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reprogram_fixed_counters(pmu, data);
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return 0;
|
||||
}
|
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break;
|
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case MSR_CORE_PERF_GLOBAL_STATUS:
|
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if (msr_info->host_initiated) {
|
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pmu->global_status = data;
|
||||
return 0;
|
||||
}
|
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break; /* RO MSR */
|
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case MSR_CORE_PERF_GLOBAL_CTRL:
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if (pmu->global_ctrl == data)
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return 0;
|
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if (!(data & pmu->global_ctrl_mask)) {
|
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global_ctrl_changed(pmu, data);
|
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return 0;
|
||||
}
|
||||
break;
|
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case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
|
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if (!(data & (pmu->global_ctrl_mask & ~(3ull<<62)))) {
|
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if (!msr_info->host_initiated)
|
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pmu->global_status &= ~data;
|
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pmu->global_ovf_ctrl = data;
|
||||
return 0;
|
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}
|
||||
break;
|
||||
default:
|
||||
if ((pmc = get_gp_pmc(pmu, index, MSR_IA32_PERFCTR0)) ||
|
||||
(pmc = get_fixed_pmc(pmu, index))) {
|
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if (!msr_info->host_initiated)
|
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data = (s64)(s32)data;
|
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pmc->counter += data - read_pmc(pmc);
|
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return 0;
|
||||
} else if ((pmc = get_gp_pmc(pmu, index, MSR_P6_EVNTSEL0))) {
|
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if (data == pmc->eventsel)
|
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return 0;
|
||||
if (!(data & pmu->reserved_bits)) {
|
||||
reprogram_gp_counter(pmc, data);
|
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return 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
int kvm_pmu_check_pmc(struct kvm_vcpu *vcpu, unsigned pmc)
|
||||
{
|
||||
struct kvm_pmu *pmu = &vcpu->arch.pmu;
|
||||
bool fixed = pmc & (1u << 30);
|
||||
pmc &= ~(3u << 30);
|
||||
return (!fixed && pmc >= pmu->nr_arch_gp_counters) ||
|
||||
(fixed && pmc >= pmu->nr_arch_fixed_counters);
|
||||
}
|
||||
|
||||
int kvm_pmu_read_pmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data)
|
||||
{
|
||||
struct kvm_pmu *pmu = &vcpu->arch.pmu;
|
||||
bool fast_mode = pmc & (1u << 31);
|
||||
bool fixed = pmc & (1u << 30);
|
||||
struct kvm_pmc *counters;
|
||||
u64 ctr;
|
||||
|
||||
pmc &= ~(3u << 30);
|
||||
if (!fixed && pmc >= pmu->nr_arch_gp_counters)
|
||||
return 1;
|
||||
if (fixed && pmc >= pmu->nr_arch_fixed_counters)
|
||||
return 1;
|
||||
counters = fixed ? pmu->fixed_counters : pmu->gp_counters;
|
||||
ctr = read_pmc(&counters[pmc]);
|
||||
if (fast_mode)
|
||||
ctr = (u32)ctr;
|
||||
*data = ctr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct kvm_pmu *pmu = &vcpu->arch.pmu;
|
||||
struct kvm_cpuid_entry2 *entry;
|
||||
union cpuid10_eax eax;
|
||||
union cpuid10_edx edx;
|
||||
|
||||
pmu->nr_arch_gp_counters = 0;
|
||||
pmu->nr_arch_fixed_counters = 0;
|
||||
pmu->counter_bitmask[KVM_PMC_GP] = 0;
|
||||
pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
|
||||
pmu->version = 0;
|
||||
pmu->reserved_bits = 0xffffffff00200000ull;
|
||||
|
||||
entry = kvm_find_cpuid_entry(vcpu, 0xa, 0);
|
||||
if (!entry)
|
||||
return;
|
||||
eax.full = entry->eax;
|
||||
edx.full = entry->edx;
|
||||
|
||||
pmu->version = eax.split.version_id;
|
||||
if (!pmu->version)
|
||||
return;
|
||||
|
||||
pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters,
|
||||
INTEL_PMC_MAX_GENERIC);
|
||||
pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1;
|
||||
pmu->available_event_types = ~entry->ebx &
|
||||
((1ull << eax.split.mask_length) - 1);
|
||||
|
||||
if (pmu->version == 1) {
|
||||
pmu->nr_arch_fixed_counters = 0;
|
||||
} else {
|
||||
pmu->nr_arch_fixed_counters =
|
||||
min_t(int, edx.split.num_counters_fixed,
|
||||
INTEL_PMC_MAX_FIXED);
|
||||
pmu->counter_bitmask[KVM_PMC_FIXED] =
|
||||
((u64)1 << edx.split.bit_width_fixed) - 1;
|
||||
}
|
||||
|
||||
pmu->global_ctrl = ((1 << pmu->nr_arch_gp_counters) - 1) |
|
||||
(((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);
|
||||
pmu->global_ctrl_mask = ~pmu->global_ctrl;
|
||||
|
||||
entry = kvm_find_cpuid_entry(vcpu, 7, 0);
|
||||
if (entry &&
|
||||
(boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) &&
|
||||
(entry->ebx & (X86_FEATURE_HLE|X86_FEATURE_RTM)))
|
||||
pmu->reserved_bits ^= HSW_IN_TX|HSW_IN_TX_CHECKPOINTED;
|
||||
}
|
||||
|
||||
void kvm_pmu_init(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
int i;
|
||||
struct kvm_pmu *pmu = &vcpu->arch.pmu;
|
||||
|
||||
memset(pmu, 0, sizeof(*pmu));
|
||||
for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
|
||||
pmu->gp_counters[i].type = KVM_PMC_GP;
|
||||
pmu->gp_counters[i].vcpu = vcpu;
|
||||
pmu->gp_counters[i].idx = i;
|
||||
}
|
||||
for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) {
|
||||
pmu->fixed_counters[i].type = KVM_PMC_FIXED;
|
||||
pmu->fixed_counters[i].vcpu = vcpu;
|
||||
pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED;
|
||||
}
|
||||
init_irq_work(&pmu->irq_work, trigger_pmi);
|
||||
kvm_pmu_cpuid_update(vcpu);
|
||||
}
|
||||
|
||||
void kvm_pmu_reset(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct kvm_pmu *pmu = &vcpu->arch.pmu;
|
||||
int i;
|
||||
|
||||
irq_work_sync(&pmu->irq_work);
|
||||
for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
|
||||
struct kvm_pmc *pmc = &pmu->gp_counters[i];
|
||||
stop_counter(pmc);
|
||||
pmc->counter = pmc->eventsel = 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < INTEL_PMC_MAX_FIXED; i++)
|
||||
stop_counter(&pmu->fixed_counters[i]);
|
||||
|
||||
pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status =
|
||||
pmu->global_ovf_ctrl = 0;
|
||||
}
|
||||
|
||||
void kvm_pmu_destroy(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
kvm_pmu_reset(vcpu);
|
||||
}
|
||||
|
||||
void kvm_handle_pmu_event(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct kvm_pmu *pmu = &vcpu->arch.pmu;
|
||||
u64 bitmask;
|
||||
int bit;
|
||||
|
||||
bitmask = pmu->reprogram_pmi;
|
||||
|
||||
for_each_set_bit(bit, (unsigned long *)&bitmask, X86_PMC_IDX_MAX) {
|
||||
struct kvm_pmc *pmc = global_idx_to_pmc(pmu, bit);
|
||||
|
||||
if (unlikely(!pmc || !pmc->perf_event)) {
|
||||
clear_bit(bit, (unsigned long *)&pmu->reprogram_pmi);
|
||||
continue;
|
||||
}
|
||||
|
||||
reprogram_idx(pmu, bit);
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue