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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 09:08:05 -04:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
329
arch/x86/power/cpu.c
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329
arch/x86/power/cpu.c
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/*
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* Suspend support specific for i386/x86-64.
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*
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* Distribute under GPLv2
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*
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* Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
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* Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
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* Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
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*/
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#include <linux/suspend.h>
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#include <linux/export.h>
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#include <linux/smp.h>
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#include <linux/perf_event.h>
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#include <asm/pgtable.h>
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#include <asm/proto.h>
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#include <asm/mtrr.h>
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#include <asm/page.h>
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#include <asm/mce.h>
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#include <asm/xcr.h>
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#include <asm/suspend.h>
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#include <asm/debugreg.h>
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#include <asm/fpu-internal.h> /* pcntxt_mask */
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#include <asm/cpu.h>
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#ifdef CONFIG_X86_32
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__visible unsigned long saved_context_ebx;
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__visible unsigned long saved_context_esp, saved_context_ebp;
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__visible unsigned long saved_context_esi, saved_context_edi;
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__visible unsigned long saved_context_eflags;
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#endif
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struct saved_context saved_context;
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/**
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* __save_processor_state - save CPU registers before creating a
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* hibernation image and before restoring the memory state from it
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* @ctxt - structure to store the registers contents in
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*
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* NOTE: If there is a CPU register the modification of which by the
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* boot kernel (ie. the kernel used for loading the hibernation image)
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* might affect the operations of the restored target kernel (ie. the one
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* saved in the hibernation image), then its contents must be saved by this
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* function. In other words, if kernel A is hibernated and different
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* kernel B is used for loading the hibernation image into memory, the
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* kernel A's __save_processor_state() function must save all registers
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* needed by kernel A, so that it can operate correctly after the resume
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* regardless of what kernel B does in the meantime.
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*/
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static void __save_processor_state(struct saved_context *ctxt)
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{
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#ifdef CONFIG_X86_32
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mtrr_save_fixed_ranges(NULL);
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#endif
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kernel_fpu_begin();
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/*
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* descriptor tables
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*/
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#ifdef CONFIG_X86_32
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store_idt(&ctxt->idt);
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#else
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/* CONFIG_X86_64 */
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store_idt((struct desc_ptr *)&ctxt->idt_limit);
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#endif
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/*
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* We save it here, but restore it only in the hibernate case.
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* For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
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* mode in "secondary_startup_64". In 32-bit mode it is done via
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* 'pmode_gdt' in wakeup_start.
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*/
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ctxt->gdt_desc.size = GDT_SIZE - 1;
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ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_table(smp_processor_id());
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store_tr(ctxt->tr);
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/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
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/*
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* segment registers
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*/
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#ifdef CONFIG_X86_32
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savesegment(es, ctxt->es);
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savesegment(fs, ctxt->fs);
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savesegment(gs, ctxt->gs);
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savesegment(ss, ctxt->ss);
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#else
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/* CONFIG_X86_64 */
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asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
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asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
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asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
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asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
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asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
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rdmsrl(MSR_FS_BASE, ctxt->fs_base);
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rdmsrl(MSR_GS_BASE, ctxt->gs_base);
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rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
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mtrr_save_fixed_ranges(NULL);
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rdmsrl(MSR_EFER, ctxt->efer);
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#endif
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/*
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* control registers
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*/
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ctxt->cr0 = read_cr0();
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ctxt->cr2 = read_cr2();
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ctxt->cr3 = read_cr3();
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#ifdef CONFIG_X86_32
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ctxt->cr4 = read_cr4_safe();
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#else
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/* CONFIG_X86_64 */
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ctxt->cr4 = read_cr4();
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ctxt->cr8 = read_cr8();
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#endif
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ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
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&ctxt->misc_enable);
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}
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/* Needed by apm.c */
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void save_processor_state(void)
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{
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__save_processor_state(&saved_context);
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x86_platform.save_sched_clock_state();
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}
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#ifdef CONFIG_X86_32
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EXPORT_SYMBOL(save_processor_state);
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#endif
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static void do_fpu_end(void)
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{
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/*
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* Restore FPU regs if necessary.
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*/
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kernel_fpu_end();
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}
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static void fix_processor_context(void)
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{
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int cpu = smp_processor_id();
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struct tss_struct *t = &per_cpu(init_tss, cpu);
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#ifdef CONFIG_X86_64
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struct desc_struct *desc = get_cpu_gdt_table(cpu);
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tss_desc tss;
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#endif
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set_tss_desc(cpu, t); /*
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* This just modifies memory; should not be
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* necessary. But... This is necessary, because
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* 386 hardware has concept of busy TSS or some
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* similar stupidity.
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*/
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#ifdef CONFIG_X86_64
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memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
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tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
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write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
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syscall_init(); /* This sets MSR_*STAR and related */
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#endif
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load_TR_desc(); /* This does ltr */
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load_LDT(¤t->active_mm->context); /* This does lldt */
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}
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/**
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* __restore_processor_state - restore the contents of CPU registers saved
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* by __save_processor_state()
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* @ctxt - structure to load the registers contents from
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*/
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static void notrace __restore_processor_state(struct saved_context *ctxt)
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{
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if (ctxt->misc_enable_saved)
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wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
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/*
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* control registers
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*/
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/* cr4 was introduced in the Pentium CPU */
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#ifdef CONFIG_X86_32
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if (ctxt->cr4)
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write_cr4(ctxt->cr4);
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#else
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/* CONFIG X86_64 */
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wrmsrl(MSR_EFER, ctxt->efer);
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write_cr8(ctxt->cr8);
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write_cr4(ctxt->cr4);
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#endif
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write_cr3(ctxt->cr3);
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write_cr2(ctxt->cr2);
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write_cr0(ctxt->cr0);
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/*
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* now restore the descriptor tables to their proper values
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* ltr is done i fix_processor_context().
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*/
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#ifdef CONFIG_X86_32
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load_idt(&ctxt->idt);
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#else
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/* CONFIG_X86_64 */
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load_idt((const struct desc_ptr *)&ctxt->idt_limit);
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#endif
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/*
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* segment registers
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*/
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#ifdef CONFIG_X86_32
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loadsegment(es, ctxt->es);
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loadsegment(fs, ctxt->fs);
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loadsegment(gs, ctxt->gs);
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loadsegment(ss, ctxt->ss);
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/*
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* sysenter MSRs
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*/
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if (boot_cpu_has(X86_FEATURE_SEP))
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enable_sep_cpu();
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#else
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/* CONFIG_X86_64 */
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asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
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asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
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asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
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load_gs_index(ctxt->gs);
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asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
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wrmsrl(MSR_FS_BASE, ctxt->fs_base);
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wrmsrl(MSR_GS_BASE, ctxt->gs_base);
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wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
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#endif
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/*
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* restore XCR0 for xsave capable cpu's.
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*/
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if (cpu_has_xsave)
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xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
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fix_processor_context();
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do_fpu_end();
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x86_platform.restore_sched_clock_state();
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mtrr_bp_restore();
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perf_restore_debug_store();
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}
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/* Needed by apm.c */
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void notrace restore_processor_state(void)
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{
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__restore_processor_state(&saved_context);
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}
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#ifdef CONFIG_X86_32
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EXPORT_SYMBOL(restore_processor_state);
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#endif
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/*
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* When bsp_check() is called in hibernate and suspend, cpu hotplug
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* is disabled already. So it's unnessary to handle race condition between
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* cpumask query and cpu hotplug.
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*/
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static int bsp_check(void)
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{
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if (cpumask_first(cpu_online_mask) != 0) {
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pr_warn("CPU0 is offline.\n");
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return -ENODEV;
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}
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return 0;
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}
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static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
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void *ptr)
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{
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int ret = 0;
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switch (action) {
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case PM_SUSPEND_PREPARE:
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case PM_HIBERNATION_PREPARE:
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ret = bsp_check();
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break;
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#ifdef CONFIG_DEBUG_HOTPLUG_CPU0
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case PM_RESTORE_PREPARE:
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/*
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* When system resumes from hibernation, online CPU0 because
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* 1. it's required for resume and
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* 2. the CPU was online before hibernation
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*/
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if (!cpu_online(0))
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_debug_hotplug_cpu(0, 1);
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break;
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case PM_POST_RESTORE:
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/*
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* When a resume really happens, this code won't be called.
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*
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* This code is called only when user space hibernation software
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* prepares for snapshot device during boot time. So we just
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* call _debug_hotplug_cpu() to restore to CPU0's state prior to
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* preparing the snapshot device.
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*
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* This works for normal boot case in our CPU0 hotplug debug
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* mode, i.e. CPU0 is offline and user mode hibernation
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* software initializes during boot time.
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*
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* If CPU0 is online and user application accesses snapshot
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* device after boot time, this will offline CPU0 and user may
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* see different CPU0 state before and after accessing
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* the snapshot device. But hopefully this is not a case when
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* user debugging CPU0 hotplug. Even if users hit this case,
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* they can easily online CPU0 back.
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*
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* To simplify this debug code, we only consider normal boot
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* case. Otherwise we need to remember CPU0's state and restore
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* to that state and resolve racy conditions etc.
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*/
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_debug_hotplug_cpu(0, 0);
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break;
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#endif
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default:
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break;
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}
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return notifier_from_errno(ret);
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}
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static int __init bsp_pm_check_init(void)
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{
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/*
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* Set this bsp_pm_callback as lower priority than
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* cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
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* earlier to disable cpu hotplug before bsp online check.
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*/
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pm_notifier(bsp_pm_callback, -INT_MAX);
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return 0;
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}
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core_initcall(bsp_pm_check_init);
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