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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
278
arch/xtensa/mm/tlb.c
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278
arch/xtensa/mm/tlb.c
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/*
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* arch/xtensa/mm/tlb.c
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*
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* Logic that manipulates the Xtensa MMU. Derived from MIPS.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2003 Tensilica Inc.
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*
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* Joe Taylor
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* Chris Zankel <chris@zankel.net>
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* Marc Gauthier
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*/
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#include <linux/mm.h>
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#include <asm/processor.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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static inline void __flush_itlb_all (void)
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{
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int w, i;
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for (w = 0; w < ITLB_ARF_WAYS; w++) {
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for (i = 0; i < (1 << XCHAL_ITLB_ARF_ENTRIES_LOG2); i++) {
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int e = w + (i << PAGE_SHIFT);
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invalidate_itlb_entry_no_isync(e);
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}
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}
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asm volatile ("isync\n");
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}
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static inline void __flush_dtlb_all (void)
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{
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int w, i;
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for (w = 0; w < DTLB_ARF_WAYS; w++) {
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for (i = 0; i < (1 << XCHAL_DTLB_ARF_ENTRIES_LOG2); i++) {
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int e = w + (i << PAGE_SHIFT);
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invalidate_dtlb_entry_no_isync(e);
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}
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}
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asm volatile ("isync\n");
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}
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void local_flush_tlb_all(void)
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{
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__flush_itlb_all();
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__flush_dtlb_all();
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}
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/* If mm is current, we simply assign the current task a new ASID, thus,
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* invalidating all previous tlb entries. If mm is someone else's user mapping,
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* wie invalidate the context, thus, when that user mapping is swapped in,
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* a new context will be assigned to it.
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*/
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void local_flush_tlb_mm(struct mm_struct *mm)
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{
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int cpu = smp_processor_id();
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if (mm == current->active_mm) {
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unsigned long flags;
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local_irq_save(flags);
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mm->context.asid[cpu] = NO_CONTEXT;
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activate_context(mm, cpu);
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local_irq_restore(flags);
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} else {
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mm->context.asid[cpu] = NO_CONTEXT;
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mm->context.cpu = -1;
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}
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}
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#define _ITLB_ENTRIES (ITLB_ARF_WAYS << XCHAL_ITLB_ARF_ENTRIES_LOG2)
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#define _DTLB_ENTRIES (DTLB_ARF_WAYS << XCHAL_DTLB_ARF_ENTRIES_LOG2)
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#if _ITLB_ENTRIES > _DTLB_ENTRIES
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# define _TLB_ENTRIES _ITLB_ENTRIES
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#else
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# define _TLB_ENTRIES _DTLB_ENTRIES
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#endif
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void local_flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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int cpu = smp_processor_id();
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struct mm_struct *mm = vma->vm_mm;
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unsigned long flags;
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if (mm->context.asid[cpu] == NO_CONTEXT)
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return;
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#if 0
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printk("[tlbrange<%02lx,%08lx,%08lx>]\n",
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(unsigned long)mm->context.asid[cpu], start, end);
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#endif
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local_irq_save(flags);
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if (end-start + (PAGE_SIZE-1) <= _TLB_ENTRIES << PAGE_SHIFT) {
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int oldpid = get_rasid_register();
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set_rasid_register(ASID_INSERT(mm->context.asid[cpu]));
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start &= PAGE_MASK;
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if (vma->vm_flags & VM_EXEC)
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while(start < end) {
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invalidate_itlb_mapping(start);
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invalidate_dtlb_mapping(start);
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start += PAGE_SIZE;
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}
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else
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while(start < end) {
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invalidate_dtlb_mapping(start);
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start += PAGE_SIZE;
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}
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set_rasid_register(oldpid);
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} else {
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local_flush_tlb_mm(mm);
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}
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local_irq_restore(flags);
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}
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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int cpu = smp_processor_id();
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struct mm_struct* mm = vma->vm_mm;
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unsigned long flags;
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int oldpid;
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if (mm->context.asid[cpu] == NO_CONTEXT)
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return;
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local_irq_save(flags);
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oldpid = get_rasid_register();
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set_rasid_register(ASID_INSERT(mm->context.asid[cpu]));
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if (vma->vm_flags & VM_EXEC)
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invalidate_itlb_mapping(page);
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invalidate_dtlb_mapping(page);
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set_rasid_register(oldpid);
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local_irq_restore(flags);
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}
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void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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if (end > start && start >= TASK_SIZE && end <= PAGE_OFFSET &&
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end - start < _TLB_ENTRIES << PAGE_SHIFT) {
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start &= PAGE_MASK;
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while (start < end) {
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invalidate_itlb_mapping(start);
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invalidate_dtlb_mapping(start);
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start += PAGE_SIZE;
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}
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} else {
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local_flush_tlb_all();
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}
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}
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#ifdef CONFIG_DEBUG_TLB_SANITY
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static unsigned get_pte_for_vaddr(unsigned vaddr)
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{
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struct task_struct *task = get_current();
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struct mm_struct *mm = task->mm;
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pgd_t *pgd;
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pmd_t *pmd;
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pte_t *pte;
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if (!mm)
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mm = task->active_mm;
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pgd = pgd_offset(mm, vaddr);
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if (pgd_none_or_clear_bad(pgd))
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return 0;
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pmd = pmd_offset(pgd, vaddr);
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if (pmd_none_or_clear_bad(pmd))
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return 0;
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pte = pte_offset_map(pmd, vaddr);
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if (!pte)
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return 0;
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return pte_val(*pte);
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}
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enum {
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TLB_SUSPICIOUS = 1,
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TLB_INSANE = 2,
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};
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static void tlb_insane(void)
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{
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BUG_ON(1);
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}
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static void tlb_suspicious(void)
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{
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WARN_ON(1);
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}
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/*
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* Check that TLB entries with kernel ASID (1) have kernel VMA (>= TASK_SIZE),
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* and TLB entries with user ASID (>=4) have VMA < TASK_SIZE.
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*
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* Check that valid TLB entries either have the same PA as the PTE, or PTE is
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* marked as non-present. Non-present PTE and the page with non-zero refcount
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* and zero mapcount is normal for batched TLB flush operation. Zero refcount
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* means that the page was freed prematurely. Non-zero mapcount is unusual,
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* but does not necessary means an error, thus marked as suspicious.
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*/
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static int check_tlb_entry(unsigned w, unsigned e, bool dtlb)
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{
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unsigned tlbidx = w | (e << PAGE_SHIFT);
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unsigned r0 = dtlb ?
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read_dtlb_virtual(tlbidx) : read_itlb_virtual(tlbidx);
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unsigned vpn = (r0 & PAGE_MASK) | (e << PAGE_SHIFT);
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unsigned pte = get_pte_for_vaddr(vpn);
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unsigned mm_asid = (get_rasid_register() >> 8) & ASID_MASK;
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unsigned tlb_asid = r0 & ASID_MASK;
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bool kernel = tlb_asid == 1;
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int rc = 0;
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if (tlb_asid > 0 && ((vpn < TASK_SIZE) == kernel)) {
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pr_err("%cTLB: way: %u, entry: %u, VPN %08x in %s PTE\n",
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dtlb ? 'D' : 'I', w, e, vpn,
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kernel ? "kernel" : "user");
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rc |= TLB_INSANE;
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}
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if (tlb_asid == mm_asid) {
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unsigned r1 = dtlb ? read_dtlb_translation(tlbidx) :
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read_itlb_translation(tlbidx);
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if ((pte ^ r1) & PAGE_MASK) {
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pr_err("%cTLB: way: %u, entry: %u, mapping: %08x->%08x, PTE: %08x\n",
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dtlb ? 'D' : 'I', w, e, r0, r1, pte);
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if (pte == 0 || !pte_present(__pte(pte))) {
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struct page *p = pfn_to_page(r1 >> PAGE_SHIFT);
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pr_err("page refcount: %d, mapcount: %d\n",
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page_count(p),
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page_mapcount(p));
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if (!page_count(p))
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rc |= TLB_INSANE;
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else if (page_mapped(p))
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rc |= TLB_SUSPICIOUS;
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} else {
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rc |= TLB_INSANE;
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}
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}
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}
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return rc;
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}
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void check_tlb_sanity(void)
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{
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unsigned long flags;
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unsigned w, e;
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int bug = 0;
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local_irq_save(flags);
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for (w = 0; w < DTLB_ARF_WAYS; ++w)
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for (e = 0; e < (1 << XCHAL_DTLB_ARF_ENTRIES_LOG2); ++e)
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bug |= check_tlb_entry(w, e, true);
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for (w = 0; w < ITLB_ARF_WAYS; ++w)
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for (e = 0; e < (1 << XCHAL_ITLB_ARF_ENTRIES_LOG2); ++e)
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bug |= check_tlb_entry(w, e, false);
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if (bug & TLB_INSANE)
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tlb_insane();
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if (bug & TLB_SUSPICIOUS)
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tlb_suspicious();
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local_irq_restore(flags);
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}
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#endif /* CONFIG_DEBUG_TLB_SANITY */
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