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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 01:28:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
245
drivers/ata/sata_uli.c
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245
drivers/ata/sata_uli.c
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/*
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* sata_uli.c - ULi Electronics SATA
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* Hardware documentation available under NDA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/gfp.h>
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#include <linux/pci.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "sata_uli"
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#define DRV_VERSION "1.3"
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enum {
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uli_5289 = 0,
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uli_5287 = 1,
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uli_5281 = 2,
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uli_max_ports = 4,
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/* PCI configuration registers */
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ULI5287_BASE = 0x90, /* sata0 phy SCR registers */
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ULI5287_OFFS = 0x10, /* offset from sata0->sata1 phy regs */
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ULI5281_BASE = 0x60, /* sata0 phy SCR registers */
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ULI5281_OFFS = 0x60, /* offset from sata0->sata1 phy regs */
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};
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struct uli_priv {
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unsigned int scr_cfg_addr[uli_max_ports];
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};
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static int uli_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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static int uli_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
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static int uli_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
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static const struct pci_device_id uli_pci_tbl[] = {
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{ PCI_VDEVICE(AL, 0x5289), uli_5289 },
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{ PCI_VDEVICE(AL, 0x5287), uli_5287 },
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{ PCI_VDEVICE(AL, 0x5281), uli_5281 },
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{ } /* terminate list */
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};
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static struct pci_driver uli_pci_driver = {
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.name = DRV_NAME,
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.id_table = uli_pci_tbl,
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.probe = uli_init_one,
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.remove = ata_pci_remove_one,
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};
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static struct scsi_host_template uli_sht = {
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ATA_BMDMA_SHT(DRV_NAME),
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};
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static struct ata_port_operations uli_ops = {
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.inherits = &ata_bmdma_port_ops,
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.scr_read = uli_scr_read,
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.scr_write = uli_scr_write,
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.hardreset = ATA_OP_NULL,
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};
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static const struct ata_port_info uli_port_info = {
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.flags = ATA_FLAG_SATA | ATA_FLAG_IGN_SIMPLEX,
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.pio_mask = ATA_PIO4,
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.udma_mask = ATA_UDMA6,
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.port_ops = &uli_ops,
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};
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MODULE_AUTHOR("Peer Chen");
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MODULE_DESCRIPTION("low-level driver for ULi Electronics SATA controller");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, uli_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
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{
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struct uli_priv *hpriv = ap->host->private_data;
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return hpriv->scr_cfg_addr[ap->port_no] + (4 * sc_reg);
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}
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static u32 uli_scr_cfg_read(struct ata_link *link, unsigned int sc_reg)
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{
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struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
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unsigned int cfg_addr = get_scr_cfg_addr(link->ap, sc_reg);
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u32 val;
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pci_read_config_dword(pdev, cfg_addr, &val);
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return val;
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}
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static void uli_scr_cfg_write(struct ata_link *link, unsigned int scr, u32 val)
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{
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struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
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unsigned int cfg_addr = get_scr_cfg_addr(link->ap, scr);
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pci_write_config_dword(pdev, cfg_addr, val);
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}
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static int uli_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
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{
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if (sc_reg > SCR_CONTROL)
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return -EINVAL;
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*val = uli_scr_cfg_read(link, sc_reg);
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return 0;
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}
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static int uli_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
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{
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if (sc_reg > SCR_CONTROL) //SCR_CONTROL=2, SCR_ERROR=1, SCR_STATUS=0
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return -EINVAL;
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uli_scr_cfg_write(link, sc_reg, val);
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return 0;
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}
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static int uli_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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const struct ata_port_info *ppi[] = { &uli_port_info, NULL };
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unsigned int board_idx = (unsigned int) ent->driver_data;
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struct ata_host *host;
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struct uli_priv *hpriv;
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void __iomem * const *iomap;
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struct ata_ioports *ioaddr;
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int n_ports, rc;
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ata_print_version_once(&pdev->dev, DRV_VERSION);
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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n_ports = 2;
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if (board_idx == uli_5287)
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n_ports = 4;
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/* allocate the host */
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host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
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if (!host)
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return -ENOMEM;
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hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
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if (!hpriv)
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return -ENOMEM;
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host->private_data = hpriv;
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/* the first two ports are standard SFF */
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rc = ata_pci_sff_init_host(host);
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if (rc)
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return rc;
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ata_pci_bmdma_init(host);
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iomap = host->iomap;
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switch (board_idx) {
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case uli_5287:
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/* If there are four, the last two live right after
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* the standard SFF ports.
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*/
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hpriv->scr_cfg_addr[0] = ULI5287_BASE;
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hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS;
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ioaddr = &host->ports[2]->ioaddr;
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ioaddr->cmd_addr = iomap[0] + 8;
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ioaddr->altstatus_addr =
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ioaddr->ctl_addr = (void __iomem *)
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((unsigned long)iomap[1] | ATA_PCI_CTL_OFS) + 4;
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ioaddr->bmdma_addr = iomap[4] + 16;
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hpriv->scr_cfg_addr[2] = ULI5287_BASE + ULI5287_OFFS*4;
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ata_sff_std_ports(ioaddr);
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ata_port_desc(host->ports[2],
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"cmd 0x%llx ctl 0x%llx bmdma 0x%llx",
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(unsigned long long)pci_resource_start(pdev, 0) + 8,
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((unsigned long long)pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS) + 4,
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(unsigned long long)pci_resource_start(pdev, 4) + 16);
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ioaddr = &host->ports[3]->ioaddr;
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ioaddr->cmd_addr = iomap[2] + 8;
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ioaddr->altstatus_addr =
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ioaddr->ctl_addr = (void __iomem *)
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((unsigned long)iomap[3] | ATA_PCI_CTL_OFS) + 4;
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ioaddr->bmdma_addr = iomap[4] + 24;
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hpriv->scr_cfg_addr[3] = ULI5287_BASE + ULI5287_OFFS*5;
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ata_sff_std_ports(ioaddr);
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ata_port_desc(host->ports[2],
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"cmd 0x%llx ctl 0x%llx bmdma 0x%llx",
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(unsigned long long)pci_resource_start(pdev, 2) + 9,
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((unsigned long long)pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS) + 4,
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(unsigned long long)pci_resource_start(pdev, 4) + 24);
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break;
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case uli_5289:
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hpriv->scr_cfg_addr[0] = ULI5287_BASE;
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hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS;
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break;
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case uli_5281:
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hpriv->scr_cfg_addr[0] = ULI5281_BASE;
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hpriv->scr_cfg_addr[1] = ULI5281_BASE + ULI5281_OFFS;
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break;
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default:
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BUG();
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break;
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}
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pci_set_master(pdev);
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pci_intx(pdev, 1);
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return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
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IRQF_SHARED, &uli_sht);
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}
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module_pci_driver(uli_pci_driver);
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