mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 01:28:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
248
drivers/atm/nicstarmac.c
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248
drivers/atm/nicstarmac.c
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/*
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* this file included by nicstar.c
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*/
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/*
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* nicstarmac.c
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* Read this ForeRunner's MAC address from eprom/eeprom
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*/
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#include <linux/kernel.h>
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typedef void __iomem *virt_addr_t;
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#define CYCLE_DELAY 5
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/*
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This was the original definition
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#define osp_MicroDelay(microsec) \
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do { int _i = 4*microsec; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0)
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*/
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#define osp_MicroDelay(microsec) {unsigned long useconds = (microsec); \
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udelay((useconds));}
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/*
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* The following tables represent the timing diagrams found in
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* the Data Sheet for the Xicor X25020 EEProm. The #defines below
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* represent the bits in the NICStAR's General Purpose register
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* that must be toggled for the corresponding actions on the EEProm
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* to occur.
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*/
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/* Write Data To EEProm from SI line on rising edge of CLK */
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/* Read Data From EEProm on falling edge of CLK */
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#define CS_HIGH 0x0002 /* Chip select high */
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#define CS_LOW 0x0000 /* Chip select low (active low) */
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#define CLK_HIGH 0x0004 /* Clock high */
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#define CLK_LOW 0x0000 /* Clock low */
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#define SI_HIGH 0x0001 /* Serial input data high */
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#define SI_LOW 0x0000 /* Serial input data low */
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/* Read Status Register = 0000 0101b */
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#if 0
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static u_int32_t rdsrtab[] = {
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CS_HIGH | CLK_HIGH,
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CS_LOW | CLK_LOW,
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CLK_HIGH, /* 0 */
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CLK_LOW,
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CLK_HIGH, /* 0 */
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CLK_LOW,
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CLK_HIGH, /* 0 */
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CLK_LOW,
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CLK_HIGH, /* 0 */
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CLK_LOW,
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CLK_HIGH, /* 0 */
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CLK_LOW | SI_HIGH,
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CLK_HIGH | SI_HIGH, /* 1 */
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CLK_LOW | SI_LOW,
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CLK_HIGH, /* 0 */
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CLK_LOW | SI_HIGH,
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CLK_HIGH | SI_HIGH /* 1 */
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};
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#endif /* 0 */
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/* Read from EEPROM = 0000 0011b */
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static u_int32_t readtab[] = {
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/*
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CS_HIGH | CLK_HIGH,
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*/
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CS_LOW | CLK_LOW,
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CLK_HIGH, /* 0 */
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CLK_LOW,
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CLK_HIGH, /* 0 */
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CLK_LOW,
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CLK_HIGH, /* 0 */
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CLK_LOW,
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CLK_HIGH, /* 0 */
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CLK_LOW,
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CLK_HIGH, /* 0 */
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CLK_LOW,
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CLK_HIGH, /* 0 */
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CLK_LOW | SI_HIGH,
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CLK_HIGH | SI_HIGH, /* 1 */
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CLK_LOW | SI_HIGH,
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CLK_HIGH | SI_HIGH /* 1 */
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};
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/* Clock to read from/write to the eeprom */
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static u_int32_t clocktab[] = {
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CLK_LOW,
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CLK_HIGH,
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CLK_LOW,
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CLK_HIGH,
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CLK_LOW,
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CLK_HIGH,
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CLK_LOW,
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CLK_HIGH,
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CLK_LOW,
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CLK_HIGH,
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CLK_LOW,
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CLK_HIGH,
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CLK_LOW,
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CLK_HIGH,
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CLK_LOW,
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CLK_HIGH,
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CLK_LOW
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};
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#define NICSTAR_REG_WRITE(bs, reg, val) \
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while ( readl(bs + STAT) & 0x0200 ) ; \
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writel((val),(base)+(reg))
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#define NICSTAR_REG_READ(bs, reg) \
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readl((base)+(reg))
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#define NICSTAR_REG_GENERAL_PURPOSE GP
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/*
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* This routine will clock the Read_Status_reg function into the X2520
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* eeprom, then pull the result from bit 16 of the NicSTaR's General Purpose
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* register.
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*/
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#if 0
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u_int32_t nicstar_read_eprom_status(virt_addr_t base)
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{
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u_int32_t val;
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u_int32_t rbyte;
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int32_t i, j;
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/* Send read instruction */
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val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
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for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {
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NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
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(val | rdsrtab[i]));
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osp_MicroDelay(CYCLE_DELAY);
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}
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/* Done sending instruction - now pull data off of bit 16, MSB first */
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/* Data clocked out of eeprom on falling edge of clock */
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rbyte = 0;
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for (i = 7, j = 0; i >= 0; i--) {
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NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
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(val | clocktab[j++]));
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rbyte |= (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE)
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& 0x00010000) >> 16) << i);
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NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
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(val | clocktab[j++]));
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osp_MicroDelay(CYCLE_DELAY);
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}
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NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2);
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osp_MicroDelay(CYCLE_DELAY);
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return rbyte;
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}
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#endif /* 0 */
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/*
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* This routine will clock the Read_data function into the X2520
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* eeprom, followed by the address to read from, through the NicSTaR's General
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* Purpose register.
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*/
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static u_int8_t read_eprom_byte(virt_addr_t base, u_int8_t offset)
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{
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u_int32_t val = 0;
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int i, j = 0;
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u_int8_t tempread = 0;
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val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
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/* Send READ instruction */
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for (i = 0; i < ARRAY_SIZE(readtab); i++) {
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NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
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(val | readtab[i]));
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osp_MicroDelay(CYCLE_DELAY);
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}
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/* Next, we need to send the byte address to read from */
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for (i = 7; i >= 0; i--) {
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NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
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(val | clocktab[j++] | ((offset >> i) & 1)));
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osp_MicroDelay(CYCLE_DELAY);
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NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
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(val | clocktab[j++] | ((offset >> i) & 1)));
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osp_MicroDelay(CYCLE_DELAY);
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}
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j = 0;
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/* Now, we can read data from the eeprom by clocking it in */
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for (i = 7; i >= 0; i--) {
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NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
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(val | clocktab[j++]));
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osp_MicroDelay(CYCLE_DELAY);
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tempread |=
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(((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE)
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& 0x00010000) >> 16) << i);
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NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
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(val | clocktab[j++]));
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osp_MicroDelay(CYCLE_DELAY);
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}
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NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2);
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osp_MicroDelay(CYCLE_DELAY);
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return tempread;
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}
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static void nicstar_init_eprom(virt_addr_t base)
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{
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u_int32_t val;
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/*
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* turn chip select off
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*/
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val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
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NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
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(val | CS_HIGH | CLK_HIGH));
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osp_MicroDelay(CYCLE_DELAY);
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NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
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(val | CS_HIGH | CLK_LOW));
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osp_MicroDelay(CYCLE_DELAY);
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NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
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(val | CS_HIGH | CLK_HIGH));
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osp_MicroDelay(CYCLE_DELAY);
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NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
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(val | CS_HIGH | CLK_LOW));
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osp_MicroDelay(CYCLE_DELAY);
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}
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/*
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* This routine will be the interface to the ReadPromByte function
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* above.
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*/
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static void
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nicstar_read_eprom(virt_addr_t base,
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u_int8_t prom_offset, u_int8_t * buffer, u_int32_t nbytes)
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{
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u_int i;
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for (i = 0; i < nbytes; i++) {
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buffer[i] = read_eprom_byte(base, prom_offset);
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++prom_offset;
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osp_MicroDelay(CYCLE_DELAY);
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}
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}
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