mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
310
drivers/bcma/host_pci.c
Normal file
310
drivers/bcma/host_pci.c
Normal file
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@ -0,0 +1,310 @@
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/*
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* Broadcom specific AMBA
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* PCI Host
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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#include <linux/slab.h>
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#include <linux/bcma/bcma.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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static void bcma_host_pci_switch_core(struct bcma_device *core)
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{
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pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN,
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core->addr);
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pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
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core->wrap);
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core->bus->mapped_core = core;
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bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id);
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}
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/* Provides access to the requested core. Returns base offset that has to be
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* used. It makes use of fixed windows when possible. */
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static u16 bcma_host_pci_provide_access_to_core(struct bcma_device *core)
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{
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switch (core->id.id) {
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case BCMA_CORE_CHIPCOMMON:
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return 3 * BCMA_CORE_SIZE;
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case BCMA_CORE_PCIE:
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return 2 * BCMA_CORE_SIZE;
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}
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if (core->bus->mapped_core != core)
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bcma_host_pci_switch_core(core);
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return 0;
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}
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static u8 bcma_host_pci_read8(struct bcma_device *core, u16 offset)
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{
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offset += bcma_host_pci_provide_access_to_core(core);
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return ioread8(core->bus->mmio + offset);
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}
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static u16 bcma_host_pci_read16(struct bcma_device *core, u16 offset)
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{
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offset += bcma_host_pci_provide_access_to_core(core);
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return ioread16(core->bus->mmio + offset);
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}
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static u32 bcma_host_pci_read32(struct bcma_device *core, u16 offset)
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{
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offset += bcma_host_pci_provide_access_to_core(core);
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return ioread32(core->bus->mmio + offset);
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}
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static void bcma_host_pci_write8(struct bcma_device *core, u16 offset,
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u8 value)
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{
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offset += bcma_host_pci_provide_access_to_core(core);
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iowrite8(value, core->bus->mmio + offset);
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}
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static void bcma_host_pci_write16(struct bcma_device *core, u16 offset,
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u16 value)
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{
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offset += bcma_host_pci_provide_access_to_core(core);
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iowrite16(value, core->bus->mmio + offset);
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}
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static void bcma_host_pci_write32(struct bcma_device *core, u16 offset,
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u32 value)
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{
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offset += bcma_host_pci_provide_access_to_core(core);
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iowrite32(value, core->bus->mmio + offset);
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}
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#ifdef CONFIG_BCMA_BLOCKIO
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static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
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size_t count, u16 offset, u8 reg_width)
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{
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void __iomem *addr = core->bus->mmio + offset;
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if (core->bus->mapped_core != core)
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bcma_host_pci_switch_core(core);
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switch (reg_width) {
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case sizeof(u8):
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ioread8_rep(addr, buffer, count);
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break;
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case sizeof(u16):
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WARN_ON(count & 1);
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ioread16_rep(addr, buffer, count >> 1);
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break;
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case sizeof(u32):
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WARN_ON(count & 3);
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ioread32_rep(addr, buffer, count >> 2);
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break;
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default:
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WARN_ON(1);
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}
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}
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static void bcma_host_pci_block_write(struct bcma_device *core,
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const void *buffer, size_t count,
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u16 offset, u8 reg_width)
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{
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void __iomem *addr = core->bus->mmio + offset;
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if (core->bus->mapped_core != core)
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bcma_host_pci_switch_core(core);
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switch (reg_width) {
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case sizeof(u8):
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iowrite8_rep(addr, buffer, count);
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break;
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case sizeof(u16):
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WARN_ON(count & 1);
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iowrite16_rep(addr, buffer, count >> 1);
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break;
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case sizeof(u32):
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WARN_ON(count & 3);
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iowrite32_rep(addr, buffer, count >> 2);
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break;
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default:
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WARN_ON(1);
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}
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}
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#endif
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static u32 bcma_host_pci_aread32(struct bcma_device *core, u16 offset)
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{
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if (core->bus->mapped_core != core)
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bcma_host_pci_switch_core(core);
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return ioread32(core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
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}
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static void bcma_host_pci_awrite32(struct bcma_device *core, u16 offset,
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u32 value)
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{
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if (core->bus->mapped_core != core)
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bcma_host_pci_switch_core(core);
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iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
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}
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static const struct bcma_host_ops bcma_host_pci_ops = {
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.read8 = bcma_host_pci_read8,
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.read16 = bcma_host_pci_read16,
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.read32 = bcma_host_pci_read32,
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.write8 = bcma_host_pci_write8,
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.write16 = bcma_host_pci_write16,
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.write32 = bcma_host_pci_write32,
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#ifdef CONFIG_BCMA_BLOCKIO
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.block_read = bcma_host_pci_block_read,
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.block_write = bcma_host_pci_block_write,
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#endif
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.aread32 = bcma_host_pci_aread32,
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.awrite32 = bcma_host_pci_awrite32,
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};
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static int bcma_host_pci_probe(struct pci_dev *dev,
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const struct pci_device_id *id)
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{
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struct bcma_bus *bus;
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int err = -ENOMEM;
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const char *name;
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u32 val;
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/* Alloc */
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bus = kzalloc(sizeof(*bus), GFP_KERNEL);
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if (!bus)
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goto out;
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/* Basic PCI configuration */
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err = pci_enable_device(dev);
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if (err)
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goto err_kfree_bus;
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name = dev_name(&dev->dev);
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if (dev->driver && dev->driver->name)
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name = dev->driver->name;
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err = pci_request_regions(dev, name);
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if (err)
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goto err_pci_disable;
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pci_set_master(dev);
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/* Disable the RETRY_TIMEOUT register (0x41) to keep
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* PCI Tx retries from interfering with C3 CPU state */
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pci_read_config_dword(dev, 0x40, &val);
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if ((val & 0x0000ff00) != 0)
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pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
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/* SSB needed additional powering up, do we have any AMBA PCI cards? */
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if (!pci_is_pcie(dev)) {
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bcma_err(bus, "PCI card detected, they are not supported.\n");
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err = -ENXIO;
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goto err_pci_release_regions;
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}
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/* Map MMIO */
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err = -ENOMEM;
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bus->mmio = pci_iomap(dev, 0, ~0UL);
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if (!bus->mmio)
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goto err_pci_release_regions;
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/* Host specific */
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bus->host_pci = dev;
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bus->hosttype = BCMA_HOSTTYPE_PCI;
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bus->ops = &bcma_host_pci_ops;
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bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
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bus->boardinfo.type = bus->host_pci->subsystem_device;
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/* Initialize struct, detect chip */
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bcma_init_bus(bus);
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/* Register */
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err = bcma_bus_register(bus);
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if (err)
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goto err_pci_unmap_mmio;
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pci_set_drvdata(dev, bus);
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out:
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return err;
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err_pci_unmap_mmio:
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pci_iounmap(dev, bus->mmio);
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err_pci_release_regions:
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pci_release_regions(dev);
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err_pci_disable:
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pci_disable_device(dev);
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err_kfree_bus:
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kfree(bus);
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return err;
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}
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static void bcma_host_pci_remove(struct pci_dev *dev)
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{
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struct bcma_bus *bus = pci_get_drvdata(dev);
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bcma_bus_unregister(bus);
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pci_iounmap(dev, bus->mmio);
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pci_release_regions(dev);
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pci_disable_device(dev);
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kfree(bus);
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}
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#ifdef CONFIG_PM_SLEEP
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static int bcma_host_pci_suspend(struct device *dev)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct bcma_bus *bus = pci_get_drvdata(pdev);
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bus->mapped_core = NULL;
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return bcma_bus_suspend(bus);
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}
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static int bcma_host_pci_resume(struct device *dev)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct bcma_bus *bus = pci_get_drvdata(pdev);
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return bcma_bus_resume(bus);
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}
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static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bcma_host_pci_suspend,
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bcma_host_pci_resume);
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#define BCMA_PM_OPS (&bcma_pm_ops)
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#else /* CONFIG_PM_SLEEP */
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#define BCMA_PM_OPS NULL
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#endif /* CONFIG_PM_SLEEP */
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static const struct pci_device_id bcma_pci_bridge_tbl[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) }, /* 0xa8d8 */
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xa8db, BCM43217 (sic!) */
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43228) }, /* 0xa8dc */
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
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static struct pci_driver bcma_pci_bridge_driver = {
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.name = "bcma-pci-bridge",
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.id_table = bcma_pci_bridge_tbl,
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.probe = bcma_host_pci_probe,
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.remove = bcma_host_pci_remove,
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.driver.pm = BCMA_PM_OPS,
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};
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int __init bcma_host_pci_init(void)
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{
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return pci_register_driver(&bcma_pci_bridge_driver);
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}
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void __exit bcma_host_pci_exit(void)
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{
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pci_unregister_driver(&bcma_pci_bridge_driver);
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}
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