mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 01:12:45 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
434
drivers/block/rsxx/rsxx_priv.h
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434
drivers/block/rsxx/rsxx_priv.h
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/*
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* Filename: rsxx_priv.h
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*
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*
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* Authors: Joshua Morris <josh.h.morris@us.ibm.com>
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* Philip Kelleher <pjk1939@linux.vnet.ibm.com>
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*
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* (C) Copyright 2013 IBM Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __RSXX_PRIV_H__
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#define __RSXX_PRIV_H__
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#include <linux/version.h>
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#include <linux/semaphore.h>
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#include <linux/fs.h>
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#include <linux/interrupt.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/sysfs.h>
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#include <linux/workqueue.h>
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#include <linux/bio.h>
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#include <linux/vmalloc.h>
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#include <linux/timer.h>
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#include <linux/ioctl.h>
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#include <linux/delay.h>
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#include "rsxx.h"
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#include "rsxx_cfg.h"
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struct proc_cmd;
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#define PCI_DEVICE_ID_FS70_FLASH 0x04A9
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#define PCI_DEVICE_ID_FS80_FLASH 0x04AA
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#define RS70_PCI_REV_SUPPORTED 4
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#define DRIVER_NAME "rsxx"
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#define DRIVER_VERSION "4.0.3.2516"
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/* Block size is 4096 */
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#define RSXX_HW_BLK_SHIFT 12
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#define RSXX_HW_BLK_SIZE (1 << RSXX_HW_BLK_SHIFT)
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#define RSXX_HW_BLK_MASK (RSXX_HW_BLK_SIZE - 1)
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#define MAX_CREG_DATA8 32
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#define LOG_BUF_SIZE8 128
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#define RSXX_MAX_OUTSTANDING_CMDS 255
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#define RSXX_CS_IDX_MASK 0xff
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#define STATUS_BUFFER_SIZE8 4096
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#define COMMAND_BUFFER_SIZE8 4096
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#define RSXX_MAX_TARGETS 8
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struct dma_tracker_list;
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/* DMA Command/Status Buffer structure */
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struct rsxx_cs_buffer {
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dma_addr_t dma_addr;
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void *buf;
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u32 idx;
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};
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struct rsxx_dma_stats {
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u32 crc_errors;
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u32 hard_errors;
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u32 soft_errors;
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u32 writes_issued;
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u32 writes_failed;
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u32 reads_issued;
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u32 reads_failed;
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u32 reads_retried;
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u32 discards_issued;
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u32 discards_failed;
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u32 done_rescheduled;
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u32 issue_rescheduled;
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u32 dma_sw_err;
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u32 dma_hw_fault;
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u32 dma_cancelled;
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u32 sw_q_depth; /* Number of DMAs on the SW queue. */
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atomic_t hw_q_depth; /* Number of DMAs queued to HW. */
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};
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struct rsxx_dma_ctrl {
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struct rsxx_cardinfo *card;
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int id;
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void __iomem *regmap;
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struct rsxx_cs_buffer status;
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struct rsxx_cs_buffer cmd;
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u16 e_cnt;
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spinlock_t queue_lock;
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struct list_head queue;
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struct workqueue_struct *issue_wq;
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struct work_struct issue_dma_work;
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struct workqueue_struct *done_wq;
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struct work_struct dma_done_work;
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struct timer_list activity_timer;
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struct dma_tracker_list *trackers;
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struct rsxx_dma_stats stats;
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struct mutex work_lock;
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};
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struct rsxx_cardinfo {
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struct pci_dev *dev;
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unsigned int halt;
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unsigned int eeh_state;
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void __iomem *regmap;
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spinlock_t irq_lock;
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unsigned int isr_mask;
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unsigned int ier_mask;
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struct rsxx_card_cfg config;
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int config_valid;
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/* Embedded CPU Communication */
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struct {
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spinlock_t lock;
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bool active;
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struct creg_cmd *active_cmd;
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struct workqueue_struct *creg_wq;
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struct work_struct done_work;
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struct list_head queue;
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unsigned int q_depth;
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/* Cache the creg status to prevent ioreads */
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struct {
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u32 stat;
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u32 failed_cancel_timer;
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u32 creg_timeout;
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} creg_stats;
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struct timer_list cmd_timer;
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struct mutex reset_lock;
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int reset;
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} creg_ctrl;
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struct {
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char tmp[MAX_CREG_DATA8];
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char buf[LOG_BUF_SIZE8]; /* terminated */
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int buf_len;
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} log;
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struct workqueue_struct *event_wq;
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struct work_struct event_work;
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unsigned int state;
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u64 size8;
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/* Lock the device attach/detach function */
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struct mutex dev_lock;
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/* Block Device Variables */
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bool bdev_attached;
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int disk_id;
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int major;
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struct request_queue *queue;
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struct gendisk *gendisk;
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struct {
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/* Used to convert a byte address to a device address. */
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u64 lower_mask;
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u64 upper_shift;
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u64 upper_mask;
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u64 target_mask;
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u64 target_shift;
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} _stripe;
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unsigned int dma_fault;
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int scrub_hard;
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int n_targets;
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struct rsxx_dma_ctrl *ctrl;
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struct dentry *debugfs_dir;
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};
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enum rsxx_pci_regmap {
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HWID = 0x00, /* Hardware Identification Register */
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SCRATCH = 0x04, /* Scratch/Debug Register */
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RESET = 0x08, /* Reset Register */
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ISR = 0x10, /* Interrupt Status Register */
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IER = 0x14, /* Interrupt Enable Register */
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IPR = 0x18, /* Interrupt Poll Register */
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CB_ADD_LO = 0x20, /* Command Host Buffer Address [31:0] */
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CB_ADD_HI = 0x24, /* Command Host Buffer Address [63:32]*/
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HW_CMD_IDX = 0x28, /* Hardware Processed Command Index */
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SW_CMD_IDX = 0x2C, /* Software Processed Command Index */
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SB_ADD_LO = 0x30, /* Status Host Buffer Address [31:0] */
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SB_ADD_HI = 0x34, /* Status Host Buffer Address [63:32] */
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HW_STATUS_CNT = 0x38, /* Hardware Status Counter */
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SW_STATUS_CNT = 0x3C, /* Deprecated */
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CREG_CMD = 0x40, /* CPU Command Register */
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CREG_ADD = 0x44, /* CPU Address Register */
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CREG_CNT = 0x48, /* CPU Count Register */
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CREG_STAT = 0x4C, /* CPU Status Register */
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CREG_DATA0 = 0x50, /* CPU Data Registers */
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CREG_DATA1 = 0x54,
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CREG_DATA2 = 0x58,
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CREG_DATA3 = 0x5C,
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CREG_DATA4 = 0x60,
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CREG_DATA5 = 0x64,
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CREG_DATA6 = 0x68,
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CREG_DATA7 = 0x6c,
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INTR_COAL = 0x70, /* Interrupt Coalescing Register */
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HW_ERROR = 0x74, /* Card Error Register */
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PCI_DEBUG0 = 0x78, /* PCI Debug Registers */
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PCI_DEBUG1 = 0x7C,
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PCI_DEBUG2 = 0x80,
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PCI_DEBUG3 = 0x84,
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PCI_DEBUG4 = 0x88,
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PCI_DEBUG5 = 0x8C,
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PCI_DEBUG6 = 0x90,
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PCI_DEBUG7 = 0x94,
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PCI_POWER_THROTTLE = 0x98,
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PERF_CTRL = 0x9c,
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PERF_TIMER_LO = 0xa0,
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PERF_TIMER_HI = 0xa4,
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PERF_RD512_LO = 0xa8,
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PERF_RD512_HI = 0xac,
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PERF_WR512_LO = 0xb0,
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PERF_WR512_HI = 0xb4,
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PCI_RECONFIG = 0xb8,
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};
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enum rsxx_intr {
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CR_INTR_DMA0 = 0x00000001,
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CR_INTR_CREG = 0x00000002,
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CR_INTR_DMA1 = 0x00000004,
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CR_INTR_EVENT = 0x00000008,
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CR_INTR_DMA2 = 0x00000010,
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CR_INTR_DMA3 = 0x00000020,
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CR_INTR_DMA4 = 0x00000040,
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CR_INTR_DMA5 = 0x00000080,
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CR_INTR_DMA6 = 0x00000100,
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CR_INTR_DMA7 = 0x00000200,
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CR_INTR_ALL_C = 0x0000003f,
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CR_INTR_ALL_G = 0x000003ff,
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CR_INTR_DMA_ALL = 0x000003f5,
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CR_INTR_ALL = 0xffffffff,
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};
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static inline int CR_INTR_DMA(int N)
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{
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static const unsigned int _CR_INTR_DMA[] = {
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CR_INTR_DMA0, CR_INTR_DMA1, CR_INTR_DMA2, CR_INTR_DMA3,
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CR_INTR_DMA4, CR_INTR_DMA5, CR_INTR_DMA6, CR_INTR_DMA7
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};
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return _CR_INTR_DMA[N];
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}
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enum rsxx_pci_reset {
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DMA_QUEUE_RESET = 0x00000001,
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};
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enum rsxx_hw_fifo_flush {
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RSXX_FLUSH_BUSY = 0x00000002,
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RSXX_FLUSH_TIMEOUT = 0x00000004,
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};
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enum rsxx_pci_revision {
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RSXX_DISCARD_SUPPORT = 2,
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RSXX_EEH_SUPPORT = 3,
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};
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enum rsxx_creg_cmd {
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CREG_CMD_TAG_MASK = 0x0000FF00,
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CREG_OP_WRITE = 0x000000C0,
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CREG_OP_READ = 0x000000E0,
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};
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enum rsxx_creg_addr {
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CREG_ADD_CARD_CMD = 0x80001000,
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CREG_ADD_CARD_STATE = 0x80001004,
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CREG_ADD_CARD_SIZE = 0x8000100c,
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CREG_ADD_CAPABILITIES = 0x80001050,
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CREG_ADD_LOG = 0x80002000,
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CREG_ADD_NUM_TARGETS = 0x80003000,
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CREG_ADD_CRAM = 0xA0000000,
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CREG_ADD_CONFIG = 0xB0000000,
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};
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enum rsxx_creg_card_cmd {
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CARD_CMD_STARTUP = 1,
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CARD_CMD_SHUTDOWN = 2,
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CARD_CMD_LOW_LEVEL_FORMAT = 3,
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CARD_CMD_FPGA_RECONFIG_BR = 4,
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CARD_CMD_FPGA_RECONFIG_MAIN = 5,
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CARD_CMD_BACKUP = 6,
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CARD_CMD_RESET = 7,
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CARD_CMD_deprecated = 8,
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CARD_CMD_UNINITIALIZE = 9,
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CARD_CMD_DSTROY_EMERGENCY = 10,
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CARD_CMD_DSTROY_NORMAL = 11,
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CARD_CMD_DSTROY_EXTENDED = 12,
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CARD_CMD_DSTROY_ABORT = 13,
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};
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enum rsxx_card_state {
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CARD_STATE_SHUTDOWN = 0x00000001,
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CARD_STATE_STARTING = 0x00000002,
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CARD_STATE_FORMATTING = 0x00000004,
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CARD_STATE_UNINITIALIZED = 0x00000008,
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CARD_STATE_GOOD = 0x00000010,
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CARD_STATE_SHUTTING_DOWN = 0x00000020,
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CARD_STATE_FAULT = 0x00000040,
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CARD_STATE_RD_ONLY_FAULT = 0x00000080,
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CARD_STATE_DSTROYING = 0x00000100,
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};
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enum rsxx_led {
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LED_DEFAULT = 0x0,
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LED_IDENTIFY = 0x1,
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LED_SOAK = 0x2,
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};
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enum rsxx_creg_flash_lock {
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CREG_FLASH_LOCK = 1,
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CREG_FLASH_UNLOCK = 2,
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};
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enum rsxx_card_capabilities {
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CARD_CAP_SUBPAGE_WRITES = 0x00000080,
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};
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enum rsxx_creg_stat {
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CREG_STAT_STATUS_MASK = 0x00000003,
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CREG_STAT_SUCCESS = 0x1,
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CREG_STAT_ERROR = 0x2,
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CREG_STAT_CHAR_PENDING = 0x00000004, /* Character I/O pending bit */
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CREG_STAT_LOG_PENDING = 0x00000008, /* HW log message pending bit */
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CREG_STAT_TAG_MASK = 0x0000ff00,
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};
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enum rsxx_dma_finish {
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FREE_DMA = 0x0,
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COMPLETE_DMA = 0x1,
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};
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static inline unsigned int CREG_DATA(int N)
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{
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return CREG_DATA0 + (N << 2);
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}
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/*----------------- Convenient Log Wrappers -------------------*/
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#define CARD_TO_DEV(__CARD) (&(__CARD)->dev->dev)
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/***** config.c *****/
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int rsxx_load_config(struct rsxx_cardinfo *card);
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/***** core.c *****/
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void rsxx_enable_ier(struct rsxx_cardinfo *card, unsigned int intr);
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void rsxx_disable_ier(struct rsxx_cardinfo *card, unsigned int intr);
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void rsxx_enable_ier_and_isr(struct rsxx_cardinfo *card,
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unsigned int intr);
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void rsxx_disable_ier_and_isr(struct rsxx_cardinfo *card,
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unsigned int intr);
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/***** dev.c *****/
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int rsxx_attach_dev(struct rsxx_cardinfo *card);
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void rsxx_detach_dev(struct rsxx_cardinfo *card);
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int rsxx_setup_dev(struct rsxx_cardinfo *card);
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void rsxx_destroy_dev(struct rsxx_cardinfo *card);
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int rsxx_dev_init(void);
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void rsxx_dev_cleanup(void);
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/***** dma.c ****/
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typedef void (*rsxx_dma_cb)(struct rsxx_cardinfo *card,
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void *cb_data,
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unsigned int status);
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int rsxx_dma_setup(struct rsxx_cardinfo *card);
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void rsxx_dma_destroy(struct rsxx_cardinfo *card);
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int rsxx_dma_init(void);
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int rsxx_cleanup_dma_queue(struct rsxx_dma_ctrl *ctrl,
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struct list_head *q,
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unsigned int done);
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int rsxx_dma_cancel(struct rsxx_dma_ctrl *ctrl);
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void rsxx_dma_cleanup(void);
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void rsxx_dma_queue_reset(struct rsxx_cardinfo *card);
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int rsxx_dma_configure(struct rsxx_cardinfo *card);
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int rsxx_dma_queue_bio(struct rsxx_cardinfo *card,
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struct bio *bio,
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atomic_t *n_dmas,
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rsxx_dma_cb cb,
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void *cb_data);
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int rsxx_hw_buffers_init(struct pci_dev *dev, struct rsxx_dma_ctrl *ctrl);
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int rsxx_eeh_save_issued_dmas(struct rsxx_cardinfo *card);
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int rsxx_eeh_remap_dmas(struct rsxx_cardinfo *card);
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/***** cregs.c *****/
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int rsxx_creg_write(struct rsxx_cardinfo *card, u32 addr,
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unsigned int size8,
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void *data,
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int byte_stream);
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int rsxx_creg_read(struct rsxx_cardinfo *card,
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u32 addr,
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unsigned int size8,
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void *data,
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int byte_stream);
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int rsxx_read_hw_log(struct rsxx_cardinfo *card);
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int rsxx_get_card_state(struct rsxx_cardinfo *card,
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unsigned int *state);
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int rsxx_get_card_size8(struct rsxx_cardinfo *card, u64 *size8);
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int rsxx_get_num_targets(struct rsxx_cardinfo *card,
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unsigned int *n_targets);
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int rsxx_get_card_capabilities(struct rsxx_cardinfo *card,
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u32 *capabilities);
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int rsxx_issue_card_cmd(struct rsxx_cardinfo *card, u32 cmd);
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int rsxx_creg_setup(struct rsxx_cardinfo *card);
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void rsxx_creg_destroy(struct rsxx_cardinfo *card);
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int rsxx_creg_init(void);
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void rsxx_creg_cleanup(void);
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int rsxx_reg_access(struct rsxx_cardinfo *card,
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struct rsxx_reg_access __user *ucmd,
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int read);
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void rsxx_eeh_save_issued_creg(struct rsxx_cardinfo *card);
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void rsxx_kick_creg_queue(struct rsxx_cardinfo *card);
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#endif /* __DRIVERS_BLOCK_RSXX_H__ */
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