mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 01:08:03 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
33
drivers/bts/Kconfig
Normal file
33
drivers/bts/Kconfig
Normal file
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@ -0,0 +1,33 @@
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#
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# BTS driver configuration
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#
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menuconfig EXYNOS_BTS
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bool "BTS driver support"
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default y
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help
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Enable BTS (Bus traffic shaper) support
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if EXYNOS_BTS
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config EXYNOS8890_BTS
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bool "Bus traffic shaper support"
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default y
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depends on SOC_EXYNOS8890
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help
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Enable BTS (Bus traffic shaper) support
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config EXYNOS7870_BTS
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bool "Bus traffic shaper support"
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default y
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depends on SOC_EXYNOS7870
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help
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Enable BTS (Bus traffic shaper) support
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config EXYNOS7570_BTS
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bool "Bus traffic shaper support"
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default y
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depends on SOC_EXYNOS7570
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help
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Enable BTS (Bus traffic shaper) support
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endif
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7
drivers/bts/Makefile
Normal file
7
drivers/bts/Makefile
Normal file
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@ -0,0 +1,7 @@
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#
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# Makefile for BTS.
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#
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obj-$(CONFIG_EXYNOS8890_BTS) += cal_bts8890.o bts-exynos8890.o
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obj-$(CONFIG_EXYNOS7870_BTS) += cal_bts7870.o bts-exynos7870.o
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obj-$(CONFIG_EXYNOS7570_BTS) += cal_bts7570.o bts-exynos7570.o
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670
drivers/bts/bts-exynos7570.c
Normal file
670
drivers/bts/bts-exynos7570.c
Normal file
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@ -0,0 +1,670 @@
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/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/list.h>
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#include <linux/dma-mapping.h>
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#include <linux/pm_runtime.h>
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#include <linux/pm_qos.h>
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#include <linux/suspend.h>
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#include <linux/debugfs.h>
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#include <linux/clk-provider.h>
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#include <soc/samsung/bts.h>
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#include "cal_bts7570.h"
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#define BUS_WIDTH 16
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#define MIF_UTIL 15
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#define MIF_UTIL_WITH_CAM 10
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#ifdef BTS_DBGGEN
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#define BTS_DBG(x...) pr_err(x)
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#else
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#define BTS_DBG(x...) do {} while (0)
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#endif
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enum bts_index {
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BTS_IDX_CP_CELLULAR,
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BTS_IDX_ISP,
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BTS_IDX_DISPAUD,
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BTS_IDX_CPU,
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BTS_IDX_APM,
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BTS_IDX_CP_GNSS,
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BTS_IDX_CP_WLBT,
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BTS_IDX_MFCMSCL,
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BTS_IDX_G3D,
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BTS_IDX_FSYS,
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BTS_MAX,
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};
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enum exynos_bts_scenario {
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BS_DEFAULT,
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BS_DISABLE,
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BS_MAX,
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BS_USER = 2,
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};
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enum exynos_bts_function {
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F_NOP,
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BF_SETQOS,
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BF_SETQOS_BW,
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BF_SETQOS_MO,
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BF_DISABLE,
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TF_SETQOS,
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TF_SETQOS_MO,
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TF_DISABLE,
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SF_SETQOS,
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SF_DISABLE,
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};
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struct bts_table {
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enum exynos_bts_function fn;
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unsigned int priority;
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unsigned int window;
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unsigned int token;
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unsigned int mo;
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struct bts_info *next_bts;
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int prev_scen;
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int next_scen;
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};
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struct bts_info {
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enum bts_index id;
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const char *name;
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unsigned int pa_base;
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void __iomem *va_base;
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struct bts_table table[BS_MAX];
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const char *pd_name;
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bool on;
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struct list_head list;
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bool enable;
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struct clk_info *ct_ptr;
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enum exynos_bts_scenario top_scen;
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};
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struct bts_scenario {
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const char *name;
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enum exynos_bts_scenario id;
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struct bts_info *head;
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};
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struct clk_info {
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const char *clk_name;
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struct clk *clk;
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struct bts_info *bts;
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};
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static struct pm_qos_request exynos7_mif_bts_qos;
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static struct pm_qos_request exynos7_int_bts_qos;
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static DEFINE_MUTEX(media_mutex);
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static void __iomem *base_drex;
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static struct bts_info exynos7_bts[] = {
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[BTS_IDX_CPU] = {
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.id = BTS_SYSREG_CPU,
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.name = "cpu",
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.pa_base = EXYNOS7570_PA_SYSREG_CPU,
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.pd_name = "pd-cpu",
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.table[BS_DISABLE].fn = SF_DISABLE,
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.table[BS_DEFAULT].fn = SF_SETQOS,
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.table[BS_DEFAULT].priority = 0x4,
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.on = false,
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.enable = true,
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},
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[BTS_IDX_APM] = {
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.id = BTS_SYSREG_APM,
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.name = "apm",
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.pa_base = EXYNOS7570_PA_SYSREG_APM,
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.pd_name = "pd-apm",
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.table[BS_DISABLE].fn = SF_DISABLE,
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.table[BS_DEFAULT].fn = SF_SETQOS,
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.table[BS_DEFAULT].priority = 0x4,
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.on = false,
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.enable = true,
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},
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[BTS_IDX_CP_GNSS] = {
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.id = BTS_SYSREG_CPGNSS,
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.name = "cp_gnss",
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.pa_base = EXYNOS7570_PA_SYSREG_CP,
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.pd_name = "pd-pmu",
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.table[BS_DISABLE].fn = SF_DISABLE,
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.table[BS_DEFAULT].fn = SF_SETQOS,
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.table[BS_DEFAULT].priority = 0x4,
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.on = false,
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.enable = true,
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},
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[BTS_IDX_CP_CELLULAR] = {
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.name = "cp_cell",
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.pa_base = EXYNOS7570_PA_TREX_CELLULAR,
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.pd_name = "pd-trex",
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.table[BS_DISABLE].fn = TF_DISABLE,
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.table[BS_DEFAULT].fn = TF_DISABLE,
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.on = false,
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.enable = true,
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},
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[BTS_IDX_CP_WLBT] = {
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.name = "cp_wlbt",
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.pa_base = EXYNOS7570_PA_TREX_WLBT,
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.pd_name = "pd-trex",
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.table[BS_DISABLE].fn = TF_DISABLE,
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.table[BS_DEFAULT].fn = TF_SETQOS,
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.table[BS_DEFAULT].priority = 0x4,
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.on = false,
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.enable = true,
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},
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[BTS_IDX_MFCMSCL] = {
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.name = "mfcmscl",
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.pa_base = EXYNOS7570_PA_TREX_MFCMSCL,
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.pd_name = "pd-trex",
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.table[BS_DISABLE].fn = TF_DISABLE,
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.table[BS_DEFAULT].fn = TF_SETQOS,
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.table[BS_DEFAULT].priority = 0x4,
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.on = false,
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.enable = true,
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},
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[BTS_IDX_G3D] = {
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.name = "g3d",
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.pa_base = EXYNOS7570_PA_TREX_G3D,
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.pd_name = "pd-trex",
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.table[BS_DISABLE].fn = TF_DISABLE,
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.table[BS_DEFAULT].fn = TF_SETQOS,
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.table[BS_DEFAULT].priority = 0x4,
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.on = false,
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.enable = true,
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},
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[BTS_IDX_FSYS] = {
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.name = "fsys",
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.pa_base = EXYNOS7570_PA_TREX_FSYS,
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.pd_name = "pd-trex",
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.table[BS_DISABLE].fn = TF_DISABLE,
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.table[BS_DEFAULT].fn = TF_SETQOS,
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.table[BS_DEFAULT].priority = 0x4,
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.on = false,
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.enable = true,
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},
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[BTS_IDX_ISP] = {
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.name = "isp",
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.pa_base = EXYNOS7570_PA_TREX_ISP,
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.pd_name = "pd-trex",
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.table[BS_DISABLE].fn = TF_DISABLE,
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.table[BS_DEFAULT].fn = TF_SETQOS,
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.table[BS_DEFAULT].priority = 0xC,
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.on = false,
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.enable = true,
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},
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[BTS_IDX_DISPAUD] = {
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.name = "dispaud",
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.pa_base = EXYNOS7570_PA_TREX_DISPAUD,
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.pd_name = "pd-trex",
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.table[BS_DISABLE].fn = TF_DISABLE,
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.table[BS_DEFAULT].fn = TF_SETQOS,
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.table[BS_DEFAULT].priority = 0xA,
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.on = false,
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.enable = true,
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},
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};
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static struct clk_info clk_table[0];
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static struct bts_scenario bts_scen[BS_MAX] = {
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[BS_DISABLE] = {
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.name = "disable",
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},
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[BS_DEFAULT] = {
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.name = "default",
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},
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};
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|
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static DEFINE_SPINLOCK(bts_lock);
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static LIST_HEAD(bts_list);
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static void bts_clk_on(struct bts_info *bts)
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{
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struct clk_info *ptr;
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ptr = bts->ct_ptr;
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if (ptr) {
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bts = ptr->bts;
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do {
|
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clk_enable(ptr->clk);
|
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} while (++ptr < clk_table + ARRAY_SIZE(clk_table)
|
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&& ptr->bts == bts);
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}
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}
|
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|
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static void bts_clk_off(struct bts_info *bts)
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{
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struct clk_info *ptr;
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|
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ptr = bts->ct_ptr;
|
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if (ptr) {
|
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bts = ptr->bts;
|
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do {
|
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clk_disable(ptr->clk);
|
||||
} while (++ptr < clk_table + ARRAY_SIZE(clk_table)
|
||||
&& ptr->bts == bts);
|
||||
}
|
||||
}
|
||||
|
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static void bts_set_ip_table(struct bts_info *bts)
|
||||
{
|
||||
enum exynos_bts_scenario scen = bts->top_scen;
|
||||
enum exynos_bts_function fn = bts->table[scen].fn;
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||||
|
||||
BTS_DBG("[BTS] %s on:%d bts scen: [%s]->[%s]\n", bts->name, bts->on,
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bts_scen[scen].name, bts_scen[scen].name);
|
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|
||||
switch (fn) {
|
||||
case BF_SETQOS:
|
||||
bts_setqos(bts->va_base, bts->table[scen].priority);
|
||||
break;
|
||||
case BF_SETQOS_MO:
|
||||
bts_setqos_mo(bts->va_base, bts->table[scen].priority,
|
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bts->table[scen].mo);
|
||||
break;
|
||||
case BF_DISABLE:
|
||||
bts_disable(bts->va_base);
|
||||
break;
|
||||
case TF_SETQOS:
|
||||
trex_setqos(bts->va_base, bts->table[scen].priority);
|
||||
break;
|
||||
case TF_SETQOS_MO:
|
||||
trex_setqos_mo(bts->va_base, bts->table[scen].priority,
|
||||
bts->table[scen].mo);
|
||||
break;
|
||||
case TF_DISABLE:
|
||||
trex_disable(bts->va_base);
|
||||
break;
|
||||
case SF_SETQOS:
|
||||
sysreg_setqos(bts->id, bts->va_base,
|
||||
bts->table[scen].priority);
|
||||
break;
|
||||
case SF_DISABLE:
|
||||
sysreg_disable(bts->id, bts->va_base);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void bts_add_scen(enum exynos_bts_scenario scen)
|
||||
{
|
||||
struct bts_info *first = bts_scen[scen].head;
|
||||
struct bts_info *bts = bts_scen[scen].head;
|
||||
int next = 0;
|
||||
int prev = 0;
|
||||
|
||||
if (!bts || scen < BS_USER)
|
||||
return;
|
||||
|
||||
BTS_DBG("[bts] scen %s on\n", bts_scen[scen].name);
|
||||
|
||||
do {
|
||||
if (bts->enable &&!bts->table[scen].next_scen) {
|
||||
if (scen >= bts->top_scen) {
|
||||
/* insert at top priority */
|
||||
bts->table[scen].prev_scen = bts->top_scen;
|
||||
bts->table[bts->top_scen].next_scen = scen;
|
||||
bts->top_scen = scen;
|
||||
bts->table[scen].next_scen = -1;
|
||||
|
||||
if (bts->on)
|
||||
bts_set_ip_table(bts);
|
||||
|
||||
} else {
|
||||
/* insert at middle */
|
||||
for (prev = bts->top_scen; prev > scen; prev = bts->table[prev].prev_scen)
|
||||
next = prev;
|
||||
|
||||
bts->table[scen].prev_scen = bts->table[next].prev_scen;
|
||||
bts->table[scen].next_scen = bts->table[prev].next_scen;
|
||||
bts->table[next].prev_scen = scen;
|
||||
bts->table[prev].next_scen = scen;
|
||||
}
|
||||
}
|
||||
|
||||
bts = bts->table[scen].next_bts;
|
||||
/* set all bts ip in the current scenario */
|
||||
} while (bts && bts != first);
|
||||
}
|
||||
|
||||
static void bts_del_scen(enum exynos_bts_scenario scen)
|
||||
{
|
||||
struct bts_info *first = bts_scen[scen].head;
|
||||
struct bts_info *bts = bts_scen[scen].head;
|
||||
int next = 0;
|
||||
int prev = 0;
|
||||
|
||||
if (!bts || scen < BS_USER)
|
||||
return;
|
||||
|
||||
BTS_DBG("[bts] scen %s off\n", bts_scen[scen].name);
|
||||
|
||||
do {
|
||||
if (bts->enable && bts->table[scen].next_scen) {
|
||||
if (scen == bts->top_scen) {
|
||||
/* revert to prev scenario */
|
||||
prev = bts->table[scen].prev_scen;
|
||||
bts->top_scen = prev;
|
||||
bts->table[prev].next_scen = -1;
|
||||
bts->table[scen].next_scen = 0;
|
||||
bts->table[scen].prev_scen = 0;
|
||||
|
||||
if (bts->on)
|
||||
bts_set_ip_table(bts);
|
||||
} else if (scen < bts->top_scen) {
|
||||
/* delete mid scenario */
|
||||
prev = bts->table[scen].prev_scen;
|
||||
next = bts->table[scen].next_scen;
|
||||
|
||||
bts->table[next].prev_scen = bts->table[scen].prev_scen;
|
||||
bts->table[prev].next_scen = bts->table[scen].next_scen;
|
||||
|
||||
bts->table[scen].prev_scen = 0;
|
||||
bts->table[scen].next_scen = 0;
|
||||
|
||||
} else {
|
||||
BTS_DBG("[BTS]%s scenario couldn't exist above top_scen\n", bts_scen[scen].name);
|
||||
}
|
||||
}
|
||||
|
||||
bts = bts->table[scen].next_bts;
|
||||
/* revert all bts ip to prev in the current scenario */
|
||||
} while (bts && bts != first);
|
||||
}
|
||||
|
||||
void bts_scen_update(enum bts_scen_type type, unsigned int val)
|
||||
{
|
||||
enum exynos_bts_scenario scen = BS_DEFAULT;
|
||||
bool on = val ? 1 : 0;
|
||||
|
||||
spin_lock(&bts_lock);
|
||||
|
||||
switch (type) {
|
||||
default:
|
||||
spin_unlock(&bts_lock);
|
||||
return;
|
||||
}
|
||||
|
||||
if (on)
|
||||
bts_add_scen(scen);
|
||||
else
|
||||
bts_del_scen(scen);
|
||||
|
||||
spin_unlock(&bts_lock);
|
||||
}
|
||||
|
||||
void bts_initialize(const char *pd_name, bool on)
|
||||
{
|
||||
struct bts_info *bts;
|
||||
|
||||
spin_lock(&bts_lock);
|
||||
|
||||
list_for_each_entry(bts, &bts_list, list)
|
||||
if (pd_name && bts->pd_name && !strncmp(bts->pd_name, pd_name, strlen(pd_name))) {
|
||||
BTS_DBG("[BTS] %s on/off:%d->%d\n", bts->name, bts->on, on);
|
||||
|
||||
if (!bts->enable) {
|
||||
bts->on = on;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (on) {
|
||||
bts->on = true;
|
||||
bts_set_ip_table(bts);
|
||||
} else {
|
||||
bts->on = false;
|
||||
}
|
||||
}
|
||||
|
||||
spin_unlock(&bts_lock);
|
||||
}
|
||||
|
||||
static void scen_chaining(enum exynos_bts_scenario scen)
|
||||
{
|
||||
struct bts_info *prev = NULL;
|
||||
struct bts_info *first = NULL;
|
||||
struct bts_info *bts;
|
||||
|
||||
list_for_each_entry(bts, &bts_list, list) {
|
||||
if (bts->table[scen].fn) {
|
||||
if (!first)
|
||||
first = bts;
|
||||
if (prev)
|
||||
prev->table[scen].next_bts = bts;
|
||||
|
||||
prev = bts;
|
||||
}
|
||||
}
|
||||
|
||||
if (prev)
|
||||
prev->table[scen].next_bts = first;
|
||||
|
||||
bts_scen[scen].head = first;
|
||||
}
|
||||
|
||||
static int exynos7_qos_status_open_show(struct seq_file *buf, void *d)
|
||||
{
|
||||
struct bts_info *bts;
|
||||
|
||||
spin_lock(&bts_lock);
|
||||
|
||||
for (bts = exynos7_bts; bts <= &exynos7_bts[BTS_MAX - 1]; bts++) {
|
||||
if (!bts->enable)
|
||||
continue;
|
||||
seq_printf(buf, "[BTS] %7s: scen %s, ", bts->name,
|
||||
bts_scen[bts->top_scen].name);
|
||||
if (bts->on) {
|
||||
if (bts->ct_ptr)
|
||||
bts_clk_on(bts);
|
||||
|
||||
switch (bts->table[BS_DISABLE].fn) {
|
||||
case BF_DISABLE:
|
||||
bts_showqos(bts->va_base, buf);
|
||||
break;
|
||||
case TF_DISABLE:
|
||||
trex_showqos(bts->va_base, buf);
|
||||
break;
|
||||
case SF_DISABLE:
|
||||
sysreg_showqos(bts->id, bts->va_base, buf);
|
||||
break;
|
||||
default:
|
||||
seq_puts(buf, "none\n");
|
||||
break;
|
||||
}
|
||||
|
||||
if (bts->ct_ptr)
|
||||
bts_clk_off(bts);
|
||||
} else {
|
||||
seq_puts(buf, "off\n");
|
||||
}
|
||||
}
|
||||
|
||||
spin_unlock(&bts_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int exynos7_qos_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, exynos7_qos_status_open_show, inode->i_private);
|
||||
}
|
||||
|
||||
static const struct file_operations debug_qos_status_fops = {
|
||||
.open = exynos7_qos_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
void bts_debugfs(void)
|
||||
{
|
||||
struct dentry *den;
|
||||
|
||||
den = debugfs_create_dir("bts", NULL);
|
||||
debugfs_create_file("qos", 0440, den, NULL, &debug_qos_status_fops);
|
||||
}
|
||||
|
||||
static void bts_drex_init(void __iomem *base)
|
||||
{
|
||||
|
||||
BTS_DBG("[BTS][%s] bts drex init\n", __func__);
|
||||
|
||||
__raw_writel(0x00000000, base + QOS_TIMEOUT_0xF);
|
||||
__raw_writel(0x00000004, base + QOS_TIMEOUT_0xE);
|
||||
__raw_writel(0x00000010, base + QOS_TIMEOUT_0xD);
|
||||
__raw_writel(0x00000010, base + QOS_TIMEOUT_0xC);
|
||||
__raw_writel(0x00000020, base + QOS_TIMEOUT_0xB);
|
||||
__raw_writel(0x00000040, base + QOS_TIMEOUT_0xA);
|
||||
__raw_writel(0x00000100, base + QOS_TIMEOUT_0x9);
|
||||
__raw_writel(0x00000100, base + QOS_TIMEOUT_0x8);
|
||||
__raw_writel(0x00000100, base + QOS_TIMEOUT_0x7);
|
||||
__raw_writel(0x00000100, base + QOS_TIMEOUT_0x6);
|
||||
__raw_writel(0x00000100, base + QOS_TIMEOUT_0x5);
|
||||
__raw_writel(0x00000100, base + QOS_TIMEOUT_0x4);
|
||||
__raw_writel(0x00000100, base + QOS_TIMEOUT_0x3);
|
||||
__raw_writel(0x00000100, base + QOS_TIMEOUT_0x2);
|
||||
__raw_writel(0x00000100, base + QOS_TIMEOUT_0x1);
|
||||
__raw_writel(0x00000100, base + QOS_TIMEOUT_0x0);
|
||||
}
|
||||
|
||||
static void bts_initialize_domains(void)
|
||||
{
|
||||
bts_initialize("pd-cpu", true);
|
||||
bts_initialize("pd-apm", true);
|
||||
bts_initialize("pd-pmu", true);
|
||||
bts_initialize("pd-trex", true);
|
||||
}
|
||||
|
||||
static int exynos_bts_notifier_event(struct notifier_block *this,
|
||||
unsigned long event,
|
||||
void *ptr)
|
||||
{
|
||||
switch (event) {
|
||||
case PM_POST_SUSPEND:
|
||||
bts_drex_init(base_drex);
|
||||
bts_initialize_domains();
|
||||
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static struct notifier_block exynos_bts_notifier = {
|
||||
.notifier_call = exynos_bts_notifier_event,
|
||||
};
|
||||
|
||||
void exynos7_init_bts_ioremap(void)
|
||||
{
|
||||
base_drex = ioremap(EXYNOS7570_PA_DREX, SZ_4K);
|
||||
}
|
||||
|
||||
void exynos_update_media_scenario(enum bts_media_type media_type,
|
||||
unsigned int bw, int bw_type)
|
||||
{
|
||||
static unsigned int decon_bw, cam_bw;
|
||||
unsigned int mif_freq;
|
||||
unsigned int total_bw;
|
||||
mutex_lock(&media_mutex);
|
||||
|
||||
switch (media_type) {
|
||||
case TYPE_DECON_INT:
|
||||
if (decon_bw == bw)
|
||||
goto out;
|
||||
decon_bw = bw >> 10;
|
||||
break;
|
||||
case TYPE_CAM:
|
||||
if (cam_bw == bw)
|
||||
goto out;
|
||||
cam_bw = bw >> 10;
|
||||
break;
|
||||
default:
|
||||
pr_err("DEVFREQ(MIF) : unsupportd media_type - %u", media_type);
|
||||
break;
|
||||
}
|
||||
|
||||
total_bw = decon_bw + cam_bw;
|
||||
|
||||
/* MIF minimum frequency calculation as per BTS guide */
|
||||
if (cam_bw) {
|
||||
mif_freq = decon_bw * 100 / BUS_WIDTH / MIF_UTIL_WITH_CAM;
|
||||
} else {
|
||||
mif_freq = decon_bw * 100 / BUS_WIDTH / MIF_UTIL;
|
||||
}
|
||||
|
||||
BTS_DBG("[BTS BW] total: %uKB/s, decon %uKB/s, cam %uKB/s\n",
|
||||
total_bw, decon_bw, cam_bw);
|
||||
BTS_DBG("[BTS FREQ] mif_freq: %uKhz\n", mif_freq);
|
||||
|
||||
pm_qos_update_request(&exynos7_mif_bts_qos, mif_freq);
|
||||
out:
|
||||
mutex_unlock(&media_mutex);
|
||||
}
|
||||
|
||||
static int __init exynos7_bts_init(void)
|
||||
{
|
||||
int i;
|
||||
int ret;
|
||||
struct bts_info *bts = NULL;
|
||||
|
||||
BTS_DBG("[BTS][%s] bts init\n", __func__);
|
||||
|
||||
/* clk initialize */
|
||||
for (i = 0; i < ARRAY_SIZE(clk_table); i++) {
|
||||
|
||||
if (bts && bts != clk_table[i].bts) {
|
||||
bts = clk_table[i].bts;
|
||||
bts->ct_ptr = clk_table + i;
|
||||
}
|
||||
clk_table[i].clk = clk_get(NULL, clk_table[i].clk_name);
|
||||
|
||||
if (IS_ERR(clk_table[i].clk)){
|
||||
BTS_DBG("failed to get bts clk %s\n",
|
||||
clk_table[i].clk_name);
|
||||
bts->ct_ptr = NULL;
|
||||
}
|
||||
else {
|
||||
ret = clk_prepare(clk_table[i].clk);
|
||||
if (ret) {
|
||||
pr_err("[BTS] failed to prepare bts clk %s\n",
|
||||
clk_table[i].clk_name);
|
||||
for (; i >= 0; i--)
|
||||
clk_put(clk_table[i].clk);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(exynos7_bts); i++) {
|
||||
exynos7_bts[i].va_base = ioremap(exynos7_bts[i].pa_base, SZ_2K);
|
||||
|
||||
list_add(&exynos7_bts[i].list, &bts_list);
|
||||
}
|
||||
|
||||
for (i = BS_USER; i < BS_MAX; i++) {
|
||||
scen_chaining(i);
|
||||
BTS_DBG("[BTS][%s] scene(%d) is chanined\n", __func__, i);
|
||||
}
|
||||
|
||||
exynos7_init_bts_ioremap();
|
||||
bts_drex_init(base_drex);
|
||||
bts_initialize_domains();
|
||||
|
||||
pm_qos_add_request(&exynos7_mif_bts_qos, PM_QOS_BUS_THROUGHPUT, 0);
|
||||
pm_qos_add_request(&exynos7_int_bts_qos, PM_QOS_DEVICE_THROUGHPUT, 0);
|
||||
|
||||
register_pm_notifier(&exynos_bts_notifier);
|
||||
bts_debugfs();
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(exynos7_bts_init);
|
||||
1185
drivers/bts/bts-exynos7870.c
Normal file
1185
drivers/bts/bts-exynos7870.c
Normal file
File diff suppressed because it is too large
Load diff
1024
drivers/bts/bts-exynos8890.c
Normal file
1024
drivers/bts/bts-exynos8890.c
Normal file
File diff suppressed because it is too large
Load diff
332
drivers/bts/cal_bts.c
Normal file
332
drivers/bts/cal_bts.c
Normal file
|
|
@ -0,0 +1,332 @@
|
|||
/* arch/arm/mach-exynos/cal_bts.c
|
||||
*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* EXYNOS - BTS CAL code.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "cal_bts.h"
|
||||
|
||||
void bts_setqos(addr_u32 base, unsigned int priority) //QOS : [RRRRWWWW]
|
||||
{
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY, ((priority >> 16) & 0xFFFF));
|
||||
Outp32(base + BTS_TOKENMAX, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND, 0x1);
|
||||
Outp32(base + BTS_INITTKN, 0x8);
|
||||
|
||||
Outp32(base + BTS_PRIORITY + WOFFSET, (priority & 0xFFFF));
|
||||
Outp32(base + BTS_TOKENMAX + WOFFSET, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND + WOFFSET, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND + WOFFSET, 0x1);
|
||||
Outp32(base + BTS_INITTKN + WOFFSET, 0x8);
|
||||
|
||||
Outp32(base + BTS_RCON, 0x1);
|
||||
Outp32(base + BTS_WCON, 0x1);
|
||||
}
|
||||
|
||||
void bts_setqos_bw(addr_u32 base, unsigned int priority,
|
||||
unsigned int window, unsigned int token) //QOS : [RRRRWWWW]
|
||||
{
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY, ((priority >> 16) & 0xFFFF));
|
||||
Outp32(base + BTS_TOKENMAX, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND, 0x1);
|
||||
Outp32(base + BTS_INITTKN, 0x8);
|
||||
Outp32(base + BTS_DEMWIN, window);
|
||||
Outp32(base + BTS_DEMTKN, token);
|
||||
Outp32(base + BTS_DEFWIN, window);
|
||||
Outp32(base + BTS_DEFTKN, token);
|
||||
Outp32(base + BTS_PRMWIN, window);
|
||||
Outp32(base + BTS_PRMTKN, token);
|
||||
Outp32(base + BTS_FLEXIBLE, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY + WOFFSET, (priority & 0xFFFF));
|
||||
Outp32(base + BTS_TOKENMAX + WOFFSET, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND + WOFFSET, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND + WOFFSET, 0x1);
|
||||
Outp32(base + BTS_INITTKN + WOFFSET, 0x8);
|
||||
Outp32(base + BTS_DEMWIN + WOFFSET, window);
|
||||
Outp32(base + BTS_DEMTKN + WOFFSET, token);
|
||||
Outp32(base + BTS_DEFWIN + WOFFSET, window);
|
||||
Outp32(base + BTS_DEFTKN + WOFFSET, token);
|
||||
Outp32(base + BTS_PRMWIN + WOFFSET, window);
|
||||
Outp32(base + BTS_PRMTKN + WOFFSET, token);
|
||||
Outp32(base + BTS_FLEXIBLE + WOFFSET, 0x0);
|
||||
|
||||
Outp32(base + BTS_RMODE, 0x1);
|
||||
Outp32(base + BTS_WMODE, 0x1);
|
||||
Outp32(base + BTS_RCON, 0x3);
|
||||
Outp32(base + BTS_WCON, 0x3);
|
||||
}
|
||||
|
||||
|
||||
void bts_setqos_mo(addr_u32 base, unsigned int priority,
|
||||
unsigned int rmo, unsigned int wmo) //QOS : [RRRRWWWW]
|
||||
{
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY, ((priority >> 16) & 0xFFFF));
|
||||
Outp32(base + BTS_PRIORITY + WOFFSET, (priority & 0xFFFF));
|
||||
|
||||
if(rmo < MAX_MO_LIMIT)
|
||||
{
|
||||
Outp32(base + BTS_MOUPBOUND, 0x7F - rmo);
|
||||
Outp32(base + BTS_MOLOBOUND, rmo);
|
||||
Outp32(base + BTS_FLEXIBLE, 0x0);
|
||||
Outp32(base + BTS_RMODE, 0x2);
|
||||
Outp32(base + BTS_RCON, 0x3);
|
||||
}
|
||||
else
|
||||
{
|
||||
Outp32(base + BTS_TOKENMAX, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND, 0x1);
|
||||
Outp32(base + BTS_INITTKN, 0x8);
|
||||
Outp32(base + BTS_RCON, 0x1);
|
||||
}
|
||||
|
||||
if(wmo < MAX_MO_LIMIT)
|
||||
{
|
||||
Outp32(base + BTS_MOUPBOUND + WOFFSET, 0x7F - wmo);
|
||||
Outp32(base + BTS_MOLOBOUND + WOFFSET, wmo);
|
||||
Outp32(base + BTS_FLEXIBLE + WOFFSET, 0x0);
|
||||
Outp32(base + BTS_WMODE, 0x2);
|
||||
Outp32(base + BTS_WCON, 0x3);
|
||||
}
|
||||
else
|
||||
{
|
||||
Outp32(base + BTS_TOKENMAX + WOFFSET, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND + WOFFSET, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND + WOFFSET, 0x1);
|
||||
Outp32(base + BTS_INITTKN + WOFFSET, 0x8);
|
||||
Outp32(base + BTS_WCON, 0x1);
|
||||
}
|
||||
}
|
||||
|
||||
void bts_setqos_fbmbw(addr_u32 base, unsigned int priority, unsigned int window,
|
||||
unsigned int token, unsigned int fbm) //QOS : [RRRRWWWW]
|
||||
{
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY, ((priority >> 16) & 0xFFFF));
|
||||
Outp32(base + BTS_TOKENMAX, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND, 0x1);
|
||||
Outp32(base + BTS_INITTKN, 0x8);
|
||||
Outp32(base + BTS_DEMWIN, window);
|
||||
Outp32(base + BTS_DEMTKN, token);
|
||||
Outp32(base + BTS_DEFWIN, window);
|
||||
Outp32(base + BTS_DEFTKN, token);
|
||||
Outp32(base + BTS_PRMWIN, window);
|
||||
Outp32(base + BTS_PRMTKN, token);
|
||||
Outp32(base + BTS_FLEXIBLE, 0x2);
|
||||
|
||||
Outp32(base + BTS_PRIORITY + WOFFSET, (priority & 0xFFFF));
|
||||
Outp32(base + BTS_TOKENMAX + WOFFSET, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND + WOFFSET, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND + WOFFSET, 0x1);
|
||||
Outp32(base + BTS_INITTKN + WOFFSET, 0x8);
|
||||
Outp32(base + BTS_DEMWIN + WOFFSET, window);
|
||||
Outp32(base + BTS_DEMTKN + WOFFSET, token);
|
||||
Outp32(base + BTS_DEFWIN + WOFFSET, window);
|
||||
Outp32(base + BTS_DEFTKN + WOFFSET, token);
|
||||
Outp32(base + BTS_PRMWIN + WOFFSET, window);
|
||||
Outp32(base + BTS_PRMTKN + WOFFSET, token);
|
||||
Outp32(base + BTS_FLEXIBLE + WOFFSET, 0x1);
|
||||
|
||||
Outp32(base + BTS_RMODE, 0x1);
|
||||
Outp32(base + BTS_WMODE, 0x1);
|
||||
|
||||
if(fbm == 1) {
|
||||
Outp32(base + BTS_RCON, 0x7);
|
||||
Outp32(base + BTS_WCON, 0x7);
|
||||
} else {
|
||||
Outp32(base + BTS_RCON, 0x3);
|
||||
Outp32(base + BTS_WCON, 0x3);
|
||||
}
|
||||
}
|
||||
|
||||
void bts_disable(addr_u32 base)
|
||||
{
|
||||
/* reset to default */
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + BTS_RMODE, 0x1);
|
||||
Outp32(base + BTS_WMODE, 0x1);
|
||||
|
||||
Outp32(base + BTS_PRIORITY, 0xA942);
|
||||
Outp32(base + BTS_TOKENMAX, 0x0);
|
||||
Outp32(base + BTS_BWUPBOUND, 0x3FFF);
|
||||
Outp32(base + BTS_BWLOBOUND, 0x3FFF);
|
||||
Outp32(base + BTS_INITTKN, 0x7FFF);
|
||||
Outp32(base + BTS_DEMWIN, 0x7FFF);
|
||||
Outp32(base + BTS_DEMTKN, 0x1FFF);
|
||||
Outp32(base + BTS_DEFWIN, 0x7FFF);
|
||||
Outp32(base + BTS_DEFTKN, 0x1FFF);
|
||||
Outp32(base + BTS_PRMWIN, 0x7FFF);
|
||||
Outp32(base + BTS_PRMTKN, 0x1FFF);
|
||||
Outp32(base + BTS_MOUPBOUND, 0x1F);
|
||||
Outp32(base + BTS_MOLOBOUND, 0x1F);
|
||||
Outp32(base + BTS_FLEXIBLE, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY + WOFFSET, 0xA942);
|
||||
Outp32(base + BTS_TOKENMAX + WOFFSET, 0x0);
|
||||
Outp32(base + BTS_BWUPBOUND + WOFFSET, 0x3FFF);
|
||||
Outp32(base + BTS_BWLOBOUND + WOFFSET, 0x3FFF);
|
||||
Outp32(base + BTS_INITTKN + WOFFSET, 0x7FFF);
|
||||
Outp32(base + BTS_DEMWIN + WOFFSET, 0x7FFF);
|
||||
Outp32(base + BTS_DEMTKN + WOFFSET, 0x1FFF);
|
||||
Outp32(base + BTS_DEFWIN + WOFFSET, 0x7FFF);
|
||||
Outp32(base + BTS_DEFTKN + WOFFSET, 0x1FFF);
|
||||
Outp32(base + BTS_PRMWIN + WOFFSET, 0x7FFF);
|
||||
Outp32(base + BTS_PRMTKN + WOFFSET, 0x1FFF);
|
||||
Outp32(base + BTS_MOUPBOUND + WOFFSET, 0x1F);
|
||||
Outp32(base + BTS_MOLOBOUND + WOFFSET, 0x1F);
|
||||
Outp32(base + BTS_FLEXIBLE + WOFFSET, 0x0);
|
||||
}
|
||||
|
||||
void bts_settrexqos(addr_u32 base, unsigned int priority)
|
||||
{
|
||||
Outp32(base + TBTS_CON, 0x0);
|
||||
Outp32(base + TBTS_RCON, 0x0);
|
||||
Outp32(base + TBTS_WCON, 0x0);
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS7420_EVT_0)
|
||||
Outp32(base + TBTS_QURGUPTH, 0xF);
|
||||
Outp32(base + TBTS_QURGDOWNTH, 0xF);
|
||||
#endif
|
||||
Outp32(base + TBTS_DEMQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_DEFQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_PRMQOS, priority & 0xF);
|
||||
|
||||
Outp32(base + TBTS_CON, 0x1);
|
||||
}
|
||||
|
||||
void bts_settrexqos_mo(addr_u32 base, unsigned int priority, unsigned int mo)
|
||||
{
|
||||
Outp32(base + TBTS_CON, 0x0);
|
||||
Outp32(base + TBTS_RCON, 0x0);
|
||||
Outp32(base + TBTS_WCON, 0x0);
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS7420_EVT_0)
|
||||
Outp32(base + TBTS_QURGUPTH, 0xF);
|
||||
Outp32(base + TBTS_QURGDOWNTH, 0xF);
|
||||
#endif
|
||||
Outp32(base + TBTS_TKNUPBOUND, mo);
|
||||
Outp32(base + TBTS_TKNLOBOUND, mo);
|
||||
|
||||
Outp32(base + TBTS_DEMTH, mo);
|
||||
Outp32(base + TBTS_PRMTH, mo);
|
||||
|
||||
Outp32(base + TBTS_DEMQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_DEFQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_PRMQOS, priority & 0xF);
|
||||
|
||||
Outp32(base + TBTS_RCON, 0x11); // MO mode & Blocking on
|
||||
Outp32(base + TBTS_WCON, 0x11);
|
||||
Outp32(base + TBTS_CON, 0x1);
|
||||
}
|
||||
|
||||
void bts_settrexqos_bw(addr_u32 base, unsigned int priority, unsigned int decval)
|
||||
{
|
||||
Outp32(base + TBTS_CON, 0x0);
|
||||
Outp32(base + TBTS_RCON, 0x0);
|
||||
Outp32(base + TBTS_WCON, 0x0);
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS7420_EVT_0)
|
||||
Outp32(base + TBTS_QURGUPTH, 0xF);
|
||||
Outp32(base + TBTS_QURGDOWNTH, 0xF);
|
||||
#endif
|
||||
|
||||
Outp32(base + TBTS_TKNUPBOUND, 0x3FFF);
|
||||
Outp32(base + TBTS_TKNLOBOUND, 0x3FF7);
|
||||
Outp32(base + TBTS_RTKNINIT, 0x3FFF);
|
||||
Outp32(base + TBTS_WTKNINIT, 0x3FFF);
|
||||
|
||||
Outp32(base + TBTS_DEMQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_DEFQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_PRMQOS, priority & 0xF);
|
||||
|
||||
Outp32(base + TBTS_RTKNDEC, decval);
|
||||
Outp32(base + TBTS_WTKNDEC, decval);
|
||||
|
||||
Outp32(base + TBTS_RCON, 0x1); // Blocking on
|
||||
Outp32(base + TBTS_WCON, 0x1);
|
||||
Outp32(base + TBTS_CON, 0x1);
|
||||
|
||||
}
|
||||
|
||||
void bts_settrexqos_fbmbw(addr_u32 base, unsigned int priority)
|
||||
{
|
||||
Outp32(base + TBTS_CON, 0x0);
|
||||
Outp32(base + TBTS_RCON, 0x0);
|
||||
Outp32(base + TBTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + TBTS_DEMQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_DEFQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_PRMQOS, priority & 0xF);
|
||||
|
||||
Outp32(base + TBTS_RCON, 0x1); // Blocking on
|
||||
Outp32(base + TBTS_WCON, 0x1);
|
||||
Outp32(base + TBTS_CON, 0x1);
|
||||
}
|
||||
|
||||
void bts_trexdisable(addr_u32 base)
|
||||
{
|
||||
Outp32(base + TBTS_CON, 0x00010000);
|
||||
Outp32(base + TBTS_RCON, 0x0);
|
||||
Outp32(base + TBTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + TBTS_TKNUPBOUND, 0x5FFF);
|
||||
Outp32(base + TBTS_TKNLOBOUND, 0x1FFF);
|
||||
|
||||
Outp32(base + TBTS_DEMTH, 0x5FFF);
|
||||
Outp32(base + TBTS_PRMTH, 0x1FFF);
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS7420_EVT_0)
|
||||
Outp32(base + TBTS_DEMQOS, 0x9);
|
||||
Outp32(base + TBTS_DEFQOS, 0x4);
|
||||
Outp32(base + TBTS_PRMQOS, 0x2);
|
||||
#else
|
||||
Outp32(base + TBTS_DEMQOS, 0x2);
|
||||
Outp32(base + TBTS_DEFQOS, 0x4);
|
||||
Outp32(base + TBTS_PRMQOS, 0x9);
|
||||
#endif
|
||||
|
||||
Outp32(base + TBTS_QURGUPTH, 0x8);
|
||||
Outp32(base + TBTS_QURGDOWNTH, 0x8);
|
||||
Outp32(base + TBTS_RTKNINIT, 0x3FFF);
|
||||
Outp32(base + TBTS_WTKNINIT, 0x3FFF);
|
||||
Outp32(base + TBTS_RTKNDEC, 0x0);
|
||||
Outp32(base + TBTS_WTKNDEC, 0x0);
|
||||
}
|
||||
|
||||
void bts_setnsp(addr_u32 base, unsigned int nsp)
|
||||
{
|
||||
Outp32(base , nsp);
|
||||
}
|
||||
125
drivers/bts/cal_bts.h
Normal file
125
drivers/bts/cal_bts.h
Normal file
|
|
@ -0,0 +1,125 @@
|
|||
/* arch/arm/mach-exynos/cal_bts.h
|
||||
*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* EXYNOS - BTS CAL code.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __BTSCAL_H__
|
||||
#define __BTSCAL_H__
|
||||
|
||||
#if defined(CONFIG_EXYNOS7420_BTS)
|
||||
#include <linux/io.h>
|
||||
|
||||
#define Outp32(addr, data) (__raw_writel(data, addr))
|
||||
#define Inp32(addr) (__raw_readl(addr))
|
||||
typedef void __iomem *addr_u32;
|
||||
|
||||
#else
|
||||
typedef unsigned long u32;
|
||||
typedef unsigned long addr_u32;
|
||||
#define Outp32(addr, data) (*(volatile unsigned int *)(addr) = (data))
|
||||
#define Inp32(addr) (*(volatile unsigned int *)(addr))
|
||||
|
||||
#endif
|
||||
|
||||
/* for BTS V2.1 Register */
|
||||
#define BTS_RCON 0x100
|
||||
#define BTS_RMODE 0x104
|
||||
#define BTS_WCON 0x180
|
||||
#define BTS_WMODE 0x184
|
||||
#define BTS_PRIORITY 0x200
|
||||
#define BTS_TOKENMAX 0x204
|
||||
#define BTS_BWUPBOUND 0x20C
|
||||
#define BTS_BWLOBOUND 0x210
|
||||
#define BTS_INITTKN 0x214
|
||||
#define BTS_RSTCLK 0x218
|
||||
#define BTS_RSTTKN 0x21C
|
||||
#define BTS_DEMWIN 0x220
|
||||
#define BTS_DEMTKN 0x224
|
||||
#define BTS_DEFWIN 0x228
|
||||
#define BTS_DEFTKN 0x22C
|
||||
#define BTS_PRMWIN 0x230
|
||||
#define BTS_PRMTKN 0x234
|
||||
#define BTS_MOUPBOUND 0x240
|
||||
#define BTS_MOLOBOUND 0x244
|
||||
#define BTS_FLEXIBLE 0x280
|
||||
#define BTS_POLARITY 0x284
|
||||
#define BTS_FBMGRP0ADRS 0x290
|
||||
#define BTS_FBMGRP0ADRE 0x294
|
||||
#define BTS_FBMGRP1ADRS 0x298
|
||||
#define BTS_FBMGRP1ADRE 0x29C
|
||||
#define BTS_FBMGRP2ADRS 0x2A0
|
||||
#define BTS_FBMGRP2ADRE 0x2A4
|
||||
#define BTS_FBMGRP3ADRS 0x2A8
|
||||
#define BTS_FBMGRP3ADRE 0x2AC
|
||||
#define BTS_FBMGRP4ADRS 0x2B0
|
||||
#define BTS_FBMGRP4ADRE 0x2B4
|
||||
#define BTS_EMERGENTRID 0x2C0
|
||||
#define BTS_EMERGENTWID 0x3C0
|
||||
#define BTS_RISINGTH 0x2C4
|
||||
#define BTS_FALLINGTH 0x2C8
|
||||
#define BTS_FALLINGMO 0x2CC
|
||||
#define BTS_MOCOUNTER 0x2F0
|
||||
#define BTS_STATUS 0x2F4
|
||||
#define BTS_BWMONLOW 0x2F8
|
||||
#define BTS_BWMONUP 0x2FC
|
||||
|
||||
#define WOFFSET 0x100
|
||||
|
||||
/* for TREX_BTS Register */
|
||||
#define TBTS_CON 0x000
|
||||
#define TBTS_TKNUPBOUND 0x010
|
||||
#define TBTS_TKNLOBOUND 0x014
|
||||
#define TBTS_LOADUP 0x020
|
||||
#define TBTS_LOADDOWN 0x024
|
||||
#define TBTS_TKNINC0 0x040
|
||||
#define TBTS_TKNINC1 0x044
|
||||
#define TBTS_TKNINC2 0x048
|
||||
#define TBTS_TKNINC3 0x04C
|
||||
#define TBTS_TKNINC4 0x050
|
||||
#define TBTS_TKNINC5 0x054
|
||||
#define TBTS_TKNINC6 0x058
|
||||
#define TBTS_TKNINC7 0x05C
|
||||
#define TBTS_DEMTH 0x070
|
||||
#define TBTS_PRMTH 0x074
|
||||
#define TBTS_DEMQOS 0x080
|
||||
#define TBTS_DEFQOS 0x084
|
||||
#define TBTS_PRMQOS 0x088
|
||||
#define TBTS_TIMEOUT 0x090
|
||||
#define TBTS_QURGUPTH 0x0D0
|
||||
#define TBTS_QURGDOWNTH 0x0D4
|
||||
#define TBTS_SELIDMASK 0x0E0
|
||||
#define TBTS_SELIDVAL 0x0E4
|
||||
#define TBTS_RCON 0x100
|
||||
#define TBTS_RTKNINIT 0x110
|
||||
#define TBTS_RTKNDEC 0x120
|
||||
#define TBTS_WCON 0x200
|
||||
#define TBTS_WTKNINIT 0x210
|
||||
#define TBTS_WTKNDEC 0x220
|
||||
#define TBTS_EMERGENTID 0x2014
|
||||
#define TBTS_MASK 0x2010
|
||||
|
||||
#define MAX_MO_LIMIT 0x80
|
||||
|
||||
void bts_setqos(addr_u32 base, unsigned int priority);
|
||||
void bts_setqos_bw(addr_u32 base, unsigned int priority,
|
||||
unsigned int window, unsigned int token);
|
||||
void bts_setqos_mo(addr_u32 base, unsigned int priority,
|
||||
unsigned int rmo, unsigned int wmo);
|
||||
void bts_setqos_fbmbw(addr_u32 base, unsigned int priority, unsigned int window,
|
||||
unsigned int token, unsigned int fbm);
|
||||
void bts_disable(addr_u32 base);
|
||||
void bts_settrexqos(addr_u32 base, unsigned int priority);
|
||||
void bts_settrexqos_mo(addr_u32 base, unsigned int priority, unsigned int mo);
|
||||
void bts_settrexqos_bw(addr_u32 base, unsigned int priority, unsigned int decval);
|
||||
void bts_settrexqos_fbmbw(addr_u32 base, unsigned int priority);
|
||||
void bts_trexdisable(addr_u32 base);
|
||||
void bts_setnsp(addr_u32 base, unsigned int nsp);
|
||||
|
||||
#endif
|
||||
354
drivers/bts/cal_bts7570.c
Normal file
354
drivers/bts/cal_bts7570.c
Normal file
|
|
@ -0,0 +1,354 @@
|
|||
/* arch/arm/mach-exynos/cal_bts.c
|
||||
*
|
||||
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* EXYNOS - BTS CAL code.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "cal_bts7570.h"
|
||||
|
||||
#define LOG(x, ...) \
|
||||
({ \
|
||||
seq_printf(buf, x, ##__VA_ARGS__); \
|
||||
})
|
||||
|
||||
/* for BTS V2.1 Register */
|
||||
#define BTS_RCON 0x100
|
||||
#define BTS_RMODE 0x104
|
||||
#define BTS_WCON 0x180
|
||||
#define BTS_WMODE 0x184
|
||||
#define BTS_PRIORITY 0x200
|
||||
#define BTS_TOKENMAX 0x204
|
||||
#define BTS_BWUPBOUND 0x20C
|
||||
#define BTS_BWLOBOUND 0x210
|
||||
#define BTS_INITTKN 0x214
|
||||
#define BTS_RSTCLK 0x218
|
||||
#define BTS_RSTTKN 0x21C
|
||||
#define BTS_DEMWIN 0x220
|
||||
#define BTS_DEMTKN 0x224
|
||||
#define BTS_DEFWIN 0x228
|
||||
#define BTS_DEFTKN 0x22C
|
||||
#define BTS_PRMWIN 0x230
|
||||
#define BTS_PRMTKN 0x234
|
||||
#define BTS_MOUPBOUND 0x240
|
||||
#define BTS_MOLOBOUND 0x244
|
||||
#define BTS_FLEXIBLE 0x280
|
||||
#define BTS_POLARITY 0x284
|
||||
#define BTS_FBMGRP0ADRS 0x290
|
||||
#define BTS_FBMGRP0ADRE 0x294
|
||||
#define BTS_FBMGRP1ADRS 0x298
|
||||
#define BTS_FBMGRP1ADRE 0x29C
|
||||
#define BTS_FBMGRP2ADRS 0x2A0
|
||||
#define BTS_FBMGRP2ADRE 0x2A4
|
||||
#define BTS_FBMGRP3ADRS 0x2A8
|
||||
#define BTS_FBMGRP3ADRE 0x2AC
|
||||
#define BTS_FBMGRP4ADRS 0x2B0
|
||||
#define BTS_FBMGRP4ADRE 0x2B4
|
||||
#define BTS_EMERGENTID 0x2C0
|
||||
#define BTS_RISINGTH 0x2C4
|
||||
#define BTS_FALLINGTH 0x2C8
|
||||
#define BTS_FALLINGMO 0x2CC
|
||||
#define BTS_MOCOUNTER 0x2F0
|
||||
#define BTS_STATUS 0x2F4
|
||||
#define BTS_BWMONLOW 0x2F8
|
||||
#define BTS_BWMONUP 0x2FC
|
||||
#define WOFFSET 0x100
|
||||
|
||||
#define TREX_CON 0x000
|
||||
#define TREX_TIMEOUT 0x010
|
||||
#define TREX_BLOCK_IDMASK 0x018
|
||||
#define TREX_BLOCK_IDVALUE 0x01C
|
||||
#define TREX_RCON 0x020
|
||||
#define TREX_WCON 0x040
|
||||
#define TREX_RBLOCK_UPPER 0x024
|
||||
#define TREX_WBLOCK_UPPER 0x044
|
||||
#define TREX_RBLOCK_UPPER_NORMAL 0x028
|
||||
#define TREX_WBLOCK_UPPER_NORMAL 0x048
|
||||
#define TREX_RBLOCK_UPPER_FULL 0x02C
|
||||
#define TREX_WBLOCK_UPPER_FULL 0x04C
|
||||
#define TREX_RBLOCK_UPPER_BUSY 0x030
|
||||
#define TREX_WBLOCK_UPPER_BUSY 0x050
|
||||
#define TREX_RBLOCK_UPPER_MAX 0x034
|
||||
#define TREX_WBLOCK_UPPER_MAX 0x054
|
||||
#define SYSREG_CP_QOS 0x0078
|
||||
#define SYSREG_GNSS_QOS 0x00B8
|
||||
#define SYSREG_WIFI_QOS 0x0178
|
||||
#define SYSREG_APM_QOS 0x000C
|
||||
#define SYSREG_DISPAUD_QOS 0x0600
|
||||
#define SYSREG_DISPAUD_SEL 0x0604
|
||||
#define SYSREG_FSYS_VAL0 0x0600
|
||||
#define SYSREG_FSYS_VAL1 0x0604
|
||||
#define SYSREG_FSYS_VAL2 0x0608
|
||||
#define SYSREG_ISP_QOS 0x0500
|
||||
#define SYSREG_CPU_QOS 0x0610
|
||||
#define SYSREG_MFCMSCL_QOS 0x0600
|
||||
|
||||
|
||||
void bts_setqos(addr_u32 base, unsigned int priority) /* QOS : [RRRRWWWW] */
|
||||
{
|
||||
__raw_writel(0x0, base + BTS_RCON);
|
||||
__raw_writel(0x0, base + BTS_RCON);
|
||||
__raw_writel(0x0, base + BTS_WCON);
|
||||
__raw_writel(0x0, base + BTS_WCON);
|
||||
__raw_writel(((priority >> 16) & 0xFFFF), base + BTS_PRIORITY);
|
||||
__raw_writel(0xFFDF, base + BTS_TOKENMAX);
|
||||
__raw_writel(0x18, base + BTS_BWUPBOUND);
|
||||
__raw_writel(0x1, base + BTS_BWLOBOUND);
|
||||
__raw_writel(0x8, base + BTS_INITTKN);
|
||||
__raw_writel((priority & 0xFFFF), base + BTS_PRIORITY + WOFFSET);
|
||||
__raw_writel(0xFFDF, base + BTS_TOKENMAX + WOFFSET);
|
||||
__raw_writel(0x18, base + BTS_BWUPBOUND + WOFFSET);
|
||||
__raw_writel(0x1, base + BTS_BWLOBOUND + WOFFSET);
|
||||
__raw_writel(0x8, base + BTS_INITTKN + WOFFSET);
|
||||
__raw_writel(0x1, base + BTS_RCON);
|
||||
__raw_writel(0x1, base + BTS_WCON);
|
||||
}
|
||||
|
||||
void bts_setqos_bw(addr_u32 base, unsigned int priority,
|
||||
unsigned int window, unsigned int token) /* QOS : [RRRRWWWW] */
|
||||
{
|
||||
__raw_writel(0x0, base + BTS_RCON);
|
||||
__raw_writel(0x0, base + BTS_RCON);
|
||||
__raw_writel(0x0, base + BTS_WCON);
|
||||
__raw_writel(0x0, base + BTS_WCON);
|
||||
__raw_writel(((priority >> 16) & 0xFFFF), base + BTS_PRIORITY);
|
||||
__raw_writel(0xFFDF, base + BTS_TOKENMAX);
|
||||
__raw_writel(0x18, base + BTS_BWUPBOUND);
|
||||
__raw_writel(0x1, base + BTS_BWLOBOUND);
|
||||
__raw_writel(0x8, base + BTS_INITTKN);
|
||||
__raw_writel(window, base + BTS_DEMWIN);
|
||||
__raw_writel(token, base + BTS_DEMTKN);
|
||||
__raw_writel(window, base + BTS_DEFWIN);
|
||||
__raw_writel(token, base + BTS_DEFTKN);
|
||||
__raw_writel(window, base + BTS_PRMWIN);
|
||||
__raw_writel(token, base + BTS_PRMTKN);
|
||||
__raw_writel(0x0, base + BTS_FLEXIBLE);
|
||||
__raw_writel((priority & 0xFFFF), base + BTS_PRIORITY + WOFFSET);
|
||||
__raw_writel(0xFFDF, base + BTS_TOKENMAX + WOFFSET);
|
||||
__raw_writel(0x18, base + BTS_BWUPBOUND + WOFFSET);
|
||||
__raw_writel(0x1, base + BTS_BWLOBOUND + WOFFSET);
|
||||
__raw_writel(0x8, base + BTS_INITTKN + WOFFSET);
|
||||
__raw_writel(window, base + BTS_DEMWIN + WOFFSET);
|
||||
__raw_writel(token, base + BTS_DEMTKN + WOFFSET);
|
||||
__raw_writel(window, base + BTS_DEFWIN + WOFFSET);
|
||||
__raw_writel(token, base + BTS_DEFTKN + WOFFSET);
|
||||
__raw_writel(window, base + BTS_PRMWIN + WOFFSET);
|
||||
__raw_writel(token, base + BTS_PRMTKN + WOFFSET);
|
||||
__raw_writel(0x0, base + BTS_FLEXIBLE + WOFFSET);
|
||||
__raw_writel(0x1, base + BTS_RMODE);
|
||||
__raw_writel(0x1, base + BTS_WMODE);
|
||||
__raw_writel(0x3, base + BTS_RCON);
|
||||
__raw_writel(0x3, base + BTS_WCON);
|
||||
}
|
||||
|
||||
void bts_setqos_mo(addr_u32 base, unsigned int priority, unsigned int mo) /* QOS : [RRRRWWWW] */
|
||||
{
|
||||
__raw_writel(0x0, base + BTS_RCON);
|
||||
__raw_writel(0x0, base + BTS_RCON);
|
||||
__raw_writel(0x0, base + BTS_WCON);
|
||||
__raw_writel(0x0, base + BTS_WCON);
|
||||
__raw_writel(((priority >> 16) & 0xFFFF), base + BTS_PRIORITY);
|
||||
__raw_writel(0x7F - mo, base + BTS_MOUPBOUND);
|
||||
__raw_writel(mo, base + BTS_MOLOBOUND);
|
||||
__raw_writel(0x0, base + BTS_FLEXIBLE);
|
||||
__raw_writel((priority & 0xFFFF), base + BTS_PRIORITY + WOFFSET);
|
||||
__raw_writel(0x7F - mo, base + BTS_MOUPBOUND + WOFFSET);
|
||||
__raw_writel(mo, base + BTS_MOLOBOUND + WOFFSET);
|
||||
__raw_writel(0x0, base + BTS_FLEXIBLE + WOFFSET);
|
||||
__raw_writel(0x2, base + BTS_RMODE);
|
||||
__raw_writel(0x2, base + BTS_WMODE);
|
||||
__raw_writel(0x3, base + BTS_RCON);
|
||||
__raw_writel(0x3, base + BTS_WCON);
|
||||
}
|
||||
|
||||
void bts_showqos(addr_u32 base, struct seq_file *buf)
|
||||
{
|
||||
LOG("conreg 0x%Xr 0x%Xw qos 0x%Xr 0x%Xw\n",
|
||||
__raw_readl(base + BTS_RCON),
|
||||
__raw_readl(base + BTS_WCON),
|
||||
__raw_readl(base + BTS_PRIORITY),
|
||||
__raw_readl(base + BTS_PRIORITY + WOFFSET));
|
||||
}
|
||||
void bts_disable(addr_u32 base)
|
||||
{
|
||||
/* reset to default */
|
||||
__raw_writel(0x0, base + BTS_RCON);
|
||||
__raw_writel(0x0, base + BTS_RCON);
|
||||
__raw_writel(0x0, base + BTS_WCON);
|
||||
__raw_writel(0x0, base + BTS_WCON);
|
||||
__raw_writel(0x1, base + BTS_RMODE);
|
||||
__raw_writel(0x1, base + BTS_WMODE);
|
||||
__raw_writel(0xA942, base + BTS_PRIORITY);
|
||||
__raw_writel(0x0, base + BTS_TOKENMAX);
|
||||
__raw_writel(0x3FFF, base + BTS_BWUPBOUND);
|
||||
__raw_writel(0x3FFF, base + BTS_BWLOBOUND);
|
||||
__raw_writel(0x7FFF, base + BTS_INITTKN);
|
||||
__raw_writel(0x7FFF, base + BTS_DEMWIN);
|
||||
__raw_writel(0x1FFF, base + BTS_DEMTKN);
|
||||
__raw_writel(0x7FFF, base + BTS_DEFWIN);
|
||||
__raw_writel(0x1FFF, base + BTS_DEFTKN);
|
||||
__raw_writel(0x7FFF, base + BTS_PRMWIN);
|
||||
__raw_writel(0x1FFF, base + BTS_PRMTKN);
|
||||
__raw_writel(0x1F, base + BTS_MOUPBOUND);
|
||||
__raw_writel(0x1F, base + BTS_MOLOBOUND);
|
||||
__raw_writel(0x0, base + BTS_FLEXIBLE);
|
||||
__raw_writel(0xA942, base + BTS_PRIORITY + WOFFSET);
|
||||
__raw_writel(0x0, base + BTS_TOKENMAX + WOFFSET);
|
||||
__raw_writel(0x3FFF, base + BTS_BWUPBOUND + WOFFSET);
|
||||
__raw_writel(0x3FFF, base + BTS_BWLOBOUND + WOFFSET);
|
||||
__raw_writel(0x7FFF, base + BTS_INITTKN + WOFFSET);
|
||||
__raw_writel(0x7FFF, base + BTS_DEMWIN + WOFFSET);
|
||||
__raw_writel(0x1FFF, base + BTS_DEMTKN + WOFFSET);
|
||||
__raw_writel(0x7FFF, base + BTS_DEFWIN + WOFFSET);
|
||||
__raw_writel(0x1FFF, base + BTS_DEFTKN + WOFFSET);
|
||||
__raw_writel(0x7FFF, base + BTS_PRMWIN + WOFFSET);
|
||||
__raw_writel(0x1FFF, base + BTS_PRMTKN + WOFFSET);
|
||||
__raw_writel(0x1F, base + BTS_MOUPBOUND + WOFFSET);
|
||||
__raw_writel(0x1F, base + BTS_MOLOBOUND + WOFFSET);
|
||||
__raw_writel(0x0, base + BTS_FLEXIBLE + WOFFSET);
|
||||
}
|
||||
|
||||
void trex_setqos(addr_u32 base, unsigned int priority)
|
||||
{
|
||||
unsigned int tmp_reg = 0;
|
||||
/* override QoS value */
|
||||
tmp_reg |= 1 << 8;
|
||||
tmp_reg |= (priority & 0xf) << 12;
|
||||
__raw_writel(tmp_reg, base + TREX_RCON);
|
||||
__raw_writel(tmp_reg, base + TREX_WCON);
|
||||
|
||||
__raw_writel(0x1, base + TREX_CON);
|
||||
}
|
||||
|
||||
void trex_setqos_mo(addr_u32 base, unsigned int priority, unsigned int mo)
|
||||
{
|
||||
unsigned int tmp_reg = 0;
|
||||
if (mo > 0xffff)
|
||||
mo = 0xffff;
|
||||
__raw_writel(mo, base + TREX_RBLOCK_UPPER);
|
||||
__raw_writel(mo, base + TREX_WBLOCK_UPPER);
|
||||
/* override QoS value */
|
||||
tmp_reg |= 1 << 8;
|
||||
tmp_reg |= (priority & 0xf) << 12;
|
||||
/* enable Blocking logic */
|
||||
tmp_reg |= 1 << 0;
|
||||
__raw_writel(tmp_reg, base + TREX_RCON);
|
||||
__raw_writel(tmp_reg, base + TREX_WCON);
|
||||
__raw_writel(0x1, base + TREX_CON);
|
||||
}
|
||||
|
||||
void trex_showqos(addr_u32 base, struct seq_file *buf)
|
||||
{
|
||||
LOG("conreg 0x%X qos(%d,%d) 0x%Xr 0x%Xw mo(%d,%d) %dr %dw\n",
|
||||
__raw_readl(base + TREX_CON),
|
||||
(__raw_readl(base + TREX_RCON) >> 8) & 0x1,
|
||||
(__raw_readl(base + TREX_WCON) >> 8) & 0x1,
|
||||
(__raw_readl(base + TREX_RCON) >> 12) & 0xf,
|
||||
(__raw_readl(base + TREX_WCON) >> 12) & 0xf,
|
||||
__raw_readl(base + TREX_RCON) & 0x1,
|
||||
__raw_readl(base + TREX_WCON) & 0x1,
|
||||
__raw_readl(base + TREX_RBLOCK_UPPER),
|
||||
__raw_readl(base + TREX_WBLOCK_UPPER));
|
||||
}
|
||||
void trex_disable(addr_u32 base)
|
||||
{
|
||||
__raw_writel(0x0, base + TREX_CON);
|
||||
__raw_writel(0x4000, base + TREX_RCON);
|
||||
__raw_writel(0x4000, base + TREX_WCON);
|
||||
}
|
||||
|
||||
void sysreg_setqos(QOS_SYSREG_IP qos_id, addr_u32 base, unsigned int priority)
|
||||
{
|
||||
unsigned int tmp_reg;
|
||||
switch (qos_id) {
|
||||
case BTS_SYSREG_CPGNSS:
|
||||
tmp_reg = __raw_readl(base + SYSREG_CP_QOS);
|
||||
tmp_reg |= 1;
|
||||
__raw_writel(tmp_reg, base + SYSREG_CP_QOS);
|
||||
tmp_reg = __raw_readl(base + SYSREG_GNSS_QOS);
|
||||
tmp_reg &= ~1;
|
||||
tmp_reg &= ~((0xf << 12) | (0xf << 16));
|
||||
tmp_reg |= (priority & 0xf) << 8;
|
||||
tmp_reg |= (priority & 0xf) << 16;
|
||||
__raw_writel(tmp_reg, base + SYSREG_GNSS_QOS);
|
||||
break;
|
||||
case BTS_SYSREG_APM:
|
||||
tmp_reg = __raw_readl(base + SYSREG_APM_QOS);
|
||||
tmp_reg &= ~(0xf | (0xf << 4));
|
||||
tmp_reg |= (priority & 0xf);
|
||||
tmp_reg |= (priority & 0xf) << 4;
|
||||
__raw_writel(tmp_reg, base + SYSREG_APM_QOS);
|
||||
break;
|
||||
case BTS_SYSREG_CPU:
|
||||
tmp_reg = __raw_readl(base + SYSREG_CPU_QOS);
|
||||
tmp_reg &= ~(0xf | (0xf << 4));
|
||||
tmp_reg |= (priority & 0xf);
|
||||
tmp_reg |= (priority & 0xf) << 4;
|
||||
__raw_writel(tmp_reg, base + SYSREG_CPU_QOS);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
void sysreg_disable(QOS_SYSREG_IP qos_id, addr_u32 base)
|
||||
{
|
||||
unsigned int tmp_reg;
|
||||
switch (qos_id) {
|
||||
case BTS_SYSREG_CPGNSS:
|
||||
tmp_reg = __raw_readl(base + SYSREG_CP_QOS);
|
||||
tmp_reg |= 1;
|
||||
__raw_writel(tmp_reg, base + SYSREG_CP_QOS);
|
||||
tmp_reg = __raw_readl(base + SYSREG_GNSS_QOS);
|
||||
tmp_reg |= 1;
|
||||
tmp_reg |= (0x4) << 8;
|
||||
tmp_reg |= (0x4) << 16;
|
||||
__raw_writel(tmp_reg, base + SYSREG_GNSS_QOS);
|
||||
break;
|
||||
case BTS_SYSREG_APM:
|
||||
tmp_reg = __raw_readl(base + SYSREG_APM_QOS);
|
||||
tmp_reg &= ~(0xf | (0xf << 4));
|
||||
tmp_reg |= 0x4;
|
||||
tmp_reg |= 0x4 << 4;
|
||||
__raw_writel(tmp_reg, base + SYSREG_APM_QOS);
|
||||
break;
|
||||
case BTS_SYSREG_CPU:
|
||||
tmp_reg = __raw_readl(base + SYSREG_CPU_QOS);
|
||||
tmp_reg &= ~(0xf | (0xf << 4));
|
||||
tmp_reg |= 0x4;
|
||||
tmp_reg |= 0x4 << 4;
|
||||
__raw_writel(tmp_reg, base + SYSREG_CPU_QOS);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void sysreg_showqos(QOS_SYSREG_IP qos_id, addr_u32 base, struct seq_file *buf)
|
||||
{
|
||||
unsigned int tmp_reg;
|
||||
switch (qos_id) {
|
||||
case BTS_SYSREG_CPGNSS:
|
||||
tmp_reg = __raw_readl(base + SYSREG_GNSS_QOS);
|
||||
LOG("(cp bypass %d)bypass %u qos 0x%Xr 0x%Xw\n",
|
||||
__raw_readl(base + SYSREG_CP_QOS) && 0x1,
|
||||
tmp_reg & 1, (tmp_reg >> 8) & 0xf, (tmp_reg >> 16) & 0xf);
|
||||
break;
|
||||
case BTS_SYSREG_APM:
|
||||
tmp_reg = __raw_readl(base + SYSREG_APM_QOS);
|
||||
LOG("qos 0x%Xr 0x%Xw\n", tmp_reg & 0xf,
|
||||
(tmp_reg >> 4) & 0xf);
|
||||
break;
|
||||
case BTS_SYSREG_CPU:
|
||||
tmp_reg = __raw_readl(base + SYSREG_CPU_QOS);
|
||||
LOG("qos 0x%Xr 0x%Xw\n", tmp_reg & 0xf,
|
||||
(tmp_reg >> 4) & 0xf);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
83
drivers/bts/cal_bts7570.h
Normal file
83
drivers/bts/cal_bts7570.h
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
/* arch/arm/mach-exynos/cal_bts.h
|
||||
*
|
||||
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* EXYNOS - BTS CAL code.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __BTSCAL_H__
|
||||
#define __BTSCAL_H__
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/debugfs.h>
|
||||
/* for BTS Through SYSTEM Register */
|
||||
typedef enum {
|
||||
BTS_SYSREG_CPU = 1,
|
||||
BTS_SYSREG_APM,
|
||||
BTS_SYSREG_CPGNSS,
|
||||
} QOS_SYSREG_IP;
|
||||
|
||||
typedef void __iomem *addr_u32;
|
||||
|
||||
void trex_setqos(addr_u32 base, unsigned int priority);
|
||||
void trex_setqos_mo(addr_u32 base, unsigned int priority, unsigned int mo);
|
||||
void trex_disable(addr_u32 base);
|
||||
void trex_showqos(addr_u32 base, struct seq_file *buf);
|
||||
void sysreg_setqos(QOS_SYSREG_IP qos_id, addr_u32 base,
|
||||
unsigned int priority);
|
||||
void sysreg_disable(QOS_SYSREG_IP qos_id, addr_u32 base);
|
||||
void sysreg_showqos(QOS_SYSREG_IP qos_id, addr_u32 base, struct seq_file *buf);
|
||||
|
||||
void bts_setqos(addr_u32 base, unsigned int priority);
|
||||
void bts_setqos_bw(addr_u32 base, unsigned int priority,
|
||||
unsigned int window, unsigned int token);
|
||||
void bts_setqos_mo(addr_u32 base, unsigned int priority, unsigned int mo);
|
||||
void bts_disable(addr_u32 base);
|
||||
void bts_showqos(addr_u32 base, struct seq_file *buf);
|
||||
|
||||
#define EXYNOS7570_PA_BTS_CPU 0x104D0000
|
||||
|
||||
#define EXYNOS7570_PA_TREX_MFCMSCL 0x12420000
|
||||
#define EXYNOS7570_PA_TREX_G3D 0x12430000
|
||||
#define EXYNOS7570_PA_TREX_FSYS 0x12440000
|
||||
#define EXYNOS7570_PA_TREX_ISP 0x12450000
|
||||
#define EXYNOS7570_PA_TREX_DISPAUD 0x12460000
|
||||
#define EXYNOS7570_PA_TREX_CELLULAR 0x12480000
|
||||
#define EXYNOS7570_PA_TREX_WLBT 0x12490000
|
||||
|
||||
#define EXYNOS7570_PA_TREX_SLAVE_CP 0x124B0000
|
||||
#define EXYNOS7570_PA_TREX_SLAVE_MM 0x124C0000
|
||||
|
||||
#define EXYNOS7570_PA_SYSREG_CP 0x11C80000
|
||||
#define EXYNOS7570_PA_SYSREG_APM 0x11C50000
|
||||
#define EXYNOS7570_PA_SYSREG_DISPAUD 0x148F0000
|
||||
#define EXYNOS7570_PA_SYSREG_FSYS 0x13720000
|
||||
#define EXYNOS7570_PA_SYSREG_ISP 0x144F0000
|
||||
#define EXYNOS7570_PA_SYSREG_CPU 0x10450000
|
||||
#define EXYNOS7570_PA_SYSREG_MFCMSCL 0x12CA0000
|
||||
|
||||
#define EXYNOS7570_PA_DREX 0x10400000
|
||||
|
||||
#define QOS_TIMEOUT_0x0 0x300
|
||||
#define QOS_TIMEOUT_0x1 0x304
|
||||
#define QOS_TIMEOUT_0x2 0x308
|
||||
#define QOS_TIMEOUT_0x3 0x30c
|
||||
#define QOS_TIMEOUT_0x4 0x310
|
||||
#define QOS_TIMEOUT_0x5 0x314
|
||||
#define QOS_TIMEOUT_0x6 0x318
|
||||
#define QOS_TIMEOUT_0x7 0x31c
|
||||
#define QOS_TIMEOUT_0x8 0x320
|
||||
#define QOS_TIMEOUT_0x9 0x324
|
||||
#define QOS_TIMEOUT_0xA 0x328
|
||||
#define QOS_TIMEOUT_0xB 0x32C
|
||||
#define QOS_TIMEOUT_0xC 0x330
|
||||
#define QOS_TIMEOUT_0xD 0x334
|
||||
#define QOS_TIMEOUT_0xE 0x338
|
||||
#define QOS_TIMEOUT_0xF 0x33c
|
||||
|
||||
#endif
|
||||
209
drivers/bts/cal_bts7870.c
Normal file
209
drivers/bts/cal_bts7870.c
Normal file
|
|
@ -0,0 +1,209 @@
|
|||
/* arch/arm/mach-exynos/cal_bts.c
|
||||
*
|
||||
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* EXYNOS - BTS CAL code.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "cal_bts7870.h"
|
||||
|
||||
#define QOS_AUD 0x4
|
||||
#define QOS_JPEG 0x4
|
||||
#define QOS_MSCL 0x4
|
||||
|
||||
void bts_setotf_sysreg(BWL_SYSREG_RT_NRT_SEL path_sel, addr_u32 base, bool enable)
|
||||
{
|
||||
unsigned int tmp_reg;
|
||||
|
||||
tmp_reg = Inp32(base + ISP_USER_CON);
|
||||
|
||||
if (enable)
|
||||
Outp32(base + ISP_USER_CON, tmp_reg | (0x1 << path_sel));
|
||||
else
|
||||
Outp32(base + ISP_USER_CON, tmp_reg & ~(0x1 << path_sel));
|
||||
}
|
||||
|
||||
void bts_setmo_sysreg(BWL_MO_SYSREG_IP mo_id, addr_u32 base, unsigned int ar,
|
||||
unsigned int aw)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
void bts_setqos_sysreg(BWL_QOS_SYSREG_IP qos_id, addr_u32 base, unsigned int *priority)
|
||||
{
|
||||
unsigned int tmp_reg;
|
||||
|
||||
switch (qos_id) {
|
||||
case BTS_SYSREG_DISPAUD:
|
||||
tmp_reg = Inp32(base + DISPAUD_QOS_CON);
|
||||
tmp_reg &= ~((0xf << 20) | (0xf << 16) | (0xf << 8) | (0xf << 4) | 0xf);
|
||||
Outp32(base + DISPAUD_QOS_CON, tmp_reg | (QOS_AUD << 20) |
|
||||
(QOS_AUD << 16) | (priority[0] << 8) | (priority[0] << 4) |
|
||||
(priority[0]));
|
||||
break;
|
||||
case BTS_SYSREG_ISP0:
|
||||
tmp_reg = Inp32(base + ISP_QOS_CON0);
|
||||
tmp_reg &= ~((0xf << 8) | (0xf << 4) | 0xf);
|
||||
Outp32(base + ISP_QOS_CON0, tmp_reg | (priority[0] << 8) | (priority[0] << 4) | (priority[0]));
|
||||
break;
|
||||
case BTS_SYSREG_ISP1:
|
||||
Outp32(base + ISP_QOS_CON1, (priority[0] << 28) | (priority[0] << 24) |
|
||||
(priority[0] << 20) | (priority[0] << 16) | (priority[0] << 12) |
|
||||
(priority[0] << 8) | (priority[0] << 4) | (priority[0]));
|
||||
break;
|
||||
case BTS_SYSREG_MIF_MODAPIF_CP:
|
||||
/* CP Qos select : 0x0(SYSREG QOS), 0x1(CP QOS) */
|
||||
Outp32(base + PMUALIVE_MODAPIF_CP_QOS_CON, (priority[0] << 16)|(priority[0] << 8) | CP_QOS_OVERRIDE);
|
||||
break;
|
||||
case BTS_SYSREG_MIF_MODAPIF_GNSS:
|
||||
/* GNSS Qos select : 0x0(SYSREG QOS), 0x1(GNSS QOS) */
|
||||
Outp32(base + PMUALIVE_MODAPIF_GNSS_QOS_CON, (priority[0] << 16)|(priority[0] << 8) | GNSS_QOS_OVERRIDE);
|
||||
break;
|
||||
case BTS_SYSREG_MFCMSCL:
|
||||
Outp32(base + MFCMSCL_QOS_CON, (priority[0] << 28) | (priority[0] << 24) |
|
||||
(QOS_JPEG << 20) | (QOS_JPEG << 16) | (QOS_MSCL << 12) |
|
||||
(QOS_MSCL << 8) | (QOS_MSCL << 4) | QOS_MSCL);
|
||||
break;
|
||||
case BTS_SYSREG_MIF_CPU:
|
||||
Outp32(base + MIF_CPU_QOS_CON, (priority[0] << 4) | (priority[0]));
|
||||
break;
|
||||
case BTS_SYSREG_MIF_APL:
|
||||
Outp32(base + MIF_APL_QOS_CON, (priority[0] << 4) | (priority[0]));
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void bts_setqos(addr_u32 base, unsigned int priority) /* QOS : [RRRRWWWW] */
|
||||
{
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY, ((priority >> 16) & 0xFFFF));
|
||||
Outp32(base + BTS_TOKENMAX, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND, 0x1);
|
||||
Outp32(base + BTS_INITTKN, 0x8);
|
||||
|
||||
Outp32(base + BTS_PRIORITY + WOFFSET, (priority & 0xFFFF));
|
||||
Outp32(base + BTS_TOKENMAX + WOFFSET, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND + WOFFSET, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND + WOFFSET, 0x1);
|
||||
Outp32(base + BTS_INITTKN + WOFFSET, 0x8);
|
||||
|
||||
Outp32(base + BTS_RCON, 0x1);
|
||||
Outp32(base + BTS_WCON, 0x1);
|
||||
}
|
||||
|
||||
void bts_setqos_bw(addr_u32 base, unsigned int priority,
|
||||
unsigned int window, unsigned int token) /* QOS : [RRRRWWWW] */
|
||||
{
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY, ((priority >> 16) & 0xFFFF));
|
||||
Outp32(base + BTS_TOKENMAX, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND, 0x1);
|
||||
Outp32(base + BTS_INITTKN, 0x8);
|
||||
Outp32(base + BTS_DEMWIN, window);
|
||||
Outp32(base + BTS_DEMTKN, token);
|
||||
Outp32(base + BTS_DEFWIN, window);
|
||||
Outp32(base + BTS_DEFTKN, token);
|
||||
Outp32(base + BTS_PRMWIN, window);
|
||||
Outp32(base + BTS_PRMTKN, token);
|
||||
Outp32(base + BTS_FLEXIBLE, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY + WOFFSET, (priority & 0xFFFF));
|
||||
Outp32(base + BTS_TOKENMAX + WOFFSET, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND + WOFFSET, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND + WOFFSET, 0x1);
|
||||
Outp32(base + BTS_INITTKN + WOFFSET, 0x8);
|
||||
Outp32(base + BTS_DEMWIN + WOFFSET, window);
|
||||
Outp32(base + BTS_DEMTKN + WOFFSET, token);
|
||||
Outp32(base + BTS_DEFWIN + WOFFSET, window);
|
||||
Outp32(base + BTS_DEFTKN + WOFFSET, token);
|
||||
Outp32(base + BTS_PRMWIN + WOFFSET, window);
|
||||
Outp32(base + BTS_PRMTKN + WOFFSET, token);
|
||||
Outp32(base + BTS_FLEXIBLE + WOFFSET, 0x0);
|
||||
|
||||
Outp32(base + BTS_RMODE, 0x1);
|
||||
Outp32(base + BTS_WMODE, 0x1);
|
||||
Outp32(base + BTS_RCON, 0x3);
|
||||
Outp32(base + BTS_WCON, 0x3);
|
||||
}
|
||||
|
||||
void bts_setqos_mo(addr_u32 base, unsigned int priority, unsigned int mo) /* QOS : [RRRRWWWW] */
|
||||
{
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY, ((priority >> 16) & 0xFFFF));
|
||||
Outp32(base + BTS_MOUPBOUND, 0x7F - mo);
|
||||
Outp32(base + BTS_MOLOBOUND, mo);
|
||||
Outp32(base + BTS_FLEXIBLE, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY + WOFFSET, (priority & 0xFFFF));
|
||||
Outp32(base + BTS_MOUPBOUND + WOFFSET, 0x7F - mo);
|
||||
Outp32(base + BTS_MOLOBOUND + WOFFSET, mo);
|
||||
Outp32(base + BTS_FLEXIBLE + WOFFSET, 0x0);
|
||||
|
||||
Outp32(base + BTS_RMODE, 0x2);
|
||||
Outp32(base + BTS_WMODE, 0x2);
|
||||
Outp32(base + BTS_RCON, 0x3);
|
||||
Outp32(base + BTS_WCON, 0x3);
|
||||
}
|
||||
|
||||
void bts_disable(addr_u32 base)
|
||||
{
|
||||
/* reset to default */
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + BTS_RMODE, 0x1);
|
||||
Outp32(base + BTS_WMODE, 0x1);
|
||||
|
||||
Outp32(base + BTS_PRIORITY, 0xA942);
|
||||
Outp32(base + BTS_TOKENMAX, 0x0);
|
||||
Outp32(base + BTS_BWUPBOUND, 0x3FFF);
|
||||
Outp32(base + BTS_BWLOBOUND, 0x3FFF);
|
||||
Outp32(base + BTS_INITTKN, 0x7FFF);
|
||||
Outp32(base + BTS_DEMWIN, 0x7FFF);
|
||||
Outp32(base + BTS_DEMTKN, 0x1FFF);
|
||||
Outp32(base + BTS_DEFWIN, 0x7FFF);
|
||||
Outp32(base + BTS_DEFTKN, 0x1FFF);
|
||||
Outp32(base + BTS_PRMWIN, 0x7FFF);
|
||||
Outp32(base + BTS_PRMTKN, 0x1FFF);
|
||||
Outp32(base + BTS_MOUPBOUND, 0x1F);
|
||||
Outp32(base + BTS_MOLOBOUND, 0x1F);
|
||||
Outp32(base + BTS_FLEXIBLE, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY + WOFFSET, 0xA942);
|
||||
Outp32(base + BTS_TOKENMAX + WOFFSET, 0x0);
|
||||
Outp32(base + BTS_BWUPBOUND + WOFFSET, 0x3FFF);
|
||||
Outp32(base + BTS_BWLOBOUND + WOFFSET, 0x3FFF);
|
||||
Outp32(base + BTS_INITTKN + WOFFSET, 0x7FFF);
|
||||
Outp32(base + BTS_DEMWIN + WOFFSET, 0x7FFF);
|
||||
Outp32(base + BTS_DEMTKN + WOFFSET, 0x1FFF);
|
||||
Outp32(base + BTS_DEFWIN + WOFFSET, 0x7FFF);
|
||||
Outp32(base + BTS_DEFTKN + WOFFSET, 0x1FFF);
|
||||
Outp32(base + BTS_PRMWIN + WOFFSET, 0x7FFF);
|
||||
Outp32(base + BTS_PRMTKN + WOFFSET, 0x1FFF);
|
||||
Outp32(base + BTS_MOUPBOUND + WOFFSET, 0x1F);
|
||||
Outp32(base + BTS_MOLOBOUND + WOFFSET, 0x1F);
|
||||
Outp32(base + BTS_FLEXIBLE + WOFFSET, 0x0);
|
||||
}
|
||||
157
drivers/bts/cal_bts7870.h
Normal file
157
drivers/bts/cal_bts7870.h
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/* arch/arm/mach-exynos/cal_bts.h
|
||||
*
|
||||
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* EXYNOS - BTS CAL code.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __BTSCAL_H__
|
||||
#define __BTSCAL_H__
|
||||
|
||||
#if defined(CONFIG_EXYNOS7870_BTS)
|
||||
|
||||
#include <linux/io.h>
|
||||
|
||||
#define Outp32(addr, data) (__raw_writel(data, addr))
|
||||
#define Inp32(addr) (__raw_readl(addr))
|
||||
typedef void __iomem *addr_u32;
|
||||
|
||||
#else
|
||||
|
||||
typedef unsigned long u32;
|
||||
typedef unsigned long addr_u32;
|
||||
#define Outp32(addr, data) (*(unsigned int *)(addr) = (data))
|
||||
#define Inp32(addr) (*(unsigned int *)(addr))
|
||||
|
||||
#endif
|
||||
|
||||
/* for ISP RT/NRT Path Setting Through SYSTEM Register */
|
||||
typedef enum {
|
||||
BTS_SYSREG_ISP_VRA_SEL = 0x0,
|
||||
BTS_SYSREG_ISP_ISP_SCL_SEL
|
||||
} BWL_SYSREG_RT_NRT_SEL;
|
||||
|
||||
/* for BTS Through SYSTEM Register */
|
||||
typedef enum {
|
||||
BTS_SYSREG_DISPAUD, /* AUD,DECON_INT2,DECON_INT1, DECON_INT0 */
|
||||
BTS_SYSREG_FSYS0, /* FSYS_PDMA1, PDMA0, FSYS_USB20DRD */
|
||||
BTS_SYSREG_FSYS1, /* FSYS_MMC2, FSYS_MMC1, FSYS_MMC0 */
|
||||
BTS_SYSREG_FSYS2, /* UFS, RTIC, SSS_MDMA, SSS */
|
||||
BTS_SYSREG_ISP0, /* SCALER, VRA */
|
||||
BTS_SYSREG_ISP1, /* CSIS0, CSIS1, BNS, TAA, ISP */
|
||||
BTS_SYSREG_MIF_MODAPIF_CP,
|
||||
BTS_SYSREG_MIF_MODAPIF_GNSS,
|
||||
BTS_SYSREG_MIF_CPU,
|
||||
BTS_SYSREG_MIF_APL,
|
||||
BTS_SYSREG_MFCMSCL,
|
||||
BTS_SYSREG_TOTAL_NUM
|
||||
} BWL_QOS_SYSREG_IP;
|
||||
|
||||
typedef enum {
|
||||
BTS_DISP_M0,
|
||||
BTS_DISP_S2,
|
||||
BTS_DISP_S1,
|
||||
BTS_DISP_S0,
|
||||
BTS_ISP1_M0,
|
||||
BTS_ISP1_S2,
|
||||
BTS_ISP1_S1,
|
||||
BTS_ISP1_S0,
|
||||
BTS_MSCL_M0,
|
||||
BTS_JPEG_S0,
|
||||
BTS_MSCALER0_S1,
|
||||
BTS_MSCALER1_S2,
|
||||
BTS_MO_SYSREG_TOTAL_NUM
|
||||
} BWL_MO_SYSREG_IP;
|
||||
|
||||
/* SYSREG offsets */
|
||||
#define DISPAUD_QOS_CON 0x600
|
||||
#define DISP_QOS_SEL 0x604
|
||||
#define DISP_XIU_DISP1_AR_AC_TARGET_CON 0x1014
|
||||
|
||||
#define ISP_QOS_CON0 0x500
|
||||
#define ISP_QOS_CON1 0x600
|
||||
#define ISP_USER_CON 0x1000
|
||||
#define ISP_XIU_ISP1_AR_AC_TARGET_CON 0x1034
|
||||
#define ISP_XIU_ISP1_AW_AC_TARGET_CON 0x1038
|
||||
|
||||
#define MFCMSCL_QOS_CON 0x600
|
||||
#define MFCMSCL_XIU_MSCL0DX_M0 0x1000
|
||||
#define MFCMSCL_XIU_MSCL0DX_S0 0x1004
|
||||
#define MFCMSCL_XIU_MSCL0DX_S1 0x1008
|
||||
#define MFCMSCL_XIU_MSCL0DX_S2 0x100C
|
||||
|
||||
#define AUD_QOS_CON 0x600
|
||||
|
||||
#define FSYS_QOS_CON0 0x600
|
||||
#define FSYS_QOS_CON1 0x604
|
||||
#define FSYS_QOS_CON2 0x608
|
||||
|
||||
#define PMUALIVE_MODAPIF_CP_QOS_CON 0x078 /* csj */
|
||||
#define PMUALIVE_MODAPIF_GNSS_QOS_CON 0x0B8 /* csj */
|
||||
#define MIF_CPU_QOS_CON 0x608 /* csj */
|
||||
#define MIF_APL_QOS_CON 0x60C /* csj */
|
||||
|
||||
#define CP_QOS_OVERRIDE 0x1
|
||||
#define GNSS_QOS_OVERRIDE 0x1
|
||||
|
||||
/* for BTS V2.1 Register */
|
||||
#define BTS_RCON 0x100
|
||||
#define BTS_RMODE 0x104
|
||||
#define BTS_WCON 0x180
|
||||
#define BTS_WMODE 0x184
|
||||
#define BTS_PRIORITY 0x200
|
||||
#define BTS_TOKENMAX 0x204
|
||||
#define BTS_BWUPBOUND 0x20C
|
||||
#define BTS_BWLOBOUND 0x210
|
||||
#define BTS_INITTKN 0x214
|
||||
#define BTS_RSTCLK 0x218
|
||||
#define BTS_RSTTKN 0x21C
|
||||
#define BTS_DEMWIN 0x220
|
||||
#define BTS_DEMTKN 0x224
|
||||
#define BTS_DEFWIN 0x228
|
||||
#define BTS_DEFTKN 0x22C
|
||||
#define BTS_PRMWIN 0x230
|
||||
#define BTS_PRMTKN 0x234
|
||||
#define BTS_MOUPBOUND 0x240
|
||||
#define BTS_MOLOBOUND 0x244
|
||||
#define BTS_FLEXIBLE 0x280
|
||||
#define BTS_POLARITY 0x284
|
||||
#define BTS_FBMGRP0ADRS 0x290
|
||||
#define BTS_FBMGRP0ADRE 0x294
|
||||
#define BTS_FBMGRP1ADRS 0x298
|
||||
#define BTS_FBMGRP1ADRE 0x29C
|
||||
#define BTS_FBMGRP2ADRS 0x2A0
|
||||
#define BTS_FBMGRP2ADRE 0x2A4
|
||||
#define BTS_FBMGRP3ADRS 0x2A8
|
||||
#define BTS_FBMGRP3ADRE 0x2AC
|
||||
#define BTS_FBMGRP4ADRS 0x2B0
|
||||
#define BTS_FBMGRP4ADRE 0x2B4
|
||||
#define BTS_EMERGENTID 0x2C0
|
||||
#define BTS_RISINGTH 0x2C4
|
||||
#define BTS_FALLINGTH 0x2C8
|
||||
#define BTS_FALLINGMO 0x2CC
|
||||
#define BTS_MOCOUNTER 0x2F0
|
||||
#define BTS_STATUS 0x2F4
|
||||
#define BTS_BWMONLOW 0x2F8
|
||||
#define BTS_BWMONUP 0x2FC
|
||||
|
||||
#define WOFFSET 0x100
|
||||
|
||||
void bts_setotf_sysreg(BWL_SYSREG_RT_NRT_SEL path_sel, addr_u32 base,
|
||||
bool enable);
|
||||
void bts_setmo_sysreg(BWL_MO_SYSREG_IP mo_id, addr_u32 base,
|
||||
unsigned int ar, unsigned int aw);
|
||||
void bts_setqos_sysreg(BWL_QOS_SYSREG_IP qos_id, addr_u32 base,
|
||||
unsigned int *priority);
|
||||
void bts_setqos(addr_u32 base, unsigned int priority);
|
||||
void bts_setqos_bw(addr_u32 base, unsigned int priority,
|
||||
unsigned int window, unsigned int token);
|
||||
void bts_setqos_mo(addr_u32 base, unsigned int priority, unsigned int mo);
|
||||
void bts_disable(addr_u32 base);
|
||||
|
||||
#endif
|
||||
354
drivers/bts/cal_bts8890.c
Normal file
354
drivers/bts/cal_bts8890.c
Normal file
|
|
@ -0,0 +1,354 @@
|
|||
/* arch/arm/mach-exynos/cal_bts.c
|
||||
*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* EXYNOS - BTS CAL code.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "cal_bts8890.h"
|
||||
|
||||
void bts_setqos(addr_u32 base, unsigned int priority, unsigned int master_id) //QOS : [RRRRWWWW]
|
||||
{
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY, ((priority >> 16) & 0xFFFF));
|
||||
Outp32(base + BTS_TOKENMAX, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND, 0x1);
|
||||
Outp32(base + BTS_INITTKN, 0x8);
|
||||
|
||||
Outp32(base + BTS_PRIORITY + WOFFSET, (priority & 0xFFFF));
|
||||
Outp32(base + BTS_TOKENMAX + WOFFSET, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND + WOFFSET, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND + WOFFSET, 0x1);
|
||||
Outp32(base + BTS_INITTKN + WOFFSET, 0x8);
|
||||
|
||||
Outp32(base + BTS_EMERGENTRID, master_id);
|
||||
Outp32(base + BTS_EMERGENTWID, master_id);
|
||||
Outp32(base + BTS_RCON, 0x1);
|
||||
Outp32(base + BTS_WCON, 0x1);
|
||||
}
|
||||
|
||||
void bts_setqos_bw(addr_u32 base, unsigned int priority,
|
||||
unsigned int window, unsigned int token, unsigned int master_id) //QOS : [RRRRWWWW]
|
||||
{
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY, ((priority >> 16) & 0xFFFF));
|
||||
Outp32(base + BTS_TOKENMAX, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND, 0x1);
|
||||
Outp32(base + BTS_INITTKN, 0x8);
|
||||
Outp32(base + BTS_DEMWIN, window);
|
||||
Outp32(base + BTS_DEMTKN, token);
|
||||
Outp32(base + BTS_DEFWIN, window);
|
||||
Outp32(base + BTS_DEFTKN, token);
|
||||
Outp32(base + BTS_PRMWIN, window);
|
||||
Outp32(base + BTS_PRMTKN, token);
|
||||
Outp32(base + BTS_FLEXIBLE, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY + WOFFSET, (priority & 0xFFFF));
|
||||
Outp32(base + BTS_TOKENMAX + WOFFSET, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND + WOFFSET, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND + WOFFSET, 0x1);
|
||||
Outp32(base + BTS_INITTKN + WOFFSET, 0x8);
|
||||
Outp32(base + BTS_DEMWIN + WOFFSET, window);
|
||||
Outp32(base + BTS_DEMTKN + WOFFSET, token);
|
||||
Outp32(base + BTS_DEFWIN + WOFFSET, window);
|
||||
Outp32(base + BTS_DEFTKN + WOFFSET, token);
|
||||
Outp32(base + BTS_PRMWIN + WOFFSET, window);
|
||||
Outp32(base + BTS_PRMTKN + WOFFSET, token);
|
||||
Outp32(base + BTS_FLEXIBLE + WOFFSET, 0x0);
|
||||
|
||||
Outp32(base + BTS_RMODE, 0x1);
|
||||
Outp32(base + BTS_WMODE, 0x1);
|
||||
Outp32(base + BTS_EMERGENTRID, master_id);
|
||||
Outp32(base + BTS_EMERGENTWID, master_id);
|
||||
Outp32(base + BTS_RCON, 0x3);
|
||||
Outp32(base + BTS_WCON, 0x3);
|
||||
}
|
||||
|
||||
void bts_setqos_mo(addr_u32 base, unsigned int priority, unsigned int mo, unsigned int master_id) //QOS : [RRRRWWWW]
|
||||
{
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY, ((priority >> 16) & 0xFFFF));
|
||||
Outp32(base + BTS_MOUPBOUND, 0x7F - mo);
|
||||
Outp32(base + BTS_MOLOBOUND, mo);
|
||||
Outp32(base + BTS_FLEXIBLE, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY + WOFFSET, (priority & 0xFFFF));
|
||||
Outp32(base + BTS_MOUPBOUND + WOFFSET, 0x7F - mo);
|
||||
Outp32(base + BTS_MOLOBOUND + WOFFSET, mo);
|
||||
Outp32(base + BTS_FLEXIBLE + WOFFSET, 0x0);
|
||||
|
||||
Outp32(base + BTS_RMODE, 0x2);
|
||||
Outp32(base + BTS_WMODE, 0x2);
|
||||
Outp32(base + BTS_EMERGENTRID, master_id);
|
||||
Outp32(base + BTS_EMERGENTWID, master_id);
|
||||
Outp32(base + BTS_RCON, 0x3);
|
||||
Outp32(base + BTS_WCON, 0x3);
|
||||
}
|
||||
|
||||
void bts_setqos_fbmbw(addr_u32 base, unsigned int priority, unsigned int window,
|
||||
unsigned int token, unsigned int fbm, unsigned int master_id) //QOS : [RRRRWWWW]
|
||||
{
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY, ((priority >> 16) & 0xFFFF));
|
||||
Outp32(base + BTS_TOKENMAX, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND, 0x1);
|
||||
Outp32(base + BTS_INITTKN, 0x8);
|
||||
Outp32(base + BTS_DEMWIN, window);
|
||||
Outp32(base + BTS_DEMTKN, token);
|
||||
Outp32(base + BTS_DEFWIN, window);
|
||||
Outp32(base + BTS_DEFTKN, token);
|
||||
Outp32(base + BTS_PRMWIN, window);
|
||||
Outp32(base + BTS_PRMTKN, token);
|
||||
Outp32(base + BTS_FLEXIBLE, 0x2);
|
||||
|
||||
Outp32(base + BTS_PRIORITY + WOFFSET, (priority & 0xFFFF));
|
||||
Outp32(base + BTS_TOKENMAX + WOFFSET, 0xFFDF);
|
||||
Outp32(base + BTS_BWUPBOUND + WOFFSET, 0x18);
|
||||
Outp32(base + BTS_BWLOBOUND + WOFFSET, 0x1);
|
||||
Outp32(base + BTS_INITTKN + WOFFSET, 0x8);
|
||||
Outp32(base + BTS_DEMWIN + WOFFSET, window);
|
||||
Outp32(base + BTS_DEMTKN + WOFFSET, token);
|
||||
Outp32(base + BTS_DEFWIN + WOFFSET, window);
|
||||
Outp32(base + BTS_DEFTKN + WOFFSET, token);
|
||||
Outp32(base + BTS_PRMWIN + WOFFSET, window);
|
||||
Outp32(base + BTS_PRMTKN + WOFFSET, token);
|
||||
Outp32(base + BTS_FLEXIBLE + WOFFSET, 0x1);
|
||||
|
||||
Outp32(base + BTS_RMODE, 0x1);
|
||||
Outp32(base + BTS_WMODE, 0x1);
|
||||
|
||||
Outp32(base + BTS_EMERGENTRID, master_id);
|
||||
Outp32(base + BTS_EMERGENTWID, master_id);
|
||||
if(fbm == 1) {
|
||||
Outp32(base + BTS_RCON, 0x7);
|
||||
Outp32(base + BTS_WCON, 0x7);
|
||||
} else {
|
||||
Outp32(base + BTS_RCON, 0x3);
|
||||
Outp32(base + BTS_WCON, 0x3);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void bts_setemergentID(addr_u32 base, unsigned int master_id)
|
||||
{
|
||||
Outp32(base + BTS_PRIORITY, 0x4444);
|
||||
Outp32(base + BTS_PRIORITY + WOFFSET, 0x4444);
|
||||
|
||||
Outp32(base + BTS_EMERGENTRID, master_id);
|
||||
Outp32(base + BTS_EMERGENTWID, master_id);
|
||||
}
|
||||
|
||||
|
||||
void bts_disable(addr_u32 base, unsigned int master_id)
|
||||
{
|
||||
/* reset to default */
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_RCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
Outp32(base + BTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + BTS_RMODE, 0x1);
|
||||
Outp32(base + BTS_WMODE, 0x1);
|
||||
|
||||
Outp32(base + BTS_PRIORITY, 0xA942);
|
||||
Outp32(base + BTS_TOKENMAX, 0x0);
|
||||
Outp32(base + BTS_BWUPBOUND, 0x3FFF);
|
||||
Outp32(base + BTS_BWLOBOUND, 0x3FFF);
|
||||
Outp32(base + BTS_INITTKN, 0x7FFF);
|
||||
Outp32(base + BTS_DEMWIN, 0x7FFF);
|
||||
Outp32(base + BTS_DEMTKN, 0x1FFF);
|
||||
Outp32(base + BTS_DEFWIN, 0x7FFF);
|
||||
Outp32(base + BTS_DEFTKN, 0x1FFF);
|
||||
Outp32(base + BTS_PRMWIN, 0x7FFF);
|
||||
Outp32(base + BTS_PRMTKN, 0x1FFF);
|
||||
Outp32(base + BTS_MOUPBOUND, 0x1F);
|
||||
Outp32(base + BTS_MOLOBOUND, 0x1F);
|
||||
Outp32(base + BTS_FLEXIBLE, 0x0);
|
||||
|
||||
Outp32(base + BTS_PRIORITY + WOFFSET, 0xA942);
|
||||
Outp32(base + BTS_TOKENMAX + WOFFSET, 0x0);
|
||||
Outp32(base + BTS_BWUPBOUND + WOFFSET, 0x3FFF);
|
||||
Outp32(base + BTS_BWLOBOUND + WOFFSET, 0x3FFF);
|
||||
Outp32(base + BTS_INITTKN + WOFFSET, 0x7FFF);
|
||||
Outp32(base + BTS_DEMWIN + WOFFSET, 0x7FFF);
|
||||
Outp32(base + BTS_DEMTKN + WOFFSET, 0x1FFF);
|
||||
Outp32(base + BTS_DEFWIN + WOFFSET, 0x7FFF);
|
||||
Outp32(base + BTS_DEFTKN + WOFFSET, 0x1FFF);
|
||||
Outp32(base + BTS_PRMWIN + WOFFSET, 0x7FFF);
|
||||
Outp32(base + BTS_PRMTKN + WOFFSET, 0x1FFF);
|
||||
Outp32(base + BTS_MOUPBOUND + WOFFSET, 0x1F);
|
||||
Outp32(base + BTS_MOLOBOUND + WOFFSET, 0x1F);
|
||||
Outp32(base + BTS_FLEXIBLE + WOFFSET, 0x0);
|
||||
Outp32(base + BTS_EMERGENTRID, master_id);
|
||||
Outp32(base + BTS_EMERGENTWID, master_id);
|
||||
}
|
||||
|
||||
void bts_settrexqos(addr_u32 base, unsigned int priority, unsigned int master_id, unsigned int mask)
|
||||
{
|
||||
Outp32(base + TBTS_CON, 0x0);
|
||||
Outp32(base + TBTS_RCON, 0x0);
|
||||
Outp32(base + TBTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + TBTS_DEMQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_DEFQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_PRMQOS, priority & 0xF);
|
||||
|
||||
Outp32(base + TBTS_EMERGENTID, master_id);
|
||||
Outp32(base + TBTS_MASK, mask);
|
||||
Outp32(base + TBTS_CON, 0x1001);
|
||||
}
|
||||
|
||||
void bts_settrexqos_mo(addr_u32 base, unsigned int priority, unsigned int mo, unsigned int master_id, unsigned int mask)
|
||||
{
|
||||
Outp32(base + TBTS_CON, 0x0);
|
||||
Outp32(base + TBTS_RCON, 0x0);
|
||||
Outp32(base + TBTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + TBTS_TKNUPBOUND, mo);
|
||||
Outp32(base + TBTS_TKNLOBOUND, mo);
|
||||
|
||||
Outp32(base + TBTS_DEMTH, mo);
|
||||
Outp32(base + TBTS_PRMTH, mo);
|
||||
|
||||
Outp32(base + TBTS_DEMQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_DEFQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_PRMQOS, priority & 0xF);
|
||||
|
||||
Outp32(base + TBTS_RCON, 0x11); // MO mode & Blocking on
|
||||
Outp32(base + TBTS_WCON, 0x11);
|
||||
Outp32(base + TBTS_EMERGENTID, master_id);
|
||||
Outp32(base + TBTS_MASK, mask);
|
||||
Outp32(base + TBTS_CON, 0x1001);
|
||||
}
|
||||
|
||||
void bts_settrexqos_mo_rt(addr_u32 base, unsigned int priority, unsigned int mo, unsigned int master_id, unsigned int mask,
|
||||
unsigned int time_out, unsigned int bypass_en)
|
||||
{
|
||||
Outp32(base + TBTS_CON, 0x0);
|
||||
Outp32(base + TBTS_RCON, 0x0);
|
||||
Outp32(base + TBTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + TBTS_TKNUPBOUND, mo);
|
||||
Outp32(base + TBTS_TKNLOBOUND, mo);
|
||||
|
||||
Outp32(base + TBTS_DEMTH, mo);
|
||||
Outp32(base + TBTS_PRMTH, mo);
|
||||
|
||||
Outp32(base + TBTS_DEMQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_DEFQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_PRMQOS, priority & 0xF);
|
||||
|
||||
Outp32(base + TBTS_TIMEOUT, time_out);
|
||||
|
||||
if(bypass_en) {
|
||||
Outp32(base + TBTS_RCON, 0x111); // MO mode & Qos bypass
|
||||
Outp32(base + TBTS_WCON, 0x111);
|
||||
} else {
|
||||
Outp32(base + TBTS_RCON, 0x11); // MO mode
|
||||
Outp32(base + TBTS_WCON, 0x11);
|
||||
}
|
||||
Outp32(base + TBTS_EMERGENTID, master_id);
|
||||
Outp32(base + TBTS_MASK, mask);
|
||||
Outp32(base + TBTS_CON, 0x1001); // Time out, Urgent enable
|
||||
}
|
||||
|
||||
void bts_settrexqos_bw(addr_u32 base, unsigned int priority, unsigned int decval, unsigned int master_id, unsigned int mask)
|
||||
{
|
||||
Outp32(base + TBTS_CON, 0x0);
|
||||
Outp32(base + TBTS_RCON, 0x0);
|
||||
Outp32(base + TBTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + TBTS_TKNUPBOUND, 0x3FFF);
|
||||
Outp32(base + TBTS_TKNLOBOUND, 0x3FF7);
|
||||
Outp32(base + TBTS_RTKNINIT, 0x3FFF);
|
||||
Outp32(base + TBTS_WTKNINIT, 0x3FFF);
|
||||
|
||||
Outp32(base + TBTS_DEMQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_DEFQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_PRMQOS, priority & 0xF);
|
||||
|
||||
Outp32(base + TBTS_RTKNDEC, decval);
|
||||
Outp32(base + TBTS_WTKNDEC, decval);
|
||||
|
||||
Outp32(base + TBTS_RCON, 0x1); // Blocking on
|
||||
Outp32(base + TBTS_WCON, 0x1);
|
||||
Outp32(base + TBTS_EMERGENTID, master_id);
|
||||
Outp32(base + TBTS_MASK, mask);
|
||||
Outp32(base + TBTS_CON, 0x1001);
|
||||
|
||||
}
|
||||
|
||||
void bts_settrexqos_fbmbw(addr_u32 base, unsigned int priority, unsigned int master_id, unsigned int mask)
|
||||
{
|
||||
Outp32(base + TBTS_CON, 0x0);
|
||||
Outp32(base + TBTS_RCON, 0x0);
|
||||
Outp32(base + TBTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + TBTS_DEMQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_DEFQOS, priority & 0xF);
|
||||
Outp32(base + TBTS_PRMQOS, priority & 0xF);
|
||||
|
||||
Outp32(base + TBTS_RCON, 0x1); // Blocking on
|
||||
Outp32(base + TBTS_WCON, 0x1);
|
||||
Outp32(base + TBTS_EMERGENTID, master_id);
|
||||
Outp32(base + TBTS_MASK, mask);
|
||||
Outp32(base + TBTS_CON, 0x1001);
|
||||
}
|
||||
|
||||
|
||||
void bts_trexdisable(addr_u32 base, unsigned int master_id, unsigned int mask)
|
||||
{
|
||||
Outp32(base + TBTS_CON, 0x00010000);
|
||||
Outp32(base + TBTS_RCON, 0x0);
|
||||
Outp32(base + TBTS_WCON, 0x0);
|
||||
|
||||
Outp32(base + TBTS_TKNUPBOUND, 0x5FFF);
|
||||
Outp32(base + TBTS_TKNLOBOUND, 0x1FFF);
|
||||
|
||||
Outp32(base + TBTS_DEMTH, 0x5FFF);
|
||||
Outp32(base + TBTS_PRMTH, 0x1FFF);
|
||||
|
||||
Outp32(base + TBTS_DEMQOS, 0x2);
|
||||
Outp32(base + TBTS_DEFQOS, 0x4);
|
||||
Outp32(base + TBTS_PRMQOS, 0x9);
|
||||
|
||||
Outp32(base + TBTS_QURGUPTH, 0x8);
|
||||
Outp32(base + TBTS_QURGDOWNTH, 0x8);
|
||||
Outp32(base + TBTS_RTKNINIT, 0x3FFF);
|
||||
Outp32(base + TBTS_WTKNINIT, 0x3FFF);
|
||||
Outp32(base + TBTS_RTKNDEC, 0x0);
|
||||
Outp32(base + TBTS_WTKNDEC, 0x0);
|
||||
Outp32(base + TBTS_EMERGENTID, master_id);
|
||||
Outp32(base + TBTS_MASK, mask);
|
||||
}
|
||||
|
||||
|
||||
|
||||
void bts_setnsp(addr_u32 base, unsigned int nsp)
|
||||
{
|
||||
Outp32(base , nsp);
|
||||
}
|
||||
126
drivers/bts/cal_bts8890.h
Normal file
126
drivers/bts/cal_bts8890.h
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
/* arch/arm/mach-exynos/cal_bts.h
|
||||
*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* EXYNOS - BTS CAL code.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __BTSCAL_H__
|
||||
#define __BTSCAL_H__
|
||||
|
||||
#if defined(CONFIG_EXYNOS8890_BTS)
|
||||
#include <linux/io.h>
|
||||
|
||||
#define Outp32(addr, data) (__raw_writel(data, addr))
|
||||
#define Inp32(addr) (__raw_readl(addr))
|
||||
typedef void __iomem *addr_u32;
|
||||
|
||||
#else
|
||||
typedef unsigned long u32;
|
||||
typedef unsigned long addr_u32;
|
||||
#define Outp32(addr, data) (*(volatile unsigned int *)(addr) = (data))
|
||||
#define Inp32(addr) (*(volatile unsigned int *)(addr))
|
||||
|
||||
#endif
|
||||
|
||||
/* for BTS V2.1 Register */
|
||||
#define BTS_RCON 0x100
|
||||
#define BTS_RMODE 0x104
|
||||
#define BTS_WCON 0x180
|
||||
#define BTS_WMODE 0x184
|
||||
#define BTS_PRIORITY 0x200
|
||||
#define BTS_TOKENMAX 0x204
|
||||
#define BTS_BWUPBOUND 0x20C
|
||||
#define BTS_BWLOBOUND 0x210
|
||||
#define BTS_INITTKN 0x214
|
||||
#define BTS_RSTCLK 0x218
|
||||
#define BTS_RSTTKN 0x21C
|
||||
#define BTS_DEMWIN 0x220
|
||||
#define BTS_DEMTKN 0x224
|
||||
#define BTS_DEFWIN 0x228
|
||||
#define BTS_DEFTKN 0x22C
|
||||
#define BTS_PRMWIN 0x230
|
||||
#define BTS_PRMTKN 0x234
|
||||
#define BTS_MOUPBOUND 0x240
|
||||
#define BTS_MOLOBOUND 0x244
|
||||
#define BTS_FLEXIBLE 0x280
|
||||
#define BTS_POLARITY 0x284
|
||||
#define BTS_FBMGRP0ADRS 0x290
|
||||
#define BTS_FBMGRP0ADRE 0x294
|
||||
#define BTS_FBMGRP1ADRS 0x298
|
||||
#define BTS_FBMGRP1ADRE 0x29C
|
||||
#define BTS_FBMGRP2ADRS 0x2A0
|
||||
#define BTS_FBMGRP2ADRE 0x2A4
|
||||
#define BTS_FBMGRP3ADRS 0x2A8
|
||||
#define BTS_FBMGRP3ADRE 0x2AC
|
||||
#define BTS_FBMGRP4ADRS 0x2B0
|
||||
#define BTS_FBMGRP4ADRE 0x2B4
|
||||
#define BTS_EMERGENTRID 0x2C0
|
||||
#define BTS_EMERGENTWID 0x3C0
|
||||
#define BTS_RISINGTH 0x2C4
|
||||
#define BTS_FALLINGTH 0x2C8
|
||||
#define BTS_FALLINGMO 0x2CC
|
||||
#define BTS_MOCOUNTER 0x2F0
|
||||
#define BTS_STATUS 0x2F4
|
||||
#define BTS_BWMONLOW 0x2F8
|
||||
#define BTS_BWMONUP 0x2FC
|
||||
|
||||
#define WOFFSET 0x100
|
||||
|
||||
/* for TREX_BTS Register */
|
||||
#define TBTS_CON 0x000
|
||||
#define TBTS_TKNUPBOUND 0x010
|
||||
#define TBTS_TKNLOBOUND 0x014
|
||||
#define TBTS_LOADUP 0x020
|
||||
#define TBTS_LOADDOWN 0x024
|
||||
#define TBTS_LOADBUSY 0x028
|
||||
#define TBTS_TKNINC0 0x040
|
||||
#define TBTS_TKNINC1 0x044
|
||||
#define TBTS_TKNINC2 0x048
|
||||
#define TBTS_TKNINC3 0x04C
|
||||
#define TBTS_TKNINC4 0x050
|
||||
#define TBTS_TKNINC5 0x054
|
||||
#define TBTS_TKNINC6 0x058
|
||||
#define TBTS_TKNINC7 0x05C
|
||||
#define TBTS_DEMTH 0x070
|
||||
#define TBTS_PRMTH 0x074
|
||||
#define TBTS_DEMQOS 0x080
|
||||
#define TBTS_DEFQOS 0x084
|
||||
#define TBTS_PRMQOS 0x088
|
||||
#define TBTS_TIMEOUT 0x090
|
||||
#define TBTS_QURGUPTH 0x0D0
|
||||
#define TBTS_QURGDOWNTH 0x0D4
|
||||
#define TBTS_SELIDMASK 0x0E0
|
||||
#define TBTS_SELIDVAL 0x0E4
|
||||
#define TBTS_RCON 0x100
|
||||
#define TBTS_RTKNINIT 0x110
|
||||
#define TBTS_RTKNDEC 0x120
|
||||
#define TBTS_WCON 0x200
|
||||
#define TBTS_WTKNINIT 0x210
|
||||
#define TBTS_WTKNDEC 0x220
|
||||
#define TBTS_EMERGENTID 0x2014
|
||||
#define TBTS_MASK 0x2010
|
||||
|
||||
void bts_setqos(addr_u32 base, unsigned int priority, unsigned int master_id);
|
||||
void bts_setqos_bw(addr_u32 base, unsigned int priority,
|
||||
unsigned int window, unsigned int token, unsigned int master_id);
|
||||
void bts_setqos_mo(addr_u32 base, unsigned int priority, unsigned int mo, unsigned int master_id);
|
||||
void bts_setqos_fbmbw(addr_u32 base, unsigned int priority, unsigned int window,
|
||||
unsigned int token, unsigned int fbm, unsigned int master_id);
|
||||
void bts_setemergentID(addr_u32 base, unsigned int master_id);
|
||||
void bts_disable(addr_u32 base, unsigned int master_id);
|
||||
void bts_settrexqos(addr_u32 base, unsigned int priority, unsigned int master_id, unsigned int mask);
|
||||
void bts_settrexqos_mo(addr_u32 base, unsigned int priority, unsigned int mo, unsigned int master_id, unsigned int mask);
|
||||
void bts_settrexqos_mo_rt(addr_u32 base, unsigned int priority, unsigned int mo, unsigned int master_id, unsigned int mask,
|
||||
unsigned int time_out, unsigned int bypass_en);
|
||||
void bts_settrexqos_bw(addr_u32 base, unsigned int priority, unsigned int decval, unsigned int master_id, unsigned int mask);
|
||||
void bts_settrexqos_fbmbw(addr_u32 base, unsigned int priority, unsigned int master_id, unsigned int mask);
|
||||
void bts_trexdisable(addr_u32 base, unsigned int master_id, unsigned int mask);
|
||||
void bts_setnsp(addr_u32 base, unsigned int nsp);
|
||||
|
||||
#endif
|
||||
250
drivers/bts/regs-bts.h
Normal file
250
drivers/bts/regs-bts.h
Normal file
|
|
@ -0,0 +1,250 @@
|
|||
#ifndef __ASM_ARCH_REGS_BTS_H
|
||||
#define __ASM_ARCH_REGS_BTS_H
|
||||
|
||||
/* EXYNOS5433 BTS SFR base address */
|
||||
#define EXYNOS5433_PA_BTS_DECONM0 0x13A80000
|
||||
#define EXYNOS5433_PA_BTS_DECONM1 0x13A90000
|
||||
#define EXYNOS5433_PA_BTS_DECONM2 0x13AA0000
|
||||
#define EXYNOS5433_PA_BTS_DECONM3 0x13AB0000
|
||||
#define EXYNOS5433_PA_BTS_DECONM4 0x13AC0000
|
||||
#define EXYNOS5433_PA_BTS_DECONTV_M0 0x13B00000
|
||||
#define EXYNOS5433_PA_BTS_DECONTV_M1 0x13B10000
|
||||
#define EXYNOS5433_PA_BTS_DECONTV_M2 0x13B20000
|
||||
#define EXYNOS5433_PA_BTS_DECONTV_M3 0x13B30000
|
||||
#define EXYNOS5433_PA_BTS_FIMC_LITE0 0x12000000
|
||||
#define EXYNOS5433_PA_BTS_FIMC_LITE1 0x12010000
|
||||
#define EXYNOS5433_PA_BTS_FIMC_LITE2 0x14500000
|
||||
#define EXYNOS5433_PA_BTS_FIMC_LITE3 0x12020000
|
||||
#define EXYNOS5433_PA_BTS_3AA0 0x12030000
|
||||
#define EXYNOS5433_PA_BTS_3AA1 0x12040000
|
||||
#define EXYNOS5433_PA_BTS_GSCL0 0x13CC0000
|
||||
#define EXYNOS5433_PA_BTS_GSCL1 0x13CD0000
|
||||
#define EXYNOS5433_PA_BTS_GSCL2 0x13CE0000
|
||||
#define EXYNOS5433_PA_BTS_MFC0 0x15220000
|
||||
#define EXYNOS5433_PA_BTS_MFC1 0x15230000
|
||||
|
||||
#define EXYNOS5433_PA_DREX0 0x10400000
|
||||
#define EXYNOS5433_PA_DREX1 0x10440000
|
||||
|
||||
/* EXYNOS7420 BTS SFR base address */
|
||||
#define EXYNOS7420_PA_BTS_USBDRD30 0x10EA0000
|
||||
#define EXYNOS7420_PA_BTS_MODEMX 0x10E30000
|
||||
#define EXYNOS7420_PA_BTS_SDCARDX 0x10E20000
|
||||
#define EXYNOS7420_PA_BTS_WIFI1 0x15640000
|
||||
#define EXYNOS7420_PA_BTS_EMBEDDED 0x15620000
|
||||
#define EXYNOS7420_PA_BTS_M2M1 0x15090000
|
||||
#define EXYNOS7420_PA_BTS_M2M0 0x15080000
|
||||
#define EXYNOS7420_PA_BTS_JPEG0 0x15070000
|
||||
#define EXYNOS7420_PA_BTS_G2D 0x15180000
|
||||
#define EXYNOS7420_PA_BTS_G3D0 0x14A00000
|
||||
#define EXYNOS7420_PA_BTS_G3D1 0x14A20000
|
||||
#define EXYNOS7420_PA_BTS_SLIMSSS 0x111F0000
|
||||
#define EXYNOS7420_PA_BTS_SSS 0x111E0000
|
||||
#define EXYNOS7420_PA_BTS_SMDMA 0x111D0000
|
||||
#define EXYNOS7420_PA_BTS_MCOMP 0x111A0000
|
||||
|
||||
|
||||
|
||||
#define EXYNOS7420_PA_BTS_DISP_RO_0 0x13A80000
|
||||
#define EXYNOS7420_PA_BTS_DISP_RO_1 0x13A90000
|
||||
#define EXYNOS7420_PA_BTS_DISP_RW_0 0x13AA0000
|
||||
#define EXYNOS7420_PA_BTS_DISP_RW_1 0x13AB0000
|
||||
#define EXYNOS7420_PA_BTS_VPP0 0x13E60000
|
||||
#define EXYNOS7420_PA_BTS_VPP1 0x13E70000
|
||||
#define EXYNOS7420_PA_BTS_VPP2 0x13E80000
|
||||
#define EXYNOS7420_PA_BTS_VPP3 0x13E90000
|
||||
#define EXYNOS7420_PA_BTS_TREX_FIMC_BNS_A 0x14400000
|
||||
#define EXYNOS7420_PA_BTS_TREX_FIMC_BNS_B 0x14410000
|
||||
#define EXYNOS7420_PA_BTS_TREX_FIMC_BNS_C 0x14500000
|
||||
#define EXYNOS7420_PA_BTS_TREX_FIMC_BNS_D 0x14420000
|
||||
#define EXYNOS7420_PA_BTS_TREX_3AA0 0x14430000
|
||||
#define EXYNOS7420_PA_BTS_TREX_3AA1 0x14440000
|
||||
#define EXYNOS7420_PA_BTS_TREX_ISPCPU 0x14540000
|
||||
#define EXYNOS7420_PA_BTS_TREX_VRA 0x14530000
|
||||
#define EXYNOS7420_PA_BTS_TREX_SCALER 0x14520000
|
||||
#define EXYNOS7420_PA_BTS_TREX_ISP1 0x14510000
|
||||
#define EXYNOS7420_PA_BTS_TREX_TPU 0x14610000
|
||||
#define EXYNOS7420_PA_BTS_TREX_ISP0 0x14600000
|
||||
#define EXYNOS7420_PA_BTS_MFC_0 0x15220000
|
||||
#define EXYNOS7420_PA_BTS_MFC_1 0x15230000
|
||||
#define EXYNOS7420_PA_BTS_BIG 0x10530000
|
||||
#define EXYNOS7420_PA_BTS_LITTLE 0x10540000
|
||||
|
||||
#define EXYNOS7_PA_DREX0 0x10800000
|
||||
#define EXYNOS7_PA_DREX1 0x10900000
|
||||
#define EXYNOS7_PA_DREX2 0x10A00000
|
||||
#define EXYNOS7_PA_DREX3 0x10B00000
|
||||
#define EXYNOS7_PA_NSP 0x10550000
|
||||
#define EXYNOS7_PA_SYSREG 0x10050000
|
||||
|
||||
#define EXYNOS7_TREX_ID_MASK 0x3F
|
||||
|
||||
/* EXYNOS7420 BTS system register offet */
|
||||
#define FSYS0_QOS_VAL0 0x1038
|
||||
|
||||
/* EXYNOS7420 BTS SFR offset*/
|
||||
#define READ_QOS_CONTROL 0x0100
|
||||
#define READ_QOS_MODE 0x0104
|
||||
#define READ_CHANNEL_PRIORITY 0x0200
|
||||
#define READ_TOKEN_MAX_VALUE 0x0204
|
||||
#define READ_BW_UPPER_BOUNDARY 0x020C
|
||||
#define READ_BW_LOWER_BOUNDARY 0x0210
|
||||
#define READ_INITIAL_TOKEN_VALUE 0x0214
|
||||
#define READ_DEMOTION_WINDOW 0x0220
|
||||
#define READ_DEMOTION_TOKEN 0x0224
|
||||
#define READ_DEFAULT_WINDOW 0x0228
|
||||
#define READ_DEFAULT_TOKEN 0x022C
|
||||
#define READ_PROMOTION_WINDOW 0X0230
|
||||
#define READ_PROMOTION_TOKEN 0x0234
|
||||
#define READ_ISSUE_CAPABILITY_UPPER_BOUNDARY 0x0240
|
||||
#define READ_ISSUE_CAPABILITY_LOWER_BOUNDARY 0x0244
|
||||
#define READ_FLEXIBLE_BLOCKING_CONTROL 0x0280
|
||||
#define READ_FLEXIBLE_BLOCKING_POLARITY 0x0284
|
||||
#define READ_MO 0x02F0
|
||||
|
||||
#define WRITE_QOS_CONTROL 0x0180
|
||||
#define WRITE_QOS_MODE 0x0184
|
||||
#define WRITE_CHANNEL_PRIORITY 0x0300
|
||||
#define WRITE_TOKEN_MAX_VALUE 0x0304
|
||||
#define WRITE_BW_UPPER_BOUNDARY 0x030C
|
||||
#define WRITE_BW_LOWER_BOUNDARY 0x0310
|
||||
#define WRITE_INITIAL_TOKEN_VALUE 0x0314
|
||||
#define WRITE_DEMOTION_WINDOW 0x0320
|
||||
#define WRITE_DEMOTION_TOKEN 0x0324
|
||||
#define WRITE_DEFAULT_WINDOW 0x0328
|
||||
#define WRITE_DEFAULT_TOKEN 0x032C
|
||||
#define WRITE_PROMOTION_WINDOW 0X0330
|
||||
#define WRITE_PROMOTION_TOKEN 0x0334
|
||||
#define WRITE_ISSUE_CAPABILITY_UPPER_BOUNDARY 0x0340
|
||||
#define WRITE_ISSUE_CAPABILITY_LOWER_BOUNDARY 0x0344
|
||||
#define WRITE_FLEXIBLE_BLOCKING_CONTROL 0x0380
|
||||
#define WRITE_FLEXIBLE_BLOCKING_POLARITY 0x0384
|
||||
#define WRITE_MO 0x03F0
|
||||
|
||||
#define FBM_MODESEL0 0x00
|
||||
#define FBM_MODESEL1 0x04
|
||||
#define FBM_MODESEL2 0x08
|
||||
#define FBM_THRESHOLD0 0x40
|
||||
#define FBM_THRESHOLD1 0x44
|
||||
#define FBM_THRESHOLD2 0x48
|
||||
#define FBM_OUTSEL0 0x80
|
||||
#define FBM_OUTSEL2 0x88
|
||||
#define FBM_OUTSEL20 0xD0
|
||||
|
||||
#define TREX_QOS_CONTROL 0x0000
|
||||
#define TREX_DEMOTION_QOS_VALUE 0x0080
|
||||
#define TREX_DEFAULT_QOS_VALUE 0x0084
|
||||
#define TREX_PROMOTION_QOS_VALUE 0x0088
|
||||
#define TREX_QOS_THRESHOLD_FOR_EMERGENCY_RISING 0x00D0
|
||||
#define TREX_QOS_THRESHOLD_FOR_EMERGENCY_FALLING 0x00D4
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS7870)
|
||||
#define QOS_TIMEOUT_0x0 0x300
|
||||
#define QOS_TIMEOUT_0x1 0x304
|
||||
#define QOS_TIMEOUT_0x2 0x308
|
||||
#define QOS_TIMEOUT_0x3 0x30c
|
||||
#define QOS_TIMEOUT_0x4 0x310
|
||||
#define QOS_TIMEOUT_0x5 0x314
|
||||
#define QOS_TIMEOUT_0x6 0x318
|
||||
#define QOS_TIMEOUT_0x7 0x31c
|
||||
#define QOS_TIMEOUT_0x8 0x320
|
||||
#define QOS_TIMEOUT_0x9 0x324
|
||||
#define QOS_TIMEOUT_0xA 0x328
|
||||
#define QOS_TIMEOUT_0xB 0x32C
|
||||
#define QOS_TIMEOUT_0xC 0x330
|
||||
#define QOS_TIMEOUT_0xD 0x334
|
||||
#define QOS_TIMEOUT_0xE 0x338
|
||||
#define QOS_TIMEOUT_0xF 0x33c
|
||||
#else
|
||||
#define QOS_TIMEOUT_0x8 0xA0
|
||||
#define QOS_TIMEOUT_0xA 0xB0
|
||||
#define QOS_TIMEOUT_0xB 0xB8
|
||||
#define QOS_TIMEOUT_0xC 0xC0
|
||||
#define QOS_TIMEOUT_0xD 0xC8
|
||||
#define QOS_TIMEOUT_0xE 0xD0
|
||||
#define QOS_TIMEOUT_0xF 0xD8
|
||||
#define QOS_TIMEOUT_0x5 0x88
|
||||
#define QOS_TIMEOUT_0x4 0x80
|
||||
#define BRB_CON 0x100
|
||||
#define BRB_THRESHOLD 0x104
|
||||
#endif
|
||||
|
||||
#define NSP_CH0 0x0008
|
||||
#define NSP_CH1 0x0408
|
||||
#define NSP_CH2 0x0808
|
||||
#define NSP_CH3 0x0C08
|
||||
|
||||
#define SYSREG_FSYS0 0x1064
|
||||
#define SYSREG_FSYS1 0x2664
|
||||
#define SYSREG_APM_R 0x1438
|
||||
#define SYSREG_APM_W 0x143C
|
||||
#define SYSREG_RTIC 0x1440
|
||||
#define SYSREG_PDMA_SECURE_R 0x144C
|
||||
#define SYSREG_PDMA_SECURE_W 0x1450
|
||||
#define SYSREG_AUD 0x0248
|
||||
|
||||
/* Exynos8890 BTS */
|
||||
#define EXYNOS8890_PA_BTS_TREX_DISP0_0 0x11F30000
|
||||
#define EXYNOS8890_PA_BTS_TREX_DISP0_1 0x11F40000
|
||||
#define EXYNOS8890_PA_BTS_TREX_DISP1_0 0x11F50000
|
||||
#define EXYNOS8890_PA_BTS_TREX_DISP1_1 0x11F60000
|
||||
#define EXYNOS8890_PA_BTS_TREX_ISP0 0x11F20000
|
||||
#define EXYNOS8890_PA_BTS_TREX_CAM0 0x11F70000
|
||||
#define EXYNOS8890_PA_BTS_TREX_CAM1 0x11F10000
|
||||
#define EXYNOS8890_PA_BTS_TREX_CP 0x10730000
|
||||
#define EXYNOS8890_PA_BTS_TREX_MFC0 0x11D30000
|
||||
#define EXYNOS8890_PA_BTS_TREX_MFC1 0x11D40000
|
||||
#define EXYNOS8890_PA_BTS_TREX_G3D0 0x10680000
|
||||
#define EXYNOS8890_PA_BTS_TREX_G3D1 0x10690000
|
||||
#define EXYNOS8890_PA_BTS_TREX_FSYS0 0x11D00000
|
||||
#define EXYNOS8890_PA_BTS_TREX_FSYS1 0x11F00000
|
||||
#define EXYNOS8890_PA_BTS_TREX_MSCL0 0x11D10000
|
||||
#define EXYNOS8890_PA_BTS_TREX_MSCL1 0x11D20000
|
||||
|
||||
#define EXYNOS8_PA_SMC0 0x10800000
|
||||
#define EXYNOS8_PA_SMC1 0x10900000
|
||||
#define EXYNOS8_PA_SMC2 0x10A00000
|
||||
#define EXYNOS8_PA_SMC3 0x10B00000
|
||||
#define EXYNOS8_PA_SYSREG 0x10050000
|
||||
|
||||
#define EXYNOS8_PA_TREX_CCORE0 0x10704000
|
||||
#define EXYNOS8_PA_TREX_CCORE1 0x10714000
|
||||
|
||||
#define SCI_CTRL 0x0000
|
||||
#define READ_QURGENT 0x0010
|
||||
#define WRITE_QURGENT 0x0030
|
||||
#define VC_NUM0 0x0050
|
||||
#define VC_NUM1 0x0054
|
||||
#define TH_IMM0 0x0100
|
||||
#define TH_IMM1 0x0104
|
||||
#define TH_IMM2 0x0108
|
||||
#define TH_IMM3 0x010C
|
||||
#define TH_IMM4 0x0110
|
||||
#define TH_IMM5 0x0114
|
||||
#define TH_IMM6 0x0118
|
||||
#define TH_HIGH0 0x0200
|
||||
#define TH_HIGH1 0x0204
|
||||
#define TH_HIGH2 0x0208
|
||||
#define TH_HIGH3 0x020C
|
||||
#define TH_HIGH4 0x0210
|
||||
#define TH_HIGH5 0x0214
|
||||
#define TH_HIGH6 0x0218
|
||||
|
||||
#define SCHED_CTRL0 0x0248
|
||||
#define SCHED_CTRL1 0x024C
|
||||
#define SCHED_CTRL2 0x0250
|
||||
#define SCHED_CTRL3 0x0254
|
||||
|
||||
/* Exynos7870 BTS */
|
||||
#define EXYNOS7870_PA_SYSREG_DISPAUD 0x148F0000
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||||
#define EXYNOS7870_PA_SYSREG_FSYS 0x13720000
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#define EXYNOS7870_PA_SYSREG_ISP 0x144F0000
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||||
#define EXYNOS7870_PA_SYSREG_MFCMSCL 0x12CA0000
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#define EXYNOS7870_PA_PMU_ALIVE 0x10480000
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#define EXYNOS7870_PA_SYSREG_MIF 0x10450000
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||||
#define EXYNOS7870_PA_DREX0 0x10400000
|
||||
|
||||
#define EXYNOS7870_PA_BTS_CPU 0x104D0000
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||||
#define EXYNOS7870_PA_BTS_G3D 0x11440000
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_BTS_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue