mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 01:08:03 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
8
drivers/clk/mxs/Makefile
Normal file
8
drivers/clk/mxs/Makefile
Normal file
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@ -0,0 +1,8 @@
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#
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# Makefile for mxs specific clk
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#
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obj-y += clk.o clk-pll.o clk-ref.o clk-div.o clk-frac.o clk-ssp.o
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obj-$(CONFIG_SOC_IMX23) += clk-imx23.o
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obj-$(CONFIG_SOC_IMX28) += clk-imx28.o
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110
drivers/clk/mxs/clk-div.c
Normal file
110
drivers/clk/mxs/clk-div.c
Normal file
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@ -0,0 +1,110 @@
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include "clk.h"
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/**
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* struct clk_div - mxs integer divider clock
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* @divider: the parent class
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* @ops: pointer to clk_ops of parent class
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* @reg: register address
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* @busy: busy bit shift
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*
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* The mxs divider clock is a subclass of basic clk_divider with an
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* addtional busy bit.
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*/
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struct clk_div {
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struct clk_divider divider;
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const struct clk_ops *ops;
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void __iomem *reg;
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u8 busy;
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};
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static inline struct clk_div *to_clk_div(struct clk_hw *hw)
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{
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struct clk_divider *divider = container_of(hw, struct clk_divider, hw);
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return container_of(divider, struct clk_div, divider);
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}
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static unsigned long clk_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_div *div = to_clk_div(hw);
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return div->ops->recalc_rate(&div->divider.hw, parent_rate);
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}
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static long clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_div *div = to_clk_div(hw);
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return div->ops->round_rate(&div->divider.hw, rate, prate);
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}
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static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_div *div = to_clk_div(hw);
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int ret;
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ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate);
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if (!ret)
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ret = mxs_clk_wait(div->reg, div->busy);
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return ret;
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}
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static struct clk_ops clk_div_ops = {
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.recalc_rate = clk_div_recalc_rate,
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.round_rate = clk_div_round_rate,
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.set_rate = clk_div_set_rate,
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};
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struct clk *mxs_clk_div(const char *name, const char *parent_name,
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void __iomem *reg, u8 shift, u8 width, u8 busy)
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{
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struct clk_div *div;
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struct clk *clk;
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struct clk_init_data init;
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_div_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = (parent_name ? &parent_name: NULL);
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init.num_parents = (parent_name ? 1 : 0);
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div->reg = reg;
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div->busy = busy;
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div->divider.reg = reg;
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div->divider.shift = shift;
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div->divider.width = width;
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div->divider.flags = CLK_DIVIDER_ONE_BASED;
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div->divider.lock = &mxs_lock;
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div->divider.hw.init = &init;
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div->ops = &clk_divider_ops;
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clk = clk_register(NULL, &div->divider.hw);
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if (IS_ERR(clk))
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kfree(div);
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return clk;
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}
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139
drivers/clk/mxs/clk-frac.c
Normal file
139
drivers/clk/mxs/clk-frac.c
Normal file
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@ -0,0 +1,139 @@
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
|
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* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "clk.h"
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/**
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* struct clk_frac - mxs fractional divider clock
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* @hw: clk_hw for the fractional divider clock
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* @reg: register address
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* @shift: the divider bit shift
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* @width: the divider bit width
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* @busy: busy bit shift
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*
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* The clock is an adjustable fractional divider with a busy bit to wait
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* when the divider is adjusted.
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*/
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struct clk_frac {
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struct clk_hw hw;
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void __iomem *reg;
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u8 shift;
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u8 width;
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u8 busy;
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};
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#define to_clk_frac(_hw) container_of(_hw, struct clk_frac, hw)
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static unsigned long clk_frac_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_frac *frac = to_clk_frac(hw);
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u32 div;
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div = readl_relaxed(frac->reg) >> frac->shift;
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div &= (1 << frac->width) - 1;
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return (parent_rate >> frac->width) * div;
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}
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static long clk_frac_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_frac *frac = to_clk_frac(hw);
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unsigned long parent_rate = *prate;
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u32 div;
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u64 tmp;
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if (rate > parent_rate)
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return -EINVAL;
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tmp = rate;
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tmp <<= frac->width;
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do_div(tmp, parent_rate);
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div = tmp;
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if (!div)
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return -EINVAL;
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return (parent_rate >> frac->width) * div;
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}
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static int clk_frac_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_frac *frac = to_clk_frac(hw);
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unsigned long flags;
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u32 div, val;
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u64 tmp;
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if (rate > parent_rate)
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return -EINVAL;
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tmp = rate;
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tmp <<= frac->width;
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do_div(tmp, parent_rate);
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div = tmp;
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if (!div)
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return -EINVAL;
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spin_lock_irqsave(&mxs_lock, flags);
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val = readl_relaxed(frac->reg);
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val &= ~(((1 << frac->width) - 1) << frac->shift);
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val |= div << frac->shift;
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writel_relaxed(val, frac->reg);
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spin_unlock_irqrestore(&mxs_lock, flags);
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return mxs_clk_wait(frac->reg, frac->busy);
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}
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static struct clk_ops clk_frac_ops = {
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.recalc_rate = clk_frac_recalc_rate,
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.round_rate = clk_frac_round_rate,
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.set_rate = clk_frac_set_rate,
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};
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struct clk *mxs_clk_frac(const char *name, const char *parent_name,
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void __iomem *reg, u8 shift, u8 width, u8 busy)
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{
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struct clk_frac *frac;
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struct clk *clk;
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struct clk_init_data init;
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frac = kzalloc(sizeof(*frac), GFP_KERNEL);
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if (!frac)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_frac_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = (parent_name ? &parent_name: NULL);
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init.num_parents = (parent_name ? 1 : 0);
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frac->reg = reg;
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frac->shift = shift;
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frac->width = width;
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frac->busy = busy;
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frac->hw.init = &init;
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clk = clk_register(NULL, &frac->hw);
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if (IS_ERR(clk))
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kfree(frac);
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return clk;
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}
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177
drivers/clk/mxs/clk-imx23.c
Normal file
177
drivers/clk/mxs/clk-imx23.c
Normal file
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@ -0,0 +1,177 @@
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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||||
* The code contained herein is licensed under the GNU General Public
|
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* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/clk/mxs.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "clk.h"
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static void __iomem *clkctrl;
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static void __iomem *digctrl;
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#define CLKCTRL clkctrl
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#define DIGCTRL digctrl
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#define PLLCTRL0 (CLKCTRL + 0x0000)
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#define CPU (CLKCTRL + 0x0020)
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#define HBUS (CLKCTRL + 0x0030)
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#define XBUS (CLKCTRL + 0x0040)
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#define XTAL (CLKCTRL + 0x0050)
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#define PIX (CLKCTRL + 0x0060)
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#define SSP (CLKCTRL + 0x0070)
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#define GPMI (CLKCTRL + 0x0080)
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#define SPDIF (CLKCTRL + 0x0090)
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#define EMI (CLKCTRL + 0x00a0)
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#define SAIF (CLKCTRL + 0x00c0)
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#define TV (CLKCTRL + 0x00d0)
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#define ETM (CLKCTRL + 0x00e0)
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#define FRAC (CLKCTRL + 0x00f0)
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#define CLKSEQ (CLKCTRL + 0x0110)
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#define BP_CPU_INTERRUPT_WAIT 12
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#define BP_CLKSEQ_BYPASS_SAIF 0
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#define BP_CLKSEQ_BYPASS_SSP 5
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#define BP_SAIF_DIV_FRAC_EN 16
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#define BP_FRAC_IOFRAC 24
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static void __init clk_misc_init(void)
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{
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u32 val;
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/* Gate off cpu clock in WFI for power saving */
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writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
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/* Clear BYPASS for SAIF */
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writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR);
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/* SAIF has to use frac div for functional operation */
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val = readl_relaxed(SAIF);
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val |= 1 << BP_SAIF_DIV_FRAC_EN;
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writel_relaxed(val, SAIF);
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/*
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* Source ssp clock from ref_io than ref_xtal,
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* as ref_xtal only provides 24 MHz as maximum.
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*/
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writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR);
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/*
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* 480 MHz seems too high to be ssp clock source directly,
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* so set frac to get a 288 MHz ref_io.
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*/
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writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR);
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writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET);
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}
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|
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static const char *sel_pll[] __initconst = { "pll", "ref_xtal", };
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static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", };
|
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static const char *sel_pix[] __initconst = { "ref_pix", "ref_xtal", };
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static const char *sel_io[] __initconst = { "ref_io", "ref_xtal", };
|
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static const char *cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };
|
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static const char *emi_sels[] __initconst = { "emi_pll", "emi_xtal", };
|
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|
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enum imx23_clk {
|
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ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel,
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lcdif_sel, gpmi_sel, ssp_sel, emi_sel, cpu, etm_sel, cpu_pll,
|
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cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll,
|
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emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div,
|
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clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif,
|
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lcdif, etm, usb, usb_phy,
|
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clk_max
|
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};
|
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|
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static struct clk *clks[clk_max];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
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static enum imx23_clk clks_init_on[] __initdata = {
|
||||
cpu, hbus, xbus, emi, uart,
|
||||
};
|
||||
|
||||
static void __init mx23_clocks_init(struct device_node *np)
|
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{
|
||||
struct device_node *dcnp;
|
||||
u32 i;
|
||||
|
||||
dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl");
|
||||
digctrl = of_iomap(dcnp, 0);
|
||||
WARN_ON(!digctrl);
|
||||
of_node_put(dcnp);
|
||||
|
||||
clkctrl = of_iomap(np, 0);
|
||||
WARN_ON(!clkctrl);
|
||||
|
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clk_misc_init();
|
||||
|
||||
clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
|
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clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000);
|
||||
clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0);
|
||||
clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1);
|
||||
clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2);
|
||||
clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3);
|
||||
clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll));
|
||||
clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix));
|
||||
clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io));
|
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clks[ssp_sel] = mxs_clk_mux("ssp_sel", CLKSEQ, 5, 1, sel_io, ARRAY_SIZE(sel_io));
|
||||
clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 6, 1, emi_sels, ARRAY_SIZE(emi_sels));
|
||||
clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 7, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
|
||||
clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
|
||||
clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
|
||||
clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
|
||||
clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 29);
|
||||
clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
|
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clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", PIX, 0, 12, 29);
|
||||
clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29);
|
||||
clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
|
||||
clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
|
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clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
|
||||
clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29);
|
||||
clks[saif_div] = mxs_clk_frac("saif_div", "saif_sel", SAIF, 0, 16, 29);
|
||||
clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
|
||||
clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
|
||||
clks[adc] = mxs_clk_fixed_factor("adc", "clk32k", 1, 16);
|
||||
clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll", 1, 4);
|
||||
clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
|
||||
clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28);
|
||||
clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
|
||||
clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30);
|
||||
clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
|
||||
clks[ssp] = mxs_clk_gate("ssp", "ssp_div", SSP, 31);
|
||||
clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
|
||||
clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
|
||||
clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
|
||||
clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31);
|
||||
clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31);
|
||||
clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
|
||||
clks[usb] = mxs_clk_gate("usb", "usb_phy", DIGCTRL, 2);
|
||||
clks[usb_phy] = clk_register_gate(NULL, "usb_phy", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks); i++)
|
||||
if (IS_ERR(clks[i])) {
|
||||
pr_err("i.MX23 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clks[i]));
|
||||
return;
|
||||
}
|
||||
|
||||
clk_data.clks = clks;
|
||||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
|
||||
clk_prepare_enable(clks[clks_init_on[i]]);
|
||||
|
||||
}
|
||||
CLK_OF_DECLARE(imx23_clkctrl, "fsl,imx23-clkctrl", mx23_clocks_init);
|
||||
255
drivers/clk/mxs/clk-imx28.c
Normal file
255
drivers/clk/mxs/clk-imx28.c
Normal file
|
|
@ -0,0 +1,255 @@
|
|||
/*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk/mxs.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include "clk.h"
|
||||
|
||||
static void __iomem *clkctrl;
|
||||
#define CLKCTRL clkctrl
|
||||
|
||||
#define PLL0CTRL0 (CLKCTRL + 0x0000)
|
||||
#define PLL1CTRL0 (CLKCTRL + 0x0020)
|
||||
#define PLL2CTRL0 (CLKCTRL + 0x0040)
|
||||
#define CPU (CLKCTRL + 0x0050)
|
||||
#define HBUS (CLKCTRL + 0x0060)
|
||||
#define XBUS (CLKCTRL + 0x0070)
|
||||
#define XTAL (CLKCTRL + 0x0080)
|
||||
#define SSP0 (CLKCTRL + 0x0090)
|
||||
#define SSP1 (CLKCTRL + 0x00a0)
|
||||
#define SSP2 (CLKCTRL + 0x00b0)
|
||||
#define SSP3 (CLKCTRL + 0x00c0)
|
||||
#define GPMI (CLKCTRL + 0x00d0)
|
||||
#define SPDIF (CLKCTRL + 0x00e0)
|
||||
#define EMI (CLKCTRL + 0x00f0)
|
||||
#define SAIF0 (CLKCTRL + 0x0100)
|
||||
#define SAIF1 (CLKCTRL + 0x0110)
|
||||
#define LCDIF (CLKCTRL + 0x0120)
|
||||
#define ETM (CLKCTRL + 0x0130)
|
||||
#define ENET (CLKCTRL + 0x0140)
|
||||
#define FLEXCAN (CLKCTRL + 0x0160)
|
||||
#define FRAC0 (CLKCTRL + 0x01b0)
|
||||
#define FRAC1 (CLKCTRL + 0x01c0)
|
||||
#define CLKSEQ (CLKCTRL + 0x01d0)
|
||||
|
||||
#define BP_CPU_INTERRUPT_WAIT 12
|
||||
#define BP_SAIF_DIV_FRAC_EN 16
|
||||
#define BP_ENET_DIV_TIME 21
|
||||
#define BP_ENET_SLEEP 31
|
||||
#define BP_CLKSEQ_BYPASS_SAIF0 0
|
||||
#define BP_CLKSEQ_BYPASS_SSP0 3
|
||||
#define BP_FRAC0_IO1FRAC 16
|
||||
#define BP_FRAC0_IO0FRAC 24
|
||||
|
||||
static void __iomem *digctrl;
|
||||
#define DIGCTRL digctrl
|
||||
#define BP_SAIF_CLKMUX 10
|
||||
|
||||
/*
|
||||
* HW_SAIF_CLKMUX_SEL:
|
||||
* DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
|
||||
* clock pins selected for SAIF1 input clocks.
|
||||
* CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
|
||||
* SAIF0 clock inputs selected for SAIF1 input clocks.
|
||||
* EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
|
||||
* clocks.
|
||||
* EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
|
||||
* clocks.
|
||||
*/
|
||||
int mxs_saif_clkmux_select(unsigned int clkmux)
|
||||
{
|
||||
if (clkmux > 0x3)
|
||||
return -EINVAL;
|
||||
|
||||
writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR);
|
||||
writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init clk_misc_init(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* Gate off cpu clock in WFI for power saving */
|
||||
writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
|
||||
|
||||
/* 0 is a bad default value for a divider */
|
||||
writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET);
|
||||
|
||||
/* Clear BYPASS for SAIF */
|
||||
writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR);
|
||||
|
||||
/* SAIF has to use frac div for functional operation */
|
||||
val = readl_relaxed(SAIF0);
|
||||
val |= 1 << BP_SAIF_DIV_FRAC_EN;
|
||||
writel_relaxed(val, SAIF0);
|
||||
|
||||
val = readl_relaxed(SAIF1);
|
||||
val |= 1 << BP_SAIF_DIV_FRAC_EN;
|
||||
writel_relaxed(val, SAIF1);
|
||||
|
||||
/* Extra fec clock setting */
|
||||
val = readl_relaxed(ENET);
|
||||
val &= ~(1 << BP_ENET_SLEEP);
|
||||
writel_relaxed(val, ENET);
|
||||
|
||||
/*
|
||||
* Source ssp clock from ref_io than ref_xtal,
|
||||
* as ref_xtal only provides 24 MHz as maximum.
|
||||
*/
|
||||
writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR);
|
||||
|
||||
/*
|
||||
* 480 MHz seems too high to be ssp clock source directly,
|
||||
* so set frac0 to get a 288 MHz ref_io0 and ref_io1.
|
||||
*/
|
||||
val = readl_relaxed(FRAC0);
|
||||
val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
|
||||
val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
|
||||
writel_relaxed(val, FRAC0);
|
||||
}
|
||||
|
||||
static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", };
|
||||
static const char *sel_io0[] __initconst = { "ref_io0", "ref_xtal", };
|
||||
static const char *sel_io1[] __initconst = { "ref_io1", "ref_xtal", };
|
||||
static const char *sel_pix[] __initconst = { "ref_pix", "ref_xtal", };
|
||||
static const char *sel_gpmi[] __initconst = { "ref_gpmi", "ref_xtal", };
|
||||
static const char *sel_pll0[] __initconst = { "pll0", "ref_xtal", };
|
||||
static const char *cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };
|
||||
static const char *emi_sels[] __initconst = { "emi_pll", "emi_xtal", };
|
||||
static const char *ptp_sels[] __initconst = { "ref_xtal", "pll0", };
|
||||
|
||||
enum imx28_clk {
|
||||
ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1,
|
||||
ref_pix, ref_hsadc, ref_gpmi, saif0_sel, saif1_sel, gpmi_sel,
|
||||
ssp0_sel, ssp1_sel, ssp2_sel, ssp3_sel, emi_sel, etm_sel,
|
||||
lcdif_sel, cpu, ptp_sel, cpu_pll, cpu_xtal, hbus, xbus,
|
||||
ssp0_div, ssp1_div, ssp2_div, ssp3_div, gpmi_div, emi_pll,
|
||||
emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div,
|
||||
clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0,
|
||||
ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm,
|
||||
fec, can0, can1, usb0, usb1, usb0_phy, usb1_phy, enet_out,
|
||||
clk_max
|
||||
};
|
||||
|
||||
static struct clk *clks[clk_max];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static enum imx28_clk clks_init_on[] __initdata = {
|
||||
cpu, hbus, xbus, emi, uart,
|
||||
};
|
||||
|
||||
static void __init mx28_clocks_init(struct device_node *np)
|
||||
{
|
||||
struct device_node *dcnp;
|
||||
u32 i;
|
||||
|
||||
dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl");
|
||||
digctrl = of_iomap(dcnp, 0);
|
||||
WARN_ON(!digctrl);
|
||||
of_node_put(dcnp);
|
||||
|
||||
clkctrl = of_iomap(np, 0);
|
||||
WARN_ON(!clkctrl);
|
||||
|
||||
clk_misc_init();
|
||||
|
||||
clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
|
||||
clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000);
|
||||
clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000);
|
||||
clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000);
|
||||
clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0);
|
||||
clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1);
|
||||
clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2);
|
||||
clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3);
|
||||
clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0);
|
||||
clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1);
|
||||
clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2);
|
||||
clks[saif0_sel] = mxs_clk_mux("saif0_sel", CLKSEQ, 0, 1, sel_pll0, ARRAY_SIZE(sel_pll0));
|
||||
clks[saif1_sel] = mxs_clk_mux("saif1_sel", CLKSEQ, 1, 1, sel_pll0, ARRAY_SIZE(sel_pll0));
|
||||
clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 2, 1, sel_gpmi, ARRAY_SIZE(sel_gpmi));
|
||||
clks[ssp0_sel] = mxs_clk_mux("ssp0_sel", CLKSEQ, 3, 1, sel_io0, ARRAY_SIZE(sel_io0));
|
||||
clks[ssp1_sel] = mxs_clk_mux("ssp1_sel", CLKSEQ, 4, 1, sel_io0, ARRAY_SIZE(sel_io0));
|
||||
clks[ssp2_sel] = mxs_clk_mux("ssp2_sel", CLKSEQ, 5, 1, sel_io1, ARRAY_SIZE(sel_io1));
|
||||
clks[ssp3_sel] = mxs_clk_mux("ssp3_sel", CLKSEQ, 6, 1, sel_io1, ARRAY_SIZE(sel_io1));
|
||||
clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 7, 1, emi_sels, ARRAY_SIZE(emi_sels));
|
||||
clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
|
||||
clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 14, 1, sel_pix, ARRAY_SIZE(sel_pix));
|
||||
clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 18, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
|
||||
clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels));
|
||||
clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
|
||||
clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
|
||||
clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 31);
|
||||
clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
|
||||
clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29);
|
||||
clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29);
|
||||
clks[ssp2_div] = mxs_clk_div("ssp2_div", "ssp2_sel", SSP2, 0, 9, 29);
|
||||
clks[ssp3_div] = mxs_clk_div("ssp3_div", "ssp3_sel", SSP3, 0, 9, 29);
|
||||
clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
|
||||
clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
|
||||
clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
|
||||
clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29);
|
||||
clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29);
|
||||
clks[ptp] = mxs_clk_div("ptp", "ptp_sel", ENET, 21, 6, 27);
|
||||
clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29);
|
||||
clks[saif1_div] = mxs_clk_frac("saif1_div", "saif1_sel", SAIF1, 0, 16, 29);
|
||||
clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
|
||||
clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
|
||||
clks[lradc] = mxs_clk_fixed_factor("lradc", "clk32k", 1, 16);
|
||||
clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll0", 1, 4);
|
||||
clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
|
||||
clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
|
||||
clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
|
||||
clks[ssp0] = mxs_clk_gate("ssp0", "ssp0_div", SSP0, 31);
|
||||
clks[ssp1] = mxs_clk_gate("ssp1", "ssp1_div", SSP1, 31);
|
||||
clks[ssp2] = mxs_clk_gate("ssp2", "ssp2_div", SSP2, 31);
|
||||
clks[ssp3] = mxs_clk_gate("ssp3", "ssp3_div", SSP3, 31);
|
||||
clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
|
||||
clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
|
||||
clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
|
||||
clks[saif0] = mxs_clk_gate("saif0", "saif0_div", SAIF0, 31);
|
||||
clks[saif1] = mxs_clk_gate("saif1", "saif1_div", SAIF1, 31);
|
||||
clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31);
|
||||
clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
|
||||
clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30);
|
||||
clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30);
|
||||
clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28);
|
||||
clks[usb0] = mxs_clk_gate("usb0", "usb0_phy", DIGCTRL, 2);
|
||||
clks[usb1] = mxs_clk_gate("usb1", "usb1_phy", DIGCTRL, 16);
|
||||
clks[usb0_phy] = clk_register_gate(NULL, "usb0_phy", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock);
|
||||
clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock);
|
||||
clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks); i++)
|
||||
if (IS_ERR(clks[i])) {
|
||||
pr_err("i.MX28 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clks[i]));
|
||||
return;
|
||||
}
|
||||
|
||||
clk_data.clks = clks;
|
||||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
clk_register_clkdev(clks[enet_out], NULL, "enet_out");
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
|
||||
clk_prepare_enable(clks[clks_init_on[i]]);
|
||||
}
|
||||
CLK_OF_DECLARE(imx28_clkctrl, "fsl,imx28-clkctrl", mx28_clocks_init);
|
||||
116
drivers/clk/mxs/clk-pll.c
Normal file
116
drivers/clk/mxs/clk-pll.c
Normal file
|
|
@ -0,0 +1,116 @@
|
|||
/*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include "clk.h"
|
||||
|
||||
/**
|
||||
* struct clk_pll - mxs pll clock
|
||||
* @hw: clk_hw for the pll
|
||||
* @base: base address of the pll
|
||||
* @power: the shift of power bit
|
||||
* @rate: the clock rate of the pll
|
||||
*
|
||||
* The mxs pll is a fixed rate clock with power and gate control,
|
||||
* and the shift of gate bit is always 31.
|
||||
*/
|
||||
struct clk_pll {
|
||||
struct clk_hw hw;
|
||||
void __iomem *base;
|
||||
u8 power;
|
||||
unsigned long rate;
|
||||
};
|
||||
|
||||
#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
|
||||
|
||||
static int clk_pll_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_pll *pll = to_clk_pll(hw);
|
||||
|
||||
writel_relaxed(1 << pll->power, pll->base + SET);
|
||||
|
||||
udelay(10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void clk_pll_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_pll *pll = to_clk_pll(hw);
|
||||
|
||||
writel_relaxed(1 << pll->power, pll->base + CLR);
|
||||
}
|
||||
|
||||
static int clk_pll_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_pll *pll = to_clk_pll(hw);
|
||||
|
||||
writel_relaxed(1 << 31, pll->base + CLR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void clk_pll_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_pll *pll = to_clk_pll(hw);
|
||||
|
||||
writel_relaxed(1 << 31, pll->base + SET);
|
||||
}
|
||||
|
||||
static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_pll *pll = to_clk_pll(hw);
|
||||
|
||||
return pll->rate;
|
||||
}
|
||||
|
||||
static const struct clk_ops clk_pll_ops = {
|
||||
.prepare = clk_pll_prepare,
|
||||
.unprepare = clk_pll_unprepare,
|
||||
.enable = clk_pll_enable,
|
||||
.disable = clk_pll_disable,
|
||||
.recalc_rate = clk_pll_recalc_rate,
|
||||
};
|
||||
|
||||
struct clk *mxs_clk_pll(const char *name, const char *parent_name,
|
||||
void __iomem *base, u8 power, unsigned long rate)
|
||||
{
|
||||
struct clk_pll *pll;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
||||
if (!pll)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = &clk_pll_ops;
|
||||
init.flags = 0;
|
||||
init.parent_names = (parent_name ? &parent_name: NULL);
|
||||
init.num_parents = (parent_name ? 1 : 0);
|
||||
|
||||
pll->base = base;
|
||||
pll->rate = rate;
|
||||
pll->power = power;
|
||||
pll->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &pll->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(pll);
|
||||
|
||||
return clk;
|
||||
}
|
||||
154
drivers/clk/mxs/clk-ref.c
Normal file
154
drivers/clk/mxs/clk-ref.c
Normal file
|
|
@ -0,0 +1,154 @@
|
|||
/*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include "clk.h"
|
||||
|
||||
/**
|
||||
* struct clk_ref - mxs reference clock
|
||||
* @hw: clk_hw for the reference clock
|
||||
* @reg: register address
|
||||
* @idx: the index of the reference clock within the same register
|
||||
*
|
||||
* The mxs reference clock sources from pll. Every 4 reference clocks share
|
||||
* one register space, and @idx is used to identify them. Each reference
|
||||
* clock has a gate control and a fractional * divider. The rate is calculated
|
||||
* as pll rate * (18 / FRAC), where FRAC = 18 ~ 35.
|
||||
*/
|
||||
struct clk_ref {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
u8 idx;
|
||||
};
|
||||
|
||||
#define to_clk_ref(_hw) container_of(_hw, struct clk_ref, hw)
|
||||
|
||||
static int clk_ref_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_ref *ref = to_clk_ref(hw);
|
||||
|
||||
writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void clk_ref_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_ref *ref = to_clk_ref(hw);
|
||||
|
||||
writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET);
|
||||
}
|
||||
|
||||
static unsigned long clk_ref_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_ref *ref = to_clk_ref(hw);
|
||||
u64 tmp = parent_rate;
|
||||
u8 frac = (readl_relaxed(ref->reg) >> (ref->idx * 8)) & 0x3f;
|
||||
|
||||
tmp *= 18;
|
||||
do_div(tmp, frac);
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
||||
static long clk_ref_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
unsigned long parent_rate = *prate;
|
||||
u64 tmp = parent_rate;
|
||||
u8 frac;
|
||||
|
||||
tmp = tmp * 18 + rate / 2;
|
||||
do_div(tmp, rate);
|
||||
frac = tmp;
|
||||
|
||||
if (frac < 18)
|
||||
frac = 18;
|
||||
else if (frac > 35)
|
||||
frac = 35;
|
||||
|
||||
tmp = parent_rate;
|
||||
tmp *= 18;
|
||||
do_div(tmp, frac);
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
||||
static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_ref *ref = to_clk_ref(hw);
|
||||
unsigned long flags;
|
||||
u64 tmp = parent_rate;
|
||||
u32 val;
|
||||
u8 frac, shift = ref->idx * 8;
|
||||
|
||||
tmp = tmp * 18 + rate / 2;
|
||||
do_div(tmp, rate);
|
||||
frac = tmp;
|
||||
|
||||
if (frac < 18)
|
||||
frac = 18;
|
||||
else if (frac > 35)
|
||||
frac = 35;
|
||||
|
||||
spin_lock_irqsave(&mxs_lock, flags);
|
||||
|
||||
val = readl_relaxed(ref->reg);
|
||||
val &= ~(0x3f << shift);
|
||||
val |= frac << shift;
|
||||
writel_relaxed(val, ref->reg);
|
||||
|
||||
spin_unlock_irqrestore(&mxs_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops clk_ref_ops = {
|
||||
.enable = clk_ref_enable,
|
||||
.disable = clk_ref_disable,
|
||||
.recalc_rate = clk_ref_recalc_rate,
|
||||
.round_rate = clk_ref_round_rate,
|
||||
.set_rate = clk_ref_set_rate,
|
||||
};
|
||||
|
||||
struct clk *mxs_clk_ref(const char *name, const char *parent_name,
|
||||
void __iomem *reg, u8 idx)
|
||||
{
|
||||
struct clk_ref *ref;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
ref = kzalloc(sizeof(*ref), GFP_KERNEL);
|
||||
if (!ref)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = &clk_ref_ops;
|
||||
init.flags = 0;
|
||||
init.parent_names = (parent_name ? &parent_name: NULL);
|
||||
init.num_parents = (parent_name ? 1 : 0);
|
||||
|
||||
ref->reg = reg;
|
||||
ref->idx = idx;
|
||||
ref->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &ref->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(ref);
|
||||
|
||||
return clk;
|
||||
}
|
||||
62
drivers/clk/mxs/clk-ssp.c
Normal file
62
drivers/clk/mxs/clk-ssp.c
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Copyright 2012 DENX Software Engineering, GmbH
|
||||
*
|
||||
* Pulled from code:
|
||||
* Portions copyright (C) 2003 Russell King, PXA MMCI Driver
|
||||
* Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
|
||||
*
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc.
|
||||
* Copyright 2009-2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/spi/mxs-spi.h>
|
||||
|
||||
void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate)
|
||||
{
|
||||
unsigned int ssp_clk, ssp_sck;
|
||||
u32 clock_divide, clock_rate;
|
||||
u32 val;
|
||||
|
||||
ssp_clk = clk_get_rate(ssp->clk);
|
||||
|
||||
for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
|
||||
clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
|
||||
clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
|
||||
if (clock_rate <= 255)
|
||||
break;
|
||||
}
|
||||
|
||||
if (clock_divide > 254) {
|
||||
dev_err(ssp->dev,
|
||||
"%s: cannot set clock to %d\n", __func__, rate);
|
||||
return;
|
||||
}
|
||||
|
||||
ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
|
||||
|
||||
val = readl(ssp->base + HW_SSP_TIMING(ssp));
|
||||
val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
|
||||
val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
|
||||
val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
|
||||
writel(val, ssp->base + HW_SSP_TIMING(ssp));
|
||||
|
||||
ssp->clk_rate = ssp_sck;
|
||||
|
||||
dev_dbg(ssp->dev,
|
||||
"%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
|
||||
__func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mxs_ssp_set_clk_rate);
|
||||
29
drivers/clk/mxs/clk.c
Normal file
29
drivers/clk/mxs/clk.c
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include "clk.h"
|
||||
|
||||
DEFINE_SPINLOCK(mxs_lock);
|
||||
|
||||
int mxs_clk_wait(void __iomem *reg, u8 shift)
|
||||
{
|
||||
unsigned long timeout = jiffies + msecs_to_jiffies(10);
|
||||
|
||||
while (readl_relaxed(reg) & (1 << shift))
|
||||
if (time_after(jiffies, timeout))
|
||||
return -ETIMEDOUT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
66
drivers/clk/mxs/clk.h
Normal file
66
drivers/clk/mxs/clk.h
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#ifndef __MXS_CLK_H
|
||||
#define __MXS_CLK_H
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#define SET 0x4
|
||||
#define CLR 0x8
|
||||
|
||||
extern spinlock_t mxs_lock;
|
||||
|
||||
int mxs_clk_wait(void __iomem *reg, u8 shift);
|
||||
|
||||
struct clk *mxs_clk_pll(const char *name, const char *parent_name,
|
||||
void __iomem *base, u8 power, unsigned long rate);
|
||||
|
||||
struct clk *mxs_clk_ref(const char *name, const char *parent_name,
|
||||
void __iomem *reg, u8 idx);
|
||||
|
||||
struct clk *mxs_clk_div(const char *name, const char *parent_name,
|
||||
void __iomem *reg, u8 shift, u8 width, u8 busy);
|
||||
|
||||
struct clk *mxs_clk_frac(const char *name, const char *parent_name,
|
||||
void __iomem *reg, u8 shift, u8 width, u8 busy);
|
||||
|
||||
static inline struct clk *mxs_clk_fixed(const char *name, int rate)
|
||||
{
|
||||
return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
|
||||
}
|
||||
|
||||
static inline struct clk *mxs_clk_gate(const char *name,
|
||||
const char *parent_name, void __iomem *reg, u8 shift)
|
||||
{
|
||||
return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT,
|
||||
reg, shift, CLK_GATE_SET_TO_DISABLE,
|
||||
&mxs_lock);
|
||||
}
|
||||
|
||||
static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg,
|
||||
u8 shift, u8 width, const char **parent_names, int num_parents)
|
||||
{
|
||||
return clk_register_mux(NULL, name, parent_names, num_parents,
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
reg, shift, width, 0, &mxs_lock);
|
||||
}
|
||||
|
||||
static inline struct clk *mxs_clk_fixed_factor(const char *name,
|
||||
const char *parent_name, unsigned int mult, unsigned int div)
|
||||
{
|
||||
return clk_register_fixed_factor(NULL, name, parent_name,
|
||||
CLK_SET_RATE_PARENT, mult, div);
|
||||
}
|
||||
|
||||
#endif /* __MXS_CLK_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue