mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
2
drivers/clk/pxa/Makefile
Normal file
2
drivers/clk/pxa/Makefile
Normal file
|
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@ -0,0 +1,2 @@
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obj-y += clk-pxa.o
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obj-$(CONFIG_PXA27x) += clk-pxa27x.o
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97
drivers/clk/pxa/clk-pxa.c
Normal file
97
drivers/clk/pxa/clk-pxa.c
Normal file
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@ -0,0 +1,97 @@
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/*
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* Marvell PXA family clocks
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*
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* Copyright (C) 2014 Robert Jarzmik
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*
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* Common clock code for PXA clocks ("CKEN" type clocks + DT)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <dt-bindings/clock/pxa-clock.h>
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#include "clk-pxa.h"
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DEFINE_SPINLOCK(lock);
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static struct clk *pxa_clocks[CLK_MAX];
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static struct clk_onecell_data onecell_data = {
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.clks = pxa_clocks,
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.clk_num = CLK_MAX,
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};
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#define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk_cken, hw)
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static unsigned long cken_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct pxa_clk_cken *pclk = to_pxa_clk(hw);
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struct clk_fixed_factor *fix;
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if (!pclk->is_in_low_power || pclk->is_in_low_power())
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fix = &pclk->lp;
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else
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fix = &pclk->hp;
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fix->hw.clk = hw->clk;
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return clk_fixed_factor_ops.recalc_rate(&fix->hw, parent_rate);
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}
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static struct clk_ops cken_rate_ops = {
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.recalc_rate = cken_recalc_rate,
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};
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static u8 cken_get_parent(struct clk_hw *hw)
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{
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struct pxa_clk_cken *pclk = to_pxa_clk(hw);
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if (!pclk->is_in_low_power)
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return 0;
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return pclk->is_in_low_power() ? 0 : 1;
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}
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static struct clk_ops cken_mux_ops = {
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.get_parent = cken_get_parent,
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.set_parent = dummy_clk_set_parent,
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};
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void __init clkdev_pxa_register(int ckid, const char *con_id,
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const char *dev_id, struct clk *clk)
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{
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if (!IS_ERR(clk) && (ckid != CLK_NONE))
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pxa_clocks[ckid] = clk;
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if (!IS_ERR(clk))
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clk_register_clkdev(clk, con_id, dev_id);
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}
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int __init clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks)
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{
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int i;
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struct pxa_clk_cken *pclk;
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struct clk *clk;
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for (i = 0; i < nb_clks; i++) {
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pclk = clks + i;
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pclk->gate.lock = &lock;
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clk = clk_register_composite(NULL, pclk->name,
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pclk->parent_names, 2,
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&pclk->hw, &cken_mux_ops,
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&pclk->hw, &cken_rate_ops,
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&pclk->gate.hw, &clk_gate_ops,
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pclk->flags);
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clkdev_pxa_register(pclk->ckid, pclk->con_id, pclk->dev_id,
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clk);
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}
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return 0;
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}
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static void __init pxa_dt_clocks_init(struct device_node *np)
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{
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of_clk_add_provider(np, of_clk_src_onecell_get, &onecell_data);
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}
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CLK_OF_DECLARE(pxa_clks, "marvell,pxa-clocks", pxa_dt_clocks_init);
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107
drivers/clk/pxa/clk-pxa.h
Normal file
107
drivers/clk/pxa/clk-pxa.h
Normal file
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@ -0,0 +1,107 @@
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/*
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* Marvell PXA family clocks
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*
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* Copyright (C) 2014 Robert Jarzmik
|
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*
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* Common clock code for PXA clocks ("CKEN" type clocks + DT)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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*/
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#ifndef _CLK_PXA_
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#define _CLK_PXA_
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#define PARENTS(name) \
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static const char *name ## _parents[] __initconst
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#define MUX_RO_RATE_RO_OPS(name, clk_name) \
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static struct clk_hw name ## _mux_hw; \
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static struct clk_hw name ## _rate_hw; \
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static struct clk_ops name ## _mux_ops = { \
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.get_parent = name ## _get_parent, \
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.set_parent = dummy_clk_set_parent, \
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}; \
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static struct clk_ops name ## _rate_ops = { \
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.recalc_rate = name ## _get_rate, \
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}; \
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static struct clk *clk_register_ ## name(void) \
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{ \
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return clk_register_composite(NULL, clk_name, \
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name ## _parents, \
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ARRAY_SIZE(name ## _parents), \
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&name ## _mux_hw, &name ## _mux_ops, \
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&name ## _rate_hw, &name ## _rate_ops, \
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NULL, NULL, CLK_GET_RATE_NOCACHE); \
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}
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#define RATE_RO_OPS(name, clk_name) \
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static struct clk_hw name ## _rate_hw; \
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static struct clk_ops name ## _rate_ops = { \
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.recalc_rate = name ## _get_rate, \
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}; \
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static struct clk *clk_register_ ## name(void) \
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{ \
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return clk_register_composite(NULL, clk_name, \
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name ## _parents, \
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ARRAY_SIZE(name ## _parents), \
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NULL, NULL, \
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&name ## _rate_hw, &name ## _rate_ops, \
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NULL, NULL, CLK_GET_RATE_NOCACHE); \
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}
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/*
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* CKEN clock type
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* This clock takes it source from 2 possible parents :
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* - a low power parent
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* - a normal parent
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*
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* +------------+ +-----------+
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* | Low Power | --- | x mult_lp |
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* | Clock | | / div_lp |\
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* +------------+ +-----------+ \+-----+ +-----------+
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* | Mux |---| CKEN gate |
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* +------------+ +-----------+ /+-----+ +-----------+
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* | High Power | | x mult_hp |/
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* | Clock | --- | / div_hp |
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* +------------+ +-----------+
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*/
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struct pxa_clk_cken {
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struct clk_hw hw;
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int ckid;
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const char *name;
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const char *dev_id;
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const char *con_id;
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const char **parent_names;
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struct clk_fixed_factor lp;
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struct clk_fixed_factor hp;
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struct clk_gate gate;
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bool (*is_in_low_power)(void);
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const unsigned long flags;
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};
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#define PXA_CKEN(_dev_id, _con_id, _name, parents, _mult_lp, _div_lp, \
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_mult_hp, _div_hp, is_lp, _cken_reg, _cken_bit, flag) \
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{ .ckid = CLK_ ## _name, .name = #_name, \
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.dev_id = _dev_id, .con_id = _con_id, .parent_names = parents,\
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.lp = { .mult = _mult_lp, .div = _div_lp }, \
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.hp = { .mult = _mult_hp, .div = _div_hp }, \
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.is_in_low_power = is_lp, \
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.gate = { .reg = (void __iomem *)_cken_reg, .bit_idx = _cken_bit }, \
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.flags = flag, \
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}
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#define PXA_CKEN_1RATE(dev_id, con_id, name, parents, cken_reg, \
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cken_bit, flag) \
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PXA_CKEN(dev_id, con_id, name, parents, 1, 1, 1, 1, \
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NULL, cken_reg, cken_bit, flag)
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static int dummy_clk_set_parent(struct clk_hw *hw, u8 index)
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{
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return 0;
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}
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extern void clkdev_pxa_register(int ckid, const char *con_id,
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const char *dev_id, struct clk *clk);
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extern int clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks);
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#endif
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370
drivers/clk/pxa/clk-pxa27x.c
Normal file
370
drivers/clk/pxa/clk-pxa27x.c
Normal file
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@ -0,0 +1,370 @@
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/*
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* Marvell PXA27x family clocks
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*
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* Copyright (C) 2014 Robert Jarzmik
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*
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* Heavily inspired from former arch/arm/mach-pxa/clock.c.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
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*
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*/
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#include <linux/clk-provider.h>
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#include <mach/pxa2xx-regs.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <dt-bindings/clock/pxa-clock.h>
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#include "clk-pxa.h"
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#define KHz 1000
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#define MHz (1000 * 1000)
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enum {
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PXA_CORE_13Mhz = 0,
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PXA_CORE_RUN,
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PXA_CORE_TURBO,
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};
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enum {
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PXA_BUS_13Mhz = 0,
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PXA_BUS_RUN,
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};
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enum {
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PXA_LCD_13Mhz = 0,
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PXA_LCD_RUN,
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};
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enum {
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PXA_MEM_13Mhz = 0,
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PXA_MEM_SYSTEM_BUS,
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PXA_MEM_RUN,
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};
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static const char * const get_freq_khz[] = {
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"core", "run", "cpll", "memory",
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"system_bus"
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};
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/*
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* Get the clock frequency as reflected by CCSR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int pxa27x_get_clk_frequency_khz(int info)
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{
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struct clk *clk;
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unsigned long clks[5];
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int i;
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for (i = 0; i < 5; i++) {
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clk = clk_get(NULL, get_freq_khz[i]);
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if (IS_ERR(clk)) {
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clks[i] = 0;
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} else {
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clks[i] = clk_get_rate(clk);
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clk_put(clk);
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}
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}
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if (info) {
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pr_info("Run Mode clock: %ld.%02ldMHz\n",
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clks[1] / 1000000, (clks[1] % 1000000) / 10000);
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pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
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clks[2] / 1000000, (clks[2] % 1000000) / 10000);
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pr_info("Memory clock: %ld.%02ldMHz\n",
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clks[3] / 1000000, (clks[3] % 1000000) / 10000);
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pr_info("System bus clock: %ld.%02ldMHz\n",
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clks[4] / 1000000, (clks[4] % 1000000) / 10000);
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}
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return (unsigned int)clks[0];
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}
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bool pxa27x_is_ppll_disabled(void)
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{
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unsigned long ccsr = CCSR;
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return ccsr & (1 << CCCR_PPDIS_BIT);
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}
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#define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \
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bit, is_lp, flags) \
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PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \
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is_lp, &CKEN, CKEN_ ## bit, flags)
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#define PXA27X_PBUS_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
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PXA27X_CKEN(dev_id, con_id, pxa27x_pbus_parents, mult_hp, \
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div_hp, bit, pxa27x_is_ppll_disabled, 0)
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PARENTS(pxa27x_pbus) = { "osc_13mhz", "ppll_312mhz" };
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PARENTS(pxa27x_sbus) = { "system_bus", "system_bus" };
|
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PARENTS(pxa27x_32Mhz_bus) = { "osc_32_768khz", "osc_32_768khz" };
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PARENTS(pxa27x_lcd_bus) = { "lcd_base", "lcd_base" };
|
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PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };
|
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#define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \
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PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
|
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&CKEN, CKEN_ ## bit, 0)
|
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#define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \
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PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
|
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&CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
|
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|
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static struct pxa_clk_cken pxa27x_clocks[] = {
|
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PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
|
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PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1),
|
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PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1),
|
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PXA27X_PBUS_CKEN("pxa2xx-i2s", NULL, I2S, 2, 51, 0),
|
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PXA27X_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 19, 0),
|
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PXA27X_PBUS_CKEN("pxa27x-udc", NULL, USB, 2, 13, 5),
|
||||
PXA27X_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC, 2, 32, 0),
|
||||
PXA27X_PBUS_CKEN("pxa2xx-ir", "FICPCLK", FICP, 2, 13, 0),
|
||||
PXA27X_PBUS_CKEN("pxa27x-ohci", NULL, USBHOST, 2, 13, 0),
|
||||
PXA27X_PBUS_CKEN("pxa2xx-i2c.1", NULL, PWRI2C, 1, 24, 0),
|
||||
PXA27X_PBUS_CKEN("pxa27x-ssp.0", NULL, SSP1, 1, 24, 0),
|
||||
PXA27X_PBUS_CKEN("pxa27x-ssp.1", NULL, SSP2, 1, 24, 0),
|
||||
PXA27X_PBUS_CKEN("pxa27x-ssp.2", NULL, SSP3, 1, 24, 0),
|
||||
PXA27X_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 24, 0),
|
||||
PXA27X_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 24, 0),
|
||||
PXA27X_PBUS_CKEN(NULL, "MSLCLK", MSL, 2, 13, 0),
|
||||
PXA27X_PBUS_CKEN(NULL, "USIMCLK", USIM, 2, 13, 0),
|
||||
PXA27X_PBUS_CKEN(NULL, "MSTKCLK", MEMSTK, 2, 32, 0),
|
||||
PXA27X_PBUS_CKEN(NULL, "AC97CLK", AC97, 1, 1, 0),
|
||||
PXA27X_PBUS_CKEN(NULL, "AC97CONFCLK", AC97CONF, 1, 1, 0),
|
||||
PXA27X_PBUS_CKEN(NULL, "OSTIMER0", OSTIMER, 1, 96, 0),
|
||||
|
||||
PXA27X_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
|
||||
pxa27x_32Mhz_bus_parents, 0),
|
||||
PXA27X_CKEN_1RATE(NULL, "IMCLK", IM, pxa27x_sbus_parents, 0),
|
||||
PXA27X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, pxa27x_lcd_bus_parents, 0),
|
||||
PXA27X_CKEN_1RATE("pxa27x-camera.0", NULL, CAMERA,
|
||||
pxa27x_lcd_bus_parents, 0),
|
||||
PXA27X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
|
||||
pxa27x_membus_parents, 0),
|
||||
|
||||
};
|
||||
|
||||
static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned long clkcfg;
|
||||
unsigned int t, ht;
|
||||
unsigned int l, L, n2, N;
|
||||
unsigned long ccsr = CCSR;
|
||||
|
||||
asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
|
||||
t = clkcfg & (1 << 0);
|
||||
ht = clkcfg & (1 << 2);
|
||||
|
||||
l = ccsr & CCSR_L_MASK;
|
||||
n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
|
||||
L = l * parent_rate;
|
||||
N = (L * n2) / 2;
|
||||
|
||||
return t ? N : L;
|
||||
}
|
||||
PARENTS(clk_pxa27x_cpll) = { "osc_13mhz" };
|
||||
RATE_RO_OPS(clk_pxa27x_cpll, "cpll");
|
||||
|
||||
static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned int l, osc_forced;
|
||||
unsigned long ccsr = CCSR;
|
||||
unsigned long cccr = CCCR;
|
||||
|
||||
l = ccsr & CCSR_L_MASK;
|
||||
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
|
||||
if (osc_forced) {
|
||||
if (cccr & (1 << CCCR_LCD_26_BIT))
|
||||
return parent_rate * 2;
|
||||
else
|
||||
return parent_rate;
|
||||
}
|
||||
|
||||
if (l <= 7)
|
||||
return parent_rate;
|
||||
if (l <= 16)
|
||||
return parent_rate / 2;
|
||||
return parent_rate / 4;
|
||||
}
|
||||
|
||||
static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
unsigned int osc_forced;
|
||||
unsigned long ccsr = CCSR;
|
||||
|
||||
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
|
||||
if (osc_forced)
|
||||
return PXA_LCD_13Mhz;
|
||||
else
|
||||
return PXA_LCD_RUN;
|
||||
}
|
||||
|
||||
PARENTS(clk_pxa27x_lcd_base) = { "osc_13mhz", "run" };
|
||||
MUX_RO_RATE_RO_OPS(clk_pxa27x_lcd_base, "lcd_base");
|
||||
|
||||
static void __init pxa27x_register_plls(void)
|
||||
{
|
||||
clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
|
||||
13 * MHz);
|
||||
clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
|
||||
32768 * KHz);
|
||||
clk_register_fixed_rate(NULL, "clk_dummy", NULL, CLK_IS_ROOT, 0);
|
||||
clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
|
||||
}
|
||||
|
||||
static unsigned long clk_pxa27x_core_get_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned long clkcfg;
|
||||
unsigned int t, ht, b, osc_forced;
|
||||
unsigned long ccsr = CCSR;
|
||||
|
||||
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
|
||||
asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
|
||||
t = clkcfg & (1 << 0);
|
||||
ht = clkcfg & (1 << 2);
|
||||
b = clkcfg & (1 << 3);
|
||||
|
||||
if (osc_forced)
|
||||
return parent_rate;
|
||||
if (ht)
|
||||
return parent_rate / 2;
|
||||
else
|
||||
return parent_rate;
|
||||
}
|
||||
|
||||
static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
unsigned long clkcfg;
|
||||
unsigned int t, ht, b, osc_forced;
|
||||
unsigned long ccsr = CCSR;
|
||||
|
||||
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
|
||||
if (osc_forced)
|
||||
return PXA_CORE_13Mhz;
|
||||
|
||||
asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
|
||||
t = clkcfg & (1 << 0);
|
||||
ht = clkcfg & (1 << 2);
|
||||
b = clkcfg & (1 << 3);
|
||||
|
||||
if (ht || t)
|
||||
return PXA_CORE_TURBO;
|
||||
return PXA_CORE_RUN;
|
||||
}
|
||||
PARENTS(clk_pxa27x_core) = { "osc_13mhz", "run", "cpll" };
|
||||
MUX_RO_RATE_RO_OPS(clk_pxa27x_core, "core");
|
||||
|
||||
static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned long ccsr = CCSR;
|
||||
unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
|
||||
|
||||
return (parent_rate / n2) * 2;
|
||||
}
|
||||
PARENTS(clk_pxa27x_run) = { "cpll" };
|
||||
RATE_RO_OPS(clk_pxa27x_run, "run");
|
||||
|
||||
static void __init pxa27x_register_core(void)
|
||||
{
|
||||
clk_register_clk_pxa27x_cpll();
|
||||
clk_register_clk_pxa27x_run();
|
||||
|
||||
clkdev_pxa_register(CLK_CORE, "core", NULL,
|
||||
clk_register_clk_pxa27x_core());
|
||||
}
|
||||
|
||||
static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned long clkcfg;
|
||||
unsigned int b, osc_forced;
|
||||
unsigned long ccsr = CCSR;
|
||||
|
||||
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
|
||||
asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
|
||||
b = clkcfg & (1 << 3);
|
||||
|
||||
if (osc_forced)
|
||||
return parent_rate;
|
||||
if (b)
|
||||
return parent_rate / 2;
|
||||
else
|
||||
return parent_rate;
|
||||
}
|
||||
|
||||
static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
unsigned int osc_forced;
|
||||
unsigned long ccsr = CCSR;
|
||||
|
||||
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
|
||||
if (osc_forced)
|
||||
return PXA_BUS_13Mhz;
|
||||
else
|
||||
return PXA_BUS_RUN;
|
||||
}
|
||||
|
||||
PARENTS(clk_pxa27x_system_bus) = { "osc_13mhz", "run" };
|
||||
MUX_RO_RATE_RO_OPS(clk_pxa27x_system_bus, "system_bus");
|
||||
|
||||
static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned int a, l, osc_forced;
|
||||
unsigned long cccr = CCCR;
|
||||
unsigned long ccsr = CCSR;
|
||||
|
||||
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
|
||||
a = cccr & (1 << CCCR_A_BIT);
|
||||
l = ccsr & CCSR_L_MASK;
|
||||
|
||||
if (osc_forced || a)
|
||||
return parent_rate;
|
||||
if (l <= 10)
|
||||
return parent_rate;
|
||||
if (l <= 20)
|
||||
return parent_rate / 2;
|
||||
return parent_rate / 4;
|
||||
}
|
||||
|
||||
static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
unsigned int osc_forced, a;
|
||||
unsigned long cccr = CCCR;
|
||||
unsigned long ccsr = CCSR;
|
||||
|
||||
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
|
||||
a = cccr & (1 << CCCR_A_BIT);
|
||||
if (osc_forced)
|
||||
return PXA_MEM_13Mhz;
|
||||
if (a)
|
||||
return PXA_MEM_SYSTEM_BUS;
|
||||
else
|
||||
return PXA_MEM_RUN;
|
||||
}
|
||||
|
||||
PARENTS(clk_pxa27x_memory) = { "osc_13mhz", "system_bus", "run" };
|
||||
MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory");
|
||||
|
||||
static void __init pxa27x_base_clocks_init(void)
|
||||
{
|
||||
pxa27x_register_plls();
|
||||
pxa27x_register_core();
|
||||
clk_register_clk_pxa27x_system_bus();
|
||||
clk_register_clk_pxa27x_memory();
|
||||
clk_register_clk_pxa27x_lcd_base();
|
||||
}
|
||||
|
||||
static int __init pxa27x_clocks_init(void)
|
||||
{
|
||||
pxa27x_base_clocks_init();
|
||||
return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks));
|
||||
}
|
||||
postcore_initcall(pxa27x_clocks_init);
|
||||
Loading…
Add table
Add a link
Reference in a new issue