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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
236
drivers/cpufreq/exynos4x12-cpufreq.c
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236
drivers/cpufreq/exynos4x12-cpufreq.c
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@ -0,0 +1,236 @@
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/*
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* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4X12 - CPU frequency scaling support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/cpufreq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "exynos-cpufreq.h"
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static struct clk *cpu_clk;
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static struct clk *moutcore;
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static struct clk *mout_mpll;
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static struct clk *mout_apll;
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static struct exynos_dvfs_info *cpufreq;
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static unsigned int exynos4x12_volt_table[] = {
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1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
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1000000, 987500, 975000, 950000, 925000, 900000, 900000
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};
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static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
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{CPUFREQ_BOOST_FREQ, L0, 1500 * 1000},
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{0, L1, 1400 * 1000},
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{0, L2, 1300 * 1000},
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{0, L3, 1200 * 1000},
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{0, L4, 1100 * 1000},
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{0, L5, 1000 * 1000},
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{0, L6, 900 * 1000},
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{0, L7, 800 * 1000},
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{0, L8, 700 * 1000},
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{0, L9, 600 * 1000},
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{0, L10, 500 * 1000},
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{0, L11, 400 * 1000},
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{0, L12, 300 * 1000},
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{0, L13, 200 * 1000},
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{0, 0, CPUFREQ_TABLE_END},
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};
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static struct apll_freq *apll_freq_4x12;
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static struct apll_freq apll_freq_4212[] = {
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/*
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* values:
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* freq
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* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
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* clock divider for COPY, HPM, RESERVED
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* PLL M, P, S
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*/
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APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
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APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
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APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
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APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
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APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
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APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
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APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
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APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
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APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
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APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
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APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
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APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
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APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
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APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
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};
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static struct apll_freq apll_freq_4412[] = {
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/*
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* values:
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* freq
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* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
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* clock divider for COPY, HPM, CORES
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* PLL M, P, S
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*/
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APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
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APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
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APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
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APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
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APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
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APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
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APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
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APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
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APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
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APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
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APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
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APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
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APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
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APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
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};
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static void exynos4x12_set_clkdiv(unsigned int div_index)
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{
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unsigned int tmp;
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/* Change Divider - CPU0 */
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tmp = apll_freq_4x12[div_index].clk_div_cpu0;
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__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
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while (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU)
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& 0x11111111)
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cpu_relax();
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/* Change Divider - CPU1 */
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tmp = apll_freq_4x12[div_index].clk_div_cpu1;
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__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
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do {
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cpu_relax();
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tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
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} while (tmp != 0x0);
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}
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static void exynos4x12_set_apll(unsigned int index)
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{
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unsigned int tmp, freq = apll_freq_4x12[index].freq;
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/* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
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clk_set_parent(moutcore, mout_mpll);
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do {
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cpu_relax();
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tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
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>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
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tmp &= 0x7;
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} while (tmp != 0x2);
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clk_set_rate(mout_apll, freq * 1000);
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/* MUX_CORE_SEL = APLL */
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clk_set_parent(moutcore, mout_apll);
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do {
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cpu_relax();
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tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
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tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
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} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
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}
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static void exynos4x12_set_frequency(unsigned int old_index,
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unsigned int new_index)
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{
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if (old_index > new_index) {
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exynos4x12_set_clkdiv(new_index);
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exynos4x12_set_apll(new_index);
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} else if (old_index < new_index) {
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exynos4x12_set_apll(new_index);
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exynos4x12_set_clkdiv(new_index);
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}
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}
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int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
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{
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struct device_node *np;
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unsigned long rate;
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/*
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* HACK: This is a temporary workaround to get access to clock
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* controller registers directly and remove static mappings and
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* dependencies on platform headers. It is necessary to enable
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* Exynos multi-platform support and will be removed together with
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* this whole driver as soon as Exynos gets migrated to use
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* cpufreq-dt driver.
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*/
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np = of_find_compatible_node(NULL, NULL, "samsung,exynos4412-clock");
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if (!np) {
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pr_err("%s: failed to find clock controller DT node\n",
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__func__);
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return -ENODEV;
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}
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info->cmu_regs = of_iomap(np, 0);
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if (!info->cmu_regs) {
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pr_err("%s: failed to map CMU registers\n", __func__);
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return -EFAULT;
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}
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cpu_clk = clk_get(NULL, "armclk");
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if (IS_ERR(cpu_clk))
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return PTR_ERR(cpu_clk);
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moutcore = clk_get(NULL, "moutcore");
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if (IS_ERR(moutcore))
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goto err_moutcore;
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mout_mpll = clk_get(NULL, "mout_mpll");
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if (IS_ERR(mout_mpll))
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goto err_mout_mpll;
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rate = clk_get_rate(mout_mpll) / 1000;
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mout_apll = clk_get(NULL, "mout_apll");
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if (IS_ERR(mout_apll))
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goto err_mout_apll;
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if (info->type == EXYNOS_SOC_4212)
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apll_freq_4x12 = apll_freq_4212;
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else
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apll_freq_4x12 = apll_freq_4412;
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info->mpll_freq_khz = rate;
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/* 800Mhz */
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info->pll_safe_idx = L7;
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info->cpu_clk = cpu_clk;
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info->volt_table = exynos4x12_volt_table;
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info->freq_table = exynos4x12_freq_table;
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info->set_freq = exynos4x12_set_frequency;
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cpufreq = info;
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return 0;
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err_mout_apll:
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clk_put(mout_mpll);
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err_mout_mpll:
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clk_put(moutcore);
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err_moutcore:
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clk_put(cpu_clk);
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pr_debug("%s: failed initialization\n", __func__);
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return -EINVAL;
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}
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