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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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2
drivers/crypto/amcc/Makefile Normal file
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obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += crypto4xx.o
crypto4xx-y := crypto4xx_core.o crypto4xx_alg.o crypto4xx_sa.o

295
drivers/crypto/amcc/crypto4xx_alg.c Normal file
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/**
* AMCC SoC PPC4xx Crypto Driver
*
* Copyright (c) 2008 Applied Micro Circuits Corporation.
* All rights reserved. James Hsiao <jhsiao@amcc.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* This file implements the Linux crypto algorithms.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/spinlock_types.h>
#include <linux/scatterlist.h>
#include <linux/crypto.h>
#include <linux/hash.h>
#include <crypto/internal/hash.h>
#include <linux/dma-mapping.h>
#include <crypto/algapi.h>
#include <crypto/aes.h>
#include <crypto/sha.h>
#include "crypto4xx_reg_def.h"
#include "crypto4xx_sa.h"
#include "crypto4xx_core.h"
static void set_dynamic_sa_command_0(struct dynamic_sa_ctl *sa, u32 save_h,
u32 save_iv, u32 ld_h, u32 ld_iv,
u32 hdr_proc, u32 h, u32 c, u32 pad_type,
u32 op_grp, u32 op, u32 dir)
{
sa->sa_command_0.w = 0;
sa->sa_command_0.bf.save_hash_state = save_h;
sa->sa_command_0.bf.save_iv = save_iv;
sa->sa_command_0.bf.load_hash_state = ld_h;
sa->sa_command_0.bf.load_iv = ld_iv;
sa->sa_command_0.bf.hdr_proc = hdr_proc;
sa->sa_command_0.bf.hash_alg = h;
sa->sa_command_0.bf.cipher_alg = c;
sa->sa_command_0.bf.pad_type = pad_type & 3;
sa->sa_command_0.bf.extend_pad = pad_type >> 2;
sa->sa_command_0.bf.op_group = op_grp;
sa->sa_command_0.bf.opcode = op;
sa->sa_command_0.bf.dir = dir;
}
static void set_dynamic_sa_command_1(struct dynamic_sa_ctl *sa, u32 cm,
u32 hmac_mc, u32 cfb, u32 esn,
u32 sn_mask, u32 mute, u32 cp_pad,
u32 cp_pay, u32 cp_hdr)
{
sa->sa_command_1.w = 0;
sa->sa_command_1.bf.crypto_mode31 = (cm & 4) >> 2;
sa->sa_command_1.bf.crypto_mode9_8 = cm & 3;
sa->sa_command_1.bf.feedback_mode = cfb,
sa->sa_command_1.bf.sa_rev = 1;
sa->sa_command_1.bf.extended_seq_num = esn;
sa->sa_command_1.bf.seq_num_mask = sn_mask;
sa->sa_command_1.bf.mutable_bit_proc = mute;
sa->sa_command_1.bf.copy_pad = cp_pad;
sa->sa_command_1.bf.copy_payload = cp_pay;
sa->sa_command_1.bf.copy_hdr = cp_hdr;
}
int crypto4xx_encrypt(struct ablkcipher_request *req)
{
struct crypto4xx_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
ctx->direction = DIR_OUTBOUND;
ctx->hash_final = 0;
ctx->is_hash = 0;
ctx->pd_ctl = 0x1;
return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
req->nbytes, req->info,
get_dynamic_sa_iv_size(ctx));
}
int crypto4xx_decrypt(struct ablkcipher_request *req)
{
struct crypto4xx_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
ctx->direction = DIR_INBOUND;
ctx->hash_final = 0;
ctx->is_hash = 0;
ctx->pd_ctl = 1;
return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
req->nbytes, req->info,
get_dynamic_sa_iv_size(ctx));
}
/**
* AES Functions
*/
static int crypto4xx_setkey_aes(struct crypto_ablkcipher *cipher,
const u8 *key,
unsigned int keylen,
unsigned char cm,
u8 fb)
{
struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
struct crypto4xx_ctx *ctx = crypto_tfm_ctx(tfm);
struct dynamic_sa_ctl *sa;
int rc;
if (keylen != AES_KEYSIZE_256 &&
keylen != AES_KEYSIZE_192 && keylen != AES_KEYSIZE_128) {
crypto_ablkcipher_set_flags(cipher,
CRYPTO_TFM_RES_BAD_KEY_LEN);
return -EINVAL;
}
/* Create SA */
if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
crypto4xx_free_sa(ctx);
rc = crypto4xx_alloc_sa(ctx, SA_AES128_LEN + (keylen-16) / 4);
if (rc)
return rc;
if (ctx->state_record_dma_addr == 0) {
rc = crypto4xx_alloc_state_record(ctx);
if (rc) {
crypto4xx_free_sa(ctx);
return rc;
}
}
/* Setup SA */
sa = (struct dynamic_sa_ctl *) ctx->sa_in;
ctx->hash_final = 0;
set_dynamic_sa_command_0(sa, SA_NOT_SAVE_HASH, SA_NOT_SAVE_IV,
SA_LOAD_HASH_FROM_SA, SA_LOAD_IV_FROM_STATE,
SA_NO_HEADER_PROC, SA_HASH_ALG_NULL,
SA_CIPHER_ALG_AES, SA_PAD_TYPE_ZERO,
SA_OP_GROUP_BASIC, SA_OPCODE_DECRYPT,
DIR_INBOUND);
set_dynamic_sa_command_1(sa, cm, SA_HASH_MODE_HASH,
fb, SA_EXTENDED_SN_OFF,
SA_SEQ_MASK_OFF, SA_MC_ENABLE,
SA_NOT_COPY_PAD, SA_NOT_COPY_PAYLOAD,
SA_NOT_COPY_HDR);
crypto4xx_memcpy_le(ctx->sa_in + get_dynamic_sa_offset_key_field(ctx),
key, keylen);
sa->sa_contents = SA_AES_CONTENTS | (keylen << 2);
sa->sa_command_1.bf.key_len = keylen >> 3;
ctx->is_hash = 0;
ctx->direction = DIR_INBOUND;
memcpy(ctx->sa_in + get_dynamic_sa_offset_state_ptr_field(ctx),
(void *)&ctx->state_record_dma_addr, 4);
ctx->offset_to_sr_ptr = get_dynamic_sa_offset_state_ptr_field(ctx);
memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
sa = (struct dynamic_sa_ctl *) ctx->sa_out;
sa->sa_command_0.bf.dir = DIR_OUTBOUND;
return 0;
}
int crypto4xx_setkey_aes_cbc(struct crypto_ablkcipher *cipher,
const u8 *key, unsigned int keylen)
{
return crypto4xx_setkey_aes(cipher, key, keylen, CRYPTO_MODE_CBC,
CRYPTO_FEEDBACK_MODE_NO_FB);
}
/**
* HASH SHA1 Functions
*/
static int crypto4xx_hash_alg_init(struct crypto_tfm *tfm,
unsigned int sa_len,
unsigned char ha,
unsigned char hm)
{
struct crypto_alg *alg = tfm->__crt_alg;
struct crypto4xx_alg *my_alg = crypto_alg_to_crypto4xx_alg(alg);
struct crypto4xx_ctx *ctx = crypto_tfm_ctx(tfm);
struct dynamic_sa_ctl *sa;
struct dynamic_sa_hash160 *sa_in;
int rc;
ctx->dev = my_alg->dev;
ctx->is_hash = 1;
ctx->hash_final = 0;
/* Create SA */
if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
crypto4xx_free_sa(ctx);
rc = crypto4xx_alloc_sa(ctx, sa_len);
if (rc)
return rc;
if (ctx->state_record_dma_addr == 0) {
crypto4xx_alloc_state_record(ctx);
if (!ctx->state_record_dma_addr) {
crypto4xx_free_sa(ctx);
return -ENOMEM;
}
}
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
sizeof(struct crypto4xx_ctx));
sa = (struct dynamic_sa_ctl *) ctx->sa_in;
set_dynamic_sa_command_0(sa, SA_SAVE_HASH, SA_NOT_SAVE_IV,
SA_NOT_LOAD_HASH, SA_LOAD_IV_FROM_SA,
SA_NO_HEADER_PROC, ha, SA_CIPHER_ALG_NULL,
SA_PAD_TYPE_ZERO, SA_OP_GROUP_BASIC,
SA_OPCODE_HASH, DIR_INBOUND);
set_dynamic_sa_command_1(sa, 0, SA_HASH_MODE_HASH,
CRYPTO_FEEDBACK_MODE_NO_FB, SA_EXTENDED_SN_OFF,
SA_SEQ_MASK_OFF, SA_MC_ENABLE,
SA_NOT_COPY_PAD, SA_NOT_COPY_PAYLOAD,
SA_NOT_COPY_HDR);
ctx->direction = DIR_INBOUND;
sa->sa_contents = SA_HASH160_CONTENTS;
sa_in = (struct dynamic_sa_hash160 *) ctx->sa_in;
/* Need to zero hash digest in SA */
memset(sa_in->inner_digest, 0, sizeof(sa_in->inner_digest));
memset(sa_in->outer_digest, 0, sizeof(sa_in->outer_digest));
sa_in->state_ptr = ctx->state_record_dma_addr;
ctx->offset_to_sr_ptr = get_dynamic_sa_offset_state_ptr_field(ctx);
return 0;
}
int crypto4xx_hash_init(struct ahash_request *req)
{
struct crypto4xx_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
int ds;
struct dynamic_sa_ctl *sa;
sa = (struct dynamic_sa_ctl *) ctx->sa_in;
ds = crypto_ahash_digestsize(
__crypto_ahash_cast(req->base.tfm));
sa->sa_command_0.bf.digest_len = ds >> 2;
sa->sa_command_0.bf.load_hash_state = SA_LOAD_HASH_FROM_SA;
ctx->is_hash = 1;
ctx->direction = DIR_INBOUND;
return 0;
}
int crypto4xx_hash_update(struct ahash_request *req)
{
struct crypto4xx_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
ctx->is_hash = 1;
ctx->hash_final = 0;
ctx->pd_ctl = 0x11;
ctx->direction = DIR_INBOUND;
return crypto4xx_build_pd(&req->base, ctx, req->src,
(struct scatterlist *) req->result,
req->nbytes, NULL, 0);
}
int crypto4xx_hash_final(struct ahash_request *req)
{
return 0;
}
int crypto4xx_hash_digest(struct ahash_request *req)
{
struct crypto4xx_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
ctx->hash_final = 1;
ctx->pd_ctl = 0x11;
ctx->direction = DIR_INBOUND;
return crypto4xx_build_pd(&req->base, ctx, req->src,
(struct scatterlist *) req->result,
req->nbytes, NULL, 0);
}
/**
* SHA1 Algorithm
*/
int crypto4xx_sha1_alg_init(struct crypto_tfm *tfm)
{
return crypto4xx_hash_alg_init(tfm, SA_HASH160_LEN, SA_HASH_ALG_SHA1,
SA_HASH_MODE_HASH);
}

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drivers/crypto/amcc/crypto4xx_core.c Normal file
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drivers/crypto/amcc/crypto4xx_core.h Normal file
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/**
* AMCC SoC PPC4xx Crypto Driver
*
* Copyright (c) 2008 Applied Micro Circuits Corporation.
* All rights reserved. James Hsiao <jhsiao@amcc.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* This is the header file for AMCC Crypto offload Linux device driver for
* use with Linux CryptoAPI.
*/
#ifndef __CRYPTO4XX_CORE_H__
#define __CRYPTO4XX_CORE_H__
#include <crypto/internal/hash.h>
#define PPC460SX_SDR0_SRST 0x201
#define PPC405EX_SDR0_SRST 0x200
#define PPC460EX_SDR0_SRST 0x201
#define PPC460EX_CE_RESET 0x08000000
#define PPC460SX_CE_RESET 0x20000000
#define PPC405EX_CE_RESET 0x00000008
#define CRYPTO4XX_CRYPTO_PRIORITY 300
#define PPC4XX_LAST_PD 63
#define PPC4XX_NUM_PD 64
#define PPC4XX_LAST_GD 1023
#define PPC4XX_NUM_GD 1024
#define PPC4XX_LAST_SD 63
#define PPC4XX_NUM_SD 64
#define PPC4XX_SD_BUFFER_SIZE 2048
#define PD_ENTRY_INUSE 1
#define PD_ENTRY_FREE 0
#define ERING_WAS_FULL 0xffffffff
struct crypto4xx_device;
struct pd_uinfo {
struct crypto4xx_device *dev;
u32 state;
u32 using_sd;
u32 first_gd; /* first gather discriptor
used by this packet */
u32 num_gd; /* number of gather discriptor
used by this packet */
u32 first_sd; /* first scatter discriptor
used by this packet */
u32 num_sd; /* number of scatter discriptors
used by this packet */
void *sa_va; /* shadow sa, when using cp from ctx->sa */
u32 sa_pa;
void *sr_va; /* state record for shadow sa */
u32 sr_pa;
struct scatterlist *dest_va;
struct crypto_async_request *async_req; /* base crypto request
for this packet */
};
struct crypto4xx_device {
struct crypto4xx_core_device *core_dev;
char *name;
u64 ce_phy_address;
void __iomem *ce_base;
void *pdr; /* base address of packet
descriptor ring */
dma_addr_t pdr_pa; /* physical address used to
program ce pdr_base_register */
void *gdr; /* gather descriptor ring */
dma_addr_t gdr_pa; /* physical address used to
program ce gdr_base_register */
void *sdr; /* scatter descriptor ring */
dma_addr_t sdr_pa; /* physical address used to
program ce sdr_base_register */
void *scatter_buffer_va;
dma_addr_t scatter_buffer_pa;
u32 scatter_buffer_size;
void *shadow_sa_pool; /* pool of memory for sa in pd_uinfo */
dma_addr_t shadow_sa_pool_pa;
void *shadow_sr_pool; /* pool of memory for sr in pd_uinfo */
dma_addr_t shadow_sr_pool_pa;
u32 pdr_tail;
u32 pdr_head;
u32 gdr_tail;
u32 gdr_head;
u32 sdr_tail;
u32 sdr_head;
void *pdr_uinfo;
struct list_head alg_list; /* List of algorithm supported
by this device */
};
struct crypto4xx_core_device {
struct device *device;
struct platform_device *ofdev;
struct crypto4xx_device *dev;
u32 int_status;
u32 irq;
struct tasklet_struct tasklet;
spinlock_t lock;
};
struct crypto4xx_ctx {
struct crypto4xx_device *dev;
void *sa_in;
dma_addr_t sa_in_dma_addr;
void *sa_out;
dma_addr_t sa_out_dma_addr;
void *state_record;
dma_addr_t state_record_dma_addr;
u32 sa_len;
u32 offset_to_sr_ptr; /* offset to state ptr, in dynamic sa */
u32 direction;
u32 next_hdr;
u32 save_iv;
u32 pd_ctl_len;
u32 pd_ctl;
u32 bypass;
u32 is_hash;
u32 hash_final;
};
struct crypto4xx_req_ctx {
struct crypto4xx_device *dev; /* Device in which
operation to send to */
void *sa;
u32 sa_dma_addr;
u16 sa_len;
};
struct crypto4xx_alg_common {
u32 type;
union {
struct crypto_alg cipher;
struct ahash_alg hash;
} u;
};
struct crypto4xx_alg {
struct list_head entry;
struct crypto4xx_alg_common alg;
struct crypto4xx_device *dev;
};
static inline struct crypto4xx_alg *crypto_alg_to_crypto4xx_alg(
struct crypto_alg *x)
{
switch (x->cra_flags & CRYPTO_ALG_TYPE_MASK) {
case CRYPTO_ALG_TYPE_AHASH:
return container_of(__crypto_ahash_alg(x),
struct crypto4xx_alg, alg.u.hash);
}
return container_of(x, struct crypto4xx_alg, alg.u.cipher);
}
extern int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size);
extern void crypto4xx_free_sa(struct crypto4xx_ctx *ctx);
extern u32 crypto4xx_alloc_sa_rctx(struct crypto4xx_ctx *ctx,
struct crypto4xx_ctx *rctx);
extern void crypto4xx_free_sa_rctx(struct crypto4xx_ctx *rctx);
extern void crypto4xx_free_ctx(struct crypto4xx_ctx *ctx);
extern u32 crypto4xx_alloc_state_record(struct crypto4xx_ctx *ctx);
extern u32 get_dynamic_sa_offset_state_ptr_field(struct crypto4xx_ctx *ctx);
extern u32 get_dynamic_sa_offset_key_field(struct crypto4xx_ctx *ctx);
extern u32 get_dynamic_sa_iv_size(struct crypto4xx_ctx *ctx);
extern void crypto4xx_memcpy_le(unsigned int *dst,
const unsigned char *buf, int len);
extern u32 crypto4xx_build_pd(struct crypto_async_request *req,
struct crypto4xx_ctx *ctx,
struct scatterlist *src,
struct scatterlist *dst,
unsigned int datalen,
void *iv, u32 iv_len);
extern int crypto4xx_setkey_aes_cbc(struct crypto_ablkcipher *cipher,
const u8 *key, unsigned int keylen);
extern int crypto4xx_encrypt(struct ablkcipher_request *req);
extern int crypto4xx_decrypt(struct ablkcipher_request *req);
extern int crypto4xx_sha1_alg_init(struct crypto_tfm *tfm);
extern int crypto4xx_hash_digest(struct ahash_request *req);
extern int crypto4xx_hash_final(struct ahash_request *req);
extern int crypto4xx_hash_update(struct ahash_request *req);
extern int crypto4xx_hash_init(struct ahash_request *req);
#endif

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drivers/crypto/amcc/crypto4xx_reg_def.h Normal file
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/**
* AMCC SoC PPC4xx Crypto Driver
*
* Copyright (c) 2008 Applied Micro Circuits Corporation.
* All rights reserved. James Hsiao <jhsiao@amcc.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* This filr defines the register set for Security Subsystem
*/
#ifndef __CRYPTO4XX_REG_DEF_H__
#define __CRYPTO4XX_REG_DEF_H__
/* CRYPTO4XX Register offset */
#define CRYPTO4XX_DESCRIPTOR 0x00000000
#define CRYPTO4XX_CTRL_STAT 0x00000000
#define CRYPTO4XX_SOURCE 0x00000004
#define CRYPTO4XX_DEST 0x00000008
#define CRYPTO4XX_SA 0x0000000C
#define CRYPTO4XX_SA_LENGTH 0x00000010
#define CRYPTO4XX_LENGTH 0x00000014
#define CRYPTO4XX_PE_DMA_CFG 0x00000040
#define CRYPTO4XX_PE_DMA_STAT 0x00000044
#define CRYPTO4XX_PDR_BASE 0x00000048
#define CRYPTO4XX_RDR_BASE 0x0000004c
#define CRYPTO4XX_RING_SIZE 0x00000050
#define CRYPTO4XX_RING_CTRL 0x00000054
#define CRYPTO4XX_INT_RING_STAT 0x00000058
#define CRYPTO4XX_EXT_RING_STAT 0x0000005c
#define CRYPTO4XX_IO_THRESHOLD 0x00000060
#define CRYPTO4XX_GATH_RING_BASE 0x00000064
#define CRYPTO4XX_SCAT_RING_BASE 0x00000068
#define CRYPTO4XX_PART_RING_SIZE 0x0000006c
#define CRYPTO4XX_PART_RING_CFG 0x00000070
#define CRYPTO4XX_PDR_BASE_UADDR 0x00000080
#define CRYPTO4XX_RDR_BASE_UADDR 0x00000084
#define CRYPTO4XX_PKT_SRC_UADDR 0x00000088
#define CRYPTO4XX_PKT_DEST_UADDR 0x0000008c
#define CRYPTO4XX_SA_UADDR 0x00000090
#define CRYPTO4XX_GATH_RING_BASE_UADDR 0x000000A0
#define CRYPTO4XX_SCAT_RING_BASE_UADDR 0x000000A4
#define CRYPTO4XX_SEQ_RD 0x00000408
#define CRYPTO4XX_SEQ_MASK_RD 0x0000040C
#define CRYPTO4XX_SA_CMD_0 0x00010600
#define CRYPTO4XX_SA_CMD_1 0x00010604
#define CRYPTO4XX_STATE_PTR 0x000106dc
#define CRYPTO4XX_STATE_IV 0x00010700
#define CRYPTO4XX_STATE_HASH_BYTE_CNT_0 0x00010710
#define CRYPTO4XX_STATE_HASH_BYTE_CNT_1 0x00010714
#define CRYPTO4XX_STATE_IDIGEST_0 0x00010718
#define CRYPTO4XX_STATE_IDIGEST_1 0x0001071c
#define CRYPTO4XX_DATA_IN 0x00018000
#define CRYPTO4XX_DATA_OUT 0x0001c000
#define CRYPTO4XX_INT_UNMASK_STAT 0x000500a0
#define CRYPTO4XX_INT_MASK_STAT 0x000500a4
#define CRYPTO4XX_INT_CLR 0x000500a4
#define CRYPTO4XX_INT_EN 0x000500a8
#define CRYPTO4XX_INT_PKA 0x00000002
#define CRYPTO4XX_INT_PDR_DONE 0x00008000
#define CRYPTO4XX_INT_MA_WR_ERR 0x00020000
#define CRYPTO4XX_INT_MA_RD_ERR 0x00010000
#define CRYPTO4XX_INT_PE_ERR 0x00000200
#define CRYPTO4XX_INT_USER_DMA_ERR 0x00000040
#define CRYPTO4XX_INT_SLAVE_ERR 0x00000010
#define CRYPTO4XX_INT_MASTER_ERR 0x00000008
#define CRYPTO4XX_INT_ERROR 0x00030258
#define CRYPTO4XX_INT_CFG 0x000500ac
#define CRYPTO4XX_INT_DESCR_RD 0x000500b0
#define CRYPTO4XX_INT_DESCR_CNT 0x000500b4
#define CRYPTO4XX_INT_TIMEOUT_CNT 0x000500b8
#define CRYPTO4XX_DEVICE_CTRL 0x00060080
#define CRYPTO4XX_DEVICE_ID 0x00060084
#define CRYPTO4XX_DEVICE_INFO 0x00060088
#define CRYPTO4XX_DMA_USER_SRC 0x00060094
#define CRYPTO4XX_DMA_USER_DEST 0x00060098
#define CRYPTO4XX_DMA_USER_CMD 0x0006009C
#define CRYPTO4XX_DMA_CFG 0x000600d4
#define CRYPTO4XX_BYTE_ORDER_CFG 0x000600d8
#define CRYPTO4XX_ENDIAN_CFG 0x000600d8
#define CRYPTO4XX_PRNG_STAT 0x00070000
#define CRYPTO4XX_PRNG_CTRL 0x00070004
#define CRYPTO4XX_PRNG_SEED_L 0x00070008
#define CRYPTO4XX_PRNG_SEED_H 0x0007000c
#define CRYPTO4XX_PRNG_RES_0 0x00070020
#define CRYPTO4XX_PRNG_RES_1 0x00070024
#define CRYPTO4XX_PRNG_RES_2 0x00070028
#define CRYPTO4XX_PRNG_RES_3 0x0007002C
#define CRYPTO4XX_PRNG_LFSR_L 0x00070030
#define CRYPTO4XX_PRNG_LFSR_H 0x00070034
/**
* Initialize CRYPTO ENGINE registers, and memory bases.
*/
#define PPC4XX_PDR_POLL 0x3ff
#define PPC4XX_OUTPUT_THRESHOLD 2
#define PPC4XX_INPUT_THRESHOLD 2
#define PPC4XX_PD_SIZE 6
#define PPC4XX_CTX_DONE_INT 0x2000
#define PPC4XX_PD_DONE_INT 0x8000
#define PPC4XX_BYTE_ORDER 0x22222
#define PPC4XX_INTERRUPT_CLR 0x3ffff
#define PPC4XX_PRNG_CTRL_AUTO_EN 0x3
#define PPC4XX_DC_3DES_EN 1
#define PPC4XX_INT_DESCR_CNT 4
#define PPC4XX_INT_TIMEOUT_CNT 0
#define PPC4XX_INT_CFG 1
/**
* all follow define are ad hoc
*/
#define PPC4XX_RING_RETRY 100
#define PPC4XX_RING_POLL 100
#define PPC4XX_SDR_SIZE PPC4XX_NUM_SD
#define PPC4XX_GDR_SIZE PPC4XX_NUM_GD
/**
* Generic Security Association (SA) with all possible fields. These will
* never likely used except for reference purpose. These structure format
* can be not changed as the hardware expects them to be layout as defined.
* Field can be removed or reduced but ordering can not be changed.
*/
#define CRYPTO4XX_DMA_CFG_OFFSET 0x40
union ce_pe_dma_cfg {
struct {
u32 rsv:7;
u32 dir_host:1;
u32 rsv1:2;
u32 bo_td_en:1;
u32 dis_pdr_upd:1;
u32 bo_sgpd_en:1;
u32 bo_data_en:1;
u32 bo_sa_en:1;
u32 bo_pd_en:1;
u32 rsv2:4;
u32 dynamic_sa_en:1;
u32 pdr_mode:2;
u32 pe_mode:1;
u32 rsv3:5;
u32 reset_sg:1;
u32 reset_pdr:1;
u32 reset_pe:1;
} bf;
u32 w;
} __attribute__((packed));
#define CRYPTO4XX_PDR_BASE_OFFSET 0x48
#define CRYPTO4XX_RDR_BASE_OFFSET 0x4c
#define CRYPTO4XX_RING_SIZE_OFFSET 0x50
union ce_ring_size {
struct {
u32 ring_offset:16;
u32 rsv:6;
u32 ring_size:10;
} bf;
u32 w;
} __attribute__((packed));
#define CRYPTO4XX_RING_CONTROL_OFFSET 0x54
union ce_ring_contol {
struct {
u32 continuous:1;
u32 rsv:5;
u32 ring_retry_divisor:10;
u32 rsv1:4;
u32 ring_poll_divisor:10;
} bf;
u32 w;
} __attribute__((packed));
#define CRYPTO4XX_IO_THRESHOLD_OFFSET 0x60
union ce_io_threshold {
struct {
u32 rsv:6;
u32 output_threshold:10;
u32 rsv1:6;
u32 input_threshold:10;
} bf;
u32 w;
} __attribute__((packed));
#define CRYPTO4XX_GATHER_RING_BASE_OFFSET 0x64
#define CRYPTO4XX_SCATTER_RING_BASE_OFFSET 0x68
union ce_part_ring_size {
struct {
u32 sdr_size:16;
u32 gdr_size:16;
} bf;
u32 w;
} __attribute__((packed));
#define MAX_BURST_SIZE_32 0
#define MAX_BURST_SIZE_64 1
#define MAX_BURST_SIZE_128 2
#define MAX_BURST_SIZE_256 3
/* gather descriptor control length */
struct gd_ctl_len {
u32 len:16;
u32 rsv:14;
u32 done:1;
u32 ready:1;
} __attribute__((packed));
struct ce_gd {
u32 ptr;
struct gd_ctl_len ctl_len;
} __attribute__((packed));
struct sd_ctl {
u32 ctl:30;
u32 done:1;
u32 rdy:1;
} __attribute__((packed));
struct ce_sd {
u32 ptr;
struct sd_ctl ctl;
} __attribute__((packed));
#define PD_PAD_CTL_32 0x10
#define PD_PAD_CTL_64 0x20
#define PD_PAD_CTL_128 0x40
#define PD_PAD_CTL_256 0x80
union ce_pd_ctl {
struct {
u32 pd_pad_ctl:8;
u32 status:8;
u32 next_hdr:8;
u32 rsv:2;
u32 cached_sa:1;
u32 hash_final:1;
u32 init_arc4:1;
u32 rsv1:1;
u32 pe_done:1;
u32 host_ready:1;
} bf;
u32 w;
} __attribute__((packed));
union ce_pd_ctl_len {
struct {
u32 bypass:8;
u32 pe_done:1;
u32 host_ready:1;
u32 rsv:2;
u32 pkt_len:20;
} bf;
u32 w;
} __attribute__((packed));
struct ce_pd {
union ce_pd_ctl pd_ctl;
u32 src;
u32 dest;
u32 sa; /* get from ctx->sa_dma_addr */
u32 sa_len; /* only if dynamic sa is used */
union ce_pd_ctl_len pd_ctl_len;
} __attribute__((packed));
#endif

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/**
* AMCC SoC PPC4xx Crypto Driver
*
* Copyright (c) 2008 Applied Micro Circuits Corporation.
* All rights reserved. James Hsiao <jhsiao@amcc.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* @file crypto4xx_sa.c
*
* This file implements the security context
* associate format.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/mod_devicetable.h>
#include <linux/interrupt.h>
#include <linux/spinlock_types.h>
#include <linux/highmem.h>
#include <linux/scatterlist.h>
#include <linux/crypto.h>
#include <crypto/algapi.h>
#include <crypto/des.h>
#include "crypto4xx_reg_def.h"
#include "crypto4xx_sa.h"
#include "crypto4xx_core.h"
u32 get_dynamic_sa_offset_iv_field(struct crypto4xx_ctx *ctx)
{
u32 offset;
union dynamic_sa_contents cts;
if (ctx->direction == DIR_INBOUND)
cts.w = ((struct dynamic_sa_ctl *)(ctx->sa_in))->sa_contents;
else
cts.w = ((struct dynamic_sa_ctl *)(ctx->sa_out))->sa_contents;
offset = cts.bf.key_size
+ cts.bf.inner_size
+ cts.bf.outer_size
+ cts.bf.spi
+ cts.bf.seq_num0
+ cts.bf.seq_num1
+ cts.bf.seq_num_mask0
+ cts.bf.seq_num_mask1
+ cts.bf.seq_num_mask2
+ cts.bf.seq_num_mask3;
return sizeof(struct dynamic_sa_ctl) + offset * 4;
}
u32 get_dynamic_sa_offset_state_ptr_field(struct crypto4xx_ctx *ctx)
{
u32 offset;
union dynamic_sa_contents cts;
if (ctx->direction == DIR_INBOUND)
cts.w = ((struct dynamic_sa_ctl *) ctx->sa_in)->sa_contents;
else
cts.w = ((struct dynamic_sa_ctl *) ctx->sa_out)->sa_contents;
offset = cts.bf.key_size
+ cts.bf.inner_size
+ cts.bf.outer_size
+ cts.bf.spi
+ cts.bf.seq_num0
+ cts.bf.seq_num1
+ cts.bf.seq_num_mask0
+ cts.bf.seq_num_mask1
+ cts.bf.seq_num_mask2
+ cts.bf.seq_num_mask3
+ cts.bf.iv0
+ cts.bf.iv1
+ cts.bf.iv2
+ cts.bf.iv3;
return sizeof(struct dynamic_sa_ctl) + offset * 4;
}
u32 get_dynamic_sa_iv_size(struct crypto4xx_ctx *ctx)
{
union dynamic_sa_contents cts;
if (ctx->direction == DIR_INBOUND)
cts.w = ((struct dynamic_sa_ctl *) ctx->sa_in)->sa_contents;
else
cts.w = ((struct dynamic_sa_ctl *) ctx->sa_out)->sa_contents;
return (cts.bf.iv0 + cts.bf.iv1 + cts.bf.iv2 + cts.bf.iv3) * 4;
}
u32 get_dynamic_sa_offset_key_field(struct crypto4xx_ctx *ctx)
{
union dynamic_sa_contents cts;
if (ctx->direction == DIR_INBOUND)
cts.w = ((struct dynamic_sa_ctl *) ctx->sa_in)->sa_contents;
else
cts.w = ((struct dynamic_sa_ctl *) ctx->sa_out)->sa_contents;
return sizeof(struct dynamic_sa_ctl);
}

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/**
* AMCC SoC PPC4xx Crypto Driver
*
* Copyright (c) 2008 Applied Micro Circuits Corporation.
* All rights reserved. James Hsiao <jhsiao@amcc.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* This file defines the security context
* associate format.
*/
#ifndef __CRYPTO4XX_SA_H__
#define __CRYPTO4XX_SA_H__
#define AES_IV_SIZE 16
/**
* Contents of Dynamic Security Association (SA) with all possible fields
*/
union dynamic_sa_contents {
struct {
u32 arc4_state_ptr:1;
u32 arc4_ij_ptr:1;
u32 state_ptr:1;
u32 iv3:1;
u32 iv2:1;
u32 iv1:1;
u32 iv0:1;
u32 seq_num_mask3:1;
u32 seq_num_mask2:1;
u32 seq_num_mask1:1;
u32 seq_num_mask0:1;
u32 seq_num1:1;
u32 seq_num0:1;
u32 spi:1;
u32 outer_size:5;
u32 inner_size:5;
u32 key_size:4;
u32 cmd_size:4;
} bf;
u32 w;
} __attribute__((packed));
#define DIR_OUTBOUND 0
#define DIR_INBOUND 1
#define SA_OP_GROUP_BASIC 0
#define SA_OPCODE_ENCRYPT 0
#define SA_OPCODE_DECRYPT 0
#define SA_OPCODE_HASH 3
#define SA_CIPHER_ALG_DES 0
#define SA_CIPHER_ALG_3DES 1
#define SA_CIPHER_ALG_ARC4 2
#define SA_CIPHER_ALG_AES 3
#define SA_CIPHER_ALG_KASUMI 4
#define SA_CIPHER_ALG_NULL 15
#define SA_HASH_ALG_MD5 0
#define SA_HASH_ALG_SHA1 1
#define SA_HASH_ALG_NULL 15
#define SA_HASH_ALG_SHA1_DIGEST_SIZE 20
#define SA_LOAD_HASH_FROM_SA 0
#define SA_LOAD_HASH_FROM_STATE 2
#define SA_NOT_LOAD_HASH 3
#define SA_LOAD_IV_FROM_SA 0
#define SA_LOAD_IV_FROM_INPUT 1
#define SA_LOAD_IV_FROM_STATE 2
#define SA_LOAD_IV_GEN_IV 3
#define SA_PAD_TYPE_CONSTANT 2
#define SA_PAD_TYPE_ZERO 3
#define SA_PAD_TYPE_TLS 5
#define SA_PAD_TYPE_DTLS 5
#define SA_NOT_SAVE_HASH 0
#define SA_SAVE_HASH 1
#define SA_NOT_SAVE_IV 0
#define SA_SAVE_IV 1
#define SA_HEADER_PROC 1
#define SA_NO_HEADER_PROC 0
union sa_command_0 {
struct {
u32 scatter:1;
u32 gather:1;
u32 save_hash_state:1;
u32 save_iv:1;
u32 load_hash_state:2;
u32 load_iv:2;
u32 digest_len:4;
u32 hdr_proc:1;
u32 extend_pad:1;
u32 stream_cipher_pad:1;
u32 rsv:1;
u32 hash_alg:4;
u32 cipher_alg:4;
u32 pad_type:2;
u32 op_group:2;
u32 dir:1;
u32 opcode:3;
} bf;
u32 w;
} __attribute__((packed));
#define CRYPTO_MODE_ECB 0
#define CRYPTO_MODE_CBC 1
#define CRYPTO_FEEDBACK_MODE_NO_FB 0
#define CRYPTO_FEEDBACK_MODE_64BIT_OFB 0
#define CRYPTO_FEEDBACK_MODE_8BIT_CFB 1
#define CRYPTO_FEEDBACK_MODE_1BIT_CFB 2
#define CRYPTO_FEEDBACK_MODE_128BIT_CFB 3
#define SA_AES_KEY_LEN_128 2
#define SA_AES_KEY_LEN_192 3
#define SA_AES_KEY_LEN_256 4
#define SA_REV2 1
/**
* The follow defines bits sa_command_1
* In Basic hash mode this bit define simple hash or hmac.
* In IPsec mode, this bit define muting control.
*/
#define SA_HASH_MODE_HASH 0
#define SA_HASH_MODE_HMAC 1
#define SA_MC_ENABLE 0
#define SA_MC_DISABLE 1
#define SA_NOT_COPY_HDR 0
#define SA_COPY_HDR 1
#define SA_NOT_COPY_PAD 0
#define SA_COPY_PAD 1
#define SA_NOT_COPY_PAYLOAD 0
#define SA_COPY_PAYLOAD 1
#define SA_EXTENDED_SN_OFF 0
#define SA_EXTENDED_SN_ON 1
#define SA_SEQ_MASK_OFF 0
#define SA_SEQ_MASK_ON 1
union sa_command_1 {
struct {
u32 crypto_mode31:1;
u32 save_arc4_state:1;
u32 arc4_stateful:1;
u32 key_len:5;
u32 hash_crypto_offset:8;
u32 sa_rev:2;
u32 byte_offset:1;
u32 hmac_muting:1;
u32 feedback_mode:2;
u32 crypto_mode9_8:2;
u32 extended_seq_num:1;
u32 seq_num_mask:1;
u32 mutable_bit_proc:1;
u32 ip_version:1;
u32 copy_pad:1;
u32 copy_payload:1;
u32 copy_hdr:1;
u32 rsv1:1;
} bf;
u32 w;
} __attribute__((packed));
struct dynamic_sa_ctl {
u32 sa_contents;
union sa_command_0 sa_command_0;
union sa_command_1 sa_command_1;
} __attribute__((packed));
/**
* State Record for Security Association (SA)
*/
struct sa_state_record {
u32 save_iv[4];
u32 save_hash_byte_cnt[2];
u32 save_digest[16];
} __attribute__((packed));
/**
* Security Association (SA) for AES128
*
*/
struct dynamic_sa_aes128 {
struct dynamic_sa_ctl ctrl;
u32 key[4];
u32 iv[4]; /* for CBC, OFC, and CFB mode */
u32 state_ptr;
u32 reserved;
} __attribute__((packed));
#define SA_AES128_LEN (sizeof(struct dynamic_sa_aes128)/4)
#define SA_AES128_CONTENTS 0x3e000042
/*
* Security Association (SA) for AES192
*/
struct dynamic_sa_aes192 {
struct dynamic_sa_ctl ctrl;
u32 key[6];
u32 iv[4]; /* for CBC, OFC, and CFB mode */
u32 state_ptr;
u32 reserved;
} __attribute__((packed));
#define SA_AES192_LEN (sizeof(struct dynamic_sa_aes192)/4)
#define SA_AES192_CONTENTS 0x3e000062
/**
* Security Association (SA) for AES256
*/
struct dynamic_sa_aes256 {
struct dynamic_sa_ctl ctrl;
u32 key[8];
u32 iv[4]; /* for CBC, OFC, and CFB mode */
u32 state_ptr;
u32 reserved;
} __attribute__((packed));
#define SA_AES256_LEN (sizeof(struct dynamic_sa_aes256)/4)
#define SA_AES256_CONTENTS 0x3e000082
#define SA_AES_CONTENTS 0x3e000002
/**
* Security Association (SA) for HASH160: HMAC-SHA1
*/
struct dynamic_sa_hash160 {
struct dynamic_sa_ctl ctrl;
u32 inner_digest[5];
u32 outer_digest[5];
u32 state_ptr;
u32 reserved;
} __attribute__((packed));
#define SA_HASH160_LEN (sizeof(struct dynamic_sa_hash160)/4)
#define SA_HASH160_CONTENTS 0x2000a502
#endif