mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 01:28:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
460
drivers/dma/Kconfig
Normal file
460
drivers/dma/Kconfig
Normal file
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@ -0,0 +1,460 @@
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#
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# DMA engine configuration
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#
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menuconfig DMADEVICES
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bool "DMA Engine support"
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depends on HAS_DMA
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help
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DMA engines can do asynchronous data transfers without
|
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involving the host CPU. Currently, this framework can be
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used to offload memory copies in the network stack and
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RAID operations in the MD driver. This menu only presents
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DMA Device drivers supported by the configured arch, it may
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be empty in some cases.
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config DMADEVICES_DEBUG
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bool "DMA Engine debugging"
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depends on DMADEVICES != n
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help
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This is an option for use by developers; most people should
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say N here. This enables DMA engine core and driver debugging.
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config DMADEVICES_VDEBUG
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bool "DMA Engine verbose debugging"
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depends on DMADEVICES_DEBUG != n
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help
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This is an option for use by developers; most people should
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say N here. This enables deeper (more verbose) debugging of
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the DMA engine core and drivers.
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if DMADEVICES
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comment "DMA Devices"
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config INTEL_MIC_X100_DMA
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tristate "Intel MIC X100 DMA Driver"
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depends on 64BIT && X86 && INTEL_MIC_BUS
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select DMA_ENGINE
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help
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This enables DMA support for the Intel Many Integrated Core
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(MIC) family of PCIe form factor coprocessor X100 devices that
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run a 64 bit Linux OS. This driver will be used by both MIC
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host and card drivers.
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If you are building host kernel with a MIC device or a card
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kernel for a MIC device, then say M (recommended) or Y, else
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say N. If unsure say N.
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More information about the Intel MIC family as well as the Linux
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OS and tools for MIC to use with this driver are available from
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<http://software.intel.com/en-us/mic-developer>.
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config INTEL_MID_DMAC
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tristate "Intel MID DMA support for Peripheral DMA controllers"
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depends on PCI && X86
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select DMA_ENGINE
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default n
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help
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Enable support for the Intel(R) MID DMA engine present
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in Intel MID chipsets.
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Say Y here if you have such a chipset.
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If unsure, say N.
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config ASYNC_TX_ENABLE_CHANNEL_SWITCH
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bool
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config AMBA_PL08X
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bool "ARM PrimeCell PL080 or PL081 support"
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depends on ARM_AMBA
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Platform has a PL08x DMAC device
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which can provide DMA engine support
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config INTEL_IOATDMA
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tristate "Intel I/OAT DMA support"
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depends on PCI && X86
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select DMA_ENGINE
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select DMA_ENGINE_RAID
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select DCA
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help
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Enable support for the Intel(R) I/OAT DMA engine present
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in recent Intel Xeon chipsets.
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Say Y here if you have such a chipset.
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If unsure, say N.
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config INTEL_IOP_ADMA
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tristate "Intel IOP ADMA support"
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depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
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select DMA_ENGINE
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select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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help
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Enable support for the Intel(R) IOP Series RAID engines.
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source "drivers/dma/dw/Kconfig"
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config AT_HDMAC
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tristate "Atmel AHB DMA support"
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depends on ARCH_AT91
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select DMA_ENGINE
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help
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Support the Atmel AHB DMA controller.
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config FSL_DMA
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tristate "Freescale Elo series DMA support"
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depends on FSL_SOC
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select DMA_ENGINE
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select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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---help---
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Enable support for the Freescale Elo series DMA controllers.
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The Elo is the DMA controller on some mpc82xx and mpc83xx parts, the
|
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EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on
|
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some Txxx and Bxxx parts.
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config MPC512X_DMA
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tristate "Freescale MPC512x built-in DMA engine support"
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depends on PPC_MPC512x || PPC_MPC831x
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select DMA_ENGINE
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---help---
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Enable support for the Freescale MPC512x built-in DMA engine.
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source "drivers/dma/bestcomm/Kconfig"
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config MV_XOR
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bool "Marvell XOR engine support"
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depends on PLAT_ORION
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select DMA_ENGINE
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select DMA_ENGINE_RAID
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select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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---help---
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Enable support for the Marvell XOR engine.
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config MX3_IPU
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bool "MX3x Image Processing Unit support"
|
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depends on ARCH_MXC
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select DMA_ENGINE
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default y
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help
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If you plan to use the Image Processing unit in the i.MX3x, say
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Y here. If unsure, select Y.
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config MX3_IPU_IRQS
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int "Number of dynamically mapped interrupts for IPU"
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depends on MX3_IPU
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range 2 137
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default 4
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help
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Out of 137 interrupt sources on i.MX31 IPU only very few are used.
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To avoid bloating the irq_desc[] array we allocate a sufficient
|
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number of IRQ slots and map them dynamically to specific sources.
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config TXX9_DMAC
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tristate "Toshiba TXx9 SoC DMA support"
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depends on MACH_TX49XX || MACH_TX39XX
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select DMA_ENGINE
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help
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Support the TXx9 SoC internal DMA controller. This can be
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integrated in chips such as the Toshiba TX4927/38/39.
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config TEGRA20_APB_DMA
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bool "NVIDIA Tegra20 APB DMA support"
|
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depends on ARCH_TEGRA
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select DMA_ENGINE
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help
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Support for the NVIDIA Tegra20 APB DMA controller driver. The
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DMA controller is having multiple DMA channel which can be
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configured for different peripherals like audio, UART, SPI,
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I2C etc which is in APB bus.
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This DMA controller transfers data from memory to peripheral fifo
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or vice versa. It does not support memory to memory data transfer.
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config S3C24XX_DMAC
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tristate "Samsung S3C24XX DMA support"
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depends on ARCH_S3C24XX && !S3C24XX_DMA
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Support for the Samsung S3C24XX DMA controller driver. The
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DMA controller is having multiple DMA channels which can be
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configured for different peripherals like audio, UART, SPI.
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The DMA controller can transfer data from memory to peripheral,
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periphal to memory, periphal to periphal and memory to memory.
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source "drivers/dma/sh/Kconfig"
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config COH901318
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bool "ST-Ericsson COH901318 DMA support"
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select DMA_ENGINE
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depends on ARCH_U300
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help
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Enable support for ST-Ericsson COH 901 318 DMA.
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config STE_DMA40
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bool "ST-Ericsson DMA40 support"
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depends on ARCH_U8500
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select DMA_ENGINE
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help
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Support for ST-Ericsson DMA40 controller
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config AMCC_PPC440SPE_ADMA
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tristate "AMCC PPC440SPe ADMA support"
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depends on 440SPe || 440SP
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select DMA_ENGINE
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select DMA_ENGINE_RAID
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select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
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select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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help
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Enable support for the AMCC PPC440SPe RAID engines.
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config TIMB_DMA
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tristate "Timberdale FPGA DMA support"
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depends on MFD_TIMBERDALE
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select DMA_ENGINE
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help
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Enable support for the Timberdale FPGA DMA engine.
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config SIRF_DMA
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tristate "CSR SiRFprimaII/SiRFmarco DMA support"
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depends on ARCH_SIRF
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select DMA_ENGINE
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help
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Enable support for the CSR SiRFprimaII DMA engine.
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config TI_EDMA
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bool "TI EDMA support"
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depends on ARCH_DAVINCI || ARCH_OMAP || ARCH_KEYSTONE
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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select TI_PRIV_EDMA
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default n
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help
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Enable support for the TI EDMA controller. This DMA
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engine is found on TI DaVinci and AM33xx parts.
|
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config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
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bool
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config PL330_DMA
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tristate "DMA API Driver for PL330"
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select DMA_ENGINE
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depends on ARM_AMBA
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help
|
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Select if your platform has one or more PL330 DMACs.
|
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You need to provide platform specific settings via
|
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platform_data for a dma-pl330 device.
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config PCH_DMA
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tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"
|
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depends on PCI && (X86_32 || COMPILE_TEST)
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select DMA_ENGINE
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help
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Enable support for Intel EG20T PCH DMA engine.
|
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This driver also can be used for LAPIS Semiconductor IOH(Input/
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Output Hub), ML7213, ML7223 and ML7831.
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ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is
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for MP(Media Phone) use and ML7831 IOH is for general purpose use.
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ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
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ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
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config IMX_SDMA
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tristate "i.MX SDMA support"
|
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depends on ARCH_MXC
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select DMA_ENGINE
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help
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Support the i.MX SDMA engine. This engine is integrated into
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Freescale i.MX25/31/35/51/53/6 chips.
|
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config IMX_DMA
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tristate "i.MX DMA support"
|
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depends on ARCH_MXC
|
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select DMA_ENGINE
|
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help
|
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Support the i.MX DMA engine. This engine is integrated into
|
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Freescale i.MX1/21/27 chips.
|
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|
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config MXS_DMA
|
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bool "MXS DMA support"
|
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depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q
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select STMP_DEVICE
|
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select DMA_ENGINE
|
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help
|
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Support the MXS DMA engine. This engine including APBH-DMA
|
||||
and APBX-DMA is integrated into Freescale i.MX23/28/MX6Q/MX6DL chips.
|
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|
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config EP93XX_DMA
|
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bool "Cirrus Logic EP93xx DMA support"
|
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depends on ARCH_EP93XX
|
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select DMA_ENGINE
|
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help
|
||||
Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
|
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|
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config DMA_SA11X0
|
||||
tristate "SA-11x0 DMA support"
|
||||
depends on ARCH_SA1100
|
||||
select DMA_ENGINE
|
||||
select DMA_VIRTUAL_CHANNELS
|
||||
help
|
||||
Support the DMA engine found on Intel StrongARM SA-1100 and
|
||||
SA-1110 SoCs. This DMA engine can only be used with on-chip
|
||||
devices.
|
||||
|
||||
config MMP_TDMA
|
||||
bool "MMP Two-Channel DMA support"
|
||||
depends on ARCH_MMP
|
||||
select DMA_ENGINE
|
||||
select MMP_SRAM
|
||||
help
|
||||
Support the MMP Two-Channel DMA engine.
|
||||
This engine used for MMP Audio DMA and pxa910 SQU.
|
||||
It needs sram driver under mach-mmp.
|
||||
|
||||
Say Y here if you enabled MMP ADMA, otherwise say N.
|
||||
|
||||
config DMA_OMAP
|
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tristate "OMAP DMA support"
|
||||
depends on ARCH_OMAP
|
||||
select DMA_ENGINE
|
||||
select DMA_VIRTUAL_CHANNELS
|
||||
|
||||
config DMA_BCM2835
|
||||
tristate "BCM2835 DMA engine support"
|
||||
depends on ARCH_BCM2835
|
||||
select DMA_ENGINE
|
||||
select DMA_VIRTUAL_CHANNELS
|
||||
|
||||
config TI_CPPI41
|
||||
tristate "AM33xx CPPI41 DMA support"
|
||||
depends on ARCH_OMAP
|
||||
select DMA_ENGINE
|
||||
help
|
||||
The Communications Port Programming Interface (CPPI) 4.1 DMA engine
|
||||
is currently used by the USB driver on AM335x platforms.
|
||||
|
||||
config MMP_PDMA
|
||||
bool "MMP PDMA support"
|
||||
depends on (ARCH_MMP || ARCH_PXA)
|
||||
select DMA_ENGINE
|
||||
help
|
||||
Support the MMP PDMA engine for PXA and MMP platform.
|
||||
|
||||
config DMA_JZ4740
|
||||
tristate "JZ4740 DMA support"
|
||||
depends on MACH_JZ4740
|
||||
select DMA_ENGINE
|
||||
select DMA_VIRTUAL_CHANNELS
|
||||
|
||||
config K3_DMA
|
||||
tristate "Hisilicon K3 DMA support"
|
||||
depends on ARCH_HI3xxx
|
||||
select DMA_ENGINE
|
||||
select DMA_VIRTUAL_CHANNELS
|
||||
help
|
||||
Support the DMA engine for Hisilicon K3 platform
|
||||
devices.
|
||||
|
||||
config MOXART_DMA
|
||||
tristate "MOXART DMA support"
|
||||
depends on ARCH_MOXART
|
||||
select DMA_ENGINE
|
||||
select DMA_OF
|
||||
select DMA_VIRTUAL_CHANNELS
|
||||
help
|
||||
Enable support for the MOXA ART SoC DMA controller.
|
||||
|
||||
config FSL_EDMA
|
||||
tristate "Freescale eDMA engine support"
|
||||
depends on OF
|
||||
select DMA_ENGINE
|
||||
select DMA_VIRTUAL_CHANNELS
|
||||
help
|
||||
Support the Freescale eDMA engine with programmable channel
|
||||
multiplexing capability for DMA request sources(slot).
|
||||
This module can be found on Freescale Vybrid and LS-1 SoCs.
|
||||
|
||||
config XILINX_VDMA
|
||||
tristate "Xilinx AXI VDMA Engine"
|
||||
depends on (ARCH_ZYNQ || MICROBLAZE)
|
||||
select DMA_ENGINE
|
||||
help
|
||||
Enable support for Xilinx AXI VDMA Soft IP.
|
||||
|
||||
This engine provides high-bandwidth direct memory access
|
||||
between memory and AXI4-Stream video type target
|
||||
peripherals including peripherals which support AXI4-
|
||||
Stream Video Protocol. It has two stream interfaces/
|
||||
channels, Memory Mapped to Stream (MM2S) and Stream to
|
||||
Memory Mapped (S2MM) for the data transfers.
|
||||
|
||||
config DMA_SUN6I
|
||||
tristate "Allwinner A31 SoCs DMA support"
|
||||
depends on MACH_SUN6I || COMPILE_TEST
|
||||
depends on RESET_CONTROLLER
|
||||
select DMA_ENGINE
|
||||
select DMA_VIRTUAL_CHANNELS
|
||||
help
|
||||
Support for the DMA engine for Allwinner A31 SoCs.
|
||||
|
||||
config NBPFAXI_DMA
|
||||
tristate "Renesas Type-AXI NBPF DMA support"
|
||||
select DMA_ENGINE
|
||||
depends on ARM || COMPILE_TEST
|
||||
help
|
||||
Support for "Type-AXI" NBPF DMA IPs from Renesas
|
||||
|
||||
config DMA_ENGINE
|
||||
bool
|
||||
|
||||
config DMA_VIRTUAL_CHANNELS
|
||||
tristate
|
||||
|
||||
config DMA_ACPI
|
||||
def_bool y
|
||||
depends on ACPI
|
||||
|
||||
config DMA_OF
|
||||
def_bool y
|
||||
depends on OF
|
||||
select DMA_ENGINE
|
||||
|
||||
comment "DMA Clients"
|
||||
depends on DMA_ENGINE
|
||||
|
||||
config ASYNC_TX_DMA
|
||||
bool "Async_tx: Offload support for the async_tx api"
|
||||
depends on DMA_ENGINE
|
||||
help
|
||||
This allows the async_tx api to take advantage of offload engines for
|
||||
memcpy, memset, xor, and raid6 p+q operations. If your platform has
|
||||
a dma engine that can perform raid operations and you have enabled
|
||||
MD_RAID456 say Y.
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
config DMATEST
|
||||
tristate "DMA Test client"
|
||||
depends on DMA_ENGINE
|
||||
help
|
||||
Simple DMA test client. Say N unless you're debugging a
|
||||
DMA Device driver.
|
||||
|
||||
config DMA_ENGINE_RAID
|
||||
bool
|
||||
|
||||
config QCOM_BAM_DMA
|
||||
tristate "QCOM BAM DMA support"
|
||||
depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM)
|
||||
select DMA_ENGINE
|
||||
select DMA_VIRTUAL_CHANNELS
|
||||
---help---
|
||||
Enable support for the QCOM BAM DMA controller. This controller
|
||||
provides DMA capabilities for a variety of on-chip devices.
|
||||
|
||||
endif
|
||||
51
drivers/dma/Makefile
Normal file
51
drivers/dma/Makefile
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
subdir-ccflags-$(CONFIG_DMADEVICES_DEBUG) := -DDEBUG
|
||||
subdir-ccflags-$(CONFIG_DMADEVICES_VDEBUG) += -DVERBOSE_DEBUG
|
||||
|
||||
obj-$(CONFIG_DMA_ENGINE) += dmaengine.o
|
||||
obj-$(CONFIG_DMA_VIRTUAL_CHANNELS) += virt-dma.o
|
||||
obj-$(CONFIG_DMA_ACPI) += acpi-dma.o
|
||||
obj-$(CONFIG_DMA_OF) += of-dma.o
|
||||
|
||||
obj-$(CONFIG_INTEL_MID_DMAC) += intel_mid_dma.o
|
||||
obj-$(CONFIG_DMATEST) += dmatest.o
|
||||
obj-$(CONFIG_INTEL_IOATDMA) += ioat/
|
||||
obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
|
||||
obj-$(CONFIG_FSL_DMA) += fsldma.o
|
||||
obj-$(CONFIG_MPC512X_DMA) += mpc512x_dma.o
|
||||
obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
|
||||
obj-$(CONFIG_MV_XOR) += mv_xor.o
|
||||
obj-$(CONFIG_DW_DMAC_CORE) += dw/
|
||||
obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
|
||||
obj-$(CONFIG_MX3_IPU) += ipu/
|
||||
obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
|
||||
obj-$(CONFIG_SH_DMAE_BASE) += sh/
|
||||
obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
|
||||
obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/
|
||||
obj-$(CONFIG_IMX_SDMA) += imx-sdma.o
|
||||
obj-$(CONFIG_IMX_DMA) += imx-dma.o
|
||||
obj-$(CONFIG_MXS_DMA) += mxs-dma.o
|
||||
obj-$(CONFIG_TIMB_DMA) += timb_dma.o
|
||||
obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
|
||||
obj-$(CONFIG_TI_EDMA) += edma.o
|
||||
obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
|
||||
obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
|
||||
obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o
|
||||
obj-$(CONFIG_PL330_DMA) += pl330.o samsung-dma.o
|
||||
obj-$(CONFIG_PCH_DMA) += pch_dma.o
|
||||
obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o
|
||||
obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
|
||||
obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
|
||||
obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
|
||||
obj-$(CONFIG_DMA_OMAP) += omap-dma.o
|
||||
obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o
|
||||
obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
|
||||
obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
|
||||
obj-$(CONFIG_TI_CPPI41) += cppi41.o
|
||||
obj-$(CONFIG_K3_DMA) += k3dma.o
|
||||
obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
|
||||
obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
|
||||
obj-$(CONFIG_QCOM_BAM_DMA) += qcom_bam_dma.o
|
||||
obj-y += xilinx/
|
||||
obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o
|
||||
obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o
|
||||
obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o
|
||||
12
drivers/dma/TODO
Normal file
12
drivers/dma/TODO
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
TODO for slave dma
|
||||
|
||||
1. Move remaining drivers to use new slave interface
|
||||
2. Remove old slave pointer machansim
|
||||
3. Make issue_pending to start the transaction in below drivers
|
||||
- mpc512x_dma
|
||||
- imx-dma
|
||||
- imx-sdma
|
||||
- mxs-dma.c
|
||||
- intel_mid_dma
|
||||
4. Check other subsystems for dma drivers and merge/move to dmaengine
|
||||
5. Remove dma_slave_config's dma direction.
|
||||
456
drivers/dma/acpi-dma.c
Normal file
456
drivers/dma/acpi-dma.c
Normal file
|
|
@ -0,0 +1,456 @@
|
|||
/*
|
||||
* ACPI helpers for DMA request / controller
|
||||
*
|
||||
* Based on of-dma.c
|
||||
*
|
||||
* Copyright (C) 2013, Intel Corporation
|
||||
* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||
* Mika Westerberg <mika.westerberg@linux.intel.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/acpi_dma.h>
|
||||
|
||||
static LIST_HEAD(acpi_dma_list);
|
||||
static DEFINE_MUTEX(acpi_dma_lock);
|
||||
|
||||
/**
|
||||
* acpi_dma_parse_resource_group - match device and parse resource group
|
||||
* @grp: CSRT resource group
|
||||
* @adev: ACPI device to match with
|
||||
* @adma: struct acpi_dma of the given DMA controller
|
||||
*
|
||||
* In order to match a device from DSDT table to the corresponding CSRT device
|
||||
* we use MMIO address and IRQ.
|
||||
*
|
||||
* Return:
|
||||
* 1 on success, 0 when no information is available, or appropriate errno value
|
||||
* on error.
|
||||
*/
|
||||
static int acpi_dma_parse_resource_group(const struct acpi_csrt_group *grp,
|
||||
struct acpi_device *adev, struct acpi_dma *adma)
|
||||
{
|
||||
const struct acpi_csrt_shared_info *si;
|
||||
struct list_head resource_list;
|
||||
struct resource_list_entry *rentry;
|
||||
resource_size_t mem = 0, irq = 0;
|
||||
int ret;
|
||||
|
||||
if (grp->shared_info_length != sizeof(struct acpi_csrt_shared_info))
|
||||
return -ENODEV;
|
||||
|
||||
INIT_LIST_HEAD(&resource_list);
|
||||
ret = acpi_dev_get_resources(adev, &resource_list, NULL, NULL);
|
||||
if (ret <= 0)
|
||||
return 0;
|
||||
|
||||
list_for_each_entry(rentry, &resource_list, node) {
|
||||
if (resource_type(&rentry->res) == IORESOURCE_MEM)
|
||||
mem = rentry->res.start;
|
||||
else if (resource_type(&rentry->res) == IORESOURCE_IRQ)
|
||||
irq = rentry->res.start;
|
||||
}
|
||||
|
||||
acpi_dev_free_resource_list(&resource_list);
|
||||
|
||||
/* Consider initial zero values as resource not found */
|
||||
if (mem == 0 && irq == 0)
|
||||
return 0;
|
||||
|
||||
si = (const struct acpi_csrt_shared_info *)&grp[1];
|
||||
|
||||
/* Match device by MMIO and IRQ */
|
||||
if (si->mmio_base_low != mem || si->gsi_interrupt != irq)
|
||||
return 0;
|
||||
|
||||
dev_dbg(&adev->dev, "matches with %.4s%04X (rev %u)\n",
|
||||
(char *)&grp->vendor_id, grp->device_id, grp->revision);
|
||||
|
||||
/* Check if the request line range is available */
|
||||
if (si->base_request_line == 0 && si->num_handshake_signals == 0)
|
||||
return 0;
|
||||
|
||||
adma->base_request_line = si->base_request_line;
|
||||
adma->end_request_line = si->base_request_line +
|
||||
si->num_handshake_signals - 1;
|
||||
|
||||
dev_dbg(&adev->dev, "request line base: 0x%04x end: 0x%04x\n",
|
||||
adma->base_request_line, adma->end_request_line);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* acpi_dma_parse_csrt - parse CSRT to exctract additional DMA resources
|
||||
* @adev: ACPI device to match with
|
||||
* @adma: struct acpi_dma of the given DMA controller
|
||||
*
|
||||
* CSRT or Core System Resources Table is a proprietary ACPI table
|
||||
* introduced by Microsoft. This table can contain devices that are not in
|
||||
* the system DSDT table. In particular DMA controllers might be described
|
||||
* here.
|
||||
*
|
||||
* We are using this table to get the request line range of the specific DMA
|
||||
* controller to be used later.
|
||||
*/
|
||||
static void acpi_dma_parse_csrt(struct acpi_device *adev, struct acpi_dma *adma)
|
||||
{
|
||||
struct acpi_csrt_group *grp, *end;
|
||||
struct acpi_table_csrt *csrt;
|
||||
acpi_status status;
|
||||
int ret;
|
||||
|
||||
status = acpi_get_table(ACPI_SIG_CSRT, 0,
|
||||
(struct acpi_table_header **)&csrt);
|
||||
if (ACPI_FAILURE(status)) {
|
||||
if (status != AE_NOT_FOUND)
|
||||
dev_warn(&adev->dev, "failed to get the CSRT table\n");
|
||||
return;
|
||||
}
|
||||
|
||||
grp = (struct acpi_csrt_group *)(csrt + 1);
|
||||
end = (struct acpi_csrt_group *)((void *)csrt + csrt->header.length);
|
||||
|
||||
while (grp < end) {
|
||||
ret = acpi_dma_parse_resource_group(grp, adev, adma);
|
||||
if (ret < 0) {
|
||||
dev_warn(&adev->dev,
|
||||
"error in parsing resource group\n");
|
||||
return;
|
||||
}
|
||||
|
||||
grp = (struct acpi_csrt_group *)((void *)grp + grp->length);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* acpi_dma_controller_register - Register a DMA controller to ACPI DMA helpers
|
||||
* @dev: struct device of DMA controller
|
||||
* @acpi_dma_xlate: translation function which converts a dma specifier
|
||||
* into a dma_chan structure
|
||||
* @data pointer to controller specific data to be used by
|
||||
* translation function
|
||||
*
|
||||
* Allocated memory should be freed with appropriate acpi_dma_controller_free()
|
||||
* call.
|
||||
*
|
||||
* Return:
|
||||
* 0 on success or appropriate errno value on error.
|
||||
*/
|
||||
int acpi_dma_controller_register(struct device *dev,
|
||||
struct dma_chan *(*acpi_dma_xlate)
|
||||
(struct acpi_dma_spec *, struct acpi_dma *),
|
||||
void *data)
|
||||
{
|
||||
struct acpi_device *adev;
|
||||
struct acpi_dma *adma;
|
||||
|
||||
if (!dev || !acpi_dma_xlate)
|
||||
return -EINVAL;
|
||||
|
||||
/* Check if the device was enumerated by ACPI */
|
||||
if (!ACPI_HANDLE(dev))
|
||||
return -EINVAL;
|
||||
|
||||
if (acpi_bus_get_device(ACPI_HANDLE(dev), &adev))
|
||||
return -EINVAL;
|
||||
|
||||
adma = kzalloc(sizeof(*adma), GFP_KERNEL);
|
||||
if (!adma)
|
||||
return -ENOMEM;
|
||||
|
||||
adma->dev = dev;
|
||||
adma->acpi_dma_xlate = acpi_dma_xlate;
|
||||
adma->data = data;
|
||||
|
||||
acpi_dma_parse_csrt(adev, adma);
|
||||
|
||||
/* Now queue acpi_dma controller structure in list */
|
||||
mutex_lock(&acpi_dma_lock);
|
||||
list_add_tail(&adma->dma_controllers, &acpi_dma_list);
|
||||
mutex_unlock(&acpi_dma_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(acpi_dma_controller_register);
|
||||
|
||||
/**
|
||||
* acpi_dma_controller_free - Remove a DMA controller from ACPI DMA helpers list
|
||||
* @dev: struct device of DMA controller
|
||||
*
|
||||
* Memory allocated by acpi_dma_controller_register() is freed here.
|
||||
*
|
||||
* Return:
|
||||
* 0 on success or appropriate errno value on error.
|
||||
*/
|
||||
int acpi_dma_controller_free(struct device *dev)
|
||||
{
|
||||
struct acpi_dma *adma;
|
||||
|
||||
if (!dev)
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&acpi_dma_lock);
|
||||
|
||||
list_for_each_entry(adma, &acpi_dma_list, dma_controllers)
|
||||
if (adma->dev == dev) {
|
||||
list_del(&adma->dma_controllers);
|
||||
mutex_unlock(&acpi_dma_lock);
|
||||
kfree(adma);
|
||||
return 0;
|
||||
}
|
||||
|
||||
mutex_unlock(&acpi_dma_lock);
|
||||
return -ENODEV;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(acpi_dma_controller_free);
|
||||
|
||||
static void devm_acpi_dma_release(struct device *dev, void *res)
|
||||
{
|
||||
acpi_dma_controller_free(dev);
|
||||
}
|
||||
|
||||
/**
|
||||
* devm_acpi_dma_controller_register - resource managed acpi_dma_controller_register()
|
||||
* @dev: device that is registering this DMA controller
|
||||
* @acpi_dma_xlate: translation function
|
||||
* @data pointer to controller specific data
|
||||
*
|
||||
* Managed acpi_dma_controller_register(). DMA controller registered by this
|
||||
* function are automatically freed on driver detach. See
|
||||
* acpi_dma_controller_register() for more information.
|
||||
*
|
||||
* Return:
|
||||
* 0 on success or appropriate errno value on error.
|
||||
*/
|
||||
int devm_acpi_dma_controller_register(struct device *dev,
|
||||
struct dma_chan *(*acpi_dma_xlate)
|
||||
(struct acpi_dma_spec *, struct acpi_dma *),
|
||||
void *data)
|
||||
{
|
||||
void *res;
|
||||
int ret;
|
||||
|
||||
res = devres_alloc(devm_acpi_dma_release, 0, GFP_KERNEL);
|
||||
if (!res)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = acpi_dma_controller_register(dev, acpi_dma_xlate, data);
|
||||
if (ret) {
|
||||
devres_free(res);
|
||||
return ret;
|
||||
}
|
||||
devres_add(dev, res);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(devm_acpi_dma_controller_register);
|
||||
|
||||
/**
|
||||
* devm_acpi_dma_controller_free - resource managed acpi_dma_controller_free()
|
||||
*
|
||||
* Unregister a DMA controller registered with
|
||||
* devm_acpi_dma_controller_register(). Normally this function will not need to
|
||||
* be called and the resource management code will ensure that the resource is
|
||||
* freed.
|
||||
*/
|
||||
void devm_acpi_dma_controller_free(struct device *dev)
|
||||
{
|
||||
WARN_ON(devres_release(dev, devm_acpi_dma_release, NULL, NULL));
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(devm_acpi_dma_controller_free);
|
||||
|
||||
/**
|
||||
* acpi_dma_update_dma_spec - prepare dma specifier to pass to translation function
|
||||
* @adma: struct acpi_dma of DMA controller
|
||||
* @dma_spec: dma specifier to update
|
||||
*
|
||||
* Accordingly to ACPI 5.0 Specification Table 6-170 "Fixed DMA Resource
|
||||
* Descriptor":
|
||||
* DMA Request Line bits is a platform-relative number uniquely
|
||||
* identifying the request line assigned. Request line-to-Controller
|
||||
* mapping is done in a controller-specific OS driver.
|
||||
* That's why we can safely adjust slave_id when the appropriate controller is
|
||||
* found.
|
||||
*
|
||||
* Return:
|
||||
* 0, if no information is avaiable, -1 on mismatch, and 1 otherwise.
|
||||
*/
|
||||
static int acpi_dma_update_dma_spec(struct acpi_dma *adma,
|
||||
struct acpi_dma_spec *dma_spec)
|
||||
{
|
||||
/* Set link to the DMA controller device */
|
||||
dma_spec->dev = adma->dev;
|
||||
|
||||
/* Check if the request line range is available */
|
||||
if (adma->base_request_line == 0 && adma->end_request_line == 0)
|
||||
return 0;
|
||||
|
||||
/* Check if slave_id falls to the range */
|
||||
if (dma_spec->slave_id < adma->base_request_line ||
|
||||
dma_spec->slave_id > adma->end_request_line)
|
||||
return -1;
|
||||
|
||||
/*
|
||||
* Here we adjust slave_id. It should be a relative number to the base
|
||||
* request line.
|
||||
*/
|
||||
dma_spec->slave_id -= adma->base_request_line;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
struct acpi_dma_parser_data {
|
||||
struct acpi_dma_spec dma_spec;
|
||||
size_t index;
|
||||
size_t n;
|
||||
};
|
||||
|
||||
/**
|
||||
* acpi_dma_parse_fixed_dma - Parse FixedDMA ACPI resources to a DMA specifier
|
||||
* @res: struct acpi_resource to get FixedDMA resources from
|
||||
* @data: pointer to a helper struct acpi_dma_parser_data
|
||||
*/
|
||||
static int acpi_dma_parse_fixed_dma(struct acpi_resource *res, void *data)
|
||||
{
|
||||
struct acpi_dma_parser_data *pdata = data;
|
||||
|
||||
if (res->type == ACPI_RESOURCE_TYPE_FIXED_DMA) {
|
||||
struct acpi_resource_fixed_dma *dma = &res->data.fixed_dma;
|
||||
|
||||
if (pdata->n++ == pdata->index) {
|
||||
pdata->dma_spec.chan_id = dma->channels;
|
||||
pdata->dma_spec.slave_id = dma->request_lines;
|
||||
}
|
||||
}
|
||||
|
||||
/* Tell the ACPI core to skip this resource */
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* acpi_dma_request_slave_chan_by_index - Get the DMA slave channel
|
||||
* @dev: struct device to get DMA request from
|
||||
* @index: index of FixedDMA descriptor for @dev
|
||||
*
|
||||
* Return:
|
||||
* Pointer to appropriate dma channel on success or an error pointer.
|
||||
*/
|
||||
struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
|
||||
size_t index)
|
||||
{
|
||||
struct acpi_dma_parser_data pdata;
|
||||
struct acpi_dma_spec *dma_spec = &pdata.dma_spec;
|
||||
struct list_head resource_list;
|
||||
struct acpi_device *adev;
|
||||
struct acpi_dma *adma;
|
||||
struct dma_chan *chan = NULL;
|
||||
int found;
|
||||
|
||||
/* Check if the device was enumerated by ACPI */
|
||||
if (!dev || !ACPI_HANDLE(dev))
|
||||
return ERR_PTR(-ENODEV);
|
||||
|
||||
if (acpi_bus_get_device(ACPI_HANDLE(dev), &adev))
|
||||
return ERR_PTR(-ENODEV);
|
||||
|
||||
memset(&pdata, 0, sizeof(pdata));
|
||||
pdata.index = index;
|
||||
|
||||
/* Initial values for the request line and channel */
|
||||
dma_spec->chan_id = -1;
|
||||
dma_spec->slave_id = -1;
|
||||
|
||||
INIT_LIST_HEAD(&resource_list);
|
||||
acpi_dev_get_resources(adev, &resource_list,
|
||||
acpi_dma_parse_fixed_dma, &pdata);
|
||||
acpi_dev_free_resource_list(&resource_list);
|
||||
|
||||
if (dma_spec->slave_id < 0 || dma_spec->chan_id < 0)
|
||||
return ERR_PTR(-ENODEV);
|
||||
|
||||
mutex_lock(&acpi_dma_lock);
|
||||
|
||||
list_for_each_entry(adma, &acpi_dma_list, dma_controllers) {
|
||||
/*
|
||||
* We are not going to call translation function if slave_id
|
||||
* doesn't fall to the request range.
|
||||
*/
|
||||
found = acpi_dma_update_dma_spec(adma, dma_spec);
|
||||
if (found < 0)
|
||||
continue;
|
||||
chan = adma->acpi_dma_xlate(dma_spec, adma);
|
||||
/*
|
||||
* Try to get a channel only from the DMA controller that
|
||||
* matches the slave_id. See acpi_dma_update_dma_spec()
|
||||
* description for the details.
|
||||
*/
|
||||
if (found > 0 || chan)
|
||||
break;
|
||||
}
|
||||
|
||||
mutex_unlock(&acpi_dma_lock);
|
||||
return chan ? chan : ERR_PTR(-EPROBE_DEFER);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(acpi_dma_request_slave_chan_by_index);
|
||||
|
||||
/**
|
||||
* acpi_dma_request_slave_chan_by_name - Get the DMA slave channel
|
||||
* @dev: struct device to get DMA request from
|
||||
* @name: represents corresponding FixedDMA descriptor for @dev
|
||||
*
|
||||
* In order to support both Device Tree and ACPI in a single driver we
|
||||
* translate the names "tx" and "rx" here based on the most common case where
|
||||
* the first FixedDMA descriptor is TX and second is RX.
|
||||
*
|
||||
* Return:
|
||||
* Pointer to appropriate dma channel on success or an error pointer.
|
||||
*/
|
||||
struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
|
||||
const char *name)
|
||||
{
|
||||
size_t index;
|
||||
|
||||
if (!strcmp(name, "tx"))
|
||||
index = 0;
|
||||
else if (!strcmp(name, "rx"))
|
||||
index = 1;
|
||||
else
|
||||
return ERR_PTR(-ENODEV);
|
||||
|
||||
return acpi_dma_request_slave_chan_by_index(dev, index);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(acpi_dma_request_slave_chan_by_name);
|
||||
|
||||
/**
|
||||
* acpi_dma_simple_xlate - Simple ACPI DMA engine translation helper
|
||||
* @dma_spec: pointer to ACPI DMA specifier
|
||||
* @adma: pointer to ACPI DMA controller data
|
||||
*
|
||||
* A simple translation function for ACPI based devices. Passes &struct
|
||||
* dma_spec to the DMA controller driver provided filter function.
|
||||
*
|
||||
* Return:
|
||||
* Pointer to the channel if found or %NULL otherwise.
|
||||
*/
|
||||
struct dma_chan *acpi_dma_simple_xlate(struct acpi_dma_spec *dma_spec,
|
||||
struct acpi_dma *adma)
|
||||
{
|
||||
struct acpi_dma_filter_info *info = adma->data;
|
||||
|
||||
if (!info || !info->filter_fn)
|
||||
return NULL;
|
||||
|
||||
return dma_request_channel(info->dma_cap, info->filter_fn, dma_spec);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(acpi_dma_simple_xlate);
|
||||
2302
drivers/dma/amba-pl08x.c
Normal file
2302
drivers/dma/amba-pl08x.c
Normal file
File diff suppressed because it is too large
Load diff
1737
drivers/dma/at_hdmac.c
Normal file
1737
drivers/dma/at_hdmac.c
Normal file
File diff suppressed because it is too large
Load diff
452
drivers/dma/at_hdmac_regs.h
Normal file
452
drivers/dma/at_hdmac_regs.h
Normal file
|
|
@ -0,0 +1,452 @@
|
|||
/*
|
||||
* Header file for the Atmel AHB DMA Controller driver
|
||||
*
|
||||
* Copyright (C) 2008 Atmel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
#ifndef AT_HDMAC_REGS_H
|
||||
#define AT_HDMAC_REGS_H
|
||||
|
||||
#include <linux/platform_data/dma-atmel.h>
|
||||
|
||||
#define AT_DMA_MAX_NR_CHANNELS 8
|
||||
|
||||
|
||||
#define AT_DMA_GCFG 0x00 /* Global Configuration Register */
|
||||
#define AT_DMA_IF_BIGEND(i) (0x1 << (i)) /* AHB-Lite Interface i in Big-endian mode */
|
||||
#define AT_DMA_ARB_CFG (0x1 << 4) /* Arbiter mode. */
|
||||
#define AT_DMA_ARB_CFG_FIXED (0x0 << 4)
|
||||
#define AT_DMA_ARB_CFG_ROUND_ROBIN (0x1 << 4)
|
||||
|
||||
#define AT_DMA_EN 0x04 /* Controller Enable Register */
|
||||
#define AT_DMA_ENABLE (0x1 << 0)
|
||||
|
||||
#define AT_DMA_SREQ 0x08 /* Software Single Request Register */
|
||||
#define AT_DMA_SSREQ(x) (0x1 << ((x) << 1)) /* Request a source single transfer on channel x */
|
||||
#define AT_DMA_DSREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination single transfer on channel x */
|
||||
|
||||
#define AT_DMA_CREQ 0x0C /* Software Chunk Transfer Request Register */
|
||||
#define AT_DMA_SCREQ(x) (0x1 << ((x) << 1)) /* Request a source chunk transfer on channel x */
|
||||
#define AT_DMA_DCREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination chunk transfer on channel x */
|
||||
|
||||
#define AT_DMA_LAST 0x10 /* Software Last Transfer Flag Register */
|
||||
#define AT_DMA_SLAST(x) (0x1 << ((x) << 1)) /* This src rq is last tx of buffer on channel x */
|
||||
#define AT_DMA_DLAST(x) (0x1 << (1 + ((x) << 1))) /* This dst rq is last tx of buffer on channel x */
|
||||
|
||||
#define AT_DMA_SYNC 0x14 /* Request Synchronization Register */
|
||||
#define AT_DMA_SYR(h) (0x1 << (h)) /* Synchronize handshake line h */
|
||||
|
||||
/* Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt registers */
|
||||
#define AT_DMA_EBCIER 0x18 /* Enable register */
|
||||
#define AT_DMA_EBCIDR 0x1C /* Disable register */
|
||||
#define AT_DMA_EBCIMR 0x20 /* Mask Register */
|
||||
#define AT_DMA_EBCISR 0x24 /* Status Register */
|
||||
#define AT_DMA_CBTC_OFFSET 8
|
||||
#define AT_DMA_ERR_OFFSET 16
|
||||
#define AT_DMA_BTC(x) (0x1 << (x))
|
||||
#define AT_DMA_CBTC(x) (0x1 << (AT_DMA_CBTC_OFFSET + (x)))
|
||||
#define AT_DMA_ERR(x) (0x1 << (AT_DMA_ERR_OFFSET + (x)))
|
||||
|
||||
#define AT_DMA_CHER 0x28 /* Channel Handler Enable Register */
|
||||
#define AT_DMA_ENA(x) (0x1 << (x))
|
||||
#define AT_DMA_SUSP(x) (0x1 << ( 8 + (x)))
|
||||
#define AT_DMA_KEEP(x) (0x1 << (24 + (x)))
|
||||
|
||||
#define AT_DMA_CHDR 0x2C /* Channel Handler Disable Register */
|
||||
#define AT_DMA_DIS(x) (0x1 << (x))
|
||||
#define AT_DMA_RES(x) (0x1 << ( 8 + (x)))
|
||||
|
||||
#define AT_DMA_CHSR 0x30 /* Channel Handler Status Register */
|
||||
#define AT_DMA_EMPT(x) (0x1 << (16 + (x)))
|
||||
#define AT_DMA_STAL(x) (0x1 << (24 + (x)))
|
||||
|
||||
|
||||
#define AT_DMA_CH_REGS_BASE 0x3C /* Channel registers base address */
|
||||
#define ch_regs(x) (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */
|
||||
|
||||
/* Hardware register offset for each channel */
|
||||
#define ATC_SADDR_OFFSET 0x00 /* Source Address Register */
|
||||
#define ATC_DADDR_OFFSET 0x04 /* Destination Address Register */
|
||||
#define ATC_DSCR_OFFSET 0x08 /* Descriptor Address Register */
|
||||
#define ATC_CTRLA_OFFSET 0x0C /* Control A Register */
|
||||
#define ATC_CTRLB_OFFSET 0x10 /* Control B Register */
|
||||
#define ATC_CFG_OFFSET 0x14 /* Configuration Register */
|
||||
#define ATC_SPIP_OFFSET 0x18 /* Src PIP Configuration Register */
|
||||
#define ATC_DPIP_OFFSET 0x1C /* Dst PIP Configuration Register */
|
||||
|
||||
|
||||
/* Bitfield definitions */
|
||||
|
||||
/* Bitfields in DSCR */
|
||||
#define ATC_DSCR_IF(i) (0x3 & (i)) /* Dsc feched via AHB-Lite Interface i */
|
||||
|
||||
/* Bitfields in CTRLA */
|
||||
#define ATC_BTSIZE_MAX 0xFFFFUL /* Maximum Buffer Transfer Size */
|
||||
#define ATC_BTSIZE(x) (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */
|
||||
#define ATC_SCSIZE_MASK (0x7 << 16) /* Source Chunk Transfer Size */
|
||||
#define ATC_SCSIZE(x) (ATC_SCSIZE_MASK & ((x) << 16))
|
||||
#define ATC_SCSIZE_1 (0x0 << 16)
|
||||
#define ATC_SCSIZE_4 (0x1 << 16)
|
||||
#define ATC_SCSIZE_8 (0x2 << 16)
|
||||
#define ATC_SCSIZE_16 (0x3 << 16)
|
||||
#define ATC_SCSIZE_32 (0x4 << 16)
|
||||
#define ATC_SCSIZE_64 (0x5 << 16)
|
||||
#define ATC_SCSIZE_128 (0x6 << 16)
|
||||
#define ATC_SCSIZE_256 (0x7 << 16)
|
||||
#define ATC_DCSIZE_MASK (0x7 << 20) /* Destination Chunk Transfer Size */
|
||||
#define ATC_DCSIZE(x) (ATC_DCSIZE_MASK & ((x) << 20))
|
||||
#define ATC_DCSIZE_1 (0x0 << 20)
|
||||
#define ATC_DCSIZE_4 (0x1 << 20)
|
||||
#define ATC_DCSIZE_8 (0x2 << 20)
|
||||
#define ATC_DCSIZE_16 (0x3 << 20)
|
||||
#define ATC_DCSIZE_32 (0x4 << 20)
|
||||
#define ATC_DCSIZE_64 (0x5 << 20)
|
||||
#define ATC_DCSIZE_128 (0x6 << 20)
|
||||
#define ATC_DCSIZE_256 (0x7 << 20)
|
||||
#define ATC_SRC_WIDTH_MASK (0x3 << 24) /* Source Single Transfer Size */
|
||||
#define ATC_SRC_WIDTH(x) ((x) << 24)
|
||||
#define ATC_SRC_WIDTH_BYTE (0x0 << 24)
|
||||
#define ATC_SRC_WIDTH_HALFWORD (0x1 << 24)
|
||||
#define ATC_SRC_WIDTH_WORD (0x2 << 24)
|
||||
#define ATC_DST_WIDTH_MASK (0x3 << 28) /* Destination Single Transfer Size */
|
||||
#define ATC_DST_WIDTH(x) ((x) << 28)
|
||||
#define ATC_DST_WIDTH_BYTE (0x0 << 28)
|
||||
#define ATC_DST_WIDTH_HALFWORD (0x1 << 28)
|
||||
#define ATC_DST_WIDTH_WORD (0x2 << 28)
|
||||
#define ATC_DONE (0x1 << 31) /* Tx Done (only written back in descriptor) */
|
||||
|
||||
/* Bitfields in CTRLB */
|
||||
#define ATC_SIF(i) (0x3 & (i)) /* Src tx done via AHB-Lite Interface i */
|
||||
#define ATC_DIF(i) ((0x3 & (i)) << 4) /* Dst tx done via AHB-Lite Interface i */
|
||||
/* Specify AHB interfaces */
|
||||
#define AT_DMA_MEM_IF 0 /* interface 0 as memory interface */
|
||||
#define AT_DMA_PER_IF 1 /* interface 1 as peripheral interface */
|
||||
|
||||
#define ATC_SRC_PIP (0x1 << 8) /* Source Picture-in-Picture enabled */
|
||||
#define ATC_DST_PIP (0x1 << 12) /* Destination Picture-in-Picture enabled */
|
||||
#define ATC_SRC_DSCR_DIS (0x1 << 16) /* Src Descriptor fetch disable */
|
||||
#define ATC_DST_DSCR_DIS (0x1 << 20) /* Dst Descriptor fetch disable */
|
||||
#define ATC_FC_MASK (0x7 << 21) /* Choose Flow Controller */
|
||||
#define ATC_FC_MEM2MEM (0x0 << 21) /* Mem-to-Mem (DMA) */
|
||||
#define ATC_FC_MEM2PER (0x1 << 21) /* Mem-to-Periph (DMA) */
|
||||
#define ATC_FC_PER2MEM (0x2 << 21) /* Periph-to-Mem (DMA) */
|
||||
#define ATC_FC_PER2PER (0x3 << 21) /* Periph-to-Periph (DMA) */
|
||||
#define ATC_FC_PER2MEM_PER (0x4 << 21) /* Periph-to-Mem (Peripheral) */
|
||||
#define ATC_FC_MEM2PER_PER (0x5 << 21) /* Mem-to-Periph (Peripheral) */
|
||||
#define ATC_FC_PER2PER_SRCPER (0x6 << 21) /* Periph-to-Periph (Src Peripheral) */
|
||||
#define ATC_FC_PER2PER_DSTPER (0x7 << 21) /* Periph-to-Periph (Dst Peripheral) */
|
||||
#define ATC_SRC_ADDR_MODE_MASK (0x3 << 24)
|
||||
#define ATC_SRC_ADDR_MODE_INCR (0x0 << 24) /* Incrementing Mode */
|
||||
#define ATC_SRC_ADDR_MODE_DECR (0x1 << 24) /* Decrementing Mode */
|
||||
#define ATC_SRC_ADDR_MODE_FIXED (0x2 << 24) /* Fixed Mode */
|
||||
#define ATC_DST_ADDR_MODE_MASK (0x3 << 28)
|
||||
#define ATC_DST_ADDR_MODE_INCR (0x0 << 28) /* Incrementing Mode */
|
||||
#define ATC_DST_ADDR_MODE_DECR (0x1 << 28) /* Decrementing Mode */
|
||||
#define ATC_DST_ADDR_MODE_FIXED (0x2 << 28) /* Fixed Mode */
|
||||
#define ATC_IEN (0x1 << 30) /* BTC interrupt enable (active low) */
|
||||
#define ATC_AUTO (0x1 << 31) /* Auto multiple buffer tx enable */
|
||||
|
||||
/* Bitfields in CFG */
|
||||
/* are in at_hdmac.h */
|
||||
|
||||
/* Bitfields in SPIP */
|
||||
#define ATC_SPIP_HOLE(x) (0xFFFFU & (x))
|
||||
#define ATC_SPIP_BOUNDARY(x) ((0x3FF & (x)) << 16)
|
||||
|
||||
/* Bitfields in DPIP */
|
||||
#define ATC_DPIP_HOLE(x) (0xFFFFU & (x))
|
||||
#define ATC_DPIP_BOUNDARY(x) ((0x3FF & (x)) << 16)
|
||||
|
||||
|
||||
/*-- descriptors -----------------------------------------------------*/
|
||||
|
||||
/* LLI == Linked List Item; aka DMA buffer descriptor */
|
||||
struct at_lli {
|
||||
/* values that are not changed by hardware */
|
||||
dma_addr_t saddr;
|
||||
dma_addr_t daddr;
|
||||
/* value that may get written back: */
|
||||
u32 ctrla;
|
||||
/* more values that are not changed by hardware */
|
||||
u32 ctrlb;
|
||||
dma_addr_t dscr; /* chain to next lli */
|
||||
};
|
||||
|
||||
/**
|
||||
* struct at_desc - software descriptor
|
||||
* @at_lli: hardware lli structure
|
||||
* @txd: support for the async_tx api
|
||||
* @desc_node: node on the channed descriptors list
|
||||
* @len: total transaction bytecount
|
||||
* @tx_width: transfer width
|
||||
*/
|
||||
struct at_desc {
|
||||
/* FIRST values the hardware uses */
|
||||
struct at_lli lli;
|
||||
|
||||
/* THEN values for driver housekeeping */
|
||||
struct list_head tx_list;
|
||||
struct dma_async_tx_descriptor txd;
|
||||
struct list_head desc_node;
|
||||
size_t len;
|
||||
u32 tx_width;
|
||||
};
|
||||
|
||||
static inline struct at_desc *
|
||||
txd_to_at_desc(struct dma_async_tx_descriptor *txd)
|
||||
{
|
||||
return container_of(txd, struct at_desc, txd);
|
||||
}
|
||||
|
||||
|
||||
/*-- Channels --------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* atc_status - information bits stored in channel status flag
|
||||
*
|
||||
* Manipulated with atomic operations.
|
||||
*/
|
||||
enum atc_status {
|
||||
ATC_IS_ERROR = 0,
|
||||
ATC_IS_PAUSED = 1,
|
||||
ATC_IS_BTC = 2,
|
||||
ATC_IS_CYCLIC = 24,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct at_dma_chan - internal representation of an Atmel HDMAC channel
|
||||
* @chan_common: common dmaengine channel object members
|
||||
* @device: parent device
|
||||
* @ch_regs: memory mapped register base
|
||||
* @mask: channel index in a mask
|
||||
* @per_if: peripheral interface
|
||||
* @mem_if: memory interface
|
||||
* @status: transmit status information from irq/prep* functions
|
||||
* to tasklet (use atomic operations)
|
||||
* @tasklet: bottom half to finish transaction work
|
||||
* @save_cfg: configuration register that is saved on suspend/resume cycle
|
||||
* @save_dscr: for cyclic operations, preserve next descriptor address in
|
||||
* the cyclic list on suspend/resume cycle
|
||||
* @remain_desc: to save remain desc length
|
||||
* @dma_sconfig: configuration for slave transfers, passed via DMA_SLAVE_CONFIG
|
||||
* @lock: serializes enqueue/dequeue operations to descriptors lists
|
||||
* @active_list: list of descriptors dmaengine is being running on
|
||||
* @queue: list of descriptors ready to be submitted to engine
|
||||
* @free_list: list of descriptors usable by the channel
|
||||
* @descs_allocated: records the actual size of the descriptor pool
|
||||
*/
|
||||
struct at_dma_chan {
|
||||
struct dma_chan chan_common;
|
||||
struct at_dma *device;
|
||||
void __iomem *ch_regs;
|
||||
u8 mask;
|
||||
u8 per_if;
|
||||
u8 mem_if;
|
||||
unsigned long status;
|
||||
struct tasklet_struct tasklet;
|
||||
u32 save_cfg;
|
||||
u32 save_dscr;
|
||||
u32 remain_desc;
|
||||
struct dma_slave_config dma_sconfig;
|
||||
|
||||
spinlock_t lock;
|
||||
|
||||
/* these other elements are all protected by lock */
|
||||
struct list_head active_list;
|
||||
struct list_head queue;
|
||||
struct list_head free_list;
|
||||
unsigned int descs_allocated;
|
||||
};
|
||||
|
||||
#define channel_readl(atchan, name) \
|
||||
__raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET)
|
||||
|
||||
#define channel_writel(atchan, name, val) \
|
||||
__raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET)
|
||||
|
||||
static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan)
|
||||
{
|
||||
return container_of(dchan, struct at_dma_chan, chan_common);
|
||||
}
|
||||
|
||||
/*
|
||||
* Fix sconfig's burst size according to at_hdmac. We need to convert them as:
|
||||
* 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7.
|
||||
*
|
||||
* This can be done by finding most significant bit set.
|
||||
*/
|
||||
static inline void convert_burst(u32 *maxburst)
|
||||
{
|
||||
if (*maxburst > 1)
|
||||
*maxburst = fls(*maxburst) - 2;
|
||||
else
|
||||
*maxburst = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Fix sconfig's bus width according to at_hdmac.
|
||||
* 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2.
|
||||
*/
|
||||
static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width)
|
||||
{
|
||||
switch (addr_width) {
|
||||
case DMA_SLAVE_BUSWIDTH_2_BYTES:
|
||||
return 1;
|
||||
case DMA_SLAVE_BUSWIDTH_4_BYTES:
|
||||
return 2;
|
||||
default:
|
||||
/* For 1 byte width or fallback */
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*-- Controller ------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* struct at_dma - internal representation of an Atmel HDMA Controller
|
||||
* @chan_common: common dmaengine dma_device object members
|
||||
* @atdma_devtype: identifier of DMA controller compatibility
|
||||
* @ch_regs: memory mapped register base
|
||||
* @clk: dma controller clock
|
||||
* @save_imr: interrupt mask register that is saved on suspend/resume cycle
|
||||
* @all_chan_mask: all channels availlable in a mask
|
||||
* @dma_desc_pool: base of DMA descriptor region (DMA address)
|
||||
* @chan: channels table to store at_dma_chan structures
|
||||
*/
|
||||
struct at_dma {
|
||||
struct dma_device dma_common;
|
||||
void __iomem *regs;
|
||||
struct clk *clk;
|
||||
u32 save_imr;
|
||||
|
||||
u8 all_chan_mask;
|
||||
|
||||
struct dma_pool *dma_desc_pool;
|
||||
/* AT THE END channels table */
|
||||
struct at_dma_chan chan[0];
|
||||
};
|
||||
|
||||
#define dma_readl(atdma, name) \
|
||||
__raw_readl((atdma)->regs + AT_DMA_##name)
|
||||
#define dma_writel(atdma, name, val) \
|
||||
__raw_writel((val), (atdma)->regs + AT_DMA_##name)
|
||||
|
||||
static inline struct at_dma *to_at_dma(struct dma_device *ddev)
|
||||
{
|
||||
return container_of(ddev, struct at_dma, dma_common);
|
||||
}
|
||||
|
||||
|
||||
/*-- Helper functions ------------------------------------------------*/
|
||||
|
||||
static struct device *chan2dev(struct dma_chan *chan)
|
||||
{
|
||||
return &chan->dev->device;
|
||||
}
|
||||
|
||||
#if defined(VERBOSE_DEBUG)
|
||||
static void vdbg_dump_regs(struct at_dma_chan *atchan)
|
||||
{
|
||||
struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
|
||||
|
||||
dev_err(chan2dev(&atchan->chan_common),
|
||||
" channel %d : imr = 0x%x, chsr = 0x%x\n",
|
||||
atchan->chan_common.chan_id,
|
||||
dma_readl(atdma, EBCIMR),
|
||||
dma_readl(atdma, CHSR));
|
||||
|
||||
dev_err(chan2dev(&atchan->chan_common),
|
||||
" channel: s0x%x d0x%x ctrl0x%x:0x%x cfg0x%x l0x%x\n",
|
||||
channel_readl(atchan, SADDR),
|
||||
channel_readl(atchan, DADDR),
|
||||
channel_readl(atchan, CTRLA),
|
||||
channel_readl(atchan, CTRLB),
|
||||
channel_readl(atchan, CFG),
|
||||
channel_readl(atchan, DSCR));
|
||||
}
|
||||
#else
|
||||
static void vdbg_dump_regs(struct at_dma_chan *atchan) {}
|
||||
#endif
|
||||
|
||||
static void atc_dump_lli(struct at_dma_chan *atchan, struct at_lli *lli)
|
||||
{
|
||||
dev_crit(chan2dev(&atchan->chan_common),
|
||||
" desc: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n",
|
||||
lli->saddr, lli->daddr,
|
||||
lli->ctrla, lli->ctrlb, lli->dscr);
|
||||
}
|
||||
|
||||
|
||||
static void atc_setup_irq(struct at_dma *atdma, int chan_id, int on)
|
||||
{
|
||||
u32 ebci;
|
||||
|
||||
/* enable interrupts on buffer transfer completion & error */
|
||||
ebci = AT_DMA_BTC(chan_id)
|
||||
| AT_DMA_ERR(chan_id);
|
||||
if (on)
|
||||
dma_writel(atdma, EBCIER, ebci);
|
||||
else
|
||||
dma_writel(atdma, EBCIDR, ebci);
|
||||
}
|
||||
|
||||
static void atc_enable_chan_irq(struct at_dma *atdma, int chan_id)
|
||||
{
|
||||
atc_setup_irq(atdma, chan_id, 1);
|
||||
}
|
||||
|
||||
static void atc_disable_chan_irq(struct at_dma *atdma, int chan_id)
|
||||
{
|
||||
atc_setup_irq(atdma, chan_id, 0);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* atc_chan_is_enabled - test if given channel is enabled
|
||||
* @atchan: channel we want to test status
|
||||
*/
|
||||
static inline int atc_chan_is_enabled(struct at_dma_chan *atchan)
|
||||
{
|
||||
struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
|
||||
|
||||
return !!(dma_readl(atdma, CHSR) & atchan->mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* atc_chan_is_paused - test channel pause/resume status
|
||||
* @atchan: channel we want to test status
|
||||
*/
|
||||
static inline int atc_chan_is_paused(struct at_dma_chan *atchan)
|
||||
{
|
||||
return test_bit(ATC_IS_PAUSED, &atchan->status);
|
||||
}
|
||||
|
||||
/**
|
||||
* atc_chan_is_cyclic - test if given channel has cyclic property set
|
||||
* @atchan: channel we want to test status
|
||||
*/
|
||||
static inline int atc_chan_is_cyclic(struct at_dma_chan *atchan)
|
||||
{
|
||||
return test_bit(ATC_IS_CYCLIC, &atchan->status);
|
||||
}
|
||||
|
||||
/**
|
||||
* set_desc_eol - set end-of-link to descriptor so it will end transfer
|
||||
* @desc: descriptor, signle or at the end of a chain, to end chain on
|
||||
*/
|
||||
static void set_desc_eol(struct at_desc *desc)
|
||||
{
|
||||
u32 ctrlb = desc->lli.ctrlb;
|
||||
|
||||
ctrlb &= ~ATC_IEN;
|
||||
ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS;
|
||||
|
||||
desc->lli.ctrlb = ctrlb;
|
||||
desc->lli.dscr = 0;
|
||||
}
|
||||
|
||||
#endif /* AT_HDMAC_REGS_H */
|
||||
707
drivers/dma/bcm2835-dma.c
Normal file
707
drivers/dma/bcm2835-dma.c
Normal file
|
|
@ -0,0 +1,707 @@
|
|||
/*
|
||||
* BCM2835 DMA engine support
|
||||
*
|
||||
* This driver only supports cyclic DMA transfers
|
||||
* as needed for the I2S module.
|
||||
*
|
||||
* Author: Florian Meier <florian.meier@koalo.de>
|
||||
* Copyright 2013
|
||||
*
|
||||
* Based on
|
||||
* OMAP DMAengine support by Russell King
|
||||
*
|
||||
* BCM2708 DMA Driver
|
||||
* Copyright (C) 2010 Broadcom
|
||||
*
|
||||
* Raspberry Pi PCM I2S ALSA Driver
|
||||
* Copyright (c) by Phil Poole 2013
|
||||
*
|
||||
* MARVELL MMP Peripheral DMA Driver
|
||||
* Copyright 2012 Marvell International Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_dma.h>
|
||||
|
||||
#include "virt-dma.h"
|
||||
|
||||
struct bcm2835_dmadev {
|
||||
struct dma_device ddev;
|
||||
spinlock_t lock;
|
||||
void __iomem *base;
|
||||
struct device_dma_parameters dma_parms;
|
||||
};
|
||||
|
||||
struct bcm2835_dma_cb {
|
||||
uint32_t info;
|
||||
uint32_t src;
|
||||
uint32_t dst;
|
||||
uint32_t length;
|
||||
uint32_t stride;
|
||||
uint32_t next;
|
||||
uint32_t pad[2];
|
||||
};
|
||||
|
||||
struct bcm2835_chan {
|
||||
struct virt_dma_chan vc;
|
||||
struct list_head node;
|
||||
|
||||
struct dma_slave_config cfg;
|
||||
bool cyclic;
|
||||
unsigned int dreq;
|
||||
|
||||
int ch;
|
||||
struct bcm2835_desc *desc;
|
||||
|
||||
void __iomem *chan_base;
|
||||
int irq_number;
|
||||
};
|
||||
|
||||
struct bcm2835_desc {
|
||||
struct virt_dma_desc vd;
|
||||
enum dma_transfer_direction dir;
|
||||
|
||||
unsigned int control_block_size;
|
||||
struct bcm2835_dma_cb *control_block_base;
|
||||
dma_addr_t control_block_base_phys;
|
||||
|
||||
unsigned int frames;
|
||||
size_t size;
|
||||
};
|
||||
|
||||
#define BCM2835_DMA_CS 0x00
|
||||
#define BCM2835_DMA_ADDR 0x04
|
||||
#define BCM2835_DMA_SOURCE_AD 0x0c
|
||||
#define BCM2835_DMA_DEST_AD 0x10
|
||||
#define BCM2835_DMA_NEXTCB 0x1C
|
||||
|
||||
/* DMA CS Control and Status bits */
|
||||
#define BCM2835_DMA_ACTIVE BIT(0)
|
||||
#define BCM2835_DMA_INT BIT(2)
|
||||
#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
|
||||
#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
|
||||
#define BCM2835_DMA_ERR BIT(8)
|
||||
#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */
|
||||
#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */
|
||||
|
||||
#define BCM2835_DMA_INT_EN BIT(0)
|
||||
#define BCM2835_DMA_D_INC BIT(4)
|
||||
#define BCM2835_DMA_D_DREQ BIT(6)
|
||||
#define BCM2835_DMA_S_INC BIT(8)
|
||||
#define BCM2835_DMA_S_DREQ BIT(10)
|
||||
|
||||
#define BCM2835_DMA_PER_MAP(x) ((x) << 16)
|
||||
|
||||
#define BCM2835_DMA_DATA_TYPE_S8 1
|
||||
#define BCM2835_DMA_DATA_TYPE_S16 2
|
||||
#define BCM2835_DMA_DATA_TYPE_S32 4
|
||||
#define BCM2835_DMA_DATA_TYPE_S128 16
|
||||
|
||||
#define BCM2835_DMA_BULK_MASK BIT(0)
|
||||
#define BCM2835_DMA_FIQ_MASK (BIT(2) | BIT(3))
|
||||
|
||||
/* Valid only for channels 0 - 14, 15 has its own base address */
|
||||
#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
|
||||
#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
|
||||
|
||||
static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
|
||||
{
|
||||
return container_of(d, struct bcm2835_dmadev, ddev);
|
||||
}
|
||||
|
||||
static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c)
|
||||
{
|
||||
return container_of(c, struct bcm2835_chan, vc.chan);
|
||||
}
|
||||
|
||||
static inline struct bcm2835_desc *to_bcm2835_dma_desc(
|
||||
struct dma_async_tx_descriptor *t)
|
||||
{
|
||||
return container_of(t, struct bcm2835_desc, vd.tx);
|
||||
}
|
||||
|
||||
static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
|
||||
{
|
||||
struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd);
|
||||
dma_free_coherent(desc->vd.tx.chan->device->dev,
|
||||
desc->control_block_size,
|
||||
desc->control_block_base,
|
||||
desc->control_block_base_phys);
|
||||
kfree(desc);
|
||||
}
|
||||
|
||||
static int bcm2835_dma_abort(void __iomem *chan_base)
|
||||
{
|
||||
unsigned long cs;
|
||||
long int timeout = 10000;
|
||||
|
||||
cs = readl(chan_base + BCM2835_DMA_CS);
|
||||
if (!(cs & BCM2835_DMA_ACTIVE))
|
||||
return 0;
|
||||
|
||||
/* Write 0 to the active bit - Pause the DMA */
|
||||
writel(0, chan_base + BCM2835_DMA_CS);
|
||||
|
||||
/* Wait for any current AXI transfer to complete */
|
||||
while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) {
|
||||
cpu_relax();
|
||||
cs = readl(chan_base + BCM2835_DMA_CS);
|
||||
}
|
||||
|
||||
/* We'll un-pause when we set of our next DMA */
|
||||
if (!timeout)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
if (!(cs & BCM2835_DMA_ACTIVE))
|
||||
return 0;
|
||||
|
||||
/* Terminate the control block chain */
|
||||
writel(0, chan_base + BCM2835_DMA_NEXTCB);
|
||||
|
||||
/* Abort the whole DMA */
|
||||
writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
|
||||
chan_base + BCM2835_DMA_CS);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
|
||||
{
|
||||
struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
|
||||
struct bcm2835_desc *d;
|
||||
|
||||
if (!vd) {
|
||||
c->desc = NULL;
|
||||
return;
|
||||
}
|
||||
|
||||
list_del(&vd->node);
|
||||
|
||||
c->desc = d = to_bcm2835_dma_desc(&vd->tx);
|
||||
|
||||
writel(d->control_block_base_phys, c->chan_base + BCM2835_DMA_ADDR);
|
||||
writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
|
||||
}
|
||||
|
||||
static irqreturn_t bcm2835_dma_callback(int irq, void *data)
|
||||
{
|
||||
struct bcm2835_chan *c = data;
|
||||
struct bcm2835_desc *d;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&c->vc.lock, flags);
|
||||
|
||||
/* Acknowledge interrupt */
|
||||
writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS);
|
||||
|
||||
d = c->desc;
|
||||
|
||||
if (d) {
|
||||
/* TODO Only works for cyclic DMA */
|
||||
vchan_cyclic_callback(&d->vd);
|
||||
}
|
||||
|
||||
/* Keep the DMA engine running */
|
||||
writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
|
||||
|
||||
spin_unlock_irqrestore(&c->vc.lock, flags);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
|
||||
|
||||
dev_dbg(c->vc.chan.device->dev,
|
||||
"Allocating DMA channel %d\n", c->ch);
|
||||
|
||||
return request_irq(c->irq_number,
|
||||
bcm2835_dma_callback, 0, "DMA IRQ", c);
|
||||
}
|
||||
|
||||
static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
|
||||
|
||||
vchan_free_chan_resources(&c->vc);
|
||||
free_irq(c->irq_number, c);
|
||||
|
||||
dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
|
||||
}
|
||||
|
||||
static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
|
||||
{
|
||||
return d->size;
|
||||
}
|
||||
|
||||
static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
|
||||
{
|
||||
unsigned int i;
|
||||
size_t size;
|
||||
|
||||
for (size = i = 0; i < d->frames; i++) {
|
||||
struct bcm2835_dma_cb *control_block =
|
||||
&d->control_block_base[i];
|
||||
size_t this_size = control_block->length;
|
||||
dma_addr_t dma;
|
||||
|
||||
if (d->dir == DMA_DEV_TO_MEM)
|
||||
dma = control_block->dst;
|
||||
else
|
||||
dma = control_block->src;
|
||||
|
||||
if (size)
|
||||
size += this_size;
|
||||
else if (addr >= dma && addr < dma + this_size)
|
||||
size += dma + this_size - addr;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
|
||||
dma_cookie_t cookie, struct dma_tx_state *txstate)
|
||||
{
|
||||
struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
|
||||
struct virt_dma_desc *vd;
|
||||
enum dma_status ret;
|
||||
unsigned long flags;
|
||||
|
||||
ret = dma_cookie_status(chan, cookie, txstate);
|
||||
if (ret == DMA_COMPLETE || !txstate)
|
||||
return ret;
|
||||
|
||||
spin_lock_irqsave(&c->vc.lock, flags);
|
||||
vd = vchan_find_desc(&c->vc, cookie);
|
||||
if (vd) {
|
||||
txstate->residue =
|
||||
bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx));
|
||||
} else if (c->desc && c->desc->vd.tx.cookie == cookie) {
|
||||
struct bcm2835_desc *d = c->desc;
|
||||
dma_addr_t pos;
|
||||
|
||||
if (d->dir == DMA_MEM_TO_DEV)
|
||||
pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);
|
||||
else if (d->dir == DMA_DEV_TO_MEM)
|
||||
pos = readl(c->chan_base + BCM2835_DMA_DEST_AD);
|
||||
else
|
||||
pos = 0;
|
||||
|
||||
txstate->residue = bcm2835_dma_desc_size_pos(d, pos);
|
||||
} else {
|
||||
txstate->residue = 0;
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&c->vc.lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void bcm2835_dma_issue_pending(struct dma_chan *chan)
|
||||
{
|
||||
struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
|
||||
unsigned long flags;
|
||||
|
||||
c->cyclic = true; /* Nothing else is implemented */
|
||||
|
||||
spin_lock_irqsave(&c->vc.lock, flags);
|
||||
if (vchan_issue_pending(&c->vc) && !c->desc)
|
||||
bcm2835_dma_start_desc(c);
|
||||
|
||||
spin_unlock_irqrestore(&c->vc.lock, flags);
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
|
||||
struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
|
||||
size_t period_len, enum dma_transfer_direction direction,
|
||||
unsigned long flags, void *context)
|
||||
{
|
||||
struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
|
||||
enum dma_slave_buswidth dev_width;
|
||||
struct bcm2835_desc *d;
|
||||
dma_addr_t dev_addr;
|
||||
unsigned int es, sync_type;
|
||||
unsigned int frame;
|
||||
|
||||
/* Grab configuration */
|
||||
if (!is_slave_direction(direction)) {
|
||||
dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (direction == DMA_DEV_TO_MEM) {
|
||||
dev_addr = c->cfg.src_addr;
|
||||
dev_width = c->cfg.src_addr_width;
|
||||
sync_type = BCM2835_DMA_S_DREQ;
|
||||
} else {
|
||||
dev_addr = c->cfg.dst_addr;
|
||||
dev_width = c->cfg.dst_addr_width;
|
||||
sync_type = BCM2835_DMA_D_DREQ;
|
||||
}
|
||||
|
||||
/* Bus width translates to the element size (ES) */
|
||||
switch (dev_width) {
|
||||
case DMA_SLAVE_BUSWIDTH_4_BYTES:
|
||||
es = BCM2835_DMA_DATA_TYPE_S32;
|
||||
break;
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Now allocate and setup the descriptor. */
|
||||
d = kzalloc(sizeof(*d), GFP_NOWAIT);
|
||||
if (!d)
|
||||
return NULL;
|
||||
|
||||
d->dir = direction;
|
||||
d->frames = buf_len / period_len;
|
||||
|
||||
/* Allocate memory for control blocks */
|
||||
d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
|
||||
d->control_block_base = dma_zalloc_coherent(chan->device->dev,
|
||||
d->control_block_size, &d->control_block_base_phys,
|
||||
GFP_NOWAIT);
|
||||
|
||||
if (!d->control_block_base) {
|
||||
kfree(d);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Iterate over all frames, create a control block
|
||||
* for each frame and link them together.
|
||||
*/
|
||||
for (frame = 0; frame < d->frames; frame++) {
|
||||
struct bcm2835_dma_cb *control_block =
|
||||
&d->control_block_base[frame];
|
||||
|
||||
/* Setup adresses */
|
||||
if (d->dir == DMA_DEV_TO_MEM) {
|
||||
control_block->info = BCM2835_DMA_D_INC;
|
||||
control_block->src = dev_addr;
|
||||
control_block->dst = buf_addr + frame * period_len;
|
||||
} else {
|
||||
control_block->info = BCM2835_DMA_S_INC;
|
||||
control_block->src = buf_addr + frame * period_len;
|
||||
control_block->dst = dev_addr;
|
||||
}
|
||||
|
||||
/* Enable interrupt */
|
||||
control_block->info |= BCM2835_DMA_INT_EN;
|
||||
|
||||
/* Setup synchronization */
|
||||
if (sync_type != 0)
|
||||
control_block->info |= sync_type;
|
||||
|
||||
/* Setup DREQ channel */
|
||||
if (c->dreq != 0)
|
||||
control_block->info |=
|
||||
BCM2835_DMA_PER_MAP(c->dreq);
|
||||
|
||||
/* Length of a frame */
|
||||
control_block->length = period_len;
|
||||
d->size += control_block->length;
|
||||
|
||||
/*
|
||||
* Next block is the next frame.
|
||||
* This DMA engine driver currently only supports cyclic DMA.
|
||||
* Therefore, wrap around at number of frames.
|
||||
*/
|
||||
control_block->next = d->control_block_base_phys +
|
||||
sizeof(struct bcm2835_dma_cb)
|
||||
* ((frame + 1) % d->frames);
|
||||
}
|
||||
|
||||
return vchan_tx_prep(&c->vc, &d->vd, flags);
|
||||
}
|
||||
|
||||
static int bcm2835_dma_slave_config(struct bcm2835_chan *c,
|
||||
struct dma_slave_config *cfg)
|
||||
{
|
||||
if ((cfg->direction == DMA_DEV_TO_MEM &&
|
||||
cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
|
||||
(cfg->direction == DMA_MEM_TO_DEV &&
|
||||
cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
|
||||
!is_slave_direction(cfg->direction)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
c->cfg = *cfg;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm2835_dma_terminate_all(struct bcm2835_chan *c)
|
||||
{
|
||||
struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device);
|
||||
unsigned long flags;
|
||||
int timeout = 10000;
|
||||
LIST_HEAD(head);
|
||||
|
||||
spin_lock_irqsave(&c->vc.lock, flags);
|
||||
|
||||
/* Prevent this channel being scheduled */
|
||||
spin_lock(&d->lock);
|
||||
list_del_init(&c->node);
|
||||
spin_unlock(&d->lock);
|
||||
|
||||
/*
|
||||
* Stop DMA activity: we assume the callback will not be called
|
||||
* after bcm_dma_abort() returns (even if it does, it will see
|
||||
* c->desc is NULL and exit.)
|
||||
*/
|
||||
if (c->desc) {
|
||||
c->desc = NULL;
|
||||
bcm2835_dma_abort(c->chan_base);
|
||||
|
||||
/* Wait for stopping */
|
||||
while (--timeout) {
|
||||
if (!(readl(c->chan_base + BCM2835_DMA_CS) &
|
||||
BCM2835_DMA_ACTIVE))
|
||||
break;
|
||||
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
if (!timeout)
|
||||
dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");
|
||||
}
|
||||
|
||||
vchan_get_all_descriptors(&c->vc, &head);
|
||||
spin_unlock_irqrestore(&c->vc.lock, flags);
|
||||
vchan_dma_desc_free_list(&c->vc, &head);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm2835_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
|
||||
|
||||
switch (cmd) {
|
||||
case DMA_SLAVE_CONFIG:
|
||||
return bcm2835_dma_slave_config(c,
|
||||
(struct dma_slave_config *)arg);
|
||||
|
||||
case DMA_TERMINATE_ALL:
|
||||
return bcm2835_dma_terminate_all(c);
|
||||
|
||||
default:
|
||||
return -ENXIO;
|
||||
}
|
||||
}
|
||||
|
||||
static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq)
|
||||
{
|
||||
struct bcm2835_chan *c;
|
||||
|
||||
c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
|
||||
if (!c)
|
||||
return -ENOMEM;
|
||||
|
||||
c->vc.desc_free = bcm2835_dma_desc_free;
|
||||
vchan_init(&c->vc, &d->ddev);
|
||||
INIT_LIST_HEAD(&c->node);
|
||||
|
||||
d->ddev.chancnt++;
|
||||
|
||||
c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id);
|
||||
c->ch = chan_id;
|
||||
c->irq_number = irq;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void bcm2835_dma_free(struct bcm2835_dmadev *od)
|
||||
{
|
||||
struct bcm2835_chan *c, *next;
|
||||
|
||||
list_for_each_entry_safe(c, next, &od->ddev.channels,
|
||||
vc.chan.device_node) {
|
||||
list_del(&c->vc.chan.device_node);
|
||||
tasklet_kill(&c->vc.task);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct of_device_id bcm2835_dma_of_match[] = {
|
||||
{ .compatible = "brcm,bcm2835-dma", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
|
||||
|
||||
static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
struct bcm2835_dmadev *d = ofdma->of_dma_data;
|
||||
struct dma_chan *chan;
|
||||
|
||||
chan = dma_get_any_slave_channel(&d->ddev);
|
||||
if (!chan)
|
||||
return NULL;
|
||||
|
||||
/* Set DREQ from param */
|
||||
to_bcm2835_dma_chan(chan)->dreq = spec->args[0];
|
||||
|
||||
return chan;
|
||||
}
|
||||
|
||||
static int bcm2835_dma_device_slave_caps(struct dma_chan *dchan,
|
||||
struct dma_slave_caps *caps)
|
||||
{
|
||||
caps->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
|
||||
caps->dstn_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
|
||||
caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
|
||||
caps->cmd_pause = false;
|
||||
caps->cmd_terminate = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm2835_dma_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct bcm2835_dmadev *od;
|
||||
struct resource *res;
|
||||
void __iomem *base;
|
||||
int rc;
|
||||
int i;
|
||||
int irq;
|
||||
uint32_t chans_available;
|
||||
|
||||
if (!pdev->dev.dma_mask)
|
||||
pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
|
||||
|
||||
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
|
||||
if (!od)
|
||||
return -ENOMEM;
|
||||
|
||||
pdev->dev.dma_parms = &od->dma_parms;
|
||||
dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
od->base = base;
|
||||
|
||||
dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
|
||||
dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
|
||||
dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
|
||||
od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
|
||||
od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
|
||||
od->ddev.device_tx_status = bcm2835_dma_tx_status;
|
||||
od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
|
||||
od->ddev.device_slave_caps = bcm2835_dma_device_slave_caps;
|
||||
od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
|
||||
od->ddev.device_control = bcm2835_dma_control;
|
||||
od->ddev.dev = &pdev->dev;
|
||||
INIT_LIST_HEAD(&od->ddev.channels);
|
||||
spin_lock_init(&od->lock);
|
||||
|
||||
platform_set_drvdata(pdev, od);
|
||||
|
||||
/* Request DMA channel mask from device tree */
|
||||
if (of_property_read_u32(pdev->dev.of_node,
|
||||
"brcm,dma-channel-mask",
|
||||
&chans_available)) {
|
||||
dev_err(&pdev->dev, "Failed to get channel mask\n");
|
||||
rc = -EINVAL;
|
||||
goto err_no_dma;
|
||||
}
|
||||
|
||||
/*
|
||||
* Do not use the FIQ and BULK channels,
|
||||
* because they are used by the GPU.
|
||||
*/
|
||||
chans_available &= ~(BCM2835_DMA_FIQ_MASK | BCM2835_DMA_BULK_MASK);
|
||||
|
||||
for (i = 0; i < pdev->num_resources; i++) {
|
||||
irq = platform_get_irq(pdev, i);
|
||||
if (irq < 0)
|
||||
break;
|
||||
|
||||
if (chans_available & (1 << i)) {
|
||||
rc = bcm2835_dma_chan_init(od, i, irq);
|
||||
if (rc)
|
||||
goto err_no_dma;
|
||||
}
|
||||
}
|
||||
|
||||
dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
|
||||
|
||||
/* Device-tree DMA controller registration */
|
||||
rc = of_dma_controller_register(pdev->dev.of_node,
|
||||
bcm2835_dma_xlate, od);
|
||||
if (rc) {
|
||||
dev_err(&pdev->dev, "Failed to register DMA controller\n");
|
||||
goto err_no_dma;
|
||||
}
|
||||
|
||||
rc = dma_async_device_register(&od->ddev);
|
||||
if (rc) {
|
||||
dev_err(&pdev->dev,
|
||||
"Failed to register slave DMA engine device: %d\n", rc);
|
||||
goto err_no_dma;
|
||||
}
|
||||
|
||||
dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n");
|
||||
|
||||
return 0;
|
||||
|
||||
err_no_dma:
|
||||
bcm2835_dma_free(od);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int bcm2835_dma_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
|
||||
|
||||
dma_async_device_unregister(&od->ddev);
|
||||
bcm2835_dma_free(od);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver bcm2835_dma_driver = {
|
||||
.probe = bcm2835_dma_probe,
|
||||
.remove = bcm2835_dma_remove,
|
||||
.driver = {
|
||||
.name = "bcm2835-dma",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(bcm2835_dma_of_match),
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(bcm2835_dma_driver);
|
||||
|
||||
MODULE_ALIAS("platform:bcm2835-dma");
|
||||
MODULE_DESCRIPTION("BCM2835 DMA engine driver");
|
||||
MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
36
drivers/dma/bestcomm/Kconfig
Normal file
36
drivers/dma/bestcomm/Kconfig
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
#
|
||||
# Kconfig options for Bestcomm
|
||||
#
|
||||
|
||||
config PPC_BESTCOMM
|
||||
tristate "Bestcomm DMA engine support"
|
||||
depends on PPC_MPC52xx
|
||||
default n
|
||||
select PPC_LIB_RHEAP
|
||||
help
|
||||
BestComm is the name of the communication coprocessor found
|
||||
on the Freescale MPC5200 family of processor. Its usage is
|
||||
optional for some drivers (like ATA), but required for
|
||||
others (like FEC).
|
||||
|
||||
If you want to use drivers that require DMA operations,
|
||||
answer Y or M. Otherwise say N.
|
||||
|
||||
config PPC_BESTCOMM_ATA
|
||||
tristate
|
||||
depends on PPC_BESTCOMM
|
||||
help
|
||||
This option enables the support for the ATA task.
|
||||
|
||||
config PPC_BESTCOMM_FEC
|
||||
tristate
|
||||
depends on PPC_BESTCOMM
|
||||
help
|
||||
This option enables the support for the FEC tasks.
|
||||
|
||||
config PPC_BESTCOMM_GEN_BD
|
||||
tristate
|
||||
depends on PPC_BESTCOMM
|
||||
help
|
||||
This option enables the support for the GenBD tasks.
|
||||
|
||||
14
drivers/dma/bestcomm/Makefile
Normal file
14
drivers/dma/bestcomm/Makefile
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
#
|
||||
# Makefile for BestComm & co
|
||||
#
|
||||
|
||||
bestcomm-core-objs := bestcomm.o sram.o
|
||||
bestcomm-ata-objs := ata.o bcom_ata_task.o
|
||||
bestcomm-fec-objs := fec.o bcom_fec_rx_task.o bcom_fec_tx_task.o
|
||||
bestcomm-gen-bd-objs := gen_bd.o bcom_gen_bd_rx_task.o bcom_gen_bd_tx_task.o
|
||||
|
||||
obj-$(CONFIG_PPC_BESTCOMM) += bestcomm-core.o
|
||||
obj-$(CONFIG_PPC_BESTCOMM_ATA) += bestcomm-ata.o
|
||||
obj-$(CONFIG_PPC_BESTCOMM_FEC) += bestcomm-fec.o
|
||||
obj-$(CONFIG_PPC_BESTCOMM_GEN_BD) += bestcomm-gen-bd.o
|
||||
|
||||
157
drivers/dma/bestcomm/ata.c
Normal file
157
drivers/dma/bestcomm/ata.c
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/*
|
||||
* Bestcomm ATA task driver
|
||||
*
|
||||
*
|
||||
* Patterned after bestcomm/fec.c by Dale Farnsworth <dfarnsworth@mvista.com>
|
||||
* 2003-2004 (c) MontaVista, Software, Inc.
|
||||
*
|
||||
* Copyright (C) 2006-2007 Sylvain Munaut <tnt@246tNt.com>
|
||||
* Copyright (C) 2006 Freescale - John Rigby
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <linux/fsl/bestcomm/bestcomm.h>
|
||||
#include <linux/fsl/bestcomm/bestcomm_priv.h>
|
||||
#include <linux/fsl/bestcomm/ata.h>
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* Task image/var/inc */
|
||||
/* ======================================================================== */
|
||||
|
||||
/* ata task image */
|
||||
extern u32 bcom_ata_task[];
|
||||
|
||||
/* ata task vars that need to be set before enabling the task */
|
||||
struct bcom_ata_var {
|
||||
u32 enable; /* (u16*) address of task's control register */
|
||||
u32 bd_base; /* (struct bcom_bd*) beginning of ring buffer */
|
||||
u32 bd_last; /* (struct bcom_bd*) end of ring buffer */
|
||||
u32 bd_start; /* (struct bcom_bd*) current bd */
|
||||
u32 buffer_size; /* size of receive buffer */
|
||||
};
|
||||
|
||||
/* ata task incs that need to be set before enabling the task */
|
||||
struct bcom_ata_inc {
|
||||
u16 pad0;
|
||||
s16 incr_bytes;
|
||||
u16 pad1;
|
||||
s16 incr_dst;
|
||||
u16 pad2;
|
||||
s16 incr_src;
|
||||
};
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* Task support code */
|
||||
/* ======================================================================== */
|
||||
|
||||
struct bcom_task *
|
||||
bcom_ata_init(int queue_len, int maxbufsize)
|
||||
{
|
||||
struct bcom_task *tsk;
|
||||
struct bcom_ata_var *var;
|
||||
struct bcom_ata_inc *inc;
|
||||
|
||||
/* Prefetch breaks ATA DMA. Turn it off for ATA DMA */
|
||||
bcom_disable_prefetch();
|
||||
|
||||
tsk = bcom_task_alloc(queue_len, sizeof(struct bcom_ata_bd), 0);
|
||||
if (!tsk)
|
||||
return NULL;
|
||||
|
||||
tsk->flags = BCOM_FLAGS_NONE;
|
||||
|
||||
bcom_ata_reset_bd(tsk);
|
||||
|
||||
var = (struct bcom_ata_var *) bcom_task_var(tsk->tasknum);
|
||||
inc = (struct bcom_ata_inc *) bcom_task_inc(tsk->tasknum);
|
||||
|
||||
if (bcom_load_image(tsk->tasknum, bcom_ata_task)) {
|
||||
bcom_task_free(tsk);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
var->enable = bcom_eng->regs_base +
|
||||
offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]);
|
||||
var->bd_base = tsk->bd_pa;
|
||||
var->bd_last = tsk->bd_pa + ((tsk->num_bd-1) * tsk->bd_size);
|
||||
var->bd_start = tsk->bd_pa;
|
||||
var->buffer_size = maxbufsize;
|
||||
|
||||
/* Configure some stuff */
|
||||
bcom_set_task_pragma(tsk->tasknum, BCOM_ATA_PRAGMA);
|
||||
bcom_set_task_auto_start(tsk->tasknum, tsk->tasknum);
|
||||
|
||||
out_8(&bcom_eng->regs->ipr[BCOM_INITIATOR_ATA_RX], BCOM_IPR_ATA_RX);
|
||||
out_8(&bcom_eng->regs->ipr[BCOM_INITIATOR_ATA_TX], BCOM_IPR_ATA_TX);
|
||||
|
||||
out_be32(&bcom_eng->regs->IntPend, 1<<tsk->tasknum); /* Clear ints */
|
||||
|
||||
return tsk;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_ata_init);
|
||||
|
||||
void bcom_ata_rx_prepare(struct bcom_task *tsk)
|
||||
{
|
||||
struct bcom_ata_inc *inc;
|
||||
|
||||
inc = (struct bcom_ata_inc *) bcom_task_inc(tsk->tasknum);
|
||||
|
||||
inc->incr_bytes = -(s16)sizeof(u32);
|
||||
inc->incr_src = 0;
|
||||
inc->incr_dst = sizeof(u32);
|
||||
|
||||
bcom_set_initiator(tsk->tasknum, BCOM_INITIATOR_ATA_RX);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_ata_rx_prepare);
|
||||
|
||||
void bcom_ata_tx_prepare(struct bcom_task *tsk)
|
||||
{
|
||||
struct bcom_ata_inc *inc;
|
||||
|
||||
inc = (struct bcom_ata_inc *) bcom_task_inc(tsk->tasknum);
|
||||
|
||||
inc->incr_bytes = -(s16)sizeof(u32);
|
||||
inc->incr_src = sizeof(u32);
|
||||
inc->incr_dst = 0;
|
||||
|
||||
bcom_set_initiator(tsk->tasknum, BCOM_INITIATOR_ATA_TX);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_ata_tx_prepare);
|
||||
|
||||
void bcom_ata_reset_bd(struct bcom_task *tsk)
|
||||
{
|
||||
struct bcom_ata_var *var;
|
||||
|
||||
/* Reset all BD */
|
||||
memset(tsk->bd, 0x00, tsk->num_bd * tsk->bd_size);
|
||||
|
||||
tsk->index = 0;
|
||||
tsk->outdex = 0;
|
||||
|
||||
var = (struct bcom_ata_var *) bcom_task_var(tsk->tasknum);
|
||||
var->bd_start = var->bd_base;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_ata_reset_bd);
|
||||
|
||||
void bcom_ata_release(struct bcom_task *tsk)
|
||||
{
|
||||
/* Nothing special for the ATA tasks */
|
||||
bcom_task_free(tsk);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_ata_release);
|
||||
|
||||
|
||||
MODULE_DESCRIPTION("BestComm ATA task driver");
|
||||
MODULE_AUTHOR("John Rigby");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
67
drivers/dma/bestcomm/bcom_ata_task.c
Normal file
67
drivers/dma/bestcomm/bcom_ata_task.c
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* Bestcomm ATA task microcode
|
||||
*
|
||||
* Copyright (c) 2004 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* Created based on bestcom/code_dma/image_rtos1/dma_image.hex
|
||||
*/
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
/*
|
||||
* The header consists of the following fields:
|
||||
* u32 magic;
|
||||
* u8 desc_size;
|
||||
* u8 var_size;
|
||||
* u8 inc_size;
|
||||
* u8 first_var;
|
||||
* u8 reserved[8];
|
||||
*
|
||||
* The size fields contain the number of 32-bit words.
|
||||
*/
|
||||
|
||||
u32 bcom_ata_task[] = {
|
||||
/* header */
|
||||
0x4243544b,
|
||||
0x0e060709,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
/* Task descriptors */
|
||||
0x8198009b, /* LCD: idx0 = var3; idx0 <= var2; idx0 += inc3 */
|
||||
0x13e00c08, /* DRD1A: var3 = var1; FN=0 MORE init=31 WS=0 RS=0 */
|
||||
0xb8000264, /* LCD: idx1 = *idx0, idx2 = var0; idx1 < var9; idx1 += inc4, idx2 += inc4 */
|
||||
0x10000f00, /* DRD1A: var3 = idx0; FN=0 MORE init=0 WS=0 RS=0 */
|
||||
0x60140002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=2 RS=2 */
|
||||
0x0c8cfc8a, /* DRD2B1: *idx2 = EU3(); EU3(*idx2,var10) */
|
||||
0xd8988240, /* LCDEXT: idx1 = idx1; idx1 > var9; idx1 += inc0 */
|
||||
0xf845e011, /* LCDEXT: idx2 = *(idx0 + var00000015); ; idx2 += inc2 */
|
||||
0xb845e00a, /* LCD: idx3 = *(idx0 + var00000019); ; idx3 += inc1 */
|
||||
0x0bfecf90, /* DRD1A: *idx3 = *idx2; FN=0 TFD init=31 WS=3 RS=3 */
|
||||
0x9898802d, /* LCD: idx1 = idx1; idx1 once var0; idx1 += inc5 */
|
||||
0x64000005, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 INT EXT init=0 WS=0 RS=0 */
|
||||
0x0c0cf849, /* DRD2B1: *idx0 = EU3(); EU3(idx1,var9) */
|
||||
0x000001f8, /* NOP */
|
||||
|
||||
/* VAR[9]-VAR[14] */
|
||||
0x40000000,
|
||||
0x7fff7fff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
/* INC[0]-INC[6] */
|
||||
0x40000000,
|
||||
0xe0000000,
|
||||
0xe0000000,
|
||||
0xa000000c,
|
||||
0x20000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
};
|
||||
|
||||
78
drivers/dma/bestcomm/bcom_fec_rx_task.c
Normal file
78
drivers/dma/bestcomm/bcom_fec_rx_task.c
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Bestcomm FEC RX task microcode
|
||||
*
|
||||
* Copyright (c) 2004 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* Automatically created based on BestCommAPI-2.2/code_dma/image_rtos1/dma_image.hex
|
||||
* on Tue Mar 22 11:19:38 2005 GMT
|
||||
*/
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
/*
|
||||
* The header consists of the following fields:
|
||||
* u32 magic;
|
||||
* u8 desc_size;
|
||||
* u8 var_size;
|
||||
* u8 inc_size;
|
||||
* u8 first_var;
|
||||
* u8 reserved[8];
|
||||
*
|
||||
* The size fields contain the number of 32-bit words.
|
||||
*/
|
||||
|
||||
u32 bcom_fec_rx_task[] = {
|
||||
/* header */
|
||||
0x4243544b,
|
||||
0x18060709,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
/* Task descriptors */
|
||||
0x808220e3, /* LCD: idx0 = var1, idx1 = var4; idx1 <= var3; idx0 += inc4, idx1 += inc3 */
|
||||
0x10601010, /* DRD1A: var4 = var2; FN=0 MORE init=3 WS=0 RS=0 */
|
||||
0xb8800264, /* LCD: idx2 = *idx1, idx3 = var0; idx2 < var9; idx2 += inc4, idx3 += inc4 */
|
||||
0x10001308, /* DRD1A: var4 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
|
||||
0x60140002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=2 RS=2 */
|
||||
0x0cccfcca, /* DRD2B1: *idx3 = EU3(); EU3(*idx3,var10) */
|
||||
0x80004000, /* LCDEXT: idx2 = 0x00000000; ; */
|
||||
0xb8c58029, /* LCD: idx3 = *(idx1 + var00000015); idx3 once var0; idx3 += inc5 */
|
||||
0x60000002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=0 RS=0 */
|
||||
0x088cf8cc, /* DRD2B1: idx2 = EU3(); EU3(idx3,var12) */
|
||||
0x991982f2, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var11; idx2 += inc6, idx3 += inc2 */
|
||||
0x006acf80, /* DRD1A: *idx3 = *idx0; FN=0 init=3 WS=1 RS=1 */
|
||||
0x80004000, /* LCDEXT: idx2 = 0x00000000; ; */
|
||||
0x9999802d, /* LCD: idx3 = idx3; idx3 once var0; idx3 += inc5 */
|
||||
0x70000002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
|
||||
0x034cfc4e, /* DRD2B1: var13 = EU3(); EU3(*idx1,var14) */
|
||||
0x00008868, /* DRD1A: idx2 = var13; FN=0 init=0 WS=0 RS=0 */
|
||||
0x99198341, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var13; idx2 += inc0, idx3 += inc1 */
|
||||
0x007ecf80, /* DRD1A: *idx3 = *idx0; FN=0 init=3 WS=3 RS=3 */
|
||||
0x99198272, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var9; idx2 += inc6, idx3 += inc2 */
|
||||
0x046acf80, /* DRD1A: *idx3 = *idx0; FN=0 INT init=3 WS=1 RS=1 */
|
||||
0x9819002d, /* LCD: idx2 = idx0; idx2 once var0; idx2 += inc5 */
|
||||
0x0060c790, /* DRD1A: *idx1 = *idx2; FN=0 init=3 WS=0 RS=0 */
|
||||
0x000001f8, /* NOP */
|
||||
|
||||
/* VAR[9]-VAR[14] */
|
||||
0x40000000,
|
||||
0x7fff7fff,
|
||||
0x00000000,
|
||||
0x00000003,
|
||||
0x40000008,
|
||||
0x43ffffff,
|
||||
|
||||
/* INC[0]-INC[6] */
|
||||
0x40000000,
|
||||
0xe0000000,
|
||||
0xe0000000,
|
||||
0xa0000008,
|
||||
0x20000000,
|
||||
0x00000000,
|
||||
0x4000ffff,
|
||||
};
|
||||
|
||||
91
drivers/dma/bestcomm/bcom_fec_tx_task.c
Normal file
91
drivers/dma/bestcomm/bcom_fec_tx_task.c
Normal file
|
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* Bestcomm FEC TX task microcode
|
||||
*
|
||||
* Copyright (c) 2004 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* Automatically created based on BestCommAPI-2.2/code_dma/image_rtos1/dma_image.hex
|
||||
* on Tue Mar 22 11:19:29 2005 GMT
|
||||
*/
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
/*
|
||||
* The header consists of the following fields:
|
||||
* u32 magic;
|
||||
* u8 desc_size;
|
||||
* u8 var_size;
|
||||
* u8 inc_size;
|
||||
* u8 first_var;
|
||||
* u8 reserved[8];
|
||||
*
|
||||
* The size fields contain the number of 32-bit words.
|
||||
*/
|
||||
|
||||
u32 bcom_fec_tx_task[] = {
|
||||
/* header */
|
||||
0x4243544b,
|
||||
0x2407070d,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
/* Task descriptors */
|
||||
0x8018001b, /* LCD: idx0 = var0; idx0 <= var0; idx0 += inc3 */
|
||||
0x60000005, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 EXT init=0 WS=0 RS=0 */
|
||||
0x01ccfc0d, /* DRD2B1: var7 = EU3(); EU3(*idx0,var13) */
|
||||
0x8082a123, /* LCD: idx0 = var1, idx1 = var5; idx1 <= var4; idx0 += inc4, idx1 += inc3 */
|
||||
0x10801418, /* DRD1A: var5 = var3; FN=0 MORE init=4 WS=0 RS=0 */
|
||||
0xf88103a4, /* LCDEXT: idx2 = *idx1, idx3 = var2; idx2 < var14; idx2 += inc4, idx3 += inc4 */
|
||||
0x801a6024, /* LCD: idx4 = var0; ; idx4 += inc4 */
|
||||
0x10001708, /* DRD1A: var5 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
|
||||
0x60140002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=2 RS=2 */
|
||||
0x0cccfccf, /* DRD2B1: *idx3 = EU3(); EU3(*idx3,var15) */
|
||||
0x991a002c, /* LCD: idx2 = idx2, idx3 = idx4; idx2 once var0; idx2 += inc5, idx3 += inc4 */
|
||||
0x70000002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
|
||||
0x024cfc4d, /* DRD2B1: var9 = EU3(); EU3(*idx1,var13) */
|
||||
0x60000003, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=3 EXT init=0 WS=0 RS=0 */
|
||||
0x0cccf247, /* DRD2B1: *idx3 = EU3(); EU3(var9,var7) */
|
||||
0x80004000, /* LCDEXT: idx2 = 0x00000000; ; */
|
||||
0xb8c80029, /* LCD: idx3 = *(idx1 + var0000001a); idx3 once var0; idx3 += inc5 */
|
||||
0x70000002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
|
||||
0x088cf8d1, /* DRD2B1: idx2 = EU3(); EU3(idx3,var17) */
|
||||
0x00002f10, /* DRD1A: var11 = idx2; FN=0 init=0 WS=0 RS=0 */
|
||||
0x99198432, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var16; idx2 += inc6, idx3 += inc2 */
|
||||
0x008ac398, /* DRD1A: *idx0 = *idx3; FN=0 init=4 WS=1 RS=1 */
|
||||
0x80004000, /* LCDEXT: idx2 = 0x00000000; ; */
|
||||
0x9999802d, /* LCD: idx3 = idx3; idx3 once var0; idx3 += inc5 */
|
||||
0x70000002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
|
||||
0x048cfc53, /* DRD2B1: var18 = EU3(); EU3(*idx1,var19) */
|
||||
0x60000008, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=8 EXT init=0 WS=0 RS=0 */
|
||||
0x088cf48b, /* DRD2B1: idx2 = EU3(); EU3(var18,var11) */
|
||||
0x99198481, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var18; idx2 += inc0, idx3 += inc1 */
|
||||
0x009ec398, /* DRD1A: *idx0 = *idx3; FN=0 init=4 WS=3 RS=3 */
|
||||
0x991983b2, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var14; idx2 += inc6, idx3 += inc2 */
|
||||
0x088ac398, /* DRD1A: *idx0 = *idx3; FN=0 TFD init=4 WS=1 RS=1 */
|
||||
0x9919002d, /* LCD: idx2 = idx2; idx2 once var0; idx2 += inc5 */
|
||||
0x60000005, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 EXT init=0 WS=0 RS=0 */
|
||||
0x0c4cf88e, /* DRD2B1: *idx1 = EU3(); EU3(idx2,var14) */
|
||||
0x000001f8, /* NOP */
|
||||
|
||||
/* VAR[13]-VAR[19] */
|
||||
0x0c000000,
|
||||
0x40000000,
|
||||
0x7fff7fff,
|
||||
0x00000000,
|
||||
0x00000003,
|
||||
0x40000004,
|
||||
0x43ffffff,
|
||||
|
||||
/* INC[0]-INC[6] */
|
||||
0x40000000,
|
||||
0xe0000000,
|
||||
0xe0000000,
|
||||
0xa0000008,
|
||||
0x20000000,
|
||||
0x00000000,
|
||||
0x4000ffff,
|
||||
};
|
||||
|
||||
63
drivers/dma/bestcomm/bcom_gen_bd_rx_task.c
Normal file
63
drivers/dma/bestcomm/bcom_gen_bd_rx_task.c
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Bestcomm GenBD RX task microcode
|
||||
*
|
||||
* Copyright (C) 2006 AppSpec Computer Technologies Corp.
|
||||
* Jeff Gibbons <jeff.gibbons@appspec.com>
|
||||
* Copyright (c) 2004 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* Based on BestCommAPI-2.2/code_dma/image_rtos1/dma_image.hex
|
||||
* on Tue Mar 4 10:14:12 2006 GMT
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
/*
|
||||
* The header consists of the following fields:
|
||||
* u32 magic;
|
||||
* u8 desc_size;
|
||||
* u8 var_size;
|
||||
* u8 inc_size;
|
||||
* u8 first_var;
|
||||
* u8 reserved[8];
|
||||
*
|
||||
* The size fields contain the number of 32-bit words.
|
||||
*/
|
||||
|
||||
u32 bcom_gen_bd_rx_task[] = {
|
||||
/* header */
|
||||
0x4243544b,
|
||||
0x0d020409,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
/* Task descriptors */
|
||||
0x808220da, /* LCD: idx0 = var1, idx1 = var4; idx1 <= var3; idx0 += inc3, idx1 += inc2 */
|
||||
0x13e01010, /* DRD1A: var4 = var2; FN=0 MORE init=31 WS=0 RS=0 */
|
||||
0xb880025b, /* LCD: idx2 = *idx1, idx3 = var0; idx2 < var9; idx2 += inc3, idx3 += inc3 */
|
||||
0x10001308, /* DRD1A: var4 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
|
||||
0x60140002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=2 RS=2 */
|
||||
0x0cccfcca, /* DRD2B1: *idx3 = EU3(); EU3(*idx3,var10) */
|
||||
0xd9190240, /* LCDEXT: idx2 = idx2; idx2 > var9; idx2 += inc0 */
|
||||
0xb8c5e009, /* LCD: idx3 = *(idx1 + var00000015); ; idx3 += inc1 */
|
||||
0x07fecf80, /* DRD1A: *idx3 = *idx0; FN=0 INT init=31 WS=3 RS=3 */
|
||||
0x99190024, /* LCD: idx2 = idx2; idx2 once var0; idx2 += inc4 */
|
||||
0x60000005, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 EXT init=0 WS=0 RS=0 */
|
||||
0x0c4cf889, /* DRD2B1: *idx1 = EU3(); EU3(idx2,var9) */
|
||||
0x000001f8, /* NOP */
|
||||
|
||||
/* VAR[9]-VAR[10] */
|
||||
0x40000000,
|
||||
0x7fff7fff,
|
||||
|
||||
/* INC[0]-INC[3] */
|
||||
0x40000000,
|
||||
0xe0000000,
|
||||
0xa0000008,
|
||||
0x20000000,
|
||||
};
|
||||
|
||||
69
drivers/dma/bestcomm/bcom_gen_bd_tx_task.c
Normal file
69
drivers/dma/bestcomm/bcom_gen_bd_tx_task.c
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* Bestcomm GenBD TX task microcode
|
||||
*
|
||||
* Copyright (C) 2006 AppSpec Computer Technologies Corp.
|
||||
* Jeff Gibbons <jeff.gibbons@appspec.com>
|
||||
* Copyright (c) 2004 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* Based on BestCommAPI-2.2/code_dma/image_rtos1/dma_image.hex
|
||||
* on Tue Mar 4 10:14:12 2006 GMT
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
/*
|
||||
* The header consists of the following fields:
|
||||
* u32 magic;
|
||||
* u8 desc_size;
|
||||
* u8 var_size;
|
||||
* u8 inc_size;
|
||||
* u8 first_var;
|
||||
* u8 reserved[8];
|
||||
*
|
||||
* The size fields contain the number of 32-bit words.
|
||||
*/
|
||||
|
||||
u32 bcom_gen_bd_tx_task[] = {
|
||||
/* header */
|
||||
0x4243544b,
|
||||
0x0f040609,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
/* Task descriptors */
|
||||
0x800220e3, /* LCD: idx0 = var0, idx1 = var4; idx1 <= var3; idx0 += inc4, idx1 += inc3 */
|
||||
0x13e01010, /* DRD1A: var4 = var2; FN=0 MORE init=31 WS=0 RS=0 */
|
||||
0xb8808264, /* LCD: idx2 = *idx1, idx3 = var1; idx2 < var9; idx2 += inc4, idx3 += inc4 */
|
||||
0x10001308, /* DRD1A: var4 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
|
||||
0x60140002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=2 RS=2 */
|
||||
0x0cccfcca, /* DRD2B1: *idx3 = EU3(); EU3(*idx3,var10) */
|
||||
0xd9190300, /* LCDEXT: idx2 = idx2; idx2 > var12; idx2 += inc0 */
|
||||
0xb8c5e009, /* LCD: idx3 = *(idx1 + var00000015); ; idx3 += inc1 */
|
||||
0x03fec398, /* DRD1A: *idx0 = *idx3; FN=0 init=31 WS=3 RS=3 */
|
||||
0x9919826a, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var9; idx2 += inc5, idx3 += inc2 */
|
||||
0x0feac398, /* DRD1A: *idx0 = *idx3; FN=0 TFD INT init=31 WS=1 RS=1 */
|
||||
0x99190036, /* LCD: idx2 = idx2; idx2 once var0; idx2 += inc6 */
|
||||
0x60000005, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 EXT init=0 WS=0 RS=0 */
|
||||
0x0c4cf889, /* DRD2B1: *idx1 = EU3(); EU3(idx2,var9) */
|
||||
0x000001f8, /* NOP */
|
||||
|
||||
/* VAR[9]-VAR[12] */
|
||||
0x40000000,
|
||||
0x7fff7fff,
|
||||
0x00000000,
|
||||
0x40000004,
|
||||
|
||||
/* INC[0]-INC[5] */
|
||||
0x40000000,
|
||||
0xe0000000,
|
||||
0xe0000000,
|
||||
0xa0000008,
|
||||
0x20000000,
|
||||
0x4000ffff,
|
||||
};
|
||||
|
||||
531
drivers/dma/bestcomm/bestcomm.c
Normal file
531
drivers/dma/bestcomm/bestcomm.c
Normal file
|
|
@ -0,0 +1,531 @@
|
|||
/*
|
||||
* Driver for MPC52xx processor BestComm peripheral controller
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2006-2007 Sylvain Munaut <tnt@246tNt.com>
|
||||
* Copyright (C) 2005 Varma Electronics Oy,
|
||||
* ( by Andrey Volkov <avolkov@varma-el.com> )
|
||||
* Copyright (C) 2003-2004 MontaVista, Software, Inc.
|
||||
* ( by Dale Farnsworth <dfarnsworth@mvista.com> )
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mpc52xx.h>
|
||||
|
||||
#include <linux/fsl/bestcomm/sram.h>
|
||||
#include <linux/fsl/bestcomm/bestcomm_priv.h>
|
||||
#include "linux/fsl/bestcomm/bestcomm.h"
|
||||
|
||||
#define DRIVER_NAME "bestcomm-core"
|
||||
|
||||
/* MPC5200 device tree match tables */
|
||||
static struct of_device_id mpc52xx_sram_ids[] = {
|
||||
{ .compatible = "fsl,mpc5200-sram", },
|
||||
{ .compatible = "mpc5200-sram", },
|
||||
{}
|
||||
};
|
||||
|
||||
|
||||
struct bcom_engine *bcom_eng = NULL;
|
||||
EXPORT_SYMBOL_GPL(bcom_eng); /* needed for inline functions */
|
||||
|
||||
/* ======================================================================== */
|
||||
/* Public and private API */
|
||||
/* ======================================================================== */
|
||||
|
||||
/* Private API */
|
||||
|
||||
struct bcom_task *
|
||||
bcom_task_alloc(int bd_count, int bd_size, int priv_size)
|
||||
{
|
||||
int i, tasknum = -1;
|
||||
struct bcom_task *tsk;
|
||||
|
||||
/* Don't try to do anything if bestcomm init failed */
|
||||
if (!bcom_eng)
|
||||
return NULL;
|
||||
|
||||
/* Get and reserve a task num */
|
||||
spin_lock(&bcom_eng->lock);
|
||||
|
||||
for (i=0; i<BCOM_MAX_TASKS; i++)
|
||||
if (!bcom_eng->tdt[i].stop) { /* we use stop as a marker */
|
||||
bcom_eng->tdt[i].stop = 0xfffffffful; /* dummy addr */
|
||||
tasknum = i;
|
||||
break;
|
||||
}
|
||||
|
||||
spin_unlock(&bcom_eng->lock);
|
||||
|
||||
if (tasknum < 0)
|
||||
return NULL;
|
||||
|
||||
/* Allocate our structure */
|
||||
tsk = kzalloc(sizeof(struct bcom_task) + priv_size, GFP_KERNEL);
|
||||
if (!tsk)
|
||||
goto error;
|
||||
|
||||
tsk->tasknum = tasknum;
|
||||
if (priv_size)
|
||||
tsk->priv = (void*)tsk + sizeof(struct bcom_task);
|
||||
|
||||
/* Get IRQ of that task */
|
||||
tsk->irq = irq_of_parse_and_map(bcom_eng->ofnode, tsk->tasknum);
|
||||
if (tsk->irq == NO_IRQ)
|
||||
goto error;
|
||||
|
||||
/* Init the BDs, if needed */
|
||||
if (bd_count) {
|
||||
tsk->cookie = kmalloc(sizeof(void*) * bd_count, GFP_KERNEL);
|
||||
if (!tsk->cookie)
|
||||
goto error;
|
||||
|
||||
tsk->bd = bcom_sram_alloc(bd_count * bd_size, 4, &tsk->bd_pa);
|
||||
if (!tsk->bd)
|
||||
goto error;
|
||||
memset(tsk->bd, 0x00, bd_count * bd_size);
|
||||
|
||||
tsk->num_bd = bd_count;
|
||||
tsk->bd_size = bd_size;
|
||||
}
|
||||
|
||||
return tsk;
|
||||
|
||||
error:
|
||||
if (tsk) {
|
||||
if (tsk->irq != NO_IRQ)
|
||||
irq_dispose_mapping(tsk->irq);
|
||||
bcom_sram_free(tsk->bd);
|
||||
kfree(tsk->cookie);
|
||||
kfree(tsk);
|
||||
}
|
||||
|
||||
bcom_eng->tdt[tasknum].stop = 0;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_task_alloc);
|
||||
|
||||
void
|
||||
bcom_task_free(struct bcom_task *tsk)
|
||||
{
|
||||
/* Stop the task */
|
||||
bcom_disable_task(tsk->tasknum);
|
||||
|
||||
/* Clear TDT */
|
||||
bcom_eng->tdt[tsk->tasknum].start = 0;
|
||||
bcom_eng->tdt[tsk->tasknum].stop = 0;
|
||||
|
||||
/* Free everything */
|
||||
irq_dispose_mapping(tsk->irq);
|
||||
bcom_sram_free(tsk->bd);
|
||||
kfree(tsk->cookie);
|
||||
kfree(tsk);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_task_free);
|
||||
|
||||
int
|
||||
bcom_load_image(int task, u32 *task_image)
|
||||
{
|
||||
struct bcom_task_header *hdr = (struct bcom_task_header *)task_image;
|
||||
struct bcom_tdt *tdt;
|
||||
u32 *desc, *var, *inc;
|
||||
u32 *desc_src, *var_src, *inc_src;
|
||||
|
||||
/* Safety checks */
|
||||
if (hdr->magic != BCOM_TASK_MAGIC) {
|
||||
printk(KERN_ERR DRIVER_NAME
|
||||
": Trying to load invalid microcode\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ((task < 0) || (task >= BCOM_MAX_TASKS)) {
|
||||
printk(KERN_ERR DRIVER_NAME
|
||||
": Trying to load invalid task %d\n", task);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Initial load or reload */
|
||||
tdt = &bcom_eng->tdt[task];
|
||||
|
||||
if (tdt->start) {
|
||||
desc = bcom_task_desc(task);
|
||||
if (hdr->desc_size != bcom_task_num_descs(task)) {
|
||||
printk(KERN_ERR DRIVER_NAME
|
||||
": Trying to reload wrong task image "
|
||||
"(%d size %d/%d)!\n",
|
||||
task,
|
||||
hdr->desc_size,
|
||||
bcom_task_num_descs(task));
|
||||
return -EINVAL;
|
||||
}
|
||||
} else {
|
||||
phys_addr_t start_pa;
|
||||
|
||||
desc = bcom_sram_alloc(hdr->desc_size * sizeof(u32), 4, &start_pa);
|
||||
if (!desc)
|
||||
return -ENOMEM;
|
||||
|
||||
tdt->start = start_pa;
|
||||
tdt->stop = start_pa + ((hdr->desc_size-1) * sizeof(u32));
|
||||
}
|
||||
|
||||
var = bcom_task_var(task);
|
||||
inc = bcom_task_inc(task);
|
||||
|
||||
/* Clear & copy */
|
||||
memset(var, 0x00, BCOM_VAR_SIZE);
|
||||
memset(inc, 0x00, BCOM_INC_SIZE);
|
||||
|
||||
desc_src = (u32 *)(hdr + 1);
|
||||
var_src = desc_src + hdr->desc_size;
|
||||
inc_src = var_src + hdr->var_size;
|
||||
|
||||
memcpy(desc, desc_src, hdr->desc_size * sizeof(u32));
|
||||
memcpy(var + hdr->first_var, var_src, hdr->var_size * sizeof(u32));
|
||||
memcpy(inc, inc_src, hdr->inc_size * sizeof(u32));
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_load_image);
|
||||
|
||||
void
|
||||
bcom_set_initiator(int task, int initiator)
|
||||
{
|
||||
int i;
|
||||
int num_descs;
|
||||
u32 *desc;
|
||||
int next_drd_has_initiator;
|
||||
|
||||
bcom_set_tcr_initiator(task, initiator);
|
||||
|
||||
/* Just setting tcr is apparently not enough due to some problem */
|
||||
/* with it. So we just go thru all the microcode and replace in */
|
||||
/* the DRD directly */
|
||||
|
||||
desc = bcom_task_desc(task);
|
||||
next_drd_has_initiator = 1;
|
||||
num_descs = bcom_task_num_descs(task);
|
||||
|
||||
for (i=0; i<num_descs; i++, desc++) {
|
||||
if (!bcom_desc_is_drd(*desc))
|
||||
continue;
|
||||
if (next_drd_has_initiator)
|
||||
if (bcom_desc_initiator(*desc) != BCOM_INITIATOR_ALWAYS)
|
||||
bcom_set_desc_initiator(desc, initiator);
|
||||
next_drd_has_initiator = !bcom_drd_is_extended(*desc);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_set_initiator);
|
||||
|
||||
|
||||
/* Public API */
|
||||
|
||||
void
|
||||
bcom_enable(struct bcom_task *tsk)
|
||||
{
|
||||
bcom_enable_task(tsk->tasknum);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_enable);
|
||||
|
||||
void
|
||||
bcom_disable(struct bcom_task *tsk)
|
||||
{
|
||||
bcom_disable_task(tsk->tasknum);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_disable);
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* Engine init/cleanup */
|
||||
/* ======================================================================== */
|
||||
|
||||
/* Function Descriptor table */
|
||||
/* this will need to be updated if Freescale changes their task code FDT */
|
||||
static u32 fdt_ops[] = {
|
||||
0xa0045670, /* FDT[48] - load_acc() */
|
||||
0x80045670, /* FDT[49] - unload_acc() */
|
||||
0x21800000, /* FDT[50] - and() */
|
||||
0x21e00000, /* FDT[51] - or() */
|
||||
0x21500000, /* FDT[52] - xor() */
|
||||
0x21400000, /* FDT[53] - andn() */
|
||||
0x21500000, /* FDT[54] - not() */
|
||||
0x20400000, /* FDT[55] - add() */
|
||||
0x20500000, /* FDT[56] - sub() */
|
||||
0x20800000, /* FDT[57] - lsh() */
|
||||
0x20a00000, /* FDT[58] - rsh() */
|
||||
0xc0170000, /* FDT[59] - crc8() */
|
||||
0xc0145670, /* FDT[60] - crc16() */
|
||||
0xc0345670, /* FDT[61] - crc32() */
|
||||
0xa0076540, /* FDT[62] - endian32() */
|
||||
0xa0000760, /* FDT[63] - endian16() */
|
||||
};
|
||||
|
||||
|
||||
static int bcom_engine_init(void)
|
||||
{
|
||||
int task;
|
||||
phys_addr_t tdt_pa, ctx_pa, var_pa, fdt_pa;
|
||||
unsigned int tdt_size, ctx_size, var_size, fdt_size;
|
||||
|
||||
/* Allocate & clear SRAM zones for FDT, TDTs, contexts and vars/incs */
|
||||
tdt_size = BCOM_MAX_TASKS * sizeof(struct bcom_tdt);
|
||||
ctx_size = BCOM_MAX_TASKS * BCOM_CTX_SIZE;
|
||||
var_size = BCOM_MAX_TASKS * (BCOM_VAR_SIZE + BCOM_INC_SIZE);
|
||||
fdt_size = BCOM_FDT_SIZE;
|
||||
|
||||
bcom_eng->tdt = bcom_sram_alloc(tdt_size, sizeof(u32), &tdt_pa);
|
||||
bcom_eng->ctx = bcom_sram_alloc(ctx_size, BCOM_CTX_ALIGN, &ctx_pa);
|
||||
bcom_eng->var = bcom_sram_alloc(var_size, BCOM_VAR_ALIGN, &var_pa);
|
||||
bcom_eng->fdt = bcom_sram_alloc(fdt_size, BCOM_FDT_ALIGN, &fdt_pa);
|
||||
|
||||
if (!bcom_eng->tdt || !bcom_eng->ctx || !bcom_eng->var || !bcom_eng->fdt) {
|
||||
printk(KERN_ERR "DMA: SRAM alloc failed in engine init !\n");
|
||||
|
||||
bcom_sram_free(bcom_eng->tdt);
|
||||
bcom_sram_free(bcom_eng->ctx);
|
||||
bcom_sram_free(bcom_eng->var);
|
||||
bcom_sram_free(bcom_eng->fdt);
|
||||
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
memset(bcom_eng->tdt, 0x00, tdt_size);
|
||||
memset(bcom_eng->ctx, 0x00, ctx_size);
|
||||
memset(bcom_eng->var, 0x00, var_size);
|
||||
memset(bcom_eng->fdt, 0x00, fdt_size);
|
||||
|
||||
/* Copy the FDT for the EU#3 */
|
||||
memcpy(&bcom_eng->fdt[48], fdt_ops, sizeof(fdt_ops));
|
||||
|
||||
/* Initialize Task base structure */
|
||||
for (task=0; task<BCOM_MAX_TASKS; task++)
|
||||
{
|
||||
out_be16(&bcom_eng->regs->tcr[task], 0);
|
||||
out_8(&bcom_eng->regs->ipr[task], 0);
|
||||
|
||||
bcom_eng->tdt[task].context = ctx_pa;
|
||||
bcom_eng->tdt[task].var = var_pa;
|
||||
bcom_eng->tdt[task].fdt = fdt_pa;
|
||||
|
||||
var_pa += BCOM_VAR_SIZE + BCOM_INC_SIZE;
|
||||
ctx_pa += BCOM_CTX_SIZE;
|
||||
}
|
||||
|
||||
out_be32(&bcom_eng->regs->taskBar, tdt_pa);
|
||||
|
||||
/* Init 'always' initiator */
|
||||
out_8(&bcom_eng->regs->ipr[BCOM_INITIATOR_ALWAYS], BCOM_IPR_ALWAYS);
|
||||
|
||||
/* Disable COMM Bus Prefetch on the original 5200; it's broken */
|
||||
if ((mfspr(SPRN_SVR) & MPC5200_SVR_MASK) == MPC5200_SVR)
|
||||
bcom_disable_prefetch();
|
||||
|
||||
/* Init lock */
|
||||
spin_lock_init(&bcom_eng->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
bcom_engine_cleanup(void)
|
||||
{
|
||||
int task;
|
||||
|
||||
/* Stop all tasks */
|
||||
for (task=0; task<BCOM_MAX_TASKS; task++)
|
||||
{
|
||||
out_be16(&bcom_eng->regs->tcr[task], 0);
|
||||
out_8(&bcom_eng->regs->ipr[task], 0);
|
||||
}
|
||||
|
||||
out_be32(&bcom_eng->regs->taskBar, 0ul);
|
||||
|
||||
/* Release the SRAM zones */
|
||||
bcom_sram_free(bcom_eng->tdt);
|
||||
bcom_sram_free(bcom_eng->ctx);
|
||||
bcom_sram_free(bcom_eng->var);
|
||||
bcom_sram_free(bcom_eng->fdt);
|
||||
}
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* OF platform driver */
|
||||
/* ======================================================================== */
|
||||
|
||||
static int mpc52xx_bcom_probe(struct platform_device *op)
|
||||
{
|
||||
struct device_node *ofn_sram;
|
||||
struct resource res_bcom;
|
||||
|
||||
int rv;
|
||||
|
||||
/* Inform user we're ok so far */
|
||||
printk(KERN_INFO "DMA: MPC52xx BestComm driver\n");
|
||||
|
||||
/* Get the bestcomm node */
|
||||
of_node_get(op->dev.of_node);
|
||||
|
||||
/* Prepare SRAM */
|
||||
ofn_sram = of_find_matching_node(NULL, mpc52xx_sram_ids);
|
||||
if (!ofn_sram) {
|
||||
printk(KERN_ERR DRIVER_NAME ": "
|
||||
"No SRAM found in device tree\n");
|
||||
rv = -ENODEV;
|
||||
goto error_ofput;
|
||||
}
|
||||
rv = bcom_sram_init(ofn_sram, DRIVER_NAME);
|
||||
of_node_put(ofn_sram);
|
||||
|
||||
if (rv) {
|
||||
printk(KERN_ERR DRIVER_NAME ": "
|
||||
"Error in SRAM init\n");
|
||||
goto error_ofput;
|
||||
}
|
||||
|
||||
/* Get a clean struct */
|
||||
bcom_eng = kzalloc(sizeof(struct bcom_engine), GFP_KERNEL);
|
||||
if (!bcom_eng) {
|
||||
printk(KERN_ERR DRIVER_NAME ": "
|
||||
"Can't allocate state structure\n");
|
||||
rv = -ENOMEM;
|
||||
goto error_sramclean;
|
||||
}
|
||||
|
||||
/* Save the node */
|
||||
bcom_eng->ofnode = op->dev.of_node;
|
||||
|
||||
/* Get, reserve & map io */
|
||||
if (of_address_to_resource(op->dev.of_node, 0, &res_bcom)) {
|
||||
printk(KERN_ERR DRIVER_NAME ": "
|
||||
"Can't get resource\n");
|
||||
rv = -EINVAL;
|
||||
goto error_sramclean;
|
||||
}
|
||||
|
||||
if (!request_mem_region(res_bcom.start, resource_size(&res_bcom),
|
||||
DRIVER_NAME)) {
|
||||
printk(KERN_ERR DRIVER_NAME ": "
|
||||
"Can't request registers region\n");
|
||||
rv = -EBUSY;
|
||||
goto error_sramclean;
|
||||
}
|
||||
|
||||
bcom_eng->regs_base = res_bcom.start;
|
||||
bcom_eng->regs = ioremap(res_bcom.start, sizeof(struct mpc52xx_sdma));
|
||||
if (!bcom_eng->regs) {
|
||||
printk(KERN_ERR DRIVER_NAME ": "
|
||||
"Can't map registers\n");
|
||||
rv = -ENOMEM;
|
||||
goto error_release;
|
||||
}
|
||||
|
||||
/* Now, do the real init */
|
||||
rv = bcom_engine_init();
|
||||
if (rv)
|
||||
goto error_unmap;
|
||||
|
||||
/* Done ! */
|
||||
printk(KERN_INFO "DMA: MPC52xx BestComm engine @%08lx ok !\n",
|
||||
(long)bcom_eng->regs_base);
|
||||
|
||||
return 0;
|
||||
|
||||
/* Error path */
|
||||
error_unmap:
|
||||
iounmap(bcom_eng->regs);
|
||||
error_release:
|
||||
release_mem_region(res_bcom.start, sizeof(struct mpc52xx_sdma));
|
||||
error_sramclean:
|
||||
kfree(bcom_eng);
|
||||
bcom_sram_cleanup();
|
||||
error_ofput:
|
||||
of_node_put(op->dev.of_node);
|
||||
|
||||
printk(KERN_ERR "DMA: MPC52xx BestComm init failed !\n");
|
||||
|
||||
return rv;
|
||||
}
|
||||
|
||||
|
||||
static int mpc52xx_bcom_remove(struct platform_device *op)
|
||||
{
|
||||
/* Clean up the engine */
|
||||
bcom_engine_cleanup();
|
||||
|
||||
/* Cleanup SRAM */
|
||||
bcom_sram_cleanup();
|
||||
|
||||
/* Release regs */
|
||||
iounmap(bcom_eng->regs);
|
||||
release_mem_region(bcom_eng->regs_base, sizeof(struct mpc52xx_sdma));
|
||||
|
||||
/* Release the node */
|
||||
of_node_put(bcom_eng->ofnode);
|
||||
|
||||
/* Release memory */
|
||||
kfree(bcom_eng);
|
||||
bcom_eng = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct of_device_id mpc52xx_bcom_of_match[] = {
|
||||
{ .compatible = "fsl,mpc5200-bestcomm", },
|
||||
{ .compatible = "mpc5200-bestcomm", },
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, mpc52xx_bcom_of_match);
|
||||
|
||||
|
||||
static struct platform_driver mpc52xx_bcom_of_platform_driver = {
|
||||
.probe = mpc52xx_bcom_probe,
|
||||
.remove = mpc52xx_bcom_remove,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = mpc52xx_bcom_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* Module */
|
||||
/* ======================================================================== */
|
||||
|
||||
static int __init
|
||||
mpc52xx_bcom_init(void)
|
||||
{
|
||||
return platform_driver_register(&mpc52xx_bcom_of_platform_driver);
|
||||
}
|
||||
|
||||
static void __exit
|
||||
mpc52xx_bcom_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&mpc52xx_bcom_of_platform_driver);
|
||||
}
|
||||
|
||||
/* If we're not a module, we must make sure everything is setup before */
|
||||
/* anyone tries to use us ... that's why we use subsys_initcall instead */
|
||||
/* of module_init. */
|
||||
subsys_initcall(mpc52xx_bcom_init);
|
||||
module_exit(mpc52xx_bcom_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Freescale MPC52xx BestComm DMA");
|
||||
MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
|
||||
MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
|
||||
MODULE_AUTHOR("Dale Farnsworth <dfarnsworth@mvista.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
270
drivers/dma/bestcomm/fec.c
Normal file
270
drivers/dma/bestcomm/fec.c
Normal file
|
|
@ -0,0 +1,270 @@
|
|||
/*
|
||||
* Bestcomm FEC tasks driver
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2006-2007 Sylvain Munaut <tnt@246tNt.com>
|
||||
* Copyright (C) 2003-2004 MontaVista, Software, Inc.
|
||||
* ( by Dale Farnsworth <dfarnsworth@mvista.com> )
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <linux/fsl/bestcomm/bestcomm.h>
|
||||
#include <linux/fsl/bestcomm/bestcomm_priv.h>
|
||||
#include <linux/fsl/bestcomm/fec.h>
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* Task image/var/inc */
|
||||
/* ======================================================================== */
|
||||
|
||||
/* fec tasks images */
|
||||
extern u32 bcom_fec_rx_task[];
|
||||
extern u32 bcom_fec_tx_task[];
|
||||
|
||||
/* rx task vars that need to be set before enabling the task */
|
||||
struct bcom_fec_rx_var {
|
||||
u32 enable; /* (u16*) address of task's control register */
|
||||
u32 fifo; /* (u32*) address of fec's fifo */
|
||||
u32 bd_base; /* (struct bcom_bd*) beginning of ring buffer */
|
||||
u32 bd_last; /* (struct bcom_bd*) end of ring buffer */
|
||||
u32 bd_start; /* (struct bcom_bd*) current bd */
|
||||
u32 buffer_size; /* size of receive buffer */
|
||||
};
|
||||
|
||||
/* rx task incs that need to be set before enabling the task */
|
||||
struct bcom_fec_rx_inc {
|
||||
u16 pad0;
|
||||
s16 incr_bytes;
|
||||
u16 pad1;
|
||||
s16 incr_dst;
|
||||
u16 pad2;
|
||||
s16 incr_dst_ma;
|
||||
};
|
||||
|
||||
/* tx task vars that need to be set before enabling the task */
|
||||
struct bcom_fec_tx_var {
|
||||
u32 DRD; /* (u32*) address of self-modified DRD */
|
||||
u32 fifo; /* (u32*) address of fec's fifo */
|
||||
u32 enable; /* (u16*) address of task's control register */
|
||||
u32 bd_base; /* (struct bcom_bd*) beginning of ring buffer */
|
||||
u32 bd_last; /* (struct bcom_bd*) end of ring buffer */
|
||||
u32 bd_start; /* (struct bcom_bd*) current bd */
|
||||
u32 buffer_size; /* set by uCode for each packet */
|
||||
};
|
||||
|
||||
/* tx task incs that need to be set before enabling the task */
|
||||
struct bcom_fec_tx_inc {
|
||||
u16 pad0;
|
||||
s16 incr_bytes;
|
||||
u16 pad1;
|
||||
s16 incr_src;
|
||||
u16 pad2;
|
||||
s16 incr_src_ma;
|
||||
};
|
||||
|
||||
/* private structure in the task */
|
||||
struct bcom_fec_priv {
|
||||
phys_addr_t fifo;
|
||||
int maxbufsize;
|
||||
};
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* Task support code */
|
||||
/* ======================================================================== */
|
||||
|
||||
struct bcom_task *
|
||||
bcom_fec_rx_init(int queue_len, phys_addr_t fifo, int maxbufsize)
|
||||
{
|
||||
struct bcom_task *tsk;
|
||||
struct bcom_fec_priv *priv;
|
||||
|
||||
tsk = bcom_task_alloc(queue_len, sizeof(struct bcom_fec_bd),
|
||||
sizeof(struct bcom_fec_priv));
|
||||
if (!tsk)
|
||||
return NULL;
|
||||
|
||||
tsk->flags = BCOM_FLAGS_NONE;
|
||||
|
||||
priv = tsk->priv;
|
||||
priv->fifo = fifo;
|
||||
priv->maxbufsize = maxbufsize;
|
||||
|
||||
if (bcom_fec_rx_reset(tsk)) {
|
||||
bcom_task_free(tsk);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return tsk;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_fec_rx_init);
|
||||
|
||||
int
|
||||
bcom_fec_rx_reset(struct bcom_task *tsk)
|
||||
{
|
||||
struct bcom_fec_priv *priv = tsk->priv;
|
||||
struct bcom_fec_rx_var *var;
|
||||
struct bcom_fec_rx_inc *inc;
|
||||
|
||||
/* Shutdown the task */
|
||||
bcom_disable_task(tsk->tasknum);
|
||||
|
||||
/* Reset the microcode */
|
||||
var = (struct bcom_fec_rx_var *) bcom_task_var(tsk->tasknum);
|
||||
inc = (struct bcom_fec_rx_inc *) bcom_task_inc(tsk->tasknum);
|
||||
|
||||
if (bcom_load_image(tsk->tasknum, bcom_fec_rx_task))
|
||||
return -1;
|
||||
|
||||
var->enable = bcom_eng->regs_base +
|
||||
offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]);
|
||||
var->fifo = (u32) priv->fifo;
|
||||
var->bd_base = tsk->bd_pa;
|
||||
var->bd_last = tsk->bd_pa + ((tsk->num_bd-1) * tsk->bd_size);
|
||||
var->bd_start = tsk->bd_pa;
|
||||
var->buffer_size = priv->maxbufsize;
|
||||
|
||||
inc->incr_bytes = -(s16)sizeof(u32); /* These should be in the */
|
||||
inc->incr_dst = sizeof(u32); /* task image, but we stick */
|
||||
inc->incr_dst_ma= sizeof(u8); /* to the official ones */
|
||||
|
||||
/* Reset the BDs */
|
||||
tsk->index = 0;
|
||||
tsk->outdex = 0;
|
||||
|
||||
memset(tsk->bd, 0x00, tsk->num_bd * tsk->bd_size);
|
||||
|
||||
/* Configure some stuff */
|
||||
bcom_set_task_pragma(tsk->tasknum, BCOM_FEC_RX_BD_PRAGMA);
|
||||
bcom_set_task_auto_start(tsk->tasknum, tsk->tasknum);
|
||||
|
||||
out_8(&bcom_eng->regs->ipr[BCOM_INITIATOR_FEC_RX], BCOM_IPR_FEC_RX);
|
||||
|
||||
out_be32(&bcom_eng->regs->IntPend, 1<<tsk->tasknum); /* Clear ints */
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_fec_rx_reset);
|
||||
|
||||
void
|
||||
bcom_fec_rx_release(struct bcom_task *tsk)
|
||||
{
|
||||
/* Nothing special for the FEC tasks */
|
||||
bcom_task_free(tsk);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_fec_rx_release);
|
||||
|
||||
|
||||
|
||||
/* Return 2nd to last DRD */
|
||||
/* This is an ugly hack, but at least it's only done
|
||||
once at initialization */
|
||||
static u32 *self_modified_drd(int tasknum)
|
||||
{
|
||||
u32 *desc;
|
||||
int num_descs;
|
||||
int drd_count;
|
||||
int i;
|
||||
|
||||
num_descs = bcom_task_num_descs(tasknum);
|
||||
desc = bcom_task_desc(tasknum) + num_descs - 1;
|
||||
drd_count = 0;
|
||||
for (i=0; i<num_descs; i++, desc--)
|
||||
if (bcom_desc_is_drd(*desc) && ++drd_count == 3)
|
||||
break;
|
||||
return desc;
|
||||
}
|
||||
|
||||
struct bcom_task *
|
||||
bcom_fec_tx_init(int queue_len, phys_addr_t fifo)
|
||||
{
|
||||
struct bcom_task *tsk;
|
||||
struct bcom_fec_priv *priv;
|
||||
|
||||
tsk = bcom_task_alloc(queue_len, sizeof(struct bcom_fec_bd),
|
||||
sizeof(struct bcom_fec_priv));
|
||||
if (!tsk)
|
||||
return NULL;
|
||||
|
||||
tsk->flags = BCOM_FLAGS_ENABLE_TASK;
|
||||
|
||||
priv = tsk->priv;
|
||||
priv->fifo = fifo;
|
||||
|
||||
if (bcom_fec_tx_reset(tsk)) {
|
||||
bcom_task_free(tsk);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return tsk;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_fec_tx_init);
|
||||
|
||||
int
|
||||
bcom_fec_tx_reset(struct bcom_task *tsk)
|
||||
{
|
||||
struct bcom_fec_priv *priv = tsk->priv;
|
||||
struct bcom_fec_tx_var *var;
|
||||
struct bcom_fec_tx_inc *inc;
|
||||
|
||||
/* Shutdown the task */
|
||||
bcom_disable_task(tsk->tasknum);
|
||||
|
||||
/* Reset the microcode */
|
||||
var = (struct bcom_fec_tx_var *) bcom_task_var(tsk->tasknum);
|
||||
inc = (struct bcom_fec_tx_inc *) bcom_task_inc(tsk->tasknum);
|
||||
|
||||
if (bcom_load_image(tsk->tasknum, bcom_fec_tx_task))
|
||||
return -1;
|
||||
|
||||
var->enable = bcom_eng->regs_base +
|
||||
offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]);
|
||||
var->fifo = (u32) priv->fifo;
|
||||
var->DRD = bcom_sram_va2pa(self_modified_drd(tsk->tasknum));
|
||||
var->bd_base = tsk->bd_pa;
|
||||
var->bd_last = tsk->bd_pa + ((tsk->num_bd-1) * tsk->bd_size);
|
||||
var->bd_start = tsk->bd_pa;
|
||||
|
||||
inc->incr_bytes = -(s16)sizeof(u32); /* These should be in the */
|
||||
inc->incr_src = sizeof(u32); /* task image, but we stick */
|
||||
inc->incr_src_ma= sizeof(u8); /* to the official ones */
|
||||
|
||||
/* Reset the BDs */
|
||||
tsk->index = 0;
|
||||
tsk->outdex = 0;
|
||||
|
||||
memset(tsk->bd, 0x00, tsk->num_bd * tsk->bd_size);
|
||||
|
||||
/* Configure some stuff */
|
||||
bcom_set_task_pragma(tsk->tasknum, BCOM_FEC_TX_BD_PRAGMA);
|
||||
bcom_set_task_auto_start(tsk->tasknum, tsk->tasknum);
|
||||
|
||||
out_8(&bcom_eng->regs->ipr[BCOM_INITIATOR_FEC_TX], BCOM_IPR_FEC_TX);
|
||||
|
||||
out_be32(&bcom_eng->regs->IntPend, 1<<tsk->tasknum); /* Clear ints */
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_fec_tx_reset);
|
||||
|
||||
void
|
||||
bcom_fec_tx_release(struct bcom_task *tsk)
|
||||
{
|
||||
/* Nothing special for the FEC tasks */
|
||||
bcom_task_free(tsk);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_fec_tx_release);
|
||||
|
||||
|
||||
MODULE_DESCRIPTION("BestComm FEC tasks driver");
|
||||
MODULE_AUTHOR("Dale Farnsworth <dfarnsworth@mvista.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
354
drivers/dma/bestcomm/gen_bd.c
Normal file
354
drivers/dma/bestcomm/gen_bd.c
Normal file
|
|
@ -0,0 +1,354 @@
|
|||
/*
|
||||
* Driver for MPC52xx processor BestComm General Buffer Descriptor
|
||||
*
|
||||
* Copyright (C) 2007 Sylvain Munaut <tnt@246tNt.com>
|
||||
* Copyright (C) 2006 AppSpec Computer Technologies Corp.
|
||||
* Jeff Gibbons <jeff.gibbons@appspec.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <asm/mpc52xx.h>
|
||||
#include <asm/mpc52xx_psc.h>
|
||||
|
||||
#include <linux/fsl/bestcomm/bestcomm.h>
|
||||
#include <linux/fsl/bestcomm/bestcomm_priv.h>
|
||||
#include <linux/fsl/bestcomm/gen_bd.h>
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* Task image/var/inc */
|
||||
/* ======================================================================== */
|
||||
|
||||
/* gen_bd tasks images */
|
||||
extern u32 bcom_gen_bd_rx_task[];
|
||||
extern u32 bcom_gen_bd_tx_task[];
|
||||
|
||||
/* rx task vars that need to be set before enabling the task */
|
||||
struct bcom_gen_bd_rx_var {
|
||||
u32 enable; /* (u16*) address of task's control register */
|
||||
u32 fifo; /* (u32*) address of gen_bd's fifo */
|
||||
u32 bd_base; /* (struct bcom_bd*) beginning of ring buffer */
|
||||
u32 bd_last; /* (struct bcom_bd*) end of ring buffer */
|
||||
u32 bd_start; /* (struct bcom_bd*) current bd */
|
||||
u32 buffer_size; /* size of receive buffer */
|
||||
};
|
||||
|
||||
/* rx task incs that need to be set before enabling the task */
|
||||
struct bcom_gen_bd_rx_inc {
|
||||
u16 pad0;
|
||||
s16 incr_bytes;
|
||||
u16 pad1;
|
||||
s16 incr_dst;
|
||||
};
|
||||
|
||||
/* tx task vars that need to be set before enabling the task */
|
||||
struct bcom_gen_bd_tx_var {
|
||||
u32 fifo; /* (u32*) address of gen_bd's fifo */
|
||||
u32 enable; /* (u16*) address of task's control register */
|
||||
u32 bd_base; /* (struct bcom_bd*) beginning of ring buffer */
|
||||
u32 bd_last; /* (struct bcom_bd*) end of ring buffer */
|
||||
u32 bd_start; /* (struct bcom_bd*) current bd */
|
||||
u32 buffer_size; /* set by uCode for each packet */
|
||||
};
|
||||
|
||||
/* tx task incs that need to be set before enabling the task */
|
||||
struct bcom_gen_bd_tx_inc {
|
||||
u16 pad0;
|
||||
s16 incr_bytes;
|
||||
u16 pad1;
|
||||
s16 incr_src;
|
||||
u16 pad2;
|
||||
s16 incr_src_ma;
|
||||
};
|
||||
|
||||
/* private structure */
|
||||
struct bcom_gen_bd_priv {
|
||||
phys_addr_t fifo;
|
||||
int initiator;
|
||||
int ipr;
|
||||
int maxbufsize;
|
||||
};
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* Task support code */
|
||||
/* ======================================================================== */
|
||||
|
||||
struct bcom_task *
|
||||
bcom_gen_bd_rx_init(int queue_len, phys_addr_t fifo,
|
||||
int initiator, int ipr, int maxbufsize)
|
||||
{
|
||||
struct bcom_task *tsk;
|
||||
struct bcom_gen_bd_priv *priv;
|
||||
|
||||
tsk = bcom_task_alloc(queue_len, sizeof(struct bcom_gen_bd),
|
||||
sizeof(struct bcom_gen_bd_priv));
|
||||
if (!tsk)
|
||||
return NULL;
|
||||
|
||||
tsk->flags = BCOM_FLAGS_NONE;
|
||||
|
||||
priv = tsk->priv;
|
||||
priv->fifo = fifo;
|
||||
priv->initiator = initiator;
|
||||
priv->ipr = ipr;
|
||||
priv->maxbufsize = maxbufsize;
|
||||
|
||||
if (bcom_gen_bd_rx_reset(tsk)) {
|
||||
bcom_task_free(tsk);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return tsk;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_gen_bd_rx_init);
|
||||
|
||||
int
|
||||
bcom_gen_bd_rx_reset(struct bcom_task *tsk)
|
||||
{
|
||||
struct bcom_gen_bd_priv *priv = tsk->priv;
|
||||
struct bcom_gen_bd_rx_var *var;
|
||||
struct bcom_gen_bd_rx_inc *inc;
|
||||
|
||||
/* Shutdown the task */
|
||||
bcom_disable_task(tsk->tasknum);
|
||||
|
||||
/* Reset the microcode */
|
||||
var = (struct bcom_gen_bd_rx_var *) bcom_task_var(tsk->tasknum);
|
||||
inc = (struct bcom_gen_bd_rx_inc *) bcom_task_inc(tsk->tasknum);
|
||||
|
||||
if (bcom_load_image(tsk->tasknum, bcom_gen_bd_rx_task))
|
||||
return -1;
|
||||
|
||||
var->enable = bcom_eng->regs_base +
|
||||
offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]);
|
||||
var->fifo = (u32) priv->fifo;
|
||||
var->bd_base = tsk->bd_pa;
|
||||
var->bd_last = tsk->bd_pa + ((tsk->num_bd-1) * tsk->bd_size);
|
||||
var->bd_start = tsk->bd_pa;
|
||||
var->buffer_size = priv->maxbufsize;
|
||||
|
||||
inc->incr_bytes = -(s16)sizeof(u32);
|
||||
inc->incr_dst = sizeof(u32);
|
||||
|
||||
/* Reset the BDs */
|
||||
tsk->index = 0;
|
||||
tsk->outdex = 0;
|
||||
|
||||
memset(tsk->bd, 0x00, tsk->num_bd * tsk->bd_size);
|
||||
|
||||
/* Configure some stuff */
|
||||
bcom_set_task_pragma(tsk->tasknum, BCOM_GEN_RX_BD_PRAGMA);
|
||||
bcom_set_task_auto_start(tsk->tasknum, tsk->tasknum);
|
||||
|
||||
out_8(&bcom_eng->regs->ipr[priv->initiator], priv->ipr);
|
||||
bcom_set_initiator(tsk->tasknum, priv->initiator);
|
||||
|
||||
out_be32(&bcom_eng->regs->IntPend, 1<<tsk->tasknum); /* Clear ints */
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_gen_bd_rx_reset);
|
||||
|
||||
void
|
||||
bcom_gen_bd_rx_release(struct bcom_task *tsk)
|
||||
{
|
||||
/* Nothing special for the GenBD tasks */
|
||||
bcom_task_free(tsk);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_gen_bd_rx_release);
|
||||
|
||||
|
||||
extern struct bcom_task *
|
||||
bcom_gen_bd_tx_init(int queue_len, phys_addr_t fifo,
|
||||
int initiator, int ipr)
|
||||
{
|
||||
struct bcom_task *tsk;
|
||||
struct bcom_gen_bd_priv *priv;
|
||||
|
||||
tsk = bcom_task_alloc(queue_len, sizeof(struct bcom_gen_bd),
|
||||
sizeof(struct bcom_gen_bd_priv));
|
||||
if (!tsk)
|
||||
return NULL;
|
||||
|
||||
tsk->flags = BCOM_FLAGS_NONE;
|
||||
|
||||
priv = tsk->priv;
|
||||
priv->fifo = fifo;
|
||||
priv->initiator = initiator;
|
||||
priv->ipr = ipr;
|
||||
|
||||
if (bcom_gen_bd_tx_reset(tsk)) {
|
||||
bcom_task_free(tsk);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return tsk;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_gen_bd_tx_init);
|
||||
|
||||
int
|
||||
bcom_gen_bd_tx_reset(struct bcom_task *tsk)
|
||||
{
|
||||
struct bcom_gen_bd_priv *priv = tsk->priv;
|
||||
struct bcom_gen_bd_tx_var *var;
|
||||
struct bcom_gen_bd_tx_inc *inc;
|
||||
|
||||
/* Shutdown the task */
|
||||
bcom_disable_task(tsk->tasknum);
|
||||
|
||||
/* Reset the microcode */
|
||||
var = (struct bcom_gen_bd_tx_var *) bcom_task_var(tsk->tasknum);
|
||||
inc = (struct bcom_gen_bd_tx_inc *) bcom_task_inc(tsk->tasknum);
|
||||
|
||||
if (bcom_load_image(tsk->tasknum, bcom_gen_bd_tx_task))
|
||||
return -1;
|
||||
|
||||
var->enable = bcom_eng->regs_base +
|
||||
offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]);
|
||||
var->fifo = (u32) priv->fifo;
|
||||
var->bd_base = tsk->bd_pa;
|
||||
var->bd_last = tsk->bd_pa + ((tsk->num_bd-1) * tsk->bd_size);
|
||||
var->bd_start = tsk->bd_pa;
|
||||
|
||||
inc->incr_bytes = -(s16)sizeof(u32);
|
||||
inc->incr_src = sizeof(u32);
|
||||
inc->incr_src_ma = sizeof(u8);
|
||||
|
||||
/* Reset the BDs */
|
||||
tsk->index = 0;
|
||||
tsk->outdex = 0;
|
||||
|
||||
memset(tsk->bd, 0x00, tsk->num_bd * tsk->bd_size);
|
||||
|
||||
/* Configure some stuff */
|
||||
bcom_set_task_pragma(tsk->tasknum, BCOM_GEN_TX_BD_PRAGMA);
|
||||
bcom_set_task_auto_start(tsk->tasknum, tsk->tasknum);
|
||||
|
||||
out_8(&bcom_eng->regs->ipr[priv->initiator], priv->ipr);
|
||||
bcom_set_initiator(tsk->tasknum, priv->initiator);
|
||||
|
||||
out_be32(&bcom_eng->regs->IntPend, 1<<tsk->tasknum); /* Clear ints */
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_gen_bd_tx_reset);
|
||||
|
||||
void
|
||||
bcom_gen_bd_tx_release(struct bcom_task *tsk)
|
||||
{
|
||||
/* Nothing special for the GenBD tasks */
|
||||
bcom_task_free(tsk);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_gen_bd_tx_release);
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* PSC support code
|
||||
*/
|
||||
|
||||
/**
|
||||
* bcom_psc_parameters - Bestcomm initialization value table for PSC devices
|
||||
*
|
||||
* This structure is only used internally. It is a lookup table for PSC
|
||||
* specific parameters to bestcomm tasks.
|
||||
*/
|
||||
static struct bcom_psc_params {
|
||||
int rx_initiator;
|
||||
int rx_ipr;
|
||||
int tx_initiator;
|
||||
int tx_ipr;
|
||||
} bcom_psc_params[] = {
|
||||
[0] = {
|
||||
.rx_initiator = BCOM_INITIATOR_PSC1_RX,
|
||||
.rx_ipr = BCOM_IPR_PSC1_RX,
|
||||
.tx_initiator = BCOM_INITIATOR_PSC1_TX,
|
||||
.tx_ipr = BCOM_IPR_PSC1_TX,
|
||||
},
|
||||
[1] = {
|
||||
.rx_initiator = BCOM_INITIATOR_PSC2_RX,
|
||||
.rx_ipr = BCOM_IPR_PSC2_RX,
|
||||
.tx_initiator = BCOM_INITIATOR_PSC2_TX,
|
||||
.tx_ipr = BCOM_IPR_PSC2_TX,
|
||||
},
|
||||
[2] = {
|
||||
.rx_initiator = BCOM_INITIATOR_PSC3_RX,
|
||||
.rx_ipr = BCOM_IPR_PSC3_RX,
|
||||
.tx_initiator = BCOM_INITIATOR_PSC3_TX,
|
||||
.tx_ipr = BCOM_IPR_PSC3_TX,
|
||||
},
|
||||
[3] = {
|
||||
.rx_initiator = BCOM_INITIATOR_PSC4_RX,
|
||||
.rx_ipr = BCOM_IPR_PSC4_RX,
|
||||
.tx_initiator = BCOM_INITIATOR_PSC4_TX,
|
||||
.tx_ipr = BCOM_IPR_PSC4_TX,
|
||||
},
|
||||
[4] = {
|
||||
.rx_initiator = BCOM_INITIATOR_PSC5_RX,
|
||||
.rx_ipr = BCOM_IPR_PSC5_RX,
|
||||
.tx_initiator = BCOM_INITIATOR_PSC5_TX,
|
||||
.tx_ipr = BCOM_IPR_PSC5_TX,
|
||||
},
|
||||
[5] = {
|
||||
.rx_initiator = BCOM_INITIATOR_PSC6_RX,
|
||||
.rx_ipr = BCOM_IPR_PSC6_RX,
|
||||
.tx_initiator = BCOM_INITIATOR_PSC6_TX,
|
||||
.tx_ipr = BCOM_IPR_PSC6_TX,
|
||||
},
|
||||
};
|
||||
|
||||
/**
|
||||
* bcom_psc_gen_bd_rx_init - Allocate a receive bcom_task for a PSC port
|
||||
* @psc_num: Number of the PSC to allocate a task for
|
||||
* @queue_len: number of buffer descriptors to allocate for the task
|
||||
* @fifo: physical address of FIFO register
|
||||
* @maxbufsize: Maximum receive data size in bytes.
|
||||
*
|
||||
* Allocate a bestcomm task structure for receiving data from a PSC.
|
||||
*/
|
||||
struct bcom_task * bcom_psc_gen_bd_rx_init(unsigned psc_num, int queue_len,
|
||||
phys_addr_t fifo, int maxbufsize)
|
||||
{
|
||||
if (psc_num >= MPC52xx_PSC_MAXNUM)
|
||||
return NULL;
|
||||
|
||||
return bcom_gen_bd_rx_init(queue_len, fifo,
|
||||
bcom_psc_params[psc_num].rx_initiator,
|
||||
bcom_psc_params[psc_num].rx_ipr,
|
||||
maxbufsize);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_psc_gen_bd_rx_init);
|
||||
|
||||
/**
|
||||
* bcom_psc_gen_bd_tx_init - Allocate a transmit bcom_task for a PSC port
|
||||
* @psc_num: Number of the PSC to allocate a task for
|
||||
* @queue_len: number of buffer descriptors to allocate for the task
|
||||
* @fifo: physical address of FIFO register
|
||||
*
|
||||
* Allocate a bestcomm task structure for transmitting data to a PSC.
|
||||
*/
|
||||
struct bcom_task *
|
||||
bcom_psc_gen_bd_tx_init(unsigned psc_num, int queue_len, phys_addr_t fifo)
|
||||
{
|
||||
struct psc;
|
||||
return bcom_gen_bd_tx_init(queue_len, fifo,
|
||||
bcom_psc_params[psc_num].tx_initiator,
|
||||
bcom_psc_params[psc_num].tx_ipr);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_psc_gen_bd_tx_init);
|
||||
|
||||
|
||||
MODULE_DESCRIPTION("BestComm General Buffer Descriptor tasks driver");
|
||||
MODULE_AUTHOR("Jeff Gibbons <jeff.gibbons@appspec.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
179
drivers/dma/bestcomm/sram.c
Normal file
179
drivers/dma/bestcomm/sram.c
Normal file
|
|
@ -0,0 +1,179 @@
|
|||
/*
|
||||
* Simple memory allocator for on-board SRAM
|
||||
*
|
||||
*
|
||||
* Maintainer : Sylvain Munaut <tnt@246tNt.com>
|
||||
*
|
||||
* Copyright (C) 2005 Sylvain Munaut <tnt@246tNt.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
#include <linux/fsl/bestcomm/sram.h>
|
||||
|
||||
|
||||
/* Struct keeping our 'state' */
|
||||
struct bcom_sram *bcom_sram = NULL;
|
||||
EXPORT_SYMBOL_GPL(bcom_sram); /* needed for inline functions */
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* Public API */
|
||||
/* ======================================================================== */
|
||||
/* DO NOT USE in interrupts, if needed in irq handler, we should use the
|
||||
_irqsave version of the spin_locks */
|
||||
|
||||
int bcom_sram_init(struct device_node *sram_node, char *owner)
|
||||
{
|
||||
int rv;
|
||||
const u32 *regaddr_p;
|
||||
u64 regaddr64, size64;
|
||||
unsigned int psize;
|
||||
|
||||
/* Create our state struct */
|
||||
if (bcom_sram) {
|
||||
printk(KERN_ERR "%s: bcom_sram_init: "
|
||||
"Already initialized !\n", owner);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
bcom_sram = kmalloc(sizeof(struct bcom_sram), GFP_KERNEL);
|
||||
if (!bcom_sram) {
|
||||
printk(KERN_ERR "%s: bcom_sram_init: "
|
||||
"Couldn't allocate internal state !\n", owner);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* Get address and size of the sram */
|
||||
regaddr_p = of_get_address(sram_node, 0, &size64, NULL);
|
||||
if (!regaddr_p) {
|
||||
printk(KERN_ERR "%s: bcom_sram_init: "
|
||||
"Invalid device node !\n", owner);
|
||||
rv = -EINVAL;
|
||||
goto error_free;
|
||||
}
|
||||
|
||||
regaddr64 = of_translate_address(sram_node, regaddr_p);
|
||||
|
||||
bcom_sram->base_phys = (phys_addr_t) regaddr64;
|
||||
bcom_sram->size = (unsigned int) size64;
|
||||
|
||||
/* Request region */
|
||||
if (!request_mem_region(bcom_sram->base_phys, bcom_sram->size, owner)) {
|
||||
printk(KERN_ERR "%s: bcom_sram_init: "
|
||||
"Couldn't request region !\n", owner);
|
||||
rv = -EBUSY;
|
||||
goto error_free;
|
||||
}
|
||||
|
||||
/* Map SRAM */
|
||||
/* sram is not really __iomem */
|
||||
bcom_sram->base_virt = (void*) ioremap(bcom_sram->base_phys, bcom_sram->size);
|
||||
|
||||
if (!bcom_sram->base_virt) {
|
||||
printk(KERN_ERR "%s: bcom_sram_init: "
|
||||
"Map error SRAM zone 0x%08lx (0x%0x)!\n",
|
||||
owner, (long)bcom_sram->base_phys, bcom_sram->size );
|
||||
rv = -ENOMEM;
|
||||
goto error_release;
|
||||
}
|
||||
|
||||
/* Create an rheap (defaults to 32 bits word alignment) */
|
||||
bcom_sram->rh = rh_create(4);
|
||||
|
||||
/* Attach the free zones */
|
||||
#if 0
|
||||
/* Currently disabled ... for future use only */
|
||||
reg_addr_p = of_get_property(sram_node, "available", &psize);
|
||||
#else
|
||||
regaddr_p = NULL;
|
||||
psize = 0;
|
||||
#endif
|
||||
|
||||
if (!regaddr_p || !psize) {
|
||||
/* Attach the whole zone */
|
||||
rh_attach_region(bcom_sram->rh, 0, bcom_sram->size);
|
||||
} else {
|
||||
/* Attach each zone independently */
|
||||
while (psize >= 2 * sizeof(u32)) {
|
||||
phys_addr_t zbase = of_translate_address(sram_node, regaddr_p);
|
||||
rh_attach_region(bcom_sram->rh, zbase - bcom_sram->base_phys, regaddr_p[1]);
|
||||
regaddr_p += 2;
|
||||
psize -= 2 * sizeof(u32);
|
||||
}
|
||||
}
|
||||
|
||||
/* Init our spinlock */
|
||||
spin_lock_init(&bcom_sram->lock);
|
||||
|
||||
return 0;
|
||||
|
||||
error_release:
|
||||
release_mem_region(bcom_sram->base_phys, bcom_sram->size);
|
||||
error_free:
|
||||
kfree(bcom_sram);
|
||||
bcom_sram = NULL;
|
||||
|
||||
return rv;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_sram_init);
|
||||
|
||||
void bcom_sram_cleanup(void)
|
||||
{
|
||||
/* Free resources */
|
||||
if (bcom_sram) {
|
||||
rh_destroy(bcom_sram->rh);
|
||||
iounmap((void __iomem *)bcom_sram->base_virt);
|
||||
release_mem_region(bcom_sram->base_phys, bcom_sram->size);
|
||||
kfree(bcom_sram);
|
||||
bcom_sram = NULL;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_sram_cleanup);
|
||||
|
||||
void* bcom_sram_alloc(int size, int align, phys_addr_t *phys)
|
||||
{
|
||||
unsigned long offset;
|
||||
|
||||
spin_lock(&bcom_sram->lock);
|
||||
offset = rh_alloc_align(bcom_sram->rh, size, align, NULL);
|
||||
spin_unlock(&bcom_sram->lock);
|
||||
|
||||
if (IS_ERR_VALUE(offset))
|
||||
return NULL;
|
||||
|
||||
*phys = bcom_sram->base_phys + offset;
|
||||
return bcom_sram->base_virt + offset;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_sram_alloc);
|
||||
|
||||
void bcom_sram_free(void *ptr)
|
||||
{
|
||||
unsigned long offset;
|
||||
|
||||
if (!ptr)
|
||||
return;
|
||||
|
||||
offset = ptr - bcom_sram->base_virt;
|
||||
|
||||
spin_lock(&bcom_sram->lock);
|
||||
rh_free(bcom_sram->rh, offset);
|
||||
spin_unlock(&bcom_sram->lock);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcom_sram_free);
|
||||
|
||||
2809
drivers/dma/coh901318.c
Normal file
2809
drivers/dma/coh901318.c
Normal file
File diff suppressed because it is too large
Load diff
141
drivers/dma/coh901318.h
Normal file
141
drivers/dma/coh901318.h
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
/*
|
||||
* Copyright (C) 2007-2013 ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* DMA driver for COH 901 318
|
||||
* Author: Per Friden <per.friden@stericsson.com>
|
||||
*/
|
||||
|
||||
#ifndef COH901318_H
|
||||
#define COH901318_H
|
||||
|
||||
#define MAX_DMA_PACKET_SIZE_SHIFT 11
|
||||
#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
|
||||
|
||||
struct device;
|
||||
|
||||
struct coh901318_pool {
|
||||
spinlock_t lock;
|
||||
struct dma_pool *dmapool;
|
||||
struct device *dev;
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
int debugfs_pool_counter;
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* struct coh901318_lli - linked list item for DMAC
|
||||
* @control: control settings for DMAC
|
||||
* @src_addr: transfer source address
|
||||
* @dst_addr: transfer destination address
|
||||
* @link_addr: physical address to next lli
|
||||
* @virt_link_addr: virtual address of next lli (only used by pool_free)
|
||||
* @phy_this: physical address of current lli (only used by pool_free)
|
||||
*/
|
||||
struct coh901318_lli {
|
||||
u32 control;
|
||||
dma_addr_t src_addr;
|
||||
dma_addr_t dst_addr;
|
||||
dma_addr_t link_addr;
|
||||
|
||||
void *virt_link_addr;
|
||||
dma_addr_t phy_this;
|
||||
};
|
||||
|
||||
/**
|
||||
* coh901318_pool_create() - Creates an dma pool for lli:s
|
||||
* @pool: pool handle
|
||||
* @dev: dma device
|
||||
* @lli_nbr: number of lli:s in the pool
|
||||
* @algin: address alignemtn of lli:s
|
||||
* returns 0 on success otherwise none zero
|
||||
*/
|
||||
int coh901318_pool_create(struct coh901318_pool *pool,
|
||||
struct device *dev,
|
||||
size_t lli_nbr, size_t align);
|
||||
|
||||
/**
|
||||
* coh901318_pool_destroy() - Destroys the dma pool
|
||||
* @pool: pool handle
|
||||
* returns 0 on success otherwise none zero
|
||||
*/
|
||||
int coh901318_pool_destroy(struct coh901318_pool *pool);
|
||||
|
||||
/**
|
||||
* coh901318_lli_alloc() - Allocates a linked list
|
||||
*
|
||||
* @pool: pool handle
|
||||
* @len: length to list
|
||||
* return: none NULL if success otherwise NULL
|
||||
*/
|
||||
struct coh901318_lli *
|
||||
coh901318_lli_alloc(struct coh901318_pool *pool,
|
||||
unsigned int len);
|
||||
|
||||
/**
|
||||
* coh901318_lli_free() - Returns the linked list items to the pool
|
||||
* @pool: pool handle
|
||||
* @lli: reference to lli pointer to be freed
|
||||
*/
|
||||
void coh901318_lli_free(struct coh901318_pool *pool,
|
||||
struct coh901318_lli **lli);
|
||||
|
||||
/**
|
||||
* coh901318_lli_fill_memcpy() - Prepares the lli:s for dma memcpy
|
||||
* @pool: pool handle
|
||||
* @lli: allocated lli
|
||||
* @src: src address
|
||||
* @size: transfer size
|
||||
* @dst: destination address
|
||||
* @ctrl_chained: ctrl for chained lli
|
||||
* @ctrl_last: ctrl for the last lli
|
||||
* returns number of CPU interrupts for the lli, negative on error.
|
||||
*/
|
||||
int
|
||||
coh901318_lli_fill_memcpy(struct coh901318_pool *pool,
|
||||
struct coh901318_lli *lli,
|
||||
dma_addr_t src, unsigned int size,
|
||||
dma_addr_t dst, u32 ctrl_chained, u32 ctrl_last);
|
||||
|
||||
/**
|
||||
* coh901318_lli_fill_single() - Prepares the lli:s for dma single transfer
|
||||
* @pool: pool handle
|
||||
* @lli: allocated lli
|
||||
* @buf: transfer buffer
|
||||
* @size: transfer size
|
||||
* @dev_addr: address of periphal
|
||||
* @ctrl_chained: ctrl for chained lli
|
||||
* @ctrl_last: ctrl for the last lli
|
||||
* @dir: direction of transfer (to or from device)
|
||||
* returns number of CPU interrupts for the lli, negative on error.
|
||||
*/
|
||||
int
|
||||
coh901318_lli_fill_single(struct coh901318_pool *pool,
|
||||
struct coh901318_lli *lli,
|
||||
dma_addr_t buf, unsigned int size,
|
||||
dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_last,
|
||||
enum dma_transfer_direction dir);
|
||||
|
||||
/**
|
||||
* coh901318_lli_fill_single() - Prepares the lli:s for dma scatter list transfer
|
||||
* @pool: pool handle
|
||||
* @lli: allocated lli
|
||||
* @sg: scatter gather list
|
||||
* @nents: number of entries in sg
|
||||
* @dev_addr: address of periphal
|
||||
* @ctrl_chained: ctrl for chained lli
|
||||
* @ctrl: ctrl of middle lli
|
||||
* @ctrl_last: ctrl for the last lli
|
||||
* @dir: direction of transfer (to or from device)
|
||||
* @ctrl_irq_mask: ctrl mask for CPU interrupt
|
||||
* returns number of CPU interrupts for the lli, negative on error.
|
||||
*/
|
||||
int
|
||||
coh901318_lli_fill_sg(struct coh901318_pool *pool,
|
||||
struct coh901318_lli *lli,
|
||||
struct scatterlist *sg, unsigned int nents,
|
||||
dma_addr_t dev_addr, u32 ctrl_chained,
|
||||
u32 ctrl, u32 ctrl_last,
|
||||
enum dma_transfer_direction dir, u32 ctrl_irq_mask);
|
||||
|
||||
#endif /* COH901318_H */
|
||||
313
drivers/dma/coh901318_lli.c
Normal file
313
drivers/dma/coh901318_lli.c
Normal file
|
|
@ -0,0 +1,313 @@
|
|||
/*
|
||||
* driver/dma/coh901318_lli.c
|
||||
*
|
||||
* Copyright (C) 2007-2009 ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* Support functions for handling lli for dma
|
||||
* Author: Per Friden <per.friden@stericsson.com>
|
||||
*/
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/memory.h>
|
||||
#include <linux/gfp.h>
|
||||
#include <linux/dmapool.h>
|
||||
#include <linux/dmaengine.h>
|
||||
|
||||
#include "coh901318.h"
|
||||
|
||||
#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
|
||||
#define DEBUGFS_POOL_COUNTER_RESET(pool) (pool->debugfs_pool_counter = 0)
|
||||
#define DEBUGFS_POOL_COUNTER_ADD(pool, add) (pool->debugfs_pool_counter += add)
|
||||
#else
|
||||
#define DEBUGFS_POOL_COUNTER_RESET(pool)
|
||||
#define DEBUGFS_POOL_COUNTER_ADD(pool, add)
|
||||
#endif
|
||||
|
||||
static struct coh901318_lli *
|
||||
coh901318_lli_next(struct coh901318_lli *data)
|
||||
{
|
||||
if (data == NULL || data->link_addr == 0)
|
||||
return NULL;
|
||||
|
||||
return (struct coh901318_lli *) data->virt_link_addr;
|
||||
}
|
||||
|
||||
int coh901318_pool_create(struct coh901318_pool *pool,
|
||||
struct device *dev,
|
||||
size_t size, size_t align)
|
||||
{
|
||||
spin_lock_init(&pool->lock);
|
||||
pool->dev = dev;
|
||||
pool->dmapool = dma_pool_create("lli_pool", dev, size, align, 0);
|
||||
|
||||
DEBUGFS_POOL_COUNTER_RESET(pool);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int coh901318_pool_destroy(struct coh901318_pool *pool)
|
||||
{
|
||||
|
||||
dma_pool_destroy(pool->dmapool);
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct coh901318_lli *
|
||||
coh901318_lli_alloc(struct coh901318_pool *pool, unsigned int len)
|
||||
{
|
||||
int i;
|
||||
struct coh901318_lli *head;
|
||||
struct coh901318_lli *lli;
|
||||
struct coh901318_lli *lli_prev;
|
||||
dma_addr_t phy;
|
||||
|
||||
if (len == 0)
|
||||
return NULL;
|
||||
|
||||
spin_lock(&pool->lock);
|
||||
|
||||
head = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);
|
||||
|
||||
if (head == NULL)
|
||||
goto err;
|
||||
|
||||
DEBUGFS_POOL_COUNTER_ADD(pool, 1);
|
||||
|
||||
lli = head;
|
||||
lli->phy_this = phy;
|
||||
lli->link_addr = 0x00000000;
|
||||
lli->virt_link_addr = 0x00000000U;
|
||||
|
||||
for (i = 1; i < len; i++) {
|
||||
lli_prev = lli;
|
||||
|
||||
lli = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);
|
||||
|
||||
if (lli == NULL)
|
||||
goto err_clean_up;
|
||||
|
||||
DEBUGFS_POOL_COUNTER_ADD(pool, 1);
|
||||
lli->phy_this = phy;
|
||||
lli->link_addr = 0x00000000;
|
||||
lli->virt_link_addr = 0x00000000U;
|
||||
|
||||
lli_prev->link_addr = phy;
|
||||
lli_prev->virt_link_addr = lli;
|
||||
}
|
||||
|
||||
spin_unlock(&pool->lock);
|
||||
|
||||
return head;
|
||||
|
||||
err:
|
||||
spin_unlock(&pool->lock);
|
||||
return NULL;
|
||||
|
||||
err_clean_up:
|
||||
lli_prev->link_addr = 0x00000000U;
|
||||
spin_unlock(&pool->lock);
|
||||
coh901318_lli_free(pool, &head);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
void coh901318_lli_free(struct coh901318_pool *pool,
|
||||
struct coh901318_lli **lli)
|
||||
{
|
||||
struct coh901318_lli *l;
|
||||
struct coh901318_lli *next;
|
||||
|
||||
if (lli == NULL)
|
||||
return;
|
||||
|
||||
l = *lli;
|
||||
|
||||
if (l == NULL)
|
||||
return;
|
||||
|
||||
spin_lock(&pool->lock);
|
||||
|
||||
while (l->link_addr) {
|
||||
next = l->virt_link_addr;
|
||||
dma_pool_free(pool->dmapool, l, l->phy_this);
|
||||
DEBUGFS_POOL_COUNTER_ADD(pool, -1);
|
||||
l = next;
|
||||
}
|
||||
dma_pool_free(pool->dmapool, l, l->phy_this);
|
||||
DEBUGFS_POOL_COUNTER_ADD(pool, -1);
|
||||
|
||||
spin_unlock(&pool->lock);
|
||||
*lli = NULL;
|
||||
}
|
||||
|
||||
int
|
||||
coh901318_lli_fill_memcpy(struct coh901318_pool *pool,
|
||||
struct coh901318_lli *lli,
|
||||
dma_addr_t source, unsigned int size,
|
||||
dma_addr_t destination, u32 ctrl_chained,
|
||||
u32 ctrl_eom)
|
||||
{
|
||||
int s = size;
|
||||
dma_addr_t src = source;
|
||||
dma_addr_t dst = destination;
|
||||
|
||||
lli->src_addr = src;
|
||||
lli->dst_addr = dst;
|
||||
|
||||
while (lli->link_addr) {
|
||||
lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;
|
||||
lli->src_addr = src;
|
||||
lli->dst_addr = dst;
|
||||
|
||||
s -= MAX_DMA_PACKET_SIZE;
|
||||
lli = coh901318_lli_next(lli);
|
||||
|
||||
src += MAX_DMA_PACKET_SIZE;
|
||||
dst += MAX_DMA_PACKET_SIZE;
|
||||
}
|
||||
|
||||
lli->control = ctrl_eom | s;
|
||||
lli->src_addr = src;
|
||||
lli->dst_addr = dst;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
coh901318_lli_fill_single(struct coh901318_pool *pool,
|
||||
struct coh901318_lli *lli,
|
||||
dma_addr_t buf, unsigned int size,
|
||||
dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_eom,
|
||||
enum dma_transfer_direction dir)
|
||||
{
|
||||
int s = size;
|
||||
dma_addr_t src;
|
||||
dma_addr_t dst;
|
||||
|
||||
|
||||
if (dir == DMA_MEM_TO_DEV) {
|
||||
src = buf;
|
||||
dst = dev_addr;
|
||||
|
||||
} else if (dir == DMA_DEV_TO_MEM) {
|
||||
|
||||
src = dev_addr;
|
||||
dst = buf;
|
||||
} else {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
while (lli->link_addr) {
|
||||
size_t block_size = MAX_DMA_PACKET_SIZE;
|
||||
lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;
|
||||
|
||||
/* If we are on the next-to-final block and there will
|
||||
* be less than half a DMA packet left for the last
|
||||
* block, then we want to make this block a little
|
||||
* smaller to balance the sizes. This is meant to
|
||||
* avoid too small transfers if the buffer size is
|
||||
* (MAX_DMA_PACKET_SIZE*N + 1) */
|
||||
if (s < (MAX_DMA_PACKET_SIZE + MAX_DMA_PACKET_SIZE/2))
|
||||
block_size = MAX_DMA_PACKET_SIZE/2;
|
||||
|
||||
s -= block_size;
|
||||
lli->src_addr = src;
|
||||
lli->dst_addr = dst;
|
||||
|
||||
lli = coh901318_lli_next(lli);
|
||||
|
||||
if (dir == DMA_MEM_TO_DEV)
|
||||
src += block_size;
|
||||
else if (dir == DMA_DEV_TO_MEM)
|
||||
dst += block_size;
|
||||
}
|
||||
|
||||
lli->control = ctrl_eom | s;
|
||||
lli->src_addr = src;
|
||||
lli->dst_addr = dst;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
coh901318_lli_fill_sg(struct coh901318_pool *pool,
|
||||
struct coh901318_lli *lli,
|
||||
struct scatterlist *sgl, unsigned int nents,
|
||||
dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl,
|
||||
u32 ctrl_last,
|
||||
enum dma_transfer_direction dir, u32 ctrl_irq_mask)
|
||||
{
|
||||
int i;
|
||||
struct scatterlist *sg;
|
||||
u32 ctrl_sg;
|
||||
dma_addr_t src = 0;
|
||||
dma_addr_t dst = 0;
|
||||
u32 bytes_to_transfer;
|
||||
u32 elem_size;
|
||||
|
||||
if (lli == NULL)
|
||||
goto err;
|
||||
|
||||
spin_lock(&pool->lock);
|
||||
|
||||
if (dir == DMA_MEM_TO_DEV)
|
||||
dst = dev_addr;
|
||||
else if (dir == DMA_DEV_TO_MEM)
|
||||
src = dev_addr;
|
||||
else
|
||||
goto err;
|
||||
|
||||
for_each_sg(sgl, sg, nents, i) {
|
||||
if (sg_is_chain(sg)) {
|
||||
/* sg continues to the next sg-element don't
|
||||
* send ctrl_finish until the last
|
||||
* sg-element in the chain
|
||||
*/
|
||||
ctrl_sg = ctrl_chained;
|
||||
} else if (i == nents - 1)
|
||||
ctrl_sg = ctrl_last;
|
||||
else
|
||||
ctrl_sg = ctrl ? ctrl : ctrl_last;
|
||||
|
||||
|
||||
if (dir == DMA_MEM_TO_DEV)
|
||||
/* increment source address */
|
||||
src = sg_dma_address(sg);
|
||||
else
|
||||
/* increment destination address */
|
||||
dst = sg_dma_address(sg);
|
||||
|
||||
bytes_to_transfer = sg_dma_len(sg);
|
||||
|
||||
while (bytes_to_transfer) {
|
||||
u32 val;
|
||||
|
||||
if (bytes_to_transfer > MAX_DMA_PACKET_SIZE) {
|
||||
elem_size = MAX_DMA_PACKET_SIZE;
|
||||
val = ctrl_chained;
|
||||
} else {
|
||||
elem_size = bytes_to_transfer;
|
||||
val = ctrl_sg;
|
||||
}
|
||||
|
||||
lli->control = val | elem_size;
|
||||
lli->src_addr = src;
|
||||
lli->dst_addr = dst;
|
||||
|
||||
if (dir == DMA_DEV_TO_MEM)
|
||||
dst += elem_size;
|
||||
else
|
||||
src += elem_size;
|
||||
|
||||
BUG_ON(lli->link_addr & 3);
|
||||
|
||||
bytes_to_transfer -= elem_size;
|
||||
lli = coh901318_lli_next(lli);
|
||||
}
|
||||
|
||||
}
|
||||
spin_unlock(&pool->lock);
|
||||
|
||||
return 0;
|
||||
err:
|
||||
spin_unlock(&pool->lock);
|
||||
return -EINVAL;
|
||||
}
|
||||
1099
drivers/dma/cppi41.c
Normal file
1099
drivers/dma/cppi41.c
Normal file
File diff suppressed because it is too large
Load diff
618
drivers/dma/dma-jz4740.c
Normal file
618
drivers/dma/dma-jz4740.c
Normal file
|
|
@ -0,0 +1,618 @@
|
|||
/*
|
||||
* Copyright (C) 2013, Lars-Peter Clausen <lars@metafoo.de>
|
||||
* JZ4740 DMAC support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include <asm/mach-jz4740/dma.h>
|
||||
|
||||
#include "virt-dma.h"
|
||||
|
||||
#define JZ_DMA_NR_CHANS 6
|
||||
|
||||
#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
|
||||
#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
|
||||
#define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20)
|
||||
#define JZ_REG_DMA_REQ_TYPE(x) (0x0C + (x) * 0x20)
|
||||
#define JZ_REG_DMA_STATUS_CTRL(x) (0x10 + (x) * 0x20)
|
||||
#define JZ_REG_DMA_CMD(x) (0x14 + (x) * 0x20)
|
||||
#define JZ_REG_DMA_DESC_ADDR(x) (0x18 + (x) * 0x20)
|
||||
|
||||
#define JZ_REG_DMA_CTRL 0x300
|
||||
#define JZ_REG_DMA_IRQ 0x304
|
||||
#define JZ_REG_DMA_DOORBELL 0x308
|
||||
#define JZ_REG_DMA_DOORBELL_SET 0x30C
|
||||
|
||||
#define JZ_DMA_STATUS_CTRL_NO_DESC BIT(31)
|
||||
#define JZ_DMA_STATUS_CTRL_DESC_INV BIT(6)
|
||||
#define JZ_DMA_STATUS_CTRL_ADDR_ERR BIT(4)
|
||||
#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE BIT(3)
|
||||
#define JZ_DMA_STATUS_CTRL_HALT BIT(2)
|
||||
#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE BIT(1)
|
||||
#define JZ_DMA_STATUS_CTRL_ENABLE BIT(0)
|
||||
|
||||
#define JZ_DMA_CMD_SRC_INC BIT(23)
|
||||
#define JZ_DMA_CMD_DST_INC BIT(22)
|
||||
#define JZ_DMA_CMD_RDIL_MASK (0xf << 16)
|
||||
#define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14)
|
||||
#define JZ_DMA_CMD_DST_WIDTH_MASK (0x3 << 12)
|
||||
#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK (0x7 << 8)
|
||||
#define JZ_DMA_CMD_BLOCK_MODE BIT(7)
|
||||
#define JZ_DMA_CMD_DESC_VALID BIT(4)
|
||||
#define JZ_DMA_CMD_DESC_VALID_MODE BIT(3)
|
||||
#define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2)
|
||||
#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1)
|
||||
#define JZ_DMA_CMD_LINK_ENABLE BIT(0)
|
||||
|
||||
#define JZ_DMA_CMD_FLAGS_OFFSET 22
|
||||
#define JZ_DMA_CMD_RDIL_OFFSET 16
|
||||
#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
|
||||
#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
|
||||
#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
|
||||
#define JZ_DMA_CMD_MODE_OFFSET 7
|
||||
|
||||
#define JZ_DMA_CTRL_PRIORITY_MASK (0x3 << 8)
|
||||
#define JZ_DMA_CTRL_HALT BIT(3)
|
||||
#define JZ_DMA_CTRL_ADDRESS_ERROR BIT(2)
|
||||
#define JZ_DMA_CTRL_ENABLE BIT(0)
|
||||
|
||||
enum jz4740_dma_width {
|
||||
JZ4740_DMA_WIDTH_32BIT = 0,
|
||||
JZ4740_DMA_WIDTH_8BIT = 1,
|
||||
JZ4740_DMA_WIDTH_16BIT = 2,
|
||||
};
|
||||
|
||||
enum jz4740_dma_transfer_size {
|
||||
JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0,
|
||||
JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1,
|
||||
JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2,
|
||||
JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
|
||||
JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
|
||||
};
|
||||
|
||||
enum jz4740_dma_flags {
|
||||
JZ4740_DMA_SRC_AUTOINC = 0x2,
|
||||
JZ4740_DMA_DST_AUTOINC = 0x1,
|
||||
};
|
||||
|
||||
enum jz4740_dma_mode {
|
||||
JZ4740_DMA_MODE_SINGLE = 0,
|
||||
JZ4740_DMA_MODE_BLOCK = 1,
|
||||
};
|
||||
|
||||
struct jz4740_dma_sg {
|
||||
dma_addr_t addr;
|
||||
unsigned int len;
|
||||
};
|
||||
|
||||
struct jz4740_dma_desc {
|
||||
struct virt_dma_desc vdesc;
|
||||
|
||||
enum dma_transfer_direction direction;
|
||||
bool cyclic;
|
||||
|
||||
unsigned int num_sgs;
|
||||
struct jz4740_dma_sg sg[];
|
||||
};
|
||||
|
||||
struct jz4740_dmaengine_chan {
|
||||
struct virt_dma_chan vchan;
|
||||
unsigned int id;
|
||||
|
||||
dma_addr_t fifo_addr;
|
||||
unsigned int transfer_shift;
|
||||
|
||||
struct jz4740_dma_desc *desc;
|
||||
unsigned int next_sg;
|
||||
};
|
||||
|
||||
struct jz4740_dma_dev {
|
||||
struct dma_device ddev;
|
||||
void __iomem *base;
|
||||
struct clk *clk;
|
||||
|
||||
struct jz4740_dmaengine_chan chan[JZ_DMA_NR_CHANS];
|
||||
};
|
||||
|
||||
static struct jz4740_dma_dev *jz4740_dma_chan_get_dev(
|
||||
struct jz4740_dmaengine_chan *chan)
|
||||
{
|
||||
return container_of(chan->vchan.chan.device, struct jz4740_dma_dev,
|
||||
ddev);
|
||||
}
|
||||
|
||||
static struct jz4740_dmaengine_chan *to_jz4740_dma_chan(struct dma_chan *c)
|
||||
{
|
||||
return container_of(c, struct jz4740_dmaengine_chan, vchan.chan);
|
||||
}
|
||||
|
||||
static struct jz4740_dma_desc *to_jz4740_dma_desc(struct virt_dma_desc *vdesc)
|
||||
{
|
||||
return container_of(vdesc, struct jz4740_dma_desc, vdesc);
|
||||
}
|
||||
|
||||
static inline uint32_t jz4740_dma_read(struct jz4740_dma_dev *dmadev,
|
||||
unsigned int reg)
|
||||
{
|
||||
return readl(dmadev->base + reg);
|
||||
}
|
||||
|
||||
static inline void jz4740_dma_write(struct jz4740_dma_dev *dmadev,
|
||||
unsigned reg, uint32_t val)
|
||||
{
|
||||
writel(val, dmadev->base + reg);
|
||||
}
|
||||
|
||||
static inline void jz4740_dma_write_mask(struct jz4740_dma_dev *dmadev,
|
||||
unsigned int reg, uint32_t val, uint32_t mask)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
tmp = jz4740_dma_read(dmadev, reg);
|
||||
tmp &= ~mask;
|
||||
tmp |= val;
|
||||
jz4740_dma_write(dmadev, reg, tmp);
|
||||
}
|
||||
|
||||
static struct jz4740_dma_desc *jz4740_dma_alloc_desc(unsigned int num_sgs)
|
||||
{
|
||||
return kzalloc(sizeof(struct jz4740_dma_desc) +
|
||||
sizeof(struct jz4740_dma_sg) * num_sgs, GFP_ATOMIC);
|
||||
}
|
||||
|
||||
static enum jz4740_dma_width jz4740_dma_width(enum dma_slave_buswidth width)
|
||||
{
|
||||
switch (width) {
|
||||
case DMA_SLAVE_BUSWIDTH_1_BYTE:
|
||||
return JZ4740_DMA_WIDTH_8BIT;
|
||||
case DMA_SLAVE_BUSWIDTH_2_BYTES:
|
||||
return JZ4740_DMA_WIDTH_16BIT;
|
||||
case DMA_SLAVE_BUSWIDTH_4_BYTES:
|
||||
return JZ4740_DMA_WIDTH_32BIT;
|
||||
default:
|
||||
return JZ4740_DMA_WIDTH_32BIT;
|
||||
}
|
||||
}
|
||||
|
||||
static enum jz4740_dma_transfer_size jz4740_dma_maxburst(u32 maxburst)
|
||||
{
|
||||
if (maxburst <= 1)
|
||||
return JZ4740_DMA_TRANSFER_SIZE_1BYTE;
|
||||
else if (maxburst <= 3)
|
||||
return JZ4740_DMA_TRANSFER_SIZE_2BYTE;
|
||||
else if (maxburst <= 15)
|
||||
return JZ4740_DMA_TRANSFER_SIZE_4BYTE;
|
||||
else if (maxburst <= 31)
|
||||
return JZ4740_DMA_TRANSFER_SIZE_16BYTE;
|
||||
|
||||
return JZ4740_DMA_TRANSFER_SIZE_32BYTE;
|
||||
}
|
||||
|
||||
static int jz4740_dma_slave_config(struct dma_chan *c,
|
||||
const struct dma_slave_config *config)
|
||||
{
|
||||
struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
|
||||
struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
|
||||
enum jz4740_dma_width src_width;
|
||||
enum jz4740_dma_width dst_width;
|
||||
enum jz4740_dma_transfer_size transfer_size;
|
||||
enum jz4740_dma_flags flags;
|
||||
uint32_t cmd;
|
||||
|
||||
switch (config->direction) {
|
||||
case DMA_MEM_TO_DEV:
|
||||
flags = JZ4740_DMA_SRC_AUTOINC;
|
||||
transfer_size = jz4740_dma_maxburst(config->dst_maxburst);
|
||||
chan->fifo_addr = config->dst_addr;
|
||||
break;
|
||||
case DMA_DEV_TO_MEM:
|
||||
flags = JZ4740_DMA_DST_AUTOINC;
|
||||
transfer_size = jz4740_dma_maxburst(config->src_maxburst);
|
||||
chan->fifo_addr = config->src_addr;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
src_width = jz4740_dma_width(config->src_addr_width);
|
||||
dst_width = jz4740_dma_width(config->dst_addr_width);
|
||||
|
||||
switch (transfer_size) {
|
||||
case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
|
||||
chan->transfer_shift = 1;
|
||||
break;
|
||||
case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
|
||||
chan->transfer_shift = 2;
|
||||
break;
|
||||
case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
|
||||
chan->transfer_shift = 4;
|
||||
break;
|
||||
case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
|
||||
chan->transfer_shift = 5;
|
||||
break;
|
||||
default:
|
||||
chan->transfer_shift = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
cmd = flags << JZ_DMA_CMD_FLAGS_OFFSET;
|
||||
cmd |= src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
|
||||
cmd |= dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
|
||||
cmd |= transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
|
||||
cmd |= JZ4740_DMA_MODE_SINGLE << JZ_DMA_CMD_MODE_OFFSET;
|
||||
cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
|
||||
|
||||
jz4740_dma_write(dmadev, JZ_REG_DMA_CMD(chan->id), cmd);
|
||||
jz4740_dma_write(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0);
|
||||
jz4740_dma_write(dmadev, JZ_REG_DMA_REQ_TYPE(chan->id),
|
||||
config->slave_id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jz4740_dma_terminate_all(struct dma_chan *c)
|
||||
{
|
||||
struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
|
||||
struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
|
||||
unsigned long flags;
|
||||
LIST_HEAD(head);
|
||||
|
||||
spin_lock_irqsave(&chan->vchan.lock, flags);
|
||||
jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0,
|
||||
JZ_DMA_STATUS_CTRL_ENABLE);
|
||||
chan->desc = NULL;
|
||||
vchan_get_all_descriptors(&chan->vchan, &head);
|
||||
spin_unlock_irqrestore(&chan->vchan.lock, flags);
|
||||
|
||||
vchan_dma_desc_free_list(&chan->vchan, &head);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jz4740_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
struct dma_slave_config *config = (struct dma_slave_config *)arg;
|
||||
|
||||
switch (cmd) {
|
||||
case DMA_SLAVE_CONFIG:
|
||||
return jz4740_dma_slave_config(chan, config);
|
||||
case DMA_TERMINATE_ALL:
|
||||
return jz4740_dma_terminate_all(chan);
|
||||
default:
|
||||
return -ENOSYS;
|
||||
}
|
||||
}
|
||||
|
||||
static int jz4740_dma_start_transfer(struct jz4740_dmaengine_chan *chan)
|
||||
{
|
||||
struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
|
||||
dma_addr_t src_addr, dst_addr;
|
||||
struct virt_dma_desc *vdesc;
|
||||
struct jz4740_dma_sg *sg;
|
||||
|
||||
jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0,
|
||||
JZ_DMA_STATUS_CTRL_ENABLE);
|
||||
|
||||
if (!chan->desc) {
|
||||
vdesc = vchan_next_desc(&chan->vchan);
|
||||
if (!vdesc)
|
||||
return 0;
|
||||
chan->desc = to_jz4740_dma_desc(vdesc);
|
||||
chan->next_sg = 0;
|
||||
}
|
||||
|
||||
if (chan->next_sg == chan->desc->num_sgs)
|
||||
chan->next_sg = 0;
|
||||
|
||||
sg = &chan->desc->sg[chan->next_sg];
|
||||
|
||||
if (chan->desc->direction == DMA_MEM_TO_DEV) {
|
||||
src_addr = sg->addr;
|
||||
dst_addr = chan->fifo_addr;
|
||||
} else {
|
||||
src_addr = chan->fifo_addr;
|
||||
dst_addr = sg->addr;
|
||||
}
|
||||
jz4740_dma_write(dmadev, JZ_REG_DMA_SRC_ADDR(chan->id), src_addr);
|
||||
jz4740_dma_write(dmadev, JZ_REG_DMA_DST_ADDR(chan->id), dst_addr);
|
||||
jz4740_dma_write(dmadev, JZ_REG_DMA_TRANSFER_COUNT(chan->id),
|
||||
sg->len >> chan->transfer_shift);
|
||||
|
||||
chan->next_sg++;
|
||||
|
||||
jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id),
|
||||
JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE,
|
||||
JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC |
|
||||
JZ_DMA_STATUS_CTRL_ENABLE);
|
||||
|
||||
jz4740_dma_write_mask(dmadev, JZ_REG_DMA_CTRL,
|
||||
JZ_DMA_CTRL_ENABLE,
|
||||
JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void jz4740_dma_chan_irq(struct jz4740_dmaengine_chan *chan)
|
||||
{
|
||||
spin_lock(&chan->vchan.lock);
|
||||
if (chan->desc) {
|
||||
if (chan->desc && chan->desc->cyclic) {
|
||||
vchan_cyclic_callback(&chan->desc->vdesc);
|
||||
} else {
|
||||
if (chan->next_sg == chan->desc->num_sgs) {
|
||||
list_del(&chan->desc->vdesc.node);
|
||||
vchan_cookie_complete(&chan->desc->vdesc);
|
||||
chan->desc = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
jz4740_dma_start_transfer(chan);
|
||||
spin_unlock(&chan->vchan.lock);
|
||||
}
|
||||
|
||||
static irqreturn_t jz4740_dma_irq(int irq, void *devid)
|
||||
{
|
||||
struct jz4740_dma_dev *dmadev = devid;
|
||||
uint32_t irq_status;
|
||||
unsigned int i;
|
||||
|
||||
irq_status = readl(dmadev->base + JZ_REG_DMA_IRQ);
|
||||
|
||||
for (i = 0; i < 6; ++i) {
|
||||
if (irq_status & (1 << i)) {
|
||||
jz4740_dma_write_mask(dmadev,
|
||||
JZ_REG_DMA_STATUS_CTRL(i), 0,
|
||||
JZ_DMA_STATUS_CTRL_ENABLE |
|
||||
JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
|
||||
|
||||
jz4740_dma_chan_irq(&dmadev->chan[i]);
|
||||
}
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void jz4740_dma_issue_pending(struct dma_chan *c)
|
||||
{
|
||||
struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&chan->vchan.lock, flags);
|
||||
if (vchan_issue_pending(&chan->vchan) && !chan->desc)
|
||||
jz4740_dma_start_transfer(chan);
|
||||
spin_unlock_irqrestore(&chan->vchan.lock, flags);
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *jz4740_dma_prep_slave_sg(
|
||||
struct dma_chan *c, struct scatterlist *sgl,
|
||||
unsigned int sg_len, enum dma_transfer_direction direction,
|
||||
unsigned long flags, void *context)
|
||||
{
|
||||
struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
|
||||
struct jz4740_dma_desc *desc;
|
||||
struct scatterlist *sg;
|
||||
unsigned int i;
|
||||
|
||||
desc = jz4740_dma_alloc_desc(sg_len);
|
||||
if (!desc)
|
||||
return NULL;
|
||||
|
||||
for_each_sg(sgl, sg, sg_len, i) {
|
||||
desc->sg[i].addr = sg_dma_address(sg);
|
||||
desc->sg[i].len = sg_dma_len(sg);
|
||||
}
|
||||
|
||||
desc->num_sgs = sg_len;
|
||||
desc->direction = direction;
|
||||
desc->cyclic = false;
|
||||
|
||||
return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *jz4740_dma_prep_dma_cyclic(
|
||||
struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
|
||||
size_t period_len, enum dma_transfer_direction direction,
|
||||
unsigned long flags, void *context)
|
||||
{
|
||||
struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
|
||||
struct jz4740_dma_desc *desc;
|
||||
unsigned int num_periods, i;
|
||||
|
||||
if (buf_len % period_len)
|
||||
return NULL;
|
||||
|
||||
num_periods = buf_len / period_len;
|
||||
|
||||
desc = jz4740_dma_alloc_desc(num_periods);
|
||||
if (!desc)
|
||||
return NULL;
|
||||
|
||||
for (i = 0; i < num_periods; i++) {
|
||||
desc->sg[i].addr = buf_addr;
|
||||
desc->sg[i].len = period_len;
|
||||
buf_addr += period_len;
|
||||
}
|
||||
|
||||
desc->num_sgs = num_periods;
|
||||
desc->direction = direction;
|
||||
desc->cyclic = true;
|
||||
|
||||
return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
|
||||
}
|
||||
|
||||
static size_t jz4740_dma_desc_residue(struct jz4740_dmaengine_chan *chan,
|
||||
struct jz4740_dma_desc *desc, unsigned int next_sg)
|
||||
{
|
||||
struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
|
||||
unsigned int residue, count;
|
||||
unsigned int i;
|
||||
|
||||
residue = 0;
|
||||
|
||||
for (i = next_sg; i < desc->num_sgs; i++)
|
||||
residue += desc->sg[i].len;
|
||||
|
||||
if (next_sg != 0) {
|
||||
count = jz4740_dma_read(dmadev,
|
||||
JZ_REG_DMA_TRANSFER_COUNT(chan->id));
|
||||
residue += count << chan->transfer_shift;
|
||||
}
|
||||
|
||||
return residue;
|
||||
}
|
||||
|
||||
static enum dma_status jz4740_dma_tx_status(struct dma_chan *c,
|
||||
dma_cookie_t cookie, struct dma_tx_state *state)
|
||||
{
|
||||
struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
|
||||
struct virt_dma_desc *vdesc;
|
||||
enum dma_status status;
|
||||
unsigned long flags;
|
||||
|
||||
status = dma_cookie_status(c, cookie, state);
|
||||
if (status == DMA_COMPLETE || !state)
|
||||
return status;
|
||||
|
||||
spin_lock_irqsave(&chan->vchan.lock, flags);
|
||||
vdesc = vchan_find_desc(&chan->vchan, cookie);
|
||||
if (cookie == chan->desc->vdesc.tx.cookie) {
|
||||
state->residue = jz4740_dma_desc_residue(chan, chan->desc,
|
||||
chan->next_sg);
|
||||
} else if (vdesc) {
|
||||
state->residue = jz4740_dma_desc_residue(chan,
|
||||
to_jz4740_dma_desc(vdesc), 0);
|
||||
} else {
|
||||
state->residue = 0;
|
||||
}
|
||||
spin_unlock_irqrestore(&chan->vchan.lock, flags);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static int jz4740_dma_alloc_chan_resources(struct dma_chan *c)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void jz4740_dma_free_chan_resources(struct dma_chan *c)
|
||||
{
|
||||
vchan_free_chan_resources(to_virt_chan(c));
|
||||
}
|
||||
|
||||
static void jz4740_dma_desc_free(struct virt_dma_desc *vdesc)
|
||||
{
|
||||
kfree(container_of(vdesc, struct jz4740_dma_desc, vdesc));
|
||||
}
|
||||
|
||||
static int jz4740_dma_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct jz4740_dmaengine_chan *chan;
|
||||
struct jz4740_dma_dev *dmadev;
|
||||
struct dma_device *dd;
|
||||
unsigned int i;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
int irq;
|
||||
|
||||
dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
|
||||
if (!dmadev)
|
||||
return -EINVAL;
|
||||
|
||||
dd = &dmadev->ddev;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
dmadev->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(dmadev->base))
|
||||
return PTR_ERR(dmadev->base);
|
||||
|
||||
dmadev->clk = clk_get(&pdev->dev, "dma");
|
||||
if (IS_ERR(dmadev->clk))
|
||||
return PTR_ERR(dmadev->clk);
|
||||
|
||||
clk_prepare_enable(dmadev->clk);
|
||||
|
||||
dma_cap_set(DMA_SLAVE, dd->cap_mask);
|
||||
dma_cap_set(DMA_CYCLIC, dd->cap_mask);
|
||||
dd->device_alloc_chan_resources = jz4740_dma_alloc_chan_resources;
|
||||
dd->device_free_chan_resources = jz4740_dma_free_chan_resources;
|
||||
dd->device_tx_status = jz4740_dma_tx_status;
|
||||
dd->device_issue_pending = jz4740_dma_issue_pending;
|
||||
dd->device_prep_slave_sg = jz4740_dma_prep_slave_sg;
|
||||
dd->device_prep_dma_cyclic = jz4740_dma_prep_dma_cyclic;
|
||||
dd->device_control = jz4740_dma_control;
|
||||
dd->dev = &pdev->dev;
|
||||
dd->chancnt = JZ_DMA_NR_CHANS;
|
||||
INIT_LIST_HEAD(&dd->channels);
|
||||
|
||||
for (i = 0; i < dd->chancnt; i++) {
|
||||
chan = &dmadev->chan[i];
|
||||
chan->id = i;
|
||||
chan->vchan.desc_free = jz4740_dma_desc_free;
|
||||
vchan_init(&chan->vchan, dd);
|
||||
}
|
||||
|
||||
ret = dma_async_device_register(dd);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
ret = request_irq(irq, jz4740_dma_irq, 0, dev_name(&pdev->dev), dmadev);
|
||||
if (ret)
|
||||
goto err_unregister;
|
||||
|
||||
platform_set_drvdata(pdev, dmadev);
|
||||
|
||||
return 0;
|
||||
|
||||
err_unregister:
|
||||
dma_async_device_unregister(dd);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int jz4740_dma_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct jz4740_dma_dev *dmadev = platform_get_drvdata(pdev);
|
||||
int irq = platform_get_irq(pdev, 0);
|
||||
|
||||
free_irq(irq, dmadev);
|
||||
dma_async_device_unregister(&dmadev->ddev);
|
||||
clk_disable_unprepare(dmadev->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver jz4740_dma_driver = {
|
||||
.probe = jz4740_dma_probe,
|
||||
.remove = jz4740_dma_remove,
|
||||
.driver = {
|
||||
.name = "jz4740-dma",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
module_platform_driver(jz4740_dma_driver);
|
||||
|
||||
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
|
||||
MODULE_DESCRIPTION("JZ4740 DMA driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
1165
drivers/dma/dmaengine.c
Normal file
1165
drivers/dma/dmaengine.c
Normal file
File diff suppressed because it is too large
Load diff
89
drivers/dma/dmaengine.h
Normal file
89
drivers/dma/dmaengine.h
Normal file
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* The contents of this file are private to DMA engine drivers, and is not
|
||||
* part of the API to be used by DMA engine users.
|
||||
*/
|
||||
#ifndef DMAENGINE_H
|
||||
#define DMAENGINE_H
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/dmaengine.h>
|
||||
|
||||
/**
|
||||
* dma_cookie_init - initialize the cookies for a DMA channel
|
||||
* @chan: dma channel to initialize
|
||||
*/
|
||||
static inline void dma_cookie_init(struct dma_chan *chan)
|
||||
{
|
||||
chan->cookie = DMA_MIN_COOKIE;
|
||||
chan->completed_cookie = DMA_MIN_COOKIE;
|
||||
}
|
||||
|
||||
/**
|
||||
* dma_cookie_assign - assign a DMA engine cookie to the descriptor
|
||||
* @tx: descriptor needing cookie
|
||||
*
|
||||
* Assign a unique non-zero per-channel cookie to the descriptor.
|
||||
* Note: caller is expected to hold a lock to prevent concurrency.
|
||||
*/
|
||||
static inline dma_cookie_t dma_cookie_assign(struct dma_async_tx_descriptor *tx)
|
||||
{
|
||||
struct dma_chan *chan = tx->chan;
|
||||
dma_cookie_t cookie;
|
||||
|
||||
cookie = chan->cookie + 1;
|
||||
if (cookie < DMA_MIN_COOKIE)
|
||||
cookie = DMA_MIN_COOKIE;
|
||||
tx->cookie = chan->cookie = cookie;
|
||||
|
||||
return cookie;
|
||||
}
|
||||
|
||||
/**
|
||||
* dma_cookie_complete - complete a descriptor
|
||||
* @tx: descriptor to complete
|
||||
*
|
||||
* Mark this descriptor complete by updating the channels completed
|
||||
* cookie marker. Zero the descriptors cookie to prevent accidental
|
||||
* repeated completions.
|
||||
*
|
||||
* Note: caller is expected to hold a lock to prevent concurrency.
|
||||
*/
|
||||
static inline void dma_cookie_complete(struct dma_async_tx_descriptor *tx)
|
||||
{
|
||||
BUG_ON(tx->cookie < DMA_MIN_COOKIE);
|
||||
tx->chan->completed_cookie = tx->cookie;
|
||||
tx->cookie = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* dma_cookie_status - report cookie status
|
||||
* @chan: dma channel
|
||||
* @cookie: cookie we are interested in
|
||||
* @state: dma_tx_state structure to return last/used cookies
|
||||
*
|
||||
* Report the status of the cookie, filling in the state structure if
|
||||
* non-NULL. No locking is required.
|
||||
*/
|
||||
static inline enum dma_status dma_cookie_status(struct dma_chan *chan,
|
||||
dma_cookie_t cookie, struct dma_tx_state *state)
|
||||
{
|
||||
dma_cookie_t used, complete;
|
||||
|
||||
used = chan->cookie;
|
||||
complete = chan->completed_cookie;
|
||||
barrier();
|
||||
if (state) {
|
||||
state->last = complete;
|
||||
state->used = used;
|
||||
state->residue = 0;
|
||||
}
|
||||
return dma_async_is_complete(cookie, complete, used);
|
||||
}
|
||||
|
||||
static inline void dma_set_residue(struct dma_tx_state *state, u32 residue)
|
||||
{
|
||||
if (state)
|
||||
state->residue = residue;
|
||||
}
|
||||
|
||||
#endif
|
||||
986
drivers/dma/dmatest.c
Normal file
986
drivers/dma/dmatest.c
Normal file
|
|
@ -0,0 +1,986 @@
|
|||
/*
|
||||
* DMA Engine test module
|
||||
*
|
||||
* Copyright (C) 2007 Atmel Corporation
|
||||
* Copyright (C) 2013 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/freezer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kthread.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/random.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/wait.h>
|
||||
|
||||
static unsigned int test_buf_size = 16384;
|
||||
module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
|
||||
MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
|
||||
|
||||
static char test_channel[20];
|
||||
module_param_string(channel, test_channel, sizeof(test_channel),
|
||||
S_IRUGO | S_IWUSR);
|
||||
MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
|
||||
|
||||
static char test_device[32];
|
||||
module_param_string(device, test_device, sizeof(test_device),
|
||||
S_IRUGO | S_IWUSR);
|
||||
MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
|
||||
|
||||
static unsigned int threads_per_chan = 1;
|
||||
module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR);
|
||||
MODULE_PARM_DESC(threads_per_chan,
|
||||
"Number of threads to start per channel (default: 1)");
|
||||
|
||||
static unsigned int max_channels;
|
||||
module_param(max_channels, uint, S_IRUGO | S_IWUSR);
|
||||
MODULE_PARM_DESC(max_channels,
|
||||
"Maximum number of channels to use (default: all)");
|
||||
|
||||
static unsigned int iterations;
|
||||
module_param(iterations, uint, S_IRUGO | S_IWUSR);
|
||||
MODULE_PARM_DESC(iterations,
|
||||
"Iterations before stopping test (default: infinite)");
|
||||
|
||||
static unsigned int xor_sources = 3;
|
||||
module_param(xor_sources, uint, S_IRUGO | S_IWUSR);
|
||||
MODULE_PARM_DESC(xor_sources,
|
||||
"Number of xor source buffers (default: 3)");
|
||||
|
||||
static unsigned int pq_sources = 3;
|
||||
module_param(pq_sources, uint, S_IRUGO | S_IWUSR);
|
||||
MODULE_PARM_DESC(pq_sources,
|
||||
"Number of p+q source buffers (default: 3)");
|
||||
|
||||
static int timeout = 3000;
|
||||
module_param(timeout, uint, S_IRUGO | S_IWUSR);
|
||||
MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
|
||||
"Pass -1 for infinite timeout");
|
||||
|
||||
static bool noverify;
|
||||
module_param(noverify, bool, S_IRUGO | S_IWUSR);
|
||||
MODULE_PARM_DESC(noverify, "Disable random data setup and verification");
|
||||
|
||||
static bool verbose;
|
||||
module_param(verbose, bool, S_IRUGO | S_IWUSR);
|
||||
MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
|
||||
|
||||
/**
|
||||
* struct dmatest_params - test parameters.
|
||||
* @buf_size: size of the memcpy test buffer
|
||||
* @channel: bus ID of the channel to test
|
||||
* @device: bus ID of the DMA Engine to test
|
||||
* @threads_per_chan: number of threads to start per channel
|
||||
* @max_channels: maximum number of channels to use
|
||||
* @iterations: iterations before stopping test
|
||||
* @xor_sources: number of xor source buffers
|
||||
* @pq_sources: number of p+q source buffers
|
||||
* @timeout: transfer timeout in msec, -1 for infinite timeout
|
||||
*/
|
||||
struct dmatest_params {
|
||||
unsigned int buf_size;
|
||||
char channel[20];
|
||||
char device[32];
|
||||
unsigned int threads_per_chan;
|
||||
unsigned int max_channels;
|
||||
unsigned int iterations;
|
||||
unsigned int xor_sources;
|
||||
unsigned int pq_sources;
|
||||
int timeout;
|
||||
bool noverify;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct dmatest_info - test information.
|
||||
* @params: test parameters
|
||||
* @lock: access protection to the fields of this structure
|
||||
*/
|
||||
static struct dmatest_info {
|
||||
/* Test parameters */
|
||||
struct dmatest_params params;
|
||||
|
||||
/* Internal state */
|
||||
struct list_head channels;
|
||||
unsigned int nr_channels;
|
||||
struct mutex lock;
|
||||
bool did_init;
|
||||
} test_info = {
|
||||
.channels = LIST_HEAD_INIT(test_info.channels),
|
||||
.lock = __MUTEX_INITIALIZER(test_info.lock),
|
||||
};
|
||||
|
||||
static int dmatest_run_set(const char *val, const struct kernel_param *kp);
|
||||
static int dmatest_run_get(char *val, const struct kernel_param *kp);
|
||||
static struct kernel_param_ops run_ops = {
|
||||
.set = dmatest_run_set,
|
||||
.get = dmatest_run_get,
|
||||
};
|
||||
static bool dmatest_run;
|
||||
module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR);
|
||||
MODULE_PARM_DESC(run, "Run the test (default: false)");
|
||||
|
||||
/* Maximum amount of mismatched bytes in buffer to print */
|
||||
#define MAX_ERROR_COUNT 32
|
||||
|
||||
/*
|
||||
* Initialization patterns. All bytes in the source buffer has bit 7
|
||||
* set, all bytes in the destination buffer has bit 7 cleared.
|
||||
*
|
||||
* Bit 6 is set for all bytes which are to be copied by the DMA
|
||||
* engine. Bit 5 is set for all bytes which are to be overwritten by
|
||||
* the DMA engine.
|
||||
*
|
||||
* The remaining bits are the inverse of a counter which increments by
|
||||
* one for each byte address.
|
||||
*/
|
||||
#define PATTERN_SRC 0x80
|
||||
#define PATTERN_DST 0x00
|
||||
#define PATTERN_COPY 0x40
|
||||
#define PATTERN_OVERWRITE 0x20
|
||||
#define PATTERN_COUNT_MASK 0x1f
|
||||
|
||||
struct dmatest_thread {
|
||||
struct list_head node;
|
||||
struct dmatest_info *info;
|
||||
struct task_struct *task;
|
||||
struct dma_chan *chan;
|
||||
u8 **srcs;
|
||||
u8 **dsts;
|
||||
enum dma_transaction_type type;
|
||||
bool done;
|
||||
};
|
||||
|
||||
struct dmatest_chan {
|
||||
struct list_head node;
|
||||
struct dma_chan *chan;
|
||||
struct list_head threads;
|
||||
};
|
||||
|
||||
static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
|
||||
static bool wait;
|
||||
|
||||
static bool is_threaded_test_run(struct dmatest_info *info)
|
||||
{
|
||||
struct dmatest_chan *dtc;
|
||||
|
||||
list_for_each_entry(dtc, &info->channels, node) {
|
||||
struct dmatest_thread *thread;
|
||||
|
||||
list_for_each_entry(thread, &dtc->threads, node) {
|
||||
if (!thread->done)
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int dmatest_wait_get(char *val, const struct kernel_param *kp)
|
||||
{
|
||||
struct dmatest_info *info = &test_info;
|
||||
struct dmatest_params *params = &info->params;
|
||||
|
||||
if (params->iterations)
|
||||
wait_event(thread_wait, !is_threaded_test_run(info));
|
||||
wait = true;
|
||||
return param_get_bool(val, kp);
|
||||
}
|
||||
|
||||
static struct kernel_param_ops wait_ops = {
|
||||
.get = dmatest_wait_get,
|
||||
.set = param_set_bool,
|
||||
};
|
||||
module_param_cb(wait, &wait_ops, &wait, S_IRUGO);
|
||||
MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
|
||||
|
||||
static bool dmatest_match_channel(struct dmatest_params *params,
|
||||
struct dma_chan *chan)
|
||||
{
|
||||
if (params->channel[0] == '\0')
|
||||
return true;
|
||||
return strcmp(dma_chan_name(chan), params->channel) == 0;
|
||||
}
|
||||
|
||||
static bool dmatest_match_device(struct dmatest_params *params,
|
||||
struct dma_device *device)
|
||||
{
|
||||
if (params->device[0] == '\0')
|
||||
return true;
|
||||
return strcmp(dev_name(device->dev), params->device) == 0;
|
||||
}
|
||||
|
||||
static unsigned long dmatest_random(void)
|
||||
{
|
||||
unsigned long buf;
|
||||
|
||||
prandom_bytes(&buf, sizeof(buf));
|
||||
return buf;
|
||||
}
|
||||
|
||||
static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
|
||||
unsigned int buf_size)
|
||||
{
|
||||
unsigned int i;
|
||||
u8 *buf;
|
||||
|
||||
for (; (buf = *bufs); bufs++) {
|
||||
for (i = 0; i < start; i++)
|
||||
buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
|
||||
for ( ; i < start + len; i++)
|
||||
buf[i] = PATTERN_SRC | PATTERN_COPY
|
||||
| (~i & PATTERN_COUNT_MASK);
|
||||
for ( ; i < buf_size; i++)
|
||||
buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
|
||||
buf++;
|
||||
}
|
||||
}
|
||||
|
||||
static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
|
||||
unsigned int buf_size)
|
||||
{
|
||||
unsigned int i;
|
||||
u8 *buf;
|
||||
|
||||
for (; (buf = *bufs); bufs++) {
|
||||
for (i = 0; i < start; i++)
|
||||
buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
|
||||
for ( ; i < start + len; i++)
|
||||
buf[i] = PATTERN_DST | PATTERN_OVERWRITE
|
||||
| (~i & PATTERN_COUNT_MASK);
|
||||
for ( ; i < buf_size; i++)
|
||||
buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
|
||||
unsigned int counter, bool is_srcbuf)
|
||||
{
|
||||
u8 diff = actual ^ pattern;
|
||||
u8 expected = pattern | (~counter & PATTERN_COUNT_MASK);
|
||||
const char *thread_name = current->comm;
|
||||
|
||||
if (is_srcbuf)
|
||||
pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
|
||||
thread_name, index, expected, actual);
|
||||
else if ((pattern & PATTERN_COPY)
|
||||
&& (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
|
||||
pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
|
||||
thread_name, index, expected, actual);
|
||||
else if (diff & PATTERN_SRC)
|
||||
pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
|
||||
thread_name, index, expected, actual);
|
||||
else
|
||||
pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
|
||||
thread_name, index, expected, actual);
|
||||
}
|
||||
|
||||
static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
|
||||
unsigned int end, unsigned int counter, u8 pattern,
|
||||
bool is_srcbuf)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned int error_count = 0;
|
||||
u8 actual;
|
||||
u8 expected;
|
||||
u8 *buf;
|
||||
unsigned int counter_orig = counter;
|
||||
|
||||
for (; (buf = *bufs); bufs++) {
|
||||
counter = counter_orig;
|
||||
for (i = start; i < end; i++) {
|
||||
actual = buf[i];
|
||||
expected = pattern | (~counter & PATTERN_COUNT_MASK);
|
||||
if (actual != expected) {
|
||||
if (error_count < MAX_ERROR_COUNT)
|
||||
dmatest_mismatch(actual, pattern, i,
|
||||
counter, is_srcbuf);
|
||||
error_count++;
|
||||
}
|
||||
counter++;
|
||||
}
|
||||
}
|
||||
|
||||
if (error_count > MAX_ERROR_COUNT)
|
||||
pr_warn("%s: %u errors suppressed\n",
|
||||
current->comm, error_count - MAX_ERROR_COUNT);
|
||||
|
||||
return error_count;
|
||||
}
|
||||
|
||||
/* poor man's completion - we want to use wait_event_freezable() on it */
|
||||
struct dmatest_done {
|
||||
bool done;
|
||||
wait_queue_head_t *wait;
|
||||
};
|
||||
|
||||
static void dmatest_callback(void *arg)
|
||||
{
|
||||
struct dmatest_done *done = arg;
|
||||
|
||||
done->done = true;
|
||||
wake_up_all(done->wait);
|
||||
}
|
||||
|
||||
static unsigned int min_odd(unsigned int x, unsigned int y)
|
||||
{
|
||||
unsigned int val = min(x, y);
|
||||
|
||||
return val % 2 ? val : val - 1;
|
||||
}
|
||||
|
||||
static void result(const char *err, unsigned int n, unsigned int src_off,
|
||||
unsigned int dst_off, unsigned int len, unsigned long data)
|
||||
{
|
||||
pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
|
||||
current->comm, n, err, src_off, dst_off, len, data);
|
||||
}
|
||||
|
||||
static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
|
||||
unsigned int dst_off, unsigned int len,
|
||||
unsigned long data)
|
||||
{
|
||||
pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
|
||||
current->comm, n, err, src_off, dst_off, len, data);
|
||||
}
|
||||
|
||||
#define verbose_result(err, n, src_off, dst_off, len, data) ({ \
|
||||
if (verbose) \
|
||||
result(err, n, src_off, dst_off, len, data); \
|
||||
else \
|
||||
dbg_result(err, n, src_off, dst_off, len, data); \
|
||||
})
|
||||
|
||||
static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
|
||||
{
|
||||
unsigned long long per_sec = 1000000;
|
||||
|
||||
if (runtime <= 0)
|
||||
return 0;
|
||||
|
||||
/* drop precision until runtime is 32-bits */
|
||||
while (runtime > UINT_MAX) {
|
||||
runtime >>= 1;
|
||||
per_sec <<= 1;
|
||||
}
|
||||
|
||||
per_sec *= val;
|
||||
do_div(per_sec, runtime);
|
||||
return per_sec;
|
||||
}
|
||||
|
||||
static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
|
||||
{
|
||||
return dmatest_persec(runtime, len >> 10);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function repeatedly tests DMA transfers of various lengths and
|
||||
* offsets for a given operation type until it is told to exit by
|
||||
* kthread_stop(). There may be multiple threads running this function
|
||||
* in parallel for a single channel, and there may be multiple channels
|
||||
* being tested in parallel.
|
||||
*
|
||||
* Before each test, the source and destination buffer is initialized
|
||||
* with a known pattern. This pattern is different depending on
|
||||
* whether it's in an area which is supposed to be copied or
|
||||
* overwritten, and different in the source and destination buffers.
|
||||
* So if the DMA engine doesn't copy exactly what we tell it to copy,
|
||||
* we'll notice.
|
||||
*/
|
||||
static int dmatest_func(void *data)
|
||||
{
|
||||
DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait);
|
||||
struct dmatest_thread *thread = data;
|
||||
struct dmatest_done done = { .wait = &done_wait };
|
||||
struct dmatest_info *info;
|
||||
struct dmatest_params *params;
|
||||
struct dma_chan *chan;
|
||||
struct dma_device *dev;
|
||||
unsigned int src_off, dst_off, len;
|
||||
unsigned int error_count;
|
||||
unsigned int failed_tests = 0;
|
||||
unsigned int total_tests = 0;
|
||||
dma_cookie_t cookie;
|
||||
enum dma_status status;
|
||||
enum dma_ctrl_flags flags;
|
||||
u8 *pq_coefs = NULL;
|
||||
int ret;
|
||||
int src_cnt;
|
||||
int dst_cnt;
|
||||
int i;
|
||||
ktime_t ktime;
|
||||
s64 runtime = 0;
|
||||
unsigned long long total_len = 0;
|
||||
|
||||
set_freezable();
|
||||
|
||||
ret = -ENOMEM;
|
||||
|
||||
smp_rmb();
|
||||
info = thread->info;
|
||||
params = &info->params;
|
||||
chan = thread->chan;
|
||||
dev = chan->device;
|
||||
if (thread->type == DMA_MEMCPY)
|
||||
src_cnt = dst_cnt = 1;
|
||||
else if (thread->type == DMA_XOR) {
|
||||
/* force odd to ensure dst = src */
|
||||
src_cnt = min_odd(params->xor_sources | 1, dev->max_xor);
|
||||
dst_cnt = 1;
|
||||
} else if (thread->type == DMA_PQ) {
|
||||
/* force odd to ensure dst = src */
|
||||
src_cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
|
||||
dst_cnt = 2;
|
||||
|
||||
pq_coefs = kmalloc(params->pq_sources+1, GFP_KERNEL);
|
||||
if (!pq_coefs)
|
||||
goto err_thread_type;
|
||||
|
||||
for (i = 0; i < src_cnt; i++)
|
||||
pq_coefs[i] = 1;
|
||||
} else
|
||||
goto err_thread_type;
|
||||
|
||||
thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL);
|
||||
if (!thread->srcs)
|
||||
goto err_srcs;
|
||||
for (i = 0; i < src_cnt; i++) {
|
||||
thread->srcs[i] = kmalloc(params->buf_size, GFP_KERNEL);
|
||||
if (!thread->srcs[i])
|
||||
goto err_srcbuf;
|
||||
}
|
||||
thread->srcs[i] = NULL;
|
||||
|
||||
thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL);
|
||||
if (!thread->dsts)
|
||||
goto err_dsts;
|
||||
for (i = 0; i < dst_cnt; i++) {
|
||||
thread->dsts[i] = kmalloc(params->buf_size, GFP_KERNEL);
|
||||
if (!thread->dsts[i])
|
||||
goto err_dstbuf;
|
||||
}
|
||||
thread->dsts[i] = NULL;
|
||||
|
||||
set_user_nice(current, 10);
|
||||
|
||||
/*
|
||||
* src and dst buffers are freed by ourselves below
|
||||
*/
|
||||
flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
|
||||
|
||||
ktime = ktime_get();
|
||||
while (!kthread_should_stop()
|
||||
&& !(params->iterations && total_tests >= params->iterations)) {
|
||||
struct dma_async_tx_descriptor *tx = NULL;
|
||||
struct dmaengine_unmap_data *um;
|
||||
dma_addr_t srcs[src_cnt];
|
||||
dma_addr_t *dsts;
|
||||
u8 align = 0;
|
||||
|
||||
total_tests++;
|
||||
|
||||
/* honor alignment restrictions */
|
||||
if (thread->type == DMA_MEMCPY)
|
||||
align = dev->copy_align;
|
||||
else if (thread->type == DMA_XOR)
|
||||
align = dev->xor_align;
|
||||
else if (thread->type == DMA_PQ)
|
||||
align = dev->pq_align;
|
||||
|
||||
if (1 << align > params->buf_size) {
|
||||
pr_err("%u-byte buffer too small for %d-byte alignment\n",
|
||||
params->buf_size, 1 << align);
|
||||
break;
|
||||
}
|
||||
|
||||
if (params->noverify) {
|
||||
len = params->buf_size;
|
||||
src_off = 0;
|
||||
dst_off = 0;
|
||||
} else {
|
||||
len = dmatest_random() % params->buf_size + 1;
|
||||
len = (len >> align) << align;
|
||||
if (!len)
|
||||
len = 1 << align;
|
||||
src_off = dmatest_random() % (params->buf_size - len + 1);
|
||||
dst_off = dmatest_random() % (params->buf_size - len + 1);
|
||||
|
||||
src_off = (src_off >> align) << align;
|
||||
dst_off = (dst_off >> align) << align;
|
||||
|
||||
dmatest_init_srcs(thread->srcs, src_off, len,
|
||||
params->buf_size);
|
||||
dmatest_init_dsts(thread->dsts, dst_off, len,
|
||||
params->buf_size);
|
||||
}
|
||||
|
||||
len = (len >> align) << align;
|
||||
if (!len)
|
||||
len = 1 << align;
|
||||
total_len += len;
|
||||
|
||||
um = dmaengine_get_unmap_data(dev->dev, src_cnt+dst_cnt,
|
||||
GFP_KERNEL);
|
||||
if (!um) {
|
||||
failed_tests++;
|
||||
result("unmap data NULL", total_tests,
|
||||
src_off, dst_off, len, ret);
|
||||
continue;
|
||||
}
|
||||
|
||||
um->len = params->buf_size;
|
||||
for (i = 0; i < src_cnt; i++) {
|
||||
void *buf = thread->srcs[i];
|
||||
struct page *pg = virt_to_page(buf);
|
||||
unsigned pg_off = (unsigned long) buf & ~PAGE_MASK;
|
||||
|
||||
um->addr[i] = dma_map_page(dev->dev, pg, pg_off,
|
||||
um->len, DMA_TO_DEVICE);
|
||||
srcs[i] = um->addr[i] + src_off;
|
||||
ret = dma_mapping_error(dev->dev, um->addr[i]);
|
||||
if (ret) {
|
||||
dmaengine_unmap_put(um);
|
||||
result("src mapping error", total_tests,
|
||||
src_off, dst_off, len, ret);
|
||||
failed_tests++;
|
||||
continue;
|
||||
}
|
||||
um->to_cnt++;
|
||||
}
|
||||
/* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
|
||||
dsts = &um->addr[src_cnt];
|
||||
for (i = 0; i < dst_cnt; i++) {
|
||||
void *buf = thread->dsts[i];
|
||||
struct page *pg = virt_to_page(buf);
|
||||
unsigned pg_off = (unsigned long) buf & ~PAGE_MASK;
|
||||
|
||||
dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len,
|
||||
DMA_BIDIRECTIONAL);
|
||||
ret = dma_mapping_error(dev->dev, dsts[i]);
|
||||
if (ret) {
|
||||
dmaengine_unmap_put(um);
|
||||
result("dst mapping error", total_tests,
|
||||
src_off, dst_off, len, ret);
|
||||
failed_tests++;
|
||||
continue;
|
||||
}
|
||||
um->bidi_cnt++;
|
||||
}
|
||||
|
||||
if (thread->type == DMA_MEMCPY)
|
||||
tx = dev->device_prep_dma_memcpy(chan,
|
||||
dsts[0] + dst_off,
|
||||
srcs[0], len, flags);
|
||||
else if (thread->type == DMA_XOR)
|
||||
tx = dev->device_prep_dma_xor(chan,
|
||||
dsts[0] + dst_off,
|
||||
srcs, src_cnt,
|
||||
len, flags);
|
||||
else if (thread->type == DMA_PQ) {
|
||||
dma_addr_t dma_pq[dst_cnt];
|
||||
|
||||
for (i = 0; i < dst_cnt; i++)
|
||||
dma_pq[i] = dsts[i] + dst_off;
|
||||
tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
|
||||
src_cnt, pq_coefs,
|
||||
len, flags);
|
||||
}
|
||||
|
||||
if (!tx) {
|
||||
dmaengine_unmap_put(um);
|
||||
result("prep error", total_tests, src_off,
|
||||
dst_off, len, ret);
|
||||
msleep(100);
|
||||
failed_tests++;
|
||||
continue;
|
||||
}
|
||||
|
||||
done.done = false;
|
||||
tx->callback = dmatest_callback;
|
||||
tx->callback_param = &done;
|
||||
cookie = tx->tx_submit(tx);
|
||||
|
||||
if (dma_submit_error(cookie)) {
|
||||
dmaengine_unmap_put(um);
|
||||
result("submit error", total_tests, src_off,
|
||||
dst_off, len, ret);
|
||||
msleep(100);
|
||||
failed_tests++;
|
||||
continue;
|
||||
}
|
||||
dma_async_issue_pending(chan);
|
||||
|
||||
wait_event_freezable_timeout(done_wait, done.done,
|
||||
msecs_to_jiffies(params->timeout));
|
||||
|
||||
status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
|
||||
|
||||
if (!done.done) {
|
||||
/*
|
||||
* We're leaving the timed out dma operation with
|
||||
* dangling pointer to done_wait. To make this
|
||||
* correct, we'll need to allocate wait_done for
|
||||
* each test iteration and perform "who's gonna
|
||||
* free it this time?" dancing. For now, just
|
||||
* leave it dangling.
|
||||
*/
|
||||
dmaengine_unmap_put(um);
|
||||
result("test timed out", total_tests, src_off, dst_off,
|
||||
len, 0);
|
||||
failed_tests++;
|
||||
continue;
|
||||
} else if (status != DMA_COMPLETE) {
|
||||
dmaengine_unmap_put(um);
|
||||
result(status == DMA_ERROR ?
|
||||
"completion error status" :
|
||||
"completion busy status", total_tests, src_off,
|
||||
dst_off, len, ret);
|
||||
failed_tests++;
|
||||
continue;
|
||||
}
|
||||
|
||||
dmaengine_unmap_put(um);
|
||||
|
||||
if (params->noverify) {
|
||||
verbose_result("test passed", total_tests, src_off,
|
||||
dst_off, len, 0);
|
||||
continue;
|
||||
}
|
||||
|
||||
pr_debug("%s: verifying source buffer...\n", current->comm);
|
||||
error_count = dmatest_verify(thread->srcs, 0, src_off,
|
||||
0, PATTERN_SRC, true);
|
||||
error_count += dmatest_verify(thread->srcs, src_off,
|
||||
src_off + len, src_off,
|
||||
PATTERN_SRC | PATTERN_COPY, true);
|
||||
error_count += dmatest_verify(thread->srcs, src_off + len,
|
||||
params->buf_size, src_off + len,
|
||||
PATTERN_SRC, true);
|
||||
|
||||
pr_debug("%s: verifying dest buffer...\n", current->comm);
|
||||
error_count += dmatest_verify(thread->dsts, 0, dst_off,
|
||||
0, PATTERN_DST, false);
|
||||
error_count += dmatest_verify(thread->dsts, dst_off,
|
||||
dst_off + len, src_off,
|
||||
PATTERN_SRC | PATTERN_COPY, false);
|
||||
error_count += dmatest_verify(thread->dsts, dst_off + len,
|
||||
params->buf_size, dst_off + len,
|
||||
PATTERN_DST, false);
|
||||
|
||||
if (error_count) {
|
||||
result("data error", total_tests, src_off, dst_off,
|
||||
len, error_count);
|
||||
failed_tests++;
|
||||
} else {
|
||||
verbose_result("test passed", total_tests, src_off,
|
||||
dst_off, len, 0);
|
||||
}
|
||||
}
|
||||
runtime = ktime_us_delta(ktime_get(), ktime);
|
||||
|
||||
ret = 0;
|
||||
err_dstbuf:
|
||||
for (i = 0; thread->dsts[i]; i++)
|
||||
kfree(thread->dsts[i]);
|
||||
kfree(thread->dsts);
|
||||
err_dsts:
|
||||
err_srcbuf:
|
||||
for (i = 0; thread->srcs[i]; i++)
|
||||
kfree(thread->srcs[i]);
|
||||
kfree(thread->srcs);
|
||||
err_srcs:
|
||||
kfree(pq_coefs);
|
||||
err_thread_type:
|
||||
pr_info("%s: summary %u tests, %u failures %llu iops %llu KB/s (%d)\n",
|
||||
current->comm, total_tests, failed_tests,
|
||||
dmatest_persec(runtime, total_tests),
|
||||
dmatest_KBs(runtime, total_len), ret);
|
||||
|
||||
/* terminate all transfers on specified channels */
|
||||
if (ret)
|
||||
dmaengine_terminate_all(chan);
|
||||
|
||||
thread->done = true;
|
||||
wake_up(&thread_wait);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
|
||||
{
|
||||
struct dmatest_thread *thread;
|
||||
struct dmatest_thread *_thread;
|
||||
int ret;
|
||||
|
||||
list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
|
||||
ret = kthread_stop(thread->task);
|
||||
pr_debug("thread %s exited with status %d\n",
|
||||
thread->task->comm, ret);
|
||||
list_del(&thread->node);
|
||||
put_task_struct(thread->task);
|
||||
kfree(thread);
|
||||
}
|
||||
|
||||
/* terminate all transfers on specified channels */
|
||||
dmaengine_terminate_all(dtc->chan);
|
||||
|
||||
kfree(dtc);
|
||||
}
|
||||
|
||||
static int dmatest_add_threads(struct dmatest_info *info,
|
||||
struct dmatest_chan *dtc, enum dma_transaction_type type)
|
||||
{
|
||||
struct dmatest_params *params = &info->params;
|
||||
struct dmatest_thread *thread;
|
||||
struct dma_chan *chan = dtc->chan;
|
||||
char *op;
|
||||
unsigned int i;
|
||||
|
||||
if (type == DMA_MEMCPY)
|
||||
op = "copy";
|
||||
else if (type == DMA_XOR)
|
||||
op = "xor";
|
||||
else if (type == DMA_PQ)
|
||||
op = "pq";
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < params->threads_per_chan; i++) {
|
||||
thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
|
||||
if (!thread) {
|
||||
pr_warn("No memory for %s-%s%u\n",
|
||||
dma_chan_name(chan), op, i);
|
||||
break;
|
||||
}
|
||||
thread->info = info;
|
||||
thread->chan = dtc->chan;
|
||||
thread->type = type;
|
||||
smp_wmb();
|
||||
thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
|
||||
dma_chan_name(chan), op, i);
|
||||
if (IS_ERR(thread->task)) {
|
||||
pr_warn("Failed to create thread %s-%s%u\n",
|
||||
dma_chan_name(chan), op, i);
|
||||
kfree(thread);
|
||||
break;
|
||||
}
|
||||
|
||||
/* srcbuf and dstbuf are allocated by the thread itself */
|
||||
get_task_struct(thread->task);
|
||||
list_add_tail(&thread->node, &dtc->threads);
|
||||
wake_up_process(thread->task);
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
static int dmatest_add_channel(struct dmatest_info *info,
|
||||
struct dma_chan *chan)
|
||||
{
|
||||
struct dmatest_chan *dtc;
|
||||
struct dma_device *dma_dev = chan->device;
|
||||
unsigned int thread_count = 0;
|
||||
int cnt;
|
||||
|
||||
dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
|
||||
if (!dtc) {
|
||||
pr_warn("No memory for %s\n", dma_chan_name(chan));
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dtc->chan = chan;
|
||||
INIT_LIST_HEAD(&dtc->threads);
|
||||
|
||||
if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
|
||||
cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
|
||||
thread_count += cnt > 0 ? cnt : 0;
|
||||
}
|
||||
if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
|
||||
cnt = dmatest_add_threads(info, dtc, DMA_XOR);
|
||||
thread_count += cnt > 0 ? cnt : 0;
|
||||
}
|
||||
if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
|
||||
cnt = dmatest_add_threads(info, dtc, DMA_PQ);
|
||||
thread_count += cnt > 0 ? cnt : 0;
|
||||
}
|
||||
|
||||
pr_info("Started %u threads using %s\n",
|
||||
thread_count, dma_chan_name(chan));
|
||||
|
||||
list_add_tail(&dtc->node, &info->channels);
|
||||
info->nr_channels++;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool filter(struct dma_chan *chan, void *param)
|
||||
{
|
||||
struct dmatest_params *params = param;
|
||||
|
||||
if (!dmatest_match_channel(params, chan) ||
|
||||
!dmatest_match_device(params, chan->device))
|
||||
return false;
|
||||
else
|
||||
return true;
|
||||
}
|
||||
|
||||
static void request_channels(struct dmatest_info *info,
|
||||
enum dma_transaction_type type)
|
||||
{
|
||||
dma_cap_mask_t mask;
|
||||
|
||||
dma_cap_zero(mask);
|
||||
dma_cap_set(type, mask);
|
||||
for (;;) {
|
||||
struct dmatest_params *params = &info->params;
|
||||
struct dma_chan *chan;
|
||||
|
||||
chan = dma_request_channel(mask, filter, params);
|
||||
if (chan) {
|
||||
if (dmatest_add_channel(info, chan)) {
|
||||
dma_release_channel(chan);
|
||||
break; /* add_channel failed, punt */
|
||||
}
|
||||
} else
|
||||
break; /* no more channels available */
|
||||
if (params->max_channels &&
|
||||
info->nr_channels >= params->max_channels)
|
||||
break; /* we have all we need */
|
||||
}
|
||||
}
|
||||
|
||||
static void run_threaded_test(struct dmatest_info *info)
|
||||
{
|
||||
struct dmatest_params *params = &info->params;
|
||||
|
||||
/* Copy test parameters */
|
||||
params->buf_size = test_buf_size;
|
||||
strlcpy(params->channel, strim(test_channel), sizeof(params->channel));
|
||||
strlcpy(params->device, strim(test_device), sizeof(params->device));
|
||||
params->threads_per_chan = threads_per_chan;
|
||||
params->max_channels = max_channels;
|
||||
params->iterations = iterations;
|
||||
params->xor_sources = xor_sources;
|
||||
params->pq_sources = pq_sources;
|
||||
params->timeout = timeout;
|
||||
params->noverify = noverify;
|
||||
|
||||
request_channels(info, DMA_MEMCPY);
|
||||
request_channels(info, DMA_XOR);
|
||||
request_channels(info, DMA_PQ);
|
||||
}
|
||||
|
||||
static void stop_threaded_test(struct dmatest_info *info)
|
||||
{
|
||||
struct dmatest_chan *dtc, *_dtc;
|
||||
struct dma_chan *chan;
|
||||
|
||||
list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
|
||||
list_del(&dtc->node);
|
||||
chan = dtc->chan;
|
||||
dmatest_cleanup_channel(dtc);
|
||||
pr_debug("dropped channel %s\n", dma_chan_name(chan));
|
||||
dma_release_channel(chan);
|
||||
}
|
||||
|
||||
info->nr_channels = 0;
|
||||
}
|
||||
|
||||
static void restart_threaded_test(struct dmatest_info *info, bool run)
|
||||
{
|
||||
/* we might be called early to set run=, defer running until all
|
||||
* parameters have been evaluated
|
||||
*/
|
||||
if (!info->did_init)
|
||||
return;
|
||||
|
||||
/* Stop any running test first */
|
||||
stop_threaded_test(info);
|
||||
|
||||
/* Run test with new parameters */
|
||||
run_threaded_test(info);
|
||||
}
|
||||
|
||||
static int dmatest_run_get(char *val, const struct kernel_param *kp)
|
||||
{
|
||||
struct dmatest_info *info = &test_info;
|
||||
|
||||
mutex_lock(&info->lock);
|
||||
if (is_threaded_test_run(info)) {
|
||||
dmatest_run = true;
|
||||
} else {
|
||||
stop_threaded_test(info);
|
||||
dmatest_run = false;
|
||||
}
|
||||
mutex_unlock(&info->lock);
|
||||
|
||||
return param_get_bool(val, kp);
|
||||
}
|
||||
|
||||
static int dmatest_run_set(const char *val, const struct kernel_param *kp)
|
||||
{
|
||||
struct dmatest_info *info = &test_info;
|
||||
int ret;
|
||||
|
||||
mutex_lock(&info->lock);
|
||||
ret = param_set_bool(val, kp);
|
||||
if (ret) {
|
||||
mutex_unlock(&info->lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (is_threaded_test_run(info))
|
||||
ret = -EBUSY;
|
||||
else if (dmatest_run)
|
||||
restart_threaded_test(info, dmatest_run);
|
||||
|
||||
mutex_unlock(&info->lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init dmatest_init(void)
|
||||
{
|
||||
struct dmatest_info *info = &test_info;
|
||||
struct dmatest_params *params = &info->params;
|
||||
|
||||
if (dmatest_run) {
|
||||
mutex_lock(&info->lock);
|
||||
run_threaded_test(info);
|
||||
mutex_unlock(&info->lock);
|
||||
}
|
||||
|
||||
if (params->iterations && wait)
|
||||
wait_event(thread_wait, !is_threaded_test_run(info));
|
||||
|
||||
/* module parameters are stable, inittime tests are started,
|
||||
* let userspace take over 'run' control
|
||||
*/
|
||||
info->did_init = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
/* when compiled-in wait for drivers to load first */
|
||||
late_initcall(dmatest_init);
|
||||
|
||||
static void __exit dmatest_exit(void)
|
||||
{
|
||||
struct dmatest_info *info = &test_info;
|
||||
|
||||
mutex_lock(&info->lock);
|
||||
stop_threaded_test(info);
|
||||
mutex_unlock(&info->lock);
|
||||
}
|
||||
module_exit(dmatest_exit);
|
||||
|
||||
MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
28
drivers/dma/dw/Kconfig
Normal file
28
drivers/dma/dw/Kconfig
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
#
|
||||
# DMA engine configuration for dw
|
||||
#
|
||||
|
||||
config DW_DMAC_CORE
|
||||
tristate "Synopsys DesignWare AHB DMA support"
|
||||
select DMA_ENGINE
|
||||
|
||||
config DW_DMAC
|
||||
tristate "Synopsys DesignWare AHB DMA platform driver"
|
||||
select DW_DMAC_CORE
|
||||
select DW_DMAC_BIG_ENDIAN_IO if AVR32
|
||||
default y if CPU_AT32AP7000
|
||||
help
|
||||
Support the Synopsys DesignWare AHB DMA controller. This
|
||||
can be integrated in chips such as the Atmel AT32ap7000.
|
||||
|
||||
config DW_DMAC_PCI
|
||||
tristate "Synopsys DesignWare AHB DMA PCI driver"
|
||||
depends on PCI
|
||||
select DW_DMAC_CORE
|
||||
help
|
||||
Support the Synopsys DesignWare AHB DMA controller on the
|
||||
platfroms that enumerate it as a PCI device. For example,
|
||||
Intel Medfield has integrated this GPDMA controller.
|
||||
|
||||
config DW_DMAC_BIG_ENDIAN_IO
|
||||
bool
|
||||
8
drivers/dma/dw/Makefile
Normal file
8
drivers/dma/dw/Makefile
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
obj-$(CONFIG_DW_DMAC_CORE) += dw_dmac_core.o
|
||||
dw_dmac_core-objs := core.o
|
||||
|
||||
obj-$(CONFIG_DW_DMAC) += dw_dmac.o
|
||||
dw_dmac-objs := platform.o
|
||||
|
||||
obj-$(CONFIG_DW_DMAC_PCI) += dw_dmac_pci.o
|
||||
dw_dmac_pci-objs := pci.o
|
||||
1721
drivers/dma/dw/core.c
Normal file
1721
drivers/dma/dw/core.c
Normal file
File diff suppressed because it is too large
Load diff
23
drivers/dma/dw/internal.h
Normal file
23
drivers/dma/dw/internal.h
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Driver for the Synopsys DesignWare DMA Controller
|
||||
*
|
||||
* Copyright (C) 2013 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _DMA_DW_INTERNAL_H
|
||||
#define _DMA_DW_INTERNAL_H
|
||||
|
||||
#include <linux/dma/dw.h>
|
||||
|
||||
#include "regs.h"
|
||||
|
||||
int dw_dma_disable(struct dw_dma_chip *chip);
|
||||
int dw_dma_enable(struct dw_dma_chip *chip);
|
||||
|
||||
extern bool dw_dma_filter(struct dma_chan *chan, void *param);
|
||||
|
||||
#endif /* _DMA_DW_INTERNAL_H */
|
||||
135
drivers/dma/dw/pci.c
Normal file
135
drivers/dma/dw/pci.c
Normal file
|
|
@ -0,0 +1,135 @@
|
|||
/*
|
||||
* PCI driver for the Synopsys DesignWare DMA Controller
|
||||
*
|
||||
* Copyright (C) 2013 Intel Corporation
|
||||
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/device.h>
|
||||
|
||||
#include "internal.h"
|
||||
|
||||
static struct dw_dma_platform_data dw_pci_pdata = {
|
||||
.is_private = 1,
|
||||
.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
|
||||
.chan_priority = CHAN_PRIORITY_ASCENDING,
|
||||
};
|
||||
|
||||
static int dw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid)
|
||||
{
|
||||
struct dw_dma_chip *chip;
|
||||
struct dw_dma_platform_data *pdata = (void *)pid->driver_data;
|
||||
int ret;
|
||||
|
||||
ret = pcim_enable_device(pdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "I/O memory remapping failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pci_set_master(pdev);
|
||||
pci_try_set_mwi(pdev);
|
||||
|
||||
ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
|
||||
if (!chip)
|
||||
return -ENOMEM;
|
||||
|
||||
chip->dev = &pdev->dev;
|
||||
chip->regs = pcim_iomap_table(pdev)[0];
|
||||
chip->irq = pdev->irq;
|
||||
|
||||
ret = dw_dma_probe(chip, pdata);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pci_set_drvdata(pdev, chip);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dw_pci_remove(struct pci_dev *pdev)
|
||||
{
|
||||
struct dw_dma_chip *chip = pci_get_drvdata(pdev);
|
||||
int ret;
|
||||
|
||||
ret = dw_dma_remove(chip);
|
||||
if (ret)
|
||||
dev_warn(&pdev->dev, "can't remove device properly: %d\n", ret);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
|
||||
static int dw_pci_suspend_late(struct device *dev)
|
||||
{
|
||||
struct pci_dev *pci = to_pci_dev(dev);
|
||||
struct dw_dma_chip *chip = pci_get_drvdata(pci);
|
||||
|
||||
return dw_dma_disable(chip);
|
||||
};
|
||||
|
||||
static int dw_pci_resume_early(struct device *dev)
|
||||
{
|
||||
struct pci_dev *pci = to_pci_dev(dev);
|
||||
struct dw_dma_chip *chip = pci_get_drvdata(pci);
|
||||
|
||||
return dw_dma_enable(chip);
|
||||
};
|
||||
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
static const struct dev_pm_ops dw_pci_dev_pm_ops = {
|
||||
SET_LATE_SYSTEM_SLEEP_PM_OPS(dw_pci_suspend_late, dw_pci_resume_early)
|
||||
};
|
||||
|
||||
static const struct pci_device_id dw_pci_id_table[] = {
|
||||
/* Medfield */
|
||||
{ PCI_VDEVICE(INTEL, 0x0827), (kernel_ulong_t)&dw_pci_pdata },
|
||||
{ PCI_VDEVICE(INTEL, 0x0830), (kernel_ulong_t)&dw_pci_pdata },
|
||||
|
||||
/* BayTrail */
|
||||
{ PCI_VDEVICE(INTEL, 0x0f06), (kernel_ulong_t)&dw_pci_pdata },
|
||||
{ PCI_VDEVICE(INTEL, 0x0f40), (kernel_ulong_t)&dw_pci_pdata },
|
||||
|
||||
/* Braswell */
|
||||
{ PCI_VDEVICE(INTEL, 0x2286), (kernel_ulong_t)&dw_pci_pdata },
|
||||
{ PCI_VDEVICE(INTEL, 0x22c0), (kernel_ulong_t)&dw_pci_pdata },
|
||||
|
||||
/* Haswell */
|
||||
{ PCI_VDEVICE(INTEL, 0x9c60), (kernel_ulong_t)&dw_pci_pdata },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, dw_pci_id_table);
|
||||
|
||||
static struct pci_driver dw_pci_driver = {
|
||||
.name = "dw_dmac_pci",
|
||||
.id_table = dw_pci_id_table,
|
||||
.probe = dw_pci_probe,
|
||||
.remove = dw_pci_remove,
|
||||
.driver = {
|
||||
.pm = &dw_pci_dev_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
module_pci_driver(dw_pci_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller PCI driver");
|
||||
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
|
||||
305
drivers/dma/dw/platform.c
Normal file
305
drivers/dma/dw/platform.c
Normal file
|
|
@ -0,0 +1,305 @@
|
|||
/*
|
||||
* Platform driver for the Synopsys DesignWare DMA Controller
|
||||
*
|
||||
* Copyright (C) 2007-2008 Atmel Corporation
|
||||
* Copyright (C) 2010-2011 ST Microelectronics
|
||||
* Copyright (C) 2013 Intel Corporation
|
||||
*
|
||||
* Some parts of this driver are derived from the original dw_dmac.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_dma.h>
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/acpi_dma.h>
|
||||
|
||||
#include "internal.h"
|
||||
|
||||
#define DRV_NAME "dw_dmac"
|
||||
|
||||
static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
struct dw_dma *dw = ofdma->of_dma_data;
|
||||
struct dw_dma_slave slave = {
|
||||
.dma_dev = dw->dma.dev,
|
||||
};
|
||||
dma_cap_mask_t cap;
|
||||
|
||||
if (dma_spec->args_count != 3)
|
||||
return NULL;
|
||||
|
||||
slave.src_id = dma_spec->args[0];
|
||||
slave.dst_id = dma_spec->args[0];
|
||||
slave.src_master = dma_spec->args[1];
|
||||
slave.dst_master = dma_spec->args[2];
|
||||
|
||||
if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS ||
|
||||
slave.dst_id >= DW_DMA_MAX_NR_REQUESTS ||
|
||||
slave.src_master >= dw->nr_masters ||
|
||||
slave.dst_master >= dw->nr_masters))
|
||||
return NULL;
|
||||
|
||||
dma_cap_zero(cap);
|
||||
dma_cap_set(DMA_SLAVE, cap);
|
||||
|
||||
/* TODO: there should be a simpler way to do this */
|
||||
return dma_request_channel(cap, dw_dma_filter, &slave);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
static bool dw_dma_acpi_filter(struct dma_chan *chan, void *param)
|
||||
{
|
||||
struct acpi_dma_spec *dma_spec = param;
|
||||
struct dw_dma_slave slave = {
|
||||
.dma_dev = dma_spec->dev,
|
||||
.src_id = dma_spec->slave_id,
|
||||
.dst_id = dma_spec->slave_id,
|
||||
.src_master = 1,
|
||||
.dst_master = 0,
|
||||
};
|
||||
|
||||
return dw_dma_filter(chan, &slave);
|
||||
}
|
||||
|
||||
static void dw_dma_acpi_controller_register(struct dw_dma *dw)
|
||||
{
|
||||
struct device *dev = dw->dma.dev;
|
||||
struct acpi_dma_filter_info *info;
|
||||
int ret;
|
||||
|
||||
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
|
||||
if (!info)
|
||||
return;
|
||||
|
||||
dma_cap_zero(info->dma_cap);
|
||||
dma_cap_set(DMA_SLAVE, info->dma_cap);
|
||||
info->filter_fn = dw_dma_acpi_filter;
|
||||
|
||||
ret = devm_acpi_dma_controller_register(dev, acpi_dma_simple_xlate,
|
||||
info);
|
||||
if (ret)
|
||||
dev_err(dev, "could not register acpi_dma_controller\n");
|
||||
}
|
||||
#else /* !CONFIG_ACPI */
|
||||
static inline void dw_dma_acpi_controller_register(struct dw_dma *dw) {}
|
||||
#endif /* !CONFIG_ACPI */
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static struct dw_dma_platform_data *
|
||||
dw_dma_parse_dt(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct dw_dma_platform_data *pdata;
|
||||
u32 tmp, arr[4];
|
||||
|
||||
if (!np) {
|
||||
dev_err(&pdev->dev, "Missing DT data\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
|
||||
if (!pdata)
|
||||
return NULL;
|
||||
|
||||
if (of_property_read_u32(np, "dma-channels", &pdata->nr_channels))
|
||||
return NULL;
|
||||
|
||||
if (of_property_read_bool(np, "is_private"))
|
||||
pdata->is_private = true;
|
||||
|
||||
if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
|
||||
pdata->chan_allocation_order = (unsigned char)tmp;
|
||||
|
||||
if (!of_property_read_u32(np, "chan_priority", &tmp))
|
||||
pdata->chan_priority = tmp;
|
||||
|
||||
if (!of_property_read_u32(np, "block_size", &tmp))
|
||||
pdata->block_size = tmp;
|
||||
|
||||
if (!of_property_read_u32(np, "dma-masters", &tmp)) {
|
||||
if (tmp > 4)
|
||||
return NULL;
|
||||
|
||||
pdata->nr_masters = tmp;
|
||||
}
|
||||
|
||||
if (!of_property_read_u32_array(np, "data_width", arr,
|
||||
pdata->nr_masters))
|
||||
for (tmp = 0; tmp < pdata->nr_masters; tmp++)
|
||||
pdata->data_width[tmp] = arr[tmp];
|
||||
|
||||
return pdata;
|
||||
}
|
||||
#else
|
||||
static inline struct dw_dma_platform_data *
|
||||
dw_dma_parse_dt(struct platform_device *pdev)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int dw_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct dw_dma_chip *chip;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *mem;
|
||||
struct dw_dma_platform_data *pdata;
|
||||
int err;
|
||||
|
||||
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
|
||||
if (!chip)
|
||||
return -ENOMEM;
|
||||
|
||||
chip->irq = platform_get_irq(pdev, 0);
|
||||
if (chip->irq < 0)
|
||||
return chip->irq;
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
chip->regs = devm_ioremap_resource(dev, mem);
|
||||
if (IS_ERR(chip->regs))
|
||||
return PTR_ERR(chip->regs);
|
||||
|
||||
err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
pdata = dev_get_platdata(dev);
|
||||
if (!pdata)
|
||||
pdata = dw_dma_parse_dt(pdev);
|
||||
|
||||
chip->dev = dev;
|
||||
|
||||
chip->clk = devm_clk_get(chip->dev, "hclk");
|
||||
if (IS_ERR(chip->clk))
|
||||
return PTR_ERR(chip->clk);
|
||||
err = clk_prepare_enable(chip->clk);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = dw_dma_probe(chip, pdata);
|
||||
if (err)
|
||||
goto err_dw_dma_probe;
|
||||
|
||||
platform_set_drvdata(pdev, chip);
|
||||
|
||||
if (pdev->dev.of_node) {
|
||||
err = of_dma_controller_register(pdev->dev.of_node,
|
||||
dw_dma_of_xlate, chip->dw);
|
||||
if (err)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register of_dma_controller\n");
|
||||
}
|
||||
|
||||
if (ACPI_HANDLE(&pdev->dev))
|
||||
dw_dma_acpi_controller_register(chip->dw);
|
||||
|
||||
return 0;
|
||||
|
||||
err_dw_dma_probe:
|
||||
clk_disable_unprepare(chip->clk);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int dw_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct dw_dma_chip *chip = platform_get_drvdata(pdev);
|
||||
|
||||
if (pdev->dev.of_node)
|
||||
of_dma_controller_free(pdev->dev.of_node);
|
||||
|
||||
dw_dma_remove(chip);
|
||||
clk_disable_unprepare(chip->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dw_shutdown(struct platform_device *pdev)
|
||||
{
|
||||
struct dw_dma_chip *chip = platform_get_drvdata(pdev);
|
||||
|
||||
dw_dma_disable(chip);
|
||||
clk_disable_unprepare(chip->clk);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id dw_dma_of_id_table[] = {
|
||||
{ .compatible = "snps,dma-spear1340" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
static const struct acpi_device_id dw_dma_acpi_id_table[] = {
|
||||
{ "INTL9C60", 0 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, dw_dma_acpi_id_table);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
|
||||
static int dw_suspend_late(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct dw_dma_chip *chip = platform_get_drvdata(pdev);
|
||||
|
||||
dw_dma_disable(chip);
|
||||
clk_disable_unprepare(chip->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dw_resume_early(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct dw_dma_chip *chip = platform_get_drvdata(pdev);
|
||||
|
||||
clk_prepare_enable(chip->clk);
|
||||
return dw_dma_enable(chip);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
static const struct dev_pm_ops dw_dev_pm_ops = {
|
||||
SET_LATE_SYSTEM_SLEEP_PM_OPS(dw_suspend_late, dw_resume_early)
|
||||
};
|
||||
|
||||
static struct platform_driver dw_driver = {
|
||||
.probe = dw_probe,
|
||||
.remove = dw_remove,
|
||||
.shutdown = dw_shutdown,
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.pm = &dw_dev_pm_ops,
|
||||
.of_match_table = of_match_ptr(dw_dma_of_id_table),
|
||||
.acpi_match_table = ACPI_PTR(dw_dma_acpi_id_table),
|
||||
},
|
||||
};
|
||||
|
||||
static int __init dw_init(void)
|
||||
{
|
||||
return platform_driver_register(&dw_driver);
|
||||
}
|
||||
subsys_initcall(dw_init);
|
||||
|
||||
static void __exit dw_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&dw_driver);
|
||||
}
|
||||
module_exit(dw_exit);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller platform driver");
|
||||
MODULE_ALIAS("platform:" DRV_NAME);
|
||||
345
drivers/dma/dw/regs.h
Normal file
345
drivers/dma/dw/regs.h
Normal file
|
|
@ -0,0 +1,345 @@
|
|||
/*
|
||||
* Driver for the Synopsys DesignWare AHB DMA Controller
|
||||
*
|
||||
* Copyright (C) 2005-2007 Atmel Corporation
|
||||
* Copyright (C) 2010-2011 ST Microelectronics
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/dmaengine.h>
|
||||
|
||||
#define DW_DMA_MAX_NR_CHANNELS 8
|
||||
#define DW_DMA_MAX_NR_REQUESTS 16
|
||||
|
||||
/* flow controller */
|
||||
enum dw_dma_fc {
|
||||
DW_DMA_FC_D_M2M,
|
||||
DW_DMA_FC_D_M2P,
|
||||
DW_DMA_FC_D_P2M,
|
||||
DW_DMA_FC_D_P2P,
|
||||
DW_DMA_FC_P_P2M,
|
||||
DW_DMA_FC_SP_P2P,
|
||||
DW_DMA_FC_P_M2P,
|
||||
DW_DMA_FC_DP_P2P,
|
||||
};
|
||||
|
||||
/*
|
||||
* Redefine this macro to handle differences between 32- and 64-bit
|
||||
* addressing, big vs. little endian, etc.
|
||||
*/
|
||||
#define DW_REG(name) u32 name; u32 __pad_##name
|
||||
|
||||
/* Hardware register definitions. */
|
||||
struct dw_dma_chan_regs {
|
||||
DW_REG(SAR); /* Source Address Register */
|
||||
DW_REG(DAR); /* Destination Address Register */
|
||||
DW_REG(LLP); /* Linked List Pointer */
|
||||
u32 CTL_LO; /* Control Register Low */
|
||||
u32 CTL_HI; /* Control Register High */
|
||||
DW_REG(SSTAT);
|
||||
DW_REG(DSTAT);
|
||||
DW_REG(SSTATAR);
|
||||
DW_REG(DSTATAR);
|
||||
u32 CFG_LO; /* Configuration Register Low */
|
||||
u32 CFG_HI; /* Configuration Register High */
|
||||
DW_REG(SGR);
|
||||
DW_REG(DSR);
|
||||
};
|
||||
|
||||
struct dw_dma_irq_regs {
|
||||
DW_REG(XFER);
|
||||
DW_REG(BLOCK);
|
||||
DW_REG(SRC_TRAN);
|
||||
DW_REG(DST_TRAN);
|
||||
DW_REG(ERROR);
|
||||
};
|
||||
|
||||
struct dw_dma_regs {
|
||||
/* per-channel registers */
|
||||
struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
|
||||
|
||||
/* irq handling */
|
||||
struct dw_dma_irq_regs RAW; /* r */
|
||||
struct dw_dma_irq_regs STATUS; /* r (raw & mask) */
|
||||
struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */
|
||||
struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */
|
||||
|
||||
DW_REG(STATUS_INT); /* r */
|
||||
|
||||
/* software handshaking */
|
||||
DW_REG(REQ_SRC);
|
||||
DW_REG(REQ_DST);
|
||||
DW_REG(SGL_REQ_SRC);
|
||||
DW_REG(SGL_REQ_DST);
|
||||
DW_REG(LAST_SRC);
|
||||
DW_REG(LAST_DST);
|
||||
|
||||
/* miscellaneous */
|
||||
DW_REG(CFG);
|
||||
DW_REG(CH_EN);
|
||||
DW_REG(ID);
|
||||
DW_REG(TEST);
|
||||
|
||||
/* reserved */
|
||||
DW_REG(__reserved0);
|
||||
DW_REG(__reserved1);
|
||||
|
||||
/* optional encoded params, 0x3c8..0x3f7 */
|
||||
u32 __reserved;
|
||||
|
||||
/* per-channel configuration registers */
|
||||
u32 DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
|
||||
u32 MULTI_BLK_TYPE;
|
||||
u32 MAX_BLK_SIZE;
|
||||
|
||||
/* top-level parameters */
|
||||
u32 DW_PARAMS;
|
||||
};
|
||||
|
||||
/*
|
||||
* Big endian I/O access when reading and writing to the DMA controller
|
||||
* registers. This is needed on some platforms, like the Atmel AVR32
|
||||
* architecture.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
|
||||
#define dma_readl_native ioread32be
|
||||
#define dma_writel_native iowrite32be
|
||||
#else
|
||||
#define dma_readl_native readl
|
||||
#define dma_writel_native writel
|
||||
#endif
|
||||
|
||||
/* To access the registers in early stage of probe */
|
||||
#define dma_read_byaddr(addr, name) \
|
||||
dma_readl_native((addr) + offsetof(struct dw_dma_regs, name))
|
||||
|
||||
/* Bitfields in DW_PARAMS */
|
||||
#define DW_PARAMS_NR_CHAN 8 /* number of channels */
|
||||
#define DW_PARAMS_NR_MASTER 11 /* number of AHB masters */
|
||||
#define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n))
|
||||
#define DW_PARAMS_DATA_WIDTH1 15 /* master 1 data width */
|
||||
#define DW_PARAMS_DATA_WIDTH2 17 /* master 2 data width */
|
||||
#define DW_PARAMS_DATA_WIDTH3 19 /* master 3 data width */
|
||||
#define DW_PARAMS_DATA_WIDTH4 21 /* master 4 data width */
|
||||
#define DW_PARAMS_EN 28 /* encoded parameters */
|
||||
|
||||
/* Bitfields in DWC_PARAMS */
|
||||
#define DWC_PARAMS_MBLK_EN 11 /* multi block transfer */
|
||||
|
||||
/* bursts size */
|
||||
enum dw_dma_msize {
|
||||
DW_DMA_MSIZE_1,
|
||||
DW_DMA_MSIZE_4,
|
||||
DW_DMA_MSIZE_8,
|
||||
DW_DMA_MSIZE_16,
|
||||
DW_DMA_MSIZE_32,
|
||||
DW_DMA_MSIZE_64,
|
||||
DW_DMA_MSIZE_128,
|
||||
DW_DMA_MSIZE_256,
|
||||
};
|
||||
|
||||
/* Bitfields in CTL_LO */
|
||||
#define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */
|
||||
#define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */
|
||||
#define DWC_CTLL_SRC_WIDTH(n) ((n)<<4)
|
||||
#define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */
|
||||
#define DWC_CTLL_DST_DEC (1<<7)
|
||||
#define DWC_CTLL_DST_FIX (2<<7)
|
||||
#define DWC_CTLL_SRC_INC (0<<7) /* SAR update/not */
|
||||
#define DWC_CTLL_SRC_DEC (1<<9)
|
||||
#define DWC_CTLL_SRC_FIX (2<<9)
|
||||
#define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */
|
||||
#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
|
||||
#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */
|
||||
#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */
|
||||
#define DWC_CTLL_FC(n) ((n) << 20)
|
||||
#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */
|
||||
#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
|
||||
#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
|
||||
#define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */
|
||||
/* plus 4 transfer types for peripheral-as-flow-controller */
|
||||
#define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */
|
||||
#define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */
|
||||
#define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */
|
||||
#define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */
|
||||
|
||||
/* Bitfields in CTL_HI */
|
||||
#define DWC_CTLH_DONE 0x00001000
|
||||
#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff
|
||||
|
||||
/* Bitfields in CFG_LO */
|
||||
#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */
|
||||
#define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */
|
||||
#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */
|
||||
#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */
|
||||
#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */
|
||||
#define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */
|
||||
#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
|
||||
#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
|
||||
#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
|
||||
#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
|
||||
#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
|
||||
#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
|
||||
#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
|
||||
#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
|
||||
#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
|
||||
#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
|
||||
#define DWC_CFGL_MAX_BURST(x) ((x) << 20)
|
||||
#define DWC_CFGL_RELOAD_SAR (1 << 30)
|
||||
#define DWC_CFGL_RELOAD_DAR (1 << 31)
|
||||
|
||||
/* Bitfields in CFG_HI */
|
||||
#define DWC_CFGH_FCMODE (1 << 0)
|
||||
#define DWC_CFGH_FIFO_MODE (1 << 1)
|
||||
#define DWC_CFGH_PROTCTL(x) ((x) << 2)
|
||||
#define DWC_CFGH_DS_UPD_EN (1 << 5)
|
||||
#define DWC_CFGH_SS_UPD_EN (1 << 6)
|
||||
#define DWC_CFGH_SRC_PER(x) ((x) << 7)
|
||||
#define DWC_CFGH_DST_PER(x) ((x) << 11)
|
||||
|
||||
/* Bitfields in SGR */
|
||||
#define DWC_SGR_SGI(x) ((x) << 0)
|
||||
#define DWC_SGR_SGC(x) ((x) << 20)
|
||||
|
||||
/* Bitfields in DSR */
|
||||
#define DWC_DSR_DSI(x) ((x) << 0)
|
||||
#define DWC_DSR_DSC(x) ((x) << 20)
|
||||
|
||||
/* Bitfields in CFG */
|
||||
#define DW_CFG_DMA_EN (1 << 0)
|
||||
|
||||
enum dw_dmac_flags {
|
||||
DW_DMA_IS_CYCLIC = 0,
|
||||
DW_DMA_IS_SOFT_LLP = 1,
|
||||
};
|
||||
|
||||
struct dw_dma_chan {
|
||||
struct dma_chan chan;
|
||||
void __iomem *ch_regs;
|
||||
u8 mask;
|
||||
u8 priority;
|
||||
enum dma_transfer_direction direction;
|
||||
bool paused;
|
||||
bool initialized;
|
||||
|
||||
/* software emulation of the LLP transfers */
|
||||
struct list_head *tx_node_active;
|
||||
|
||||
spinlock_t lock;
|
||||
|
||||
/* these other elements are all protected by lock */
|
||||
unsigned long flags;
|
||||
struct list_head active_list;
|
||||
struct list_head queue;
|
||||
struct list_head free_list;
|
||||
u32 residue;
|
||||
struct dw_cyclic_desc *cdesc;
|
||||
|
||||
unsigned int descs_allocated;
|
||||
|
||||
/* hardware configuration */
|
||||
unsigned int block_size;
|
||||
bool nollp;
|
||||
|
||||
/* custom slave configuration */
|
||||
u8 src_id;
|
||||
u8 dst_id;
|
||||
u8 src_master;
|
||||
u8 dst_master;
|
||||
|
||||
/* configuration passed via DMA_SLAVE_CONFIG */
|
||||
struct dma_slave_config dma_sconfig;
|
||||
};
|
||||
|
||||
static inline struct dw_dma_chan_regs __iomem *
|
||||
__dwc_regs(struct dw_dma_chan *dwc)
|
||||
{
|
||||
return dwc->ch_regs;
|
||||
}
|
||||
|
||||
#define channel_readl(dwc, name) \
|
||||
dma_readl_native(&(__dwc_regs(dwc)->name))
|
||||
#define channel_writel(dwc, name, val) \
|
||||
dma_writel_native((val), &(__dwc_regs(dwc)->name))
|
||||
|
||||
static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
|
||||
{
|
||||
return container_of(chan, struct dw_dma_chan, chan);
|
||||
}
|
||||
|
||||
struct dw_dma {
|
||||
struct dma_device dma;
|
||||
void __iomem *regs;
|
||||
struct dma_pool *desc_pool;
|
||||
struct tasklet_struct tasklet;
|
||||
|
||||
/* channels */
|
||||
struct dw_dma_chan *chan;
|
||||
u8 all_chan_mask;
|
||||
u8 in_use;
|
||||
|
||||
/* hardware configuration */
|
||||
unsigned char nr_masters;
|
||||
unsigned char data_width[4];
|
||||
};
|
||||
|
||||
static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
|
||||
{
|
||||
return dw->regs;
|
||||
}
|
||||
|
||||
#define dma_readl(dw, name) \
|
||||
dma_readl_native(&(__dw_regs(dw)->name))
|
||||
#define dma_writel(dw, name, val) \
|
||||
dma_writel_native((val), &(__dw_regs(dw)->name))
|
||||
|
||||
#define channel_set_bit(dw, reg, mask) \
|
||||
dma_writel(dw, reg, ((mask) << 8) | (mask))
|
||||
#define channel_clear_bit(dw, reg, mask) \
|
||||
dma_writel(dw, reg, ((mask) << 8) | 0)
|
||||
|
||||
static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
|
||||
{
|
||||
return container_of(ddev, struct dw_dma, dma);
|
||||
}
|
||||
|
||||
/* LLI == Linked List Item; a.k.a. DMA block descriptor */
|
||||
struct dw_lli {
|
||||
/* values that are not changed by hardware */
|
||||
u32 sar;
|
||||
u32 dar;
|
||||
u32 llp; /* chain to next lli */
|
||||
u32 ctllo;
|
||||
/* values that may get written back: */
|
||||
u32 ctlhi;
|
||||
/* sstat and dstat can snapshot peripheral register state.
|
||||
* silicon config may discard either or both...
|
||||
*/
|
||||
u32 sstat;
|
||||
u32 dstat;
|
||||
};
|
||||
|
||||
struct dw_desc {
|
||||
/* FIRST values the hardware uses */
|
||||
struct dw_lli lli;
|
||||
|
||||
/* THEN values for driver housekeeping */
|
||||
struct list_head desc_node;
|
||||
struct list_head tx_list;
|
||||
struct dma_async_tx_descriptor txd;
|
||||
size_t len;
|
||||
size_t total_len;
|
||||
};
|
||||
|
||||
#define to_dw_desc(h) list_entry(h, struct dw_desc, desc_node)
|
||||
|
||||
static inline struct dw_desc *
|
||||
txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
|
||||
{
|
||||
return container_of(txd, struct dw_desc, txd);
|
||||
}
|
||||
1131
drivers/dma/edma.c
Normal file
1131
drivers/dma/edma.c
Normal file
File diff suppressed because it is too large
Load diff
1417
drivers/dma/ep93xx_dma.c
Normal file
1417
drivers/dma/ep93xx_dma.c
Normal file
File diff suppressed because it is too large
Load diff
987
drivers/dma/fsl-edma.c
Normal file
987
drivers/dma/fsl-edma.c
Normal file
|
|
@ -0,0 +1,987 @@
|
|||
/*
|
||||
* drivers/dma/fsl-edma.c
|
||||
*
|
||||
* Copyright 2013-2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Driver for the Freescale eDMA engine with flexible channel multiplexing
|
||||
* capability for DMA request sources. The eDMA block can be found on some
|
||||
* Vybrid and Layerscape SoCs.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/dmapool.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_dma.h>
|
||||
|
||||
#include "virt-dma.h"
|
||||
|
||||
#define EDMA_CR 0x00
|
||||
#define EDMA_ES 0x04
|
||||
#define EDMA_ERQ 0x0C
|
||||
#define EDMA_EEI 0x14
|
||||
#define EDMA_SERQ 0x1B
|
||||
#define EDMA_CERQ 0x1A
|
||||
#define EDMA_SEEI 0x19
|
||||
#define EDMA_CEEI 0x18
|
||||
#define EDMA_CINT 0x1F
|
||||
#define EDMA_CERR 0x1E
|
||||
#define EDMA_SSRT 0x1D
|
||||
#define EDMA_CDNE 0x1C
|
||||
#define EDMA_INTR 0x24
|
||||
#define EDMA_ERR 0x2C
|
||||
|
||||
#define EDMA_TCD_SADDR(x) (0x1000 + 32 * (x))
|
||||
#define EDMA_TCD_SOFF(x) (0x1004 + 32 * (x))
|
||||
#define EDMA_TCD_ATTR(x) (0x1006 + 32 * (x))
|
||||
#define EDMA_TCD_NBYTES(x) (0x1008 + 32 * (x))
|
||||
#define EDMA_TCD_SLAST(x) (0x100C + 32 * (x))
|
||||
#define EDMA_TCD_DADDR(x) (0x1010 + 32 * (x))
|
||||
#define EDMA_TCD_DOFF(x) (0x1014 + 32 * (x))
|
||||
#define EDMA_TCD_CITER_ELINK(x) (0x1016 + 32 * (x))
|
||||
#define EDMA_TCD_CITER(x) (0x1016 + 32 * (x))
|
||||
#define EDMA_TCD_DLAST_SGA(x) (0x1018 + 32 * (x))
|
||||
#define EDMA_TCD_CSR(x) (0x101C + 32 * (x))
|
||||
#define EDMA_TCD_BITER_ELINK(x) (0x101E + 32 * (x))
|
||||
#define EDMA_TCD_BITER(x) (0x101E + 32 * (x))
|
||||
|
||||
#define EDMA_CR_EDBG BIT(1)
|
||||
#define EDMA_CR_ERCA BIT(2)
|
||||
#define EDMA_CR_ERGA BIT(3)
|
||||
#define EDMA_CR_HOE BIT(4)
|
||||
#define EDMA_CR_HALT BIT(5)
|
||||
#define EDMA_CR_CLM BIT(6)
|
||||
#define EDMA_CR_EMLM BIT(7)
|
||||
#define EDMA_CR_ECX BIT(16)
|
||||
#define EDMA_CR_CX BIT(17)
|
||||
|
||||
#define EDMA_SEEI_SEEI(x) ((x) & 0x1F)
|
||||
#define EDMA_CEEI_CEEI(x) ((x) & 0x1F)
|
||||
#define EDMA_CINT_CINT(x) ((x) & 0x1F)
|
||||
#define EDMA_CERR_CERR(x) ((x) & 0x1F)
|
||||
|
||||
#define EDMA_TCD_ATTR_DSIZE(x) (((x) & 0x0007))
|
||||
#define EDMA_TCD_ATTR_DMOD(x) (((x) & 0x001F) << 3)
|
||||
#define EDMA_TCD_ATTR_SSIZE(x) (((x) & 0x0007) << 8)
|
||||
#define EDMA_TCD_ATTR_SMOD(x) (((x) & 0x001F) << 11)
|
||||
#define EDMA_TCD_ATTR_SSIZE_8BIT (0x0000)
|
||||
#define EDMA_TCD_ATTR_SSIZE_16BIT (0x0100)
|
||||
#define EDMA_TCD_ATTR_SSIZE_32BIT (0x0200)
|
||||
#define EDMA_TCD_ATTR_SSIZE_64BIT (0x0300)
|
||||
#define EDMA_TCD_ATTR_SSIZE_32BYTE (0x0500)
|
||||
#define EDMA_TCD_ATTR_DSIZE_8BIT (0x0000)
|
||||
#define EDMA_TCD_ATTR_DSIZE_16BIT (0x0001)
|
||||
#define EDMA_TCD_ATTR_DSIZE_32BIT (0x0002)
|
||||
#define EDMA_TCD_ATTR_DSIZE_64BIT (0x0003)
|
||||
#define EDMA_TCD_ATTR_DSIZE_32BYTE (0x0005)
|
||||
|
||||
#define EDMA_TCD_SOFF_SOFF(x) (x)
|
||||
#define EDMA_TCD_NBYTES_NBYTES(x) (x)
|
||||
#define EDMA_TCD_SLAST_SLAST(x) (x)
|
||||
#define EDMA_TCD_DADDR_DADDR(x) (x)
|
||||
#define EDMA_TCD_CITER_CITER(x) ((x) & 0x7FFF)
|
||||
#define EDMA_TCD_DOFF_DOFF(x) (x)
|
||||
#define EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x)
|
||||
#define EDMA_TCD_BITER_BITER(x) ((x) & 0x7FFF)
|
||||
|
||||
#define EDMA_TCD_CSR_START BIT(0)
|
||||
#define EDMA_TCD_CSR_INT_MAJOR BIT(1)
|
||||
#define EDMA_TCD_CSR_INT_HALF BIT(2)
|
||||
#define EDMA_TCD_CSR_D_REQ BIT(3)
|
||||
#define EDMA_TCD_CSR_E_SG BIT(4)
|
||||
#define EDMA_TCD_CSR_E_LINK BIT(5)
|
||||
#define EDMA_TCD_CSR_ACTIVE BIT(6)
|
||||
#define EDMA_TCD_CSR_DONE BIT(7)
|
||||
|
||||
#define EDMAMUX_CHCFG_DIS 0x0
|
||||
#define EDMAMUX_CHCFG_ENBL 0x80
|
||||
#define EDMAMUX_CHCFG_SOURCE(n) ((n) & 0x3F)
|
||||
|
||||
#define DMAMUX_NR 2
|
||||
|
||||
#define FSL_EDMA_BUSWIDTHS BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
|
||||
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
|
||||
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
|
||||
BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
|
||||
|
||||
struct fsl_edma_hw_tcd {
|
||||
u32 saddr;
|
||||
u16 soff;
|
||||
u16 attr;
|
||||
u32 nbytes;
|
||||
u32 slast;
|
||||
u32 daddr;
|
||||
u16 doff;
|
||||
u16 citer;
|
||||
u32 dlast_sga;
|
||||
u16 csr;
|
||||
u16 biter;
|
||||
};
|
||||
|
||||
struct fsl_edma_sw_tcd {
|
||||
dma_addr_t ptcd;
|
||||
struct fsl_edma_hw_tcd *vtcd;
|
||||
};
|
||||
|
||||
struct fsl_edma_slave_config {
|
||||
enum dma_transfer_direction dir;
|
||||
enum dma_slave_buswidth addr_width;
|
||||
u32 dev_addr;
|
||||
u32 burst;
|
||||
u32 attr;
|
||||
};
|
||||
|
||||
struct fsl_edma_chan {
|
||||
struct virt_dma_chan vchan;
|
||||
enum dma_status status;
|
||||
struct fsl_edma_engine *edma;
|
||||
struct fsl_edma_desc *edesc;
|
||||
struct fsl_edma_slave_config fsc;
|
||||
struct dma_pool *tcd_pool;
|
||||
};
|
||||
|
||||
struct fsl_edma_desc {
|
||||
struct virt_dma_desc vdesc;
|
||||
struct fsl_edma_chan *echan;
|
||||
bool iscyclic;
|
||||
unsigned int n_tcds;
|
||||
struct fsl_edma_sw_tcd tcd[];
|
||||
};
|
||||
|
||||
struct fsl_edma_engine {
|
||||
struct dma_device dma_dev;
|
||||
void __iomem *membase;
|
||||
void __iomem *muxbase[DMAMUX_NR];
|
||||
struct clk *muxclk[DMAMUX_NR];
|
||||
struct mutex fsl_edma_mutex;
|
||||
u32 n_chans;
|
||||
int txirq;
|
||||
int errirq;
|
||||
bool big_endian;
|
||||
struct fsl_edma_chan chans[];
|
||||
};
|
||||
|
||||
/*
|
||||
* R/W functions for big- or little-endian registers
|
||||
* the eDMA controller's endian is independent of the CPU core's endian.
|
||||
*/
|
||||
|
||||
static u16 edma_readw(struct fsl_edma_engine *edma, void __iomem *addr)
|
||||
{
|
||||
if (edma->big_endian)
|
||||
return ioread16be(addr);
|
||||
else
|
||||
return ioread16(addr);
|
||||
}
|
||||
|
||||
static u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
|
||||
{
|
||||
if (edma->big_endian)
|
||||
return ioread32be(addr);
|
||||
else
|
||||
return ioread32(addr);
|
||||
}
|
||||
|
||||
static void edma_writeb(struct fsl_edma_engine *edma, u8 val, void __iomem *addr)
|
||||
{
|
||||
iowrite8(val, addr);
|
||||
}
|
||||
|
||||
static void edma_writew(struct fsl_edma_engine *edma, u16 val, void __iomem *addr)
|
||||
{
|
||||
if (edma->big_endian)
|
||||
iowrite16be(val, addr);
|
||||
else
|
||||
iowrite16(val, addr);
|
||||
}
|
||||
|
||||
static void edma_writel(struct fsl_edma_engine *edma, u32 val, void __iomem *addr)
|
||||
{
|
||||
if (edma->big_endian)
|
||||
iowrite32be(val, addr);
|
||||
else
|
||||
iowrite32(val, addr);
|
||||
}
|
||||
|
||||
static struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
|
||||
{
|
||||
return container_of(chan, struct fsl_edma_chan, vchan.chan);
|
||||
}
|
||||
|
||||
static struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
|
||||
{
|
||||
return container_of(vd, struct fsl_edma_desc, vdesc);
|
||||
}
|
||||
|
||||
static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
|
||||
{
|
||||
void __iomem *addr = fsl_chan->edma->membase;
|
||||
u32 ch = fsl_chan->vchan.chan.chan_id;
|
||||
|
||||
edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), addr + EDMA_SEEI);
|
||||
edma_writeb(fsl_chan->edma, ch, addr + EDMA_SERQ);
|
||||
}
|
||||
|
||||
static void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
|
||||
{
|
||||
void __iomem *addr = fsl_chan->edma->membase;
|
||||
u32 ch = fsl_chan->vchan.chan.chan_id;
|
||||
|
||||
edma_writeb(fsl_chan->edma, ch, addr + EDMA_CERQ);
|
||||
edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), addr + EDMA_CEEI);
|
||||
}
|
||||
|
||||
static void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
|
||||
unsigned int slot, bool enable)
|
||||
{
|
||||
u32 ch = fsl_chan->vchan.chan.chan_id;
|
||||
void __iomem *muxaddr;
|
||||
unsigned chans_per_mux, ch_off;
|
||||
|
||||
chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR;
|
||||
ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
|
||||
muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
|
||||
|
||||
if (enable)
|
||||
edma_writeb(fsl_chan->edma,
|
||||
EDMAMUX_CHCFG_ENBL | EDMAMUX_CHCFG_SOURCE(slot),
|
||||
muxaddr + ch_off);
|
||||
else
|
||||
edma_writeb(fsl_chan->edma, EDMAMUX_CHCFG_DIS, muxaddr + ch_off);
|
||||
}
|
||||
|
||||
static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width)
|
||||
{
|
||||
switch (addr_width) {
|
||||
case 1:
|
||||
return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT;
|
||||
case 2:
|
||||
return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT;
|
||||
case 4:
|
||||
return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT;
|
||||
case 8:
|
||||
return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT;
|
||||
default:
|
||||
return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT;
|
||||
}
|
||||
}
|
||||
|
||||
static void fsl_edma_free_desc(struct virt_dma_desc *vdesc)
|
||||
{
|
||||
struct fsl_edma_desc *fsl_desc;
|
||||
int i;
|
||||
|
||||
fsl_desc = to_fsl_edma_desc(vdesc);
|
||||
for (i = 0; i < fsl_desc->n_tcds; i++)
|
||||
dma_pool_free(fsl_desc->echan->tcd_pool,
|
||||
fsl_desc->tcd[i].vtcd,
|
||||
fsl_desc->tcd[i].ptcd);
|
||||
kfree(fsl_desc);
|
||||
}
|
||||
|
||||
static int fsl_edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
|
||||
struct dma_slave_config *cfg = (void *)arg;
|
||||
unsigned long flags;
|
||||
LIST_HEAD(head);
|
||||
|
||||
switch (cmd) {
|
||||
case DMA_TERMINATE_ALL:
|
||||
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
||||
fsl_edma_disable_request(fsl_chan);
|
||||
fsl_chan->edesc = NULL;
|
||||
vchan_get_all_descriptors(&fsl_chan->vchan, &head);
|
||||
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||
vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
|
||||
return 0;
|
||||
|
||||
case DMA_SLAVE_CONFIG:
|
||||
fsl_chan->fsc.dir = cfg->direction;
|
||||
if (cfg->direction == DMA_DEV_TO_MEM) {
|
||||
fsl_chan->fsc.dev_addr = cfg->src_addr;
|
||||
fsl_chan->fsc.addr_width = cfg->src_addr_width;
|
||||
fsl_chan->fsc.burst = cfg->src_maxburst;
|
||||
fsl_chan->fsc.attr = fsl_edma_get_tcd_attr(cfg->src_addr_width);
|
||||
} else if (cfg->direction == DMA_MEM_TO_DEV) {
|
||||
fsl_chan->fsc.dev_addr = cfg->dst_addr;
|
||||
fsl_chan->fsc.addr_width = cfg->dst_addr_width;
|
||||
fsl_chan->fsc.burst = cfg->dst_maxburst;
|
||||
fsl_chan->fsc.attr = fsl_edma_get_tcd_attr(cfg->dst_addr_width);
|
||||
} else {
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
|
||||
case DMA_PAUSE:
|
||||
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
||||
if (fsl_chan->edesc) {
|
||||
fsl_edma_disable_request(fsl_chan);
|
||||
fsl_chan->status = DMA_PAUSED;
|
||||
}
|
||||
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||
return 0;
|
||||
|
||||
case DMA_RESUME:
|
||||
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
||||
if (fsl_chan->edesc) {
|
||||
fsl_edma_enable_request(fsl_chan);
|
||||
fsl_chan->status = DMA_IN_PROGRESS;
|
||||
}
|
||||
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||
return 0;
|
||||
|
||||
default:
|
||||
return -ENXIO;
|
||||
}
|
||||
}
|
||||
|
||||
static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
|
||||
struct virt_dma_desc *vdesc, bool in_progress)
|
||||
{
|
||||
struct fsl_edma_desc *edesc = fsl_chan->edesc;
|
||||
void __iomem *addr = fsl_chan->edma->membase;
|
||||
u32 ch = fsl_chan->vchan.chan.chan_id;
|
||||
enum dma_transfer_direction dir = fsl_chan->fsc.dir;
|
||||
dma_addr_t cur_addr, dma_addr;
|
||||
size_t len, size;
|
||||
int i;
|
||||
|
||||
/* calculate the total size in this desc */
|
||||
for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++)
|
||||
len += edma_readl(fsl_chan->edma, &(edesc->tcd[i].vtcd->nbytes))
|
||||
* edma_readw(fsl_chan->edma, &(edesc->tcd[i].vtcd->biter));
|
||||
|
||||
if (!in_progress)
|
||||
return len;
|
||||
|
||||
if (dir == DMA_MEM_TO_DEV)
|
||||
cur_addr = edma_readl(fsl_chan->edma, addr + EDMA_TCD_SADDR(ch));
|
||||
else
|
||||
cur_addr = edma_readl(fsl_chan->edma, addr + EDMA_TCD_DADDR(ch));
|
||||
|
||||
/* figure out the finished and calculate the residue */
|
||||
for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
|
||||
size = edma_readl(fsl_chan->edma, &(edesc->tcd[i].vtcd->nbytes))
|
||||
* edma_readw(fsl_chan->edma, &(edesc->tcd[i].vtcd->biter));
|
||||
if (dir == DMA_MEM_TO_DEV)
|
||||
dma_addr = edma_readl(fsl_chan->edma,
|
||||
&(edesc->tcd[i].vtcd->saddr));
|
||||
else
|
||||
dma_addr = edma_readl(fsl_chan->edma,
|
||||
&(edesc->tcd[i].vtcd->daddr));
|
||||
|
||||
len -= size;
|
||||
if (cur_addr > dma_addr && cur_addr < dma_addr + size) {
|
||||
len += dma_addr + size - cur_addr;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
static enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
|
||||
dma_cookie_t cookie, struct dma_tx_state *txstate)
|
||||
{
|
||||
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
|
||||
struct virt_dma_desc *vdesc;
|
||||
enum dma_status status;
|
||||
unsigned long flags;
|
||||
|
||||
status = dma_cookie_status(chan, cookie, txstate);
|
||||
if (status == DMA_COMPLETE)
|
||||
return status;
|
||||
|
||||
if (!txstate)
|
||||
return fsl_chan->status;
|
||||
|
||||
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
||||
vdesc = vchan_find_desc(&fsl_chan->vchan, cookie);
|
||||
if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie)
|
||||
txstate->residue = fsl_edma_desc_residue(fsl_chan, vdesc, true);
|
||||
else if (vdesc)
|
||||
txstate->residue = fsl_edma_desc_residue(fsl_chan, vdesc, false);
|
||||
else
|
||||
txstate->residue = 0;
|
||||
|
||||
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||
|
||||
return fsl_chan->status;
|
||||
}
|
||||
|
||||
static void fsl_edma_set_tcd_params(struct fsl_edma_chan *fsl_chan,
|
||||
u32 src, u32 dst, u16 attr, u16 soff, u32 nbytes,
|
||||
u32 slast, u16 citer, u16 biter, u32 doff, u32 dlast_sga,
|
||||
u16 csr)
|
||||
{
|
||||
void __iomem *addr = fsl_chan->edma->membase;
|
||||
u32 ch = fsl_chan->vchan.chan.chan_id;
|
||||
|
||||
/*
|
||||
* TCD parameters have been swapped in fill_tcd_params(),
|
||||
* so just write them to registers in the cpu endian here
|
||||
*/
|
||||
writew(0, addr + EDMA_TCD_CSR(ch));
|
||||
writel(src, addr + EDMA_TCD_SADDR(ch));
|
||||
writel(dst, addr + EDMA_TCD_DADDR(ch));
|
||||
writew(attr, addr + EDMA_TCD_ATTR(ch));
|
||||
writew(soff, addr + EDMA_TCD_SOFF(ch));
|
||||
writel(nbytes, addr + EDMA_TCD_NBYTES(ch));
|
||||
writel(slast, addr + EDMA_TCD_SLAST(ch));
|
||||
writew(citer, addr + EDMA_TCD_CITER(ch));
|
||||
writew(biter, addr + EDMA_TCD_BITER(ch));
|
||||
writew(doff, addr + EDMA_TCD_DOFF(ch));
|
||||
writel(dlast_sga, addr + EDMA_TCD_DLAST_SGA(ch));
|
||||
writew(csr, addr + EDMA_TCD_CSR(ch));
|
||||
}
|
||||
|
||||
static void fill_tcd_params(struct fsl_edma_engine *edma,
|
||||
struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst,
|
||||
u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer,
|
||||
u16 biter, u16 doff, u32 dlast_sga, bool major_int,
|
||||
bool disable_req, bool enable_sg)
|
||||
{
|
||||
u16 csr = 0;
|
||||
|
||||
/*
|
||||
* eDMA hardware SGs require the TCD parameters stored in memory
|
||||
* the same endian as the eDMA module so that they can be loaded
|
||||
* automatically by the engine
|
||||
*/
|
||||
edma_writel(edma, src, &(tcd->saddr));
|
||||
edma_writel(edma, dst, &(tcd->daddr));
|
||||
edma_writew(edma, attr, &(tcd->attr));
|
||||
edma_writew(edma, EDMA_TCD_SOFF_SOFF(soff), &(tcd->soff));
|
||||
edma_writel(edma, EDMA_TCD_NBYTES_NBYTES(nbytes), &(tcd->nbytes));
|
||||
edma_writel(edma, EDMA_TCD_SLAST_SLAST(slast), &(tcd->slast));
|
||||
edma_writew(edma, EDMA_TCD_CITER_CITER(citer), &(tcd->citer));
|
||||
edma_writew(edma, EDMA_TCD_DOFF_DOFF(doff), &(tcd->doff));
|
||||
edma_writel(edma, EDMA_TCD_DLAST_SGA_DLAST_SGA(dlast_sga), &(tcd->dlast_sga));
|
||||
edma_writew(edma, EDMA_TCD_BITER_BITER(biter), &(tcd->biter));
|
||||
if (major_int)
|
||||
csr |= EDMA_TCD_CSR_INT_MAJOR;
|
||||
|
||||
if (disable_req)
|
||||
csr |= EDMA_TCD_CSR_D_REQ;
|
||||
|
||||
if (enable_sg)
|
||||
csr |= EDMA_TCD_CSR_E_SG;
|
||||
|
||||
edma_writew(edma, csr, &(tcd->csr));
|
||||
}
|
||||
|
||||
static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan,
|
||||
int sg_len)
|
||||
{
|
||||
struct fsl_edma_desc *fsl_desc;
|
||||
int i;
|
||||
|
||||
fsl_desc = kzalloc(sizeof(*fsl_desc) + sizeof(struct fsl_edma_sw_tcd) * sg_len,
|
||||
GFP_NOWAIT);
|
||||
if (!fsl_desc)
|
||||
return NULL;
|
||||
|
||||
fsl_desc->echan = fsl_chan;
|
||||
fsl_desc->n_tcds = sg_len;
|
||||
for (i = 0; i < sg_len; i++) {
|
||||
fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool,
|
||||
GFP_NOWAIT, &fsl_desc->tcd[i].ptcd);
|
||||
if (!fsl_desc->tcd[i].vtcd)
|
||||
goto err;
|
||||
}
|
||||
return fsl_desc;
|
||||
|
||||
err:
|
||||
while (--i >= 0)
|
||||
dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd,
|
||||
fsl_desc->tcd[i].ptcd);
|
||||
kfree(fsl_desc);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
|
||||
struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
|
||||
size_t period_len, enum dma_transfer_direction direction,
|
||||
unsigned long flags, void *context)
|
||||
{
|
||||
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
|
||||
struct fsl_edma_desc *fsl_desc;
|
||||
dma_addr_t dma_buf_next;
|
||||
int sg_len, i;
|
||||
u32 src_addr, dst_addr, last_sg, nbytes;
|
||||
u16 soff, doff, iter;
|
||||
|
||||
if (!is_slave_direction(fsl_chan->fsc.dir))
|
||||
return NULL;
|
||||
|
||||
sg_len = buf_len / period_len;
|
||||
fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len);
|
||||
if (!fsl_desc)
|
||||
return NULL;
|
||||
fsl_desc->iscyclic = true;
|
||||
|
||||
dma_buf_next = dma_addr;
|
||||
nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst;
|
||||
iter = period_len / nbytes;
|
||||
|
||||
for (i = 0; i < sg_len; i++) {
|
||||
if (dma_buf_next >= dma_addr + buf_len)
|
||||
dma_buf_next = dma_addr;
|
||||
|
||||
/* get next sg's physical address */
|
||||
last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd;
|
||||
|
||||
if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) {
|
||||
src_addr = dma_buf_next;
|
||||
dst_addr = fsl_chan->fsc.dev_addr;
|
||||
soff = fsl_chan->fsc.addr_width;
|
||||
doff = 0;
|
||||
} else {
|
||||
src_addr = fsl_chan->fsc.dev_addr;
|
||||
dst_addr = dma_buf_next;
|
||||
soff = 0;
|
||||
doff = fsl_chan->fsc.addr_width;
|
||||
}
|
||||
|
||||
fill_tcd_params(fsl_chan->edma, fsl_desc->tcd[i].vtcd, src_addr,
|
||||
dst_addr, fsl_chan->fsc.attr, soff, nbytes, 0,
|
||||
iter, iter, doff, last_sg, true, false, true);
|
||||
dma_buf_next += period_len;
|
||||
}
|
||||
|
||||
return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
|
||||
struct dma_chan *chan, struct scatterlist *sgl,
|
||||
unsigned int sg_len, enum dma_transfer_direction direction,
|
||||
unsigned long flags, void *context)
|
||||
{
|
||||
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
|
||||
struct fsl_edma_desc *fsl_desc;
|
||||
struct scatterlist *sg;
|
||||
u32 src_addr, dst_addr, last_sg, nbytes;
|
||||
u16 soff, doff, iter;
|
||||
int i;
|
||||
|
||||
if (!is_slave_direction(fsl_chan->fsc.dir))
|
||||
return NULL;
|
||||
|
||||
fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len);
|
||||
if (!fsl_desc)
|
||||
return NULL;
|
||||
fsl_desc->iscyclic = false;
|
||||
|
||||
nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst;
|
||||
for_each_sg(sgl, sg, sg_len, i) {
|
||||
/* get next sg's physical address */
|
||||
last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd;
|
||||
|
||||
if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) {
|
||||
src_addr = sg_dma_address(sg);
|
||||
dst_addr = fsl_chan->fsc.dev_addr;
|
||||
soff = fsl_chan->fsc.addr_width;
|
||||
doff = 0;
|
||||
} else {
|
||||
src_addr = fsl_chan->fsc.dev_addr;
|
||||
dst_addr = sg_dma_address(sg);
|
||||
soff = 0;
|
||||
doff = fsl_chan->fsc.addr_width;
|
||||
}
|
||||
|
||||
iter = sg_dma_len(sg) / nbytes;
|
||||
if (i < sg_len - 1) {
|
||||
last_sg = fsl_desc->tcd[(i + 1)].ptcd;
|
||||
fill_tcd_params(fsl_chan->edma, fsl_desc->tcd[i].vtcd,
|
||||
src_addr, dst_addr, fsl_chan->fsc.attr,
|
||||
soff, nbytes, 0, iter, iter, doff, last_sg,
|
||||
false, false, true);
|
||||
} else {
|
||||
last_sg = 0;
|
||||
fill_tcd_params(fsl_chan->edma, fsl_desc->tcd[i].vtcd,
|
||||
src_addr, dst_addr, fsl_chan->fsc.attr,
|
||||
soff, nbytes, 0, iter, iter, doff, last_sg,
|
||||
true, true, false);
|
||||
}
|
||||
}
|
||||
|
||||
return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
|
||||
}
|
||||
|
||||
static void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan)
|
||||
{
|
||||
struct fsl_edma_hw_tcd *tcd;
|
||||
struct virt_dma_desc *vdesc;
|
||||
|
||||
vdesc = vchan_next_desc(&fsl_chan->vchan);
|
||||
if (!vdesc)
|
||||
return;
|
||||
fsl_chan->edesc = to_fsl_edma_desc(vdesc);
|
||||
tcd = fsl_chan->edesc->tcd[0].vtcd;
|
||||
fsl_edma_set_tcd_params(fsl_chan, tcd->saddr, tcd->daddr, tcd->attr,
|
||||
tcd->soff, tcd->nbytes, tcd->slast, tcd->citer,
|
||||
tcd->biter, tcd->doff, tcd->dlast_sga, tcd->csr);
|
||||
fsl_edma_enable_request(fsl_chan);
|
||||
fsl_chan->status = DMA_IN_PROGRESS;
|
||||
}
|
||||
|
||||
static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct fsl_edma_engine *fsl_edma = dev_id;
|
||||
unsigned int intr, ch;
|
||||
void __iomem *base_addr;
|
||||
struct fsl_edma_chan *fsl_chan;
|
||||
|
||||
base_addr = fsl_edma->membase;
|
||||
|
||||
intr = edma_readl(fsl_edma, base_addr + EDMA_INTR);
|
||||
if (!intr)
|
||||
return IRQ_NONE;
|
||||
|
||||
for (ch = 0; ch < fsl_edma->n_chans; ch++) {
|
||||
if (intr & (0x1 << ch)) {
|
||||
edma_writeb(fsl_edma, EDMA_CINT_CINT(ch),
|
||||
base_addr + EDMA_CINT);
|
||||
|
||||
fsl_chan = &fsl_edma->chans[ch];
|
||||
|
||||
spin_lock(&fsl_chan->vchan.lock);
|
||||
if (!fsl_chan->edesc->iscyclic) {
|
||||
list_del(&fsl_chan->edesc->vdesc.node);
|
||||
vchan_cookie_complete(&fsl_chan->edesc->vdesc);
|
||||
fsl_chan->edesc = NULL;
|
||||
fsl_chan->status = DMA_COMPLETE;
|
||||
} else {
|
||||
vchan_cyclic_callback(&fsl_chan->edesc->vdesc);
|
||||
}
|
||||
|
||||
if (!fsl_chan->edesc)
|
||||
fsl_edma_xfer_desc(fsl_chan);
|
||||
|
||||
spin_unlock(&fsl_chan->vchan.lock);
|
||||
}
|
||||
}
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct fsl_edma_engine *fsl_edma = dev_id;
|
||||
unsigned int err, ch;
|
||||
|
||||
err = edma_readl(fsl_edma, fsl_edma->membase + EDMA_ERR);
|
||||
if (!err)
|
||||
return IRQ_NONE;
|
||||
|
||||
for (ch = 0; ch < fsl_edma->n_chans; ch++) {
|
||||
if (err & (0x1 << ch)) {
|
||||
fsl_edma_disable_request(&fsl_edma->chans[ch]);
|
||||
edma_writeb(fsl_edma, EDMA_CERR_CERR(ch),
|
||||
fsl_edma->membase + EDMA_CERR);
|
||||
fsl_edma->chans[ch].status = DMA_ERROR;
|
||||
}
|
||||
}
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED)
|
||||
return IRQ_HANDLED;
|
||||
|
||||
return fsl_edma_err_handler(irq, dev_id);
|
||||
}
|
||||
|
||||
static void fsl_edma_issue_pending(struct dma_chan *chan)
|
||||
{
|
||||
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
||||
|
||||
if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc)
|
||||
fsl_edma_xfer_desc(fsl_chan);
|
||||
|
||||
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||
}
|
||||
|
||||
static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
|
||||
struct dma_chan *chan, *_chan;
|
||||
unsigned long chans_per_mux = fsl_edma->n_chans / DMAMUX_NR;
|
||||
|
||||
if (dma_spec->args_count != 2)
|
||||
return NULL;
|
||||
|
||||
mutex_lock(&fsl_edma->fsl_edma_mutex);
|
||||
list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
|
||||
if (chan->client_count)
|
||||
continue;
|
||||
if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) {
|
||||
chan = dma_get_slave_channel(chan);
|
||||
if (chan) {
|
||||
chan->device->privatecnt++;
|
||||
fsl_edma_chan_mux(to_fsl_edma_chan(chan),
|
||||
dma_spec->args[1], true);
|
||||
mutex_unlock(&fsl_edma->fsl_edma_mutex);
|
||||
return chan;
|
||||
}
|
||||
}
|
||||
}
|
||||
mutex_unlock(&fsl_edma->fsl_edma_mutex);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int fsl_edma_alloc_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
|
||||
|
||||
fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev,
|
||||
sizeof(struct fsl_edma_hw_tcd),
|
||||
32, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void fsl_edma_free_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
|
||||
unsigned long flags;
|
||||
LIST_HEAD(head);
|
||||
|
||||
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
||||
fsl_edma_disable_request(fsl_chan);
|
||||
fsl_edma_chan_mux(fsl_chan, 0, false);
|
||||
fsl_chan->edesc = NULL;
|
||||
vchan_get_all_descriptors(&fsl_chan->vchan, &head);
|
||||
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||
|
||||
vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
|
||||
dma_pool_destroy(fsl_chan->tcd_pool);
|
||||
fsl_chan->tcd_pool = NULL;
|
||||
}
|
||||
|
||||
static int fsl_dma_device_slave_caps(struct dma_chan *dchan,
|
||||
struct dma_slave_caps *caps)
|
||||
{
|
||||
caps->src_addr_widths = FSL_EDMA_BUSWIDTHS;
|
||||
caps->dstn_addr_widths = FSL_EDMA_BUSWIDTHS;
|
||||
caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
|
||||
caps->cmd_pause = true;
|
||||
caps->cmd_terminate = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
|
||||
{
|
||||
int ret;
|
||||
|
||||
fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
|
||||
if (fsl_edma->txirq < 0) {
|
||||
dev_err(&pdev->dev, "Can't get edma-tx irq.\n");
|
||||
return fsl_edma->txirq;
|
||||
}
|
||||
|
||||
fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
|
||||
if (fsl_edma->errirq < 0) {
|
||||
dev_err(&pdev->dev, "Can't get edma-err irq.\n");
|
||||
return fsl_edma->errirq;
|
||||
}
|
||||
|
||||
if (fsl_edma->txirq == fsl_edma->errirq) {
|
||||
ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
|
||||
fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Can't register eDMA IRQ.\n");
|
||||
return ret;
|
||||
}
|
||||
} else {
|
||||
ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
|
||||
fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
|
||||
fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_edma_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct fsl_edma_engine *fsl_edma;
|
||||
struct fsl_edma_chan *fsl_chan;
|
||||
struct resource *res;
|
||||
int len, chans;
|
||||
int ret, i;
|
||||
|
||||
ret = of_property_read_u32(np, "dma-channels", &chans);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Can't get dma-channels.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
len = sizeof(*fsl_edma) + sizeof(*fsl_chan) * chans;
|
||||
fsl_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
|
||||
if (!fsl_edma)
|
||||
return -ENOMEM;
|
||||
|
||||
fsl_edma->n_chans = chans;
|
||||
mutex_init(&fsl_edma->fsl_edma_mutex);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
fsl_edma->membase = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(fsl_edma->membase))
|
||||
return PTR_ERR(fsl_edma->membase);
|
||||
|
||||
for (i = 0; i < DMAMUX_NR; i++) {
|
||||
char clkname[32];
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1 + i);
|
||||
fsl_edma->muxbase[i] = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(fsl_edma->muxbase[i]))
|
||||
return PTR_ERR(fsl_edma->muxbase[i]);
|
||||
|
||||
sprintf(clkname, "dmamux%d", i);
|
||||
fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname);
|
||||
if (IS_ERR(fsl_edma->muxclk[i])) {
|
||||
dev_err(&pdev->dev, "Missing DMAMUX block clock.\n");
|
||||
return PTR_ERR(fsl_edma->muxclk[i]);
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(fsl_edma->muxclk[i]);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "DMAMUX clk block failed.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
ret = fsl_edma_irq_init(pdev, fsl_edma);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
|
||||
|
||||
INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
|
||||
for (i = 0; i < fsl_edma->n_chans; i++) {
|
||||
struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
|
||||
|
||||
fsl_chan->edma = fsl_edma;
|
||||
|
||||
fsl_chan->vchan.desc_free = fsl_edma_free_desc;
|
||||
vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
|
||||
|
||||
edma_writew(fsl_edma, 0x0, fsl_edma->membase + EDMA_TCD_CSR(i));
|
||||
fsl_edma_chan_mux(fsl_chan, 0, false);
|
||||
}
|
||||
|
||||
dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
|
||||
dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
|
||||
dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
|
||||
|
||||
fsl_edma->dma_dev.dev = &pdev->dev;
|
||||
fsl_edma->dma_dev.device_alloc_chan_resources
|
||||
= fsl_edma_alloc_chan_resources;
|
||||
fsl_edma->dma_dev.device_free_chan_resources
|
||||
= fsl_edma_free_chan_resources;
|
||||
fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
|
||||
fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
|
||||
fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
|
||||
fsl_edma->dma_dev.device_control = fsl_edma_control;
|
||||
fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
|
||||
fsl_edma->dma_dev.device_slave_caps = fsl_dma_device_slave_caps;
|
||||
|
||||
platform_set_drvdata(pdev, fsl_edma);
|
||||
|
||||
ret = dma_async_device_register(&fsl_edma->dma_dev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Can't register Freescale eDMA engine.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_dma_controller_register(np, fsl_edma_xlate, fsl_edma);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Can't register Freescale eDMA of_dma.\n");
|
||||
dma_async_device_unregister(&fsl_edma->dma_dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* enable round robin arbitration */
|
||||
edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, fsl_edma->membase + EDMA_CR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_edma_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
|
||||
int i;
|
||||
|
||||
of_dma_controller_free(np);
|
||||
dma_async_device_unregister(&fsl_edma->dma_dev);
|
||||
|
||||
for (i = 0; i < DMAMUX_NR; i++)
|
||||
clk_disable_unprepare(fsl_edma->muxclk[i]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id fsl_edma_dt_ids[] = {
|
||||
{ .compatible = "fsl,vf610-edma", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
|
||||
|
||||
static struct platform_driver fsl_edma_driver = {
|
||||
.driver = {
|
||||
.name = "fsl-edma",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = fsl_edma_dt_ids,
|
||||
},
|
||||
.probe = fsl_edma_probe,
|
||||
.remove = fsl_edma_remove,
|
||||
};
|
||||
|
||||
static int __init fsl_edma_init(void)
|
||||
{
|
||||
return platform_driver_register(&fsl_edma_driver);
|
||||
}
|
||||
subsys_initcall(fsl_edma_init);
|
||||
|
||||
static void __exit fsl_edma_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&fsl_edma_driver);
|
||||
}
|
||||
module_exit(fsl_edma_exit);
|
||||
|
||||
MODULE_ALIAS("platform:fsl-edma");
|
||||
MODULE_DESCRIPTION("Freescale eDMA engine driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
1572
drivers/dma/fsldma.c
Normal file
1572
drivers/dma/fsldma.c
Normal file
File diff suppressed because it is too large
Load diff
234
drivers/dma/fsldma.h
Normal file
234
drivers/dma/fsldma.h
Normal file
|
|
@ -0,0 +1,234 @@
|
|||
/*
|
||||
* Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
|
||||
*
|
||||
* Author:
|
||||
* Zhang Wei <wei.zhang@freescale.com>, Jul 2007
|
||||
* Ebony Zhu <ebony.zhu@freescale.com>, May 2007
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
#ifndef __DMA_FSLDMA_H
|
||||
#define __DMA_FSLDMA_H
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/dmapool.h>
|
||||
#include <linux/dmaengine.h>
|
||||
|
||||
/* Define data structures needed by Freescale
|
||||
* MPC8540 and MPC8349 DMA controller.
|
||||
*/
|
||||
#define FSL_DMA_MR_CS 0x00000001
|
||||
#define FSL_DMA_MR_CC 0x00000002
|
||||
#define FSL_DMA_MR_CA 0x00000008
|
||||
#define FSL_DMA_MR_EIE 0x00000040
|
||||
#define FSL_DMA_MR_XFE 0x00000020
|
||||
#define FSL_DMA_MR_EOLNIE 0x00000100
|
||||
#define FSL_DMA_MR_EOLSIE 0x00000080
|
||||
#define FSL_DMA_MR_EOSIE 0x00000200
|
||||
#define FSL_DMA_MR_CDSM 0x00000010
|
||||
#define FSL_DMA_MR_CTM 0x00000004
|
||||
#define FSL_DMA_MR_EMP_EN 0x00200000
|
||||
#define FSL_DMA_MR_EMS_EN 0x00040000
|
||||
#define FSL_DMA_MR_DAHE 0x00002000
|
||||
#define FSL_DMA_MR_SAHE 0x00001000
|
||||
|
||||
/*
|
||||
* Bandwidth/pause control determines how many bytes a given
|
||||
* channel is allowed to transfer before the DMA engine pauses
|
||||
* the current channel and switches to the next channel
|
||||
*/
|
||||
#define FSL_DMA_MR_BWC 0x0A000000
|
||||
|
||||
/* Special MR definition for MPC8349 */
|
||||
#define FSL_DMA_MR_EOTIE 0x00000080
|
||||
#define FSL_DMA_MR_PRC_RM 0x00000800
|
||||
|
||||
#define FSL_DMA_SR_CH 0x00000020
|
||||
#define FSL_DMA_SR_PE 0x00000010
|
||||
#define FSL_DMA_SR_CB 0x00000004
|
||||
#define FSL_DMA_SR_TE 0x00000080
|
||||
#define FSL_DMA_SR_EOSI 0x00000002
|
||||
#define FSL_DMA_SR_EOLSI 0x00000001
|
||||
#define FSL_DMA_SR_EOCDI 0x00000001
|
||||
#define FSL_DMA_SR_EOLNI 0x00000008
|
||||
|
||||
#define FSL_DMA_SATR_SBPATMU 0x20000000
|
||||
#define FSL_DMA_SATR_STRANSINT_RIO 0x00c00000
|
||||
#define FSL_DMA_SATR_SREADTYPE_SNOOP_READ 0x00050000
|
||||
#define FSL_DMA_SATR_SREADTYPE_BP_IORH 0x00020000
|
||||
#define FSL_DMA_SATR_SREADTYPE_BP_NREAD 0x00040000
|
||||
#define FSL_DMA_SATR_SREADTYPE_BP_MREAD 0x00070000
|
||||
|
||||
#define FSL_DMA_DATR_DBPATMU 0x20000000
|
||||
#define FSL_DMA_DATR_DTRANSINT_RIO 0x00c00000
|
||||
#define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE 0x00050000
|
||||
#define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH 0x00010000
|
||||
|
||||
#define FSL_DMA_EOL ((u64)0x1)
|
||||
#define FSL_DMA_SNEN ((u64)0x10)
|
||||
#define FSL_DMA_EOSIE 0x8
|
||||
#define FSL_DMA_NLDA_MASK (~(u64)0x1f)
|
||||
|
||||
#define FSL_DMA_BCR_MAX_CNT 0x03ffffffu
|
||||
|
||||
#define FSL_DMA_DGSR_TE 0x80
|
||||
#define FSL_DMA_DGSR_CH 0x20
|
||||
#define FSL_DMA_DGSR_PE 0x10
|
||||
#define FSL_DMA_DGSR_EOLNI 0x08
|
||||
#define FSL_DMA_DGSR_CB 0x04
|
||||
#define FSL_DMA_DGSR_EOSI 0x02
|
||||
#define FSL_DMA_DGSR_EOLSI 0x01
|
||||
|
||||
typedef u64 __bitwise v64;
|
||||
typedef u32 __bitwise v32;
|
||||
|
||||
struct fsl_dma_ld_hw {
|
||||
v64 src_addr;
|
||||
v64 dst_addr;
|
||||
v64 next_ln_addr;
|
||||
v32 count;
|
||||
v32 reserve;
|
||||
} __attribute__((aligned(32)));
|
||||
|
||||
struct fsl_desc_sw {
|
||||
struct fsl_dma_ld_hw hw;
|
||||
struct list_head node;
|
||||
struct list_head tx_list;
|
||||
struct dma_async_tx_descriptor async_tx;
|
||||
} __attribute__((aligned(32)));
|
||||
|
||||
struct fsldma_chan_regs {
|
||||
u32 mr; /* 0x00 - Mode Register */
|
||||
u32 sr; /* 0x04 - Status Register */
|
||||
u64 cdar; /* 0x08 - Current descriptor address register */
|
||||
u64 sar; /* 0x10 - Source Address Register */
|
||||
u64 dar; /* 0x18 - Destination Address Register */
|
||||
u32 bcr; /* 0x20 - Byte Count Register */
|
||||
u64 ndar; /* 0x24 - Next Descriptor Address Register */
|
||||
};
|
||||
|
||||
struct fsldma_chan;
|
||||
#define FSL_DMA_MAX_CHANS_PER_DEVICE 8
|
||||
|
||||
struct fsldma_device {
|
||||
void __iomem *regs; /* DGSR register base */
|
||||
struct device *dev;
|
||||
struct dma_device common;
|
||||
struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE];
|
||||
u32 feature; /* The same as DMA channels */
|
||||
int irq; /* Channel IRQ */
|
||||
};
|
||||
|
||||
/* Define macros for fsldma_chan->feature property */
|
||||
#define FSL_DMA_LITTLE_ENDIAN 0x00000000
|
||||
#define FSL_DMA_BIG_ENDIAN 0x00000001
|
||||
|
||||
#define FSL_DMA_IP_MASK 0x00000ff0
|
||||
#define FSL_DMA_IP_85XX 0x00000010
|
||||
#define FSL_DMA_IP_83XX 0x00000020
|
||||
|
||||
#define FSL_DMA_CHAN_PAUSE_EXT 0x00001000
|
||||
#define FSL_DMA_CHAN_START_EXT 0x00002000
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
struct fsldma_chan_regs_save {
|
||||
u32 mr;
|
||||
};
|
||||
|
||||
enum fsldma_pm_state {
|
||||
RUNNING = 0,
|
||||
SUSPENDED,
|
||||
};
|
||||
#endif
|
||||
|
||||
struct fsldma_chan {
|
||||
char name[8]; /* Channel name */
|
||||
struct fsldma_chan_regs __iomem *regs;
|
||||
spinlock_t desc_lock; /* Descriptor operation lock */
|
||||
/*
|
||||
* Descriptors which are queued to run, but have not yet been
|
||||
* submitted to the hardware for execution
|
||||
*/
|
||||
struct list_head ld_pending;
|
||||
/*
|
||||
* Descriptors which are currently being executed by the hardware
|
||||
*/
|
||||
struct list_head ld_running;
|
||||
/*
|
||||
* Descriptors which have finished execution by the hardware. These
|
||||
* descriptors have already had their cleanup actions run. They are
|
||||
* waiting for the ACK bit to be set by the async_tx API.
|
||||
*/
|
||||
struct list_head ld_completed; /* Link descriptors queue */
|
||||
struct dma_chan common; /* DMA common channel */
|
||||
struct dma_pool *desc_pool; /* Descriptors pool */
|
||||
struct device *dev; /* Channel device */
|
||||
int irq; /* Channel IRQ */
|
||||
int id; /* Raw id of this channel */
|
||||
struct tasklet_struct tasklet;
|
||||
u32 feature;
|
||||
bool idle; /* DMA controller is idle */
|
||||
#ifdef CONFIG_PM
|
||||
struct fsldma_chan_regs_save regs_save;
|
||||
enum fsldma_pm_state pm_state;
|
||||
#endif
|
||||
|
||||
void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable);
|
||||
void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable);
|
||||
void (*set_src_loop_size)(struct fsldma_chan *fsl_chan, int size);
|
||||
void (*set_dst_loop_size)(struct fsldma_chan *fsl_chan, int size);
|
||||
void (*set_request_count)(struct fsldma_chan *fsl_chan, int size);
|
||||
};
|
||||
|
||||
#define to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common)
|
||||
#define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node)
|
||||
#define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx)
|
||||
|
||||
#ifndef __powerpc64__
|
||||
static u64 in_be64(const u64 __iomem *addr)
|
||||
{
|
||||
return ((u64)in_be32((u32 __iomem *)addr) << 32) |
|
||||
(in_be32((u32 __iomem *)addr + 1));
|
||||
}
|
||||
|
||||
static void out_be64(u64 __iomem *addr, u64 val)
|
||||
{
|
||||
out_be32((u32 __iomem *)addr, val >> 32);
|
||||
out_be32((u32 __iomem *)addr + 1, (u32)val);
|
||||
}
|
||||
|
||||
/* There is no asm instructions for 64 bits reverse loads and stores */
|
||||
static u64 in_le64(const u64 __iomem *addr)
|
||||
{
|
||||
return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) |
|
||||
(in_le32((u32 __iomem *)addr));
|
||||
}
|
||||
|
||||
static void out_le64(u64 __iomem *addr, u64 val)
|
||||
{
|
||||
out_le32((u32 __iomem *)addr + 1, val >> 32);
|
||||
out_le32((u32 __iomem *)addr, (u32)val);
|
||||
}
|
||||
#endif
|
||||
|
||||
#define DMA_IN(fsl_chan, addr, width) \
|
||||
(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
|
||||
in_be##width(addr) : in_le##width(addr))
|
||||
#define DMA_OUT(fsl_chan, addr, val, width) \
|
||||
(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
|
||||
out_be##width(addr, val) : out_le##width(addr, val))
|
||||
|
||||
#define DMA_TO_CPU(fsl_chan, d, width) \
|
||||
(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
|
||||
be##width##_to_cpu((__force __be##width)(v##width)d) : \
|
||||
le##width##_to_cpu((__force __le##width)(v##width)d))
|
||||
#define CPU_TO_DMA(fsl_chan, c, width) \
|
||||
(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
|
||||
(__force v##width)cpu_to_be##width(c) : \
|
||||
(__force v##width)cpu_to_le##width(c))
|
||||
|
||||
#endif /* __DMA_FSLDMA_H */
|
||||
1254
drivers/dma/imx-dma.c
Normal file
1254
drivers/dma/imx-dma.c
Normal file
File diff suppressed because it is too large
Load diff
1682
drivers/dma/imx-sdma.c
Normal file
1682
drivers/dma/imx-sdma.c
Normal file
File diff suppressed because it is too large
Load diff
1460
drivers/dma/intel_mid_dma.c
Normal file
1460
drivers/dma/intel_mid_dma.c
Normal file
File diff suppressed because it is too large
Load diff
299
drivers/dma/intel_mid_dma_regs.h
Normal file
299
drivers/dma/intel_mid_dma_regs.h
Normal file
|
|
@ -0,0 +1,299 @@
|
|||
/*
|
||||
* intel_mid_dma_regs.h - Intel MID DMA Drivers
|
||||
*
|
||||
* Copyright (C) 2008-10 Intel Corp
|
||||
* Author: Vinod Koul <vinod.koul@intel.com>
|
||||
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
||||
*
|
||||
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
*
|
||||
*
|
||||
*/
|
||||
#ifndef __INTEL_MID_DMAC_REGS_H__
|
||||
#define __INTEL_MID_DMAC_REGS_H__
|
||||
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/dmapool.h>
|
||||
#include <linux/pci_ids.h>
|
||||
|
||||
#define INTEL_MID_DMA_DRIVER_VERSION "1.1.0"
|
||||
|
||||
#define REG_BIT0 0x00000001
|
||||
#define REG_BIT8 0x00000100
|
||||
#define INT_MASK_WE 0x8
|
||||
#define CLEAR_DONE 0xFFFFEFFF
|
||||
#define UNMASK_INTR_REG(chan_num) \
|
||||
((REG_BIT0 << chan_num) | (REG_BIT8 << chan_num))
|
||||
#define MASK_INTR_REG(chan_num) (REG_BIT8 << chan_num)
|
||||
|
||||
#define ENABLE_CHANNEL(chan_num) \
|
||||
((REG_BIT0 << chan_num) | (REG_BIT8 << chan_num))
|
||||
|
||||
#define DISABLE_CHANNEL(chan_num) \
|
||||
(REG_BIT8 << chan_num)
|
||||
|
||||
#define DESCS_PER_CHANNEL 16
|
||||
/*DMA Registers*/
|
||||
/*registers associated with channel programming*/
|
||||
#define DMA_REG_SIZE 0x400
|
||||
#define DMA_CH_SIZE 0x58
|
||||
|
||||
/*CH X REG = (DMA_CH_SIZE)*CH_NO + REG*/
|
||||
#define SAR 0x00 /* Source Address Register*/
|
||||
#define DAR 0x08 /* Destination Address Register*/
|
||||
#define LLP 0x10 /* Linked List Pointer Register*/
|
||||
#define CTL_LOW 0x18 /* Control Register*/
|
||||
#define CTL_HIGH 0x1C /* Control Register*/
|
||||
#define CFG_LOW 0x40 /* Configuration Register Low*/
|
||||
#define CFG_HIGH 0x44 /* Configuration Register high*/
|
||||
|
||||
#define STATUS_TFR 0x2E8
|
||||
#define STATUS_BLOCK 0x2F0
|
||||
#define STATUS_ERR 0x308
|
||||
|
||||
#define RAW_TFR 0x2C0
|
||||
#define RAW_BLOCK 0x2C8
|
||||
#define RAW_ERR 0x2E0
|
||||
|
||||
#define MASK_TFR 0x310
|
||||
#define MASK_BLOCK 0x318
|
||||
#define MASK_SRC_TRAN 0x320
|
||||
#define MASK_DST_TRAN 0x328
|
||||
#define MASK_ERR 0x330
|
||||
|
||||
#define CLEAR_TFR 0x338
|
||||
#define CLEAR_BLOCK 0x340
|
||||
#define CLEAR_SRC_TRAN 0x348
|
||||
#define CLEAR_DST_TRAN 0x350
|
||||
#define CLEAR_ERR 0x358
|
||||
|
||||
#define INTR_STATUS 0x360
|
||||
#define DMA_CFG 0x398
|
||||
#define DMA_CHAN_EN 0x3A0
|
||||
|
||||
/*DMA channel control registers*/
|
||||
union intel_mid_dma_ctl_lo {
|
||||
struct {
|
||||
u32 int_en:1; /*enable or disable interrupts*/
|
||||
/*should be 0*/
|
||||
u32 dst_tr_width:3; /*destination transfer width*/
|
||||
/*usually 32 bits = 010*/
|
||||
u32 src_tr_width:3; /*source transfer width*/
|
||||
/*usually 32 bits = 010*/
|
||||
u32 dinc:2; /*destination address inc/dec*/
|
||||
/*For mem:INC=00, Periphral NoINC=11*/
|
||||
u32 sinc:2; /*source address inc or dec, as above*/
|
||||
u32 dst_msize:3; /*destination burst transaction length*/
|
||||
/*always = 16 ie 011*/
|
||||
u32 src_msize:3; /*source burst transaction length*/
|
||||
/*always = 16 ie 011*/
|
||||
u32 reser1:3;
|
||||
u32 tt_fc:3; /*transfer type and flow controller*/
|
||||
/*M-M = 000
|
||||
P-M = 010
|
||||
M-P = 001*/
|
||||
u32 dms:2; /*destination master select = 0*/
|
||||
u32 sms:2; /*source master select = 0*/
|
||||
u32 llp_dst_en:1; /*enable/disable destination LLP = 0*/
|
||||
u32 llp_src_en:1; /*enable/disable source LLP = 0*/
|
||||
u32 reser2:3;
|
||||
} ctlx;
|
||||
u32 ctl_lo;
|
||||
};
|
||||
|
||||
union intel_mid_dma_ctl_hi {
|
||||
struct {
|
||||
u32 block_ts:12; /*block transfer size*/
|
||||
u32 done:1; /*Done - updated by DMAC*/
|
||||
u32 reser:19; /*configured by DMAC*/
|
||||
} ctlx;
|
||||
u32 ctl_hi;
|
||||
|
||||
};
|
||||
|
||||
/*DMA channel configuration registers*/
|
||||
union intel_mid_dma_cfg_lo {
|
||||
struct {
|
||||
u32 reser1:5;
|
||||
u32 ch_prior:3; /*channel priority = 0*/
|
||||
u32 ch_susp:1; /*channel suspend = 0*/
|
||||
u32 fifo_empty:1; /*FIFO empty or not R bit = 0*/
|
||||
u32 hs_sel_dst:1; /*select HW/SW destn handshaking*/
|
||||
/*HW = 0, SW = 1*/
|
||||
u32 hs_sel_src:1; /*select HW/SW src handshaking*/
|
||||
u32 reser2:6;
|
||||
u32 dst_hs_pol:1; /*dest HS interface polarity*/
|
||||
u32 src_hs_pol:1; /*src HS interface polarity*/
|
||||
u32 max_abrst:10; /*max AMBA burst len = 0 (no sw limit*/
|
||||
u32 reload_src:1; /*auto reload src addr =1 if src is P*/
|
||||
u32 reload_dst:1; /*AR destn addr =1 if dstn is P*/
|
||||
} cfgx;
|
||||
u32 cfg_lo;
|
||||
};
|
||||
|
||||
union intel_mid_dma_cfg_hi {
|
||||
struct {
|
||||
u32 fcmode:1; /*flow control mode = 1*/
|
||||
u32 fifo_mode:1; /*FIFO mode select = 1*/
|
||||
u32 protctl:3; /*protection control = 0*/
|
||||
u32 rsvd:2;
|
||||
u32 src_per:4; /*src hw HS interface*/
|
||||
u32 dst_per:4; /*dstn hw HS interface*/
|
||||
u32 reser2:17;
|
||||
} cfgx;
|
||||
u32 cfg_hi;
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* struct intel_mid_dma_chan - internal mid representation of a DMA channel
|
||||
* @chan: dma_chan strcture represetation for mid chan
|
||||
* @ch_regs: MMIO register space pointer to channel register
|
||||
* @dma_base: MMIO register space DMA engine base pointer
|
||||
* @ch_id: DMA channel id
|
||||
* @lock: channel spinlock
|
||||
* @active_list: current active descriptors
|
||||
* @queue: current queued up descriptors
|
||||
* @free_list: current free descriptors
|
||||
* @slave: dma slave structure
|
||||
* @descs_allocated: total number of descriptors allocated
|
||||
* @dma: dma device structure pointer
|
||||
* @busy: bool representing if ch is busy (active txn) or not
|
||||
* @in_use: bool representing if ch is in use or not
|
||||
* @raw_tfr: raw trf interrupt received
|
||||
* @raw_block: raw block interrupt received
|
||||
*/
|
||||
struct intel_mid_dma_chan {
|
||||
struct dma_chan chan;
|
||||
void __iomem *ch_regs;
|
||||
void __iomem *dma_base;
|
||||
int ch_id;
|
||||
spinlock_t lock;
|
||||
struct list_head active_list;
|
||||
struct list_head queue;
|
||||
struct list_head free_list;
|
||||
unsigned int descs_allocated;
|
||||
struct middma_device *dma;
|
||||
bool busy;
|
||||
bool in_use;
|
||||
u32 raw_tfr;
|
||||
u32 raw_block;
|
||||
struct intel_mid_dma_slave *mid_slave;
|
||||
};
|
||||
|
||||
static inline struct intel_mid_dma_chan *to_intel_mid_dma_chan(
|
||||
struct dma_chan *chan)
|
||||
{
|
||||
return container_of(chan, struct intel_mid_dma_chan, chan);
|
||||
}
|
||||
|
||||
enum intel_mid_dma_state {
|
||||
RUNNING = 0,
|
||||
SUSPENDED,
|
||||
};
|
||||
/**
|
||||
* struct middma_device - internal representation of a DMA device
|
||||
* @pdev: PCI device
|
||||
* @dma_base: MMIO register space pointer of DMA
|
||||
* @dma_pool: for allocating DMA descriptors
|
||||
* @common: embedded struct dma_device
|
||||
* @tasklet: dma tasklet for processing interrupts
|
||||
* @ch: per channel data
|
||||
* @pci_id: DMA device PCI ID
|
||||
* @intr_mask: Interrupt mask to be used
|
||||
* @mask_reg: MMIO register for periphral mask
|
||||
* @chan_base: Base ch index (read from driver data)
|
||||
* @max_chan: max number of chs supported (from drv_data)
|
||||
* @block_size: Block size of DMA transfer supported (from drv_data)
|
||||
* @pimr_mask: MMIO register addr for periphral interrupt (from drv_data)
|
||||
* @state: dma PM device state
|
||||
*/
|
||||
struct middma_device {
|
||||
struct pci_dev *pdev;
|
||||
void __iomem *dma_base;
|
||||
struct pci_pool *dma_pool;
|
||||
struct dma_device common;
|
||||
struct tasklet_struct tasklet;
|
||||
struct intel_mid_dma_chan ch[MAX_CHAN];
|
||||
unsigned int pci_id;
|
||||
unsigned int intr_mask;
|
||||
void __iomem *mask_reg;
|
||||
int chan_base;
|
||||
int max_chan;
|
||||
int block_size;
|
||||
unsigned int pimr_mask;
|
||||
enum intel_mid_dma_state state;
|
||||
};
|
||||
|
||||
static inline struct middma_device *to_middma_device(struct dma_device *common)
|
||||
{
|
||||
return container_of(common, struct middma_device, common);
|
||||
}
|
||||
|
||||
struct intel_mid_dma_desc {
|
||||
void __iomem *block; /*ch ptr*/
|
||||
struct list_head desc_node;
|
||||
struct dma_async_tx_descriptor txd;
|
||||
size_t len;
|
||||
dma_addr_t sar;
|
||||
dma_addr_t dar;
|
||||
u32 cfg_hi;
|
||||
u32 cfg_lo;
|
||||
u32 ctl_lo;
|
||||
u32 ctl_hi;
|
||||
struct pci_pool *lli_pool;
|
||||
struct intel_mid_dma_lli *lli;
|
||||
dma_addr_t lli_phys;
|
||||
unsigned int lli_length;
|
||||
unsigned int current_lli;
|
||||
dma_addr_t next;
|
||||
enum dma_transfer_direction dirn;
|
||||
enum dma_status status;
|
||||
enum dma_slave_buswidth width; /*width of DMA txn*/
|
||||
enum intel_mid_dma_mode cfg_mode; /*mode configuration*/
|
||||
|
||||
};
|
||||
|
||||
struct intel_mid_dma_lli {
|
||||
dma_addr_t sar;
|
||||
dma_addr_t dar;
|
||||
dma_addr_t llp;
|
||||
u32 ctl_lo;
|
||||
u32 ctl_hi;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
static inline int test_ch_en(void __iomem *dma, u32 ch_no)
|
||||
{
|
||||
u32 en_reg = ioread32(dma + DMA_CHAN_EN);
|
||||
return (en_reg >> ch_no) & 0x1;
|
||||
}
|
||||
|
||||
static inline struct intel_mid_dma_desc *to_intel_mid_dma_desc
|
||||
(struct dma_async_tx_descriptor *txd)
|
||||
{
|
||||
return container_of(txd, struct intel_mid_dma_desc, txd);
|
||||
}
|
||||
|
||||
static inline struct intel_mid_dma_slave *to_intel_mid_dma_slave
|
||||
(struct dma_slave_config *slave)
|
||||
{
|
||||
return container_of(slave, struct intel_mid_dma_slave, dma_slave);
|
||||
}
|
||||
|
||||
|
||||
int dma_resume(struct device *dev);
|
||||
|
||||
#endif /*__INTEL_MID_DMAC_REGS_H__*/
|
||||
2
drivers/dma/ioat/Makefile
Normal file
2
drivers/dma/ioat/Makefile
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
obj-$(CONFIG_INTEL_IOATDMA) += ioatdma.o
|
||||
ioatdma-y := pci.o dma.o dma_v2.o dma_v3.o dca.o
|
||||
710
drivers/dma/ioat/dca.c
Normal file
710
drivers/dma/ioat/dca.c
Normal file
|
|
@ -0,0 +1,710 @@
|
|||
/*
|
||||
* Intel I/OAT DMA Linux driver
|
||||
* Copyright(c) 2007 - 2009 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/dca.h>
|
||||
|
||||
/* either a kernel change is needed, or we need something like this in kernel */
|
||||
#ifndef CONFIG_SMP
|
||||
#include <asm/smp.h>
|
||||
#undef cpu_physical_id
|
||||
#define cpu_physical_id(cpu) (cpuid_ebx(1) >> 24)
|
||||
#endif
|
||||
|
||||
#include "dma.h"
|
||||
#include "registers.h"
|
||||
#include "dma_v2.h"
|
||||
|
||||
/*
|
||||
* Bit 7 of a tag map entry is the "valid" bit, if it is set then bits 0:6
|
||||
* contain the bit number of the APIC ID to map into the DCA tag. If the valid
|
||||
* bit is not set, then the value must be 0 or 1 and defines the bit in the tag.
|
||||
*/
|
||||
#define DCA_TAG_MAP_VALID 0x80
|
||||
|
||||
#define DCA3_TAG_MAP_BIT_TO_INV 0x80
|
||||
#define DCA3_TAG_MAP_BIT_TO_SEL 0x40
|
||||
#define DCA3_TAG_MAP_LITERAL_VAL 0x1
|
||||
|
||||
#define DCA_TAG_MAP_MASK 0xDF
|
||||
|
||||
/* expected tag map bytes for I/OAT ver.2 */
|
||||
#define DCA2_TAG_MAP_BYTE0 0x80
|
||||
#define DCA2_TAG_MAP_BYTE1 0x0
|
||||
#define DCA2_TAG_MAP_BYTE2 0x81
|
||||
#define DCA2_TAG_MAP_BYTE3 0x82
|
||||
#define DCA2_TAG_MAP_BYTE4 0x82
|
||||
|
||||
/* verify if tag map matches expected values */
|
||||
static inline int dca2_tag_map_valid(u8 *tag_map)
|
||||
{
|
||||
return ((tag_map[0] == DCA2_TAG_MAP_BYTE0) &&
|
||||
(tag_map[1] == DCA2_TAG_MAP_BYTE1) &&
|
||||
(tag_map[2] == DCA2_TAG_MAP_BYTE2) &&
|
||||
(tag_map[3] == DCA2_TAG_MAP_BYTE3) &&
|
||||
(tag_map[4] == DCA2_TAG_MAP_BYTE4));
|
||||
}
|
||||
|
||||
/*
|
||||
* "Legacy" DCA systems do not implement the DCA register set in the
|
||||
* I/OAT device. Software needs direct support for their tag mappings.
|
||||
*/
|
||||
|
||||
#define APICID_BIT(x) (DCA_TAG_MAP_VALID | (x))
|
||||
#define IOAT_TAG_MAP_LEN 8
|
||||
|
||||
static u8 ioat_tag_map_BNB[IOAT_TAG_MAP_LEN] = {
|
||||
1, APICID_BIT(1), APICID_BIT(2), APICID_BIT(2), };
|
||||
static u8 ioat_tag_map_SCNB[IOAT_TAG_MAP_LEN] = {
|
||||
1, APICID_BIT(1), APICID_BIT(2), APICID_BIT(2), };
|
||||
static u8 ioat_tag_map_CNB[IOAT_TAG_MAP_LEN] = {
|
||||
1, APICID_BIT(1), APICID_BIT(3), APICID_BIT(4), APICID_BIT(2), };
|
||||
static u8 ioat_tag_map_UNISYS[IOAT_TAG_MAP_LEN] = { 0 };
|
||||
|
||||
/* pack PCI B/D/F into a u16 */
|
||||
static inline u16 dcaid_from_pcidev(struct pci_dev *pci)
|
||||
{
|
||||
return (pci->bus->number << 8) | pci->devfn;
|
||||
}
|
||||
|
||||
static int dca_enabled_in_bios(struct pci_dev *pdev)
|
||||
{
|
||||
/* CPUID level 9 returns DCA configuration */
|
||||
/* Bit 0 indicates DCA enabled by the BIOS */
|
||||
unsigned long cpuid_level_9;
|
||||
int res;
|
||||
|
||||
cpuid_level_9 = cpuid_eax(9);
|
||||
res = test_bit(0, &cpuid_level_9);
|
||||
if (!res)
|
||||
dev_dbg(&pdev->dev, "DCA is disabled in BIOS\n");
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
int system_has_dca_enabled(struct pci_dev *pdev)
|
||||
{
|
||||
if (boot_cpu_has(X86_FEATURE_DCA))
|
||||
return dca_enabled_in_bios(pdev);
|
||||
|
||||
dev_dbg(&pdev->dev, "boot cpu doesn't have X86_FEATURE_DCA\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct ioat_dca_slot {
|
||||
struct pci_dev *pdev; /* requester device */
|
||||
u16 rid; /* requester id, as used by IOAT */
|
||||
};
|
||||
|
||||
#define IOAT_DCA_MAX_REQ 6
|
||||
#define IOAT3_DCA_MAX_REQ 2
|
||||
|
||||
struct ioat_dca_priv {
|
||||
void __iomem *iobase;
|
||||
void __iomem *dca_base;
|
||||
int max_requesters;
|
||||
int requester_count;
|
||||
u8 tag_map[IOAT_TAG_MAP_LEN];
|
||||
struct ioat_dca_slot req_slots[0];
|
||||
};
|
||||
|
||||
/* 5000 series chipset DCA Port Requester ID Table Entry Format
|
||||
* [15:8] PCI-Express Bus Number
|
||||
* [7:3] PCI-Express Device Number
|
||||
* [2:0] PCI-Express Function Number
|
||||
*
|
||||
* 5000 series chipset DCA control register format
|
||||
* [7:1] Reserved (0)
|
||||
* [0] Ignore Function Number
|
||||
*/
|
||||
|
||||
static int ioat_dca_add_requester(struct dca_provider *dca, struct device *dev)
|
||||
{
|
||||
struct ioat_dca_priv *ioatdca = dca_priv(dca);
|
||||
struct pci_dev *pdev;
|
||||
int i;
|
||||
u16 id;
|
||||
|
||||
/* This implementation only supports PCI-Express */
|
||||
if (!dev_is_pci(dev))
|
||||
return -ENODEV;
|
||||
pdev = to_pci_dev(dev);
|
||||
id = dcaid_from_pcidev(pdev);
|
||||
|
||||
if (ioatdca->requester_count == ioatdca->max_requesters)
|
||||
return -ENODEV;
|
||||
|
||||
for (i = 0; i < ioatdca->max_requesters; i++) {
|
||||
if (ioatdca->req_slots[i].pdev == NULL) {
|
||||
/* found an empty slot */
|
||||
ioatdca->requester_count++;
|
||||
ioatdca->req_slots[i].pdev = pdev;
|
||||
ioatdca->req_slots[i].rid = id;
|
||||
writew(id, ioatdca->dca_base + (i * 4));
|
||||
/* make sure the ignore function bit is off */
|
||||
writeb(0, ioatdca->dca_base + (i * 4) + 2);
|
||||
return i;
|
||||
}
|
||||
}
|
||||
/* Error, ioatdma->requester_count is out of whack */
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
static int ioat_dca_remove_requester(struct dca_provider *dca,
|
||||
struct device *dev)
|
||||
{
|
||||
struct ioat_dca_priv *ioatdca = dca_priv(dca);
|
||||
struct pci_dev *pdev;
|
||||
int i;
|
||||
|
||||
/* This implementation only supports PCI-Express */
|
||||
if (!dev_is_pci(dev))
|
||||
return -ENODEV;
|
||||
pdev = to_pci_dev(dev);
|
||||
|
||||
for (i = 0; i < ioatdca->max_requesters; i++) {
|
||||
if (ioatdca->req_slots[i].pdev == pdev) {
|
||||
writew(0, ioatdca->dca_base + (i * 4));
|
||||
ioatdca->req_slots[i].pdev = NULL;
|
||||
ioatdca->req_slots[i].rid = 0;
|
||||
ioatdca->requester_count--;
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static u8 ioat_dca_get_tag(struct dca_provider *dca,
|
||||
struct device *dev,
|
||||
int cpu)
|
||||
{
|
||||
struct ioat_dca_priv *ioatdca = dca_priv(dca);
|
||||
int i, apic_id, bit, value;
|
||||
u8 entry, tag;
|
||||
|
||||
tag = 0;
|
||||
apic_id = cpu_physical_id(cpu);
|
||||
|
||||
for (i = 0; i < IOAT_TAG_MAP_LEN; i++) {
|
||||
entry = ioatdca->tag_map[i];
|
||||
if (entry & DCA_TAG_MAP_VALID) {
|
||||
bit = entry & ~DCA_TAG_MAP_VALID;
|
||||
value = (apic_id & (1 << bit)) ? 1 : 0;
|
||||
} else {
|
||||
value = entry ? 1 : 0;
|
||||
}
|
||||
tag |= (value << i);
|
||||
}
|
||||
return tag;
|
||||
}
|
||||
|
||||
static int ioat_dca_dev_managed(struct dca_provider *dca,
|
||||
struct device *dev)
|
||||
{
|
||||
struct ioat_dca_priv *ioatdca = dca_priv(dca);
|
||||
struct pci_dev *pdev;
|
||||
int i;
|
||||
|
||||
pdev = to_pci_dev(dev);
|
||||
for (i = 0; i < ioatdca->max_requesters; i++) {
|
||||
if (ioatdca->req_slots[i].pdev == pdev)
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct dca_ops ioat_dca_ops = {
|
||||
.add_requester = ioat_dca_add_requester,
|
||||
.remove_requester = ioat_dca_remove_requester,
|
||||
.get_tag = ioat_dca_get_tag,
|
||||
.dev_managed = ioat_dca_dev_managed,
|
||||
};
|
||||
|
||||
|
||||
struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase)
|
||||
{
|
||||
struct dca_provider *dca;
|
||||
struct ioat_dca_priv *ioatdca;
|
||||
u8 *tag_map = NULL;
|
||||
int i;
|
||||
int err;
|
||||
u8 version;
|
||||
u8 max_requesters;
|
||||
|
||||
if (!system_has_dca_enabled(pdev))
|
||||
return NULL;
|
||||
|
||||
/* I/OAT v1 systems must have a known tag_map to support DCA */
|
||||
switch (pdev->vendor) {
|
||||
case PCI_VENDOR_ID_INTEL:
|
||||
switch (pdev->device) {
|
||||
case PCI_DEVICE_ID_INTEL_IOAT:
|
||||
tag_map = ioat_tag_map_BNB;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_IOAT_CNB:
|
||||
tag_map = ioat_tag_map_CNB;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_IOAT_SCNB:
|
||||
tag_map = ioat_tag_map_SCNB;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case PCI_VENDOR_ID_UNISYS:
|
||||
switch (pdev->device) {
|
||||
case PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR:
|
||||
tag_map = ioat_tag_map_UNISYS;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
if (tag_map == NULL)
|
||||
return NULL;
|
||||
|
||||
version = readb(iobase + IOAT_VER_OFFSET);
|
||||
if (version == IOAT_VER_3_0)
|
||||
max_requesters = IOAT3_DCA_MAX_REQ;
|
||||
else
|
||||
max_requesters = IOAT_DCA_MAX_REQ;
|
||||
|
||||
dca = alloc_dca_provider(&ioat_dca_ops,
|
||||
sizeof(*ioatdca) +
|
||||
(sizeof(struct ioat_dca_slot) * max_requesters));
|
||||
if (!dca)
|
||||
return NULL;
|
||||
|
||||
ioatdca = dca_priv(dca);
|
||||
ioatdca->max_requesters = max_requesters;
|
||||
ioatdca->dca_base = iobase + 0x54;
|
||||
|
||||
/* copy over the APIC ID to DCA tag mapping */
|
||||
for (i = 0; i < IOAT_TAG_MAP_LEN; i++)
|
||||
ioatdca->tag_map[i] = tag_map[i];
|
||||
|
||||
err = register_dca_provider(dca, &pdev->dev);
|
||||
if (err) {
|
||||
free_dca_provider(dca);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return dca;
|
||||
}
|
||||
|
||||
|
||||
static int ioat2_dca_add_requester(struct dca_provider *dca, struct device *dev)
|
||||
{
|
||||
struct ioat_dca_priv *ioatdca = dca_priv(dca);
|
||||
struct pci_dev *pdev;
|
||||
int i;
|
||||
u16 id;
|
||||
u16 global_req_table;
|
||||
|
||||
/* This implementation only supports PCI-Express */
|
||||
if (!dev_is_pci(dev))
|
||||
return -ENODEV;
|
||||
pdev = to_pci_dev(dev);
|
||||
id = dcaid_from_pcidev(pdev);
|
||||
|
||||
if (ioatdca->requester_count == ioatdca->max_requesters)
|
||||
return -ENODEV;
|
||||
|
||||
for (i = 0; i < ioatdca->max_requesters; i++) {
|
||||
if (ioatdca->req_slots[i].pdev == NULL) {
|
||||
/* found an empty slot */
|
||||
ioatdca->requester_count++;
|
||||
ioatdca->req_slots[i].pdev = pdev;
|
||||
ioatdca->req_slots[i].rid = id;
|
||||
global_req_table =
|
||||
readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET);
|
||||
writel(id | IOAT_DCA_GREQID_VALID,
|
||||
ioatdca->iobase + global_req_table + (i * 4));
|
||||
return i;
|
||||
}
|
||||
}
|
||||
/* Error, ioatdma->requester_count is out of whack */
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
static int ioat2_dca_remove_requester(struct dca_provider *dca,
|
||||
struct device *dev)
|
||||
{
|
||||
struct ioat_dca_priv *ioatdca = dca_priv(dca);
|
||||
struct pci_dev *pdev;
|
||||
int i;
|
||||
u16 global_req_table;
|
||||
|
||||
/* This implementation only supports PCI-Express */
|
||||
if (!dev_is_pci(dev))
|
||||
return -ENODEV;
|
||||
pdev = to_pci_dev(dev);
|
||||
|
||||
for (i = 0; i < ioatdca->max_requesters; i++) {
|
||||
if (ioatdca->req_slots[i].pdev == pdev) {
|
||||
global_req_table =
|
||||
readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET);
|
||||
writel(0, ioatdca->iobase + global_req_table + (i * 4));
|
||||
ioatdca->req_slots[i].pdev = NULL;
|
||||
ioatdca->req_slots[i].rid = 0;
|
||||
ioatdca->requester_count--;
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static u8 ioat2_dca_get_tag(struct dca_provider *dca,
|
||||
struct device *dev,
|
||||
int cpu)
|
||||
{
|
||||
u8 tag;
|
||||
|
||||
tag = ioat_dca_get_tag(dca, dev, cpu);
|
||||
tag = (~tag) & 0x1F;
|
||||
return tag;
|
||||
}
|
||||
|
||||
static struct dca_ops ioat2_dca_ops = {
|
||||
.add_requester = ioat2_dca_add_requester,
|
||||
.remove_requester = ioat2_dca_remove_requester,
|
||||
.get_tag = ioat2_dca_get_tag,
|
||||
.dev_managed = ioat_dca_dev_managed,
|
||||
};
|
||||
|
||||
static int ioat2_dca_count_dca_slots(void __iomem *iobase, u16 dca_offset)
|
||||
{
|
||||
int slots = 0;
|
||||
u32 req;
|
||||
u16 global_req_table;
|
||||
|
||||
global_req_table = readw(iobase + dca_offset + IOAT_DCA_GREQID_OFFSET);
|
||||
if (global_req_table == 0)
|
||||
return 0;
|
||||
do {
|
||||
req = readl(iobase + global_req_table + (slots * sizeof(u32)));
|
||||
slots++;
|
||||
} while ((req & IOAT_DCA_GREQID_LASTID) == 0);
|
||||
|
||||
return slots;
|
||||
}
|
||||
|
||||
struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase)
|
||||
{
|
||||
struct dca_provider *dca;
|
||||
struct ioat_dca_priv *ioatdca;
|
||||
int slots;
|
||||
int i;
|
||||
int err;
|
||||
u32 tag_map;
|
||||
u16 dca_offset;
|
||||
u16 csi_fsb_control;
|
||||
u16 pcie_control;
|
||||
u8 bit;
|
||||
|
||||
if (!system_has_dca_enabled(pdev))
|
||||
return NULL;
|
||||
|
||||
dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET);
|
||||
if (dca_offset == 0)
|
||||
return NULL;
|
||||
|
||||
slots = ioat2_dca_count_dca_slots(iobase, dca_offset);
|
||||
if (slots == 0)
|
||||
return NULL;
|
||||
|
||||
dca = alloc_dca_provider(&ioat2_dca_ops,
|
||||
sizeof(*ioatdca)
|
||||
+ (sizeof(struct ioat_dca_slot) * slots));
|
||||
if (!dca)
|
||||
return NULL;
|
||||
|
||||
ioatdca = dca_priv(dca);
|
||||
ioatdca->iobase = iobase;
|
||||
ioatdca->dca_base = iobase + dca_offset;
|
||||
ioatdca->max_requesters = slots;
|
||||
|
||||
/* some bios might not know to turn these on */
|
||||
csi_fsb_control = readw(ioatdca->dca_base + IOAT_FSB_CAP_ENABLE_OFFSET);
|
||||
if ((csi_fsb_control & IOAT_FSB_CAP_ENABLE_PREFETCH) == 0) {
|
||||
csi_fsb_control |= IOAT_FSB_CAP_ENABLE_PREFETCH;
|
||||
writew(csi_fsb_control,
|
||||
ioatdca->dca_base + IOAT_FSB_CAP_ENABLE_OFFSET);
|
||||
}
|
||||
pcie_control = readw(ioatdca->dca_base + IOAT_PCI_CAP_ENABLE_OFFSET);
|
||||
if ((pcie_control & IOAT_PCI_CAP_ENABLE_MEMWR) == 0) {
|
||||
pcie_control |= IOAT_PCI_CAP_ENABLE_MEMWR;
|
||||
writew(pcie_control,
|
||||
ioatdca->dca_base + IOAT_PCI_CAP_ENABLE_OFFSET);
|
||||
}
|
||||
|
||||
|
||||
/* TODO version, compatibility and configuration checks */
|
||||
|
||||
/* copy out the APIC to DCA tag map */
|
||||
tag_map = readl(ioatdca->dca_base + IOAT_APICID_TAG_MAP_OFFSET);
|
||||
for (i = 0; i < 5; i++) {
|
||||
bit = (tag_map >> (4 * i)) & 0x0f;
|
||||
if (bit < 8)
|
||||
ioatdca->tag_map[i] = bit | DCA_TAG_MAP_VALID;
|
||||
else
|
||||
ioatdca->tag_map[i] = 0;
|
||||
}
|
||||
|
||||
if (!dca2_tag_map_valid(ioatdca->tag_map)) {
|
||||
WARN_TAINT_ONCE(1, TAINT_FIRMWARE_WORKAROUND,
|
||||
"%s %s: APICID_TAG_MAP set incorrectly by BIOS, disabling DCA\n",
|
||||
dev_driver_string(&pdev->dev),
|
||||
dev_name(&pdev->dev));
|
||||
free_dca_provider(dca);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
err = register_dca_provider(dca, &pdev->dev);
|
||||
if (err) {
|
||||
free_dca_provider(dca);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return dca;
|
||||
}
|
||||
|
||||
static int ioat3_dca_add_requester(struct dca_provider *dca, struct device *dev)
|
||||
{
|
||||
struct ioat_dca_priv *ioatdca = dca_priv(dca);
|
||||
struct pci_dev *pdev;
|
||||
int i;
|
||||
u16 id;
|
||||
u16 global_req_table;
|
||||
|
||||
/* This implementation only supports PCI-Express */
|
||||
if (!dev_is_pci(dev))
|
||||
return -ENODEV;
|
||||
pdev = to_pci_dev(dev);
|
||||
id = dcaid_from_pcidev(pdev);
|
||||
|
||||
if (ioatdca->requester_count == ioatdca->max_requesters)
|
||||
return -ENODEV;
|
||||
|
||||
for (i = 0; i < ioatdca->max_requesters; i++) {
|
||||
if (ioatdca->req_slots[i].pdev == NULL) {
|
||||
/* found an empty slot */
|
||||
ioatdca->requester_count++;
|
||||
ioatdca->req_slots[i].pdev = pdev;
|
||||
ioatdca->req_slots[i].rid = id;
|
||||
global_req_table =
|
||||
readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET);
|
||||
writel(id | IOAT_DCA_GREQID_VALID,
|
||||
ioatdca->iobase + global_req_table + (i * 4));
|
||||
return i;
|
||||
}
|
||||
}
|
||||
/* Error, ioatdma->requester_count is out of whack */
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
static int ioat3_dca_remove_requester(struct dca_provider *dca,
|
||||
struct device *dev)
|
||||
{
|
||||
struct ioat_dca_priv *ioatdca = dca_priv(dca);
|
||||
struct pci_dev *pdev;
|
||||
int i;
|
||||
u16 global_req_table;
|
||||
|
||||
/* This implementation only supports PCI-Express */
|
||||
if (!dev_is_pci(dev))
|
||||
return -ENODEV;
|
||||
pdev = to_pci_dev(dev);
|
||||
|
||||
for (i = 0; i < ioatdca->max_requesters; i++) {
|
||||
if (ioatdca->req_slots[i].pdev == pdev) {
|
||||
global_req_table =
|
||||
readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET);
|
||||
writel(0, ioatdca->iobase + global_req_table + (i * 4));
|
||||
ioatdca->req_slots[i].pdev = NULL;
|
||||
ioatdca->req_slots[i].rid = 0;
|
||||
ioatdca->requester_count--;
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static u8 ioat3_dca_get_tag(struct dca_provider *dca,
|
||||
struct device *dev,
|
||||
int cpu)
|
||||
{
|
||||
u8 tag;
|
||||
|
||||
struct ioat_dca_priv *ioatdca = dca_priv(dca);
|
||||
int i, apic_id, bit, value;
|
||||
u8 entry;
|
||||
|
||||
tag = 0;
|
||||
apic_id = cpu_physical_id(cpu);
|
||||
|
||||
for (i = 0; i < IOAT_TAG_MAP_LEN; i++) {
|
||||
entry = ioatdca->tag_map[i];
|
||||
if (entry & DCA3_TAG_MAP_BIT_TO_SEL) {
|
||||
bit = entry &
|
||||
~(DCA3_TAG_MAP_BIT_TO_SEL | DCA3_TAG_MAP_BIT_TO_INV);
|
||||
value = (apic_id & (1 << bit)) ? 1 : 0;
|
||||
} else if (entry & DCA3_TAG_MAP_BIT_TO_INV) {
|
||||
bit = entry & ~DCA3_TAG_MAP_BIT_TO_INV;
|
||||
value = (apic_id & (1 << bit)) ? 0 : 1;
|
||||
} else {
|
||||
value = (entry & DCA3_TAG_MAP_LITERAL_VAL) ? 1 : 0;
|
||||
}
|
||||
tag |= (value << i);
|
||||
}
|
||||
|
||||
return tag;
|
||||
}
|
||||
|
||||
static struct dca_ops ioat3_dca_ops = {
|
||||
.add_requester = ioat3_dca_add_requester,
|
||||
.remove_requester = ioat3_dca_remove_requester,
|
||||
.get_tag = ioat3_dca_get_tag,
|
||||
.dev_managed = ioat_dca_dev_managed,
|
||||
};
|
||||
|
||||
static int ioat3_dca_count_dca_slots(void *iobase, u16 dca_offset)
|
||||
{
|
||||
int slots = 0;
|
||||
u32 req;
|
||||
u16 global_req_table;
|
||||
|
||||
global_req_table = readw(iobase + dca_offset + IOAT3_DCA_GREQID_OFFSET);
|
||||
if (global_req_table == 0)
|
||||
return 0;
|
||||
|
||||
do {
|
||||
req = readl(iobase + global_req_table + (slots * sizeof(u32)));
|
||||
slots++;
|
||||
} while ((req & IOAT_DCA_GREQID_LASTID) == 0);
|
||||
|
||||
return slots;
|
||||
}
|
||||
|
||||
static inline int dca3_tag_map_invalid(u8 *tag_map)
|
||||
{
|
||||
/*
|
||||
* If the tag map is not programmed by the BIOS the default is:
|
||||
* 0x80 0x80 0x80 0x80 0x80 0x00 0x00 0x00
|
||||
*
|
||||
* This an invalid map and will result in only 2 possible tags
|
||||
* 0x1F and 0x00. 0x00 is an invalid DCA tag so we know that
|
||||
* this entire definition is invalid.
|
||||
*/
|
||||
return ((tag_map[0] == DCA_TAG_MAP_VALID) &&
|
||||
(tag_map[1] == DCA_TAG_MAP_VALID) &&
|
||||
(tag_map[2] == DCA_TAG_MAP_VALID) &&
|
||||
(tag_map[3] == DCA_TAG_MAP_VALID) &&
|
||||
(tag_map[4] == DCA_TAG_MAP_VALID));
|
||||
}
|
||||
|
||||
struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase)
|
||||
{
|
||||
struct dca_provider *dca;
|
||||
struct ioat_dca_priv *ioatdca;
|
||||
int slots;
|
||||
int i;
|
||||
int err;
|
||||
u16 dca_offset;
|
||||
u16 csi_fsb_control;
|
||||
u16 pcie_control;
|
||||
u8 bit;
|
||||
|
||||
union {
|
||||
u64 full;
|
||||
struct {
|
||||
u32 low;
|
||||
u32 high;
|
||||
};
|
||||
} tag_map;
|
||||
|
||||
if (!system_has_dca_enabled(pdev))
|
||||
return NULL;
|
||||
|
||||
dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET);
|
||||
if (dca_offset == 0)
|
||||
return NULL;
|
||||
|
||||
slots = ioat3_dca_count_dca_slots(iobase, dca_offset);
|
||||
if (slots == 0)
|
||||
return NULL;
|
||||
|
||||
dca = alloc_dca_provider(&ioat3_dca_ops,
|
||||
sizeof(*ioatdca)
|
||||
+ (sizeof(struct ioat_dca_slot) * slots));
|
||||
if (!dca)
|
||||
return NULL;
|
||||
|
||||
ioatdca = dca_priv(dca);
|
||||
ioatdca->iobase = iobase;
|
||||
ioatdca->dca_base = iobase + dca_offset;
|
||||
ioatdca->max_requesters = slots;
|
||||
|
||||
/* some bios might not know to turn these on */
|
||||
csi_fsb_control = readw(ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET);
|
||||
if ((csi_fsb_control & IOAT3_CSI_CONTROL_PREFETCH) == 0) {
|
||||
csi_fsb_control |= IOAT3_CSI_CONTROL_PREFETCH;
|
||||
writew(csi_fsb_control,
|
||||
ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET);
|
||||
}
|
||||
pcie_control = readw(ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET);
|
||||
if ((pcie_control & IOAT3_PCI_CONTROL_MEMWR) == 0) {
|
||||
pcie_control |= IOAT3_PCI_CONTROL_MEMWR;
|
||||
writew(pcie_control,
|
||||
ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET);
|
||||
}
|
||||
|
||||
|
||||
/* TODO version, compatibility and configuration checks */
|
||||
|
||||
/* copy out the APIC to DCA tag map */
|
||||
tag_map.low =
|
||||
readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_LOW);
|
||||
tag_map.high =
|
||||
readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_HIGH);
|
||||
for (i = 0; i < 8; i++) {
|
||||
bit = tag_map.full >> (8 * i);
|
||||
ioatdca->tag_map[i] = bit & DCA_TAG_MAP_MASK;
|
||||
}
|
||||
|
||||
if (dca3_tag_map_invalid(ioatdca->tag_map)) {
|
||||
WARN_TAINT_ONCE(1, TAINT_FIRMWARE_WORKAROUND,
|
||||
"%s %s: APICID_TAG_MAP set incorrectly by BIOS, disabling DCA\n",
|
||||
dev_driver_string(&pdev->dev),
|
||||
dev_name(&pdev->dev));
|
||||
free_dca_provider(dca);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
err = register_dca_provider(dca, &pdev->dev);
|
||||
if (err) {
|
||||
free_dca_provider(dca);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return dca;
|
||||
}
|
||||
1250
drivers/dma/ioat/dma.c
Normal file
1250
drivers/dma/ioat/dma.c
Normal file
File diff suppressed because it is too large
Load diff
356
drivers/dma/ioat/dma.h
Normal file
356
drivers/dma/ioat/dma.h
Normal file
|
|
@ -0,0 +1,356 @@
|
|||
/*
|
||||
* Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called COPYING.
|
||||
*/
|
||||
#ifndef IOATDMA_H
|
||||
#define IOATDMA_H
|
||||
|
||||
#include <linux/dmaengine.h>
|
||||
#include "hw.h"
|
||||
#include "registers.h"
|
||||
#include <linux/init.h>
|
||||
#include <linux/dmapool.h>
|
||||
#include <linux/cache.h>
|
||||
#include <linux/pci_ids.h>
|
||||
#include <net/tcp.h>
|
||||
|
||||
#define IOAT_DMA_VERSION "4.00"
|
||||
|
||||
#define IOAT_LOW_COMPLETION_MASK 0xffffffc0
|
||||
#define IOAT_DMA_DCA_ANY_CPU ~0
|
||||
|
||||
#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
|
||||
#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
|
||||
#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
|
||||
#define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
|
||||
#define to_pdev(ioat_chan) ((ioat_chan)->device->pdev)
|
||||
|
||||
#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
|
||||
|
||||
/*
|
||||
* workaround for IOAT ver.3.0 null descriptor issue
|
||||
* (channel returns error when size is 0)
|
||||
*/
|
||||
#define NULL_DESC_BUFFER_SIZE 1
|
||||
|
||||
enum ioat_irq_mode {
|
||||
IOAT_NOIRQ = 0,
|
||||
IOAT_MSIX,
|
||||
IOAT_MSI,
|
||||
IOAT_INTX
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ioatdma_device - internal representation of a IOAT device
|
||||
* @pdev: PCI-Express device
|
||||
* @reg_base: MMIO register space base address
|
||||
* @dma_pool: for allocating DMA descriptors
|
||||
* @common: embedded struct dma_device
|
||||
* @version: version of ioatdma device
|
||||
* @msix_entries: irq handlers
|
||||
* @idx: per channel data
|
||||
* @dca: direct cache access context
|
||||
* @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
|
||||
* @enumerate_channels: hw version specific channel enumeration
|
||||
* @reset_hw: hw version specific channel (re)initialization
|
||||
* @cleanup_fn: select between the v2 and v3 cleanup routines
|
||||
* @timer_fn: select between the v2 and v3 timer watchdog routines
|
||||
* @self_test: hardware version specific self test for each supported op type
|
||||
*
|
||||
* Note: the v3 cleanup routine supports raid operations
|
||||
*/
|
||||
struct ioatdma_device {
|
||||
struct pci_dev *pdev;
|
||||
void __iomem *reg_base;
|
||||
struct pci_pool *dma_pool;
|
||||
struct pci_pool *completion_pool;
|
||||
#define MAX_SED_POOLS 5
|
||||
struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
|
||||
struct dma_device common;
|
||||
u8 version;
|
||||
struct msix_entry msix_entries[4];
|
||||
struct ioat_chan_common *idx[4];
|
||||
struct dca_provider *dca;
|
||||
enum ioat_irq_mode irq_mode;
|
||||
u32 cap;
|
||||
void (*intr_quirk)(struct ioatdma_device *device);
|
||||
int (*enumerate_channels)(struct ioatdma_device *device);
|
||||
int (*reset_hw)(struct ioat_chan_common *chan);
|
||||
void (*cleanup_fn)(unsigned long data);
|
||||
void (*timer_fn)(unsigned long data);
|
||||
int (*self_test)(struct ioatdma_device *device);
|
||||
};
|
||||
|
||||
struct ioat_chan_common {
|
||||
struct dma_chan common;
|
||||
void __iomem *reg_base;
|
||||
dma_addr_t last_completion;
|
||||
spinlock_t cleanup_lock;
|
||||
unsigned long state;
|
||||
#define IOAT_COMPLETION_PENDING 0
|
||||
#define IOAT_COMPLETION_ACK 1
|
||||
#define IOAT_RESET_PENDING 2
|
||||
#define IOAT_KOBJ_INIT_FAIL 3
|
||||
#define IOAT_RESHAPE_PENDING 4
|
||||
#define IOAT_RUN 5
|
||||
#define IOAT_CHAN_ACTIVE 6
|
||||
struct timer_list timer;
|
||||
#define COMPLETION_TIMEOUT msecs_to_jiffies(100)
|
||||
#define IDLE_TIMEOUT msecs_to_jiffies(2000)
|
||||
#define RESET_DELAY msecs_to_jiffies(100)
|
||||
struct ioatdma_device *device;
|
||||
dma_addr_t completion_dma;
|
||||
u64 *completion;
|
||||
struct tasklet_struct cleanup_task;
|
||||
struct kobject kobj;
|
||||
};
|
||||
|
||||
struct ioat_sysfs_entry {
|
||||
struct attribute attr;
|
||||
ssize_t (*show)(struct dma_chan *, char *);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ioat_dma_chan - internal representation of a DMA channel
|
||||
*/
|
||||
struct ioat_dma_chan {
|
||||
struct ioat_chan_common base;
|
||||
|
||||
size_t xfercap; /* XFERCAP register value expanded out */
|
||||
|
||||
spinlock_t desc_lock;
|
||||
struct list_head free_desc;
|
||||
struct list_head used_desc;
|
||||
|
||||
int pending;
|
||||
u16 desccount;
|
||||
u16 active;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ioat_sed_ent - wrapper around super extended hardware descriptor
|
||||
* @hw: hardware SED
|
||||
* @sed_dma: dma address for the SED
|
||||
* @list: list member
|
||||
* @parent: point to the dma descriptor that's the parent
|
||||
*/
|
||||
struct ioat_sed_ent {
|
||||
struct ioat_sed_raw_descriptor *hw;
|
||||
dma_addr_t dma;
|
||||
struct ioat_ring_ent *parent;
|
||||
unsigned int hw_pool;
|
||||
};
|
||||
|
||||
static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c)
|
||||
{
|
||||
return container_of(c, struct ioat_chan_common, common);
|
||||
}
|
||||
|
||||
static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
|
||||
{
|
||||
struct ioat_chan_common *chan = to_chan_common(c);
|
||||
|
||||
return container_of(chan, struct ioat_dma_chan, base);
|
||||
}
|
||||
|
||||
/* wrapper around hardware descriptor format + additional software fields */
|
||||
|
||||
/**
|
||||
* struct ioat_desc_sw - wrapper around hardware descriptor
|
||||
* @hw: hardware DMA descriptor (for memcpy)
|
||||
* @node: this descriptor will either be on the free list,
|
||||
* or attached to a transaction list (tx_list)
|
||||
* @txd: the generic software descriptor for all engines
|
||||
* @id: identifier for debug
|
||||
*/
|
||||
struct ioat_desc_sw {
|
||||
struct ioat_dma_descriptor *hw;
|
||||
struct list_head node;
|
||||
size_t len;
|
||||
struct list_head tx_list;
|
||||
struct dma_async_tx_descriptor txd;
|
||||
#ifdef DEBUG
|
||||
int id;
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef DEBUG
|
||||
#define set_desc_id(desc, i) ((desc)->id = (i))
|
||||
#define desc_id(desc) ((desc)->id)
|
||||
#else
|
||||
#define set_desc_id(desc, i)
|
||||
#define desc_id(desc) (0)
|
||||
#endif
|
||||
|
||||
static inline void
|
||||
__dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw,
|
||||
struct dma_async_tx_descriptor *tx, int id)
|
||||
{
|
||||
struct device *dev = to_dev(chan);
|
||||
|
||||
dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
|
||||
" ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id,
|
||||
(unsigned long long) tx->phys,
|
||||
(unsigned long long) hw->next, tx->cookie, tx->flags,
|
||||
hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
|
||||
}
|
||||
|
||||
#define dump_desc_dbg(c, d) \
|
||||
({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; })
|
||||
|
||||
static inline struct ioat_chan_common *
|
||||
ioat_chan_by_index(struct ioatdma_device *device, int index)
|
||||
{
|
||||
return device->idx[index];
|
||||
}
|
||||
|
||||
static inline u64 ioat_chansts_32(struct ioat_chan_common *chan)
|
||||
{
|
||||
u8 ver = chan->device->version;
|
||||
u64 status;
|
||||
u32 status_lo;
|
||||
|
||||
/* We need to read the low address first as this causes the
|
||||
* chipset to latch the upper bits for the subsequent read
|
||||
*/
|
||||
status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
|
||||
status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
|
||||
status <<= 32;
|
||||
status |= status_lo;
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
#if BITS_PER_LONG == 64
|
||||
|
||||
static inline u64 ioat_chansts(struct ioat_chan_common *chan)
|
||||
{
|
||||
u8 ver = chan->device->version;
|
||||
u64 status;
|
||||
|
||||
/* With IOAT v3.3 the status register is 64bit. */
|
||||
if (ver >= IOAT_VER_3_3)
|
||||
status = readq(chan->reg_base + IOAT_CHANSTS_OFFSET(ver));
|
||||
else
|
||||
status = ioat_chansts_32(chan);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
#else
|
||||
#define ioat_chansts ioat_chansts_32
|
||||
#endif
|
||||
|
||||
static inline void ioat_start(struct ioat_chan_common *chan)
|
||||
{
|
||||
u8 ver = chan->device->version;
|
||||
|
||||
writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
|
||||
}
|
||||
|
||||
static inline u64 ioat_chansts_to_addr(u64 status)
|
||||
{
|
||||
return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
|
||||
}
|
||||
|
||||
static inline u32 ioat_chanerr(struct ioat_chan_common *chan)
|
||||
{
|
||||
return readl(chan->reg_base + IOAT_CHANERR_OFFSET);
|
||||
}
|
||||
|
||||
static inline void ioat_suspend(struct ioat_chan_common *chan)
|
||||
{
|
||||
u8 ver = chan->device->version;
|
||||
|
||||
writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
|
||||
}
|
||||
|
||||
static inline void ioat_reset(struct ioat_chan_common *chan)
|
||||
{
|
||||
u8 ver = chan->device->version;
|
||||
|
||||
writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
|
||||
}
|
||||
|
||||
static inline bool ioat_reset_pending(struct ioat_chan_common *chan)
|
||||
{
|
||||
u8 ver = chan->device->version;
|
||||
u8 cmd;
|
||||
|
||||
cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
|
||||
return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
|
||||
}
|
||||
|
||||
static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr)
|
||||
{
|
||||
struct ioat_chan_common *chan = &ioat->base;
|
||||
|
||||
writel(addr & 0x00000000FFFFFFFF,
|
||||
chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
|
||||
writel(addr >> 32,
|
||||
chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
|
||||
}
|
||||
|
||||
static inline bool is_ioat_active(unsigned long status)
|
||||
{
|
||||
return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
|
||||
}
|
||||
|
||||
static inline bool is_ioat_idle(unsigned long status)
|
||||
{
|
||||
return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
|
||||
}
|
||||
|
||||
static inline bool is_ioat_halted(unsigned long status)
|
||||
{
|
||||
return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
|
||||
}
|
||||
|
||||
static inline bool is_ioat_suspended(unsigned long status)
|
||||
{
|
||||
return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
|
||||
}
|
||||
|
||||
/* channel was fatally programmed */
|
||||
static inline bool is_ioat_bug(unsigned long err)
|
||||
{
|
||||
return !!err;
|
||||
}
|
||||
|
||||
int ioat_probe(struct ioatdma_device *device);
|
||||
int ioat_register(struct ioatdma_device *device);
|
||||
int ioat1_dma_probe(struct ioatdma_device *dev, int dca);
|
||||
int ioat_dma_self_test(struct ioatdma_device *device);
|
||||
void ioat_dma_remove(struct ioatdma_device *device);
|
||||
struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
|
||||
dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan);
|
||||
void ioat_init_channel(struct ioatdma_device *device,
|
||||
struct ioat_chan_common *chan, int idx);
|
||||
enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
|
||||
struct dma_tx_state *txstate);
|
||||
bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
|
||||
dma_addr_t *phys_complete);
|
||||
void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type);
|
||||
void ioat_kobject_del(struct ioatdma_device *device);
|
||||
int ioat_dma_setup_interrupts(struct ioatdma_device *device);
|
||||
void ioat_stop(struct ioat_chan_common *chan);
|
||||
extern const struct sysfs_ops ioat_sysfs_ops;
|
||||
extern struct ioat_sysfs_entry ioat_version_attr;
|
||||
extern struct ioat_sysfs_entry ioat_cap_attr;
|
||||
#endif /* IOATDMA_H */
|
||||
920
drivers/dma/ioat/dma_v2.c
Normal file
920
drivers/dma/ioat/dma_v2.c
Normal file
|
|
@ -0,0 +1,920 @@
|
|||
/*
|
||||
* Intel I/OAT DMA Linux driver
|
||||
* Copyright(c) 2004 - 2009 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* This driver supports an Intel I/OAT DMA engine (versions >= 2), which
|
||||
* does asynchronous data movement and checksumming operations.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/prefetch.h>
|
||||
#include <linux/i7300_idle.h>
|
||||
#include "dma.h"
|
||||
#include "dma_v2.h"
|
||||
#include "registers.h"
|
||||
#include "hw.h"
|
||||
|
||||
#include "../dmaengine.h"
|
||||
|
||||
int ioat_ring_alloc_order = 8;
|
||||
module_param(ioat_ring_alloc_order, int, 0644);
|
||||
MODULE_PARM_DESC(ioat_ring_alloc_order,
|
||||
"ioat2+: allocate 2^n descriptors per channel"
|
||||
" (default: 8 max: 16)");
|
||||
static int ioat_ring_max_alloc_order = IOAT_MAX_ORDER;
|
||||
module_param(ioat_ring_max_alloc_order, int, 0644);
|
||||
MODULE_PARM_DESC(ioat_ring_max_alloc_order,
|
||||
"ioat2+: upper limit for ring size (default: 16)");
|
||||
|
||||
void __ioat2_issue_pending(struct ioat2_dma_chan *ioat)
|
||||
{
|
||||
struct ioat_chan_common *chan = &ioat->base;
|
||||
|
||||
ioat->dmacount += ioat2_ring_pending(ioat);
|
||||
ioat->issued = ioat->head;
|
||||
writew(ioat->dmacount, chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
|
||||
dev_dbg(to_dev(chan),
|
||||
"%s: head: %#x tail: %#x issued: %#x count: %#x\n",
|
||||
__func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
|
||||
}
|
||||
|
||||
void ioat2_issue_pending(struct dma_chan *c)
|
||||
{
|
||||
struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
|
||||
|
||||
if (ioat2_ring_pending(ioat)) {
|
||||
spin_lock_bh(&ioat->prep_lock);
|
||||
__ioat2_issue_pending(ioat);
|
||||
spin_unlock_bh(&ioat->prep_lock);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* ioat2_update_pending - log pending descriptors
|
||||
* @ioat: ioat2+ channel
|
||||
*
|
||||
* Check if the number of unsubmitted descriptors has exceeded the
|
||||
* watermark. Called with prep_lock held
|
||||
*/
|
||||
static void ioat2_update_pending(struct ioat2_dma_chan *ioat)
|
||||
{
|
||||
if (ioat2_ring_pending(ioat) > ioat_pending_level)
|
||||
__ioat2_issue_pending(ioat);
|
||||
}
|
||||
|
||||
static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
|
||||
{
|
||||
struct ioat_ring_ent *desc;
|
||||
struct ioat_dma_descriptor *hw;
|
||||
|
||||
if (ioat2_ring_space(ioat) < 1) {
|
||||
dev_err(to_dev(&ioat->base),
|
||||
"Unable to start null desc - ring full\n");
|
||||
return;
|
||||
}
|
||||
|
||||
dev_dbg(to_dev(&ioat->base), "%s: head: %#x tail: %#x issued: %#x\n",
|
||||
__func__, ioat->head, ioat->tail, ioat->issued);
|
||||
desc = ioat2_get_ring_ent(ioat, ioat->head);
|
||||
|
||||
hw = desc->hw;
|
||||
hw->ctl = 0;
|
||||
hw->ctl_f.null = 1;
|
||||
hw->ctl_f.int_en = 1;
|
||||
hw->ctl_f.compl_write = 1;
|
||||
/* set size to non-zero value (channel returns error when size is 0) */
|
||||
hw->size = NULL_DESC_BUFFER_SIZE;
|
||||
hw->src_addr = 0;
|
||||
hw->dst_addr = 0;
|
||||
async_tx_ack(&desc->txd);
|
||||
ioat2_set_chainaddr(ioat, desc->txd.phys);
|
||||
dump_desc_dbg(ioat, desc);
|
||||
wmb();
|
||||
ioat->head += 1;
|
||||
__ioat2_issue_pending(ioat);
|
||||
}
|
||||
|
||||
static void ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
|
||||
{
|
||||
spin_lock_bh(&ioat->prep_lock);
|
||||
__ioat2_start_null_desc(ioat);
|
||||
spin_unlock_bh(&ioat->prep_lock);
|
||||
}
|
||||
|
||||
static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete)
|
||||
{
|
||||
struct ioat_chan_common *chan = &ioat->base;
|
||||
struct dma_async_tx_descriptor *tx;
|
||||
struct ioat_ring_ent *desc;
|
||||
bool seen_current = false;
|
||||
u16 active;
|
||||
int idx = ioat->tail, i;
|
||||
|
||||
dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
|
||||
__func__, ioat->head, ioat->tail, ioat->issued);
|
||||
|
||||
active = ioat2_ring_active(ioat);
|
||||
for (i = 0; i < active && !seen_current; i++) {
|
||||
smp_read_barrier_depends();
|
||||
prefetch(ioat2_get_ring_ent(ioat, idx + i + 1));
|
||||
desc = ioat2_get_ring_ent(ioat, idx + i);
|
||||
tx = &desc->txd;
|
||||
dump_desc_dbg(ioat, desc);
|
||||
if (tx->cookie) {
|
||||
dma_descriptor_unmap(tx);
|
||||
dma_cookie_complete(tx);
|
||||
if (tx->callback) {
|
||||
tx->callback(tx->callback_param);
|
||||
tx->callback = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
if (tx->phys == phys_complete)
|
||||
seen_current = true;
|
||||
}
|
||||
smp_mb(); /* finish all descriptor reads before incrementing tail */
|
||||
ioat->tail = idx + i;
|
||||
BUG_ON(active && !seen_current); /* no active descs have written a completion? */
|
||||
|
||||
chan->last_completion = phys_complete;
|
||||
if (active - i == 0) {
|
||||
dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
|
||||
__func__);
|
||||
clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
|
||||
mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* ioat2_cleanup - clean finished descriptors (advance tail pointer)
|
||||
* @chan: ioat channel to be cleaned up
|
||||
*/
|
||||
static void ioat2_cleanup(struct ioat2_dma_chan *ioat)
|
||||
{
|
||||
struct ioat_chan_common *chan = &ioat->base;
|
||||
dma_addr_t phys_complete;
|
||||
|
||||
spin_lock_bh(&chan->cleanup_lock);
|
||||
if (ioat_cleanup_preamble(chan, &phys_complete))
|
||||
__cleanup(ioat, phys_complete);
|
||||
spin_unlock_bh(&chan->cleanup_lock);
|
||||
}
|
||||
|
||||
void ioat2_cleanup_event(unsigned long data)
|
||||
{
|
||||
struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data);
|
||||
struct ioat_chan_common *chan = &ioat->base;
|
||||
|
||||
ioat2_cleanup(ioat);
|
||||
if (!test_bit(IOAT_RUN, &chan->state))
|
||||
return;
|
||||
writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
|
||||
}
|
||||
|
||||
void __ioat2_restart_chan(struct ioat2_dma_chan *ioat)
|
||||
{
|
||||
struct ioat_chan_common *chan = &ioat->base;
|
||||
|
||||
/* set the tail to be re-issued */
|
||||
ioat->issued = ioat->tail;
|
||||
ioat->dmacount = 0;
|
||||
set_bit(IOAT_COMPLETION_PENDING, &chan->state);
|
||||
mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
|
||||
|
||||
dev_dbg(to_dev(chan),
|
||||
"%s: head: %#x tail: %#x issued: %#x count: %#x\n",
|
||||
__func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
|
||||
|
||||
if (ioat2_ring_pending(ioat)) {
|
||||
struct ioat_ring_ent *desc;
|
||||
|
||||
desc = ioat2_get_ring_ent(ioat, ioat->tail);
|
||||
ioat2_set_chainaddr(ioat, desc->txd.phys);
|
||||
__ioat2_issue_pending(ioat);
|
||||
} else
|
||||
__ioat2_start_null_desc(ioat);
|
||||
}
|
||||
|
||||
int ioat2_quiesce(struct ioat_chan_common *chan, unsigned long tmo)
|
||||
{
|
||||
unsigned long end = jiffies + tmo;
|
||||
int err = 0;
|
||||
u32 status;
|
||||
|
||||
status = ioat_chansts(chan);
|
||||
if (is_ioat_active(status) || is_ioat_idle(status))
|
||||
ioat_suspend(chan);
|
||||
while (is_ioat_active(status) || is_ioat_idle(status)) {
|
||||
if (tmo && time_after(jiffies, end)) {
|
||||
err = -ETIMEDOUT;
|
||||
break;
|
||||
}
|
||||
status = ioat_chansts(chan);
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
int ioat2_reset_sync(struct ioat_chan_common *chan, unsigned long tmo)
|
||||
{
|
||||
unsigned long end = jiffies + tmo;
|
||||
int err = 0;
|
||||
|
||||
ioat_reset(chan);
|
||||
while (ioat_reset_pending(chan)) {
|
||||
if (end && time_after(jiffies, end)) {
|
||||
err = -ETIMEDOUT;
|
||||
break;
|
||||
}
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void ioat2_restart_channel(struct ioat2_dma_chan *ioat)
|
||||
{
|
||||
struct ioat_chan_common *chan = &ioat->base;
|
||||
dma_addr_t phys_complete;
|
||||
|
||||
ioat2_quiesce(chan, 0);
|
||||
if (ioat_cleanup_preamble(chan, &phys_complete))
|
||||
__cleanup(ioat, phys_complete);
|
||||
|
||||
__ioat2_restart_chan(ioat);
|
||||
}
|
||||
|
||||
static void check_active(struct ioat2_dma_chan *ioat)
|
||||
{
|
||||
struct ioat_chan_common *chan = &ioat->base;
|
||||
|
||||
if (ioat2_ring_active(ioat)) {
|
||||
mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
|
||||
return;
|
||||
}
|
||||
|
||||
if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &chan->state))
|
||||
mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
|
||||
else if (ioat->alloc_order > ioat_get_alloc_order()) {
|
||||
/* if the ring is idle, empty, and oversized try to step
|
||||
* down the size
|
||||
*/
|
||||
reshape_ring(ioat, ioat->alloc_order - 1);
|
||||
|
||||
/* keep shrinking until we get back to our minimum
|
||||
* default size
|
||||
*/
|
||||
if (ioat->alloc_order > ioat_get_alloc_order())
|
||||
mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void ioat2_timer_event(unsigned long data)
|
||||
{
|
||||
struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data);
|
||||
struct ioat_chan_common *chan = &ioat->base;
|
||||
dma_addr_t phys_complete;
|
||||
u64 status;
|
||||
|
||||
status = ioat_chansts(chan);
|
||||
|
||||
/* when halted due to errors check for channel
|
||||
* programming errors before advancing the completion state
|
||||
*/
|
||||
if (is_ioat_halted(status)) {
|
||||
u32 chanerr;
|
||||
|
||||
chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
|
||||
dev_err(to_dev(chan), "%s: Channel halted (%x)\n",
|
||||
__func__, chanerr);
|
||||
if (test_bit(IOAT_RUN, &chan->state))
|
||||
BUG_ON(is_ioat_bug(chanerr));
|
||||
else /* we never got off the ground */
|
||||
return;
|
||||
}
|
||||
|
||||
/* if we haven't made progress and we have already
|
||||
* acknowledged a pending completion once, then be more
|
||||
* forceful with a restart
|
||||
*/
|
||||
spin_lock_bh(&chan->cleanup_lock);
|
||||
if (ioat_cleanup_preamble(chan, &phys_complete))
|
||||
__cleanup(ioat, phys_complete);
|
||||
else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) {
|
||||
spin_lock_bh(&ioat->prep_lock);
|
||||
ioat2_restart_channel(ioat);
|
||||
spin_unlock_bh(&ioat->prep_lock);
|
||||
spin_unlock_bh(&chan->cleanup_lock);
|
||||
return;
|
||||
} else {
|
||||
set_bit(IOAT_COMPLETION_ACK, &chan->state);
|
||||
mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
|
||||
}
|
||||
|
||||
|
||||
if (ioat2_ring_active(ioat))
|
||||
mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
|
||||
else {
|
||||
spin_lock_bh(&ioat->prep_lock);
|
||||
check_active(ioat);
|
||||
spin_unlock_bh(&ioat->prep_lock);
|
||||
}
|
||||
spin_unlock_bh(&chan->cleanup_lock);
|
||||
}
|
||||
|
||||
static int ioat2_reset_hw(struct ioat_chan_common *chan)
|
||||
{
|
||||
/* throw away whatever the channel was doing and get it initialized */
|
||||
u32 chanerr;
|
||||
|
||||
ioat2_quiesce(chan, msecs_to_jiffies(100));
|
||||
|
||||
chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
|
||||
writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
|
||||
|
||||
return ioat2_reset_sync(chan, msecs_to_jiffies(200));
|
||||
}
|
||||
|
||||
/**
|
||||
* ioat2_enumerate_channels - find and initialize the device's channels
|
||||
* @device: the device to be enumerated
|
||||
*/
|
||||
int ioat2_enumerate_channels(struct ioatdma_device *device)
|
||||
{
|
||||
struct ioat2_dma_chan *ioat;
|
||||
struct device *dev = &device->pdev->dev;
|
||||
struct dma_device *dma = &device->common;
|
||||
u8 xfercap_log;
|
||||
int i;
|
||||
|
||||
INIT_LIST_HEAD(&dma->channels);
|
||||
dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
|
||||
dma->chancnt &= 0x1f; /* bits [4:0] valid */
|
||||
if (dma->chancnt > ARRAY_SIZE(device->idx)) {
|
||||
dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
|
||||
dma->chancnt, ARRAY_SIZE(device->idx));
|
||||
dma->chancnt = ARRAY_SIZE(device->idx);
|
||||
}
|
||||
xfercap_log = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
|
||||
xfercap_log &= 0x1f; /* bits [4:0] valid */
|
||||
if (xfercap_log == 0)
|
||||
return 0;
|
||||
dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
|
||||
|
||||
/* FIXME which i/oat version is i7300? */
|
||||
#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
|
||||
if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
|
||||
dma->chancnt--;
|
||||
#endif
|
||||
for (i = 0; i < dma->chancnt; i++) {
|
||||
ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
|
||||
if (!ioat)
|
||||
break;
|
||||
|
||||
ioat_init_channel(device, &ioat->base, i);
|
||||
ioat->xfercap_log = xfercap_log;
|
||||
spin_lock_init(&ioat->prep_lock);
|
||||
if (device->reset_hw(&ioat->base)) {
|
||||
i = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
dma->chancnt = i;
|
||||
return i;
|
||||
}
|
||||
|
||||
static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
|
||||
{
|
||||
struct dma_chan *c = tx->chan;
|
||||
struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
|
||||
struct ioat_chan_common *chan = &ioat->base;
|
||||
dma_cookie_t cookie;
|
||||
|
||||
cookie = dma_cookie_assign(tx);
|
||||
dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
|
||||
|
||||
if (!test_and_set_bit(IOAT_CHAN_ACTIVE, &chan->state))
|
||||
mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
|
||||
|
||||
/* make descriptor updates visible before advancing ioat->head,
|
||||
* this is purposefully not smp_wmb() since we are also
|
||||
* publishing the descriptor updates to a dma device
|
||||
*/
|
||||
wmb();
|
||||
|
||||
ioat->head += ioat->produce;
|
||||
|
||||
ioat2_update_pending(ioat);
|
||||
spin_unlock_bh(&ioat->prep_lock);
|
||||
|
||||
return cookie;
|
||||
}
|
||||
|
||||
static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan, gfp_t flags)
|
||||
{
|
||||
struct ioat_dma_descriptor *hw;
|
||||
struct ioat_ring_ent *desc;
|
||||
struct ioatdma_device *dma;
|
||||
dma_addr_t phys;
|
||||
|
||||
dma = to_ioatdma_device(chan->device);
|
||||
hw = pci_pool_alloc(dma->dma_pool, flags, &phys);
|
||||
if (!hw)
|
||||
return NULL;
|
||||
memset(hw, 0, sizeof(*hw));
|
||||
|
||||
desc = kmem_cache_zalloc(ioat2_cache, flags);
|
||||
if (!desc) {
|
||||
pci_pool_free(dma->dma_pool, hw, phys);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
dma_async_tx_descriptor_init(&desc->txd, chan);
|
||||
desc->txd.tx_submit = ioat2_tx_submit_unlock;
|
||||
desc->hw = hw;
|
||||
desc->txd.phys = phys;
|
||||
return desc;
|
||||
}
|
||||
|
||||
static void ioat2_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan)
|
||||
{
|
||||
struct ioatdma_device *dma;
|
||||
|
||||
dma = to_ioatdma_device(chan->device);
|
||||
pci_pool_free(dma->dma_pool, desc->hw, desc->txd.phys);
|
||||
kmem_cache_free(ioat2_cache, desc);
|
||||
}
|
||||
|
||||
static struct ioat_ring_ent **ioat2_alloc_ring(struct dma_chan *c, int order, gfp_t flags)
|
||||
{
|
||||
struct ioat_ring_ent **ring;
|
||||
int descs = 1 << order;
|
||||
int i;
|
||||
|
||||
if (order > ioat_get_max_alloc_order())
|
||||
return NULL;
|
||||
|
||||
/* allocate the array to hold the software ring */
|
||||
ring = kcalloc(descs, sizeof(*ring), flags);
|
||||
if (!ring)
|
||||
return NULL;
|
||||
for (i = 0; i < descs; i++) {
|
||||
ring[i] = ioat2_alloc_ring_ent(c, flags);
|
||||
if (!ring[i]) {
|
||||
while (i--)
|
||||
ioat2_free_ring_ent(ring[i], c);
|
||||
kfree(ring);
|
||||
return NULL;
|
||||
}
|
||||
set_desc_id(ring[i], i);
|
||||
}
|
||||
|
||||
/* link descs */
|
||||
for (i = 0; i < descs-1; i++) {
|
||||
struct ioat_ring_ent *next = ring[i+1];
|
||||
struct ioat_dma_descriptor *hw = ring[i]->hw;
|
||||
|
||||
hw->next = next->txd.phys;
|
||||
}
|
||||
ring[i]->hw->next = ring[0]->txd.phys;
|
||||
|
||||
return ring;
|
||||
}
|
||||
|
||||
void ioat2_free_chan_resources(struct dma_chan *c);
|
||||
|
||||
/* ioat2_alloc_chan_resources - allocate/initialize ioat2 descriptor ring
|
||||
* @chan: channel to be initialized
|
||||
*/
|
||||
int ioat2_alloc_chan_resources(struct dma_chan *c)
|
||||
{
|
||||
struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
|
||||
struct ioat_chan_common *chan = &ioat->base;
|
||||
struct ioat_ring_ent **ring;
|
||||
u64 status;
|
||||
int order;
|
||||
int i = 0;
|
||||
|
||||
/* have we already been set up? */
|
||||
if (ioat->ring)
|
||||
return 1 << ioat->alloc_order;
|
||||
|
||||
/* Setup register to interrupt and write completion status on error */
|
||||
writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
|
||||
|
||||
/* allocate a completion writeback area */
|
||||
/* doing 2 32bit writes to mmio since 1 64b write doesn't work */
|
||||
chan->completion = pci_pool_alloc(chan->device->completion_pool,
|
||||
GFP_KERNEL, &chan->completion_dma);
|
||||
if (!chan->completion)
|
||||
return -ENOMEM;
|
||||
|
||||
memset(chan->completion, 0, sizeof(*chan->completion));
|
||||
writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
|
||||
chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
|
||||
writel(((u64) chan->completion_dma) >> 32,
|
||||
chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
|
||||
|
||||
order = ioat_get_alloc_order();
|
||||
ring = ioat2_alloc_ring(c, order, GFP_KERNEL);
|
||||
if (!ring)
|
||||
return -ENOMEM;
|
||||
|
||||
spin_lock_bh(&chan->cleanup_lock);
|
||||
spin_lock_bh(&ioat->prep_lock);
|
||||
ioat->ring = ring;
|
||||
ioat->head = 0;
|
||||
ioat->issued = 0;
|
||||
ioat->tail = 0;
|
||||
ioat->alloc_order = order;
|
||||
set_bit(IOAT_RUN, &chan->state);
|
||||
spin_unlock_bh(&ioat->prep_lock);
|
||||
spin_unlock_bh(&chan->cleanup_lock);
|
||||
|
||||
ioat2_start_null_desc(ioat);
|
||||
|
||||
/* check that we got off the ground */
|
||||
do {
|
||||
udelay(1);
|
||||
status = ioat_chansts(chan);
|
||||
} while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status));
|
||||
|
||||
if (is_ioat_active(status) || is_ioat_idle(status)) {
|
||||
return 1 << ioat->alloc_order;
|
||||
} else {
|
||||
u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
|
||||
|
||||
dev_WARN(to_dev(chan),
|
||||
"failed to start channel chanerr: %#x\n", chanerr);
|
||||
ioat2_free_chan_resources(c);
|
||||
return -EFAULT;
|
||||
}
|
||||
}
|
||||
|
||||
bool reshape_ring(struct ioat2_dma_chan *ioat, int order)
|
||||
{
|
||||
/* reshape differs from normal ring allocation in that we want
|
||||
* to allocate a new software ring while only
|
||||
* extending/truncating the hardware ring
|
||||
*/
|
||||
struct ioat_chan_common *chan = &ioat->base;
|
||||
struct dma_chan *c = &chan->common;
|
||||
const u32 curr_size = ioat2_ring_size(ioat);
|
||||
const u16 active = ioat2_ring_active(ioat);
|
||||
const u32 new_size = 1 << order;
|
||||
struct ioat_ring_ent **ring;
|
||||
u16 i;
|
||||
|
||||
if (order > ioat_get_max_alloc_order())
|
||||
return false;
|
||||
|
||||
/* double check that we have at least 1 free descriptor */
|
||||
if (active == curr_size)
|
||||
return false;
|
||||
|
||||
/* when shrinking, verify that we can hold the current active
|
||||
* set in the new ring
|
||||
*/
|
||||
if (active >= new_size)
|
||||
return false;
|
||||
|
||||
/* allocate the array to hold the software ring */
|
||||
ring = kcalloc(new_size, sizeof(*ring), GFP_NOWAIT);
|
||||
if (!ring)
|
||||
return false;
|
||||
|
||||
/* allocate/trim descriptors as needed */
|
||||
if (new_size > curr_size) {
|
||||
/* copy current descriptors to the new ring */
|
||||
for (i = 0; i < curr_size; i++) {
|
||||
u16 curr_idx = (ioat->tail+i) & (curr_size-1);
|
||||
u16 new_idx = (ioat->tail+i) & (new_size-1);
|
||||
|
||||
ring[new_idx] = ioat->ring[curr_idx];
|
||||
set_desc_id(ring[new_idx], new_idx);
|
||||
}
|
||||
|
||||
/* add new descriptors to the ring */
|
||||
for (i = curr_size; i < new_size; i++) {
|
||||
u16 new_idx = (ioat->tail+i) & (new_size-1);
|
||||
|
||||
ring[new_idx] = ioat2_alloc_ring_ent(c, GFP_NOWAIT);
|
||||
if (!ring[new_idx]) {
|
||||
while (i--) {
|
||||
u16 new_idx = (ioat->tail+i) & (new_size-1);
|
||||
|
||||
ioat2_free_ring_ent(ring[new_idx], c);
|
||||
}
|
||||
kfree(ring);
|
||||
return false;
|
||||
}
|
||||
set_desc_id(ring[new_idx], new_idx);
|
||||
}
|
||||
|
||||
/* hw link new descriptors */
|
||||
for (i = curr_size-1; i < new_size; i++) {
|
||||
u16 new_idx = (ioat->tail+i) & (new_size-1);
|
||||
struct ioat_ring_ent *next = ring[(new_idx+1) & (new_size-1)];
|
||||
struct ioat_dma_descriptor *hw = ring[new_idx]->hw;
|
||||
|
||||
hw->next = next->txd.phys;
|
||||
}
|
||||
} else {
|
||||
struct ioat_dma_descriptor *hw;
|
||||
struct ioat_ring_ent *next;
|
||||
|
||||
/* copy current descriptors to the new ring, dropping the
|
||||
* removed descriptors
|
||||
*/
|
||||
for (i = 0; i < new_size; i++) {
|
||||
u16 curr_idx = (ioat->tail+i) & (curr_size-1);
|
||||
u16 new_idx = (ioat->tail+i) & (new_size-1);
|
||||
|
||||
ring[new_idx] = ioat->ring[curr_idx];
|
||||
set_desc_id(ring[new_idx], new_idx);
|
||||
}
|
||||
|
||||
/* free deleted descriptors */
|
||||
for (i = new_size; i < curr_size; i++) {
|
||||
struct ioat_ring_ent *ent;
|
||||
|
||||
ent = ioat2_get_ring_ent(ioat, ioat->tail+i);
|
||||
ioat2_free_ring_ent(ent, c);
|
||||
}
|
||||
|
||||
/* fix up hardware ring */
|
||||
hw = ring[(ioat->tail+new_size-1) & (new_size-1)]->hw;
|
||||
next = ring[(ioat->tail+new_size) & (new_size-1)];
|
||||
hw->next = next->txd.phys;
|
||||
}
|
||||
|
||||
dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
|
||||
__func__, new_size);
|
||||
|
||||
kfree(ioat->ring);
|
||||
ioat->ring = ring;
|
||||
ioat->alloc_order = order;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* ioat2_check_space_lock - verify space and grab ring producer lock
|
||||
* @ioat: ioat2,3 channel (ring) to operate on
|
||||
* @num_descs: allocation length
|
||||
*/
|
||||
int ioat2_check_space_lock(struct ioat2_dma_chan *ioat, int num_descs)
|
||||
{
|
||||
struct ioat_chan_common *chan = &ioat->base;
|
||||
bool retry;
|
||||
|
||||
retry:
|
||||
spin_lock_bh(&ioat->prep_lock);
|
||||
/* never allow the last descriptor to be consumed, we need at
|
||||
* least one free at all times to allow for on-the-fly ring
|
||||
* resizing.
|
||||
*/
|
||||
if (likely(ioat2_ring_space(ioat) > num_descs)) {
|
||||
dev_dbg(to_dev(chan), "%s: num_descs: %d (%x:%x:%x)\n",
|
||||
__func__, num_descs, ioat->head, ioat->tail, ioat->issued);
|
||||
ioat->produce = num_descs;
|
||||
return 0; /* with ioat->prep_lock held */
|
||||
}
|
||||
retry = test_and_set_bit(IOAT_RESHAPE_PENDING, &chan->state);
|
||||
spin_unlock_bh(&ioat->prep_lock);
|
||||
|
||||
/* is another cpu already trying to expand the ring? */
|
||||
if (retry)
|
||||
goto retry;
|
||||
|
||||
spin_lock_bh(&chan->cleanup_lock);
|
||||
spin_lock_bh(&ioat->prep_lock);
|
||||
retry = reshape_ring(ioat, ioat->alloc_order + 1);
|
||||
clear_bit(IOAT_RESHAPE_PENDING, &chan->state);
|
||||
spin_unlock_bh(&ioat->prep_lock);
|
||||
spin_unlock_bh(&chan->cleanup_lock);
|
||||
|
||||
/* if we were able to expand the ring retry the allocation */
|
||||
if (retry)
|
||||
goto retry;
|
||||
|
||||
if (printk_ratelimit())
|
||||
dev_dbg(to_dev(chan), "%s: ring full! num_descs: %d (%x:%x:%x)\n",
|
||||
__func__, num_descs, ioat->head, ioat->tail, ioat->issued);
|
||||
|
||||
/* progress reclaim in the allocation failure case we may be
|
||||
* called under bh_disabled so we need to trigger the timer
|
||||
* event directly
|
||||
*/
|
||||
if (time_is_before_jiffies(chan->timer.expires)
|
||||
&& timer_pending(&chan->timer)) {
|
||||
struct ioatdma_device *device = chan->device;
|
||||
|
||||
mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
|
||||
device->timer_fn((unsigned long) &chan->common);
|
||||
}
|
||||
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
struct dma_async_tx_descriptor *
|
||||
ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
|
||||
dma_addr_t dma_src, size_t len, unsigned long flags)
|
||||
{
|
||||
struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
|
||||
struct ioat_dma_descriptor *hw;
|
||||
struct ioat_ring_ent *desc;
|
||||
dma_addr_t dst = dma_dest;
|
||||
dma_addr_t src = dma_src;
|
||||
size_t total_len = len;
|
||||
int num_descs, idx, i;
|
||||
|
||||
num_descs = ioat2_xferlen_to_descs(ioat, len);
|
||||
if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs) == 0)
|
||||
idx = ioat->head;
|
||||
else
|
||||
return NULL;
|
||||
i = 0;
|
||||
do {
|
||||
size_t copy = min_t(size_t, len, 1 << ioat->xfercap_log);
|
||||
|
||||
desc = ioat2_get_ring_ent(ioat, idx + i);
|
||||
hw = desc->hw;
|
||||
|
||||
hw->size = copy;
|
||||
hw->ctl = 0;
|
||||
hw->src_addr = src;
|
||||
hw->dst_addr = dst;
|
||||
|
||||
len -= copy;
|
||||
dst += copy;
|
||||
src += copy;
|
||||
dump_desc_dbg(ioat, desc);
|
||||
} while (++i < num_descs);
|
||||
|
||||
desc->txd.flags = flags;
|
||||
desc->len = total_len;
|
||||
hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
|
||||
hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
|
||||
hw->ctl_f.compl_write = 1;
|
||||
dump_desc_dbg(ioat, desc);
|
||||
/* we leave the channel locked to ensure in order submission */
|
||||
|
||||
return &desc->txd;
|
||||
}
|
||||
|
||||
/**
|
||||
* ioat2_free_chan_resources - release all the descriptors
|
||||
* @chan: the channel to be cleaned
|
||||
*/
|
||||
void ioat2_free_chan_resources(struct dma_chan *c)
|
||||
{
|
||||
struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
|
||||
struct ioat_chan_common *chan = &ioat->base;
|
||||
struct ioatdma_device *device = chan->device;
|
||||
struct ioat_ring_ent *desc;
|
||||
const u16 total_descs = 1 << ioat->alloc_order;
|
||||
int descs;
|
||||
int i;
|
||||
|
||||
/* Before freeing channel resources first check
|
||||
* if they have been previously allocated for this channel.
|
||||
*/
|
||||
if (!ioat->ring)
|
||||
return;
|
||||
|
||||
ioat_stop(chan);
|
||||
device->reset_hw(chan);
|
||||
|
||||
spin_lock_bh(&chan->cleanup_lock);
|
||||
spin_lock_bh(&ioat->prep_lock);
|
||||
descs = ioat2_ring_space(ioat);
|
||||
dev_dbg(to_dev(chan), "freeing %d idle descriptors\n", descs);
|
||||
for (i = 0; i < descs; i++) {
|
||||
desc = ioat2_get_ring_ent(ioat, ioat->head + i);
|
||||
ioat2_free_ring_ent(desc, c);
|
||||
}
|
||||
|
||||
if (descs < total_descs)
|
||||
dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
|
||||
total_descs - descs);
|
||||
|
||||
for (i = 0; i < total_descs - descs; i++) {
|
||||
desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
|
||||
dump_desc_dbg(ioat, desc);
|
||||
ioat2_free_ring_ent(desc, c);
|
||||
}
|
||||
|
||||
kfree(ioat->ring);
|
||||
ioat->ring = NULL;
|
||||
ioat->alloc_order = 0;
|
||||
pci_pool_free(device->completion_pool, chan->completion,
|
||||
chan->completion_dma);
|
||||
spin_unlock_bh(&ioat->prep_lock);
|
||||
spin_unlock_bh(&chan->cleanup_lock);
|
||||
|
||||
chan->last_completion = 0;
|
||||
chan->completion_dma = 0;
|
||||
ioat->dmacount = 0;
|
||||
}
|
||||
|
||||
static ssize_t ring_size_show(struct dma_chan *c, char *page)
|
||||
{
|
||||
struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
|
||||
|
||||
return sprintf(page, "%d\n", (1 << ioat->alloc_order) & ~1);
|
||||
}
|
||||
static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size);
|
||||
|
||||
static ssize_t ring_active_show(struct dma_chan *c, char *page)
|
||||
{
|
||||
struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
|
||||
|
||||
/* ...taken outside the lock, no need to be precise */
|
||||
return sprintf(page, "%d\n", ioat2_ring_active(ioat));
|
||||
}
|
||||
static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active);
|
||||
|
||||
static struct attribute *ioat2_attrs[] = {
|
||||
&ring_size_attr.attr,
|
||||
&ring_active_attr.attr,
|
||||
&ioat_cap_attr.attr,
|
||||
&ioat_version_attr.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
struct kobj_type ioat2_ktype = {
|
||||
.sysfs_ops = &ioat_sysfs_ops,
|
||||
.default_attrs = ioat2_attrs,
|
||||
};
|
||||
|
||||
int ioat2_dma_probe(struct ioatdma_device *device, int dca)
|
||||
{
|
||||
struct pci_dev *pdev = device->pdev;
|
||||
struct dma_device *dma;
|
||||
struct dma_chan *c;
|
||||
struct ioat_chan_common *chan;
|
||||
int err;
|
||||
|
||||
device->enumerate_channels = ioat2_enumerate_channels;
|
||||
device->reset_hw = ioat2_reset_hw;
|
||||
device->cleanup_fn = ioat2_cleanup_event;
|
||||
device->timer_fn = ioat2_timer_event;
|
||||
device->self_test = ioat_dma_self_test;
|
||||
dma = &device->common;
|
||||
dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
|
||||
dma->device_issue_pending = ioat2_issue_pending;
|
||||
dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
|
||||
dma->device_free_chan_resources = ioat2_free_chan_resources;
|
||||
dma->device_tx_status = ioat_dma_tx_status;
|
||||
|
||||
err = ioat_probe(device);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
list_for_each_entry(c, &dma->channels, device_node) {
|
||||
chan = to_chan_common(c);
|
||||
writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | IOAT_DMA_DCA_ANY_CPU,
|
||||
chan->reg_base + IOAT_DCACTRL_OFFSET);
|
||||
}
|
||||
|
||||
err = ioat_register(device);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
ioat_kobject_add(device, &ioat2_ktype);
|
||||
|
||||
if (dca)
|
||||
device->dca = ioat2_dca_init(pdev, device->reg_base);
|
||||
|
||||
return err;
|
||||
}
|
||||
179
drivers/dma/ioat/dma_v2.h
Normal file
179
drivers/dma/ioat/dma_v2.h
Normal file
|
|
@ -0,0 +1,179 @@
|
|||
/*
|
||||
* Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called COPYING.
|
||||
*/
|
||||
#ifndef IOATDMA_V2_H
|
||||
#define IOATDMA_V2_H
|
||||
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/circ_buf.h>
|
||||
#include "dma.h"
|
||||
#include "hw.h"
|
||||
|
||||
|
||||
extern int ioat_pending_level;
|
||||
extern int ioat_ring_alloc_order;
|
||||
|
||||
/*
|
||||
* workaround for IOAT ver.3.0 null descriptor issue
|
||||
* (channel returns error when size is 0)
|
||||
*/
|
||||
#define NULL_DESC_BUFFER_SIZE 1
|
||||
|
||||
#define IOAT_MAX_ORDER 16
|
||||
#define ioat_get_alloc_order() \
|
||||
(min(ioat_ring_alloc_order, IOAT_MAX_ORDER))
|
||||
#define ioat_get_max_alloc_order() \
|
||||
(min(ioat_ring_max_alloc_order, IOAT_MAX_ORDER))
|
||||
|
||||
/* struct ioat2_dma_chan - ioat v2 / v3 channel attributes
|
||||
* @base: common ioat channel parameters
|
||||
* @xfercap_log; log2 of channel max transfer length (for fast division)
|
||||
* @head: allocated index
|
||||
* @issued: hardware notification point
|
||||
* @tail: cleanup index
|
||||
* @dmacount: identical to 'head' except for occasionally resetting to zero
|
||||
* @alloc_order: log2 of the number of allocated descriptors
|
||||
* @produce: number of descriptors to produce at submit time
|
||||
* @ring: software ring buffer implementation of hardware ring
|
||||
* @prep_lock: serializes descriptor preparation (producers)
|
||||
*/
|
||||
struct ioat2_dma_chan {
|
||||
struct ioat_chan_common base;
|
||||
size_t xfercap_log;
|
||||
u16 head;
|
||||
u16 issued;
|
||||
u16 tail;
|
||||
u16 dmacount;
|
||||
u16 alloc_order;
|
||||
u16 produce;
|
||||
struct ioat_ring_ent **ring;
|
||||
spinlock_t prep_lock;
|
||||
};
|
||||
|
||||
static inline struct ioat2_dma_chan *to_ioat2_chan(struct dma_chan *c)
|
||||
{
|
||||
struct ioat_chan_common *chan = to_chan_common(c);
|
||||
|
||||
return container_of(chan, struct ioat2_dma_chan, base);
|
||||
}
|
||||
|
||||
static inline u32 ioat2_ring_size(struct ioat2_dma_chan *ioat)
|
||||
{
|
||||
return 1 << ioat->alloc_order;
|
||||
}
|
||||
|
||||
/* count of descriptors in flight with the engine */
|
||||
static inline u16 ioat2_ring_active(struct ioat2_dma_chan *ioat)
|
||||
{
|
||||
return CIRC_CNT(ioat->head, ioat->tail, ioat2_ring_size(ioat));
|
||||
}
|
||||
|
||||
/* count of descriptors pending submission to hardware */
|
||||
static inline u16 ioat2_ring_pending(struct ioat2_dma_chan *ioat)
|
||||
{
|
||||
return CIRC_CNT(ioat->head, ioat->issued, ioat2_ring_size(ioat));
|
||||
}
|
||||
|
||||
static inline u32 ioat2_ring_space(struct ioat2_dma_chan *ioat)
|
||||
{
|
||||
return ioat2_ring_size(ioat) - ioat2_ring_active(ioat);
|
||||
}
|
||||
|
||||
static inline u16 ioat2_xferlen_to_descs(struct ioat2_dma_chan *ioat, size_t len)
|
||||
{
|
||||
u16 num_descs = len >> ioat->xfercap_log;
|
||||
|
||||
num_descs += !!(len & ((1 << ioat->xfercap_log) - 1));
|
||||
return num_descs;
|
||||
}
|
||||
|
||||
/**
|
||||
* struct ioat_ring_ent - wrapper around hardware descriptor
|
||||
* @hw: hardware DMA descriptor (for memcpy)
|
||||
* @fill: hardware fill descriptor
|
||||
* @xor: hardware xor descriptor
|
||||
* @xor_ex: hardware xor extension descriptor
|
||||
* @pq: hardware pq descriptor
|
||||
* @pq_ex: hardware pq extension descriptor
|
||||
* @pqu: hardware pq update descriptor
|
||||
* @raw: hardware raw (un-typed) descriptor
|
||||
* @txd: the generic software descriptor for all engines
|
||||
* @len: total transaction length for unmap
|
||||
* @result: asynchronous result of validate operations
|
||||
* @id: identifier for debug
|
||||
*/
|
||||
|
||||
struct ioat_ring_ent {
|
||||
union {
|
||||
struct ioat_dma_descriptor *hw;
|
||||
struct ioat_xor_descriptor *xor;
|
||||
struct ioat_xor_ext_descriptor *xor_ex;
|
||||
struct ioat_pq_descriptor *pq;
|
||||
struct ioat_pq_ext_descriptor *pq_ex;
|
||||
struct ioat_pq_update_descriptor *pqu;
|
||||
struct ioat_raw_descriptor *raw;
|
||||
};
|
||||
size_t len;
|
||||
struct dma_async_tx_descriptor txd;
|
||||
enum sum_check_flags *result;
|
||||
#ifdef DEBUG
|
||||
int id;
|
||||
#endif
|
||||
struct ioat_sed_ent *sed;
|
||||
};
|
||||
|
||||
static inline struct ioat_ring_ent *
|
||||
ioat2_get_ring_ent(struct ioat2_dma_chan *ioat, u16 idx)
|
||||
{
|
||||
return ioat->ring[idx & (ioat2_ring_size(ioat) - 1)];
|
||||
}
|
||||
|
||||
static inline void ioat2_set_chainaddr(struct ioat2_dma_chan *ioat, u64 addr)
|
||||
{
|
||||
struct ioat_chan_common *chan = &ioat->base;
|
||||
|
||||
writel(addr & 0x00000000FFFFFFFF,
|
||||
chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
|
||||
writel(addr >> 32,
|
||||
chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
|
||||
}
|
||||
|
||||
int ioat2_dma_probe(struct ioatdma_device *dev, int dca);
|
||||
int ioat3_dma_probe(struct ioatdma_device *dev, int dca);
|
||||
struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase);
|
||||
struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase);
|
||||
int ioat2_check_space_lock(struct ioat2_dma_chan *ioat, int num_descs);
|
||||
int ioat2_enumerate_channels(struct ioatdma_device *device);
|
||||
struct dma_async_tx_descriptor *
|
||||
ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
|
||||
dma_addr_t dma_src, size_t len, unsigned long flags);
|
||||
void ioat2_issue_pending(struct dma_chan *chan);
|
||||
int ioat2_alloc_chan_resources(struct dma_chan *c);
|
||||
void ioat2_free_chan_resources(struct dma_chan *c);
|
||||
void __ioat2_restart_chan(struct ioat2_dma_chan *ioat);
|
||||
bool reshape_ring(struct ioat2_dma_chan *ioat, int order);
|
||||
void __ioat2_issue_pending(struct ioat2_dma_chan *ioat);
|
||||
void ioat2_cleanup_event(unsigned long data);
|
||||
void ioat2_timer_event(unsigned long data);
|
||||
int ioat2_quiesce(struct ioat_chan_common *chan, unsigned long tmo);
|
||||
int ioat2_reset_sync(struct ioat_chan_common *chan, unsigned long tmo);
|
||||
extern struct kobj_type ioat2_ktype;
|
||||
extern struct kmem_cache *ioat2_cache;
|
||||
#endif /* IOATDMA_V2_H */
|
||||
1675
drivers/dma/ioat/dma_v3.c
Normal file
1675
drivers/dma/ioat/dma_v3.c
Normal file
File diff suppressed because it is too large
Load diff
269
drivers/dma/ioat/hw.h
Normal file
269
drivers/dma/ioat/hw.h
Normal file
|
|
@ -0,0 +1,269 @@
|
|||
/*
|
||||
* Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called COPYING.
|
||||
*/
|
||||
#ifndef _IOAT_HW_H_
|
||||
#define _IOAT_HW_H_
|
||||
|
||||
/* PCI Configuration Space Values */
|
||||
#define IOAT_MMIO_BAR 0
|
||||
|
||||
/* CB device ID's */
|
||||
#define IOAT_PCI_DID_5000 0x1A38
|
||||
#define IOAT_PCI_DID_CNB 0x360B
|
||||
#define IOAT_PCI_DID_SCNB 0x65FF
|
||||
#define IOAT_PCI_DID_SNB 0x402F
|
||||
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_IVB0 0x0e20
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_IVB1 0x0e21
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_IVB2 0x0e22
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_IVB3 0x0e23
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_IVB4 0x0e24
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_IVB5 0x0e25
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_IVB6 0x0e26
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_IVB7 0x0e27
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_IVB8 0x0e2e
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_IVB9 0x0e2f
|
||||
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_HSW0 0x2f20
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_HSW1 0x2f21
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_HSW2 0x2f22
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_HSW3 0x2f23
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_HSW4 0x2f24
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_HSW5 0x2f25
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_HSW6 0x2f26
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_HSW7 0x2f27
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_HSW8 0x2f2e
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_HSW9 0x2f2f
|
||||
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_BWD0 0x0C50
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_BWD1 0x0C51
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_BWD2 0x0C52
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_BWD3 0x0C53
|
||||
|
||||
#define IOAT_VER_1_2 0x12 /* Version 1.2 */
|
||||
#define IOAT_VER_2_0 0x20 /* Version 2.0 */
|
||||
#define IOAT_VER_3_0 0x30 /* Version 3.0 */
|
||||
#define IOAT_VER_3_2 0x32 /* Version 3.2 */
|
||||
#define IOAT_VER_3_3 0x33 /* Version 3.3 */
|
||||
|
||||
|
||||
int system_has_dca_enabled(struct pci_dev *pdev);
|
||||
|
||||
struct ioat_dma_descriptor {
|
||||
uint32_t size;
|
||||
union {
|
||||
uint32_t ctl;
|
||||
struct {
|
||||
unsigned int int_en:1;
|
||||
unsigned int src_snoop_dis:1;
|
||||
unsigned int dest_snoop_dis:1;
|
||||
unsigned int compl_write:1;
|
||||
unsigned int fence:1;
|
||||
unsigned int null:1;
|
||||
unsigned int src_brk:1;
|
||||
unsigned int dest_brk:1;
|
||||
unsigned int bundle:1;
|
||||
unsigned int dest_dca:1;
|
||||
unsigned int hint:1;
|
||||
unsigned int rsvd2:13;
|
||||
#define IOAT_OP_COPY 0x00
|
||||
unsigned int op:8;
|
||||
} ctl_f;
|
||||
};
|
||||
uint64_t src_addr;
|
||||
uint64_t dst_addr;
|
||||
uint64_t next;
|
||||
uint64_t rsv1;
|
||||
uint64_t rsv2;
|
||||
/* store some driver data in an unused portion of the descriptor */
|
||||
union {
|
||||
uint64_t user1;
|
||||
uint64_t tx_cnt;
|
||||
};
|
||||
uint64_t user2;
|
||||
};
|
||||
|
||||
struct ioat_xor_descriptor {
|
||||
uint32_t size;
|
||||
union {
|
||||
uint32_t ctl;
|
||||
struct {
|
||||
unsigned int int_en:1;
|
||||
unsigned int src_snoop_dis:1;
|
||||
unsigned int dest_snoop_dis:1;
|
||||
unsigned int compl_write:1;
|
||||
unsigned int fence:1;
|
||||
unsigned int src_cnt:3;
|
||||
unsigned int bundle:1;
|
||||
unsigned int dest_dca:1;
|
||||
unsigned int hint:1;
|
||||
unsigned int rsvd:13;
|
||||
#define IOAT_OP_XOR 0x87
|
||||
#define IOAT_OP_XOR_VAL 0x88
|
||||
unsigned int op:8;
|
||||
} ctl_f;
|
||||
};
|
||||
uint64_t src_addr;
|
||||
uint64_t dst_addr;
|
||||
uint64_t next;
|
||||
uint64_t src_addr2;
|
||||
uint64_t src_addr3;
|
||||
uint64_t src_addr4;
|
||||
uint64_t src_addr5;
|
||||
};
|
||||
|
||||
struct ioat_xor_ext_descriptor {
|
||||
uint64_t src_addr6;
|
||||
uint64_t src_addr7;
|
||||
uint64_t src_addr8;
|
||||
uint64_t next;
|
||||
uint64_t rsvd[4];
|
||||
};
|
||||
|
||||
struct ioat_pq_descriptor {
|
||||
union {
|
||||
uint32_t size;
|
||||
uint32_t dwbes;
|
||||
struct {
|
||||
unsigned int rsvd:25;
|
||||
unsigned int p_val_err:1;
|
||||
unsigned int q_val_err:1;
|
||||
unsigned int rsvd1:4;
|
||||
unsigned int wbes:1;
|
||||
} dwbes_f;
|
||||
};
|
||||
union {
|
||||
uint32_t ctl;
|
||||
struct {
|
||||
unsigned int int_en:1;
|
||||
unsigned int src_snoop_dis:1;
|
||||
unsigned int dest_snoop_dis:1;
|
||||
unsigned int compl_write:1;
|
||||
unsigned int fence:1;
|
||||
unsigned int src_cnt:3;
|
||||
unsigned int bundle:1;
|
||||
unsigned int dest_dca:1;
|
||||
unsigned int hint:1;
|
||||
unsigned int p_disable:1;
|
||||
unsigned int q_disable:1;
|
||||
unsigned int rsvd2:2;
|
||||
unsigned int wb_en:1;
|
||||
unsigned int prl_en:1;
|
||||
unsigned int rsvd3:7;
|
||||
#define IOAT_OP_PQ 0x89
|
||||
#define IOAT_OP_PQ_VAL 0x8a
|
||||
#define IOAT_OP_PQ_16S 0xa0
|
||||
#define IOAT_OP_PQ_VAL_16S 0xa1
|
||||
unsigned int op:8;
|
||||
} ctl_f;
|
||||
};
|
||||
uint64_t src_addr;
|
||||
uint64_t p_addr;
|
||||
uint64_t next;
|
||||
uint64_t src_addr2;
|
||||
union {
|
||||
uint64_t src_addr3;
|
||||
uint64_t sed_addr;
|
||||
};
|
||||
uint8_t coef[8];
|
||||
uint64_t q_addr;
|
||||
};
|
||||
|
||||
struct ioat_pq_ext_descriptor {
|
||||
uint64_t src_addr4;
|
||||
uint64_t src_addr5;
|
||||
uint64_t src_addr6;
|
||||
uint64_t next;
|
||||
uint64_t src_addr7;
|
||||
uint64_t src_addr8;
|
||||
uint64_t rsvd[2];
|
||||
};
|
||||
|
||||
struct ioat_pq_update_descriptor {
|
||||
uint32_t size;
|
||||
union {
|
||||
uint32_t ctl;
|
||||
struct {
|
||||
unsigned int int_en:1;
|
||||
unsigned int src_snoop_dis:1;
|
||||
unsigned int dest_snoop_dis:1;
|
||||
unsigned int compl_write:1;
|
||||
unsigned int fence:1;
|
||||
unsigned int src_cnt:3;
|
||||
unsigned int bundle:1;
|
||||
unsigned int dest_dca:1;
|
||||
unsigned int hint:1;
|
||||
unsigned int p_disable:1;
|
||||
unsigned int q_disable:1;
|
||||
unsigned int rsvd:3;
|
||||
unsigned int coef:8;
|
||||
#define IOAT_OP_PQ_UP 0x8b
|
||||
unsigned int op:8;
|
||||
} ctl_f;
|
||||
};
|
||||
uint64_t src_addr;
|
||||
uint64_t p_addr;
|
||||
uint64_t next;
|
||||
uint64_t src_addr2;
|
||||
uint64_t p_src;
|
||||
uint64_t q_src;
|
||||
uint64_t q_addr;
|
||||
};
|
||||
|
||||
struct ioat_raw_descriptor {
|
||||
uint64_t field[8];
|
||||
};
|
||||
|
||||
struct ioat_pq16a_descriptor {
|
||||
uint8_t coef[8];
|
||||
uint64_t src_addr3;
|
||||
uint64_t src_addr4;
|
||||
uint64_t src_addr5;
|
||||
uint64_t src_addr6;
|
||||
uint64_t src_addr7;
|
||||
uint64_t src_addr8;
|
||||
uint64_t src_addr9;
|
||||
};
|
||||
|
||||
struct ioat_pq16b_descriptor {
|
||||
uint64_t src_addr10;
|
||||
uint64_t src_addr11;
|
||||
uint64_t src_addr12;
|
||||
uint64_t src_addr13;
|
||||
uint64_t src_addr14;
|
||||
uint64_t src_addr15;
|
||||
uint64_t src_addr16;
|
||||
uint64_t rsvd;
|
||||
};
|
||||
|
||||
union ioat_sed_pq_descriptor {
|
||||
struct ioat_pq16a_descriptor a;
|
||||
struct ioat_pq16b_descriptor b;
|
||||
};
|
||||
|
||||
#define SED_SIZE 64
|
||||
|
||||
struct ioat_sed_raw_descriptor {
|
||||
uint64_t a[8];
|
||||
uint64_t b[8];
|
||||
uint64_t c[8];
|
||||
};
|
||||
|
||||
#endif
|
||||
257
drivers/dma/ioat/pci.c
Normal file
257
drivers/dma/ioat/pci.c
Normal file
|
|
@ -0,0 +1,257 @@
|
|||
/*
|
||||
* Intel I/OAT DMA Linux driver
|
||||
* Copyright(c) 2007 - 2009 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* This driver supports an Intel I/OAT DMA engine, which does asynchronous
|
||||
* copy operations.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/dca.h>
|
||||
#include <linux/slab.h>
|
||||
#include "dma.h"
|
||||
#include "dma_v2.h"
|
||||
#include "registers.h"
|
||||
#include "hw.h"
|
||||
|
||||
MODULE_VERSION(IOAT_DMA_VERSION);
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
MODULE_AUTHOR("Intel Corporation");
|
||||
|
||||
static struct pci_device_id ioat_pci_tbl[] = {
|
||||
/* I/OAT v1 platforms */
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_CNB) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SCNB) },
|
||||
{ PCI_VDEVICE(UNISYS, PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR) },
|
||||
|
||||
/* I/OAT v2 platforms */
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB) },
|
||||
|
||||
/* I/OAT v3 platforms */
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) },
|
||||
|
||||
/* I/OAT v3.2 platforms */
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) },
|
||||
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) },
|
||||
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) },
|
||||
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) },
|
||||
|
||||
/* I/OAT v3.3 platforms */
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) },
|
||||
|
||||
{ 0, }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, ioat_pci_tbl);
|
||||
|
||||
static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
|
||||
static void ioat_remove(struct pci_dev *pdev);
|
||||
|
||||
static int ioat_dca_enabled = 1;
|
||||
module_param(ioat_dca_enabled, int, 0644);
|
||||
MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)");
|
||||
|
||||
struct kmem_cache *ioat2_cache;
|
||||
struct kmem_cache *ioat3_sed_cache;
|
||||
|
||||
#define DRV_NAME "ioatdma"
|
||||
|
||||
static struct pci_driver ioat_pci_driver = {
|
||||
.name = DRV_NAME,
|
||||
.id_table = ioat_pci_tbl,
|
||||
.probe = ioat_pci_probe,
|
||||
.remove = ioat_remove,
|
||||
};
|
||||
|
||||
static struct ioatdma_device *
|
||||
alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct ioatdma_device *d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
|
||||
|
||||
if (!d)
|
||||
return NULL;
|
||||
d->pdev = pdev;
|
||||
d->reg_base = iobase;
|
||||
return d;
|
||||
}
|
||||
|
||||
static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
{
|
||||
void __iomem * const *iomap;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct ioatdma_device *device;
|
||||
int err;
|
||||
|
||||
err = pcim_enable_device(pdev);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME);
|
||||
if (err)
|
||||
return err;
|
||||
iomap = pcim_iomap_table(pdev);
|
||||
if (!iomap)
|
||||
return -ENOMEM;
|
||||
|
||||
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
|
||||
if (err)
|
||||
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
|
||||
if (err)
|
||||
err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]);
|
||||
if (!device)
|
||||
return -ENOMEM;
|
||||
pci_set_master(pdev);
|
||||
pci_set_drvdata(pdev, device);
|
||||
|
||||
device->version = readb(device->reg_base + IOAT_VER_OFFSET);
|
||||
if (device->version == IOAT_VER_1_2)
|
||||
err = ioat1_dma_probe(device, ioat_dca_enabled);
|
||||
else if (device->version == IOAT_VER_2_0)
|
||||
err = ioat2_dma_probe(device, ioat_dca_enabled);
|
||||
else if (device->version >= IOAT_VER_3_0)
|
||||
err = ioat3_dma_probe(device, ioat_dca_enabled);
|
||||
else
|
||||
return -ENODEV;
|
||||
|
||||
if (err) {
|
||||
dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ioat_remove(struct pci_dev *pdev)
|
||||
{
|
||||
struct ioatdma_device *device = pci_get_drvdata(pdev);
|
||||
|
||||
if (!device)
|
||||
return;
|
||||
|
||||
dev_err(&pdev->dev, "Removing dma and dca services\n");
|
||||
if (device->dca) {
|
||||
unregister_dca_provider(device->dca, &pdev->dev);
|
||||
free_dca_provider(device->dca);
|
||||
device->dca = NULL;
|
||||
}
|
||||
ioat_dma_remove(device);
|
||||
}
|
||||
|
||||
static int __init ioat_init_module(void)
|
||||
{
|
||||
int err = -ENOMEM;
|
||||
|
||||
pr_info("%s: Intel(R) QuickData Technology Driver %s\n",
|
||||
DRV_NAME, IOAT_DMA_VERSION);
|
||||
|
||||
ioat2_cache = kmem_cache_create("ioat2", sizeof(struct ioat_ring_ent),
|
||||
0, SLAB_HWCACHE_ALIGN, NULL);
|
||||
if (!ioat2_cache)
|
||||
return -ENOMEM;
|
||||
|
||||
ioat3_sed_cache = KMEM_CACHE(ioat_sed_ent, 0);
|
||||
if (!ioat3_sed_cache)
|
||||
goto err_ioat2_cache;
|
||||
|
||||
err = pci_register_driver(&ioat_pci_driver);
|
||||
if (err)
|
||||
goto err_ioat3_cache;
|
||||
|
||||
return 0;
|
||||
|
||||
err_ioat3_cache:
|
||||
kmem_cache_destroy(ioat3_sed_cache);
|
||||
|
||||
err_ioat2_cache:
|
||||
kmem_cache_destroy(ioat2_cache);
|
||||
|
||||
return err;
|
||||
}
|
||||
module_init(ioat_init_module);
|
||||
|
||||
static void __exit ioat_exit_module(void)
|
||||
{
|
||||
pci_unregister_driver(&ioat_pci_driver);
|
||||
kmem_cache_destroy(ioat2_cache);
|
||||
}
|
||||
module_exit(ioat_exit_module);
|
||||
253
drivers/dma/ioat/registers.h
Normal file
253
drivers/dma/ioat/registers.h
Normal file
|
|
@ -0,0 +1,253 @@
|
|||
/*
|
||||
* Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called COPYING.
|
||||
*/
|
||||
#ifndef _IOAT_REGISTERS_H_
|
||||
#define _IOAT_REGISTERS_H_
|
||||
|
||||
#define IOAT_PCI_DMACTRL_OFFSET 0x48
|
||||
#define IOAT_PCI_DMACTRL_DMA_EN 0x00000001
|
||||
#define IOAT_PCI_DMACTRL_MSI_EN 0x00000002
|
||||
|
||||
#define IOAT_PCI_DEVICE_ID_OFFSET 0x02
|
||||
#define IOAT_PCI_DMAUNCERRSTS_OFFSET 0x148
|
||||
#define IOAT_PCI_CHANERR_INT_OFFSET 0x180
|
||||
#define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184
|
||||
|
||||
/* MMIO Device Registers */
|
||||
#define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */
|
||||
|
||||
#define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */
|
||||
#define IOAT_XFERCAP_4KB 12
|
||||
#define IOAT_XFERCAP_8KB 13
|
||||
#define IOAT_XFERCAP_16KB 14
|
||||
#define IOAT_XFERCAP_32KB 15
|
||||
#define IOAT_XFERCAP_32GB 0
|
||||
|
||||
#define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */
|
||||
#define IOAT_GENCTRL_DEBUG_EN 0x01
|
||||
|
||||
#define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */
|
||||
#define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */
|
||||
#define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */
|
||||
#define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */
|
||||
#define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */
|
||||
|
||||
#define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */
|
||||
|
||||
#define IOAT_VER_OFFSET 0x08 /* 8-bit */
|
||||
#define IOAT_VER_MAJOR_MASK 0xF0
|
||||
#define IOAT_VER_MINOR_MASK 0x0F
|
||||
#define GET_IOAT_VER_MAJOR(x) (((x) & IOAT_VER_MAJOR_MASK) >> 4)
|
||||
#define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK)
|
||||
|
||||
#define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */
|
||||
|
||||
#define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */
|
||||
#define IOAT_INTRDELAY_MASK 0x3FFF /* Interrupt Delay Time */
|
||||
#define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalescing Supported */
|
||||
|
||||
#define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */
|
||||
#define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001
|
||||
#define IOAT_DEVICE_MMIO_RESTRICTED 0x0002
|
||||
#define IOAT_DEVICE_MEMORY_BYPASS 0x0004
|
||||
#define IOAT_DEVICE_ADDRESS_REMAPPING 0x0008
|
||||
|
||||
#define IOAT_DMA_CAP_OFFSET 0x10 /* 32-bit */
|
||||
#define IOAT_CAP_PAGE_BREAK 0x00000001
|
||||
#define IOAT_CAP_CRC 0x00000002
|
||||
#define IOAT_CAP_SKIP_MARKER 0x00000004
|
||||
#define IOAT_CAP_DCA 0x00000010
|
||||
#define IOAT_CAP_CRC_MOVE 0x00000020
|
||||
#define IOAT_CAP_FILL_BLOCK 0x00000040
|
||||
#define IOAT_CAP_APIC 0x00000080
|
||||
#define IOAT_CAP_XOR 0x00000100
|
||||
#define IOAT_CAP_PQ 0x00000200
|
||||
#define IOAT_CAP_DWBES 0x00002000
|
||||
#define IOAT_CAP_RAID16SS 0x00020000
|
||||
|
||||
#define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */
|
||||
|
||||
/* DMA Channel Registers */
|
||||
#define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */
|
||||
#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000
|
||||
#define IOAT3_CHANCTRL_COMPL_DCA_EN 0x0200
|
||||
#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100
|
||||
#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020
|
||||
#define IOAT_CHANCTRL_ERR_INT_EN 0x0010
|
||||
#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
|
||||
#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
|
||||
#define IOAT_CHANCTRL_INT_REARM 0x0001
|
||||
#define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\
|
||||
IOAT_CHANCTRL_ERR_INT_EN |\
|
||||
IOAT_CHANCTRL_ERR_COMPLETION_EN |\
|
||||
IOAT_CHANCTRL_ANY_ERR_ABORT_EN)
|
||||
|
||||
#define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */
|
||||
#define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */
|
||||
#define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */
|
||||
|
||||
|
||||
#define IOAT1_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */
|
||||
#define IOAT2_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */
|
||||
#define IOAT_CHANSTS_OFFSET(ver) ((ver) < IOAT_VER_2_0 \
|
||||
? IOAT1_CHANSTS_OFFSET : IOAT2_CHANSTS_OFFSET)
|
||||
#define IOAT1_CHANSTS_OFFSET_LOW 0x04
|
||||
#define IOAT2_CHANSTS_OFFSET_LOW 0x08
|
||||
#define IOAT_CHANSTS_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \
|
||||
? IOAT1_CHANSTS_OFFSET_LOW : IOAT2_CHANSTS_OFFSET_LOW)
|
||||
#define IOAT1_CHANSTS_OFFSET_HIGH 0x08
|
||||
#define IOAT2_CHANSTS_OFFSET_HIGH 0x0C
|
||||
#define IOAT_CHANSTS_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \
|
||||
? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH)
|
||||
#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL)
|
||||
#define IOAT_CHANSTS_SOFT_ERR 0x10ULL
|
||||
#define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL
|
||||
#define IOAT_CHANSTS_STATUS 0x7ULL
|
||||
#define IOAT_CHANSTS_ACTIVE 0x0
|
||||
#define IOAT_CHANSTS_DONE 0x1
|
||||
#define IOAT_CHANSTS_SUSPENDED 0x2
|
||||
#define IOAT_CHANSTS_HALTED 0x3
|
||||
|
||||
|
||||
|
||||
#define IOAT_CHAN_DMACOUNT_OFFSET 0x06 /* 16-bit DMA Count register */
|
||||
|
||||
#define IOAT_DCACTRL_OFFSET 0x30 /* 32 bit Direct Cache Access Control Register */
|
||||
#define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000
|
||||
#define IOAT_DCACTRL_TARGET_CPU_MASK 0xFFFF /* APIC ID */
|
||||
|
||||
/* CB DCA Memory Space Registers */
|
||||
#define IOAT_DCAOFFSET_OFFSET 0x14
|
||||
/* CB_BAR + IOAT_DCAOFFSET value */
|
||||
#define IOAT_DCA_VER_OFFSET 0x00
|
||||
#define IOAT_DCA_VER_MAJOR_MASK 0xF0
|
||||
#define IOAT_DCA_VER_MINOR_MASK 0x0F
|
||||
|
||||
#define IOAT_DCA_COMP_OFFSET 0x02
|
||||
#define IOAT_DCA_COMP_V1 0x1
|
||||
|
||||
#define IOAT_FSB_CAPABILITY_OFFSET 0x04
|
||||
#define IOAT_FSB_CAPABILITY_PREFETCH 0x1
|
||||
|
||||
#define IOAT_PCI_CAPABILITY_OFFSET 0x06
|
||||
#define IOAT_PCI_CAPABILITY_MEMWR 0x1
|
||||
|
||||
#define IOAT_FSB_CAP_ENABLE_OFFSET 0x08
|
||||
#define IOAT_FSB_CAP_ENABLE_PREFETCH 0x1
|
||||
|
||||
#define IOAT_PCI_CAP_ENABLE_OFFSET 0x0A
|
||||
#define IOAT_PCI_CAP_ENABLE_MEMWR 0x1
|
||||
|
||||
#define IOAT_APICID_TAG_MAP_OFFSET 0x0C
|
||||
#define IOAT_APICID_TAG_MAP_TAG0 0x0000000F
|
||||
#define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0
|
||||
#define IOAT_APICID_TAG_MAP_TAG1 0x000000F0
|
||||
#define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4
|
||||
#define IOAT_APICID_TAG_MAP_TAG2 0x00000F00
|
||||
#define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8
|
||||
#define IOAT_APICID_TAG_MAP_TAG3 0x0000F000
|
||||
#define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12
|
||||
#define IOAT_APICID_TAG_MAP_TAG4 0x000F0000
|
||||
#define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16
|
||||
#define IOAT_APICID_TAG_CB2_VALID 0x8080808080
|
||||
|
||||
#define IOAT_DCA_GREQID_OFFSET 0x10
|
||||
#define IOAT_DCA_GREQID_SIZE 0x04
|
||||
#define IOAT_DCA_GREQID_MASK 0xFFFF
|
||||
#define IOAT_DCA_GREQID_IGNOREFUN 0x10000000
|
||||
#define IOAT_DCA_GREQID_VALID 0x20000000
|
||||
#define IOAT_DCA_GREQID_LASTID 0x80000000
|
||||
|
||||
#define IOAT3_CSI_CAPABILITY_OFFSET 0x08
|
||||
#define IOAT3_CSI_CAPABILITY_PREFETCH 0x1
|
||||
|
||||
#define IOAT3_PCI_CAPABILITY_OFFSET 0x0A
|
||||
#define IOAT3_PCI_CAPABILITY_MEMWR 0x1
|
||||
|
||||
#define IOAT3_CSI_CONTROL_OFFSET 0x0C
|
||||
#define IOAT3_CSI_CONTROL_PREFETCH 0x1
|
||||
|
||||
#define IOAT3_PCI_CONTROL_OFFSET 0x0E
|
||||
#define IOAT3_PCI_CONTROL_MEMWR 0x1
|
||||
|
||||
#define IOAT3_APICID_TAG_MAP_OFFSET 0x10
|
||||
#define IOAT3_APICID_TAG_MAP_OFFSET_LOW 0x10
|
||||
#define IOAT3_APICID_TAG_MAP_OFFSET_HIGH 0x14
|
||||
|
||||
#define IOAT3_DCA_GREQID_OFFSET 0x02
|
||||
|
||||
#define IOAT1_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */
|
||||
#define IOAT2_CHAINADDR_OFFSET 0x10 /* 64-bit Descriptor Chain Address Register */
|
||||
#define IOAT_CHAINADDR_OFFSET(ver) ((ver) < IOAT_VER_2_0 \
|
||||
? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET)
|
||||
#define IOAT1_CHAINADDR_OFFSET_LOW 0x0C
|
||||
#define IOAT2_CHAINADDR_OFFSET_LOW 0x10
|
||||
#define IOAT_CHAINADDR_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \
|
||||
? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW)
|
||||
#define IOAT1_CHAINADDR_OFFSET_HIGH 0x10
|
||||
#define IOAT2_CHAINADDR_OFFSET_HIGH 0x14
|
||||
#define IOAT_CHAINADDR_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \
|
||||
? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH)
|
||||
|
||||
#define IOAT1_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */
|
||||
#define IOAT2_CHANCMD_OFFSET 0x04 /* 8-bit DMA Channel Command Register */
|
||||
#define IOAT_CHANCMD_OFFSET(ver) ((ver) < IOAT_VER_2_0 \
|
||||
? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET)
|
||||
#define IOAT_CHANCMD_RESET 0x20
|
||||
#define IOAT_CHANCMD_RESUME 0x10
|
||||
#define IOAT_CHANCMD_ABORT 0x08
|
||||
#define IOAT_CHANCMD_SUSPEND 0x04
|
||||
#define IOAT_CHANCMD_APPEND 0x02
|
||||
#define IOAT_CHANCMD_START 0x01
|
||||
|
||||
#define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */
|
||||
#define IOAT_CHANCMP_OFFSET_LOW 0x18
|
||||
#define IOAT_CHANCMP_OFFSET_HIGH 0x1C
|
||||
|
||||
#define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */
|
||||
#define IOAT_CDAR_OFFSET_LOW 0x20
|
||||
#define IOAT_CDAR_OFFSET_HIGH 0x24
|
||||
|
||||
#define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */
|
||||
#define IOAT_CHANERR_SRC_ADDR_ERR 0x0001
|
||||
#define IOAT_CHANERR_DEST_ADDR_ERR 0x0002
|
||||
#define IOAT_CHANERR_NEXT_ADDR_ERR 0x0004
|
||||
#define IOAT_CHANERR_NEXT_DESC_ALIGN_ERR 0x0008
|
||||
#define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010
|
||||
#define IOAT_CHANERR_CHANCMD_ERR 0x0020
|
||||
#define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040
|
||||
#define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080
|
||||
#define IOAT_CHANERR_READ_DATA_ERR 0x0100
|
||||
#define IOAT_CHANERR_WRITE_DATA_ERR 0x0200
|
||||
#define IOAT_CHANERR_CONTROL_ERR 0x0400
|
||||
#define IOAT_CHANERR_LENGTH_ERR 0x0800
|
||||
#define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000
|
||||
#define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000
|
||||
#define IOAT_CHANERR_SOFT_ERR 0x4000
|
||||
#define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000
|
||||
#define IOAT_CHANERR_XOR_P_OR_CRC_ERR 0x10000
|
||||
#define IOAT_CHANERR_XOR_Q_ERR 0x20000
|
||||
#define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR 0x40000
|
||||
|
||||
#define IOAT_CHANERR_HANDLE_MASK (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR)
|
||||
|
||||
#define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */
|
||||
|
||||
#endif /* _IOAT_REGISTERS_H_ */
|
||||
1570
drivers/dma/iop-adma.c
Normal file
1570
drivers/dma/iop-adma.c
Normal file
File diff suppressed because it is too large
Load diff
1
drivers/dma/ipu/Makefile
Normal file
1
drivers/dma/ipu/Makefile
Normal file
|
|
@ -0,0 +1 @@
|
|||
obj-y += ipu_irq.o ipu_idmac.o
|
||||
1800
drivers/dma/ipu/ipu_idmac.c
Normal file
1800
drivers/dma/ipu/ipu_idmac.c
Normal file
File diff suppressed because it is too large
Load diff
176
drivers/dma/ipu/ipu_intern.h
Normal file
176
drivers/dma/ipu/ipu_intern.h
Normal file
|
|
@ -0,0 +1,176 @@
|
|||
/*
|
||||
* Copyright (C) 2008
|
||||
* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
|
||||
*
|
||||
* Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _IPU_INTERN_H_
|
||||
#define _IPU_INTERN_H_
|
||||
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
/* IPU Common registers */
|
||||
#define IPU_CONF 0x00
|
||||
#define IPU_CHA_BUF0_RDY 0x04
|
||||
#define IPU_CHA_BUF1_RDY 0x08
|
||||
#define IPU_CHA_DB_MODE_SEL 0x0C
|
||||
#define IPU_CHA_CUR_BUF 0x10
|
||||
#define IPU_FS_PROC_FLOW 0x14
|
||||
#define IPU_FS_DISP_FLOW 0x18
|
||||
#define IPU_TASKS_STAT 0x1C
|
||||
#define IPU_IMA_ADDR 0x20
|
||||
#define IPU_IMA_DATA 0x24
|
||||
#define IPU_INT_CTRL_1 0x28
|
||||
#define IPU_INT_CTRL_2 0x2C
|
||||
#define IPU_INT_CTRL_3 0x30
|
||||
#define IPU_INT_CTRL_4 0x34
|
||||
#define IPU_INT_CTRL_5 0x38
|
||||
#define IPU_INT_STAT_1 0x3C
|
||||
#define IPU_INT_STAT_2 0x40
|
||||
#define IPU_INT_STAT_3 0x44
|
||||
#define IPU_INT_STAT_4 0x48
|
||||
#define IPU_INT_STAT_5 0x4C
|
||||
#define IPU_BRK_CTRL_1 0x50
|
||||
#define IPU_BRK_CTRL_2 0x54
|
||||
#define IPU_BRK_STAT 0x58
|
||||
#define IPU_DIAGB_CTRL 0x5C
|
||||
|
||||
/* IPU_CONF Register bits */
|
||||
#define IPU_CONF_CSI_EN 0x00000001
|
||||
#define IPU_CONF_IC_EN 0x00000002
|
||||
#define IPU_CONF_ROT_EN 0x00000004
|
||||
#define IPU_CONF_PF_EN 0x00000008
|
||||
#define IPU_CONF_SDC_EN 0x00000010
|
||||
#define IPU_CONF_ADC_EN 0x00000020
|
||||
#define IPU_CONF_DI_EN 0x00000040
|
||||
#define IPU_CONF_DU_EN 0x00000080
|
||||
#define IPU_CONF_PXL_ENDIAN 0x00000100
|
||||
|
||||
/* Image Converter Registers */
|
||||
#define IC_CONF 0x88
|
||||
#define IC_PRP_ENC_RSC 0x8C
|
||||
#define IC_PRP_VF_RSC 0x90
|
||||
#define IC_PP_RSC 0x94
|
||||
#define IC_CMBP_1 0x98
|
||||
#define IC_CMBP_2 0x9C
|
||||
#define PF_CONF 0xA0
|
||||
#define IDMAC_CONF 0xA4
|
||||
#define IDMAC_CHA_EN 0xA8
|
||||
#define IDMAC_CHA_PRI 0xAC
|
||||
#define IDMAC_CHA_BUSY 0xB0
|
||||
|
||||
/* Image Converter Register bits */
|
||||
#define IC_CONF_PRPENC_EN 0x00000001
|
||||
#define IC_CONF_PRPENC_CSC1 0x00000002
|
||||
#define IC_CONF_PRPENC_ROT_EN 0x00000004
|
||||
#define IC_CONF_PRPVF_EN 0x00000100
|
||||
#define IC_CONF_PRPVF_CSC1 0x00000200
|
||||
#define IC_CONF_PRPVF_CSC2 0x00000400
|
||||
#define IC_CONF_PRPVF_CMB 0x00000800
|
||||
#define IC_CONF_PRPVF_ROT_EN 0x00001000
|
||||
#define IC_CONF_PP_EN 0x00010000
|
||||
#define IC_CONF_PP_CSC1 0x00020000
|
||||
#define IC_CONF_PP_CSC2 0x00040000
|
||||
#define IC_CONF_PP_CMB 0x00080000
|
||||
#define IC_CONF_PP_ROT_EN 0x00100000
|
||||
#define IC_CONF_IC_GLB_LOC_A 0x10000000
|
||||
#define IC_CONF_KEY_COLOR_EN 0x20000000
|
||||
#define IC_CONF_RWS_EN 0x40000000
|
||||
#define IC_CONF_CSI_MEM_WR_EN 0x80000000
|
||||
|
||||
#define IDMA_CHAN_INVALID 0x000000FF
|
||||
#define IDMA_IC_0 0x00000001
|
||||
#define IDMA_IC_1 0x00000002
|
||||
#define IDMA_IC_2 0x00000004
|
||||
#define IDMA_IC_3 0x00000008
|
||||
#define IDMA_IC_4 0x00000010
|
||||
#define IDMA_IC_5 0x00000020
|
||||
#define IDMA_IC_6 0x00000040
|
||||
#define IDMA_IC_7 0x00000080
|
||||
#define IDMA_IC_8 0x00000100
|
||||
#define IDMA_IC_9 0x00000200
|
||||
#define IDMA_IC_10 0x00000400
|
||||
#define IDMA_IC_11 0x00000800
|
||||
#define IDMA_IC_12 0x00001000
|
||||
#define IDMA_IC_13 0x00002000
|
||||
#define IDMA_SDC_BG 0x00004000
|
||||
#define IDMA_SDC_FG 0x00008000
|
||||
#define IDMA_SDC_MASK 0x00010000
|
||||
#define IDMA_SDC_PARTIAL 0x00020000
|
||||
#define IDMA_ADC_SYS1_WR 0x00040000
|
||||
#define IDMA_ADC_SYS2_WR 0x00080000
|
||||
#define IDMA_ADC_SYS1_CMD 0x00100000
|
||||
#define IDMA_ADC_SYS2_CMD 0x00200000
|
||||
#define IDMA_ADC_SYS1_RD 0x00400000
|
||||
#define IDMA_ADC_SYS2_RD 0x00800000
|
||||
#define IDMA_PF_QP 0x01000000
|
||||
#define IDMA_PF_BSP 0x02000000
|
||||
#define IDMA_PF_Y_IN 0x04000000
|
||||
#define IDMA_PF_U_IN 0x08000000
|
||||
#define IDMA_PF_V_IN 0x10000000
|
||||
#define IDMA_PF_Y_OUT 0x20000000
|
||||
#define IDMA_PF_U_OUT 0x40000000
|
||||
#define IDMA_PF_V_OUT 0x80000000
|
||||
|
||||
#define TSTAT_PF_H264_PAUSE 0x00000001
|
||||
#define TSTAT_CSI2MEM_MASK 0x0000000C
|
||||
#define TSTAT_CSI2MEM_OFFSET 2
|
||||
#define TSTAT_VF_MASK 0x00000600
|
||||
#define TSTAT_VF_OFFSET 9
|
||||
#define TSTAT_VF_ROT_MASK 0x000C0000
|
||||
#define TSTAT_VF_ROT_OFFSET 18
|
||||
#define TSTAT_ENC_MASK 0x00000180
|
||||
#define TSTAT_ENC_OFFSET 7
|
||||
#define TSTAT_ENC_ROT_MASK 0x00030000
|
||||
#define TSTAT_ENC_ROT_OFFSET 16
|
||||
#define TSTAT_PP_MASK 0x00001800
|
||||
#define TSTAT_PP_OFFSET 11
|
||||
#define TSTAT_PP_ROT_MASK 0x00300000
|
||||
#define TSTAT_PP_ROT_OFFSET 20
|
||||
#define TSTAT_PF_MASK 0x00C00000
|
||||
#define TSTAT_PF_OFFSET 22
|
||||
#define TSTAT_ADCSYS1_MASK 0x03000000
|
||||
#define TSTAT_ADCSYS1_OFFSET 24
|
||||
#define TSTAT_ADCSYS2_MASK 0x0C000000
|
||||
#define TSTAT_ADCSYS2_OFFSET 26
|
||||
|
||||
#define TASK_STAT_IDLE 0
|
||||
#define TASK_STAT_ACTIVE 1
|
||||
#define TASK_STAT_WAIT4READY 2
|
||||
|
||||
struct idmac {
|
||||
struct dma_device dma;
|
||||
};
|
||||
|
||||
struct ipu {
|
||||
void __iomem *reg_ipu;
|
||||
void __iomem *reg_ic;
|
||||
unsigned int irq_fn; /* IPU Function IRQ to the CPU */
|
||||
unsigned int irq_err; /* IPU Error IRQ to the CPU */
|
||||
unsigned int irq_base; /* Beginning of the IPU IRQ range */
|
||||
unsigned long channel_init_mask;
|
||||
spinlock_t lock;
|
||||
struct clk *ipu_clk;
|
||||
struct device *dev;
|
||||
struct idmac idmac;
|
||||
struct idmac_channel channel[IPU_CHANNELS_NUM];
|
||||
struct tasklet_struct tasklet;
|
||||
};
|
||||
|
||||
#define to_idmac(d) container_of(d, struct idmac, dma)
|
||||
|
||||
extern int ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev);
|
||||
extern void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev);
|
||||
|
||||
extern bool ipu_irq_status(uint32_t irq);
|
||||
extern int ipu_irq_map(unsigned int source);
|
||||
extern int ipu_irq_unmap(unsigned int source);
|
||||
|
||||
#endif
|
||||
415
drivers/dma/ipu/ipu_irq.c
Normal file
415
drivers/dma/ipu/ipu_irq.c
Normal file
|
|
@ -0,0 +1,415 @@
|
|||
/*
|
||||
* Copyright (C) 2008
|
||||
* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/dma/ipu-dma.h>
|
||||
|
||||
#include "ipu_intern.h"
|
||||
|
||||
/*
|
||||
* Register read / write - shall be inlined by the compiler
|
||||
*/
|
||||
static u32 ipu_read_reg(struct ipu *ipu, unsigned long reg)
|
||||
{
|
||||
return __raw_readl(ipu->reg_ipu + reg);
|
||||
}
|
||||
|
||||
static void ipu_write_reg(struct ipu *ipu, u32 value, unsigned long reg)
|
||||
{
|
||||
__raw_writel(value, ipu->reg_ipu + reg);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* IPU IRQ chip driver
|
||||
*/
|
||||
|
||||
#define IPU_IRQ_NR_FN_BANKS 3
|
||||
#define IPU_IRQ_NR_ERR_BANKS 2
|
||||
#define IPU_IRQ_NR_BANKS (IPU_IRQ_NR_FN_BANKS + IPU_IRQ_NR_ERR_BANKS)
|
||||
|
||||
struct ipu_irq_bank {
|
||||
unsigned int control;
|
||||
unsigned int status;
|
||||
struct ipu *ipu;
|
||||
};
|
||||
|
||||
static struct ipu_irq_bank irq_bank[IPU_IRQ_NR_BANKS] = {
|
||||
/* 3 groups of functional interrupts */
|
||||
{
|
||||
.control = IPU_INT_CTRL_1,
|
||||
.status = IPU_INT_STAT_1,
|
||||
}, {
|
||||
.control = IPU_INT_CTRL_2,
|
||||
.status = IPU_INT_STAT_2,
|
||||
}, {
|
||||
.control = IPU_INT_CTRL_3,
|
||||
.status = IPU_INT_STAT_3,
|
||||
},
|
||||
/* 2 groups of error interrupts */
|
||||
{
|
||||
.control = IPU_INT_CTRL_4,
|
||||
.status = IPU_INT_STAT_4,
|
||||
}, {
|
||||
.control = IPU_INT_CTRL_5,
|
||||
.status = IPU_INT_STAT_5,
|
||||
},
|
||||
};
|
||||
|
||||
struct ipu_irq_map {
|
||||
unsigned int irq;
|
||||
int source;
|
||||
struct ipu_irq_bank *bank;
|
||||
struct ipu *ipu;
|
||||
};
|
||||
|
||||
static struct ipu_irq_map irq_map[CONFIG_MX3_IPU_IRQS];
|
||||
/* Protects allocations from the above array of maps */
|
||||
static DEFINE_MUTEX(map_lock);
|
||||
/* Protects register accesses and individual mappings */
|
||||
static DEFINE_RAW_SPINLOCK(bank_lock);
|
||||
|
||||
static struct ipu_irq_map *src2map(unsigned int src)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++)
|
||||
if (irq_map[i].source == src)
|
||||
return irq_map + i;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void ipu_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
|
||||
struct ipu_irq_bank *bank;
|
||||
uint32_t reg;
|
||||
unsigned long lock_flags;
|
||||
|
||||
raw_spin_lock_irqsave(&bank_lock, lock_flags);
|
||||
|
||||
bank = map->bank;
|
||||
if (!bank) {
|
||||
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
|
||||
return;
|
||||
}
|
||||
|
||||
reg = ipu_read_reg(bank->ipu, bank->control);
|
||||
reg |= (1UL << (map->source & 31));
|
||||
ipu_write_reg(bank->ipu, reg, bank->control);
|
||||
|
||||
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
}
|
||||
|
||||
static void ipu_irq_mask(struct irq_data *d)
|
||||
{
|
||||
struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
|
||||
struct ipu_irq_bank *bank;
|
||||
uint32_t reg;
|
||||
unsigned long lock_flags;
|
||||
|
||||
raw_spin_lock_irqsave(&bank_lock, lock_flags);
|
||||
|
||||
bank = map->bank;
|
||||
if (!bank) {
|
||||
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
|
||||
return;
|
||||
}
|
||||
|
||||
reg = ipu_read_reg(bank->ipu, bank->control);
|
||||
reg &= ~(1UL << (map->source & 31));
|
||||
ipu_write_reg(bank->ipu, reg, bank->control);
|
||||
|
||||
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
}
|
||||
|
||||
static void ipu_irq_ack(struct irq_data *d)
|
||||
{
|
||||
struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
|
||||
struct ipu_irq_bank *bank;
|
||||
unsigned long lock_flags;
|
||||
|
||||
raw_spin_lock_irqsave(&bank_lock, lock_flags);
|
||||
|
||||
bank = map->bank;
|
||||
if (!bank) {
|
||||
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
|
||||
return;
|
||||
}
|
||||
|
||||
ipu_write_reg(bank->ipu, 1UL << (map->source & 31), bank->status);
|
||||
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
}
|
||||
|
||||
/**
|
||||
* ipu_irq_status() - returns the current interrupt status of the specified IRQ.
|
||||
* @irq: interrupt line to get status for.
|
||||
* @return: true if the interrupt is pending/asserted or false if the
|
||||
* interrupt is not pending.
|
||||
*/
|
||||
bool ipu_irq_status(unsigned int irq)
|
||||
{
|
||||
struct ipu_irq_map *map = irq_get_chip_data(irq);
|
||||
struct ipu_irq_bank *bank;
|
||||
unsigned long lock_flags;
|
||||
bool ret;
|
||||
|
||||
raw_spin_lock_irqsave(&bank_lock, lock_flags);
|
||||
bank = map->bank;
|
||||
ret = bank && ipu_read_reg(bank->ipu, bank->status) &
|
||||
(1UL << (map->source & 31));
|
||||
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* ipu_irq_map() - map an IPU interrupt source to an IRQ number
|
||||
* @source: interrupt source bit position (see below)
|
||||
* @return: mapped IRQ number or negative error code
|
||||
*
|
||||
* The source parameter has to be explained further. On i.MX31 IPU has 137 IRQ
|
||||
* sources, they are broken down in 5 32-bit registers, like 32, 32, 24, 32, 17.
|
||||
* However, the source argument of this function is not the sequence number of
|
||||
* the possible IRQ, but rather its bit position. So, first interrupt in fourth
|
||||
* register has source number 96, and not 88. This makes calculations easier,
|
||||
* and also provides forward compatibility with any future IPU implementations
|
||||
* with any interrupt bit assignments.
|
||||
*/
|
||||
int ipu_irq_map(unsigned int source)
|
||||
{
|
||||
int i, ret = -ENOMEM;
|
||||
struct ipu_irq_map *map;
|
||||
|
||||
might_sleep();
|
||||
|
||||
mutex_lock(&map_lock);
|
||||
map = src2map(source);
|
||||
if (map) {
|
||||
pr_err("IPU: Source %u already mapped to IRQ %u\n", source, map->irq);
|
||||
ret = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
|
||||
for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
|
||||
if (irq_map[i].source < 0) {
|
||||
unsigned long lock_flags;
|
||||
|
||||
raw_spin_lock_irqsave(&bank_lock, lock_flags);
|
||||
irq_map[i].source = source;
|
||||
irq_map[i].bank = irq_bank + source / 32;
|
||||
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
|
||||
ret = irq_map[i].irq;
|
||||
pr_debug("IPU: mapped source %u to IRQ %u\n",
|
||||
source, ret);
|
||||
break;
|
||||
}
|
||||
}
|
||||
out:
|
||||
mutex_unlock(&map_lock);
|
||||
|
||||
if (ret < 0)
|
||||
pr_err("IPU: couldn't map source %u: %d\n", source, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* ipu_irq_map() - map an IPU interrupt source to an IRQ number
|
||||
* @source: interrupt source bit position (see ipu_irq_map())
|
||||
* @return: 0 or negative error code
|
||||
*/
|
||||
int ipu_irq_unmap(unsigned int source)
|
||||
{
|
||||
int i, ret = -EINVAL;
|
||||
|
||||
might_sleep();
|
||||
|
||||
mutex_lock(&map_lock);
|
||||
for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
|
||||
if (irq_map[i].source == source) {
|
||||
unsigned long lock_flags;
|
||||
|
||||
pr_debug("IPU: unmapped source %u from IRQ %u\n",
|
||||
source, irq_map[i].irq);
|
||||
|
||||
raw_spin_lock_irqsave(&bank_lock, lock_flags);
|
||||
irq_map[i].source = -EINVAL;
|
||||
irq_map[i].bank = NULL;
|
||||
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
mutex_unlock(&map_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Chained IRQ handler for IPU error interrupt */
|
||||
static void ipu_irq_err(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
struct ipu *ipu = irq_get_handler_data(irq);
|
||||
u32 status;
|
||||
int i, line;
|
||||
|
||||
for (i = IPU_IRQ_NR_FN_BANKS; i < IPU_IRQ_NR_BANKS; i++) {
|
||||
struct ipu_irq_bank *bank = irq_bank + i;
|
||||
|
||||
raw_spin_lock(&bank_lock);
|
||||
status = ipu_read_reg(ipu, bank->status);
|
||||
/*
|
||||
* Don't think we have to clear all interrupts here, they will
|
||||
* be acked by ->handle_irq() (handle_level_irq). However, we
|
||||
* might want to clear unhandled interrupts after the loop...
|
||||
*/
|
||||
status &= ipu_read_reg(ipu, bank->control);
|
||||
raw_spin_unlock(&bank_lock);
|
||||
while ((line = ffs(status))) {
|
||||
struct ipu_irq_map *map;
|
||||
|
||||
line--;
|
||||
status &= ~(1UL << line);
|
||||
|
||||
raw_spin_lock(&bank_lock);
|
||||
map = src2map(32 * i + line);
|
||||
if (map)
|
||||
irq = map->irq;
|
||||
raw_spin_unlock(&bank_lock);
|
||||
|
||||
if (!map) {
|
||||
pr_err("IPU: Interrupt on unmapped source %u bank %d\n",
|
||||
line, i);
|
||||
continue;
|
||||
}
|
||||
generic_handle_irq(irq);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Chained IRQ handler for IPU function interrupt */
|
||||
static void ipu_irq_fn(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
struct ipu *ipu = irq_desc_get_handler_data(desc);
|
||||
u32 status;
|
||||
int i, line;
|
||||
|
||||
for (i = 0; i < IPU_IRQ_NR_FN_BANKS; i++) {
|
||||
struct ipu_irq_bank *bank = irq_bank + i;
|
||||
|
||||
raw_spin_lock(&bank_lock);
|
||||
status = ipu_read_reg(ipu, bank->status);
|
||||
/* Not clearing all interrupts, see above */
|
||||
status &= ipu_read_reg(ipu, bank->control);
|
||||
raw_spin_unlock(&bank_lock);
|
||||
while ((line = ffs(status))) {
|
||||
struct ipu_irq_map *map;
|
||||
|
||||
line--;
|
||||
status &= ~(1UL << line);
|
||||
|
||||
raw_spin_lock(&bank_lock);
|
||||
map = src2map(32 * i + line);
|
||||
if (map)
|
||||
irq = map->irq;
|
||||
raw_spin_unlock(&bank_lock);
|
||||
|
||||
if (!map) {
|
||||
pr_err("IPU: Interrupt on unmapped source %u bank %d\n",
|
||||
line, i);
|
||||
continue;
|
||||
}
|
||||
generic_handle_irq(irq);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static struct irq_chip ipu_irq_chip = {
|
||||
.name = "ipu_irq",
|
||||
.irq_ack = ipu_irq_ack,
|
||||
.irq_mask = ipu_irq_mask,
|
||||
.irq_unmask = ipu_irq_unmask,
|
||||
};
|
||||
|
||||
/* Install the IRQ handler */
|
||||
int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
|
||||
{
|
||||
unsigned int irq, i;
|
||||
int irq_base = irq_alloc_descs(-1, 0, CONFIG_MX3_IPU_IRQS,
|
||||
numa_node_id());
|
||||
|
||||
if (irq_base < 0)
|
||||
return irq_base;
|
||||
|
||||
for (i = 0; i < IPU_IRQ_NR_BANKS; i++)
|
||||
irq_bank[i].ipu = ipu;
|
||||
|
||||
for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
|
||||
int ret;
|
||||
|
||||
irq = irq_base + i;
|
||||
ret = irq_set_chip(irq, &ipu_irq_chip);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
ret = irq_set_chip_data(irq, irq_map + i);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
irq_map[i].ipu = ipu;
|
||||
irq_map[i].irq = irq;
|
||||
irq_map[i].source = -EINVAL;
|
||||
irq_set_handler(irq, handle_level_irq);
|
||||
#ifdef CONFIG_ARM
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
#endif
|
||||
}
|
||||
|
||||
irq_set_handler_data(ipu->irq_fn, ipu);
|
||||
irq_set_chained_handler(ipu->irq_fn, ipu_irq_fn);
|
||||
|
||||
irq_set_handler_data(ipu->irq_err, ipu);
|
||||
irq_set_chained_handler(ipu->irq_err, ipu_irq_err);
|
||||
|
||||
ipu->irq_base = irq_base;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev)
|
||||
{
|
||||
unsigned int irq, irq_base;
|
||||
|
||||
irq_base = ipu->irq_base;
|
||||
|
||||
irq_set_chained_handler(ipu->irq_fn, NULL);
|
||||
irq_set_handler_data(ipu->irq_fn, NULL);
|
||||
|
||||
irq_set_chained_handler(ipu->irq_err, NULL);
|
||||
irq_set_handler_data(ipu->irq_err, NULL);
|
||||
|
||||
for (irq = irq_base; irq < irq_base + CONFIG_MX3_IPU_IRQS; irq++) {
|
||||
#ifdef CONFIG_ARM
|
||||
set_irq_flags(irq, 0);
|
||||
#endif
|
||||
irq_set_chip(irq, NULL);
|
||||
irq_set_chip_data(irq, NULL);
|
||||
}
|
||||
}
|
||||
837
drivers/dma/k3dma.c
Normal file
837
drivers/dma/k3dma.c
Normal file
|
|
@ -0,0 +1,837 @@
|
|||
/*
|
||||
* Copyright (c) 2013 Linaro Ltd.
|
||||
* Copyright (c) 2013 Hisilicon Limited.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/sched.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/of_dma.h>
|
||||
|
||||
#include "virt-dma.h"
|
||||
|
||||
#define DRIVER_NAME "k3-dma"
|
||||
#define DMA_ALIGN 3
|
||||
#define DMA_MAX_SIZE 0x1ffc
|
||||
|
||||
#define INT_STAT 0x00
|
||||
#define INT_TC1 0x04
|
||||
#define INT_ERR1 0x0c
|
||||
#define INT_ERR2 0x10
|
||||
#define INT_TC1_MASK 0x18
|
||||
#define INT_ERR1_MASK 0x20
|
||||
#define INT_ERR2_MASK 0x24
|
||||
#define INT_TC1_RAW 0x600
|
||||
#define INT_ERR1_RAW 0x608
|
||||
#define INT_ERR2_RAW 0x610
|
||||
#define CH_PRI 0x688
|
||||
#define CH_STAT 0x690
|
||||
#define CX_CUR_CNT 0x704
|
||||
#define CX_LLI 0x800
|
||||
#define CX_CNT 0x810
|
||||
#define CX_SRC 0x814
|
||||
#define CX_DST 0x818
|
||||
#define CX_CFG 0x81c
|
||||
#define AXI_CFG 0x820
|
||||
#define AXI_CFG_DEFAULT 0x201201
|
||||
|
||||
#define CX_LLI_CHAIN_EN 0x2
|
||||
#define CX_CFG_EN 0x1
|
||||
#define CX_CFG_MEM2PER (0x1 << 2)
|
||||
#define CX_CFG_PER2MEM (0x2 << 2)
|
||||
#define CX_CFG_SRCINCR (0x1 << 31)
|
||||
#define CX_CFG_DSTINCR (0x1 << 30)
|
||||
|
||||
struct k3_desc_hw {
|
||||
u32 lli;
|
||||
u32 reserved[3];
|
||||
u32 count;
|
||||
u32 saddr;
|
||||
u32 daddr;
|
||||
u32 config;
|
||||
} __aligned(32);
|
||||
|
||||
struct k3_dma_desc_sw {
|
||||
struct virt_dma_desc vd;
|
||||
dma_addr_t desc_hw_lli;
|
||||
size_t desc_num;
|
||||
size_t size;
|
||||
struct k3_desc_hw desc_hw[0];
|
||||
};
|
||||
|
||||
struct k3_dma_phy;
|
||||
|
||||
struct k3_dma_chan {
|
||||
u32 ccfg;
|
||||
struct virt_dma_chan vc;
|
||||
struct k3_dma_phy *phy;
|
||||
struct list_head node;
|
||||
enum dma_transfer_direction dir;
|
||||
dma_addr_t dev_addr;
|
||||
enum dma_status status;
|
||||
};
|
||||
|
||||
struct k3_dma_phy {
|
||||
u32 idx;
|
||||
void __iomem *base;
|
||||
struct k3_dma_chan *vchan;
|
||||
struct k3_dma_desc_sw *ds_run;
|
||||
struct k3_dma_desc_sw *ds_done;
|
||||
};
|
||||
|
||||
struct k3_dma_dev {
|
||||
struct dma_device slave;
|
||||
void __iomem *base;
|
||||
struct tasklet_struct task;
|
||||
spinlock_t lock;
|
||||
struct list_head chan_pending;
|
||||
struct k3_dma_phy *phy;
|
||||
struct k3_dma_chan *chans;
|
||||
struct clk *clk;
|
||||
u32 dma_channels;
|
||||
u32 dma_requests;
|
||||
};
|
||||
|
||||
#define to_k3_dma(dmadev) container_of(dmadev, struct k3_dma_dev, slave)
|
||||
|
||||
static struct k3_dma_chan *to_k3_chan(struct dma_chan *chan)
|
||||
{
|
||||
return container_of(chan, struct k3_dma_chan, vc.chan);
|
||||
}
|
||||
|
||||
static void k3_dma_pause_dma(struct k3_dma_phy *phy, bool on)
|
||||
{
|
||||
u32 val = 0;
|
||||
|
||||
if (on) {
|
||||
val = readl_relaxed(phy->base + CX_CFG);
|
||||
val |= CX_CFG_EN;
|
||||
writel_relaxed(val, phy->base + CX_CFG);
|
||||
} else {
|
||||
val = readl_relaxed(phy->base + CX_CFG);
|
||||
val &= ~CX_CFG_EN;
|
||||
writel_relaxed(val, phy->base + CX_CFG);
|
||||
}
|
||||
}
|
||||
|
||||
static void k3_dma_terminate_chan(struct k3_dma_phy *phy, struct k3_dma_dev *d)
|
||||
{
|
||||
u32 val = 0;
|
||||
|
||||
k3_dma_pause_dma(phy, false);
|
||||
|
||||
val = 0x1 << phy->idx;
|
||||
writel_relaxed(val, d->base + INT_TC1_RAW);
|
||||
writel_relaxed(val, d->base + INT_ERR1_RAW);
|
||||
writel_relaxed(val, d->base + INT_ERR2_RAW);
|
||||
}
|
||||
|
||||
static void k3_dma_set_desc(struct k3_dma_phy *phy, struct k3_desc_hw *hw)
|
||||
{
|
||||
writel_relaxed(hw->lli, phy->base + CX_LLI);
|
||||
writel_relaxed(hw->count, phy->base + CX_CNT);
|
||||
writel_relaxed(hw->saddr, phy->base + CX_SRC);
|
||||
writel_relaxed(hw->daddr, phy->base + CX_DST);
|
||||
writel_relaxed(AXI_CFG_DEFAULT, phy->base + AXI_CFG);
|
||||
writel_relaxed(hw->config, phy->base + CX_CFG);
|
||||
}
|
||||
|
||||
static u32 k3_dma_get_curr_cnt(struct k3_dma_dev *d, struct k3_dma_phy *phy)
|
||||
{
|
||||
u32 cnt = 0;
|
||||
|
||||
cnt = readl_relaxed(d->base + CX_CUR_CNT + phy->idx * 0x10);
|
||||
cnt &= 0xffff;
|
||||
return cnt;
|
||||
}
|
||||
|
||||
static u32 k3_dma_get_curr_lli(struct k3_dma_phy *phy)
|
||||
{
|
||||
return readl_relaxed(phy->base + CX_LLI);
|
||||
}
|
||||
|
||||
static u32 k3_dma_get_chan_stat(struct k3_dma_dev *d)
|
||||
{
|
||||
return readl_relaxed(d->base + CH_STAT);
|
||||
}
|
||||
|
||||
static void k3_dma_enable_dma(struct k3_dma_dev *d, bool on)
|
||||
{
|
||||
if (on) {
|
||||
/* set same priority */
|
||||
writel_relaxed(0x0, d->base + CH_PRI);
|
||||
|
||||
/* unmask irq */
|
||||
writel_relaxed(0xffff, d->base + INT_TC1_MASK);
|
||||
writel_relaxed(0xffff, d->base + INT_ERR1_MASK);
|
||||
writel_relaxed(0xffff, d->base + INT_ERR2_MASK);
|
||||
} else {
|
||||
/* mask irq */
|
||||
writel_relaxed(0x0, d->base + INT_TC1_MASK);
|
||||
writel_relaxed(0x0, d->base + INT_ERR1_MASK);
|
||||
writel_relaxed(0x0, d->base + INT_ERR2_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t k3_dma_int_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct k3_dma_dev *d = (struct k3_dma_dev *)dev_id;
|
||||
struct k3_dma_phy *p;
|
||||
struct k3_dma_chan *c;
|
||||
u32 stat = readl_relaxed(d->base + INT_STAT);
|
||||
u32 tc1 = readl_relaxed(d->base + INT_TC1);
|
||||
u32 err1 = readl_relaxed(d->base + INT_ERR1);
|
||||
u32 err2 = readl_relaxed(d->base + INT_ERR2);
|
||||
u32 i, irq_chan = 0;
|
||||
|
||||
while (stat) {
|
||||
i = __ffs(stat);
|
||||
stat &= (stat - 1);
|
||||
if (likely(tc1 & BIT(i))) {
|
||||
p = &d->phy[i];
|
||||
c = p->vchan;
|
||||
if (c) {
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&c->vc.lock, flags);
|
||||
vchan_cookie_complete(&p->ds_run->vd);
|
||||
p->ds_done = p->ds_run;
|
||||
spin_unlock_irqrestore(&c->vc.lock, flags);
|
||||
}
|
||||
irq_chan |= BIT(i);
|
||||
}
|
||||
if (unlikely((err1 & BIT(i)) || (err2 & BIT(i))))
|
||||
dev_warn(d->slave.dev, "DMA ERR\n");
|
||||
}
|
||||
|
||||
writel_relaxed(irq_chan, d->base + INT_TC1_RAW);
|
||||
writel_relaxed(err1, d->base + INT_ERR1_RAW);
|
||||
writel_relaxed(err2, d->base + INT_ERR2_RAW);
|
||||
|
||||
if (irq_chan) {
|
||||
tasklet_schedule(&d->task);
|
||||
return IRQ_HANDLED;
|
||||
} else
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
static int k3_dma_start_txd(struct k3_dma_chan *c)
|
||||
{
|
||||
struct k3_dma_dev *d = to_k3_dma(c->vc.chan.device);
|
||||
struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
|
||||
|
||||
if (!c->phy)
|
||||
return -EAGAIN;
|
||||
|
||||
if (BIT(c->phy->idx) & k3_dma_get_chan_stat(d))
|
||||
return -EAGAIN;
|
||||
|
||||
if (vd) {
|
||||
struct k3_dma_desc_sw *ds =
|
||||
container_of(vd, struct k3_dma_desc_sw, vd);
|
||||
/*
|
||||
* fetch and remove request from vc->desc_issued
|
||||
* so vc->desc_issued only contains desc pending
|
||||
*/
|
||||
list_del(&ds->vd.node);
|
||||
c->phy->ds_run = ds;
|
||||
c->phy->ds_done = NULL;
|
||||
/* start dma */
|
||||
k3_dma_set_desc(c->phy, &ds->desc_hw[0]);
|
||||
return 0;
|
||||
}
|
||||
c->phy->ds_done = NULL;
|
||||
c->phy->ds_run = NULL;
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
static void k3_dma_tasklet(unsigned long arg)
|
||||
{
|
||||
struct k3_dma_dev *d = (struct k3_dma_dev *)arg;
|
||||
struct k3_dma_phy *p;
|
||||
struct k3_dma_chan *c, *cn;
|
||||
unsigned pch, pch_alloc = 0;
|
||||
|
||||
/* check new dma request of running channel in vc->desc_issued */
|
||||
list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
|
||||
spin_lock_irq(&c->vc.lock);
|
||||
p = c->phy;
|
||||
if (p && p->ds_done) {
|
||||
if (k3_dma_start_txd(c)) {
|
||||
/* No current txd associated with this channel */
|
||||
dev_dbg(d->slave.dev, "pchan %u: free\n", p->idx);
|
||||
/* Mark this channel free */
|
||||
c->phy = NULL;
|
||||
p->vchan = NULL;
|
||||
}
|
||||
}
|
||||
spin_unlock_irq(&c->vc.lock);
|
||||
}
|
||||
|
||||
/* check new channel request in d->chan_pending */
|
||||
spin_lock_irq(&d->lock);
|
||||
for (pch = 0; pch < d->dma_channels; pch++) {
|
||||
p = &d->phy[pch];
|
||||
|
||||
if (p->vchan == NULL && !list_empty(&d->chan_pending)) {
|
||||
c = list_first_entry(&d->chan_pending,
|
||||
struct k3_dma_chan, node);
|
||||
/* remove from d->chan_pending */
|
||||
list_del_init(&c->node);
|
||||
pch_alloc |= 1 << pch;
|
||||
/* Mark this channel allocated */
|
||||
p->vchan = c;
|
||||
c->phy = p;
|
||||
dev_dbg(d->slave.dev, "pchan %u: alloc vchan %p\n", pch, &c->vc);
|
||||
}
|
||||
}
|
||||
spin_unlock_irq(&d->lock);
|
||||
|
||||
for (pch = 0; pch < d->dma_channels; pch++) {
|
||||
if (pch_alloc & (1 << pch)) {
|
||||
p = &d->phy[pch];
|
||||
c = p->vchan;
|
||||
if (c) {
|
||||
spin_lock_irq(&c->vc.lock);
|
||||
k3_dma_start_txd(c);
|
||||
spin_unlock_irq(&c->vc.lock);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int k3_dma_alloc_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void k3_dma_free_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct k3_dma_chan *c = to_k3_chan(chan);
|
||||
struct k3_dma_dev *d = to_k3_dma(chan->device);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&d->lock, flags);
|
||||
list_del_init(&c->node);
|
||||
spin_unlock_irqrestore(&d->lock, flags);
|
||||
|
||||
vchan_free_chan_resources(&c->vc);
|
||||
c->ccfg = 0;
|
||||
}
|
||||
|
||||
static enum dma_status k3_dma_tx_status(struct dma_chan *chan,
|
||||
dma_cookie_t cookie, struct dma_tx_state *state)
|
||||
{
|
||||
struct k3_dma_chan *c = to_k3_chan(chan);
|
||||
struct k3_dma_dev *d = to_k3_dma(chan->device);
|
||||
struct k3_dma_phy *p;
|
||||
struct virt_dma_desc *vd;
|
||||
unsigned long flags;
|
||||
enum dma_status ret;
|
||||
size_t bytes = 0;
|
||||
|
||||
ret = dma_cookie_status(&c->vc.chan, cookie, state);
|
||||
if (ret == DMA_COMPLETE)
|
||||
return ret;
|
||||
|
||||
spin_lock_irqsave(&c->vc.lock, flags);
|
||||
p = c->phy;
|
||||
ret = c->status;
|
||||
|
||||
/*
|
||||
* If the cookie is on our issue queue, then the residue is
|
||||
* its total size.
|
||||
*/
|
||||
vd = vchan_find_desc(&c->vc, cookie);
|
||||
if (vd) {
|
||||
bytes = container_of(vd, struct k3_dma_desc_sw, vd)->size;
|
||||
} else if ((!p) || (!p->ds_run)) {
|
||||
bytes = 0;
|
||||
} else {
|
||||
struct k3_dma_desc_sw *ds = p->ds_run;
|
||||
u32 clli = 0, index = 0;
|
||||
|
||||
bytes = k3_dma_get_curr_cnt(d, p);
|
||||
clli = k3_dma_get_curr_lli(p);
|
||||
index = (clli - ds->desc_hw_lli) / sizeof(struct k3_desc_hw);
|
||||
for (; index < ds->desc_num; index++) {
|
||||
bytes += ds->desc_hw[index].count;
|
||||
/* end of lli */
|
||||
if (!ds->desc_hw[index].lli)
|
||||
break;
|
||||
}
|
||||
}
|
||||
spin_unlock_irqrestore(&c->vc.lock, flags);
|
||||
dma_set_residue(state, bytes);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void k3_dma_issue_pending(struct dma_chan *chan)
|
||||
{
|
||||
struct k3_dma_chan *c = to_k3_chan(chan);
|
||||
struct k3_dma_dev *d = to_k3_dma(chan->device);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&c->vc.lock, flags);
|
||||
/* add request to vc->desc_issued */
|
||||
if (vchan_issue_pending(&c->vc)) {
|
||||
spin_lock(&d->lock);
|
||||
if (!c->phy) {
|
||||
if (list_empty(&c->node)) {
|
||||
/* if new channel, add chan_pending */
|
||||
list_add_tail(&c->node, &d->chan_pending);
|
||||
/* check in tasklet */
|
||||
tasklet_schedule(&d->task);
|
||||
dev_dbg(d->slave.dev, "vchan %p: issued\n", &c->vc);
|
||||
}
|
||||
}
|
||||
spin_unlock(&d->lock);
|
||||
} else
|
||||
dev_dbg(d->slave.dev, "vchan %p: nothing to issue\n", &c->vc);
|
||||
spin_unlock_irqrestore(&c->vc.lock, flags);
|
||||
}
|
||||
|
||||
static void k3_dma_fill_desc(struct k3_dma_desc_sw *ds, dma_addr_t dst,
|
||||
dma_addr_t src, size_t len, u32 num, u32 ccfg)
|
||||
{
|
||||
if ((num + 1) < ds->desc_num)
|
||||
ds->desc_hw[num].lli = ds->desc_hw_lli + (num + 1) *
|
||||
sizeof(struct k3_desc_hw);
|
||||
ds->desc_hw[num].lli |= CX_LLI_CHAIN_EN;
|
||||
ds->desc_hw[num].count = len;
|
||||
ds->desc_hw[num].saddr = src;
|
||||
ds->desc_hw[num].daddr = dst;
|
||||
ds->desc_hw[num].config = ccfg;
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *k3_dma_prep_memcpy(
|
||||
struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
|
||||
size_t len, unsigned long flags)
|
||||
{
|
||||
struct k3_dma_chan *c = to_k3_chan(chan);
|
||||
struct k3_dma_desc_sw *ds;
|
||||
size_t copy = 0;
|
||||
int num = 0;
|
||||
|
||||
if (!len)
|
||||
return NULL;
|
||||
|
||||
num = DIV_ROUND_UP(len, DMA_MAX_SIZE);
|
||||
ds = kzalloc(sizeof(*ds) + num * sizeof(ds->desc_hw[0]), GFP_ATOMIC);
|
||||
if (!ds) {
|
||||
dev_dbg(chan->device->dev, "vchan %p: kzalloc fail\n", &c->vc);
|
||||
return NULL;
|
||||
}
|
||||
ds->desc_hw_lli = __virt_to_phys((unsigned long)&ds->desc_hw[0]);
|
||||
ds->size = len;
|
||||
ds->desc_num = num;
|
||||
num = 0;
|
||||
|
||||
if (!c->ccfg) {
|
||||
/* default is memtomem, without calling device_control */
|
||||
c->ccfg = CX_CFG_SRCINCR | CX_CFG_DSTINCR | CX_CFG_EN;
|
||||
c->ccfg |= (0xf << 20) | (0xf << 24); /* burst = 16 */
|
||||
c->ccfg |= (0x3 << 12) | (0x3 << 16); /* width = 64 bit */
|
||||
}
|
||||
|
||||
do {
|
||||
copy = min_t(size_t, len, DMA_MAX_SIZE);
|
||||
k3_dma_fill_desc(ds, dst, src, copy, num++, c->ccfg);
|
||||
|
||||
if (c->dir == DMA_MEM_TO_DEV) {
|
||||
src += copy;
|
||||
} else if (c->dir == DMA_DEV_TO_MEM) {
|
||||
dst += copy;
|
||||
} else {
|
||||
src += copy;
|
||||
dst += copy;
|
||||
}
|
||||
len -= copy;
|
||||
} while (len);
|
||||
|
||||
ds->desc_hw[num-1].lli = 0; /* end of link */
|
||||
return vchan_tx_prep(&c->vc, &ds->vd, flags);
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *k3_dma_prep_slave_sg(
|
||||
struct dma_chan *chan, struct scatterlist *sgl, unsigned int sglen,
|
||||
enum dma_transfer_direction dir, unsigned long flags, void *context)
|
||||
{
|
||||
struct k3_dma_chan *c = to_k3_chan(chan);
|
||||
struct k3_dma_desc_sw *ds;
|
||||
size_t len, avail, total = 0;
|
||||
struct scatterlist *sg;
|
||||
dma_addr_t addr, src = 0, dst = 0;
|
||||
int num = sglen, i;
|
||||
|
||||
if (sgl == NULL)
|
||||
return NULL;
|
||||
|
||||
for_each_sg(sgl, sg, sglen, i) {
|
||||
avail = sg_dma_len(sg);
|
||||
if (avail > DMA_MAX_SIZE)
|
||||
num += DIV_ROUND_UP(avail, DMA_MAX_SIZE) - 1;
|
||||
}
|
||||
|
||||
ds = kzalloc(sizeof(*ds) + num * sizeof(ds->desc_hw[0]), GFP_ATOMIC);
|
||||
if (!ds) {
|
||||
dev_dbg(chan->device->dev, "vchan %p: kzalloc fail\n", &c->vc);
|
||||
return NULL;
|
||||
}
|
||||
ds->desc_hw_lli = __virt_to_phys((unsigned long)&ds->desc_hw[0]);
|
||||
ds->desc_num = num;
|
||||
num = 0;
|
||||
|
||||
for_each_sg(sgl, sg, sglen, i) {
|
||||
addr = sg_dma_address(sg);
|
||||
avail = sg_dma_len(sg);
|
||||
total += avail;
|
||||
|
||||
do {
|
||||
len = min_t(size_t, avail, DMA_MAX_SIZE);
|
||||
|
||||
if (dir == DMA_MEM_TO_DEV) {
|
||||
src = addr;
|
||||
dst = c->dev_addr;
|
||||
} else if (dir == DMA_DEV_TO_MEM) {
|
||||
src = c->dev_addr;
|
||||
dst = addr;
|
||||
}
|
||||
|
||||
k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg);
|
||||
|
||||
addr += len;
|
||||
avail -= len;
|
||||
} while (avail);
|
||||
}
|
||||
|
||||
ds->desc_hw[num-1].lli = 0; /* end of link */
|
||||
ds->size = total;
|
||||
return vchan_tx_prep(&c->vc, &ds->vd, flags);
|
||||
}
|
||||
|
||||
static int k3_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
struct k3_dma_chan *c = to_k3_chan(chan);
|
||||
struct k3_dma_dev *d = to_k3_dma(chan->device);
|
||||
struct dma_slave_config *cfg = (void *)arg;
|
||||
struct k3_dma_phy *p = c->phy;
|
||||
unsigned long flags;
|
||||
u32 maxburst = 0, val = 0;
|
||||
enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
|
||||
LIST_HEAD(head);
|
||||
|
||||
switch (cmd) {
|
||||
case DMA_SLAVE_CONFIG:
|
||||
if (cfg == NULL)
|
||||
return -EINVAL;
|
||||
c->dir = cfg->direction;
|
||||
if (c->dir == DMA_DEV_TO_MEM) {
|
||||
c->ccfg = CX_CFG_DSTINCR;
|
||||
c->dev_addr = cfg->src_addr;
|
||||
maxburst = cfg->src_maxburst;
|
||||
width = cfg->src_addr_width;
|
||||
} else if (c->dir == DMA_MEM_TO_DEV) {
|
||||
c->ccfg = CX_CFG_SRCINCR;
|
||||
c->dev_addr = cfg->dst_addr;
|
||||
maxburst = cfg->dst_maxburst;
|
||||
width = cfg->dst_addr_width;
|
||||
}
|
||||
switch (width) {
|
||||
case DMA_SLAVE_BUSWIDTH_1_BYTE:
|
||||
case DMA_SLAVE_BUSWIDTH_2_BYTES:
|
||||
case DMA_SLAVE_BUSWIDTH_4_BYTES:
|
||||
case DMA_SLAVE_BUSWIDTH_8_BYTES:
|
||||
val = __ffs(width);
|
||||
break;
|
||||
default:
|
||||
val = 3;
|
||||
break;
|
||||
}
|
||||
c->ccfg |= (val << 12) | (val << 16);
|
||||
|
||||
if ((maxburst == 0) || (maxburst > 16))
|
||||
val = 16;
|
||||
else
|
||||
val = maxburst - 1;
|
||||
c->ccfg |= (val << 20) | (val << 24);
|
||||
c->ccfg |= CX_CFG_MEM2PER | CX_CFG_EN;
|
||||
|
||||
/* specific request line */
|
||||
c->ccfg |= c->vc.chan.chan_id << 4;
|
||||
break;
|
||||
|
||||
case DMA_TERMINATE_ALL:
|
||||
dev_dbg(d->slave.dev, "vchan %p: terminate all\n", &c->vc);
|
||||
|
||||
/* Prevent this channel being scheduled */
|
||||
spin_lock(&d->lock);
|
||||
list_del_init(&c->node);
|
||||
spin_unlock(&d->lock);
|
||||
|
||||
/* Clear the tx descriptor lists */
|
||||
spin_lock_irqsave(&c->vc.lock, flags);
|
||||
vchan_get_all_descriptors(&c->vc, &head);
|
||||
if (p) {
|
||||
/* vchan is assigned to a pchan - stop the channel */
|
||||
k3_dma_terminate_chan(p, d);
|
||||
c->phy = NULL;
|
||||
p->vchan = NULL;
|
||||
p->ds_run = p->ds_done = NULL;
|
||||
}
|
||||
spin_unlock_irqrestore(&c->vc.lock, flags);
|
||||
vchan_dma_desc_free_list(&c->vc, &head);
|
||||
break;
|
||||
|
||||
case DMA_PAUSE:
|
||||
dev_dbg(d->slave.dev, "vchan %p: pause\n", &c->vc);
|
||||
if (c->status == DMA_IN_PROGRESS) {
|
||||
c->status = DMA_PAUSED;
|
||||
if (p) {
|
||||
k3_dma_pause_dma(p, false);
|
||||
} else {
|
||||
spin_lock(&d->lock);
|
||||
list_del_init(&c->node);
|
||||
spin_unlock(&d->lock);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_RESUME:
|
||||
dev_dbg(d->slave.dev, "vchan %p: resume\n", &c->vc);
|
||||
spin_lock_irqsave(&c->vc.lock, flags);
|
||||
if (c->status == DMA_PAUSED) {
|
||||
c->status = DMA_IN_PROGRESS;
|
||||
if (p) {
|
||||
k3_dma_pause_dma(p, true);
|
||||
} else if (!list_empty(&c->vc.desc_issued)) {
|
||||
spin_lock(&d->lock);
|
||||
list_add_tail(&c->node, &d->chan_pending);
|
||||
spin_unlock(&d->lock);
|
||||
}
|
||||
}
|
||||
spin_unlock_irqrestore(&c->vc.lock, flags);
|
||||
break;
|
||||
default:
|
||||
return -ENXIO;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void k3_dma_free_desc(struct virt_dma_desc *vd)
|
||||
{
|
||||
struct k3_dma_desc_sw *ds =
|
||||
container_of(vd, struct k3_dma_desc_sw, vd);
|
||||
|
||||
kfree(ds);
|
||||
}
|
||||
|
||||
static struct of_device_id k3_pdma_dt_ids[] = {
|
||||
{ .compatible = "hisilicon,k3-dma-1.0", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, k3_pdma_dt_ids);
|
||||
|
||||
static struct dma_chan *k3_of_dma_simple_xlate(struct of_phandle_args *dma_spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
struct k3_dma_dev *d = ofdma->of_dma_data;
|
||||
unsigned int request = dma_spec->args[0];
|
||||
|
||||
if (request > d->dma_requests)
|
||||
return NULL;
|
||||
|
||||
return dma_get_slave_channel(&(d->chans[request].vc.chan));
|
||||
}
|
||||
|
||||
static int k3_dma_probe(struct platform_device *op)
|
||||
{
|
||||
struct k3_dma_dev *d;
|
||||
const struct of_device_id *of_id;
|
||||
struct resource *iores;
|
||||
int i, ret, irq = 0;
|
||||
|
||||
iores = platform_get_resource(op, IORESOURCE_MEM, 0);
|
||||
if (!iores)
|
||||
return -EINVAL;
|
||||
|
||||
d = devm_kzalloc(&op->dev, sizeof(*d), GFP_KERNEL);
|
||||
if (!d)
|
||||
return -ENOMEM;
|
||||
|
||||
d->base = devm_ioremap_resource(&op->dev, iores);
|
||||
if (IS_ERR(d->base))
|
||||
return PTR_ERR(d->base);
|
||||
|
||||
of_id = of_match_device(k3_pdma_dt_ids, &op->dev);
|
||||
if (of_id) {
|
||||
of_property_read_u32((&op->dev)->of_node,
|
||||
"dma-channels", &d->dma_channels);
|
||||
of_property_read_u32((&op->dev)->of_node,
|
||||
"dma-requests", &d->dma_requests);
|
||||
}
|
||||
|
||||
d->clk = devm_clk_get(&op->dev, NULL);
|
||||
if (IS_ERR(d->clk)) {
|
||||
dev_err(&op->dev, "no dma clk\n");
|
||||
return PTR_ERR(d->clk);
|
||||
}
|
||||
|
||||
irq = platform_get_irq(op, 0);
|
||||
ret = devm_request_irq(&op->dev, irq,
|
||||
k3_dma_int_handler, 0, DRIVER_NAME, d);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* init phy channel */
|
||||
d->phy = devm_kzalloc(&op->dev,
|
||||
d->dma_channels * sizeof(struct k3_dma_phy), GFP_KERNEL);
|
||||
if (d->phy == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < d->dma_channels; i++) {
|
||||
struct k3_dma_phy *p = &d->phy[i];
|
||||
|
||||
p->idx = i;
|
||||
p->base = d->base + i * 0x40;
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&d->slave.channels);
|
||||
dma_cap_set(DMA_SLAVE, d->slave.cap_mask);
|
||||
dma_cap_set(DMA_MEMCPY, d->slave.cap_mask);
|
||||
d->slave.dev = &op->dev;
|
||||
d->slave.device_alloc_chan_resources = k3_dma_alloc_chan_resources;
|
||||
d->slave.device_free_chan_resources = k3_dma_free_chan_resources;
|
||||
d->slave.device_tx_status = k3_dma_tx_status;
|
||||
d->slave.device_prep_dma_memcpy = k3_dma_prep_memcpy;
|
||||
d->slave.device_prep_slave_sg = k3_dma_prep_slave_sg;
|
||||
d->slave.device_issue_pending = k3_dma_issue_pending;
|
||||
d->slave.device_control = k3_dma_control;
|
||||
d->slave.copy_align = DMA_ALIGN;
|
||||
d->slave.chancnt = d->dma_requests;
|
||||
|
||||
/* init virtual channel */
|
||||
d->chans = devm_kzalloc(&op->dev,
|
||||
d->dma_requests * sizeof(struct k3_dma_chan), GFP_KERNEL);
|
||||
if (d->chans == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < d->dma_requests; i++) {
|
||||
struct k3_dma_chan *c = &d->chans[i];
|
||||
|
||||
c->status = DMA_IN_PROGRESS;
|
||||
INIT_LIST_HEAD(&c->node);
|
||||
c->vc.desc_free = k3_dma_free_desc;
|
||||
vchan_init(&c->vc, &d->slave);
|
||||
}
|
||||
|
||||
/* Enable clock before accessing registers */
|
||||
ret = clk_prepare_enable(d->clk);
|
||||
if (ret < 0) {
|
||||
dev_err(&op->dev, "clk_prepare_enable failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
k3_dma_enable_dma(d, true);
|
||||
|
||||
ret = dma_async_device_register(&d->slave);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = of_dma_controller_register((&op->dev)->of_node,
|
||||
k3_of_dma_simple_xlate, d);
|
||||
if (ret)
|
||||
goto of_dma_register_fail;
|
||||
|
||||
spin_lock_init(&d->lock);
|
||||
INIT_LIST_HEAD(&d->chan_pending);
|
||||
tasklet_init(&d->task, k3_dma_tasklet, (unsigned long)d);
|
||||
platform_set_drvdata(op, d);
|
||||
dev_info(&op->dev, "initialized\n");
|
||||
|
||||
return 0;
|
||||
|
||||
of_dma_register_fail:
|
||||
dma_async_device_unregister(&d->slave);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int k3_dma_remove(struct platform_device *op)
|
||||
{
|
||||
struct k3_dma_chan *c, *cn;
|
||||
struct k3_dma_dev *d = platform_get_drvdata(op);
|
||||
|
||||
dma_async_device_unregister(&d->slave);
|
||||
of_dma_controller_free((&op->dev)->of_node);
|
||||
|
||||
list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
|
||||
list_del(&c->vc.chan.device_node);
|
||||
tasklet_kill(&c->vc.task);
|
||||
}
|
||||
tasklet_kill(&d->task);
|
||||
clk_disable_unprepare(d->clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int k3_dma_suspend(struct device *dev)
|
||||
{
|
||||
struct k3_dma_dev *d = dev_get_drvdata(dev);
|
||||
u32 stat = 0;
|
||||
|
||||
stat = k3_dma_get_chan_stat(d);
|
||||
if (stat) {
|
||||
dev_warn(d->slave.dev,
|
||||
"chan %d is running fail to suspend\n", stat);
|
||||
return -1;
|
||||
}
|
||||
k3_dma_enable_dma(d, false);
|
||||
clk_disable_unprepare(d->clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int k3_dma_resume(struct device *dev)
|
||||
{
|
||||
struct k3_dma_dev *d = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
ret = clk_prepare_enable(d->clk);
|
||||
if (ret < 0) {
|
||||
dev_err(d->slave.dev, "clk_prepare_enable failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
k3_dma_enable_dma(d, true);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(k3_dma_pmops, k3_dma_suspend, k3_dma_resume);
|
||||
|
||||
static struct platform_driver k3_pdma_driver = {
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.pm = &k3_dma_pmops,
|
||||
.of_match_table = k3_pdma_dt_ids,
|
||||
},
|
||||
.probe = k3_dma_probe,
|
||||
.remove = k3_dma_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(k3_pdma_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Hisilicon k3 DMA Driver");
|
||||
MODULE_ALIAS("platform:k3dma");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
774
drivers/dma/mic_x100_dma.c
Normal file
774
drivers/dma/mic_x100_dma.c
Normal file
|
|
@ -0,0 +1,774 @@
|
|||
/*
|
||||
* Intel MIC Platform Software Stack (MPSS)
|
||||
*
|
||||
* Copyright(c) 2014 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
* Intel MIC X100 DMA Driver.
|
||||
*
|
||||
* Adapted from IOAT dma driver.
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/seq_file.h>
|
||||
|
||||
#include "mic_x100_dma.h"
|
||||
|
||||
#define MIC_DMA_MAX_XFER_SIZE_CARD (1 * 1024 * 1024 -\
|
||||
MIC_DMA_ALIGN_BYTES)
|
||||
#define MIC_DMA_MAX_XFER_SIZE_HOST (1 * 1024 * 1024 >> 1)
|
||||
#define MIC_DMA_DESC_TYPE_SHIFT 60
|
||||
#define MIC_DMA_MEMCPY_LEN_SHIFT 46
|
||||
#define MIC_DMA_STAT_INTR_SHIFT 59
|
||||
|
||||
/* high-water mark for pushing dma descriptors */
|
||||
static int mic_dma_pending_level = 4;
|
||||
|
||||
/* Status descriptor is used to write a 64 bit value to a memory location */
|
||||
enum mic_dma_desc_format_type {
|
||||
MIC_DMA_MEMCPY = 1,
|
||||
MIC_DMA_STATUS,
|
||||
};
|
||||
|
||||
static inline u32 mic_dma_hw_ring_inc(u32 val)
|
||||
{
|
||||
return (val + 1) % MIC_DMA_DESC_RX_SIZE;
|
||||
}
|
||||
|
||||
static inline u32 mic_dma_hw_ring_dec(u32 val)
|
||||
{
|
||||
return val ? val - 1 : MIC_DMA_DESC_RX_SIZE - 1;
|
||||
}
|
||||
|
||||
static inline void mic_dma_hw_ring_inc_head(struct mic_dma_chan *ch)
|
||||
{
|
||||
ch->head = mic_dma_hw_ring_inc(ch->head);
|
||||
}
|
||||
|
||||
/* Prepare a memcpy desc */
|
||||
static inline void mic_dma_memcpy_desc(struct mic_dma_desc *desc,
|
||||
dma_addr_t src_phys, dma_addr_t dst_phys, u64 size)
|
||||
{
|
||||
u64 qw0, qw1;
|
||||
|
||||
qw0 = src_phys;
|
||||
qw0 |= (size >> MIC_DMA_ALIGN_SHIFT) << MIC_DMA_MEMCPY_LEN_SHIFT;
|
||||
qw1 = MIC_DMA_MEMCPY;
|
||||
qw1 <<= MIC_DMA_DESC_TYPE_SHIFT;
|
||||
qw1 |= dst_phys;
|
||||
desc->qw0 = qw0;
|
||||
desc->qw1 = qw1;
|
||||
}
|
||||
|
||||
/* Prepare a status desc. with @data to be written at @dst_phys */
|
||||
static inline void mic_dma_prep_status_desc(struct mic_dma_desc *desc, u64 data,
|
||||
dma_addr_t dst_phys, bool generate_intr)
|
||||
{
|
||||
u64 qw0, qw1;
|
||||
|
||||
qw0 = data;
|
||||
qw1 = (u64) MIC_DMA_STATUS << MIC_DMA_DESC_TYPE_SHIFT | dst_phys;
|
||||
if (generate_intr)
|
||||
qw1 |= (1ULL << MIC_DMA_STAT_INTR_SHIFT);
|
||||
desc->qw0 = qw0;
|
||||
desc->qw1 = qw1;
|
||||
}
|
||||
|
||||
static void mic_dma_cleanup(struct mic_dma_chan *ch)
|
||||
{
|
||||
struct dma_async_tx_descriptor *tx;
|
||||
u32 tail;
|
||||
u32 last_tail;
|
||||
|
||||
spin_lock(&ch->cleanup_lock);
|
||||
tail = mic_dma_read_cmp_cnt(ch);
|
||||
/*
|
||||
* This is the barrier pair for smp_wmb() in fn.
|
||||
* mic_dma_tx_submit_unlock. It's required so that we read the
|
||||
* updated cookie value from tx->cookie.
|
||||
*/
|
||||
smp_rmb();
|
||||
for (last_tail = ch->last_tail; tail != last_tail;) {
|
||||
tx = &ch->tx_array[last_tail];
|
||||
if (tx->cookie) {
|
||||
dma_cookie_complete(tx);
|
||||
if (tx->callback) {
|
||||
tx->callback(tx->callback_param);
|
||||
tx->callback = NULL;
|
||||
}
|
||||
}
|
||||
last_tail = mic_dma_hw_ring_inc(last_tail);
|
||||
}
|
||||
/* finish all completion callbacks before incrementing tail */
|
||||
smp_mb();
|
||||
ch->last_tail = last_tail;
|
||||
spin_unlock(&ch->cleanup_lock);
|
||||
}
|
||||
|
||||
static u32 mic_dma_ring_count(u32 head, u32 tail)
|
||||
{
|
||||
u32 count;
|
||||
|
||||
if (head >= tail)
|
||||
count = (tail - 0) + (MIC_DMA_DESC_RX_SIZE - head);
|
||||
else
|
||||
count = tail - head;
|
||||
return count - 1;
|
||||
}
|
||||
|
||||
/* Returns the num. of free descriptors on success, -ENOMEM on failure */
|
||||
static int mic_dma_avail_desc_ring_space(struct mic_dma_chan *ch, int required)
|
||||
{
|
||||
struct device *dev = mic_dma_ch_to_device(ch);
|
||||
u32 count;
|
||||
|
||||
count = mic_dma_ring_count(ch->head, ch->last_tail);
|
||||
if (count < required) {
|
||||
mic_dma_cleanup(ch);
|
||||
count = mic_dma_ring_count(ch->head, ch->last_tail);
|
||||
}
|
||||
|
||||
if (count < required) {
|
||||
dev_dbg(dev, "Not enough desc space");
|
||||
dev_dbg(dev, "%s %d required=%u, avail=%u\n",
|
||||
__func__, __LINE__, required, count);
|
||||
return -ENOMEM;
|
||||
} else {
|
||||
return count;
|
||||
}
|
||||
}
|
||||
|
||||
/* Program memcpy descriptors into the descriptor ring and update s/w head ptr*/
|
||||
static int mic_dma_prog_memcpy_desc(struct mic_dma_chan *ch, dma_addr_t src,
|
||||
dma_addr_t dst, size_t len)
|
||||
{
|
||||
size_t current_transfer_len;
|
||||
size_t max_xfer_size = to_mic_dma_dev(ch)->max_xfer_size;
|
||||
/* 3 is added to make sure we have enough space for status desc */
|
||||
int num_desc = len / max_xfer_size + 3;
|
||||
int ret;
|
||||
|
||||
if (len % max_xfer_size)
|
||||
num_desc++;
|
||||
|
||||
ret = mic_dma_avail_desc_ring_space(ch, num_desc);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
do {
|
||||
current_transfer_len = min(len, max_xfer_size);
|
||||
mic_dma_memcpy_desc(&ch->desc_ring[ch->head],
|
||||
src, dst, current_transfer_len);
|
||||
mic_dma_hw_ring_inc_head(ch);
|
||||
len -= current_transfer_len;
|
||||
dst = dst + current_transfer_len;
|
||||
src = src + current_transfer_len;
|
||||
} while (len > 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* It's a h/w quirk and h/w needs 2 status descriptors for every status desc */
|
||||
static void mic_dma_prog_intr(struct mic_dma_chan *ch)
|
||||
{
|
||||
mic_dma_prep_status_desc(&ch->desc_ring[ch->head], 0,
|
||||
ch->status_dest_micpa, false);
|
||||
mic_dma_hw_ring_inc_head(ch);
|
||||
mic_dma_prep_status_desc(&ch->desc_ring[ch->head], 0,
|
||||
ch->status_dest_micpa, true);
|
||||
mic_dma_hw_ring_inc_head(ch);
|
||||
}
|
||||
|
||||
/* Wrapper function to program memcpy descriptors/status descriptors */
|
||||
static int mic_dma_do_dma(struct mic_dma_chan *ch, int flags, dma_addr_t src,
|
||||
dma_addr_t dst, size_t len)
|
||||
{
|
||||
if (-ENOMEM == mic_dma_prog_memcpy_desc(ch, src, dst, len))
|
||||
return -ENOMEM;
|
||||
/* Above mic_dma_prog_memcpy_desc() makes sure we have enough space */
|
||||
if (flags & DMA_PREP_FENCE) {
|
||||
mic_dma_prep_status_desc(&ch->desc_ring[ch->head], 0,
|
||||
ch->status_dest_micpa, false);
|
||||
mic_dma_hw_ring_inc_head(ch);
|
||||
}
|
||||
|
||||
if (flags & DMA_PREP_INTERRUPT)
|
||||
mic_dma_prog_intr(ch);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void mic_dma_issue_pending(struct dma_chan *ch)
|
||||
{
|
||||
struct mic_dma_chan *mic_ch = to_mic_dma_chan(ch);
|
||||
|
||||
spin_lock(&mic_ch->issue_lock);
|
||||
/*
|
||||
* Write to head triggers h/w to act on the descriptors.
|
||||
* On MIC, writing the same head value twice causes
|
||||
* a h/w error. On second write, h/w assumes we filled
|
||||
* the entire ring & overwrote some of the descriptors.
|
||||
*/
|
||||
if (mic_ch->issued == mic_ch->submitted)
|
||||
goto out;
|
||||
mic_ch->issued = mic_ch->submitted;
|
||||
/*
|
||||
* make descriptor updates visible before advancing head,
|
||||
* this is purposefully not smp_wmb() since we are also
|
||||
* publishing the descriptor updates to a dma device
|
||||
*/
|
||||
wmb();
|
||||
mic_dma_write_reg(mic_ch, MIC_DMA_REG_DHPR, mic_ch->issued);
|
||||
out:
|
||||
spin_unlock(&mic_ch->issue_lock);
|
||||
}
|
||||
|
||||
static inline void mic_dma_update_pending(struct mic_dma_chan *ch)
|
||||
{
|
||||
if (mic_dma_ring_count(ch->issued, ch->submitted)
|
||||
> mic_dma_pending_level)
|
||||
mic_dma_issue_pending(&ch->api_ch);
|
||||
}
|
||||
|
||||
static dma_cookie_t mic_dma_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
|
||||
{
|
||||
struct mic_dma_chan *mic_ch = to_mic_dma_chan(tx->chan);
|
||||
dma_cookie_t cookie;
|
||||
|
||||
dma_cookie_assign(tx);
|
||||
cookie = tx->cookie;
|
||||
/*
|
||||
* We need an smp write barrier here because another CPU might see
|
||||
* an update to submitted and update h/w head even before we
|
||||
* assigned a cookie to this tx.
|
||||
*/
|
||||
smp_wmb();
|
||||
mic_ch->submitted = mic_ch->head;
|
||||
spin_unlock(&mic_ch->prep_lock);
|
||||
mic_dma_update_pending(mic_ch);
|
||||
return cookie;
|
||||
}
|
||||
|
||||
static inline struct dma_async_tx_descriptor *
|
||||
allocate_tx(struct mic_dma_chan *ch)
|
||||
{
|
||||
u32 idx = mic_dma_hw_ring_dec(ch->head);
|
||||
struct dma_async_tx_descriptor *tx = &ch->tx_array[idx];
|
||||
|
||||
dma_async_tx_descriptor_init(tx, &ch->api_ch);
|
||||
tx->tx_submit = mic_dma_tx_submit_unlock;
|
||||
return tx;
|
||||
}
|
||||
|
||||
/*
|
||||
* Prepare a memcpy descriptor to be added to the ring.
|
||||
* Note that the temporary descriptor adds an extra overhead of copying the
|
||||
* descriptor to ring. So, we copy directly to the descriptor ring
|
||||
*/
|
||||
static struct dma_async_tx_descriptor *
|
||||
mic_dma_prep_memcpy_lock(struct dma_chan *ch, dma_addr_t dma_dest,
|
||||
dma_addr_t dma_src, size_t len, unsigned long flags)
|
||||
{
|
||||
struct mic_dma_chan *mic_ch = to_mic_dma_chan(ch);
|
||||
struct device *dev = mic_dma_ch_to_device(mic_ch);
|
||||
int result;
|
||||
|
||||
if (!len && !flags)
|
||||
return NULL;
|
||||
|
||||
spin_lock(&mic_ch->prep_lock);
|
||||
result = mic_dma_do_dma(mic_ch, flags, dma_src, dma_dest, len);
|
||||
if (result >= 0)
|
||||
return allocate_tx(mic_ch);
|
||||
dev_err(dev, "Error enqueueing dma, error=%d\n", result);
|
||||
spin_unlock(&mic_ch->prep_lock);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *
|
||||
mic_dma_prep_interrupt_lock(struct dma_chan *ch, unsigned long flags)
|
||||
{
|
||||
struct mic_dma_chan *mic_ch = to_mic_dma_chan(ch);
|
||||
int ret;
|
||||
|
||||
spin_lock(&mic_ch->prep_lock);
|
||||
ret = mic_dma_do_dma(mic_ch, flags, 0, 0, 0);
|
||||
if (!ret)
|
||||
return allocate_tx(mic_ch);
|
||||
spin_unlock(&mic_ch->prep_lock);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Return the status of the transaction */
|
||||
static enum dma_status
|
||||
mic_dma_tx_status(struct dma_chan *ch, dma_cookie_t cookie,
|
||||
struct dma_tx_state *txstate)
|
||||
{
|
||||
struct mic_dma_chan *mic_ch = to_mic_dma_chan(ch);
|
||||
|
||||
if (DMA_COMPLETE != dma_cookie_status(ch, cookie, txstate))
|
||||
mic_dma_cleanup(mic_ch);
|
||||
|
||||
return dma_cookie_status(ch, cookie, txstate);
|
||||
}
|
||||
|
||||
static irqreturn_t mic_dma_thread_fn(int irq, void *data)
|
||||
{
|
||||
mic_dma_cleanup((struct mic_dma_chan *)data);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t mic_dma_intr_handler(int irq, void *data)
|
||||
{
|
||||
struct mic_dma_chan *ch = ((struct mic_dma_chan *)data);
|
||||
|
||||
mic_dma_ack_interrupt(ch);
|
||||
return IRQ_WAKE_THREAD;
|
||||
}
|
||||
|
||||
static int mic_dma_alloc_desc_ring(struct mic_dma_chan *ch)
|
||||
{
|
||||
u64 desc_ring_size = MIC_DMA_DESC_RX_SIZE * sizeof(*ch->desc_ring);
|
||||
struct device *dev = &to_mbus_device(ch)->dev;
|
||||
|
||||
desc_ring_size = ALIGN(desc_ring_size, MIC_DMA_ALIGN_BYTES);
|
||||
ch->desc_ring = kzalloc(desc_ring_size, GFP_KERNEL);
|
||||
|
||||
if (!ch->desc_ring)
|
||||
return -ENOMEM;
|
||||
|
||||
ch->desc_ring_micpa = dma_map_single(dev, ch->desc_ring,
|
||||
desc_ring_size, DMA_BIDIRECTIONAL);
|
||||
if (dma_mapping_error(dev, ch->desc_ring_micpa))
|
||||
goto map_error;
|
||||
|
||||
ch->tx_array = vzalloc(MIC_DMA_DESC_RX_SIZE * sizeof(*ch->tx_array));
|
||||
if (!ch->tx_array)
|
||||
goto tx_error;
|
||||
return 0;
|
||||
tx_error:
|
||||
dma_unmap_single(dev, ch->desc_ring_micpa, desc_ring_size,
|
||||
DMA_BIDIRECTIONAL);
|
||||
map_error:
|
||||
kfree(ch->desc_ring);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
static void mic_dma_free_desc_ring(struct mic_dma_chan *ch)
|
||||
{
|
||||
u64 desc_ring_size = MIC_DMA_DESC_RX_SIZE * sizeof(*ch->desc_ring);
|
||||
|
||||
vfree(ch->tx_array);
|
||||
desc_ring_size = ALIGN(desc_ring_size, MIC_DMA_ALIGN_BYTES);
|
||||
dma_unmap_single(&to_mbus_device(ch)->dev, ch->desc_ring_micpa,
|
||||
desc_ring_size, DMA_BIDIRECTIONAL);
|
||||
kfree(ch->desc_ring);
|
||||
ch->desc_ring = NULL;
|
||||
}
|
||||
|
||||
static void mic_dma_free_status_dest(struct mic_dma_chan *ch)
|
||||
{
|
||||
dma_unmap_single(&to_mbus_device(ch)->dev, ch->status_dest_micpa,
|
||||
L1_CACHE_BYTES, DMA_BIDIRECTIONAL);
|
||||
kfree(ch->status_dest);
|
||||
}
|
||||
|
||||
static int mic_dma_alloc_status_dest(struct mic_dma_chan *ch)
|
||||
{
|
||||
struct device *dev = &to_mbus_device(ch)->dev;
|
||||
|
||||
ch->status_dest = kzalloc(L1_CACHE_BYTES, GFP_KERNEL);
|
||||
if (!ch->status_dest)
|
||||
return -ENOMEM;
|
||||
ch->status_dest_micpa = dma_map_single(dev, ch->status_dest,
|
||||
L1_CACHE_BYTES, DMA_BIDIRECTIONAL);
|
||||
if (dma_mapping_error(dev, ch->status_dest_micpa)) {
|
||||
kfree(ch->status_dest);
|
||||
ch->status_dest = NULL;
|
||||
return -ENOMEM;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mic_dma_check_chan(struct mic_dma_chan *ch)
|
||||
{
|
||||
if (mic_dma_read_reg(ch, MIC_DMA_REG_DCHERR) ||
|
||||
mic_dma_read_reg(ch, MIC_DMA_REG_DSTAT) & MIC_DMA_CHAN_QUIESCE) {
|
||||
mic_dma_disable_chan(ch);
|
||||
mic_dma_chan_mask_intr(ch);
|
||||
dev_err(mic_dma_ch_to_device(ch),
|
||||
"%s %d error setting up mic dma chan %d\n",
|
||||
__func__, __LINE__, ch->ch_num);
|
||||
return -EBUSY;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mic_dma_chan_setup(struct mic_dma_chan *ch)
|
||||
{
|
||||
if (MIC_DMA_CHAN_MIC == ch->owner)
|
||||
mic_dma_chan_set_owner(ch);
|
||||
mic_dma_disable_chan(ch);
|
||||
mic_dma_chan_mask_intr(ch);
|
||||
mic_dma_write_reg(ch, MIC_DMA_REG_DCHERRMSK, 0);
|
||||
mic_dma_chan_set_desc_ring(ch);
|
||||
ch->last_tail = mic_dma_read_reg(ch, MIC_DMA_REG_DTPR);
|
||||
ch->head = ch->last_tail;
|
||||
ch->issued = 0;
|
||||
mic_dma_chan_unmask_intr(ch);
|
||||
mic_dma_enable_chan(ch);
|
||||
return mic_dma_check_chan(ch);
|
||||
}
|
||||
|
||||
static void mic_dma_chan_destroy(struct mic_dma_chan *ch)
|
||||
{
|
||||
mic_dma_disable_chan(ch);
|
||||
mic_dma_chan_mask_intr(ch);
|
||||
}
|
||||
|
||||
static void mic_dma_unregister_dma_device(struct mic_dma_device *mic_dma_dev)
|
||||
{
|
||||
dma_async_device_unregister(&mic_dma_dev->dma_dev);
|
||||
}
|
||||
|
||||
static int mic_dma_setup_irq(struct mic_dma_chan *ch)
|
||||
{
|
||||
ch->cookie =
|
||||
to_mbus_hw_ops(ch)->request_threaded_irq(to_mbus_device(ch),
|
||||
mic_dma_intr_handler, mic_dma_thread_fn,
|
||||
"mic dma_channel", ch, ch->ch_num);
|
||||
if (IS_ERR(ch->cookie))
|
||||
return IS_ERR(ch->cookie);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void mic_dma_free_irq(struct mic_dma_chan *ch)
|
||||
{
|
||||
to_mbus_hw_ops(ch)->free_irq(to_mbus_device(ch), ch->cookie, ch);
|
||||
}
|
||||
|
||||
static int mic_dma_chan_init(struct mic_dma_chan *ch)
|
||||
{
|
||||
int ret = mic_dma_alloc_desc_ring(ch);
|
||||
|
||||
if (ret)
|
||||
goto ring_error;
|
||||
ret = mic_dma_alloc_status_dest(ch);
|
||||
if (ret)
|
||||
goto status_error;
|
||||
ret = mic_dma_chan_setup(ch);
|
||||
if (ret)
|
||||
goto chan_error;
|
||||
return ret;
|
||||
chan_error:
|
||||
mic_dma_free_status_dest(ch);
|
||||
status_error:
|
||||
mic_dma_free_desc_ring(ch);
|
||||
ring_error:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mic_dma_drain_chan(struct mic_dma_chan *ch)
|
||||
{
|
||||
struct dma_async_tx_descriptor *tx;
|
||||
int err = 0;
|
||||
dma_cookie_t cookie;
|
||||
|
||||
tx = mic_dma_prep_memcpy_lock(&ch->api_ch, 0, 0, 0, DMA_PREP_FENCE);
|
||||
if (!tx) {
|
||||
err = -ENOMEM;
|
||||
goto error;
|
||||
}
|
||||
|
||||
cookie = tx->tx_submit(tx);
|
||||
if (dma_submit_error(cookie))
|
||||
err = -ENOMEM;
|
||||
else
|
||||
err = dma_sync_wait(&ch->api_ch, cookie);
|
||||
if (err) {
|
||||
dev_err(mic_dma_ch_to_device(ch), "%s %d TO chan 0x%x\n",
|
||||
__func__, __LINE__, ch->ch_num);
|
||||
err = -EIO;
|
||||
}
|
||||
error:
|
||||
mic_dma_cleanup(ch);
|
||||
return err;
|
||||
}
|
||||
|
||||
static inline void mic_dma_chan_uninit(struct mic_dma_chan *ch)
|
||||
{
|
||||
mic_dma_chan_destroy(ch);
|
||||
mic_dma_cleanup(ch);
|
||||
mic_dma_free_status_dest(ch);
|
||||
mic_dma_free_desc_ring(ch);
|
||||
}
|
||||
|
||||
static int mic_dma_init(struct mic_dma_device *mic_dma_dev,
|
||||
enum mic_dma_chan_owner owner)
|
||||
{
|
||||
int i, first_chan = mic_dma_dev->start_ch;
|
||||
struct mic_dma_chan *ch;
|
||||
int ret;
|
||||
|
||||
for (i = first_chan; i < first_chan + MIC_DMA_NUM_CHAN; i++) {
|
||||
unsigned long data;
|
||||
ch = &mic_dma_dev->mic_ch[i];
|
||||
data = (unsigned long)ch;
|
||||
ch->ch_num = i;
|
||||
ch->owner = owner;
|
||||
spin_lock_init(&ch->cleanup_lock);
|
||||
spin_lock_init(&ch->prep_lock);
|
||||
spin_lock_init(&ch->issue_lock);
|
||||
ret = mic_dma_setup_irq(ch);
|
||||
if (ret)
|
||||
goto error;
|
||||
}
|
||||
return 0;
|
||||
error:
|
||||
for (i = i - 1; i >= first_chan; i--)
|
||||
mic_dma_free_irq(ch);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mic_dma_uninit(struct mic_dma_device *mic_dma_dev)
|
||||
{
|
||||
int i, first_chan = mic_dma_dev->start_ch;
|
||||
struct mic_dma_chan *ch;
|
||||
|
||||
for (i = first_chan; i < first_chan + MIC_DMA_NUM_CHAN; i++) {
|
||||
ch = &mic_dma_dev->mic_ch[i];
|
||||
mic_dma_free_irq(ch);
|
||||
}
|
||||
}
|
||||
|
||||
static int mic_dma_alloc_chan_resources(struct dma_chan *ch)
|
||||
{
|
||||
int ret = mic_dma_chan_init(to_mic_dma_chan(ch));
|
||||
if (ret)
|
||||
return ret;
|
||||
return MIC_DMA_DESC_RX_SIZE;
|
||||
}
|
||||
|
||||
static void mic_dma_free_chan_resources(struct dma_chan *ch)
|
||||
{
|
||||
struct mic_dma_chan *mic_ch = to_mic_dma_chan(ch);
|
||||
mic_dma_drain_chan(mic_ch);
|
||||
mic_dma_chan_uninit(mic_ch);
|
||||
}
|
||||
|
||||
/* Set the fn. handlers and register the dma device with dma api */
|
||||
static int mic_dma_register_dma_device(struct mic_dma_device *mic_dma_dev,
|
||||
enum mic_dma_chan_owner owner)
|
||||
{
|
||||
int i, first_chan = mic_dma_dev->start_ch;
|
||||
|
||||
dma_cap_zero(mic_dma_dev->dma_dev.cap_mask);
|
||||
/*
|
||||
* This dma engine is not capable of host memory to host memory
|
||||
* transfers
|
||||
*/
|
||||
dma_cap_set(DMA_MEMCPY, mic_dma_dev->dma_dev.cap_mask);
|
||||
|
||||
if (MIC_DMA_CHAN_HOST == owner)
|
||||
dma_cap_set(DMA_PRIVATE, mic_dma_dev->dma_dev.cap_mask);
|
||||
mic_dma_dev->dma_dev.device_alloc_chan_resources =
|
||||
mic_dma_alloc_chan_resources;
|
||||
mic_dma_dev->dma_dev.device_free_chan_resources =
|
||||
mic_dma_free_chan_resources;
|
||||
mic_dma_dev->dma_dev.device_tx_status = mic_dma_tx_status;
|
||||
mic_dma_dev->dma_dev.device_prep_dma_memcpy = mic_dma_prep_memcpy_lock;
|
||||
mic_dma_dev->dma_dev.device_prep_dma_interrupt =
|
||||
mic_dma_prep_interrupt_lock;
|
||||
mic_dma_dev->dma_dev.device_issue_pending = mic_dma_issue_pending;
|
||||
mic_dma_dev->dma_dev.copy_align = MIC_DMA_ALIGN_SHIFT;
|
||||
INIT_LIST_HEAD(&mic_dma_dev->dma_dev.channels);
|
||||
for (i = first_chan; i < first_chan + MIC_DMA_NUM_CHAN; i++) {
|
||||
mic_dma_dev->mic_ch[i].api_ch.device = &mic_dma_dev->dma_dev;
|
||||
dma_cookie_init(&mic_dma_dev->mic_ch[i].api_ch);
|
||||
list_add_tail(&mic_dma_dev->mic_ch[i].api_ch.device_node,
|
||||
&mic_dma_dev->dma_dev.channels);
|
||||
}
|
||||
return dma_async_device_register(&mic_dma_dev->dma_dev);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initializes dma channels and registers the dma device with the
|
||||
* dma engine api.
|
||||
*/
|
||||
static struct mic_dma_device *mic_dma_dev_reg(struct mbus_device *mbdev,
|
||||
enum mic_dma_chan_owner owner)
|
||||
{
|
||||
struct mic_dma_device *mic_dma_dev;
|
||||
int ret;
|
||||
struct device *dev = &mbdev->dev;
|
||||
|
||||
mic_dma_dev = kzalloc(sizeof(*mic_dma_dev), GFP_KERNEL);
|
||||
if (!mic_dma_dev) {
|
||||
ret = -ENOMEM;
|
||||
goto alloc_error;
|
||||
}
|
||||
mic_dma_dev->mbdev = mbdev;
|
||||
mic_dma_dev->dma_dev.dev = dev;
|
||||
mic_dma_dev->mmio = mbdev->mmio_va;
|
||||
if (MIC_DMA_CHAN_HOST == owner) {
|
||||
mic_dma_dev->start_ch = 0;
|
||||
mic_dma_dev->max_xfer_size = MIC_DMA_MAX_XFER_SIZE_HOST;
|
||||
} else {
|
||||
mic_dma_dev->start_ch = 4;
|
||||
mic_dma_dev->max_xfer_size = MIC_DMA_MAX_XFER_SIZE_CARD;
|
||||
}
|
||||
ret = mic_dma_init(mic_dma_dev, owner);
|
||||
if (ret)
|
||||
goto init_error;
|
||||
ret = mic_dma_register_dma_device(mic_dma_dev, owner);
|
||||
if (ret)
|
||||
goto reg_error;
|
||||
return mic_dma_dev;
|
||||
reg_error:
|
||||
mic_dma_uninit(mic_dma_dev);
|
||||
init_error:
|
||||
kfree(mic_dma_dev);
|
||||
mic_dma_dev = NULL;
|
||||
alloc_error:
|
||||
dev_err(dev, "Error at %s %d ret=%d\n", __func__, __LINE__, ret);
|
||||
return mic_dma_dev;
|
||||
}
|
||||
|
||||
static void mic_dma_dev_unreg(struct mic_dma_device *mic_dma_dev)
|
||||
{
|
||||
mic_dma_unregister_dma_device(mic_dma_dev);
|
||||
mic_dma_uninit(mic_dma_dev);
|
||||
kfree(mic_dma_dev);
|
||||
}
|
||||
|
||||
/* DEBUGFS CODE */
|
||||
static int mic_dma_reg_seq_show(struct seq_file *s, void *pos)
|
||||
{
|
||||
struct mic_dma_device *mic_dma_dev = s->private;
|
||||
int i, chan_num, first_chan = mic_dma_dev->start_ch;
|
||||
struct mic_dma_chan *ch;
|
||||
|
||||
seq_printf(s, "SBOX_DCR: %#x\n",
|
||||
mic_dma_mmio_read(&mic_dma_dev->mic_ch[first_chan],
|
||||
MIC_DMA_SBOX_BASE + MIC_DMA_SBOX_DCR));
|
||||
seq_puts(s, "DMA Channel Registers\n");
|
||||
seq_printf(s, "%-10s| %-10s %-10s %-10s %-10s %-10s",
|
||||
"Channel", "DCAR", "DTPR", "DHPR", "DRAR_HI", "DRAR_LO");
|
||||
seq_printf(s, " %-11s %-14s %-10s\n", "DCHERR", "DCHERRMSK", "DSTAT");
|
||||
for (i = first_chan; i < first_chan + MIC_DMA_NUM_CHAN; i++) {
|
||||
ch = &mic_dma_dev->mic_ch[i];
|
||||
chan_num = ch->ch_num;
|
||||
seq_printf(s, "%-10i| %-#10x %-#10x %-#10x %-#10x",
|
||||
chan_num,
|
||||
mic_dma_read_reg(ch, MIC_DMA_REG_DCAR),
|
||||
mic_dma_read_reg(ch, MIC_DMA_REG_DTPR),
|
||||
mic_dma_read_reg(ch, MIC_DMA_REG_DHPR),
|
||||
mic_dma_read_reg(ch, MIC_DMA_REG_DRAR_HI));
|
||||
seq_printf(s, " %-#10x %-#10x %-#14x %-#10x\n",
|
||||
mic_dma_read_reg(ch, MIC_DMA_REG_DRAR_LO),
|
||||
mic_dma_read_reg(ch, MIC_DMA_REG_DCHERR),
|
||||
mic_dma_read_reg(ch, MIC_DMA_REG_DCHERRMSK),
|
||||
mic_dma_read_reg(ch, MIC_DMA_REG_DSTAT));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mic_dma_reg_debug_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, mic_dma_reg_seq_show, inode->i_private);
|
||||
}
|
||||
|
||||
static int mic_dma_reg_debug_release(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_release(inode, file);
|
||||
}
|
||||
|
||||
static const struct file_operations mic_dma_reg_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = mic_dma_reg_debug_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = mic_dma_reg_debug_release
|
||||
};
|
||||
|
||||
/* Debugfs parent dir */
|
||||
static struct dentry *mic_dma_dbg;
|
||||
|
||||
static int mic_dma_driver_probe(struct mbus_device *mbdev)
|
||||
{
|
||||
struct mic_dma_device *mic_dma_dev;
|
||||
enum mic_dma_chan_owner owner;
|
||||
|
||||
if (MBUS_DEV_DMA_MIC == mbdev->id.device)
|
||||
owner = MIC_DMA_CHAN_MIC;
|
||||
else
|
||||
owner = MIC_DMA_CHAN_HOST;
|
||||
|
||||
mic_dma_dev = mic_dma_dev_reg(mbdev, owner);
|
||||
dev_set_drvdata(&mbdev->dev, mic_dma_dev);
|
||||
|
||||
if (mic_dma_dbg) {
|
||||
mic_dma_dev->dbg_dir = debugfs_create_dir(dev_name(&mbdev->dev),
|
||||
mic_dma_dbg);
|
||||
if (mic_dma_dev->dbg_dir)
|
||||
debugfs_create_file("mic_dma_reg", 0444,
|
||||
mic_dma_dev->dbg_dir, mic_dma_dev,
|
||||
&mic_dma_reg_ops);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mic_dma_driver_remove(struct mbus_device *mbdev)
|
||||
{
|
||||
struct mic_dma_device *mic_dma_dev;
|
||||
|
||||
mic_dma_dev = dev_get_drvdata(&mbdev->dev);
|
||||
debugfs_remove_recursive(mic_dma_dev->dbg_dir);
|
||||
mic_dma_dev_unreg(mic_dma_dev);
|
||||
}
|
||||
|
||||
static struct mbus_device_id id_table[] = {
|
||||
{MBUS_DEV_DMA_MIC, MBUS_DEV_ANY_ID},
|
||||
{MBUS_DEV_DMA_HOST, MBUS_DEV_ANY_ID},
|
||||
{0},
|
||||
};
|
||||
|
||||
static struct mbus_driver mic_dma_driver = {
|
||||
.driver.name = KBUILD_MODNAME,
|
||||
.driver.owner = THIS_MODULE,
|
||||
.id_table = id_table,
|
||||
.probe = mic_dma_driver_probe,
|
||||
.remove = mic_dma_driver_remove,
|
||||
};
|
||||
|
||||
static int __init mic_x100_dma_init(void)
|
||||
{
|
||||
int rc = mbus_register_driver(&mic_dma_driver);
|
||||
if (rc)
|
||||
return rc;
|
||||
mic_dma_dbg = debugfs_create_dir(KBUILD_MODNAME, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit mic_x100_dma_exit(void)
|
||||
{
|
||||
debugfs_remove_recursive(mic_dma_dbg);
|
||||
mbus_unregister_driver(&mic_dma_driver);
|
||||
}
|
||||
|
||||
module_init(mic_x100_dma_init);
|
||||
module_exit(mic_x100_dma_exit);
|
||||
|
||||
MODULE_DEVICE_TABLE(mbus, id_table);
|
||||
MODULE_AUTHOR("Intel Corporation");
|
||||
MODULE_DESCRIPTION("Intel(R) MIC X100 DMA Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
286
drivers/dma/mic_x100_dma.h
Normal file
286
drivers/dma/mic_x100_dma.h
Normal file
|
|
@ -0,0 +1,286 @@
|
|||
/*
|
||||
* Intel MIC Platform Software Stack (MPSS)
|
||||
*
|
||||
* Copyright(c) 2014 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
* Intel MIC X100 DMA Driver.
|
||||
*
|
||||
* Adapted from IOAT dma driver.
|
||||
*/
|
||||
#ifndef _MIC_X100_DMA_H_
|
||||
#define _MIC_X100_DMA_H_
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/mic_bus.h>
|
||||
|
||||
#include "dmaengine.h"
|
||||
|
||||
/*
|
||||
* MIC has a total of 8 dma channels.
|
||||
* Four channels are assigned for host SW use & the remaining for MIC SW.
|
||||
* MIC DMA transfer size & addresses need to be 64 byte aligned.
|
||||
*/
|
||||
#define MIC_DMA_MAX_NUM_CHAN 8
|
||||
#define MIC_DMA_NUM_CHAN 4
|
||||
#define MIC_DMA_ALIGN_SHIFT 6
|
||||
#define MIC_DMA_ALIGN_BYTES (1 << MIC_DMA_ALIGN_SHIFT)
|
||||
#define MIC_DMA_DESC_RX_SIZE (128 * 1024 - 4)
|
||||
|
||||
/*
|
||||
* Register descriptions
|
||||
* All the registers are 32 bit registers.
|
||||
* DCR is a global register and all others are per-channel.
|
||||
* DCR - bits 0, 2, 4, 6, 8, 10, 12, 14 - enable bits for channels 0 to 7
|
||||
* bits 1, 3, 5, 7, 9, 11, 13, 15 - owner bits for channels 0 to 7
|
||||
* DCAR - bit 24 & 25 interrupt masks for mic owned & host owned channels
|
||||
* DHPR - head of the descriptor ring updated by s/w
|
||||
* DTPR - tail of the descriptor ring updated by h/w
|
||||
* DRAR_LO - lower 32 bits of descriptor ring's mic address
|
||||
* DRAR_HI - 3:0 - remaining 4 bits of descriptor ring's mic address
|
||||
* 20:4 descriptor ring size
|
||||
* 25:21 mic smpt entry number
|
||||
* DSTAT - 16:0 h/w completion count; 31:28 dma engine status
|
||||
* DCHERR - this register is non-zero on error
|
||||
* DCHERRMSK - interrupt mask register
|
||||
*/
|
||||
#define MIC_DMA_HW_CMP_CNT_MASK 0x1ffff
|
||||
#define MIC_DMA_CHAN_QUIESCE 0x20000000
|
||||
#define MIC_DMA_SBOX_BASE 0x00010000
|
||||
#define MIC_DMA_SBOX_DCR 0x0000A280
|
||||
#define MIC_DMA_SBOX_CH_BASE 0x0001A000
|
||||
#define MIC_DMA_SBOX_CHAN_OFF 0x40
|
||||
#define MIC_DMA_SBOX_DCAR_IM0 (0x1 << 24)
|
||||
#define MIC_DMA_SBOX_DCAR_IM1 (0x1 << 25)
|
||||
#define MIC_DMA_SBOX_DRARHI_SYS_MASK (0x1 << 26)
|
||||
#define MIC_DMA_REG_DCAR 0
|
||||
#define MIC_DMA_REG_DHPR 4
|
||||
#define MIC_DMA_REG_DTPR 8
|
||||
#define MIC_DMA_REG_DRAR_LO 20
|
||||
#define MIC_DMA_REG_DRAR_HI 24
|
||||
#define MIC_DMA_REG_DSTAT 32
|
||||
#define MIC_DMA_REG_DCHERR 44
|
||||
#define MIC_DMA_REG_DCHERRMSK 48
|
||||
|
||||
/* HW dma desc */
|
||||
struct mic_dma_desc {
|
||||
u64 qw0;
|
||||
u64 qw1;
|
||||
};
|
||||
|
||||
enum mic_dma_chan_owner {
|
||||
MIC_DMA_CHAN_MIC = 0,
|
||||
MIC_DMA_CHAN_HOST
|
||||
};
|
||||
|
||||
/*
|
||||
* mic_dma_chan - channel specific information
|
||||
* @ch_num: channel number
|
||||
* @owner: owner of this channel
|
||||
* @last_tail: cached value of descriptor ring tail
|
||||
* @head: index of next descriptor in desc_ring
|
||||
* @issued: hardware notification point
|
||||
* @submitted: index that will be used to submit descriptors to h/w
|
||||
* @api_ch: dma engine api channel
|
||||
* @desc_ring: dma descriptor ring
|
||||
* @desc_ring_micpa: mic physical address of desc_ring
|
||||
* @status_dest: destination for status (fence) descriptor
|
||||
* @status_dest_micpa: mic address for status_dest,
|
||||
* DMA controller uses this address
|
||||
* @tx_array: array of async_tx
|
||||
* @cleanup_lock: lock held when processing completed tx
|
||||
* @prep_lock: lock held in prep_memcpy & released in tx_submit
|
||||
* @issue_lock: lock used to synchronize writes to head
|
||||
* @cookie: mic_irq cookie used with mic irq request
|
||||
*/
|
||||
struct mic_dma_chan {
|
||||
int ch_num;
|
||||
enum mic_dma_chan_owner owner;
|
||||
u32 last_tail;
|
||||
u32 head;
|
||||
u32 issued;
|
||||
u32 submitted;
|
||||
struct dma_chan api_ch;
|
||||
struct mic_dma_desc *desc_ring;
|
||||
dma_addr_t desc_ring_micpa;
|
||||
u64 *status_dest;
|
||||
dma_addr_t status_dest_micpa;
|
||||
struct dma_async_tx_descriptor *tx_array;
|
||||
spinlock_t cleanup_lock;
|
||||
spinlock_t prep_lock;
|
||||
spinlock_t issue_lock;
|
||||
struct mic_irq *cookie;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct mic_dma_device - per mic device
|
||||
* @mic_ch: dma channels
|
||||
* @dma_dev: underlying dma device
|
||||
* @mbdev: mic bus dma device
|
||||
* @mmio: virtual address of the mmio space
|
||||
* @dbg_dir: debugfs directory
|
||||
* @start_ch: first channel number that can be used
|
||||
* @max_xfer_size: maximum transfer size per dma descriptor
|
||||
*/
|
||||
struct mic_dma_device {
|
||||
struct mic_dma_chan mic_ch[MIC_DMA_MAX_NUM_CHAN];
|
||||
struct dma_device dma_dev;
|
||||
struct mbus_device *mbdev;
|
||||
void __iomem *mmio;
|
||||
struct dentry *dbg_dir;
|
||||
int start_ch;
|
||||
size_t max_xfer_size;
|
||||
};
|
||||
|
||||
static inline struct mic_dma_chan *to_mic_dma_chan(struct dma_chan *ch)
|
||||
{
|
||||
return container_of(ch, struct mic_dma_chan, api_ch);
|
||||
}
|
||||
|
||||
static inline struct mic_dma_device *to_mic_dma_dev(struct mic_dma_chan *ch)
|
||||
{
|
||||
return
|
||||
container_of((const typeof(((struct mic_dma_device *)0)->mic_ch)*)
|
||||
(ch - ch->ch_num), struct mic_dma_device, mic_ch);
|
||||
}
|
||||
|
||||
static inline struct mbus_device *to_mbus_device(struct mic_dma_chan *ch)
|
||||
{
|
||||
return to_mic_dma_dev(ch)->mbdev;
|
||||
}
|
||||
|
||||
static inline struct mbus_hw_ops *to_mbus_hw_ops(struct mic_dma_chan *ch)
|
||||
{
|
||||
return to_mbus_device(ch)->hw_ops;
|
||||
}
|
||||
|
||||
static inline struct device *mic_dma_ch_to_device(struct mic_dma_chan *ch)
|
||||
{
|
||||
return to_mic_dma_dev(ch)->dma_dev.dev;
|
||||
}
|
||||
|
||||
static inline void __iomem *mic_dma_chan_to_mmio(struct mic_dma_chan *ch)
|
||||
{
|
||||
return to_mic_dma_dev(ch)->mmio;
|
||||
}
|
||||
|
||||
static inline u32 mic_dma_read_reg(struct mic_dma_chan *ch, u32 reg)
|
||||
{
|
||||
return ioread32(mic_dma_chan_to_mmio(ch) + MIC_DMA_SBOX_CH_BASE +
|
||||
ch->ch_num * MIC_DMA_SBOX_CHAN_OFF + reg);
|
||||
}
|
||||
|
||||
static inline void mic_dma_write_reg(struct mic_dma_chan *ch, u32 reg, u32 val)
|
||||
{
|
||||
iowrite32(val, mic_dma_chan_to_mmio(ch) + MIC_DMA_SBOX_CH_BASE +
|
||||
ch->ch_num * MIC_DMA_SBOX_CHAN_OFF + reg);
|
||||
}
|
||||
|
||||
static inline u32 mic_dma_mmio_read(struct mic_dma_chan *ch, u32 offset)
|
||||
{
|
||||
return ioread32(mic_dma_chan_to_mmio(ch) + offset);
|
||||
}
|
||||
|
||||
static inline void mic_dma_mmio_write(struct mic_dma_chan *ch, u32 val,
|
||||
u32 offset)
|
||||
{
|
||||
iowrite32(val, mic_dma_chan_to_mmio(ch) + offset);
|
||||
}
|
||||
|
||||
static inline u32 mic_dma_read_cmp_cnt(struct mic_dma_chan *ch)
|
||||
{
|
||||
return mic_dma_read_reg(ch, MIC_DMA_REG_DSTAT) &
|
||||
MIC_DMA_HW_CMP_CNT_MASK;
|
||||
}
|
||||
|
||||
static inline void mic_dma_chan_set_owner(struct mic_dma_chan *ch)
|
||||
{
|
||||
u32 dcr = mic_dma_mmio_read(ch, MIC_DMA_SBOX_BASE + MIC_DMA_SBOX_DCR);
|
||||
u32 chan_num = ch->ch_num;
|
||||
|
||||
dcr = (dcr & ~(0x1 << (chan_num * 2))) | (ch->owner << (chan_num * 2));
|
||||
mic_dma_mmio_write(ch, dcr, MIC_DMA_SBOX_BASE + MIC_DMA_SBOX_DCR);
|
||||
}
|
||||
|
||||
static inline void mic_dma_enable_chan(struct mic_dma_chan *ch)
|
||||
{
|
||||
u32 dcr = mic_dma_mmio_read(ch, MIC_DMA_SBOX_BASE + MIC_DMA_SBOX_DCR);
|
||||
|
||||
dcr |= 2 << (ch->ch_num << 1);
|
||||
mic_dma_mmio_write(ch, dcr, MIC_DMA_SBOX_BASE + MIC_DMA_SBOX_DCR);
|
||||
}
|
||||
|
||||
static inline void mic_dma_disable_chan(struct mic_dma_chan *ch)
|
||||
{
|
||||
u32 dcr = mic_dma_mmio_read(ch, MIC_DMA_SBOX_BASE + MIC_DMA_SBOX_DCR);
|
||||
|
||||
dcr &= ~(2 << (ch->ch_num << 1));
|
||||
mic_dma_mmio_write(ch, dcr, MIC_DMA_SBOX_BASE + MIC_DMA_SBOX_DCR);
|
||||
}
|
||||
|
||||
static void mic_dma_chan_set_desc_ring(struct mic_dma_chan *ch)
|
||||
{
|
||||
u32 drar_hi;
|
||||
dma_addr_t desc_ring_micpa = ch->desc_ring_micpa;
|
||||
|
||||
drar_hi = (MIC_DMA_DESC_RX_SIZE & 0x1ffff) << 4;
|
||||
if (MIC_DMA_CHAN_MIC == ch->owner) {
|
||||
drar_hi |= (desc_ring_micpa >> 32) & 0xf;
|
||||
} else {
|
||||
drar_hi |= MIC_DMA_SBOX_DRARHI_SYS_MASK;
|
||||
drar_hi |= ((desc_ring_micpa >> 34)
|
||||
& 0x1f) << 21;
|
||||
drar_hi |= (desc_ring_micpa >> 32) & 0x3;
|
||||
}
|
||||
mic_dma_write_reg(ch, MIC_DMA_REG_DRAR_LO, (u32) desc_ring_micpa);
|
||||
mic_dma_write_reg(ch, MIC_DMA_REG_DRAR_HI, drar_hi);
|
||||
}
|
||||
|
||||
static inline void mic_dma_chan_mask_intr(struct mic_dma_chan *ch)
|
||||
{
|
||||
u32 dcar = mic_dma_read_reg(ch, MIC_DMA_REG_DCAR);
|
||||
|
||||
if (MIC_DMA_CHAN_MIC == ch->owner)
|
||||
dcar |= MIC_DMA_SBOX_DCAR_IM0;
|
||||
else
|
||||
dcar |= MIC_DMA_SBOX_DCAR_IM1;
|
||||
mic_dma_write_reg(ch, MIC_DMA_REG_DCAR, dcar);
|
||||
}
|
||||
|
||||
static inline void mic_dma_chan_unmask_intr(struct mic_dma_chan *ch)
|
||||
{
|
||||
u32 dcar = mic_dma_read_reg(ch, MIC_DMA_REG_DCAR);
|
||||
|
||||
if (MIC_DMA_CHAN_MIC == ch->owner)
|
||||
dcar &= ~MIC_DMA_SBOX_DCAR_IM0;
|
||||
else
|
||||
dcar &= ~MIC_DMA_SBOX_DCAR_IM1;
|
||||
mic_dma_write_reg(ch, MIC_DMA_REG_DCAR, dcar);
|
||||
}
|
||||
|
||||
static void mic_dma_ack_interrupt(struct mic_dma_chan *ch)
|
||||
{
|
||||
if (MIC_DMA_CHAN_MIC == ch->owner) {
|
||||
/* HW errata */
|
||||
mic_dma_chan_mask_intr(ch);
|
||||
mic_dma_chan_unmask_intr(ch);
|
||||
}
|
||||
to_mbus_hw_ops(ch)->ack_interrupt(to_mbus_device(ch), ch->ch_num);
|
||||
}
|
||||
#endif
|
||||
1126
drivers/dma/mmp_pdma.c
Normal file
1126
drivers/dma/mmp_pdma.c
Normal file
File diff suppressed because it is too large
Load diff
720
drivers/dma/mmp_tdma.c
Normal file
720
drivers/dma/mmp_tdma.c
Normal file
|
|
@ -0,0 +1,720 @@
|
|||
/*
|
||||
* Driver For Marvell Two-channel DMA Engine
|
||||
*
|
||||
* Copyright: Marvell International Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/device.h>
|
||||
#include <mach/regs-icu.h>
|
||||
#include <linux/platform_data/dma-mmp_tdma.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_dma.h>
|
||||
|
||||
#include "dmaengine.h"
|
||||
|
||||
/*
|
||||
* Two-Channel DMA registers
|
||||
*/
|
||||
#define TDBCR 0x00 /* Byte Count */
|
||||
#define TDSAR 0x10 /* Src Addr */
|
||||
#define TDDAR 0x20 /* Dst Addr */
|
||||
#define TDNDPR 0x30 /* Next Desc */
|
||||
#define TDCR 0x40 /* Control */
|
||||
#define TDCP 0x60 /* Priority*/
|
||||
#define TDCDPR 0x70 /* Current Desc */
|
||||
#define TDIMR 0x80 /* Int Mask */
|
||||
#define TDISR 0xa0 /* Int Status */
|
||||
|
||||
/* Two-Channel DMA Control Register */
|
||||
#define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */
|
||||
#define TDCR_SSZ_12_BITS (0x1 << 22)
|
||||
#define TDCR_SSZ_16_BITS (0x2 << 22)
|
||||
#define TDCR_SSZ_20_BITS (0x3 << 22)
|
||||
#define TDCR_SSZ_24_BITS (0x4 << 22)
|
||||
#define TDCR_SSZ_32_BITS (0x5 << 22)
|
||||
#define TDCR_SSZ_SHIFT (0x1 << 22)
|
||||
#define TDCR_SSZ_MASK (0x7 << 22)
|
||||
#define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */
|
||||
#define TDCR_ABR (0x1 << 20) /* Channel Abort */
|
||||
#define TDCR_CDE (0x1 << 17) /* Close Desc Enable */
|
||||
#define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */
|
||||
#define TDCR_CHANACT (0x1 << 14) /* Channel Active */
|
||||
#define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */
|
||||
#define TDCR_CHANEN (0x1 << 12) /* Channel Enable */
|
||||
#define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */
|
||||
#define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */
|
||||
#define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */
|
||||
#define TDCR_BURSTSZ_4B (0x0 << 6)
|
||||
#define TDCR_BURSTSZ_8B (0x1 << 6)
|
||||
#define TDCR_BURSTSZ_16B (0x3 << 6)
|
||||
#define TDCR_BURSTSZ_32B (0x6 << 6)
|
||||
#define TDCR_BURSTSZ_64B (0x7 << 6)
|
||||
#define TDCR_BURSTSZ_SQU_1B (0x5 << 6)
|
||||
#define TDCR_BURSTSZ_SQU_2B (0x6 << 6)
|
||||
#define TDCR_BURSTSZ_SQU_4B (0x0 << 6)
|
||||
#define TDCR_BURSTSZ_SQU_8B (0x1 << 6)
|
||||
#define TDCR_BURSTSZ_SQU_16B (0x3 << 6)
|
||||
#define TDCR_BURSTSZ_SQU_32B (0x7 << 6)
|
||||
#define TDCR_BURSTSZ_128B (0x5 << 6)
|
||||
#define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */
|
||||
#define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */
|
||||
#define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */
|
||||
#define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */
|
||||
#define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */
|
||||
#define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */
|
||||
#define TDCR_DSTDESCCONT (0x1 << 1)
|
||||
#define TDCR_SRCDESTCONT (0x1 << 0)
|
||||
|
||||
/* Two-Channel DMA Int Mask Register */
|
||||
#define TDIMR_COMP (0x1 << 0)
|
||||
|
||||
/* Two-Channel DMA Int Status Register */
|
||||
#define TDISR_COMP (0x1 << 0)
|
||||
|
||||
/*
|
||||
* Two-Channel DMA Descriptor Struct
|
||||
* NOTE: desc's buf must be aligned to 16 bytes.
|
||||
*/
|
||||
struct mmp_tdma_desc {
|
||||
u32 byte_cnt;
|
||||
u32 src_addr;
|
||||
u32 dst_addr;
|
||||
u32 nxt_desc;
|
||||
};
|
||||
|
||||
enum mmp_tdma_type {
|
||||
MMP_AUD_TDMA = 0,
|
||||
PXA910_SQU,
|
||||
};
|
||||
|
||||
#define TDMA_ALIGNMENT 3
|
||||
#define TDMA_MAX_XFER_BYTES SZ_64K
|
||||
|
||||
struct mmp_tdma_chan {
|
||||
struct device *dev;
|
||||
struct dma_chan chan;
|
||||
struct dma_async_tx_descriptor desc;
|
||||
struct tasklet_struct tasklet;
|
||||
|
||||
struct mmp_tdma_desc *desc_arr;
|
||||
phys_addr_t desc_arr_phys;
|
||||
int desc_num;
|
||||
enum dma_transfer_direction dir;
|
||||
dma_addr_t dev_addr;
|
||||
u32 burst_sz;
|
||||
enum dma_slave_buswidth buswidth;
|
||||
enum dma_status status;
|
||||
|
||||
int idx;
|
||||
enum mmp_tdma_type type;
|
||||
int irq;
|
||||
void __iomem *reg_base;
|
||||
|
||||
size_t buf_len;
|
||||
size_t period_len;
|
||||
size_t pos;
|
||||
|
||||
struct gen_pool *pool;
|
||||
};
|
||||
|
||||
#define TDMA_CHANNEL_NUM 2
|
||||
struct mmp_tdma_device {
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
struct dma_device device;
|
||||
struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM];
|
||||
};
|
||||
|
||||
#define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
|
||||
|
||||
static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys)
|
||||
{
|
||||
writel(phys, tdmac->reg_base + TDNDPR);
|
||||
writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND,
|
||||
tdmac->reg_base + TDCR);
|
||||
}
|
||||
|
||||
static void mmp_tdma_enable_irq(struct mmp_tdma_chan *tdmac, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
|
||||
else
|
||||
writel(0, tdmac->reg_base + TDIMR);
|
||||
}
|
||||
|
||||
static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac)
|
||||
{
|
||||
/* enable dma chan */
|
||||
writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
|
||||
tdmac->reg_base + TDCR);
|
||||
tdmac->status = DMA_IN_PROGRESS;
|
||||
}
|
||||
|
||||
static void mmp_tdma_disable_chan(struct mmp_tdma_chan *tdmac)
|
||||
{
|
||||
writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
|
||||
tdmac->reg_base + TDCR);
|
||||
|
||||
tdmac->status = DMA_COMPLETE;
|
||||
}
|
||||
|
||||
static void mmp_tdma_resume_chan(struct mmp_tdma_chan *tdmac)
|
||||
{
|
||||
writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
|
||||
tdmac->reg_base + TDCR);
|
||||
tdmac->status = DMA_IN_PROGRESS;
|
||||
}
|
||||
|
||||
static void mmp_tdma_pause_chan(struct mmp_tdma_chan *tdmac)
|
||||
{
|
||||
writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
|
||||
tdmac->reg_base + TDCR);
|
||||
tdmac->status = DMA_PAUSED;
|
||||
}
|
||||
|
||||
static int mmp_tdma_config_chan(struct mmp_tdma_chan *tdmac)
|
||||
{
|
||||
unsigned int tdcr = 0;
|
||||
|
||||
mmp_tdma_disable_chan(tdmac);
|
||||
|
||||
if (tdmac->dir == DMA_MEM_TO_DEV)
|
||||
tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC;
|
||||
else if (tdmac->dir == DMA_DEV_TO_MEM)
|
||||
tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC;
|
||||
|
||||
if (tdmac->type == MMP_AUD_TDMA) {
|
||||
tdcr |= TDCR_PACKMOD;
|
||||
|
||||
switch (tdmac->burst_sz) {
|
||||
case 4:
|
||||
tdcr |= TDCR_BURSTSZ_4B;
|
||||
break;
|
||||
case 8:
|
||||
tdcr |= TDCR_BURSTSZ_8B;
|
||||
break;
|
||||
case 16:
|
||||
tdcr |= TDCR_BURSTSZ_16B;
|
||||
break;
|
||||
case 32:
|
||||
tdcr |= TDCR_BURSTSZ_32B;
|
||||
break;
|
||||
case 64:
|
||||
tdcr |= TDCR_BURSTSZ_64B;
|
||||
break;
|
||||
case 128:
|
||||
tdcr |= TDCR_BURSTSZ_128B;
|
||||
break;
|
||||
default:
|
||||
dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (tdmac->buswidth) {
|
||||
case DMA_SLAVE_BUSWIDTH_1_BYTE:
|
||||
tdcr |= TDCR_SSZ_8_BITS;
|
||||
break;
|
||||
case DMA_SLAVE_BUSWIDTH_2_BYTES:
|
||||
tdcr |= TDCR_SSZ_16_BITS;
|
||||
break;
|
||||
case DMA_SLAVE_BUSWIDTH_4_BYTES:
|
||||
tdcr |= TDCR_SSZ_32_BITS;
|
||||
break;
|
||||
default:
|
||||
dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
} else if (tdmac->type == PXA910_SQU) {
|
||||
tdcr |= TDCR_SSPMOD;
|
||||
|
||||
switch (tdmac->burst_sz) {
|
||||
case 1:
|
||||
tdcr |= TDCR_BURSTSZ_SQU_1B;
|
||||
break;
|
||||
case 2:
|
||||
tdcr |= TDCR_BURSTSZ_SQU_2B;
|
||||
break;
|
||||
case 4:
|
||||
tdcr |= TDCR_BURSTSZ_SQU_4B;
|
||||
break;
|
||||
case 8:
|
||||
tdcr |= TDCR_BURSTSZ_SQU_8B;
|
||||
break;
|
||||
case 16:
|
||||
tdcr |= TDCR_BURSTSZ_SQU_16B;
|
||||
break;
|
||||
case 32:
|
||||
tdcr |= TDCR_BURSTSZ_SQU_32B;
|
||||
break;
|
||||
default:
|
||||
dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
writel(tdcr, tdmac->reg_base + TDCR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac)
|
||||
{
|
||||
u32 reg = readl(tdmac->reg_base + TDISR);
|
||||
|
||||
if (reg & TDISR_COMP) {
|
||||
/* clear irq */
|
||||
reg &= ~TDISR_COMP;
|
||||
writel(reg, tdmac->reg_base + TDISR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct mmp_tdma_chan *tdmac = dev_id;
|
||||
|
||||
if (mmp_tdma_clear_chan_irq(tdmac) == 0) {
|
||||
tdmac->pos = (tdmac->pos + tdmac->period_len) % tdmac->buf_len;
|
||||
tasklet_schedule(&tdmac->tasklet);
|
||||
return IRQ_HANDLED;
|
||||
} else
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct mmp_tdma_device *tdev = dev_id;
|
||||
int i, ret;
|
||||
int irq_num = 0;
|
||||
|
||||
for (i = 0; i < TDMA_CHANNEL_NUM; i++) {
|
||||
struct mmp_tdma_chan *tdmac = tdev->tdmac[i];
|
||||
|
||||
ret = mmp_tdma_chan_handler(irq, tdmac);
|
||||
if (ret == IRQ_HANDLED)
|
||||
irq_num++;
|
||||
}
|
||||
|
||||
if (irq_num)
|
||||
return IRQ_HANDLED;
|
||||
else
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
static void dma_do_tasklet(unsigned long data)
|
||||
{
|
||||
struct mmp_tdma_chan *tdmac = (struct mmp_tdma_chan *)data;
|
||||
|
||||
if (tdmac->desc.callback)
|
||||
tdmac->desc.callback(tdmac->desc.callback_param);
|
||||
|
||||
}
|
||||
|
||||
static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac)
|
||||
{
|
||||
struct gen_pool *gpool;
|
||||
int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
|
||||
|
||||
gpool = tdmac->pool;
|
||||
if (tdmac->desc_arr)
|
||||
gen_pool_free(gpool, (unsigned long)tdmac->desc_arr,
|
||||
size);
|
||||
tdmac->desc_arr = NULL;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx)
|
||||
{
|
||||
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan);
|
||||
|
||||
mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
|
||||
int ret;
|
||||
|
||||
dma_async_tx_descriptor_init(&tdmac->desc, chan);
|
||||
tdmac->desc.tx_submit = mmp_tdma_tx_submit;
|
||||
|
||||
if (tdmac->irq) {
|
||||
ret = devm_request_irq(tdmac->dev, tdmac->irq,
|
||||
mmp_tdma_chan_handler, 0, "tdma", tdmac);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void mmp_tdma_free_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
|
||||
|
||||
if (tdmac->irq)
|
||||
devm_free_irq(tdmac->dev, tdmac->irq, tdmac);
|
||||
mmp_tdma_free_descriptor(tdmac);
|
||||
return;
|
||||
}
|
||||
|
||||
struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac)
|
||||
{
|
||||
struct gen_pool *gpool;
|
||||
int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
|
||||
|
||||
gpool = tdmac->pool;
|
||||
if (!gpool)
|
||||
return NULL;
|
||||
|
||||
tdmac->desc_arr = gen_pool_dma_alloc(gpool, size, &tdmac->desc_arr_phys);
|
||||
|
||||
return tdmac->desc_arr;
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
|
||||
struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
|
||||
size_t period_len, enum dma_transfer_direction direction,
|
||||
unsigned long flags, void *context)
|
||||
{
|
||||
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
|
||||
struct mmp_tdma_desc *desc;
|
||||
int num_periods = buf_len / period_len;
|
||||
int i = 0, buf = 0;
|
||||
|
||||
if (tdmac->status != DMA_COMPLETE)
|
||||
return NULL;
|
||||
|
||||
if (period_len > TDMA_MAX_XFER_BYTES) {
|
||||
dev_err(tdmac->dev,
|
||||
"maximum period size exceeded: %d > %d\n",
|
||||
period_len, TDMA_MAX_XFER_BYTES);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
tdmac->status = DMA_IN_PROGRESS;
|
||||
tdmac->desc_num = num_periods;
|
||||
desc = mmp_tdma_alloc_descriptor(tdmac);
|
||||
if (!desc)
|
||||
goto err_out;
|
||||
|
||||
while (buf < buf_len) {
|
||||
desc = &tdmac->desc_arr[i];
|
||||
|
||||
if (i + 1 == num_periods)
|
||||
desc->nxt_desc = tdmac->desc_arr_phys;
|
||||
else
|
||||
desc->nxt_desc = tdmac->desc_arr_phys +
|
||||
sizeof(*desc) * (i + 1);
|
||||
|
||||
if (direction == DMA_MEM_TO_DEV) {
|
||||
desc->src_addr = dma_addr;
|
||||
desc->dst_addr = tdmac->dev_addr;
|
||||
} else {
|
||||
desc->src_addr = tdmac->dev_addr;
|
||||
desc->dst_addr = dma_addr;
|
||||
}
|
||||
desc->byte_cnt = period_len;
|
||||
dma_addr += period_len;
|
||||
buf += period_len;
|
||||
i++;
|
||||
}
|
||||
|
||||
/* enable interrupt */
|
||||
if (flags & DMA_PREP_INTERRUPT)
|
||||
mmp_tdma_enable_irq(tdmac, true);
|
||||
|
||||
tdmac->buf_len = buf_len;
|
||||
tdmac->period_len = period_len;
|
||||
tdmac->pos = 0;
|
||||
|
||||
return &tdmac->desc;
|
||||
|
||||
err_out:
|
||||
tdmac->status = DMA_ERROR;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int mmp_tdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
|
||||
struct dma_slave_config *dmaengine_cfg = (void *)arg;
|
||||
int ret = 0;
|
||||
|
||||
switch (cmd) {
|
||||
case DMA_TERMINATE_ALL:
|
||||
mmp_tdma_disable_chan(tdmac);
|
||||
/* disable interrupt */
|
||||
mmp_tdma_enable_irq(tdmac, false);
|
||||
break;
|
||||
case DMA_PAUSE:
|
||||
mmp_tdma_pause_chan(tdmac);
|
||||
break;
|
||||
case DMA_RESUME:
|
||||
mmp_tdma_resume_chan(tdmac);
|
||||
break;
|
||||
case DMA_SLAVE_CONFIG:
|
||||
if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
|
||||
tdmac->dev_addr = dmaengine_cfg->src_addr;
|
||||
tdmac->burst_sz = dmaengine_cfg->src_maxburst;
|
||||
tdmac->buswidth = dmaengine_cfg->src_addr_width;
|
||||
} else {
|
||||
tdmac->dev_addr = dmaengine_cfg->dst_addr;
|
||||
tdmac->burst_sz = dmaengine_cfg->dst_maxburst;
|
||||
tdmac->buswidth = dmaengine_cfg->dst_addr_width;
|
||||
}
|
||||
tdmac->dir = dmaengine_cfg->direction;
|
||||
return mmp_tdma_config_chan(tdmac);
|
||||
default:
|
||||
ret = -ENOSYS;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan,
|
||||
dma_cookie_t cookie, struct dma_tx_state *txstate)
|
||||
{
|
||||
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
|
||||
|
||||
dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
|
||||
tdmac->buf_len - tdmac->pos);
|
||||
|
||||
return tdmac->status;
|
||||
}
|
||||
|
||||
static void mmp_tdma_issue_pending(struct dma_chan *chan)
|
||||
{
|
||||
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
|
||||
|
||||
mmp_tdma_enable_chan(tdmac);
|
||||
}
|
||||
|
||||
static int mmp_tdma_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mmp_tdma_device *tdev = platform_get_drvdata(pdev);
|
||||
|
||||
dma_async_device_unregister(&tdev->device);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
|
||||
int idx, int irq,
|
||||
int type, struct gen_pool *pool)
|
||||
{
|
||||
struct mmp_tdma_chan *tdmac;
|
||||
|
||||
if (idx >= TDMA_CHANNEL_NUM) {
|
||||
dev_err(tdev->dev, "too many channels for device!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* alloc channel */
|
||||
tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL);
|
||||
if (!tdmac) {
|
||||
dev_err(tdev->dev, "no free memory for DMA channels!\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
if (irq)
|
||||
tdmac->irq = irq;
|
||||
tdmac->dev = tdev->dev;
|
||||
tdmac->chan.device = &tdev->device;
|
||||
tdmac->idx = idx;
|
||||
tdmac->type = type;
|
||||
tdmac->reg_base = tdev->base + idx * 4;
|
||||
tdmac->pool = pool;
|
||||
tdmac->status = DMA_COMPLETE;
|
||||
tdev->tdmac[tdmac->idx] = tdmac;
|
||||
tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac);
|
||||
|
||||
/* add the channel to tdma_chan list */
|
||||
list_add_tail(&tdmac->chan.device_node,
|
||||
&tdev->device.channels);
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct mmp_tdma_filter_param {
|
||||
struct device_node *of_node;
|
||||
unsigned int chan_id;
|
||||
};
|
||||
|
||||
static bool mmp_tdma_filter_fn(struct dma_chan *chan, void *fn_param)
|
||||
{
|
||||
struct mmp_tdma_filter_param *param = fn_param;
|
||||
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
|
||||
struct dma_device *pdma_device = tdmac->chan.device;
|
||||
|
||||
if (pdma_device->dev->of_node != param->of_node)
|
||||
return false;
|
||||
|
||||
if (chan->chan_id != param->chan_id)
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
struct dma_chan *mmp_tdma_xlate(struct of_phandle_args *dma_spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
struct mmp_tdma_device *tdev = ofdma->of_dma_data;
|
||||
dma_cap_mask_t mask = tdev->device.cap_mask;
|
||||
struct mmp_tdma_filter_param param;
|
||||
|
||||
if (dma_spec->args_count != 1)
|
||||
return NULL;
|
||||
|
||||
param.of_node = ofdma->of_node;
|
||||
param.chan_id = dma_spec->args[0];
|
||||
|
||||
if (param.chan_id >= TDMA_CHANNEL_NUM)
|
||||
return NULL;
|
||||
|
||||
return dma_request_channel(mask, mmp_tdma_filter_fn, ¶m);
|
||||
}
|
||||
|
||||
static struct of_device_id mmp_tdma_dt_ids[] = {
|
||||
{ .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA},
|
||||
{ .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU},
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids);
|
||||
|
||||
static int mmp_tdma_probe(struct platform_device *pdev)
|
||||
{
|
||||
enum mmp_tdma_type type;
|
||||
const struct of_device_id *of_id;
|
||||
struct mmp_tdma_device *tdev;
|
||||
struct resource *iores;
|
||||
int i, ret;
|
||||
int irq = 0, irq_num = 0;
|
||||
int chan_num = TDMA_CHANNEL_NUM;
|
||||
struct gen_pool *pool;
|
||||
|
||||
of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev);
|
||||
if (of_id)
|
||||
type = (enum mmp_tdma_type) of_id->data;
|
||||
else
|
||||
type = platform_get_device_id(pdev)->driver_data;
|
||||
|
||||
/* always have couple channels */
|
||||
tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
|
||||
if (!tdev)
|
||||
return -ENOMEM;
|
||||
|
||||
tdev->dev = &pdev->dev;
|
||||
|
||||
for (i = 0; i < chan_num; i++) {
|
||||
if (platform_get_irq(pdev, i) > 0)
|
||||
irq_num++;
|
||||
}
|
||||
|
||||
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
tdev->base = devm_ioremap_resource(&pdev->dev, iores);
|
||||
if (IS_ERR(tdev->base))
|
||||
return PTR_ERR(tdev->base);
|
||||
|
||||
INIT_LIST_HEAD(&tdev->device.channels);
|
||||
|
||||
if (pdev->dev.of_node)
|
||||
pool = of_get_named_gen_pool(pdev->dev.of_node, "asram", 0);
|
||||
else
|
||||
pool = sram_get_gpool("asram");
|
||||
if (!pool) {
|
||||
dev_err(&pdev->dev, "asram pool not available\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (irq_num != chan_num) {
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
ret = devm_request_irq(&pdev->dev, irq,
|
||||
mmp_tdma_int_handler, 0, "tdma", tdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* initialize channel parameters */
|
||||
for (i = 0; i < chan_num; i++) {
|
||||
irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i);
|
||||
ret = mmp_tdma_chan_init(tdev, i, irq, type, pool);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
|
||||
dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
|
||||
tdev->device.dev = &pdev->dev;
|
||||
tdev->device.device_alloc_chan_resources =
|
||||
mmp_tdma_alloc_chan_resources;
|
||||
tdev->device.device_free_chan_resources =
|
||||
mmp_tdma_free_chan_resources;
|
||||
tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic;
|
||||
tdev->device.device_tx_status = mmp_tdma_tx_status;
|
||||
tdev->device.device_issue_pending = mmp_tdma_issue_pending;
|
||||
tdev->device.device_control = mmp_tdma_control;
|
||||
tdev->device.copy_align = TDMA_ALIGNMENT;
|
||||
|
||||
dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
|
||||
platform_set_drvdata(pdev, tdev);
|
||||
|
||||
ret = dma_async_device_register(&tdev->device);
|
||||
if (ret) {
|
||||
dev_err(tdev->device.dev, "unable to register\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (pdev->dev.of_node) {
|
||||
ret = of_dma_controller_register(pdev->dev.of_node,
|
||||
mmp_tdma_xlate, tdev);
|
||||
if (ret) {
|
||||
dev_err(tdev->device.dev,
|
||||
"failed to register controller\n");
|
||||
dma_async_device_unregister(&tdev->device);
|
||||
}
|
||||
}
|
||||
|
||||
dev_info(tdev->device.dev, "initialized\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct platform_device_id mmp_tdma_id_table[] = {
|
||||
{ "mmp-adma", MMP_AUD_TDMA },
|
||||
{ "pxa910-squ", PXA910_SQU },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct platform_driver mmp_tdma_driver = {
|
||||
.driver = {
|
||||
.name = "mmp-tdma",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = mmp_tdma_dt_ids,
|
||||
},
|
||||
.id_table = mmp_tdma_id_table,
|
||||
.probe = mmp_tdma_probe,
|
||||
.remove = mmp_tdma_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(mmp_tdma_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("MMP Two-Channel DMA Driver");
|
||||
MODULE_ALIAS("platform:mmp-tdma");
|
||||
MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
|
||||
MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>");
|
||||
699
drivers/dma/moxart-dma.c
Normal file
699
drivers/dma/moxart-dma.c
Normal file
|
|
@ -0,0 +1,699 @@
|
|||
/*
|
||||
* MOXA ART SoCs DMA Engine support.
|
||||
*
|
||||
* Copyright (C) 2013 Jonas Jensen
|
||||
*
|
||||
* Jonas Jensen <jonas.jensen@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_dma.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#include "dmaengine.h"
|
||||
#include "virt-dma.h"
|
||||
|
||||
#define APB_DMA_MAX_CHANNEL 4
|
||||
|
||||
#define REG_OFF_ADDRESS_SOURCE 0
|
||||
#define REG_OFF_ADDRESS_DEST 4
|
||||
#define REG_OFF_CYCLES 8
|
||||
#define REG_OFF_CTRL 12
|
||||
#define REG_OFF_CHAN_SIZE 16
|
||||
|
||||
#define APB_DMA_ENABLE BIT(0)
|
||||
#define APB_DMA_FIN_INT_STS BIT(1)
|
||||
#define APB_DMA_FIN_INT_EN BIT(2)
|
||||
#define APB_DMA_BURST_MODE BIT(3)
|
||||
#define APB_DMA_ERR_INT_STS BIT(4)
|
||||
#define APB_DMA_ERR_INT_EN BIT(5)
|
||||
|
||||
/*
|
||||
* Unset: APB
|
||||
* Set: AHB
|
||||
*/
|
||||
#define APB_DMA_SOURCE_SELECT 0x40
|
||||
#define APB_DMA_DEST_SELECT 0x80
|
||||
|
||||
#define APB_DMA_SOURCE 0x100
|
||||
#define APB_DMA_DEST 0x1000
|
||||
|
||||
#define APB_DMA_SOURCE_MASK 0x700
|
||||
#define APB_DMA_DEST_MASK 0x7000
|
||||
|
||||
/*
|
||||
* 000: No increment
|
||||
* 001: +1 (Burst=0), +4 (Burst=1)
|
||||
* 010: +2 (Burst=0), +8 (Burst=1)
|
||||
* 011: +4 (Burst=0), +16 (Burst=1)
|
||||
* 101: -1 (Burst=0), -4 (Burst=1)
|
||||
* 110: -2 (Burst=0), -8 (Burst=1)
|
||||
* 111: -4 (Burst=0), -16 (Burst=1)
|
||||
*/
|
||||
#define APB_DMA_SOURCE_INC_0 0
|
||||
#define APB_DMA_SOURCE_INC_1_4 0x100
|
||||
#define APB_DMA_SOURCE_INC_2_8 0x200
|
||||
#define APB_DMA_SOURCE_INC_4_16 0x300
|
||||
#define APB_DMA_SOURCE_DEC_1_4 0x500
|
||||
#define APB_DMA_SOURCE_DEC_2_8 0x600
|
||||
#define APB_DMA_SOURCE_DEC_4_16 0x700
|
||||
#define APB_DMA_DEST_INC_0 0
|
||||
#define APB_DMA_DEST_INC_1_4 0x1000
|
||||
#define APB_DMA_DEST_INC_2_8 0x2000
|
||||
#define APB_DMA_DEST_INC_4_16 0x3000
|
||||
#define APB_DMA_DEST_DEC_1_4 0x5000
|
||||
#define APB_DMA_DEST_DEC_2_8 0x6000
|
||||
#define APB_DMA_DEST_DEC_4_16 0x7000
|
||||
|
||||
/*
|
||||
* Request signal select source/destination address for DMA hardware handshake.
|
||||
*
|
||||
* The request line number is a property of the DMA controller itself,
|
||||
* e.g. MMC must always request channels where dma_slave_config->slave_id is 5.
|
||||
*
|
||||
* 0: No request / Grant signal
|
||||
* 1-15: Request / Grant signal
|
||||
*/
|
||||
#define APB_DMA_SOURCE_REQ_NO 0x1000000
|
||||
#define APB_DMA_SOURCE_REQ_NO_MASK 0xf000000
|
||||
#define APB_DMA_DEST_REQ_NO 0x10000
|
||||
#define APB_DMA_DEST_REQ_NO_MASK 0xf0000
|
||||
|
||||
#define APB_DMA_DATA_WIDTH 0x100000
|
||||
#define APB_DMA_DATA_WIDTH_MASK 0x300000
|
||||
/*
|
||||
* Data width of transfer:
|
||||
*
|
||||
* 00: Word
|
||||
* 01: Half
|
||||
* 10: Byte
|
||||
*/
|
||||
#define APB_DMA_DATA_WIDTH_4 0
|
||||
#define APB_DMA_DATA_WIDTH_2 0x100000
|
||||
#define APB_DMA_DATA_WIDTH_1 0x200000
|
||||
|
||||
#define APB_DMA_CYCLES_MASK 0x00ffffff
|
||||
|
||||
#define MOXART_DMA_DATA_TYPE_S8 0x00
|
||||
#define MOXART_DMA_DATA_TYPE_S16 0x01
|
||||
#define MOXART_DMA_DATA_TYPE_S32 0x02
|
||||
|
||||
struct moxart_sg {
|
||||
dma_addr_t addr;
|
||||
uint32_t len;
|
||||
};
|
||||
|
||||
struct moxart_desc {
|
||||
enum dma_transfer_direction dma_dir;
|
||||
dma_addr_t dev_addr;
|
||||
unsigned int sglen;
|
||||
unsigned int dma_cycles;
|
||||
struct virt_dma_desc vd;
|
||||
uint8_t es;
|
||||
struct moxart_sg sg[0];
|
||||
};
|
||||
|
||||
struct moxart_chan {
|
||||
struct virt_dma_chan vc;
|
||||
|
||||
void __iomem *base;
|
||||
struct moxart_desc *desc;
|
||||
|
||||
struct dma_slave_config cfg;
|
||||
|
||||
bool allocated;
|
||||
bool error;
|
||||
int ch_num;
|
||||
unsigned int line_reqno;
|
||||
unsigned int sgidx;
|
||||
};
|
||||
|
||||
struct moxart_dmadev {
|
||||
struct dma_device dma_slave;
|
||||
struct moxart_chan slave_chans[APB_DMA_MAX_CHANNEL];
|
||||
};
|
||||
|
||||
struct moxart_filter_data {
|
||||
struct moxart_dmadev *mdc;
|
||||
struct of_phandle_args *dma_spec;
|
||||
};
|
||||
|
||||
static const unsigned int es_bytes[] = {
|
||||
[MOXART_DMA_DATA_TYPE_S8] = 1,
|
||||
[MOXART_DMA_DATA_TYPE_S16] = 2,
|
||||
[MOXART_DMA_DATA_TYPE_S32] = 4,
|
||||
};
|
||||
|
||||
static struct device *chan2dev(struct dma_chan *chan)
|
||||
{
|
||||
return &chan->dev->device;
|
||||
}
|
||||
|
||||
static inline struct moxart_chan *to_moxart_dma_chan(struct dma_chan *c)
|
||||
{
|
||||
return container_of(c, struct moxart_chan, vc.chan);
|
||||
}
|
||||
|
||||
static inline struct moxart_desc *to_moxart_dma_desc(
|
||||
struct dma_async_tx_descriptor *t)
|
||||
{
|
||||
return container_of(t, struct moxart_desc, vd.tx);
|
||||
}
|
||||
|
||||
static void moxart_dma_desc_free(struct virt_dma_desc *vd)
|
||||
{
|
||||
kfree(container_of(vd, struct moxart_desc, vd));
|
||||
}
|
||||
|
||||
static int moxart_terminate_all(struct dma_chan *chan)
|
||||
{
|
||||
struct moxart_chan *ch = to_moxart_dma_chan(chan);
|
||||
unsigned long flags;
|
||||
LIST_HEAD(head);
|
||||
u32 ctrl;
|
||||
|
||||
dev_dbg(chan2dev(chan), "%s: ch=%p\n", __func__, ch);
|
||||
|
||||
spin_lock_irqsave(&ch->vc.lock, flags);
|
||||
|
||||
if (ch->desc)
|
||||
ch->desc = NULL;
|
||||
|
||||
ctrl = readl(ch->base + REG_OFF_CTRL);
|
||||
ctrl &= ~(APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN);
|
||||
writel(ctrl, ch->base + REG_OFF_CTRL);
|
||||
|
||||
vchan_get_all_descriptors(&ch->vc, &head);
|
||||
spin_unlock_irqrestore(&ch->vc.lock, flags);
|
||||
vchan_dma_desc_free_list(&ch->vc, &head);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int moxart_slave_config(struct dma_chan *chan,
|
||||
struct dma_slave_config *cfg)
|
||||
{
|
||||
struct moxart_chan *ch = to_moxart_dma_chan(chan);
|
||||
u32 ctrl;
|
||||
|
||||
ch->cfg = *cfg;
|
||||
|
||||
ctrl = readl(ch->base + REG_OFF_CTRL);
|
||||
ctrl |= APB_DMA_BURST_MODE;
|
||||
ctrl &= ~(APB_DMA_DEST_MASK | APB_DMA_SOURCE_MASK);
|
||||
ctrl &= ~(APB_DMA_DEST_REQ_NO_MASK | APB_DMA_SOURCE_REQ_NO_MASK);
|
||||
|
||||
switch (ch->cfg.src_addr_width) {
|
||||
case DMA_SLAVE_BUSWIDTH_1_BYTE:
|
||||
ctrl |= APB_DMA_DATA_WIDTH_1;
|
||||
if (ch->cfg.direction != DMA_MEM_TO_DEV)
|
||||
ctrl |= APB_DMA_DEST_INC_1_4;
|
||||
else
|
||||
ctrl |= APB_DMA_SOURCE_INC_1_4;
|
||||
break;
|
||||
case DMA_SLAVE_BUSWIDTH_2_BYTES:
|
||||
ctrl |= APB_DMA_DATA_WIDTH_2;
|
||||
if (ch->cfg.direction != DMA_MEM_TO_DEV)
|
||||
ctrl |= APB_DMA_DEST_INC_2_8;
|
||||
else
|
||||
ctrl |= APB_DMA_SOURCE_INC_2_8;
|
||||
break;
|
||||
case DMA_SLAVE_BUSWIDTH_4_BYTES:
|
||||
ctrl &= ~APB_DMA_DATA_WIDTH;
|
||||
if (ch->cfg.direction != DMA_MEM_TO_DEV)
|
||||
ctrl |= APB_DMA_DEST_INC_4_16;
|
||||
else
|
||||
ctrl |= APB_DMA_SOURCE_INC_4_16;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (ch->cfg.direction == DMA_MEM_TO_DEV) {
|
||||
ctrl &= ~APB_DMA_DEST_SELECT;
|
||||
ctrl |= APB_DMA_SOURCE_SELECT;
|
||||
ctrl |= (ch->line_reqno << 16 &
|
||||
APB_DMA_DEST_REQ_NO_MASK);
|
||||
} else {
|
||||
ctrl |= APB_DMA_DEST_SELECT;
|
||||
ctrl &= ~APB_DMA_SOURCE_SELECT;
|
||||
ctrl |= (ch->line_reqno << 24 &
|
||||
APB_DMA_SOURCE_REQ_NO_MASK);
|
||||
}
|
||||
|
||||
writel(ctrl, ch->base + REG_OFF_CTRL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int moxart_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
switch (cmd) {
|
||||
case DMA_PAUSE:
|
||||
case DMA_RESUME:
|
||||
return -EINVAL;
|
||||
case DMA_TERMINATE_ALL:
|
||||
moxart_terminate_all(chan);
|
||||
break;
|
||||
case DMA_SLAVE_CONFIG:
|
||||
ret = moxart_slave_config(chan, (struct dma_slave_config *)arg);
|
||||
break;
|
||||
default:
|
||||
ret = -ENOSYS;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *moxart_prep_slave_sg(
|
||||
struct dma_chan *chan, struct scatterlist *sgl,
|
||||
unsigned int sg_len, enum dma_transfer_direction dir,
|
||||
unsigned long tx_flags, void *context)
|
||||
{
|
||||
struct moxart_chan *ch = to_moxart_dma_chan(chan);
|
||||
struct moxart_desc *d;
|
||||
enum dma_slave_buswidth dev_width;
|
||||
dma_addr_t dev_addr;
|
||||
struct scatterlist *sgent;
|
||||
unsigned int es;
|
||||
unsigned int i;
|
||||
|
||||
if (!is_slave_direction(dir)) {
|
||||
dev_err(chan2dev(chan), "%s: invalid DMA direction\n",
|
||||
__func__);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (dir == DMA_DEV_TO_MEM) {
|
||||
dev_addr = ch->cfg.src_addr;
|
||||
dev_width = ch->cfg.src_addr_width;
|
||||
} else {
|
||||
dev_addr = ch->cfg.dst_addr;
|
||||
dev_width = ch->cfg.dst_addr_width;
|
||||
}
|
||||
|
||||
switch (dev_width) {
|
||||
case DMA_SLAVE_BUSWIDTH_1_BYTE:
|
||||
es = MOXART_DMA_DATA_TYPE_S8;
|
||||
break;
|
||||
case DMA_SLAVE_BUSWIDTH_2_BYTES:
|
||||
es = MOXART_DMA_DATA_TYPE_S16;
|
||||
break;
|
||||
case DMA_SLAVE_BUSWIDTH_4_BYTES:
|
||||
es = MOXART_DMA_DATA_TYPE_S32;
|
||||
break;
|
||||
default:
|
||||
dev_err(chan2dev(chan), "%s: unsupported data width (%u)\n",
|
||||
__func__, dev_width);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
d = kzalloc(sizeof(*d) + sg_len * sizeof(d->sg[0]), GFP_ATOMIC);
|
||||
if (!d)
|
||||
return NULL;
|
||||
|
||||
d->dma_dir = dir;
|
||||
d->dev_addr = dev_addr;
|
||||
d->es = es;
|
||||
|
||||
for_each_sg(sgl, sgent, sg_len, i) {
|
||||
d->sg[i].addr = sg_dma_address(sgent);
|
||||
d->sg[i].len = sg_dma_len(sgent);
|
||||
}
|
||||
|
||||
d->sglen = sg_len;
|
||||
|
||||
ch->error = 0;
|
||||
|
||||
return vchan_tx_prep(&ch->vc, &d->vd, tx_flags);
|
||||
}
|
||||
|
||||
static struct dma_chan *moxart_of_xlate(struct of_phandle_args *dma_spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
struct moxart_dmadev *mdc = ofdma->of_dma_data;
|
||||
struct dma_chan *chan;
|
||||
struct moxart_chan *ch;
|
||||
|
||||
chan = dma_get_any_slave_channel(&mdc->dma_slave);
|
||||
if (!chan)
|
||||
return NULL;
|
||||
|
||||
ch = to_moxart_dma_chan(chan);
|
||||
ch->line_reqno = dma_spec->args[0];
|
||||
|
||||
return chan;
|
||||
}
|
||||
|
||||
static int moxart_alloc_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct moxart_chan *ch = to_moxart_dma_chan(chan);
|
||||
|
||||
dev_dbg(chan2dev(chan), "%s: allocating channel #%u\n",
|
||||
__func__, ch->ch_num);
|
||||
ch->allocated = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void moxart_free_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct moxart_chan *ch = to_moxart_dma_chan(chan);
|
||||
|
||||
vchan_free_chan_resources(&ch->vc);
|
||||
|
||||
dev_dbg(chan2dev(chan), "%s: freeing channel #%u\n",
|
||||
__func__, ch->ch_num);
|
||||
ch->allocated = 0;
|
||||
}
|
||||
|
||||
static void moxart_dma_set_params(struct moxart_chan *ch, dma_addr_t src_addr,
|
||||
dma_addr_t dst_addr)
|
||||
{
|
||||
writel(src_addr, ch->base + REG_OFF_ADDRESS_SOURCE);
|
||||
writel(dst_addr, ch->base + REG_OFF_ADDRESS_DEST);
|
||||
}
|
||||
|
||||
static void moxart_set_transfer_params(struct moxart_chan *ch, unsigned int len)
|
||||
{
|
||||
struct moxart_desc *d = ch->desc;
|
||||
unsigned int sglen_div = es_bytes[d->es];
|
||||
|
||||
d->dma_cycles = len >> sglen_div;
|
||||
|
||||
/*
|
||||
* There are 4 cycles on 64 bytes copied, i.e. one cycle copies 16
|
||||
* bytes ( when width is APB_DMAB_DATA_WIDTH_4 ).
|
||||
*/
|
||||
writel(d->dma_cycles, ch->base + REG_OFF_CYCLES);
|
||||
|
||||
dev_dbg(chan2dev(&ch->vc.chan), "%s: set %u DMA cycles (len=%u)\n",
|
||||
__func__, d->dma_cycles, len);
|
||||
}
|
||||
|
||||
static void moxart_start_dma(struct moxart_chan *ch)
|
||||
{
|
||||
u32 ctrl;
|
||||
|
||||
ctrl = readl(ch->base + REG_OFF_CTRL);
|
||||
ctrl |= (APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN);
|
||||
writel(ctrl, ch->base + REG_OFF_CTRL);
|
||||
}
|
||||
|
||||
static void moxart_dma_start_sg(struct moxart_chan *ch, unsigned int idx)
|
||||
{
|
||||
struct moxart_desc *d = ch->desc;
|
||||
struct moxart_sg *sg = ch->desc->sg + idx;
|
||||
|
||||
if (ch->desc->dma_dir == DMA_MEM_TO_DEV)
|
||||
moxart_dma_set_params(ch, sg->addr, d->dev_addr);
|
||||
else if (ch->desc->dma_dir == DMA_DEV_TO_MEM)
|
||||
moxart_dma_set_params(ch, d->dev_addr, sg->addr);
|
||||
|
||||
moxart_set_transfer_params(ch, sg->len);
|
||||
|
||||
moxart_start_dma(ch);
|
||||
}
|
||||
|
||||
static void moxart_dma_start_desc(struct dma_chan *chan)
|
||||
{
|
||||
struct moxart_chan *ch = to_moxart_dma_chan(chan);
|
||||
struct virt_dma_desc *vd;
|
||||
|
||||
vd = vchan_next_desc(&ch->vc);
|
||||
|
||||
if (!vd) {
|
||||
ch->desc = NULL;
|
||||
return;
|
||||
}
|
||||
|
||||
list_del(&vd->node);
|
||||
|
||||
ch->desc = to_moxart_dma_desc(&vd->tx);
|
||||
ch->sgidx = 0;
|
||||
|
||||
moxart_dma_start_sg(ch, 0);
|
||||
}
|
||||
|
||||
static void moxart_issue_pending(struct dma_chan *chan)
|
||||
{
|
||||
struct moxart_chan *ch = to_moxart_dma_chan(chan);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&ch->vc.lock, flags);
|
||||
if (vchan_issue_pending(&ch->vc) && !ch->desc)
|
||||
moxart_dma_start_desc(chan);
|
||||
spin_unlock_irqrestore(&ch->vc.lock, flags);
|
||||
}
|
||||
|
||||
static size_t moxart_dma_desc_size(struct moxart_desc *d,
|
||||
unsigned int completed_sgs)
|
||||
{
|
||||
unsigned int i;
|
||||
size_t size;
|
||||
|
||||
for (size = i = completed_sgs; i < d->sglen; i++)
|
||||
size += d->sg[i].len;
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
static size_t moxart_dma_desc_size_in_flight(struct moxart_chan *ch)
|
||||
{
|
||||
size_t size;
|
||||
unsigned int completed_cycles, cycles;
|
||||
|
||||
size = moxart_dma_desc_size(ch->desc, ch->sgidx);
|
||||
cycles = readl(ch->base + REG_OFF_CYCLES);
|
||||
completed_cycles = (ch->desc->dma_cycles - cycles);
|
||||
size -= completed_cycles << es_bytes[ch->desc->es];
|
||||
|
||||
dev_dbg(chan2dev(&ch->vc.chan), "%s: size=%zu\n", __func__, size);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
static enum dma_status moxart_tx_status(struct dma_chan *chan,
|
||||
dma_cookie_t cookie,
|
||||
struct dma_tx_state *txstate)
|
||||
{
|
||||
struct moxart_chan *ch = to_moxart_dma_chan(chan);
|
||||
struct virt_dma_desc *vd;
|
||||
struct moxart_desc *d;
|
||||
enum dma_status ret;
|
||||
unsigned long flags;
|
||||
|
||||
/*
|
||||
* dma_cookie_status() assigns initial residue value.
|
||||
*/
|
||||
ret = dma_cookie_status(chan, cookie, txstate);
|
||||
|
||||
spin_lock_irqsave(&ch->vc.lock, flags);
|
||||
vd = vchan_find_desc(&ch->vc, cookie);
|
||||
if (vd) {
|
||||
d = to_moxart_dma_desc(&vd->tx);
|
||||
txstate->residue = moxart_dma_desc_size(d, 0);
|
||||
} else if (ch->desc && ch->desc->vd.tx.cookie == cookie) {
|
||||
txstate->residue = moxart_dma_desc_size_in_flight(ch);
|
||||
}
|
||||
spin_unlock_irqrestore(&ch->vc.lock, flags);
|
||||
|
||||
if (ch->error)
|
||||
return DMA_ERROR;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void moxart_dma_init(struct dma_device *dma, struct device *dev)
|
||||
{
|
||||
dma->device_prep_slave_sg = moxart_prep_slave_sg;
|
||||
dma->device_alloc_chan_resources = moxart_alloc_chan_resources;
|
||||
dma->device_free_chan_resources = moxart_free_chan_resources;
|
||||
dma->device_issue_pending = moxart_issue_pending;
|
||||
dma->device_tx_status = moxart_tx_status;
|
||||
dma->device_control = moxart_control;
|
||||
dma->dev = dev;
|
||||
|
||||
INIT_LIST_HEAD(&dma->channels);
|
||||
}
|
||||
|
||||
static irqreturn_t moxart_dma_interrupt(int irq, void *devid)
|
||||
{
|
||||
struct moxart_dmadev *mc = devid;
|
||||
struct moxart_chan *ch = &mc->slave_chans[0];
|
||||
unsigned int i;
|
||||
unsigned long flags;
|
||||
u32 ctrl;
|
||||
|
||||
dev_dbg(chan2dev(&ch->vc.chan), "%s\n", __func__);
|
||||
|
||||
for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) {
|
||||
if (!ch->allocated)
|
||||
continue;
|
||||
|
||||
ctrl = readl(ch->base + REG_OFF_CTRL);
|
||||
|
||||
dev_dbg(chan2dev(&ch->vc.chan), "%s: ch=%p ch->base=%p ctrl=%x\n",
|
||||
__func__, ch, ch->base, ctrl);
|
||||
|
||||
if (ctrl & APB_DMA_FIN_INT_STS) {
|
||||
ctrl &= ~APB_DMA_FIN_INT_STS;
|
||||
if (ch->desc) {
|
||||
spin_lock_irqsave(&ch->vc.lock, flags);
|
||||
if (++ch->sgidx < ch->desc->sglen) {
|
||||
moxart_dma_start_sg(ch, ch->sgidx);
|
||||
} else {
|
||||
vchan_cookie_complete(&ch->desc->vd);
|
||||
moxart_dma_start_desc(&ch->vc.chan);
|
||||
}
|
||||
spin_unlock_irqrestore(&ch->vc.lock, flags);
|
||||
}
|
||||
}
|
||||
|
||||
if (ctrl & APB_DMA_ERR_INT_STS) {
|
||||
ctrl &= ~APB_DMA_ERR_INT_STS;
|
||||
ch->error = 1;
|
||||
}
|
||||
|
||||
writel(ctrl, ch->base + REG_OFF_CTRL);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int moxart_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->of_node;
|
||||
struct resource *res;
|
||||
static void __iomem *dma_base_addr;
|
||||
int ret, i;
|
||||
unsigned int irq;
|
||||
struct moxart_chan *ch;
|
||||
struct moxart_dmadev *mdc;
|
||||
|
||||
mdc = devm_kzalloc(dev, sizeof(*mdc), GFP_KERNEL);
|
||||
if (!mdc) {
|
||||
dev_err(dev, "can't allocate DMA container\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
irq = irq_of_parse_and_map(node, 0);
|
||||
if (irq == NO_IRQ) {
|
||||
dev_err(dev, "no IRQ resource\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
dma_base_addr = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(dma_base_addr))
|
||||
return PTR_ERR(dma_base_addr);
|
||||
|
||||
dma_cap_zero(mdc->dma_slave.cap_mask);
|
||||
dma_cap_set(DMA_SLAVE, mdc->dma_slave.cap_mask);
|
||||
dma_cap_set(DMA_PRIVATE, mdc->dma_slave.cap_mask);
|
||||
|
||||
moxart_dma_init(&mdc->dma_slave, dev);
|
||||
|
||||
ch = &mdc->slave_chans[0];
|
||||
for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) {
|
||||
ch->ch_num = i;
|
||||
ch->base = dma_base_addr + i * REG_OFF_CHAN_SIZE;
|
||||
ch->allocated = 0;
|
||||
|
||||
ch->vc.desc_free = moxart_dma_desc_free;
|
||||
vchan_init(&ch->vc, &mdc->dma_slave);
|
||||
|
||||
dev_dbg(dev, "%s: chs[%d]: ch->ch_num=%u ch->base=%p\n",
|
||||
__func__, i, ch->ch_num, ch->base);
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, mdc);
|
||||
|
||||
ret = devm_request_irq(dev, irq, moxart_dma_interrupt, 0,
|
||||
"moxart-dma-engine", mdc);
|
||||
if (ret) {
|
||||
dev_err(dev, "devm_request_irq failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = dma_async_device_register(&mdc->dma_slave);
|
||||
if (ret) {
|
||||
dev_err(dev, "dma_async_device_register failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_dma_controller_register(node, moxart_of_xlate, mdc);
|
||||
if (ret) {
|
||||
dev_err(dev, "of_dma_controller_register failed\n");
|
||||
dma_async_device_unregister(&mdc->dma_slave);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_dbg(dev, "%s: IRQ=%u\n", __func__, irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int moxart_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct moxart_dmadev *m = platform_get_drvdata(pdev);
|
||||
|
||||
dma_async_device_unregister(&m->dma_slave);
|
||||
|
||||
if (pdev->dev.of_node)
|
||||
of_dma_controller_free(pdev->dev.of_node);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id moxart_dma_match[] = {
|
||||
{ .compatible = "moxa,moxart-dma" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver moxart_driver = {
|
||||
.probe = moxart_probe,
|
||||
.remove = moxart_remove,
|
||||
.driver = {
|
||||
.name = "moxart-dma-engine",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = moxart_dma_match,
|
||||
},
|
||||
};
|
||||
|
||||
static int moxart_init(void)
|
||||
{
|
||||
return platform_driver_register(&moxart_driver);
|
||||
}
|
||||
subsys_initcall(moxart_init);
|
||||
|
||||
static void __exit moxart_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&moxart_driver);
|
||||
}
|
||||
module_exit(moxart_exit);
|
||||
|
||||
MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
|
||||
MODULE_DESCRIPTION("MOXART DMA engine driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
1101
drivers/dma/mpc512x_dma.c
Normal file
1101
drivers/dma/mpc512x_dma.c
Normal file
File diff suppressed because it is too large
Load diff
1298
drivers/dma/mv_xor.c
Normal file
1298
drivers/dma/mv_xor.c
Normal file
File diff suppressed because it is too large
Load diff
193
drivers/dma/mv_xor.h
Normal file
193
drivers/dma/mv_xor.h
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* Copyright (C) 2007, 2008, Marvell International Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software Foundation,
|
||||
* Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#ifndef MV_XOR_H
|
||||
#define MV_XOR_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#define MV_XOR_POOL_SIZE PAGE_SIZE
|
||||
#define MV_XOR_SLOT_SIZE 64
|
||||
#define MV_XOR_THRESHOLD 1
|
||||
#define MV_XOR_MAX_CHANNELS 2
|
||||
|
||||
#define MV_XOR_MIN_BYTE_COUNT SZ_128
|
||||
#define MV_XOR_MAX_BYTE_COUNT (SZ_16M - 1)
|
||||
|
||||
/* Values for the XOR_CONFIG register */
|
||||
#define XOR_OPERATION_MODE_XOR 0
|
||||
#define XOR_OPERATION_MODE_MEMCPY 2
|
||||
#define XOR_DESCRIPTOR_SWAP BIT(14)
|
||||
|
||||
#define XOR_DESC_DMA_OWNED BIT(31)
|
||||
#define XOR_DESC_EOD_INT_EN BIT(31)
|
||||
|
||||
#define XOR_CURR_DESC(chan) (chan->mmr_high_base + 0x10 + (chan->idx * 4))
|
||||
#define XOR_NEXT_DESC(chan) (chan->mmr_high_base + 0x00 + (chan->idx * 4))
|
||||
#define XOR_BYTE_COUNT(chan) (chan->mmr_high_base + 0x20 + (chan->idx * 4))
|
||||
#define XOR_DEST_POINTER(chan) (chan->mmr_high_base + 0xB0 + (chan->idx * 4))
|
||||
#define XOR_BLOCK_SIZE(chan) (chan->mmr_high_base + 0xC0 + (chan->idx * 4))
|
||||
#define XOR_INIT_VALUE_LOW(chan) (chan->mmr_high_base + 0xE0)
|
||||
#define XOR_INIT_VALUE_HIGH(chan) (chan->mmr_high_base + 0xE4)
|
||||
|
||||
#define XOR_CONFIG(chan) (chan->mmr_base + 0x10 + (chan->idx * 4))
|
||||
#define XOR_ACTIVATION(chan) (chan->mmr_base + 0x20 + (chan->idx * 4))
|
||||
#define XOR_INTR_CAUSE(chan) (chan->mmr_base + 0x30)
|
||||
#define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40)
|
||||
#define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50)
|
||||
#define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60)
|
||||
|
||||
#define XOR_INT_END_OF_DESC BIT(0)
|
||||
#define XOR_INT_END_OF_CHAIN BIT(1)
|
||||
#define XOR_INT_STOPPED BIT(2)
|
||||
#define XOR_INT_PAUSED BIT(3)
|
||||
#define XOR_INT_ERR_DECODE BIT(4)
|
||||
#define XOR_INT_ERR_RDPROT BIT(5)
|
||||
#define XOR_INT_ERR_WRPROT BIT(6)
|
||||
#define XOR_INT_ERR_OWN BIT(7)
|
||||
#define XOR_INT_ERR_PAR BIT(8)
|
||||
#define XOR_INT_ERR_MBUS BIT(9)
|
||||
|
||||
#define XOR_INTR_ERRORS (XOR_INT_ERR_DECODE | XOR_INT_ERR_RDPROT | \
|
||||
XOR_INT_ERR_WRPROT | XOR_INT_ERR_OWN | \
|
||||
XOR_INT_ERR_PAR | XOR_INT_ERR_MBUS)
|
||||
|
||||
#define XOR_INTR_MASK_VALUE (XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | \
|
||||
XOR_INT_STOPPED | XOR_INTR_ERRORS)
|
||||
|
||||
#define WINDOW_BASE(w) (0x50 + ((w) << 2))
|
||||
#define WINDOW_SIZE(w) (0x70 + ((w) << 2))
|
||||
#define WINDOW_REMAP_HIGH(w) (0x90 + ((w) << 2))
|
||||
#define WINDOW_BAR_ENABLE(chan) (0x40 + ((chan) << 2))
|
||||
#define WINDOW_OVERRIDE_CTRL(chan) (0xA0 + ((chan) << 2))
|
||||
|
||||
struct mv_xor_device {
|
||||
void __iomem *xor_base;
|
||||
void __iomem *xor_high_base;
|
||||
struct clk *clk;
|
||||
struct mv_xor_chan *channels[MV_XOR_MAX_CHANNELS];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct mv_xor_chan - internal representation of a XOR channel
|
||||
* @pending: allows batching of hardware operations
|
||||
* @lock: serializes enqueue/dequeue operations to the descriptors pool
|
||||
* @mmr_base: memory mapped register base
|
||||
* @idx: the index of the xor channel
|
||||
* @chain: device chain view of the descriptors
|
||||
* @completed_slots: slots completed by HW but still need to be acked
|
||||
* @device: parent device
|
||||
* @common: common dmaengine channel object members
|
||||
* @last_used: place holder for allocation to continue from where it left off
|
||||
* @all_slots: complete domain of slots usable by the channel
|
||||
* @slots_allocated: records the actual size of the descriptor slot pool
|
||||
* @irq_tasklet: bottom half where mv_xor_slot_cleanup runs
|
||||
*/
|
||||
struct mv_xor_chan {
|
||||
int pending;
|
||||
spinlock_t lock; /* protects the descriptor slot pool */
|
||||
void __iomem *mmr_base;
|
||||
void __iomem *mmr_high_base;
|
||||
unsigned int idx;
|
||||
int irq;
|
||||
enum dma_transaction_type current_type;
|
||||
struct list_head chain;
|
||||
struct list_head completed_slots;
|
||||
dma_addr_t dma_desc_pool;
|
||||
void *dma_desc_pool_virt;
|
||||
size_t pool_size;
|
||||
struct dma_device dmadev;
|
||||
struct dma_chan dmachan;
|
||||
struct mv_xor_desc_slot *last_used;
|
||||
struct list_head all_slots;
|
||||
int slots_allocated;
|
||||
struct tasklet_struct irq_tasklet;
|
||||
char dummy_src[MV_XOR_MIN_BYTE_COUNT];
|
||||
char dummy_dst[MV_XOR_MIN_BYTE_COUNT];
|
||||
dma_addr_t dummy_src_addr, dummy_dst_addr;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct mv_xor_desc_slot - software descriptor
|
||||
* @slot_node: node on the mv_xor_chan.all_slots list
|
||||
* @chain_node: node on the mv_xor_chan.chain list
|
||||
* @completed_node: node on the mv_xor_chan.completed_slots list
|
||||
* @hw_desc: virtual address of the hardware descriptor chain
|
||||
* @phys: hardware address of the hardware descriptor chain
|
||||
* @slot_used: slot in use or not
|
||||
* @idx: pool index
|
||||
* @tx_list: list of slots that make up a multi-descriptor transaction
|
||||
* @async_tx: support for the async_tx api
|
||||
*/
|
||||
struct mv_xor_desc_slot {
|
||||
struct list_head slot_node;
|
||||
struct list_head chain_node;
|
||||
struct list_head completed_node;
|
||||
enum dma_transaction_type type;
|
||||
void *hw_desc;
|
||||
u16 slot_used;
|
||||
u16 idx;
|
||||
struct dma_async_tx_descriptor async_tx;
|
||||
};
|
||||
|
||||
/*
|
||||
* This structure describes XOR descriptor size 64bytes. The
|
||||
* mv_phy_src_idx() macro must be used when indexing the values of the
|
||||
* phy_src_addr[] array. This is due to the fact that the 'descriptor
|
||||
* swap' feature, used on big endian systems, swaps descriptors data
|
||||
* within blocks of 8 bytes. So two consecutive values of the
|
||||
* phy_src_addr[] array are actually swapped in big-endian, which
|
||||
* explains the different mv_phy_src_idx() implementation.
|
||||
*/
|
||||
#if defined(__LITTLE_ENDIAN)
|
||||
struct mv_xor_desc {
|
||||
u32 status; /* descriptor execution status */
|
||||
u32 crc32_result; /* result of CRC-32 calculation */
|
||||
u32 desc_command; /* type of operation to be carried out */
|
||||
u32 phy_next_desc; /* next descriptor address pointer */
|
||||
u32 byte_count; /* size of src/dst blocks in bytes */
|
||||
u32 phy_dest_addr; /* destination block address */
|
||||
u32 phy_src_addr[8]; /* source block addresses */
|
||||
u32 reserved0;
|
||||
u32 reserved1;
|
||||
};
|
||||
#define mv_phy_src_idx(src_idx) (src_idx)
|
||||
#else
|
||||
struct mv_xor_desc {
|
||||
u32 crc32_result; /* result of CRC-32 calculation */
|
||||
u32 status; /* descriptor execution status */
|
||||
u32 phy_next_desc; /* next descriptor address pointer */
|
||||
u32 desc_command; /* type of operation to be carried out */
|
||||
u32 phy_dest_addr; /* destination block address */
|
||||
u32 byte_count; /* size of src/dst blocks in bytes */
|
||||
u32 phy_src_addr[8]; /* source block addresses */
|
||||
u32 reserved1;
|
||||
u32 reserved0;
|
||||
};
|
||||
#define mv_phy_src_idx(src_idx) (src_idx ^ 1)
|
||||
#endif
|
||||
|
||||
#define to_mv_sw_desc(addr_hw_desc) \
|
||||
container_of(addr_hw_desc, struct mv_xor_desc_slot, hw_desc)
|
||||
|
||||
#define mv_hw_desc_slot_idx(hw_desc, idx) \
|
||||
((void *)(((unsigned long)hw_desc) + ((idx) << 5)))
|
||||
|
||||
#endif
|
||||
896
drivers/dma/mxs-dma.c
Normal file
896
drivers/dma/mxs-dma.c
Normal file
|
|
@ -0,0 +1,896 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* Refer to drivers/dma/imx-sdma.c
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/semaphore.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/stmp_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_dma.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
|
||||
#include "dmaengine.h"
|
||||
|
||||
/*
|
||||
* NOTE: The term "PIO" throughout the mxs-dma implementation means
|
||||
* PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
|
||||
* dma can program the controller registers of peripheral devices.
|
||||
*/
|
||||
|
||||
#define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH)
|
||||
#define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA)
|
||||
|
||||
#define HW_APBHX_CTRL0 0x000
|
||||
#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
|
||||
#define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
|
||||
#define BP_APBH_CTRL0_RESET_CHANNEL 16
|
||||
#define HW_APBHX_CTRL1 0x010
|
||||
#define HW_APBHX_CTRL2 0x020
|
||||
#define HW_APBHX_CHANNEL_CTRL 0x030
|
||||
#define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
|
||||
/*
|
||||
* The offset of NXTCMDAR register is different per both dma type and version,
|
||||
* while stride for each channel is all the same 0x70.
|
||||
*/
|
||||
#define HW_APBHX_CHn_NXTCMDAR(d, n) \
|
||||
(((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70)
|
||||
#define HW_APBHX_CHn_SEMA(d, n) \
|
||||
(((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70)
|
||||
#define HW_APBHX_CHn_BAR(d, n) \
|
||||
(((dma_is_apbh(d) && apbh_is_old(d)) ? 0x070 : 0x130) + (n) * 0x70)
|
||||
#define HW_APBX_CHn_DEBUG1(d, n) (0x150 + (n) * 0x70)
|
||||
|
||||
/*
|
||||
* ccw bits definitions
|
||||
*
|
||||
* COMMAND: 0..1 (2)
|
||||
* CHAIN: 2 (1)
|
||||
* IRQ: 3 (1)
|
||||
* NAND_LOCK: 4 (1) - not implemented
|
||||
* NAND_WAIT4READY: 5 (1) - not implemented
|
||||
* DEC_SEM: 6 (1)
|
||||
* WAIT4END: 7 (1)
|
||||
* HALT_ON_TERMINATE: 8 (1)
|
||||
* TERMINATE_FLUSH: 9 (1)
|
||||
* RESERVED: 10..11 (2)
|
||||
* PIO_NUM: 12..15 (4)
|
||||
*/
|
||||
#define BP_CCW_COMMAND 0
|
||||
#define BM_CCW_COMMAND (3 << 0)
|
||||
#define CCW_CHAIN (1 << 2)
|
||||
#define CCW_IRQ (1 << 3)
|
||||
#define CCW_DEC_SEM (1 << 6)
|
||||
#define CCW_WAIT4END (1 << 7)
|
||||
#define CCW_HALT_ON_TERM (1 << 8)
|
||||
#define CCW_TERM_FLUSH (1 << 9)
|
||||
#define BP_CCW_PIO_NUM 12
|
||||
#define BM_CCW_PIO_NUM (0xf << 12)
|
||||
|
||||
#define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
|
||||
|
||||
#define MXS_DMA_CMD_NO_XFER 0
|
||||
#define MXS_DMA_CMD_WRITE 1
|
||||
#define MXS_DMA_CMD_READ 2
|
||||
#define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
|
||||
|
||||
struct mxs_dma_ccw {
|
||||
u32 next;
|
||||
u16 bits;
|
||||
u16 xfer_bytes;
|
||||
#define MAX_XFER_BYTES 0xff00
|
||||
u32 bufaddr;
|
||||
#define MXS_PIO_WORDS 16
|
||||
u32 pio_words[MXS_PIO_WORDS];
|
||||
};
|
||||
|
||||
#define CCW_BLOCK_SIZE (4 * PAGE_SIZE)
|
||||
#define NUM_CCW (int)(CCW_BLOCK_SIZE / sizeof(struct mxs_dma_ccw))
|
||||
|
||||
struct mxs_dma_chan {
|
||||
struct mxs_dma_engine *mxs_dma;
|
||||
struct dma_chan chan;
|
||||
struct dma_async_tx_descriptor desc;
|
||||
struct tasklet_struct tasklet;
|
||||
unsigned int chan_irq;
|
||||
struct mxs_dma_ccw *ccw;
|
||||
dma_addr_t ccw_phys;
|
||||
int desc_count;
|
||||
enum dma_status status;
|
||||
unsigned int flags;
|
||||
bool reset;
|
||||
#define MXS_DMA_SG_LOOP (1 << 0)
|
||||
#define MXS_DMA_USE_SEMAPHORE (1 << 1)
|
||||
};
|
||||
|
||||
#define MXS_DMA_CHANNELS 16
|
||||
#define MXS_DMA_CHANNELS_MASK 0xffff
|
||||
|
||||
enum mxs_dma_devtype {
|
||||
MXS_DMA_APBH,
|
||||
MXS_DMA_APBX,
|
||||
};
|
||||
|
||||
enum mxs_dma_id {
|
||||
IMX23_DMA,
|
||||
IMX28_DMA,
|
||||
};
|
||||
|
||||
struct mxs_dma_engine {
|
||||
enum mxs_dma_id dev_id;
|
||||
enum mxs_dma_devtype type;
|
||||
void __iomem *base;
|
||||
struct clk *clk;
|
||||
struct dma_device dma_device;
|
||||
struct device_dma_parameters dma_parms;
|
||||
struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS];
|
||||
struct platform_device *pdev;
|
||||
unsigned int nr_channels;
|
||||
};
|
||||
|
||||
struct mxs_dma_type {
|
||||
enum mxs_dma_id id;
|
||||
enum mxs_dma_devtype type;
|
||||
};
|
||||
|
||||
static struct mxs_dma_type mxs_dma_types[] = {
|
||||
{
|
||||
.id = IMX23_DMA,
|
||||
.type = MXS_DMA_APBH,
|
||||
}, {
|
||||
.id = IMX23_DMA,
|
||||
.type = MXS_DMA_APBX,
|
||||
}, {
|
||||
.id = IMX28_DMA,
|
||||
.type = MXS_DMA_APBH,
|
||||
}, {
|
||||
.id = IMX28_DMA,
|
||||
.type = MXS_DMA_APBX,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device_id mxs_dma_ids[] = {
|
||||
{
|
||||
.name = "imx23-dma-apbh",
|
||||
.driver_data = (kernel_ulong_t) &mxs_dma_types[0],
|
||||
}, {
|
||||
.name = "imx23-dma-apbx",
|
||||
.driver_data = (kernel_ulong_t) &mxs_dma_types[1],
|
||||
}, {
|
||||
.name = "imx28-dma-apbh",
|
||||
.driver_data = (kernel_ulong_t) &mxs_dma_types[2],
|
||||
}, {
|
||||
.name = "imx28-dma-apbx",
|
||||
.driver_data = (kernel_ulong_t) &mxs_dma_types[3],
|
||||
}, {
|
||||
/* end of list */
|
||||
}
|
||||
};
|
||||
|
||||
static const struct of_device_id mxs_dma_dt_ids[] = {
|
||||
{ .compatible = "fsl,imx23-dma-apbh", .data = &mxs_dma_ids[0], },
|
||||
{ .compatible = "fsl,imx23-dma-apbx", .data = &mxs_dma_ids[1], },
|
||||
{ .compatible = "fsl,imx28-dma-apbh", .data = &mxs_dma_ids[2], },
|
||||
{ .compatible = "fsl,imx28-dma-apbx", .data = &mxs_dma_ids[3], },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids);
|
||||
|
||||
static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
|
||||
{
|
||||
return container_of(chan, struct mxs_dma_chan, chan);
|
||||
}
|
||||
|
||||
static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
|
||||
{
|
||||
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
|
||||
int chan_id = mxs_chan->chan.chan_id;
|
||||
|
||||
/*
|
||||
* mxs dma channel resets can cause a channel stall. To recover from a
|
||||
* channel stall, we have to reset the whole DMA engine. To avoid this,
|
||||
* we use cyclic DMA with semaphores, that are enhanced in
|
||||
* mxs_dma_int_handler. To reset the channel, we can simply stop writing
|
||||
* into the semaphore counter.
|
||||
*/
|
||||
if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE &&
|
||||
mxs_chan->flags & MXS_DMA_SG_LOOP) {
|
||||
mxs_chan->reset = true;
|
||||
} else if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) {
|
||||
writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
|
||||
mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
|
||||
} else {
|
||||
unsigned long elapsed = 0;
|
||||
const unsigned long max_wait = 50000; /* 50ms */
|
||||
void __iomem *reg_dbg1 = mxs_dma->base +
|
||||
HW_APBX_CHn_DEBUG1(mxs_dma, chan_id);
|
||||
|
||||
/*
|
||||
* On i.MX28 APBX, the DMA channel can stop working if we reset
|
||||
* the channel while it is in READ_FLUSH (0x08) state.
|
||||
* We wait here until we leave the state. Then we trigger the
|
||||
* reset. Waiting a maximum of 50ms, the kernel shouldn't crash
|
||||
* because of this.
|
||||
*/
|
||||
while ((readl(reg_dbg1) & 0xf) == 0x8 && elapsed < max_wait) {
|
||||
udelay(100);
|
||||
elapsed += 100;
|
||||
}
|
||||
|
||||
if (elapsed >= max_wait)
|
||||
dev_err(&mxs_chan->mxs_dma->pdev->dev,
|
||||
"Failed waiting for the DMA channel %d to leave state READ_FLUSH, trying to reset channel in READ_FLUSH state now\n",
|
||||
chan_id);
|
||||
|
||||
writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
|
||||
mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
|
||||
}
|
||||
|
||||
mxs_chan->status = DMA_COMPLETE;
|
||||
}
|
||||
|
||||
static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
|
||||
{
|
||||
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
|
||||
int chan_id = mxs_chan->chan.chan_id;
|
||||
|
||||
/* set cmd_addr up */
|
||||
writel(mxs_chan->ccw_phys,
|
||||
mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id));
|
||||
|
||||
/* write 1 to SEMA to kick off the channel */
|
||||
if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE &&
|
||||
mxs_chan->flags & MXS_DMA_SG_LOOP) {
|
||||
/* A cyclic DMA consists of at least 2 segments, so initialize
|
||||
* the semaphore with 2 so we have enough time to add 1 to the
|
||||
* semaphore if we need to */
|
||||
writel(2, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
|
||||
} else {
|
||||
writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
|
||||
}
|
||||
mxs_chan->reset = false;
|
||||
}
|
||||
|
||||
static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan)
|
||||
{
|
||||
mxs_chan->status = DMA_COMPLETE;
|
||||
}
|
||||
|
||||
static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan)
|
||||
{
|
||||
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
|
||||
int chan_id = mxs_chan->chan.chan_id;
|
||||
|
||||
/* freeze the channel */
|
||||
if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
|
||||
writel(1 << chan_id,
|
||||
mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
|
||||
else
|
||||
writel(1 << chan_id,
|
||||
mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
|
||||
|
||||
mxs_chan->status = DMA_PAUSED;
|
||||
}
|
||||
|
||||
static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
|
||||
{
|
||||
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
|
||||
int chan_id = mxs_chan->chan.chan_id;
|
||||
|
||||
/* unfreeze the channel */
|
||||
if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
|
||||
writel(1 << chan_id,
|
||||
mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
|
||||
else
|
||||
writel(1 << chan_id,
|
||||
mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR);
|
||||
|
||||
mxs_chan->status = DMA_IN_PROGRESS;
|
||||
}
|
||||
|
||||
static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
|
||||
{
|
||||
return dma_cookie_assign(tx);
|
||||
}
|
||||
|
||||
static void mxs_dma_tasklet(unsigned long data)
|
||||
{
|
||||
struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data;
|
||||
|
||||
if (mxs_chan->desc.callback)
|
||||
mxs_chan->desc.callback(mxs_chan->desc.callback_param);
|
||||
}
|
||||
|
||||
static int mxs_dma_irq_to_chan(struct mxs_dma_engine *mxs_dma, int irq)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i != mxs_dma->nr_channels; ++i)
|
||||
if (mxs_dma->mxs_chans[i].chan_irq == irq)
|
||||
return i;
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct mxs_dma_engine *mxs_dma = dev_id;
|
||||
struct mxs_dma_chan *mxs_chan;
|
||||
u32 completed;
|
||||
u32 err;
|
||||
int chan = mxs_dma_irq_to_chan(mxs_dma, irq);
|
||||
|
||||
if (chan < 0)
|
||||
return IRQ_NONE;
|
||||
|
||||
/* completion status */
|
||||
completed = readl(mxs_dma->base + HW_APBHX_CTRL1);
|
||||
completed = (completed >> chan) & 0x1;
|
||||
|
||||
/* Clear interrupt */
|
||||
writel((1 << chan),
|
||||
mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
|
||||
|
||||
/* error status */
|
||||
err = readl(mxs_dma->base + HW_APBHX_CTRL2);
|
||||
err &= (1 << (MXS_DMA_CHANNELS + chan)) | (1 << chan);
|
||||
|
||||
/*
|
||||
* error status bit is in the upper 16 bits, error irq bit in the lower
|
||||
* 16 bits. We transform it into a simpler error code:
|
||||
* err: 0x00 = no error, 0x01 = TERMINATION, 0x02 = BUS_ERROR
|
||||
*/
|
||||
err = (err >> (MXS_DMA_CHANNELS + chan)) + (err >> chan);
|
||||
|
||||
/* Clear error irq */
|
||||
writel((1 << chan),
|
||||
mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
|
||||
|
||||
/*
|
||||
* When both completion and error of termination bits set at the
|
||||
* same time, we do not take it as an error. IOW, it only becomes
|
||||
* an error we need to handle here in case of either it's a bus
|
||||
* error or a termination error with no completion. 0x01 is termination
|
||||
* error, so we can subtract err & completed to get the real error case.
|
||||
*/
|
||||
err -= err & completed;
|
||||
|
||||
mxs_chan = &mxs_dma->mxs_chans[chan];
|
||||
|
||||
if (err) {
|
||||
dev_dbg(mxs_dma->dma_device.dev,
|
||||
"%s: error in channel %d\n", __func__,
|
||||
chan);
|
||||
mxs_chan->status = DMA_ERROR;
|
||||
mxs_dma_reset_chan(mxs_chan);
|
||||
} else if (mxs_chan->status != DMA_COMPLETE) {
|
||||
if (mxs_chan->flags & MXS_DMA_SG_LOOP) {
|
||||
mxs_chan->status = DMA_IN_PROGRESS;
|
||||
if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE)
|
||||
writel(1, mxs_dma->base +
|
||||
HW_APBHX_CHn_SEMA(mxs_dma, chan));
|
||||
} else {
|
||||
mxs_chan->status = DMA_COMPLETE;
|
||||
}
|
||||
}
|
||||
|
||||
if (mxs_chan->status == DMA_COMPLETE) {
|
||||
if (mxs_chan->reset)
|
||||
return IRQ_HANDLED;
|
||||
dma_cookie_complete(&mxs_chan->desc);
|
||||
}
|
||||
|
||||
/* schedule tasklet on this channel */
|
||||
tasklet_schedule(&mxs_chan->tasklet);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
|
||||
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
|
||||
int ret;
|
||||
|
||||
mxs_chan->ccw = dma_zalloc_coherent(mxs_dma->dma_device.dev,
|
||||
CCW_BLOCK_SIZE,
|
||||
&mxs_chan->ccw_phys, GFP_KERNEL);
|
||||
if (!mxs_chan->ccw) {
|
||||
ret = -ENOMEM;
|
||||
goto err_alloc;
|
||||
}
|
||||
|
||||
if (mxs_chan->chan_irq != NO_IRQ) {
|
||||
ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
|
||||
0, "mxs-dma", mxs_dma);
|
||||
if (ret)
|
||||
goto err_irq;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(mxs_dma->clk);
|
||||
if (ret)
|
||||
goto err_clk;
|
||||
|
||||
mxs_dma_reset_chan(mxs_chan);
|
||||
|
||||
dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
|
||||
mxs_chan->desc.tx_submit = mxs_dma_tx_submit;
|
||||
|
||||
/* the descriptor is ready */
|
||||
async_tx_ack(&mxs_chan->desc);
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk:
|
||||
free_irq(mxs_chan->chan_irq, mxs_dma);
|
||||
err_irq:
|
||||
dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
|
||||
mxs_chan->ccw, mxs_chan->ccw_phys);
|
||||
err_alloc:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mxs_dma_free_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
|
||||
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
|
||||
|
||||
mxs_dma_disable_chan(mxs_chan);
|
||||
|
||||
free_irq(mxs_chan->chan_irq, mxs_dma);
|
||||
|
||||
dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
|
||||
mxs_chan->ccw, mxs_chan->ccw_phys);
|
||||
|
||||
clk_disable_unprepare(mxs_dma->clk);
|
||||
}
|
||||
|
||||
/*
|
||||
* How to use the flags for ->device_prep_slave_sg() :
|
||||
* [1] If there is only one DMA command in the DMA chain, the code should be:
|
||||
* ......
|
||||
* ->device_prep_slave_sg(DMA_CTRL_ACK);
|
||||
* ......
|
||||
* [2] If there are two DMA commands in the DMA chain, the code should be
|
||||
* ......
|
||||
* ->device_prep_slave_sg(0);
|
||||
* ......
|
||||
* ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
* ......
|
||||
* [3] If there are more than two DMA commands in the DMA chain, the code
|
||||
* should be:
|
||||
* ......
|
||||
* ->device_prep_slave_sg(0); // First
|
||||
* ......
|
||||
* ->device_prep_slave_sg(DMA_PREP_INTERRUPT [| DMA_CTRL_ACK]);
|
||||
* ......
|
||||
* ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); // Last
|
||||
* ......
|
||||
*/
|
||||
static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
|
||||
struct dma_chan *chan, struct scatterlist *sgl,
|
||||
unsigned int sg_len, enum dma_transfer_direction direction,
|
||||
unsigned long flags, void *context)
|
||||
{
|
||||
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
|
||||
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
|
||||
struct mxs_dma_ccw *ccw;
|
||||
struct scatterlist *sg;
|
||||
u32 i, j;
|
||||
u32 *pio;
|
||||
bool append = flags & DMA_PREP_INTERRUPT;
|
||||
int idx = append ? mxs_chan->desc_count : 0;
|
||||
|
||||
if (mxs_chan->status == DMA_IN_PROGRESS && !append)
|
||||
return NULL;
|
||||
|
||||
if (sg_len + (append ? idx : 0) > NUM_CCW) {
|
||||
dev_err(mxs_dma->dma_device.dev,
|
||||
"maximum number of sg exceeded: %d > %d\n",
|
||||
sg_len, NUM_CCW);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
mxs_chan->status = DMA_IN_PROGRESS;
|
||||
mxs_chan->flags = 0;
|
||||
|
||||
/*
|
||||
* If the sg is prepared with append flag set, the sg
|
||||
* will be appended to the last prepared sg.
|
||||
*/
|
||||
if (append) {
|
||||
BUG_ON(idx < 1);
|
||||
ccw = &mxs_chan->ccw[idx - 1];
|
||||
ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
|
||||
ccw->bits |= CCW_CHAIN;
|
||||
ccw->bits &= ~CCW_IRQ;
|
||||
ccw->bits &= ~CCW_DEC_SEM;
|
||||
} else {
|
||||
idx = 0;
|
||||
}
|
||||
|
||||
if (direction == DMA_TRANS_NONE) {
|
||||
ccw = &mxs_chan->ccw[idx++];
|
||||
pio = (u32 *) sgl;
|
||||
|
||||
for (j = 0; j < sg_len;)
|
||||
ccw->pio_words[j++] = *pio++;
|
||||
|
||||
ccw->bits = 0;
|
||||
ccw->bits |= CCW_IRQ;
|
||||
ccw->bits |= CCW_DEC_SEM;
|
||||
if (flags & DMA_CTRL_ACK)
|
||||
ccw->bits |= CCW_WAIT4END;
|
||||
ccw->bits |= CCW_HALT_ON_TERM;
|
||||
ccw->bits |= CCW_TERM_FLUSH;
|
||||
ccw->bits |= BF_CCW(sg_len, PIO_NUM);
|
||||
ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
|
||||
} else {
|
||||
for_each_sg(sgl, sg, sg_len, i) {
|
||||
if (sg_dma_len(sg) > MAX_XFER_BYTES) {
|
||||
dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
|
||||
sg_dma_len(sg), MAX_XFER_BYTES);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
ccw = &mxs_chan->ccw[idx++];
|
||||
|
||||
ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
|
||||
ccw->bufaddr = sg->dma_address;
|
||||
ccw->xfer_bytes = sg_dma_len(sg);
|
||||
|
||||
ccw->bits = 0;
|
||||
ccw->bits |= CCW_CHAIN;
|
||||
ccw->bits |= CCW_HALT_ON_TERM;
|
||||
ccw->bits |= CCW_TERM_FLUSH;
|
||||
ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
|
||||
MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
|
||||
COMMAND);
|
||||
|
||||
if (i + 1 == sg_len) {
|
||||
ccw->bits &= ~CCW_CHAIN;
|
||||
ccw->bits |= CCW_IRQ;
|
||||
ccw->bits |= CCW_DEC_SEM;
|
||||
if (flags & DMA_CTRL_ACK)
|
||||
ccw->bits |= CCW_WAIT4END;
|
||||
}
|
||||
}
|
||||
}
|
||||
mxs_chan->desc_count = idx;
|
||||
|
||||
return &mxs_chan->desc;
|
||||
|
||||
err_out:
|
||||
mxs_chan->status = DMA_ERROR;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
|
||||
struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
|
||||
size_t period_len, enum dma_transfer_direction direction,
|
||||
unsigned long flags, void *context)
|
||||
{
|
||||
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
|
||||
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
|
||||
u32 num_periods = buf_len / period_len;
|
||||
u32 i = 0, buf = 0;
|
||||
|
||||
if (mxs_chan->status == DMA_IN_PROGRESS)
|
||||
return NULL;
|
||||
|
||||
mxs_chan->status = DMA_IN_PROGRESS;
|
||||
mxs_chan->flags |= MXS_DMA_SG_LOOP;
|
||||
mxs_chan->flags |= MXS_DMA_USE_SEMAPHORE;
|
||||
|
||||
if (num_periods > NUM_CCW) {
|
||||
dev_err(mxs_dma->dma_device.dev,
|
||||
"maximum number of sg exceeded: %d > %d\n",
|
||||
num_periods, NUM_CCW);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
if (period_len > MAX_XFER_BYTES) {
|
||||
dev_err(mxs_dma->dma_device.dev,
|
||||
"maximum period size exceeded: %d > %d\n",
|
||||
period_len, MAX_XFER_BYTES);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
while (buf < buf_len) {
|
||||
struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];
|
||||
|
||||
if (i + 1 == num_periods)
|
||||
ccw->next = mxs_chan->ccw_phys;
|
||||
else
|
||||
ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1);
|
||||
|
||||
ccw->bufaddr = dma_addr;
|
||||
ccw->xfer_bytes = period_len;
|
||||
|
||||
ccw->bits = 0;
|
||||
ccw->bits |= CCW_CHAIN;
|
||||
ccw->bits |= CCW_IRQ;
|
||||
ccw->bits |= CCW_HALT_ON_TERM;
|
||||
ccw->bits |= CCW_TERM_FLUSH;
|
||||
ccw->bits |= CCW_DEC_SEM;
|
||||
ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
|
||||
MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
|
||||
|
||||
dma_addr += period_len;
|
||||
buf += period_len;
|
||||
|
||||
i++;
|
||||
}
|
||||
mxs_chan->desc_count = i;
|
||||
|
||||
return &mxs_chan->desc;
|
||||
|
||||
err_out:
|
||||
mxs_chan->status = DMA_ERROR;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
|
||||
int ret = 0;
|
||||
|
||||
switch (cmd) {
|
||||
case DMA_TERMINATE_ALL:
|
||||
mxs_dma_reset_chan(mxs_chan);
|
||||
mxs_dma_disable_chan(mxs_chan);
|
||||
break;
|
||||
case DMA_PAUSE:
|
||||
mxs_dma_pause_chan(mxs_chan);
|
||||
break;
|
||||
case DMA_RESUME:
|
||||
mxs_dma_resume_chan(mxs_chan);
|
||||
break;
|
||||
default:
|
||||
ret = -ENOSYS;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
|
||||
dma_cookie_t cookie, struct dma_tx_state *txstate)
|
||||
{
|
||||
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
|
||||
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
|
||||
u32 residue = 0;
|
||||
|
||||
if (mxs_chan->status == DMA_IN_PROGRESS &&
|
||||
mxs_chan->flags & MXS_DMA_SG_LOOP) {
|
||||
struct mxs_dma_ccw *last_ccw;
|
||||
u32 bar;
|
||||
|
||||
last_ccw = &mxs_chan->ccw[mxs_chan->desc_count - 1];
|
||||
residue = last_ccw->xfer_bytes + last_ccw->bufaddr;
|
||||
|
||||
bar = readl(mxs_dma->base +
|
||||
HW_APBHX_CHn_BAR(mxs_dma, chan->chan_id));
|
||||
residue -= bar;
|
||||
}
|
||||
|
||||
dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
|
||||
residue);
|
||||
|
||||
return mxs_chan->status;
|
||||
}
|
||||
|
||||
static void mxs_dma_issue_pending(struct dma_chan *chan)
|
||||
{
|
||||
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
|
||||
|
||||
mxs_dma_enable_chan(mxs_chan);
|
||||
}
|
||||
|
||||
static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(mxs_dma->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = stmp_reset_block(mxs_dma->base);
|
||||
if (ret)
|
||||
goto err_out;
|
||||
|
||||
/* enable apbh burst */
|
||||
if (dma_is_apbh(mxs_dma)) {
|
||||
writel(BM_APBH_CTRL0_APB_BURST_EN,
|
||||
mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
|
||||
writel(BM_APBH_CTRL0_APB_BURST8_EN,
|
||||
mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
|
||||
}
|
||||
|
||||
/* enable irq for all the channels */
|
||||
writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
|
||||
mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
|
||||
|
||||
err_out:
|
||||
clk_disable_unprepare(mxs_dma->clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct mxs_dma_filter_param {
|
||||
struct device_node *of_node;
|
||||
unsigned int chan_id;
|
||||
};
|
||||
|
||||
static bool mxs_dma_filter_fn(struct dma_chan *chan, void *fn_param)
|
||||
{
|
||||
struct mxs_dma_filter_param *param = fn_param;
|
||||
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
|
||||
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
|
||||
int chan_irq;
|
||||
|
||||
if (mxs_dma->dma_device.dev->of_node != param->of_node)
|
||||
return false;
|
||||
|
||||
if (chan->chan_id != param->chan_id)
|
||||
return false;
|
||||
|
||||
chan_irq = platform_get_irq(mxs_dma->pdev, param->chan_id);
|
||||
if (chan_irq < 0)
|
||||
return false;
|
||||
|
||||
mxs_chan->chan_irq = chan_irq;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static struct dma_chan *mxs_dma_xlate(struct of_phandle_args *dma_spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
struct mxs_dma_engine *mxs_dma = ofdma->of_dma_data;
|
||||
dma_cap_mask_t mask = mxs_dma->dma_device.cap_mask;
|
||||
struct mxs_dma_filter_param param;
|
||||
|
||||
if (dma_spec->args_count != 1)
|
||||
return NULL;
|
||||
|
||||
param.of_node = ofdma->of_node;
|
||||
param.chan_id = dma_spec->args[0];
|
||||
|
||||
if (param.chan_id >= mxs_dma->nr_channels)
|
||||
return NULL;
|
||||
|
||||
return dma_request_channel(mask, mxs_dma_filter_fn, ¶m);
|
||||
}
|
||||
|
||||
static int __init mxs_dma_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
const struct platform_device_id *id_entry;
|
||||
const struct of_device_id *of_id;
|
||||
const struct mxs_dma_type *dma_type;
|
||||
struct mxs_dma_engine *mxs_dma;
|
||||
struct resource *iores;
|
||||
int ret, i;
|
||||
|
||||
mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL);
|
||||
if (!mxs_dma)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = of_property_read_u32(np, "dma-channels", &mxs_dma->nr_channels);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to read dma-channels\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
of_id = of_match_device(mxs_dma_dt_ids, &pdev->dev);
|
||||
if (of_id)
|
||||
id_entry = of_id->data;
|
||||
else
|
||||
id_entry = platform_get_device_id(pdev);
|
||||
|
||||
dma_type = (struct mxs_dma_type *)id_entry->driver_data;
|
||||
mxs_dma->type = dma_type->type;
|
||||
mxs_dma->dev_id = dma_type->id;
|
||||
|
||||
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
mxs_dma->base = devm_ioremap_resource(&pdev->dev, iores);
|
||||
if (IS_ERR(mxs_dma->base))
|
||||
return PTR_ERR(mxs_dma->base);
|
||||
|
||||
mxs_dma->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(mxs_dma->clk))
|
||||
return PTR_ERR(mxs_dma->clk);
|
||||
|
||||
dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
|
||||
dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);
|
||||
|
||||
INIT_LIST_HEAD(&mxs_dma->dma_device.channels);
|
||||
|
||||
/* Initialize channel parameters */
|
||||
for (i = 0; i < MXS_DMA_CHANNELS; i++) {
|
||||
struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];
|
||||
|
||||
mxs_chan->mxs_dma = mxs_dma;
|
||||
mxs_chan->chan.device = &mxs_dma->dma_device;
|
||||
dma_cookie_init(&mxs_chan->chan);
|
||||
|
||||
tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet,
|
||||
(unsigned long) mxs_chan);
|
||||
|
||||
|
||||
/* Add the channel to mxs_chan list */
|
||||
list_add_tail(&mxs_chan->chan.device_node,
|
||||
&mxs_dma->dma_device.channels);
|
||||
}
|
||||
|
||||
ret = mxs_dma_init(mxs_dma);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mxs_dma->pdev = pdev;
|
||||
mxs_dma->dma_device.dev = &pdev->dev;
|
||||
|
||||
/* mxs_dma gets 65535 bytes maximum sg size */
|
||||
mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms;
|
||||
dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);
|
||||
|
||||
mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
|
||||
mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
|
||||
mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
|
||||
mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
|
||||
mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
|
||||
mxs_dma->dma_device.device_control = mxs_dma_control;
|
||||
mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending;
|
||||
|
||||
ret = dma_async_device_register(&mxs_dma->dma_device);
|
||||
if (ret) {
|
||||
dev_err(mxs_dma->dma_device.dev, "unable to register\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_dma_controller_register(np, mxs_dma_xlate, mxs_dma);
|
||||
if (ret) {
|
||||
dev_err(mxs_dma->dma_device.dev,
|
||||
"failed to register controller\n");
|
||||
dma_async_device_unregister(&mxs_dma->dma_device);
|
||||
}
|
||||
|
||||
dev_info(mxs_dma->dma_device.dev, "initialized\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver mxs_dma_driver = {
|
||||
.driver = {
|
||||
.name = "mxs-dma",
|
||||
.of_match_table = mxs_dma_dt_ids,
|
||||
},
|
||||
.id_table = mxs_dma_ids,
|
||||
};
|
||||
|
||||
static int __init mxs_dma_module_init(void)
|
||||
{
|
||||
return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe);
|
||||
}
|
||||
subsys_initcall(mxs_dma_module_init);
|
||||
1517
drivers/dma/nbpfaxi.c
Normal file
1517
drivers/dma/nbpfaxi.c
Normal file
File diff suppressed because it is too large
Load diff
402
drivers/dma/of-dma.c
Normal file
402
drivers/dma/of-dma.c
Normal file
|
|
@ -0,0 +1,402 @@
|
|||
/*
|
||||
* Device tree helpers for DMA request / controller
|
||||
*
|
||||
* Based on of_gpio.c
|
||||
*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_dma.h>
|
||||
|
||||
static LIST_HEAD(of_dma_list);
|
||||
static DEFINE_MUTEX(of_dma_lock);
|
||||
|
||||
/**
|
||||
* of_dma_find_controller - Get a DMA controller in DT DMA helpers list
|
||||
* @dma_spec: pointer to DMA specifier as found in the device tree
|
||||
*
|
||||
* Finds a DMA controller with matching device node and number for dma cells
|
||||
* in a list of registered DMA controllers. If a match is found a valid pointer
|
||||
* to the DMA data stored is retuned. A NULL pointer is returned if no match is
|
||||
* found.
|
||||
*/
|
||||
static struct of_dma *of_dma_find_controller(struct of_phandle_args *dma_spec)
|
||||
{
|
||||
struct of_dma *ofdma;
|
||||
|
||||
list_for_each_entry(ofdma, &of_dma_list, of_dma_controllers)
|
||||
if (ofdma->of_node == dma_spec->np)
|
||||
return ofdma;
|
||||
|
||||
pr_debug("%s: can't find DMA controller %s\n", __func__,
|
||||
dma_spec->np->full_name);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* of_dma_controller_register - Register a DMA controller to DT DMA helpers
|
||||
* @np: device node of DMA controller
|
||||
* @of_dma_xlate: translation function which converts a phandle
|
||||
* arguments list into a dma_chan structure
|
||||
* @data pointer to controller specific data to be used by
|
||||
* translation function
|
||||
*
|
||||
* Returns 0 on success or appropriate errno value on error.
|
||||
*
|
||||
* Allocated memory should be freed with appropriate of_dma_controller_free()
|
||||
* call.
|
||||
*/
|
||||
int of_dma_controller_register(struct device_node *np,
|
||||
struct dma_chan *(*of_dma_xlate)
|
||||
(struct of_phandle_args *, struct of_dma *),
|
||||
void *data)
|
||||
{
|
||||
struct of_dma *ofdma;
|
||||
|
||||
if (!np || !of_dma_xlate) {
|
||||
pr_err("%s: not enough information provided\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ofdma = kzalloc(sizeof(*ofdma), GFP_KERNEL);
|
||||
if (!ofdma)
|
||||
return -ENOMEM;
|
||||
|
||||
ofdma->of_node = np;
|
||||
ofdma->of_dma_xlate = of_dma_xlate;
|
||||
ofdma->of_dma_data = data;
|
||||
|
||||
/* Now queue of_dma controller structure in list */
|
||||
mutex_lock(&of_dma_lock);
|
||||
list_add_tail(&ofdma->of_dma_controllers, &of_dma_list);
|
||||
mutex_unlock(&of_dma_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_dma_controller_register);
|
||||
|
||||
/**
|
||||
* of_dma_controller_free - Remove a DMA controller from DT DMA helpers list
|
||||
* @np: device node of DMA controller
|
||||
*
|
||||
* Memory allocated by of_dma_controller_register() is freed here.
|
||||
*/
|
||||
void of_dma_controller_free(struct device_node *np)
|
||||
{
|
||||
struct of_dma *ofdma;
|
||||
|
||||
mutex_lock(&of_dma_lock);
|
||||
|
||||
list_for_each_entry(ofdma, &of_dma_list, of_dma_controllers)
|
||||
if (ofdma->of_node == np) {
|
||||
list_del(&ofdma->of_dma_controllers);
|
||||
kfree(ofdma);
|
||||
break;
|
||||
}
|
||||
|
||||
mutex_unlock(&of_dma_lock);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_dma_controller_free);
|
||||
|
||||
/**
|
||||
* of_dma_match_channel - Check if a DMA specifier matches name
|
||||
* @np: device node to look for DMA channels
|
||||
* @name: channel name to be matched
|
||||
* @index: index of DMA specifier in list of DMA specifiers
|
||||
* @dma_spec: pointer to DMA specifier as found in the device tree
|
||||
*
|
||||
* Check if the DMA specifier pointed to by the index in a list of DMA
|
||||
* specifiers, matches the name provided. Returns 0 if the name matches and
|
||||
* a valid pointer to the DMA specifier is found. Otherwise returns -ENODEV.
|
||||
*/
|
||||
static int of_dma_match_channel(struct device_node *np, const char *name,
|
||||
int index, struct of_phandle_args *dma_spec)
|
||||
{
|
||||
const char *s;
|
||||
|
||||
if (of_property_read_string_index(np, "dma-names", index, &s))
|
||||
return -ENODEV;
|
||||
|
||||
if (strcmp(name, s))
|
||||
return -ENODEV;
|
||||
|
||||
if (of_parse_phandle_with_args(np, "dmas", "#dma-cells", index,
|
||||
dma_spec))
|
||||
return -ENODEV;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* of_dma_get_mcode_addr - Get the DMA micro code buffer address.
|
||||
* @np: device node of DMA controller
|
||||
*
|
||||
* Return the physical address.
|
||||
*/
|
||||
unsigned int of_dma_get_mcode_addr(struct device_node *np)
|
||||
{
|
||||
unsigned int addr = 0;
|
||||
const __be32 *prop;
|
||||
|
||||
prop = of_get_property(np, "#dma-mcode-addr", NULL);
|
||||
if (prop)
|
||||
addr = be32_to_cpup(prop);
|
||||
|
||||
return addr;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_dma_get_mcode_addr);
|
||||
|
||||
/**
|
||||
* of_dma_secure_dma_ch- Get the DMA micro code buffer address.
|
||||
* @np: device node of DMA controller
|
||||
*
|
||||
* Return the physical address.
|
||||
*/
|
||||
bool of_dma_secure_mode(struct device_node *np)
|
||||
{
|
||||
bool ret = 0;
|
||||
const __be32 *prop;
|
||||
|
||||
prop = of_get_property(np, "#dma-secure-mode", NULL);
|
||||
if (prop)
|
||||
ret = be32_to_cpup(prop);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_dma_secure_mode);
|
||||
|
||||
/**
|
||||
* of_dma_get_arwrapper_address - Get the DMA WAPPER AR address
|
||||
* @np: device node of DMA controller
|
||||
* @num: DMA channel thread number
|
||||
*
|
||||
* Return the virtual address.
|
||||
*/
|
||||
void __iomem *of_dma_get_arwrapper_address(struct device_node *np, unsigned int num)
|
||||
{
|
||||
const __be32 *reg_list;
|
||||
unsigned int length, count;
|
||||
|
||||
reg_list = of_get_property(np, "dma-arwrapper", &length);
|
||||
count = (unsigned int)(length / sizeof(unsigned int));
|
||||
|
||||
if (!reg_list || num >= count)
|
||||
return NULL;
|
||||
|
||||
return ioremap(be32_to_cpup(reg_list + num), SZ_32);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_dma_get_arwrapper_address);
|
||||
|
||||
/**
|
||||
* of_dma_get_arwrapper_address - Get the DMA WAPPER AW address
|
||||
* @np: device node of DMA controller
|
||||
* @num: DMA channel thread number
|
||||
*
|
||||
* Return the virtual address.
|
||||
*/
|
||||
void __iomem *of_dma_get_awwrapper_address(struct device_node *np, unsigned int num)
|
||||
{
|
||||
const __be32 *reg_list;
|
||||
unsigned int length, count;
|
||||
|
||||
reg_list = of_get_property(np, "dma-awwrapper", &length);
|
||||
count = (unsigned int)(length / sizeof(unsigned int));
|
||||
|
||||
if (!reg_list || num >= count)
|
||||
return NULL;
|
||||
|
||||
return ioremap(be32_to_cpup(reg_list + num), SZ_32);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_dma_get_awwrapper_address);
|
||||
|
||||
/**
|
||||
* of_dma_get_arwrapper_address - Get the DMA WAPPER AR address of DMA instruction
|
||||
* @np: device node of DMA controller
|
||||
*
|
||||
* Return the virtual address.
|
||||
*/
|
||||
void __iomem *of_dma_get_instwrapper_address(struct device_node *np)
|
||||
{
|
||||
const __be32 *reg_list;
|
||||
int ret = 0;
|
||||
|
||||
reg_list = of_get_property(np, "dma-instwrapper", NULL);
|
||||
|
||||
if (!reg_list)
|
||||
return NULL;
|
||||
|
||||
ret = be32_to_cpup(reg_list);
|
||||
if (!ret)
|
||||
return NULL;
|
||||
|
||||
return ioremap(ret, SZ_32);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_dma_get_instwrapper_address);
|
||||
|
||||
/**
|
||||
* of_dma_get_arwrapper_address - Get the DMA WAPPER availableilable
|
||||
* @np: device node of DMA controller
|
||||
*
|
||||
*/
|
||||
bool of_dma_get_wrapper_available(struct device_node *np)
|
||||
{
|
||||
const __be32 *reg_list;
|
||||
int ret = 0;
|
||||
|
||||
reg_list = of_get_property(np, "dma-instwrapper", NULL);
|
||||
|
||||
if (!reg_list)
|
||||
return false;
|
||||
|
||||
ret = be32_to_cpup(reg_list);
|
||||
if (ret)
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_dma_get_wrapper_available);
|
||||
|
||||
/**
|
||||
* of_dma_get_arwrapper_address - Get the DMA WAPPER availableilable
|
||||
* @np: device node of DMA controller
|
||||
*
|
||||
*/
|
||||
u64 of_dma_get_mask(struct device_node *np, char *name)
|
||||
{
|
||||
int bit_cnt = 0;
|
||||
|
||||
of_property_read_u32(np, name, &bit_cnt);
|
||||
|
||||
if (bit_cnt)
|
||||
return ((u64)1 << bit_cnt) - 1;
|
||||
else
|
||||
return -1;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_dma_get_mask);
|
||||
|
||||
/**
|
||||
* of_dma_request_slave_channel - Get the DMA slave channel
|
||||
* @np: device node to get DMA request from
|
||||
* @name: name of desired channel
|
||||
*
|
||||
* Returns pointer to appropriate DMA channel on success or an error pointer.
|
||||
*/
|
||||
struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
|
||||
const char *name)
|
||||
{
|
||||
struct of_phandle_args dma_spec;
|
||||
struct of_dma *ofdma;
|
||||
struct dma_chan *chan;
|
||||
int count, i;
|
||||
int ret_no_channel = -ENODEV;
|
||||
|
||||
if (!np || !name) {
|
||||
pr_err("%s: not enough information provided\n", __func__);
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
|
||||
count = of_property_count_strings(np, "dma-names");
|
||||
if (count < 0) {
|
||||
pr_err("%s: dma-names property of node '%s' missing or empty\n",
|
||||
__func__, np->full_name);
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
if (of_dma_match_channel(np, name, i, &dma_spec))
|
||||
continue;
|
||||
|
||||
mutex_lock(&of_dma_lock);
|
||||
ofdma = of_dma_find_controller(&dma_spec);
|
||||
|
||||
if (ofdma) {
|
||||
chan = ofdma->of_dma_xlate(&dma_spec, ofdma);
|
||||
} else {
|
||||
ret_no_channel = -EPROBE_DEFER;
|
||||
chan = NULL;
|
||||
}
|
||||
|
||||
mutex_unlock(&of_dma_lock);
|
||||
|
||||
of_node_put(dma_spec.np);
|
||||
|
||||
if (chan)
|
||||
return chan;
|
||||
}
|
||||
|
||||
return ERR_PTR(ret_no_channel);
|
||||
}
|
||||
|
||||
/**
|
||||
* of_dma_simple_xlate - Simple DMA engine translation function
|
||||
* @dma_spec: pointer to DMA specifier as found in the device tree
|
||||
* @of_dma: pointer to DMA controller data
|
||||
*
|
||||
* A simple translation function for devices that use a 32-bit value for the
|
||||
* filter_param when calling the DMA engine dma_request_channel() function.
|
||||
* Note that this translation function requires that #dma-cells is equal to 1
|
||||
* and the argument of the dma specifier is the 32-bit filter_param. Returns
|
||||
* pointer to appropriate dma channel on success or NULL on error.
|
||||
*/
|
||||
struct dma_chan *of_dma_simple_xlate(struct of_phandle_args *dma_spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
int count = dma_spec->args_count;
|
||||
struct of_dma_filter_info *info = ofdma->of_dma_data;
|
||||
|
||||
if (!info || !info->filter_fn)
|
||||
return NULL;
|
||||
|
||||
if (count != 1)
|
||||
return NULL;
|
||||
|
||||
return dma_request_channel(info->dma_cap, info->filter_fn,
|
||||
&dma_spec->args[0]);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_dma_simple_xlate);
|
||||
|
||||
/**
|
||||
* of_dma_xlate_by_chan_id - Translate dt property to DMA channel by channel id
|
||||
* @dma_spec: pointer to DMA specifier as found in the device tree
|
||||
* @of_dma: pointer to DMA controller data
|
||||
*
|
||||
* This function can be used as the of xlate callback for DMA driver which wants
|
||||
* to match the channel based on the channel id. When using this xlate function
|
||||
* the #dma-cells propety of the DMA controller dt node needs to be set to 1.
|
||||
* The data parameter of of_dma_controller_register must be a pointer to the
|
||||
* dma_device struct the function should match upon.
|
||||
*
|
||||
* Returns pointer to appropriate dma channel on success or NULL on error.
|
||||
*/
|
||||
struct dma_chan *of_dma_xlate_by_chan_id(struct of_phandle_args *dma_spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
struct dma_device *dev = ofdma->of_dma_data;
|
||||
struct dma_chan *chan, *candidate = NULL;
|
||||
|
||||
if (!dev || dma_spec->args_count != 1)
|
||||
return NULL;
|
||||
|
||||
list_for_each_entry(chan, &dev->channels, device_node)
|
||||
if (chan->chan_id == dma_spec->args[0]) {
|
||||
candidate = chan;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!candidate)
|
||||
return NULL;
|
||||
|
||||
return dma_get_slave_channel(candidate);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_dma_xlate_by_chan_id);
|
||||
1268
drivers/dma/omap-dma.c
Normal file
1268
drivers/dma/omap-dma.c
Normal file
File diff suppressed because it is too large
Load diff
1033
drivers/dma/pch_dma.c
Normal file
1033
drivers/dma/pch_dma.c
Normal file
File diff suppressed because it is too large
Load diff
3108
drivers/dma/pl330.c
Normal file
3108
drivers/dma/pl330.c
Normal file
File diff suppressed because it is too large
Load diff
1
drivers/dma/ppc4xx/Makefile
Normal file
1
drivers/dma/ppc4xx/Makefile
Normal file
|
|
@ -0,0 +1 @@
|
|||
obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += adma.o
|
||||
4654
drivers/dma/ppc4xx/adma.c
Normal file
4654
drivers/dma/ppc4xx/adma.c
Normal file
File diff suppressed because it is too large
Load diff
193
drivers/dma/ppc4xx/adma.h
Normal file
193
drivers/dma/ppc4xx/adma.h
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* 2006-2009 (C) DENX Software Engineering.
|
||||
*
|
||||
* Author: Yuri Tikhonov <yur@emcraft.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of
|
||||
* any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef _PPC440SPE_ADMA_H
|
||||
#define _PPC440SPE_ADMA_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include "dma.h"
|
||||
#include "xor.h"
|
||||
|
||||
#define to_ppc440spe_adma_chan(chan) \
|
||||
container_of(chan, struct ppc440spe_adma_chan, common)
|
||||
#define to_ppc440spe_adma_device(dev) \
|
||||
container_of(dev, struct ppc440spe_adma_device, common)
|
||||
#define tx_to_ppc440spe_adma_slot(tx) \
|
||||
container_of(tx, struct ppc440spe_adma_desc_slot, async_tx)
|
||||
|
||||
/* Default polynomial (for 440SP is only available) */
|
||||
#define PPC440SPE_DEFAULT_POLY 0x4d
|
||||
|
||||
#define PPC440SPE_ADMA_ENGINES_NUM (XOR_ENGINES_NUM + DMA_ENGINES_NUM)
|
||||
|
||||
#define PPC440SPE_ADMA_WATCHDOG_MSEC 3
|
||||
#define PPC440SPE_ADMA_THRESHOLD 1
|
||||
|
||||
#define PPC440SPE_DMA0_ID 0
|
||||
#define PPC440SPE_DMA1_ID 1
|
||||
#define PPC440SPE_XOR_ID 2
|
||||
|
||||
#define PPC440SPE_ADMA_DMA_MAX_BYTE_COUNT 0xFFFFFFUL
|
||||
/* this is the XOR_CBBCR width */
|
||||
#define PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT (1 << 31)
|
||||
#define PPC440SPE_ADMA_ZERO_SUM_MAX_BYTE_COUNT PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT
|
||||
|
||||
#define PPC440SPE_RXOR_RUN 0
|
||||
|
||||
#define MQ0_CF2H_RXOR_BS_MASK 0x1FF
|
||||
|
||||
#undef ADMA_LL_DEBUG
|
||||
|
||||
/**
|
||||
* struct ppc440spe_adma_device - internal representation of an ADMA device
|
||||
* @dev: device
|
||||
* @dma_reg: base for DMAx register access
|
||||
* @xor_reg: base for XOR register access
|
||||
* @i2o_reg: base for I2O register access
|
||||
* @id: HW ADMA Device selector
|
||||
* @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
|
||||
* @dma_desc_pool: base of DMA descriptor region (DMA address)
|
||||
* @pool_size: size of the pool
|
||||
* @irq: DMAx or XOR irq number
|
||||
* @err_irq: DMAx error irq number
|
||||
* @common: embedded struct dma_device
|
||||
*/
|
||||
struct ppc440spe_adma_device {
|
||||
struct device *dev;
|
||||
struct dma_regs __iomem *dma_reg;
|
||||
struct xor_regs __iomem *xor_reg;
|
||||
struct i2o_regs __iomem *i2o_reg;
|
||||
int id;
|
||||
void *dma_desc_pool_virt;
|
||||
dma_addr_t dma_desc_pool;
|
||||
size_t pool_size;
|
||||
int irq;
|
||||
int err_irq;
|
||||
struct dma_device common;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ppc440spe_adma_chan - internal representation of an ADMA channel
|
||||
* @lock: serializes enqueue/dequeue operations to the slot pool
|
||||
* @device: parent device
|
||||
* @chain: device chain view of the descriptors
|
||||
* @common: common dmaengine channel object members
|
||||
* @all_slots: complete domain of slots usable by the channel
|
||||
* @pending: allows batching of hardware operations
|
||||
* @slots_allocated: records the actual size of the descriptor slot pool
|
||||
* @hw_chain_inited: h/w descriptor chain initialization flag
|
||||
* @irq_tasklet: bottom half where ppc440spe_adma_slot_cleanup runs
|
||||
* @needs_unmap: if buffers should not be unmapped upon final processing
|
||||
* @pdest_page: P destination page for async validate operation
|
||||
* @qdest_page: Q destination page for async validate operation
|
||||
* @pdest: P dma addr for async validate operation
|
||||
* @qdest: Q dma addr for async validate operation
|
||||
*/
|
||||
struct ppc440spe_adma_chan {
|
||||
spinlock_t lock;
|
||||
struct ppc440spe_adma_device *device;
|
||||
struct list_head chain;
|
||||
struct dma_chan common;
|
||||
struct list_head all_slots;
|
||||
struct ppc440spe_adma_desc_slot *last_used;
|
||||
int pending;
|
||||
int slots_allocated;
|
||||
int hw_chain_inited;
|
||||
struct tasklet_struct irq_tasklet;
|
||||
u8 needs_unmap;
|
||||
struct page *pdest_page;
|
||||
struct page *qdest_page;
|
||||
dma_addr_t pdest;
|
||||
dma_addr_t qdest;
|
||||
};
|
||||
|
||||
struct ppc440spe_rxor {
|
||||
u32 addrl;
|
||||
u32 addrh;
|
||||
int len;
|
||||
int xor_count;
|
||||
int addr_count;
|
||||
int desc_count;
|
||||
int state;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ppc440spe_adma_desc_slot - PPC440SPE-ADMA software descriptor
|
||||
* @phys: hardware address of the hardware descriptor chain
|
||||
* @group_head: first operation in a transaction
|
||||
* @hw_next: pointer to the next descriptor in chain
|
||||
* @async_tx: support for the async_tx api
|
||||
* @slot_node: node on the iop_adma_chan.all_slots list
|
||||
* @chain_node: node on the op_adma_chan.chain list
|
||||
* @group_list: list of slots that make up a multi-descriptor transaction
|
||||
* for example transfer lengths larger than the supported hw max
|
||||
* @unmap_len: transaction bytecount
|
||||
* @hw_desc: virtual address of the hardware descriptor chain
|
||||
* @stride: currently chained or not
|
||||
* @idx: pool index
|
||||
* @slot_cnt: total slots used in an transaction (group of operations)
|
||||
* @src_cnt: number of sources set in this descriptor
|
||||
* @dst_cnt: number of destinations set in the descriptor
|
||||
* @slots_per_op: number of slots per operation
|
||||
* @descs_per_op: number of slot per P/Q operation see comment
|
||||
* for ppc440spe_prep_dma_pqxor function
|
||||
* @flags: desc state/type
|
||||
* @reverse_flags: 1 if a corresponding rxor address uses reversed address order
|
||||
* @xor_check_result: result of zero sum
|
||||
* @crc32_result: result crc calculation
|
||||
*/
|
||||
struct ppc440spe_adma_desc_slot {
|
||||
dma_addr_t phys;
|
||||
struct ppc440spe_adma_desc_slot *group_head;
|
||||
struct ppc440spe_adma_desc_slot *hw_next;
|
||||
struct dma_async_tx_descriptor async_tx;
|
||||
struct list_head slot_node;
|
||||
struct list_head chain_node; /* node in channel ops list */
|
||||
struct list_head group_list; /* list */
|
||||
unsigned int unmap_len;
|
||||
void *hw_desc;
|
||||
u16 stride;
|
||||
u16 idx;
|
||||
u16 slot_cnt;
|
||||
u8 src_cnt;
|
||||
u8 dst_cnt;
|
||||
u8 slots_per_op;
|
||||
u8 descs_per_op;
|
||||
unsigned long flags;
|
||||
unsigned long reverse_flags[8];
|
||||
|
||||
#define PPC440SPE_DESC_INT 0 /* generate interrupt on complete */
|
||||
#define PPC440SPE_ZERO_P 1 /* clear P destionaion */
|
||||
#define PPC440SPE_ZERO_Q 2 /* clear Q destination */
|
||||
#define PPC440SPE_COHERENT 3 /* src/dst are coherent */
|
||||
|
||||
#define PPC440SPE_DESC_WXOR 4 /* WXORs are in chain */
|
||||
#define PPC440SPE_DESC_RXOR 5 /* RXOR is in chain */
|
||||
|
||||
#define PPC440SPE_DESC_RXOR123 8 /* CDB for RXOR123 operation */
|
||||
#define PPC440SPE_DESC_RXOR124 9 /* CDB for RXOR124 operation */
|
||||
#define PPC440SPE_DESC_RXOR125 10 /* CDB for RXOR125 operation */
|
||||
#define PPC440SPE_DESC_RXOR12 11 /* CDB for RXOR12 operation */
|
||||
#define PPC440SPE_DESC_RXOR_REV 12 /* CDB has srcs in reversed order */
|
||||
|
||||
#define PPC440SPE_DESC_PCHECK 13
|
||||
#define PPC440SPE_DESC_QCHECK 14
|
||||
|
||||
#define PPC440SPE_DESC_RXOR_MSK 0x3
|
||||
|
||||
struct ppc440spe_rxor rxor_cursor;
|
||||
|
||||
union {
|
||||
u32 *xor_check_result;
|
||||
u32 *crc32_result;
|
||||
};
|
||||
};
|
||||
|
||||
#endif /* _PPC440SPE_ADMA_H */
|
||||
223
drivers/dma/ppc4xx/dma.h
Normal file
223
drivers/dma/ppc4xx/dma.h
Normal file
|
|
@ -0,0 +1,223 @@
|
|||
/*
|
||||
* 440SPe's DMA engines support header file
|
||||
*
|
||||
* 2006-2009 (C) DENX Software Engineering.
|
||||
*
|
||||
* Author: Yuri Tikhonov <yur@emcraft.com>
|
||||
*
|
||||
* This file is licensed under the term of the GNU General Public License
|
||||
* version 2. The program licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef _PPC440SPE_DMA_H
|
||||
#define _PPC440SPE_DMA_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/* Number of elements in the array with statical CDBs */
|
||||
#define MAX_STAT_DMA_CDBS 16
|
||||
/* Number of DMA engines available on the contoller */
|
||||
#define DMA_ENGINES_NUM 2
|
||||
|
||||
/* Maximum h/w supported number of destinations */
|
||||
#define DMA_DEST_MAX_NUM 2
|
||||
|
||||
/* FIFO's params */
|
||||
#define DMA0_FIFO_SIZE 0x1000
|
||||
#define DMA1_FIFO_SIZE 0x1000
|
||||
#define DMA_FIFO_ENABLE (1<<12)
|
||||
|
||||
/* DMA Configuration Register. Data Transfer Engine PLB Priority: */
|
||||
#define DMA_CFG_DXEPR_LP (0<<26)
|
||||
#define DMA_CFG_DXEPR_HP (3<<26)
|
||||
#define DMA_CFG_DXEPR_HHP (2<<26)
|
||||
#define DMA_CFG_DXEPR_HHHP (1<<26)
|
||||
|
||||
/* DMA Configuration Register. DMA FIFO Manager PLB Priority: */
|
||||
#define DMA_CFG_DFMPP_LP (0<<23)
|
||||
#define DMA_CFG_DFMPP_HP (3<<23)
|
||||
#define DMA_CFG_DFMPP_HHP (2<<23)
|
||||
#define DMA_CFG_DFMPP_HHHP (1<<23)
|
||||
|
||||
/* DMA Configuration Register. Force 64-byte Alignment */
|
||||
#define DMA_CFG_FALGN (1 << 19)
|
||||
|
||||
/*UIC0:*/
|
||||
#define D0CPF_INT (1<<12)
|
||||
#define D0CSF_INT (1<<11)
|
||||
#define D1CPF_INT (1<<10)
|
||||
#define D1CSF_INT (1<<9)
|
||||
/*UIC1:*/
|
||||
#define DMAE_INT (1<<9)
|
||||
|
||||
/* I2O IOP Interrupt Mask Register */
|
||||
#define I2O_IOPIM_P0SNE (1<<3)
|
||||
#define I2O_IOPIM_P0EM (1<<5)
|
||||
#define I2O_IOPIM_P1SNE (1<<6)
|
||||
#define I2O_IOPIM_P1EM (1<<8)
|
||||
|
||||
/* DMA CDB fields */
|
||||
#define DMA_CDB_MSK (0xF)
|
||||
#define DMA_CDB_64B_ADDR (1<<2)
|
||||
#define DMA_CDB_NO_INT (1<<3)
|
||||
#define DMA_CDB_STATUS_MSK (0x3)
|
||||
#define DMA_CDB_ADDR_MSK (0xFFFFFFF0)
|
||||
|
||||
/* DMA CDB OpCodes */
|
||||
#define DMA_CDB_OPC_NO_OP (0x00)
|
||||
#define DMA_CDB_OPC_MV_SG1_SG2 (0x01)
|
||||
#define DMA_CDB_OPC_MULTICAST (0x05)
|
||||
#define DMA_CDB_OPC_DFILL128 (0x24)
|
||||
#define DMA_CDB_OPC_DCHECK128 (0x23)
|
||||
|
||||
#define DMA_CUED_XOR_BASE (0x10000000)
|
||||
#define DMA_CUED_XOR_HB (0x00000008)
|
||||
|
||||
#ifdef CONFIG_440SP
|
||||
#define DMA_CUED_MULT1_OFF 0
|
||||
#define DMA_CUED_MULT2_OFF 8
|
||||
#define DMA_CUED_MULT3_OFF 16
|
||||
#define DMA_CUED_REGION_OFF 24
|
||||
#define DMA_CUED_XOR_WIN_MSK (0xFC000000)
|
||||
#else
|
||||
#define DMA_CUED_MULT1_OFF 2
|
||||
#define DMA_CUED_MULT2_OFF 10
|
||||
#define DMA_CUED_MULT3_OFF 18
|
||||
#define DMA_CUED_REGION_OFF 26
|
||||
#define DMA_CUED_XOR_WIN_MSK (0xF0000000)
|
||||
#endif
|
||||
|
||||
#define DMA_CUED_REGION_MSK 0x3
|
||||
#define DMA_RXOR123 0x0
|
||||
#define DMA_RXOR124 0x1
|
||||
#define DMA_RXOR125 0x2
|
||||
#define DMA_RXOR12 0x3
|
||||
|
||||
/* S/G addresses */
|
||||
#define DMA_CDB_SG_SRC 1
|
||||
#define DMA_CDB_SG_DST1 2
|
||||
#define DMA_CDB_SG_DST2 3
|
||||
|
||||
/*
|
||||
* DMAx engines Command Descriptor Block Type
|
||||
*/
|
||||
struct dma_cdb {
|
||||
/*
|
||||
* Basic CDB structure (Table 20-17, p.499, 440spe_um_1_22.pdf)
|
||||
*/
|
||||
u8 pad0[2]; /* reserved */
|
||||
u8 attr; /* attributes */
|
||||
u8 opc; /* opcode */
|
||||
u32 sg1u; /* upper SG1 address */
|
||||
u32 sg1l; /* lower SG1 address */
|
||||
u32 cnt; /* SG count, 3B used */
|
||||
u32 sg2u; /* upper SG2 address */
|
||||
u32 sg2l; /* lower SG2 address */
|
||||
u32 sg3u; /* upper SG3 address */
|
||||
u32 sg3l; /* lower SG3 address */
|
||||
};
|
||||
|
||||
/*
|
||||
* DMAx hardware registers (p.515 in 440SPe UM 1.22)
|
||||
*/
|
||||
struct dma_regs {
|
||||
u32 cpfpl;
|
||||
u32 cpfph;
|
||||
u32 csfpl;
|
||||
u32 csfph;
|
||||
u32 dsts;
|
||||
u32 cfg;
|
||||
u8 pad0[0x8];
|
||||
u16 cpfhp;
|
||||
u16 cpftp;
|
||||
u16 csfhp;
|
||||
u16 csftp;
|
||||
u8 pad1[0x8];
|
||||
u32 acpl;
|
||||
u32 acph;
|
||||
u32 s1bpl;
|
||||
u32 s1bph;
|
||||
u32 s2bpl;
|
||||
u32 s2bph;
|
||||
u32 s3bpl;
|
||||
u32 s3bph;
|
||||
u8 pad2[0x10];
|
||||
u32 earl;
|
||||
u32 earh;
|
||||
u8 pad3[0x8];
|
||||
u32 seat;
|
||||
u32 sead;
|
||||
u32 op;
|
||||
u32 fsiz;
|
||||
};
|
||||
|
||||
/*
|
||||
* I2O hardware registers (p.528 in 440SPe UM 1.22)
|
||||
*/
|
||||
struct i2o_regs {
|
||||
u32 ists;
|
||||
u32 iseat;
|
||||
u32 isead;
|
||||
u8 pad0[0x14];
|
||||
u32 idbel;
|
||||
u8 pad1[0xc];
|
||||
u32 ihis;
|
||||
u32 ihim;
|
||||
u8 pad2[0x8];
|
||||
u32 ihiq;
|
||||
u32 ihoq;
|
||||
u8 pad3[0x8];
|
||||
u32 iopis;
|
||||
u32 iopim;
|
||||
u32 iopiq;
|
||||
u8 iopoq;
|
||||
u8 pad4[3];
|
||||
u16 iiflh;
|
||||
u16 iiflt;
|
||||
u16 iiplh;
|
||||
u16 iiplt;
|
||||
u16 ioflh;
|
||||
u16 ioflt;
|
||||
u16 ioplh;
|
||||
u16 ioplt;
|
||||
u32 iidc;
|
||||
u32 ictl;
|
||||
u32 ifcpp;
|
||||
u8 pad5[0x4];
|
||||
u16 mfac0;
|
||||
u16 mfac1;
|
||||
u16 mfac2;
|
||||
u16 mfac3;
|
||||
u16 mfac4;
|
||||
u16 mfac5;
|
||||
u16 mfac6;
|
||||
u16 mfac7;
|
||||
u16 ifcfh;
|
||||
u16 ifcht;
|
||||
u8 pad6[0x4];
|
||||
u32 iifmc;
|
||||
u32 iodb;
|
||||
u32 iodbc;
|
||||
u32 ifbal;
|
||||
u32 ifbah;
|
||||
u32 ifsiz;
|
||||
u32 ispd0;
|
||||
u32 ispd1;
|
||||
u32 ispd2;
|
||||
u32 ispd3;
|
||||
u32 ihipl;
|
||||
u32 ihiph;
|
||||
u32 ihopl;
|
||||
u32 ihoph;
|
||||
u32 iiipl;
|
||||
u32 iiiph;
|
||||
u32 iiopl;
|
||||
u32 iioph;
|
||||
u32 ifcpl;
|
||||
u32 ifcph;
|
||||
u8 pad7[0x8];
|
||||
u32 iopt;
|
||||
};
|
||||
|
||||
#endif /* _PPC440SPE_DMA_H */
|
||||
110
drivers/dma/ppc4xx/xor.h
Normal file
110
drivers/dma/ppc4xx/xor.h
Normal file
|
|
@ -0,0 +1,110 @@
|
|||
/*
|
||||
* 440SPe's XOR engines support header file
|
||||
*
|
||||
* 2006-2009 (C) DENX Software Engineering.
|
||||
*
|
||||
* Author: Yuri Tikhonov <yur@emcraft.com>
|
||||
*
|
||||
* This file is licensed under the term of the GNU General Public License
|
||||
* version 2. The program licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef _PPC440SPE_XOR_H
|
||||
#define _PPC440SPE_XOR_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/* Number of XOR engines available on the contoller */
|
||||
#define XOR_ENGINES_NUM 1
|
||||
|
||||
/* Number of operands supported in the h/w */
|
||||
#define XOR_MAX_OPS 16
|
||||
|
||||
/*
|
||||
* XOR Command Block Control Register bits
|
||||
*/
|
||||
#define XOR_CBCR_LNK_BIT (1<<31) /* link present */
|
||||
#define XOR_CBCR_TGT_BIT (1<<30) /* target present */
|
||||
#define XOR_CBCR_CBCE_BIT (1<<29) /* command block compete enable */
|
||||
#define XOR_CBCR_RNZE_BIT (1<<28) /* result not zero enable */
|
||||
#define XOR_CBCR_XNOR_BIT (1<<15) /* XOR/XNOR */
|
||||
#define XOR_CDCR_OAC_MSK (0x7F) /* operand address count */
|
||||
|
||||
/*
|
||||
* XORCore Status Register bits
|
||||
*/
|
||||
#define XOR_SR_XCP_BIT (1<<31) /* core processing */
|
||||
#define XOR_SR_ICB_BIT (1<<17) /* invalid CB */
|
||||
#define XOR_SR_IC_BIT (1<<16) /* invalid command */
|
||||
#define XOR_SR_IPE_BIT (1<<15) /* internal parity error */
|
||||
#define XOR_SR_RNZ_BIT (1<<2) /* result not Zero */
|
||||
#define XOR_SR_CBC_BIT (1<<1) /* CB complete */
|
||||
#define XOR_SR_CBLC_BIT (1<<0) /* CB list complete */
|
||||
|
||||
/*
|
||||
* XORCore Control Set and Reset Register bits
|
||||
*/
|
||||
#define XOR_CRSR_XASR_BIT (1<<31) /* soft reset */
|
||||
#define XOR_CRSR_XAE_BIT (1<<30) /* enable */
|
||||
#define XOR_CRSR_RCBE_BIT (1<<29) /* refetch CB enable */
|
||||
#define XOR_CRSR_PAUS_BIT (1<<28) /* pause */
|
||||
#define XOR_CRSR_64BA_BIT (1<<27) /* 64/32 CB format */
|
||||
#define XOR_CRSR_CLP_BIT (1<<25) /* continue list processing */
|
||||
|
||||
/*
|
||||
* XORCore Interrupt Enable Register
|
||||
*/
|
||||
#define XOR_IE_ICBIE_BIT (1<<17) /* Invalid Command Block IRQ Enable */
|
||||
#define XOR_IE_ICIE_BIT (1<<16) /* Invalid Command IRQ Enable */
|
||||
#define XOR_IE_RPTIE_BIT (1<<14) /* Read PLB Timeout Error IRQ Enable */
|
||||
#define XOR_IE_CBCIE_BIT (1<<1) /* CB complete interrupt enable */
|
||||
#define XOR_IE_CBLCI_BIT (1<<0) /* CB list complete interrupt enable */
|
||||
|
||||
/*
|
||||
* XOR Accelerator engine Command Block Type
|
||||
*/
|
||||
struct xor_cb {
|
||||
/*
|
||||
* Basic 64-bit format XOR CB (Table 19-1, p.463, 440spe_um_1_22.pdf)
|
||||
*/
|
||||
u32 cbc; /* control */
|
||||
u32 cbbc; /* byte count */
|
||||
u32 cbs; /* status */
|
||||
u8 pad0[4]; /* reserved */
|
||||
u32 cbtah; /* target address high */
|
||||
u32 cbtal; /* target address low */
|
||||
u32 cblah; /* link address high */
|
||||
u32 cblal; /* link address low */
|
||||
struct {
|
||||
u32 h;
|
||||
u32 l;
|
||||
} __attribute__ ((packed)) ops[16];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/*
|
||||
* XOR hardware registers Table 19-3, UM 1.22
|
||||
*/
|
||||
struct xor_regs {
|
||||
u32 op_ar[16][2]; /* operand address[0]-high,[1]-low registers */
|
||||
u8 pad0[352]; /* reserved */
|
||||
u32 cbcr; /* CB control register */
|
||||
u32 cbbcr; /* CB byte count register */
|
||||
u32 cbsr; /* CB status register */
|
||||
u8 pad1[4]; /* reserved */
|
||||
u32 cbtahr; /* operand target address high register */
|
||||
u32 cbtalr; /* operand target address low register */
|
||||
u32 cblahr; /* CB link address high register */
|
||||
u32 cblalr; /* CB link address low register */
|
||||
u32 crsr; /* control set register */
|
||||
u32 crrr; /* control reset register */
|
||||
u32 ccbahr; /* current CB address high register */
|
||||
u32 ccbalr; /* current CB address low register */
|
||||
u32 plbr; /* PLB configuration register */
|
||||
u32 ier; /* interrupt enable register */
|
||||
u32 pecr; /* parity error count register */
|
||||
u32 sr; /* status register */
|
||||
u32 revidr; /* revision ID register */
|
||||
};
|
||||
|
||||
#endif /* _PPC440SPE_XOR_H */
|
||||
1127
drivers/dma/qcom_bam_dma.c
Normal file
1127
drivers/dma/qcom_bam_dma.c
Normal file
File diff suppressed because it is too large
Load diff
1430
drivers/dma/s3c24xx-dma.c
Normal file
1430
drivers/dma/s3c24xx-dma.c
Normal file
File diff suppressed because it is too large
Load diff
1101
drivers/dma/sa11x0-dma.c
Normal file
1101
drivers/dma/sa11x0-dma.c
Normal file
File diff suppressed because it is too large
Load diff
156
drivers/dma/samsung-dma.c
Normal file
156
drivers/dma/samsung-dma.c
Normal file
|
|
@ -0,0 +1,156 @@
|
|||
/* linux/arch/arm/plat-samsung/dma-ops.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Samsung DMA Operations
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/amba/pl330.h>
|
||||
#include <linux/scatterlist.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/dma/dma-pl330.h>
|
||||
|
||||
static unsigned long samsung_dmadev_request(enum dma_ch dma_ch,
|
||||
struct samsung_dma_req *param,
|
||||
struct device *dev, char *ch_name)
|
||||
{
|
||||
dma_cap_mask_t mask;
|
||||
unsigned long channel;
|
||||
|
||||
dma_cap_zero(mask);
|
||||
dma_cap_set(param->cap, mask);
|
||||
|
||||
if (dev->of_node)
|
||||
{
|
||||
channel = (unsigned long)dma_request_slave_channel(dev, ch_name);
|
||||
return channel;
|
||||
}
|
||||
else
|
||||
return (u64)dma_request_channel(mask, pl330_filter,
|
||||
(void *)dma_ch);
|
||||
}
|
||||
|
||||
static int samsung_dmadev_release(unsigned long ch, void *param)
|
||||
{
|
||||
dma_release_channel((struct dma_chan *)ch);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int samsung_dmadev_config(unsigned long ch,
|
||||
struct samsung_dma_config *param)
|
||||
{
|
||||
struct dma_chan *chan = (struct dma_chan *)ch;
|
||||
struct dma_slave_config slave_config;
|
||||
|
||||
if (param->direction == DMA_DEV_TO_MEM) {
|
||||
memset(&slave_config, 0, sizeof(struct dma_slave_config));
|
||||
slave_config.direction = param->direction;
|
||||
slave_config.src_addr = param->fifo;
|
||||
slave_config.src_addr_width = param->width;
|
||||
if (param->maxburst)
|
||||
slave_config.src_maxburst = param->maxburst;
|
||||
else
|
||||
slave_config.src_maxburst = 1;
|
||||
dmaengine_slave_config(chan, &slave_config);
|
||||
} else if (param->direction == DMA_MEM_TO_DEV) {
|
||||
memset(&slave_config, 0, sizeof(struct dma_slave_config));
|
||||
slave_config.direction = param->direction;
|
||||
slave_config.dst_addr = param->fifo;
|
||||
slave_config.dst_addr_width = param->width;
|
||||
if (param->maxburst)
|
||||
slave_config.dst_maxburst = param->maxburst;
|
||||
else
|
||||
slave_config.dst_maxburst = 1;
|
||||
dmaengine_slave_config(chan, &slave_config);
|
||||
} else {
|
||||
pr_warn("unsupported direction\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int samsung_dmadev_prepare(unsigned long ch,
|
||||
struct samsung_dma_prep *param)
|
||||
{
|
||||
struct scatterlist sg;
|
||||
struct dma_chan *chan = (struct dma_chan *)ch;
|
||||
struct dma_async_tx_descriptor *desc;
|
||||
|
||||
switch (param->cap) {
|
||||
case DMA_SLAVE:
|
||||
sg_init_table(&sg, 1);
|
||||
sg_dma_len(&sg) = param->len;
|
||||
sg_set_page(&sg, pfn_to_page(PFN_DOWN(param->buf)),
|
||||
param->len, offset_in_page(param->buf));
|
||||
sg_dma_address(&sg) = param->buf;
|
||||
|
||||
desc = dmaengine_prep_slave_sg(chan,
|
||||
&sg, 1, param->direction, DMA_PREP_INTERRUPT);
|
||||
break;
|
||||
case DMA_CYCLIC:
|
||||
desc = chan->device->device_prep_dma_cyclic(chan,
|
||||
param->buf, param->len, param->period,
|
||||
param->direction, true, ¶m->infiniteloop);
|
||||
break;
|
||||
default:
|
||||
dev_err(&chan->dev->device, "unsupported format\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
if (!desc) {
|
||||
dev_err(&chan->dev->device, "cannot prepare cyclic dma\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
desc->callback = param->fp;
|
||||
desc->callback_param = param->fp_param;
|
||||
|
||||
dmaengine_submit((struct dma_async_tx_descriptor *)desc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int samsung_dmadev_trigger(unsigned long ch)
|
||||
{
|
||||
dma_async_issue_pending((struct dma_chan *)ch);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int samsung_dmadev_getposition(unsigned long ch,
|
||||
dma_addr_t *src, dma_addr_t *dst)
|
||||
{
|
||||
return pl330_dma_getposition((struct dma_chan *)ch, src, dst);
|
||||
}
|
||||
|
||||
static inline int samsung_dmadev_flush(unsigned long ch)
|
||||
{
|
||||
return dmaengine_terminate_all((struct dma_chan *)ch);
|
||||
}
|
||||
|
||||
static struct samsung_dma_ops dmadev_ops = {
|
||||
.request = samsung_dmadev_request,
|
||||
.release = samsung_dmadev_release,
|
||||
.config = samsung_dmadev_config,
|
||||
.prepare = samsung_dmadev_prepare,
|
||||
.trigger = samsung_dmadev_trigger,
|
||||
.started = NULL,
|
||||
.getposition = samsung_dmadev_getposition,
|
||||
.flush = samsung_dmadev_flush,
|
||||
.stop = samsung_dmadev_flush,
|
||||
};
|
||||
|
||||
void *samsung_dmadev_get_ops(void)
|
||||
{
|
||||
return &dmadev_ops;
|
||||
}
|
||||
EXPORT_SYMBOL(samsung_dmadev_get_ops);
|
||||
54
drivers/dma/sh/Kconfig
Normal file
54
drivers/dma/sh/Kconfig
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
#
|
||||
# DMA engine configuration for sh
|
||||
#
|
||||
|
||||
#
|
||||
# DMA Engine Helpers
|
||||
#
|
||||
|
||||
config SH_DMAE_BASE
|
||||
bool "Renesas SuperH DMA Engine support"
|
||||
depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST
|
||||
depends on !SUPERH || SH_DMA
|
||||
depends on !SH_DMA_API
|
||||
default y
|
||||
select DMA_ENGINE
|
||||
help
|
||||
Enable support for the Renesas SuperH DMA controllers.
|
||||
|
||||
#
|
||||
# DMA Controllers
|
||||
#
|
||||
|
||||
config SH_DMAE
|
||||
tristate "Renesas SuperH DMAC support"
|
||||
depends on SH_DMAE_BASE
|
||||
help
|
||||
Enable support for the Renesas SuperH DMA controllers.
|
||||
|
||||
if SH_DMAE
|
||||
|
||||
config SH_DMAE_R8A73A4
|
||||
def_bool y
|
||||
depends on ARCH_R8A73A4
|
||||
depends on OF
|
||||
|
||||
endif
|
||||
|
||||
config SUDMAC
|
||||
tristate "Renesas SUDMAC support"
|
||||
depends on SH_DMAE_BASE
|
||||
help
|
||||
Enable support for the Renesas SUDMAC controllers.
|
||||
|
||||
config RCAR_HPB_DMAE
|
||||
tristate "Renesas R-Car HPB DMAC support"
|
||||
depends on SH_DMAE_BASE
|
||||
help
|
||||
Enable support for the Renesas R-Car series DMA controllers.
|
||||
|
||||
config RCAR_AUDMAC_PP
|
||||
tristate "Renesas R-Car Audio DMAC Peripheral Peripheral support"
|
||||
depends on SH_DMAE_BASE
|
||||
help
|
||||
Enable support for the Renesas R-Car Audio DMAC Peripheral Peripheral controllers.
|
||||
18
drivers/dma/sh/Makefile
Normal file
18
drivers/dma/sh/Makefile
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
#
|
||||
# DMA Engine Helpers
|
||||
#
|
||||
|
||||
obj-$(CONFIG_SH_DMAE_BASE) += shdma-base.o shdma-of.o
|
||||
|
||||
#
|
||||
# DMA Controllers
|
||||
#
|
||||
|
||||
shdma-y := shdmac.o
|
||||
shdma-$(CONFIG_SH_DMAE_R8A73A4) += shdma-r8a73a4.o
|
||||
shdma-objs := $(shdma-y)
|
||||
obj-$(CONFIG_SH_DMAE) += shdma.o
|
||||
|
||||
obj-$(CONFIG_SUDMAC) += sudmac.o
|
||||
obj-$(CONFIG_RCAR_HPB_DMAE) += rcar-hpbdma.o
|
||||
obj-$(CONFIG_RCAR_AUDMAC_PP) += rcar-audmapp.o
|
||||
379
drivers/dma/sh/rcar-audmapp.c
Normal file
379
drivers/dma/sh/rcar-audmapp.c
Normal file
|
|
@ -0,0 +1,379 @@
|
|||
/*
|
||||
* This is for Renesas R-Car Audio-DMAC-peri-peri.
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
* Copyright (C) 2014 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
*
|
||||
* based on the drivers/dma/sh/shdma.c
|
||||
*
|
||||
* Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
|
||||
* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
|
||||
* Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
#include <linux/delay.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/of_dma.h>
|
||||
#include <linux/platform_data/dma-rcar-audmapp.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/shdma-base.h>
|
||||
|
||||
/*
|
||||
* DMA register
|
||||
*/
|
||||
#define PDMASAR 0x00
|
||||
#define PDMADAR 0x04
|
||||
#define PDMACHCR 0x0c
|
||||
|
||||
/* PDMACHCR */
|
||||
#define PDMACHCR_DE (1 << 0)
|
||||
|
||||
#define AUDMAPP_MAX_CHANNELS 29
|
||||
|
||||
/* Default MEMCPY transfer size = 2^2 = 4 bytes */
|
||||
#define LOG2_DEFAULT_XFER_SIZE 2
|
||||
#define AUDMAPP_SLAVE_NUMBER 256
|
||||
#define AUDMAPP_LEN_MAX (16 * 1024 * 1024)
|
||||
|
||||
struct audmapp_chan {
|
||||
struct shdma_chan shdma_chan;
|
||||
void __iomem *base;
|
||||
dma_addr_t slave_addr;
|
||||
u32 chcr;
|
||||
};
|
||||
|
||||
struct audmapp_device {
|
||||
struct shdma_dev shdma_dev;
|
||||
struct audmapp_pdata *pdata;
|
||||
struct device *dev;
|
||||
void __iomem *chan_reg;
|
||||
};
|
||||
|
||||
struct audmapp_desc {
|
||||
struct shdma_desc shdma_desc;
|
||||
dma_addr_t src;
|
||||
dma_addr_t dst;
|
||||
};
|
||||
|
||||
#define to_shdma_chan(c) container_of(c, struct shdma_chan, dma_chan)
|
||||
|
||||
#define to_chan(chan) container_of(chan, struct audmapp_chan, shdma_chan)
|
||||
#define to_desc(sdesc) container_of(sdesc, struct audmapp_desc, shdma_desc)
|
||||
#define to_dev(chan) container_of(chan->shdma_chan.dma_chan.device, \
|
||||
struct audmapp_device, shdma_dev.dma_dev)
|
||||
|
||||
static void audmapp_write(struct audmapp_chan *auchan, u32 data, u32 reg)
|
||||
{
|
||||
struct audmapp_device *audev = to_dev(auchan);
|
||||
struct device *dev = audev->dev;
|
||||
|
||||
dev_dbg(dev, "w %p : %08x\n", auchan->base + reg, data);
|
||||
|
||||
iowrite32(data, auchan->base + reg);
|
||||
}
|
||||
|
||||
static u32 audmapp_read(struct audmapp_chan *auchan, u32 reg)
|
||||
{
|
||||
return ioread32(auchan->base + reg);
|
||||
}
|
||||
|
||||
static void audmapp_halt(struct shdma_chan *schan)
|
||||
{
|
||||
struct audmapp_chan *auchan = to_chan(schan);
|
||||
int i;
|
||||
|
||||
audmapp_write(auchan, 0, PDMACHCR);
|
||||
|
||||
for (i = 0; i < 1024; i++) {
|
||||
if (0 == audmapp_read(auchan, PDMACHCR))
|
||||
return;
|
||||
udelay(1);
|
||||
}
|
||||
}
|
||||
|
||||
static void audmapp_start_xfer(struct shdma_chan *schan,
|
||||
struct shdma_desc *sdesc)
|
||||
{
|
||||
struct audmapp_chan *auchan = to_chan(schan);
|
||||
struct audmapp_device *audev = to_dev(auchan);
|
||||
struct audmapp_desc *desc = to_desc(sdesc);
|
||||
struct device *dev = audev->dev;
|
||||
u32 chcr = auchan->chcr | PDMACHCR_DE;
|
||||
|
||||
dev_dbg(dev, "src/dst/chcr = %pad/%pad/%08x\n",
|
||||
&desc->src, &desc->dst, chcr);
|
||||
|
||||
audmapp_write(auchan, desc->src, PDMASAR);
|
||||
audmapp_write(auchan, desc->dst, PDMADAR);
|
||||
audmapp_write(auchan, chcr, PDMACHCR);
|
||||
}
|
||||
|
||||
static int audmapp_get_config(struct audmapp_chan *auchan, int slave_id,
|
||||
u32 *chcr, dma_addr_t *dst)
|
||||
{
|
||||
struct audmapp_device *audev = to_dev(auchan);
|
||||
struct audmapp_pdata *pdata = audev->pdata;
|
||||
struct audmapp_slave_config *cfg;
|
||||
int i;
|
||||
|
||||
*chcr = 0;
|
||||
*dst = 0;
|
||||
|
||||
if (!pdata) { /* DT */
|
||||
*chcr = ((u32)slave_id) << 16;
|
||||
auchan->shdma_chan.slave_id = (slave_id) >> 8;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* non-DT */
|
||||
|
||||
if (slave_id >= AUDMAPP_SLAVE_NUMBER)
|
||||
return -ENXIO;
|
||||
|
||||
for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
|
||||
if (cfg->slave_id == slave_id) {
|
||||
*chcr = cfg->chcr;
|
||||
*dst = cfg->dst;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
static int audmapp_set_slave(struct shdma_chan *schan, int slave_id,
|
||||
dma_addr_t slave_addr, bool try)
|
||||
{
|
||||
struct audmapp_chan *auchan = to_chan(schan);
|
||||
u32 chcr;
|
||||
dma_addr_t dst;
|
||||
int ret;
|
||||
|
||||
ret = audmapp_get_config(auchan, slave_id, &chcr, &dst);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (try)
|
||||
return 0;
|
||||
|
||||
auchan->chcr = chcr;
|
||||
auchan->slave_addr = slave_addr ? : dst;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int audmapp_desc_setup(struct shdma_chan *schan,
|
||||
struct shdma_desc *sdesc,
|
||||
dma_addr_t src, dma_addr_t dst, size_t *len)
|
||||
{
|
||||
struct audmapp_desc *desc = to_desc(sdesc);
|
||||
|
||||
if (*len > (size_t)AUDMAPP_LEN_MAX)
|
||||
*len = (size_t)AUDMAPP_LEN_MAX;
|
||||
|
||||
desc->src = src;
|
||||
desc->dst = dst;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void audmapp_setup_xfer(struct shdma_chan *schan,
|
||||
int slave_id)
|
||||
{
|
||||
}
|
||||
|
||||
static dma_addr_t audmapp_slave_addr(struct shdma_chan *schan)
|
||||
{
|
||||
struct audmapp_chan *auchan = to_chan(schan);
|
||||
|
||||
return auchan->slave_addr;
|
||||
}
|
||||
|
||||
static bool audmapp_channel_busy(struct shdma_chan *schan)
|
||||
{
|
||||
struct audmapp_chan *auchan = to_chan(schan);
|
||||
u32 chcr = audmapp_read(auchan, PDMACHCR);
|
||||
|
||||
return chcr & ~PDMACHCR_DE;
|
||||
}
|
||||
|
||||
static bool audmapp_desc_completed(struct shdma_chan *schan,
|
||||
struct shdma_desc *sdesc)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static struct shdma_desc *audmapp_embedded_desc(void *buf, int i)
|
||||
{
|
||||
return &((struct audmapp_desc *)buf)[i].shdma_desc;
|
||||
}
|
||||
|
||||
static const struct shdma_ops audmapp_shdma_ops = {
|
||||
.halt_channel = audmapp_halt,
|
||||
.desc_setup = audmapp_desc_setup,
|
||||
.set_slave = audmapp_set_slave,
|
||||
.start_xfer = audmapp_start_xfer,
|
||||
.embedded_desc = audmapp_embedded_desc,
|
||||
.setup_xfer = audmapp_setup_xfer,
|
||||
.slave_addr = audmapp_slave_addr,
|
||||
.channel_busy = audmapp_channel_busy,
|
||||
.desc_completed = audmapp_desc_completed,
|
||||
};
|
||||
|
||||
static int audmapp_chan_probe(struct platform_device *pdev,
|
||||
struct audmapp_device *audev, int id)
|
||||
{
|
||||
struct shdma_dev *sdev = &audev->shdma_dev;
|
||||
struct audmapp_chan *auchan;
|
||||
struct shdma_chan *schan;
|
||||
struct device *dev = audev->dev;
|
||||
|
||||
auchan = devm_kzalloc(dev, sizeof(*auchan), GFP_KERNEL);
|
||||
if (!auchan)
|
||||
return -ENOMEM;
|
||||
|
||||
schan = &auchan->shdma_chan;
|
||||
schan->max_xfer_len = AUDMAPP_LEN_MAX;
|
||||
|
||||
shdma_chan_probe(sdev, schan, id);
|
||||
|
||||
auchan->base = audev->chan_reg + 0x20 + (0x10 * id);
|
||||
dev_dbg(dev, "%02d : %p / %p", id, auchan->base, audev->chan_reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void audmapp_chan_remove(struct audmapp_device *audev)
|
||||
{
|
||||
struct dma_device *dma_dev = &audev->shdma_dev.dma_dev;
|
||||
struct shdma_chan *schan;
|
||||
int i;
|
||||
|
||||
shdma_for_each_chan(schan, &audev->shdma_dev, i) {
|
||||
BUG_ON(!schan);
|
||||
shdma_chan_remove(schan);
|
||||
}
|
||||
dma_dev->chancnt = 0;
|
||||
}
|
||||
|
||||
static struct dma_chan *audmapp_of_xlate(struct of_phandle_args *dma_spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
dma_cap_mask_t mask;
|
||||
struct dma_chan *chan;
|
||||
u32 chcr = dma_spec->args[0];
|
||||
|
||||
if (dma_spec->args_count != 1)
|
||||
return NULL;
|
||||
|
||||
dma_cap_zero(mask);
|
||||
dma_cap_set(DMA_SLAVE, mask);
|
||||
|
||||
chan = dma_request_channel(mask, shdma_chan_filter, NULL);
|
||||
if (chan)
|
||||
to_shdma_chan(chan)->hw_req = chcr;
|
||||
|
||||
return chan;
|
||||
}
|
||||
|
||||
static int audmapp_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct audmapp_pdata *pdata = pdev->dev.platform_data;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct audmapp_device *audev;
|
||||
struct shdma_dev *sdev;
|
||||
struct dma_device *dma_dev;
|
||||
struct resource *res;
|
||||
int err, i;
|
||||
|
||||
if (np)
|
||||
of_dma_controller_register(np, audmapp_of_xlate, pdev);
|
||||
else if (!pdata)
|
||||
return -ENODEV;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
audev = devm_kzalloc(&pdev->dev, sizeof(*audev), GFP_KERNEL);
|
||||
if (!audev)
|
||||
return -ENOMEM;
|
||||
|
||||
audev->dev = &pdev->dev;
|
||||
audev->pdata = pdata;
|
||||
audev->chan_reg = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(audev->chan_reg))
|
||||
return PTR_ERR(audev->chan_reg);
|
||||
|
||||
sdev = &audev->shdma_dev;
|
||||
sdev->ops = &audmapp_shdma_ops;
|
||||
sdev->desc_size = sizeof(struct audmapp_desc);
|
||||
|
||||
dma_dev = &sdev->dma_dev;
|
||||
dma_dev->copy_align = LOG2_DEFAULT_XFER_SIZE;
|
||||
dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
|
||||
|
||||
err = shdma_init(&pdev->dev, sdev, AUDMAPP_MAX_CHANNELS);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
platform_set_drvdata(pdev, audev);
|
||||
|
||||
/* Create DMA Channel */
|
||||
for (i = 0; i < AUDMAPP_MAX_CHANNELS; i++) {
|
||||
err = audmapp_chan_probe(pdev, audev, i);
|
||||
if (err)
|
||||
goto chan_probe_err;
|
||||
}
|
||||
|
||||
err = dma_async_device_register(dma_dev);
|
||||
if (err < 0)
|
||||
goto chan_probe_err;
|
||||
|
||||
return err;
|
||||
|
||||
chan_probe_err:
|
||||
audmapp_chan_remove(audev);
|
||||
shdma_cleanup(sdev);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int audmapp_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct audmapp_device *audev = platform_get_drvdata(pdev);
|
||||
struct dma_device *dma_dev = &audev->shdma_dev.dma_dev;
|
||||
|
||||
dma_async_device_unregister(dma_dev);
|
||||
|
||||
audmapp_chan_remove(audev);
|
||||
shdma_cleanup(&audev->shdma_dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id audmapp_of_match[] = {
|
||||
{ .compatible = "renesas,rcar-audmapp", },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver audmapp_driver = {
|
||||
.probe = audmapp_probe,
|
||||
.remove = audmapp_remove,
|
||||
.driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = "rcar-audmapp-engine",
|
||||
.of_match_table = audmapp_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(audmapp_driver);
|
||||
|
||||
MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
|
||||
MODULE_DESCRIPTION("Renesas R-Car Audio DMAC peri-peri driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
666
drivers/dma/sh/rcar-hpbdma.c
Normal file
666
drivers/dma/sh/rcar-hpbdma.c
Normal file
|
|
@ -0,0 +1,666 @@
|
|||
/*
|
||||
* Copyright (C) 2011-2013 Renesas Electronics Corporation
|
||||
* Copyright (C) 2013 Cogent Embedded, Inc.
|
||||
*
|
||||
* This file is based on the drivers/dma/sh/shdma.c
|
||||
*
|
||||
* Renesas SuperH DMA Engine support
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* - DMA of SuperH does not have Hardware DMA chain mode.
|
||||
* - max DMA size is 16MB.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_data/dma-rcar-hpbdma.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/shdma-base.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
/* DMA channel registers */
|
||||
#define HPB_DMAE_DSAR0 0x00
|
||||
#define HPB_DMAE_DDAR0 0x04
|
||||
#define HPB_DMAE_DTCR0 0x08
|
||||
#define HPB_DMAE_DSAR1 0x0C
|
||||
#define HPB_DMAE_DDAR1 0x10
|
||||
#define HPB_DMAE_DTCR1 0x14
|
||||
#define HPB_DMAE_DSASR 0x18
|
||||
#define HPB_DMAE_DDASR 0x1C
|
||||
#define HPB_DMAE_DTCSR 0x20
|
||||
#define HPB_DMAE_DPTR 0x24
|
||||
#define HPB_DMAE_DCR 0x28
|
||||
#define HPB_DMAE_DCMDR 0x2C
|
||||
#define HPB_DMAE_DSTPR 0x30
|
||||
#define HPB_DMAE_DSTSR 0x34
|
||||
#define HPB_DMAE_DDBGR 0x38
|
||||
#define HPB_DMAE_DDBGR2 0x3C
|
||||
#define HPB_DMAE_CHAN(n) (0x40 * (n))
|
||||
|
||||
/* DMA command register (DCMDR) bits */
|
||||
#define HPB_DMAE_DCMDR_BDOUT BIT(7)
|
||||
#define HPB_DMAE_DCMDR_DQSPD BIT(6)
|
||||
#define HPB_DMAE_DCMDR_DQSPC BIT(5)
|
||||
#define HPB_DMAE_DCMDR_DMSPD BIT(4)
|
||||
#define HPB_DMAE_DCMDR_DMSPC BIT(3)
|
||||
#define HPB_DMAE_DCMDR_DQEND BIT(2)
|
||||
#define HPB_DMAE_DCMDR_DNXT BIT(1)
|
||||
#define HPB_DMAE_DCMDR_DMEN BIT(0)
|
||||
|
||||
/* DMA forced stop register (DSTPR) bits */
|
||||
#define HPB_DMAE_DSTPR_DMSTP BIT(0)
|
||||
|
||||
/* DMA status register (DSTSR) bits */
|
||||
#define HPB_DMAE_DSTSR_DQSTS BIT(2)
|
||||
#define HPB_DMAE_DSTSR_DMSTS BIT(0)
|
||||
|
||||
/* DMA common registers */
|
||||
#define HPB_DMAE_DTIMR 0x00
|
||||
#define HPB_DMAE_DINTSR0 0x0C
|
||||
#define HPB_DMAE_DINTSR1 0x10
|
||||
#define HPB_DMAE_DINTCR0 0x14
|
||||
#define HPB_DMAE_DINTCR1 0x18
|
||||
#define HPB_DMAE_DINTMR0 0x1C
|
||||
#define HPB_DMAE_DINTMR1 0x20
|
||||
#define HPB_DMAE_DACTSR0 0x24
|
||||
#define HPB_DMAE_DACTSR1 0x28
|
||||
#define HPB_DMAE_HSRSTR(n) (0x40 + (n) * 4)
|
||||
#define HPB_DMAE_HPB_DMASPR(n) (0x140 + (n) * 4)
|
||||
#define HPB_DMAE_HPB_DMLVLR0 0x160
|
||||
#define HPB_DMAE_HPB_DMLVLR1 0x164
|
||||
#define HPB_DMAE_HPB_DMSHPT0 0x168
|
||||
#define HPB_DMAE_HPB_DMSHPT1 0x16C
|
||||
|
||||
#define HPB_DMA_SLAVE_NUMBER 256
|
||||
#define HPB_DMA_TCR_MAX 0x01000000 /* 16 MiB */
|
||||
|
||||
struct hpb_dmae_chan {
|
||||
struct shdma_chan shdma_chan;
|
||||
int xfer_mode; /* DMA transfer mode */
|
||||
#define XFER_SINGLE 1
|
||||
#define XFER_DOUBLE 2
|
||||
unsigned plane_idx; /* current DMA information set */
|
||||
bool first_desc; /* first/next transfer */
|
||||
int xmit_shift; /* log_2(bytes_per_xfer) */
|
||||
void __iomem *base;
|
||||
const struct hpb_dmae_slave_config *cfg;
|
||||
char dev_id[16]; /* unique name per DMAC of channel */
|
||||
dma_addr_t slave_addr;
|
||||
};
|
||||
|
||||
struct hpb_dmae_device {
|
||||
struct shdma_dev shdma_dev;
|
||||
spinlock_t reg_lock; /* comm_reg operation lock */
|
||||
struct hpb_dmae_pdata *pdata;
|
||||
void __iomem *chan_reg;
|
||||
void __iomem *comm_reg;
|
||||
void __iomem *reset_reg;
|
||||
void __iomem *mode_reg;
|
||||
};
|
||||
|
||||
struct hpb_dmae_regs {
|
||||
u32 sar; /* SAR / source address */
|
||||
u32 dar; /* DAR / destination address */
|
||||
u32 tcr; /* TCR / transfer count */
|
||||
};
|
||||
|
||||
struct hpb_desc {
|
||||
struct shdma_desc shdma_desc;
|
||||
struct hpb_dmae_regs hw;
|
||||
unsigned plane_idx;
|
||||
};
|
||||
|
||||
#define to_chan(schan) container_of(schan, struct hpb_dmae_chan, shdma_chan)
|
||||
#define to_desc(sdesc) container_of(sdesc, struct hpb_desc, shdma_desc)
|
||||
#define to_dev(sc) container_of(sc->shdma_chan.dma_chan.device, \
|
||||
struct hpb_dmae_device, shdma_dev.dma_dev)
|
||||
|
||||
static void ch_reg_write(struct hpb_dmae_chan *hpb_dc, u32 data, u32 reg)
|
||||
{
|
||||
iowrite32(data, hpb_dc->base + reg);
|
||||
}
|
||||
|
||||
static u32 ch_reg_read(struct hpb_dmae_chan *hpb_dc, u32 reg)
|
||||
{
|
||||
return ioread32(hpb_dc->base + reg);
|
||||
}
|
||||
|
||||
static void dcmdr_write(struct hpb_dmae_device *hpbdev, u32 data)
|
||||
{
|
||||
iowrite32(data, hpbdev->chan_reg + HPB_DMAE_DCMDR);
|
||||
}
|
||||
|
||||
static void hsrstr_write(struct hpb_dmae_device *hpbdev, u32 ch)
|
||||
{
|
||||
iowrite32(0x1, hpbdev->comm_reg + HPB_DMAE_HSRSTR(ch));
|
||||
}
|
||||
|
||||
static u32 dintsr_read(struct hpb_dmae_device *hpbdev, u32 ch)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
if (ch < 32)
|
||||
v = ioread32(hpbdev->comm_reg + HPB_DMAE_DINTSR0) >> ch;
|
||||
else
|
||||
v = ioread32(hpbdev->comm_reg + HPB_DMAE_DINTSR1) >> (ch - 32);
|
||||
return v & 0x1;
|
||||
}
|
||||
|
||||
static void dintcr_write(struct hpb_dmae_device *hpbdev, u32 ch)
|
||||
{
|
||||
if (ch < 32)
|
||||
iowrite32((0x1 << ch), hpbdev->comm_reg + HPB_DMAE_DINTCR0);
|
||||
else
|
||||
iowrite32((0x1 << (ch - 32)),
|
||||
hpbdev->comm_reg + HPB_DMAE_DINTCR1);
|
||||
}
|
||||
|
||||
static void asyncmdr_write(struct hpb_dmae_device *hpbdev, u32 data)
|
||||
{
|
||||
iowrite32(data, hpbdev->mode_reg);
|
||||
}
|
||||
|
||||
static u32 asyncmdr_read(struct hpb_dmae_device *hpbdev)
|
||||
{
|
||||
return ioread32(hpbdev->mode_reg);
|
||||
}
|
||||
|
||||
static void hpb_dmae_enable_int(struct hpb_dmae_device *hpbdev, u32 ch)
|
||||
{
|
||||
u32 intreg;
|
||||
|
||||
spin_lock_irq(&hpbdev->reg_lock);
|
||||
if (ch < 32) {
|
||||
intreg = ioread32(hpbdev->comm_reg + HPB_DMAE_DINTMR0);
|
||||
iowrite32(BIT(ch) | intreg,
|
||||
hpbdev->comm_reg + HPB_DMAE_DINTMR0);
|
||||
} else {
|
||||
intreg = ioread32(hpbdev->comm_reg + HPB_DMAE_DINTMR1);
|
||||
iowrite32(BIT(ch - 32) | intreg,
|
||||
hpbdev->comm_reg + HPB_DMAE_DINTMR1);
|
||||
}
|
||||
spin_unlock_irq(&hpbdev->reg_lock);
|
||||
}
|
||||
|
||||
static void hpb_dmae_async_reset(struct hpb_dmae_device *hpbdev, u32 data)
|
||||
{
|
||||
u32 rstr;
|
||||
int timeout = 10000; /* 100 ms */
|
||||
|
||||
spin_lock(&hpbdev->reg_lock);
|
||||
rstr = ioread32(hpbdev->reset_reg);
|
||||
rstr |= data;
|
||||
iowrite32(rstr, hpbdev->reset_reg);
|
||||
do {
|
||||
rstr = ioread32(hpbdev->reset_reg);
|
||||
if ((rstr & data) == data)
|
||||
break;
|
||||
udelay(10);
|
||||
} while (timeout--);
|
||||
|
||||
if (timeout < 0)
|
||||
dev_err(hpbdev->shdma_dev.dma_dev.dev,
|
||||
"%s timeout\n", __func__);
|
||||
|
||||
rstr &= ~data;
|
||||
iowrite32(rstr, hpbdev->reset_reg);
|
||||
spin_unlock(&hpbdev->reg_lock);
|
||||
}
|
||||
|
||||
static void hpb_dmae_set_async_mode(struct hpb_dmae_device *hpbdev,
|
||||
u32 mask, u32 data)
|
||||
{
|
||||
u32 mode;
|
||||
|
||||
spin_lock_irq(&hpbdev->reg_lock);
|
||||
mode = asyncmdr_read(hpbdev);
|
||||
mode &= ~mask;
|
||||
mode |= data;
|
||||
asyncmdr_write(hpbdev, mode);
|
||||
spin_unlock_irq(&hpbdev->reg_lock);
|
||||
}
|
||||
|
||||
static void hpb_dmae_ctl_stop(struct hpb_dmae_device *hpbdev)
|
||||
{
|
||||
dcmdr_write(hpbdev, HPB_DMAE_DCMDR_DQSPD);
|
||||
}
|
||||
|
||||
static void hpb_dmae_reset(struct hpb_dmae_device *hpbdev)
|
||||
{
|
||||
u32 ch;
|
||||
|
||||
for (ch = 0; ch < hpbdev->pdata->num_hw_channels; ch++)
|
||||
hsrstr_write(hpbdev, ch);
|
||||
}
|
||||
|
||||
static unsigned int calc_xmit_shift(struct hpb_dmae_chan *hpb_chan)
|
||||
{
|
||||
struct hpb_dmae_device *hpbdev = to_dev(hpb_chan);
|
||||
struct hpb_dmae_pdata *pdata = hpbdev->pdata;
|
||||
int width = ch_reg_read(hpb_chan, HPB_DMAE_DCR);
|
||||
int i;
|
||||
|
||||
switch (width & (HPB_DMAE_DCR_SPDS_MASK | HPB_DMAE_DCR_DPDS_MASK)) {
|
||||
case HPB_DMAE_DCR_SPDS_8BIT | HPB_DMAE_DCR_DPDS_8BIT:
|
||||
default:
|
||||
i = XMIT_SZ_8BIT;
|
||||
break;
|
||||
case HPB_DMAE_DCR_SPDS_16BIT | HPB_DMAE_DCR_DPDS_16BIT:
|
||||
i = XMIT_SZ_16BIT;
|
||||
break;
|
||||
case HPB_DMAE_DCR_SPDS_32BIT | HPB_DMAE_DCR_DPDS_32BIT:
|
||||
i = XMIT_SZ_32BIT;
|
||||
break;
|
||||
}
|
||||
return pdata->ts_shift[i];
|
||||
}
|
||||
|
||||
static void hpb_dmae_set_reg(struct hpb_dmae_chan *hpb_chan,
|
||||
struct hpb_dmae_regs *hw, unsigned plane)
|
||||
{
|
||||
ch_reg_write(hpb_chan, hw->sar,
|
||||
plane ? HPB_DMAE_DSAR1 : HPB_DMAE_DSAR0);
|
||||
ch_reg_write(hpb_chan, hw->dar,
|
||||
plane ? HPB_DMAE_DDAR1 : HPB_DMAE_DDAR0);
|
||||
ch_reg_write(hpb_chan, hw->tcr >> hpb_chan->xmit_shift,
|
||||
plane ? HPB_DMAE_DTCR1 : HPB_DMAE_DTCR0);
|
||||
}
|
||||
|
||||
static void hpb_dmae_start(struct hpb_dmae_chan *hpb_chan, bool next)
|
||||
{
|
||||
ch_reg_write(hpb_chan, (next ? HPB_DMAE_DCMDR_DNXT : 0) |
|
||||
HPB_DMAE_DCMDR_DMEN, HPB_DMAE_DCMDR);
|
||||
}
|
||||
|
||||
static void hpb_dmae_halt(struct shdma_chan *schan)
|
||||
{
|
||||
struct hpb_dmae_chan *chan = to_chan(schan);
|
||||
|
||||
ch_reg_write(chan, HPB_DMAE_DCMDR_DQEND, HPB_DMAE_DCMDR);
|
||||
ch_reg_write(chan, HPB_DMAE_DSTPR_DMSTP, HPB_DMAE_DSTPR);
|
||||
|
||||
chan->plane_idx = 0;
|
||||
chan->first_desc = true;
|
||||
}
|
||||
|
||||
static const struct hpb_dmae_slave_config *
|
||||
hpb_dmae_find_slave(struct hpb_dmae_chan *hpb_chan, int slave_id)
|
||||
{
|
||||
struct hpb_dmae_device *hpbdev = to_dev(hpb_chan);
|
||||
struct hpb_dmae_pdata *pdata = hpbdev->pdata;
|
||||
int i;
|
||||
|
||||
if (slave_id >= HPB_DMA_SLAVE_NUMBER)
|
||||
return NULL;
|
||||
|
||||
for (i = 0; i < pdata->num_slaves; i++)
|
||||
if (pdata->slaves[i].id == slave_id)
|
||||
return pdata->slaves + i;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void hpb_dmae_start_xfer(struct shdma_chan *schan,
|
||||
struct shdma_desc *sdesc)
|
||||
{
|
||||
struct hpb_dmae_chan *chan = to_chan(schan);
|
||||
struct hpb_dmae_device *hpbdev = to_dev(chan);
|
||||
struct hpb_desc *desc = to_desc(sdesc);
|
||||
|
||||
if (chan->cfg->flags & HPB_DMAE_SET_ASYNC_RESET)
|
||||
hpb_dmae_async_reset(hpbdev, chan->cfg->rstr);
|
||||
|
||||
desc->plane_idx = chan->plane_idx;
|
||||
hpb_dmae_set_reg(chan, &desc->hw, chan->plane_idx);
|
||||
hpb_dmae_start(chan, !chan->first_desc);
|
||||
|
||||
if (chan->xfer_mode == XFER_DOUBLE) {
|
||||
chan->plane_idx ^= 1;
|
||||
chan->first_desc = false;
|
||||
}
|
||||
}
|
||||
|
||||
static bool hpb_dmae_desc_completed(struct shdma_chan *schan,
|
||||
struct shdma_desc *sdesc)
|
||||
{
|
||||
/*
|
||||
* This is correct since we always have at most single
|
||||
* outstanding DMA transfer per channel, and by the time
|
||||
* we get completion interrupt the transfer is completed.
|
||||
* This will change if we ever use alternating DMA
|
||||
* information sets and submit two descriptors at once.
|
||||
*/
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool hpb_dmae_chan_irq(struct shdma_chan *schan, int irq)
|
||||
{
|
||||
struct hpb_dmae_chan *chan = to_chan(schan);
|
||||
struct hpb_dmae_device *hpbdev = to_dev(chan);
|
||||
int ch = chan->cfg->dma_ch;
|
||||
|
||||
/* Check Complete DMA Transfer */
|
||||
if (dintsr_read(hpbdev, ch)) {
|
||||
/* Clear Interrupt status */
|
||||
dintcr_write(hpbdev, ch);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
static int hpb_dmae_desc_setup(struct shdma_chan *schan,
|
||||
struct shdma_desc *sdesc,
|
||||
dma_addr_t src, dma_addr_t dst, size_t *len)
|
||||
{
|
||||
struct hpb_desc *desc = to_desc(sdesc);
|
||||
|
||||
if (*len > (size_t)HPB_DMA_TCR_MAX)
|
||||
*len = (size_t)HPB_DMA_TCR_MAX;
|
||||
|
||||
desc->hw.sar = src;
|
||||
desc->hw.dar = dst;
|
||||
desc->hw.tcr = *len;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static size_t hpb_dmae_get_partial(struct shdma_chan *schan,
|
||||
struct shdma_desc *sdesc)
|
||||
{
|
||||
struct hpb_desc *desc = to_desc(sdesc);
|
||||
struct hpb_dmae_chan *chan = to_chan(schan);
|
||||
u32 tcr = ch_reg_read(chan, desc->plane_idx ?
|
||||
HPB_DMAE_DTCR1 : HPB_DMAE_DTCR0);
|
||||
|
||||
return (desc->hw.tcr - tcr) << chan->xmit_shift;
|
||||
}
|
||||
|
||||
static bool hpb_dmae_channel_busy(struct shdma_chan *schan)
|
||||
{
|
||||
struct hpb_dmae_chan *chan = to_chan(schan);
|
||||
u32 dstsr = ch_reg_read(chan, HPB_DMAE_DSTSR);
|
||||
|
||||
if (chan->xfer_mode == XFER_DOUBLE)
|
||||
return dstsr & HPB_DMAE_DSTSR_DQSTS;
|
||||
else
|
||||
return dstsr & HPB_DMAE_DSTSR_DMSTS;
|
||||
}
|
||||
|
||||
static int
|
||||
hpb_dmae_alloc_chan_resources(struct hpb_dmae_chan *hpb_chan,
|
||||
const struct hpb_dmae_slave_config *cfg)
|
||||
{
|
||||
struct hpb_dmae_device *hpbdev = to_dev(hpb_chan);
|
||||
struct hpb_dmae_pdata *pdata = hpbdev->pdata;
|
||||
const struct hpb_dmae_channel *channel = pdata->channels;
|
||||
int slave_id = cfg->id;
|
||||
int i, err;
|
||||
|
||||
for (i = 0; i < pdata->num_channels; i++, channel++) {
|
||||
if (channel->s_id == slave_id) {
|
||||
struct device *dev = hpb_chan->shdma_chan.dev;
|
||||
|
||||
hpb_chan->base = hpbdev->chan_reg +
|
||||
HPB_DMAE_CHAN(cfg->dma_ch);
|
||||
|
||||
dev_dbg(dev, "Detected Slave device\n");
|
||||
dev_dbg(dev, " -- slave_id : 0x%x\n", slave_id);
|
||||
dev_dbg(dev, " -- cfg->dma_ch : %d\n", cfg->dma_ch);
|
||||
dev_dbg(dev, " -- channel->ch_irq: %d\n",
|
||||
channel->ch_irq);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
err = shdma_request_irq(&hpb_chan->shdma_chan, channel->ch_irq,
|
||||
IRQF_SHARED, hpb_chan->dev_id);
|
||||
if (err) {
|
||||
dev_err(hpb_chan->shdma_chan.dev,
|
||||
"DMA channel request_irq %d failed with error %d\n",
|
||||
channel->ch_irq, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
hpb_chan->plane_idx = 0;
|
||||
hpb_chan->first_desc = true;
|
||||
|
||||
if ((cfg->dcr & (HPB_DMAE_DCR_CT | HPB_DMAE_DCR_DIP)) == 0) {
|
||||
hpb_chan->xfer_mode = XFER_SINGLE;
|
||||
} else if ((cfg->dcr & (HPB_DMAE_DCR_CT | HPB_DMAE_DCR_DIP)) ==
|
||||
(HPB_DMAE_DCR_CT | HPB_DMAE_DCR_DIP)) {
|
||||
hpb_chan->xfer_mode = XFER_DOUBLE;
|
||||
} else {
|
||||
dev_err(hpb_chan->shdma_chan.dev, "DCR setting error");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (cfg->flags & HPB_DMAE_SET_ASYNC_MODE)
|
||||
hpb_dmae_set_async_mode(hpbdev, cfg->mdm, cfg->mdr);
|
||||
ch_reg_write(hpb_chan, cfg->dcr, HPB_DMAE_DCR);
|
||||
ch_reg_write(hpb_chan, cfg->port, HPB_DMAE_DPTR);
|
||||
hpb_chan->xmit_shift = calc_xmit_shift(hpb_chan);
|
||||
hpb_dmae_enable_int(hpbdev, cfg->dma_ch);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hpb_dmae_set_slave(struct shdma_chan *schan, int slave_id,
|
||||
dma_addr_t slave_addr, bool try)
|
||||
{
|
||||
struct hpb_dmae_chan *chan = to_chan(schan);
|
||||
const struct hpb_dmae_slave_config *sc =
|
||||
hpb_dmae_find_slave(chan, slave_id);
|
||||
|
||||
if (!sc)
|
||||
return -ENODEV;
|
||||
if (try)
|
||||
return 0;
|
||||
chan->cfg = sc;
|
||||
chan->slave_addr = slave_addr ? : sc->addr;
|
||||
return hpb_dmae_alloc_chan_resources(chan, sc);
|
||||
}
|
||||
|
||||
static void hpb_dmae_setup_xfer(struct shdma_chan *schan, int slave_id)
|
||||
{
|
||||
}
|
||||
|
||||
static dma_addr_t hpb_dmae_slave_addr(struct shdma_chan *schan)
|
||||
{
|
||||
struct hpb_dmae_chan *chan = to_chan(schan);
|
||||
|
||||
return chan->slave_addr;
|
||||
}
|
||||
|
||||
static struct shdma_desc *hpb_dmae_embedded_desc(void *buf, int i)
|
||||
{
|
||||
return &((struct hpb_desc *)buf)[i].shdma_desc;
|
||||
}
|
||||
|
||||
static const struct shdma_ops hpb_dmae_ops = {
|
||||
.desc_completed = hpb_dmae_desc_completed,
|
||||
.halt_channel = hpb_dmae_halt,
|
||||
.channel_busy = hpb_dmae_channel_busy,
|
||||
.slave_addr = hpb_dmae_slave_addr,
|
||||
.desc_setup = hpb_dmae_desc_setup,
|
||||
.set_slave = hpb_dmae_set_slave,
|
||||
.setup_xfer = hpb_dmae_setup_xfer,
|
||||
.start_xfer = hpb_dmae_start_xfer,
|
||||
.embedded_desc = hpb_dmae_embedded_desc,
|
||||
.chan_irq = hpb_dmae_chan_irq,
|
||||
.get_partial = hpb_dmae_get_partial,
|
||||
};
|
||||
|
||||
static int hpb_dmae_chan_probe(struct hpb_dmae_device *hpbdev, int id)
|
||||
{
|
||||
struct shdma_dev *sdev = &hpbdev->shdma_dev;
|
||||
struct platform_device *pdev =
|
||||
to_platform_device(hpbdev->shdma_dev.dma_dev.dev);
|
||||
struct hpb_dmae_chan *new_hpb_chan;
|
||||
struct shdma_chan *schan;
|
||||
|
||||
/* Alloc channel */
|
||||
new_hpb_chan = devm_kzalloc(&pdev->dev,
|
||||
sizeof(struct hpb_dmae_chan), GFP_KERNEL);
|
||||
if (!new_hpb_chan) {
|
||||
dev_err(hpbdev->shdma_dev.dma_dev.dev,
|
||||
"No free memory for allocating DMA channels!\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
schan = &new_hpb_chan->shdma_chan;
|
||||
schan->max_xfer_len = HPB_DMA_TCR_MAX;
|
||||
|
||||
shdma_chan_probe(sdev, schan, id);
|
||||
|
||||
if (pdev->id >= 0)
|
||||
snprintf(new_hpb_chan->dev_id, sizeof(new_hpb_chan->dev_id),
|
||||
"hpb-dmae%d.%d", pdev->id, id);
|
||||
else
|
||||
snprintf(new_hpb_chan->dev_id, sizeof(new_hpb_chan->dev_id),
|
||||
"hpb-dma.%d", id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hpb_dmae_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct hpb_dmae_pdata *pdata = pdev->dev.platform_data;
|
||||
struct hpb_dmae_device *hpbdev;
|
||||
struct dma_device *dma_dev;
|
||||
struct resource *chan, *comm, *rest, *mode, *irq_res;
|
||||
int err, i;
|
||||
|
||||
/* Get platform data */
|
||||
if (!pdata || !pdata->num_channels)
|
||||
return -ENODEV;
|
||||
|
||||
chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
comm = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
rest = platform_get_resource(pdev, IORESOURCE_MEM, 2);
|
||||
mode = platform_get_resource(pdev, IORESOURCE_MEM, 3);
|
||||
|
||||
irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!irq_res)
|
||||
return -ENODEV;
|
||||
|
||||
hpbdev = devm_kzalloc(&pdev->dev, sizeof(struct hpb_dmae_device),
|
||||
GFP_KERNEL);
|
||||
if (!hpbdev) {
|
||||
dev_err(&pdev->dev, "Not enough memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
hpbdev->chan_reg = devm_ioremap_resource(&pdev->dev, chan);
|
||||
if (IS_ERR(hpbdev->chan_reg))
|
||||
return PTR_ERR(hpbdev->chan_reg);
|
||||
|
||||
hpbdev->comm_reg = devm_ioremap_resource(&pdev->dev, comm);
|
||||
if (IS_ERR(hpbdev->comm_reg))
|
||||
return PTR_ERR(hpbdev->comm_reg);
|
||||
|
||||
hpbdev->reset_reg = devm_ioremap_resource(&pdev->dev, rest);
|
||||
if (IS_ERR(hpbdev->reset_reg))
|
||||
return PTR_ERR(hpbdev->reset_reg);
|
||||
|
||||
hpbdev->mode_reg = devm_ioremap_resource(&pdev->dev, mode);
|
||||
if (IS_ERR(hpbdev->mode_reg))
|
||||
return PTR_ERR(hpbdev->mode_reg);
|
||||
|
||||
dma_dev = &hpbdev->shdma_dev.dma_dev;
|
||||
|
||||
spin_lock_init(&hpbdev->reg_lock);
|
||||
|
||||
/* Platform data */
|
||||
hpbdev->pdata = pdata;
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
err = pm_runtime_get_sync(&pdev->dev);
|
||||
if (err < 0)
|
||||
dev_err(&pdev->dev, "%s(): GET = %d\n", __func__, err);
|
||||
|
||||
/* Reset DMA controller */
|
||||
hpb_dmae_reset(hpbdev);
|
||||
|
||||
pm_runtime_put(&pdev->dev);
|
||||
|
||||
dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
|
||||
dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
|
||||
|
||||
hpbdev->shdma_dev.ops = &hpb_dmae_ops;
|
||||
hpbdev->shdma_dev.desc_size = sizeof(struct hpb_desc);
|
||||
err = shdma_init(&pdev->dev, &hpbdev->shdma_dev, pdata->num_channels);
|
||||
if (err < 0)
|
||||
goto error;
|
||||
|
||||
/* Create DMA channels */
|
||||
for (i = 0; i < pdata->num_channels; i++)
|
||||
hpb_dmae_chan_probe(hpbdev, i);
|
||||
|
||||
platform_set_drvdata(pdev, hpbdev);
|
||||
err = dma_async_device_register(dma_dev);
|
||||
if (!err)
|
||||
return 0;
|
||||
|
||||
shdma_cleanup(&hpbdev->shdma_dev);
|
||||
error:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void hpb_dmae_chan_remove(struct hpb_dmae_device *hpbdev)
|
||||
{
|
||||
struct dma_device *dma_dev = &hpbdev->shdma_dev.dma_dev;
|
||||
struct shdma_chan *schan;
|
||||
int i;
|
||||
|
||||
shdma_for_each_chan(schan, &hpbdev->shdma_dev, i) {
|
||||
BUG_ON(!schan);
|
||||
|
||||
shdma_chan_remove(schan);
|
||||
}
|
||||
dma_dev->chancnt = 0;
|
||||
}
|
||||
|
||||
static int hpb_dmae_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct hpb_dmae_device *hpbdev = platform_get_drvdata(pdev);
|
||||
|
||||
dma_async_device_unregister(&hpbdev->shdma_dev.dma_dev);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
hpb_dmae_chan_remove(hpbdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void hpb_dmae_shutdown(struct platform_device *pdev)
|
||||
{
|
||||
struct hpb_dmae_device *hpbdev = platform_get_drvdata(pdev);
|
||||
hpb_dmae_ctl_stop(hpbdev);
|
||||
}
|
||||
|
||||
static struct platform_driver hpb_dmae_driver = {
|
||||
.probe = hpb_dmae_probe,
|
||||
.remove = hpb_dmae_remove,
|
||||
.shutdown = hpb_dmae_shutdown,
|
||||
.driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = "hpb-dma-engine",
|
||||
},
|
||||
};
|
||||
module_platform_driver(hpb_dmae_driver);
|
||||
|
||||
MODULE_AUTHOR("Max Filippov <max.filippov@cogentembedded.com>");
|
||||
MODULE_DESCRIPTION("Renesas HPB DMA Engine driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
51
drivers/dma/sh/shdma-arm.h
Normal file
51
drivers/dma/sh/shdma-arm.h
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* Renesas SuperH DMA Engine support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Electronics, Inc.
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify it under the
|
||||
* terms of version 2 the GNU General Public License as published by the Free
|
||||
* Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef SHDMA_ARM_H
|
||||
#define SHDMA_ARM_H
|
||||
|
||||
#include "shdma.h"
|
||||
|
||||
/* Transmit sizes and respective CHCR register values */
|
||||
enum {
|
||||
XMIT_SZ_8BIT = 0,
|
||||
XMIT_SZ_16BIT = 1,
|
||||
XMIT_SZ_32BIT = 2,
|
||||
XMIT_SZ_64BIT = 7,
|
||||
XMIT_SZ_128BIT = 3,
|
||||
XMIT_SZ_256BIT = 4,
|
||||
XMIT_SZ_512BIT = 5,
|
||||
};
|
||||
|
||||
/* log2(size / 8) - used to calculate number of transfers */
|
||||
#define SH_DMAE_TS_SHIFT { \
|
||||
[XMIT_SZ_8BIT] = 0, \
|
||||
[XMIT_SZ_16BIT] = 1, \
|
||||
[XMIT_SZ_32BIT] = 2, \
|
||||
[XMIT_SZ_64BIT] = 3, \
|
||||
[XMIT_SZ_128BIT] = 4, \
|
||||
[XMIT_SZ_256BIT] = 5, \
|
||||
[XMIT_SZ_512BIT] = 6, \
|
||||
}
|
||||
|
||||
#define TS_LOW_BIT 0x3 /* --xx */
|
||||
#define TS_HI_BIT 0xc /* xx-- */
|
||||
|
||||
#define TS_LOW_SHIFT (3)
|
||||
#define TS_HI_SHIFT (20 - 2) /* 2 bits for shifted low TS */
|
||||
|
||||
#define TS_INDEX2VAL(i) \
|
||||
((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\
|
||||
(((i) & TS_HI_BIT) << TS_HI_SHIFT))
|
||||
|
||||
#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL((xmit_sz)))
|
||||
#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL((xmit_sz)))
|
||||
|
||||
#endif
|
||||
1035
drivers/dma/sh/shdma-base.c
Normal file
1035
drivers/dma/sh/shdma-base.c
Normal file
File diff suppressed because it is too large
Load diff
80
drivers/dma/sh/shdma-of.c
Normal file
80
drivers/dma/sh/shdma-of.c
Normal file
|
|
@ -0,0 +1,80 @@
|
|||
/*
|
||||
* SHDMA Device Tree glue
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Electronics Inc.
|
||||
* Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_dma.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/shdma-base.h>
|
||||
|
||||
#define to_shdma_chan(c) container_of(c, struct shdma_chan, dma_chan)
|
||||
|
||||
static struct dma_chan *shdma_of_xlate(struct of_phandle_args *dma_spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
u32 id = dma_spec->args[0];
|
||||
dma_cap_mask_t mask;
|
||||
struct dma_chan *chan;
|
||||
|
||||
if (dma_spec->args_count != 1)
|
||||
return NULL;
|
||||
|
||||
dma_cap_zero(mask);
|
||||
/* Only slave DMA channels can be allocated via DT */
|
||||
dma_cap_set(DMA_SLAVE, mask);
|
||||
|
||||
chan = dma_request_channel(mask, shdma_chan_filter,
|
||||
(void *)(uintptr_t)id);
|
||||
if (chan)
|
||||
to_shdma_chan(chan)->hw_req = id;
|
||||
|
||||
return chan;
|
||||
}
|
||||
|
||||
static int shdma_of_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct of_dev_auxdata *lookup = dev_get_platdata(&pdev->dev);
|
||||
int ret;
|
||||
|
||||
ret = of_dma_controller_register(pdev->dev.of_node,
|
||||
shdma_of_xlate, pdev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = of_platform_populate(pdev->dev.of_node, NULL, lookup, &pdev->dev);
|
||||
if (ret < 0)
|
||||
of_dma_controller_free(pdev->dev.of_node);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id shdma_of_match[] = {
|
||||
{ .compatible = "renesas,shdma-mux", },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sh_dmae_of_match);
|
||||
|
||||
static struct platform_driver shdma_of = {
|
||||
.driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = "shdma-of",
|
||||
.of_match_table = shdma_of_match,
|
||||
},
|
||||
.probe = shdma_of_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(shdma_of);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("SH-DMA driver DT glue");
|
||||
MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
|
||||
77
drivers/dma/sh/shdma-r8a73a4.c
Normal file
77
drivers/dma/sh/shdma-r8a73a4.c
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* Renesas SuperH DMA Engine support for r8a73a4 (APE6) SoCs
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Electronics, Inc.
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify it under the
|
||||
* terms of version 2 the GNU General Public License as published by the Free
|
||||
* Software Foundation.
|
||||
*/
|
||||
#include <linux/sh_dma.h>
|
||||
|
||||
#include "shdma-arm.h"
|
||||
|
||||
const unsigned int dma_ts_shift[] = SH_DMAE_TS_SHIFT;
|
||||
|
||||
static const struct sh_dmae_slave_config dma_slaves[] = {
|
||||
{
|
||||
.chcr = CHCR_TX(XMIT_SZ_32BIT),
|
||||
.mid_rid = 0xd1, /* MMC0 Tx */
|
||||
}, {
|
||||
.chcr = CHCR_RX(XMIT_SZ_32BIT),
|
||||
.mid_rid = 0xd2, /* MMC0 Rx */
|
||||
}, {
|
||||
.chcr = CHCR_TX(XMIT_SZ_32BIT),
|
||||
.mid_rid = 0xe1, /* MMC1 Tx */
|
||||
}, {
|
||||
.chcr = CHCR_RX(XMIT_SZ_32BIT),
|
||||
.mid_rid = 0xe2, /* MMC1 Rx */
|
||||
},
|
||||
};
|
||||
|
||||
#define DMAE_CHANNEL(a, b) \
|
||||
{ \
|
||||
.offset = (a) - 0x20, \
|
||||
.dmars = (a) - 0x20 + 0x40, \
|
||||
.chclr_bit = (b), \
|
||||
.chclr_offset = 0x80 - 0x20, \
|
||||
}
|
||||
|
||||
static const struct sh_dmae_channel dma_channels[] = {
|
||||
DMAE_CHANNEL(0x8000, 0),
|
||||
DMAE_CHANNEL(0x8080, 1),
|
||||
DMAE_CHANNEL(0x8100, 2),
|
||||
DMAE_CHANNEL(0x8180, 3),
|
||||
DMAE_CHANNEL(0x8200, 4),
|
||||
DMAE_CHANNEL(0x8280, 5),
|
||||
DMAE_CHANNEL(0x8300, 6),
|
||||
DMAE_CHANNEL(0x8380, 7),
|
||||
DMAE_CHANNEL(0x8400, 8),
|
||||
DMAE_CHANNEL(0x8480, 9),
|
||||
DMAE_CHANNEL(0x8500, 10),
|
||||
DMAE_CHANNEL(0x8580, 11),
|
||||
DMAE_CHANNEL(0x8600, 12),
|
||||
DMAE_CHANNEL(0x8680, 13),
|
||||
DMAE_CHANNEL(0x8700, 14),
|
||||
DMAE_CHANNEL(0x8780, 15),
|
||||
DMAE_CHANNEL(0x8800, 16),
|
||||
DMAE_CHANNEL(0x8880, 17),
|
||||
DMAE_CHANNEL(0x8900, 18),
|
||||
DMAE_CHANNEL(0x8980, 19),
|
||||
};
|
||||
|
||||
const struct sh_dmae_pdata r8a73a4_dma_pdata = {
|
||||
.slave = dma_slaves,
|
||||
.slave_num = ARRAY_SIZE(dma_slaves),
|
||||
.channel = dma_channels,
|
||||
.channel_num = ARRAY_SIZE(dma_channels),
|
||||
.ts_low_shift = TS_LOW_SHIFT,
|
||||
.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
|
||||
.ts_high_shift = TS_HI_SHIFT,
|
||||
.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
|
||||
.ts_shift = dma_ts_shift,
|
||||
.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
|
||||
.dmaor_init = DMAOR_DME,
|
||||
.chclr_present = 1,
|
||||
.chclr_bitwise = 1,
|
||||
};
|
||||
72
drivers/dma/sh/shdma.h
Normal file
72
drivers/dma/sh/shdma.h
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* Renesas SuperH DMA Engine support
|
||||
*
|
||||
* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
|
||||
* Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
#ifndef __DMA_SHDMA_H
|
||||
#define __DMA_SHDMA_H
|
||||
|
||||
#include <linux/sh_dma.h>
|
||||
#include <linux/shdma-base.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
#define SH_DMAE_MAX_CHANNELS 20
|
||||
#define SH_DMAE_TCR_MAX 0x00FFFFFF /* 16MB */
|
||||
|
||||
struct device;
|
||||
|
||||
struct sh_dmae_chan {
|
||||
struct shdma_chan shdma_chan;
|
||||
const struct sh_dmae_slave_config *config; /* Slave DMA configuration */
|
||||
int xmit_shift; /* log_2(bytes_per_xfer) */
|
||||
void __iomem *base;
|
||||
char dev_id[16]; /* unique name per DMAC of channel */
|
||||
int pm_error;
|
||||
dma_addr_t slave_addr;
|
||||
};
|
||||
|
||||
struct sh_dmae_device {
|
||||
struct shdma_dev shdma_dev;
|
||||
struct sh_dmae_chan *chan[SH_DMAE_MAX_CHANNELS];
|
||||
const struct sh_dmae_pdata *pdata;
|
||||
struct list_head node;
|
||||
void __iomem *chan_reg;
|
||||
void __iomem *dmars;
|
||||
unsigned int chcr_offset;
|
||||
u32 chcr_ie_bit;
|
||||
};
|
||||
|
||||
struct sh_dmae_regs {
|
||||
u32 sar; /* SAR / source address */
|
||||
u32 dar; /* DAR / destination address */
|
||||
u32 tcr; /* TCR / transfer count */
|
||||
};
|
||||
|
||||
struct sh_dmae_desc {
|
||||
struct sh_dmae_regs hw;
|
||||
struct shdma_desc shdma_desc;
|
||||
};
|
||||
|
||||
#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, shdma_chan)
|
||||
#define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
|
||||
#define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
|
||||
#define to_sh_dev(chan) container_of(chan->shdma_chan.dma_chan.device,\
|
||||
struct sh_dmae_device, shdma_dev.dma_dev)
|
||||
|
||||
#ifdef CONFIG_SH_DMAE_R8A73A4
|
||||
extern const struct sh_dmae_pdata r8a73a4_dma_pdata;
|
||||
#define r8a73a4_shdma_devid (&r8a73a4_dma_pdata)
|
||||
#else
|
||||
#define r8a73a4_shdma_devid NULL
|
||||
#endif
|
||||
|
||||
#endif /* __DMA_SHDMA_H */
|
||||
959
drivers/dma/sh/shdmac.c
Normal file
959
drivers/dma/sh/shdmac.c
Normal file
|
|
@ -0,0 +1,959 @@
|
|||
/*
|
||||
* Renesas SuperH DMA Engine support
|
||||
*
|
||||
* base is drivers/dma/flsdma.c
|
||||
*
|
||||
* Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
|
||||
* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
|
||||
* Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* - DMA of SuperH does not have Hardware DMA chain mode.
|
||||
* - MAX DMA size is 16MB.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/kdebug.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/rculist.h>
|
||||
#include <linux/sh_dma.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include "../dmaengine.h"
|
||||
#include "shdma.h"
|
||||
|
||||
/* DMA registers */
|
||||
#define SAR 0x00 /* Source Address Register */
|
||||
#define DAR 0x04 /* Destination Address Register */
|
||||
#define TCR 0x08 /* Transfer Count Register */
|
||||
#define CHCR 0x0C /* Channel Control Register */
|
||||
#define DMAOR 0x40 /* DMA Operation Register */
|
||||
|
||||
#define TEND 0x18 /* USB-DMAC */
|
||||
|
||||
#define SH_DMAE_DRV_NAME "sh-dma-engine"
|
||||
|
||||
/* Default MEMCPY transfer size = 2^2 = 4 bytes */
|
||||
#define LOG2_DEFAULT_XFER_SIZE 2
|
||||
#define SH_DMA_SLAVE_NUMBER 256
|
||||
#define SH_DMA_TCR_MAX (16 * 1024 * 1024 - 1)
|
||||
|
||||
/*
|
||||
* Used for write-side mutual exclusion for the global device list,
|
||||
* read-side synchronization by way of RCU, and per-controller data.
|
||||
*/
|
||||
static DEFINE_SPINLOCK(sh_dmae_lock);
|
||||
static LIST_HEAD(sh_dmae_devices);
|
||||
|
||||
/*
|
||||
* Different DMAC implementations provide different ways to clear DMA channels:
|
||||
* (1) none - no CHCLR registers are available
|
||||
* (2) one CHCLR register per channel - 0 has to be written to it to clear
|
||||
* channel buffers
|
||||
* (3) one CHCLR per several channels - 1 has to be written to the bit,
|
||||
* corresponding to the specific channel to reset it
|
||||
*/
|
||||
static void channel_clear(struct sh_dmae_chan *sh_dc)
|
||||
{
|
||||
struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
|
||||
const struct sh_dmae_channel *chan_pdata = shdev->pdata->channel +
|
||||
sh_dc->shdma_chan.id;
|
||||
u32 val = shdev->pdata->chclr_bitwise ? 1 << chan_pdata->chclr_bit : 0;
|
||||
|
||||
__raw_writel(val, shdev->chan_reg + chan_pdata->chclr_offset);
|
||||
}
|
||||
|
||||
static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
|
||||
{
|
||||
__raw_writel(data, sh_dc->base + reg);
|
||||
}
|
||||
|
||||
static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
|
||||
{
|
||||
return __raw_readl(sh_dc->base + reg);
|
||||
}
|
||||
|
||||
static u16 dmaor_read(struct sh_dmae_device *shdev)
|
||||
{
|
||||
void __iomem *addr = shdev->chan_reg + DMAOR;
|
||||
|
||||
if (shdev->pdata->dmaor_is_32bit)
|
||||
return __raw_readl(addr);
|
||||
else
|
||||
return __raw_readw(addr);
|
||||
}
|
||||
|
||||
static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
|
||||
{
|
||||
void __iomem *addr = shdev->chan_reg + DMAOR;
|
||||
|
||||
if (shdev->pdata->dmaor_is_32bit)
|
||||
__raw_writel(data, addr);
|
||||
else
|
||||
__raw_writew(data, addr);
|
||||
}
|
||||
|
||||
static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data)
|
||||
{
|
||||
struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
|
||||
|
||||
__raw_writel(data, sh_dc->base + shdev->chcr_offset);
|
||||
}
|
||||
|
||||
static u32 chcr_read(struct sh_dmae_chan *sh_dc)
|
||||
{
|
||||
struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
|
||||
|
||||
return __raw_readl(sh_dc->base + shdev->chcr_offset);
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset DMA controller
|
||||
*
|
||||
* SH7780 has two DMAOR register
|
||||
*/
|
||||
static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
|
||||
{
|
||||
unsigned short dmaor;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&sh_dmae_lock, flags);
|
||||
|
||||
dmaor = dmaor_read(shdev);
|
||||
dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
|
||||
|
||||
spin_unlock_irqrestore(&sh_dmae_lock, flags);
|
||||
}
|
||||
|
||||
static int sh_dmae_rst(struct sh_dmae_device *shdev)
|
||||
{
|
||||
unsigned short dmaor;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&sh_dmae_lock, flags);
|
||||
|
||||
dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME);
|
||||
|
||||
if (shdev->pdata->chclr_present) {
|
||||
int i;
|
||||
for (i = 0; i < shdev->pdata->channel_num; i++) {
|
||||
struct sh_dmae_chan *sh_chan = shdev->chan[i];
|
||||
if (sh_chan)
|
||||
channel_clear(sh_chan);
|
||||
}
|
||||
}
|
||||
|
||||
dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init);
|
||||
|
||||
dmaor = dmaor_read(shdev);
|
||||
|
||||
spin_unlock_irqrestore(&sh_dmae_lock, flags);
|
||||
|
||||
if (dmaor & (DMAOR_AE | DMAOR_NMIF)) {
|
||||
dev_warn(shdev->shdma_dev.dma_dev.dev, "Can't initialize DMAOR.\n");
|
||||
return -EIO;
|
||||
}
|
||||
if (shdev->pdata->dmaor_init & ~dmaor)
|
||||
dev_warn(shdev->shdma_dev.dma_dev.dev,
|
||||
"DMAOR=0x%x hasn't latched the initial value 0x%x.\n",
|
||||
dmaor, shdev->pdata->dmaor_init);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
|
||||
{
|
||||
u32 chcr = chcr_read(sh_chan);
|
||||
|
||||
if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
|
||||
return true; /* working */
|
||||
|
||||
return false; /* waiting */
|
||||
}
|
||||
|
||||
static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
|
||||
{
|
||||
struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
|
||||
const struct sh_dmae_pdata *pdata = shdev->pdata;
|
||||
int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
|
||||
((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
|
||||
|
||||
if (cnt >= pdata->ts_shift_num)
|
||||
cnt = 0;
|
||||
|
||||
return pdata->ts_shift[cnt];
|
||||
}
|
||||
|
||||
static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
|
||||
{
|
||||
struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
|
||||
const struct sh_dmae_pdata *pdata = shdev->pdata;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < pdata->ts_shift_num; i++)
|
||||
if (pdata->ts_shift[i] == l2size)
|
||||
break;
|
||||
|
||||
if (i == pdata->ts_shift_num)
|
||||
i = 0;
|
||||
|
||||
return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
|
||||
((i << pdata->ts_high_shift) & pdata->ts_high_mask);
|
||||
}
|
||||
|
||||
static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
|
||||
{
|
||||
sh_dmae_writel(sh_chan, hw->sar, SAR);
|
||||
sh_dmae_writel(sh_chan, hw->dar, DAR);
|
||||
sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
|
||||
}
|
||||
|
||||
static void dmae_start(struct sh_dmae_chan *sh_chan)
|
||||
{
|
||||
struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
|
||||
u32 chcr = chcr_read(sh_chan);
|
||||
|
||||
if (shdev->pdata->needs_tend_set)
|
||||
sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND);
|
||||
|
||||
chcr |= CHCR_DE | shdev->chcr_ie_bit;
|
||||
chcr_write(sh_chan, chcr & ~CHCR_TE);
|
||||
}
|
||||
|
||||
static void dmae_init(struct sh_dmae_chan *sh_chan)
|
||||
{
|
||||
/*
|
||||
* Default configuration for dual address memory-memory transfer.
|
||||
*/
|
||||
u32 chcr = DM_INC | SM_INC | RS_AUTO | log2size_to_chcr(sh_chan,
|
||||
LOG2_DEFAULT_XFER_SIZE);
|
||||
sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
|
||||
chcr_write(sh_chan, chcr);
|
||||
}
|
||||
|
||||
static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
|
||||
{
|
||||
/* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
|
||||
if (dmae_is_busy(sh_chan))
|
||||
return -EBUSY;
|
||||
|
||||
sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
|
||||
chcr_write(sh_chan, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
|
||||
{
|
||||
struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
|
||||
const struct sh_dmae_pdata *pdata = shdev->pdata;
|
||||
const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->shdma_chan.id];
|
||||
void __iomem *addr = shdev->dmars;
|
||||
unsigned int shift = chan_pdata->dmars_bit;
|
||||
|
||||
if (dmae_is_busy(sh_chan))
|
||||
return -EBUSY;
|
||||
|
||||
if (pdata->no_dmars)
|
||||
return 0;
|
||||
|
||||
/* in the case of a missing DMARS resource use first memory window */
|
||||
if (!addr)
|
||||
addr = shdev->chan_reg;
|
||||
addr += chan_pdata->dmars;
|
||||
|
||||
__raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
|
||||
addr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sh_dmae_start_xfer(struct shdma_chan *schan,
|
||||
struct shdma_desc *sdesc)
|
||||
{
|
||||
struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
|
||||
shdma_chan);
|
||||
struct sh_dmae_desc *sh_desc = container_of(sdesc,
|
||||
struct sh_dmae_desc, shdma_desc);
|
||||
dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%x -> %x\n",
|
||||
sdesc->async_tx.cookie, sh_chan->shdma_chan.id,
|
||||
sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar);
|
||||
/* Get the ld start address from ld_queue */
|
||||
dmae_set_reg(sh_chan, &sh_desc->hw);
|
||||
dmae_start(sh_chan);
|
||||
}
|
||||
|
||||
static bool sh_dmae_channel_busy(struct shdma_chan *schan)
|
||||
{
|
||||
struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
|
||||
shdma_chan);
|
||||
return dmae_is_busy(sh_chan);
|
||||
}
|
||||
|
||||
static void sh_dmae_setup_xfer(struct shdma_chan *schan,
|
||||
int slave_id)
|
||||
{
|
||||
struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
|
||||
shdma_chan);
|
||||
|
||||
if (slave_id >= 0) {
|
||||
const struct sh_dmae_slave_config *cfg =
|
||||
sh_chan->config;
|
||||
|
||||
dmae_set_dmars(sh_chan, cfg->mid_rid);
|
||||
dmae_set_chcr(sh_chan, cfg->chcr);
|
||||
} else {
|
||||
dmae_init(sh_chan);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Find a slave channel configuration from the contoller list by either a slave
|
||||
* ID in the non-DT case, or by a MID/RID value in the DT case
|
||||
*/
|
||||
static const struct sh_dmae_slave_config *dmae_find_slave(
|
||||
struct sh_dmae_chan *sh_chan, int match)
|
||||
{
|
||||
struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
|
||||
const struct sh_dmae_pdata *pdata = shdev->pdata;
|
||||
const struct sh_dmae_slave_config *cfg;
|
||||
int i;
|
||||
|
||||
if (!sh_chan->shdma_chan.dev->of_node) {
|
||||
if (match >= SH_DMA_SLAVE_NUMBER)
|
||||
return NULL;
|
||||
|
||||
for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
|
||||
if (cfg->slave_id == match)
|
||||
return cfg;
|
||||
} else {
|
||||
for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
|
||||
if (cfg->mid_rid == match) {
|
||||
sh_chan->shdma_chan.slave_id = i;
|
||||
return cfg;
|
||||
}
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int sh_dmae_set_slave(struct shdma_chan *schan,
|
||||
int slave_id, dma_addr_t slave_addr, bool try)
|
||||
{
|
||||
struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
|
||||
shdma_chan);
|
||||
const struct sh_dmae_slave_config *cfg = dmae_find_slave(sh_chan, slave_id);
|
||||
if (!cfg)
|
||||
return -ENXIO;
|
||||
|
||||
if (!try) {
|
||||
sh_chan->config = cfg;
|
||||
sh_chan->slave_addr = slave_addr ? : cfg->addr;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dmae_halt(struct sh_dmae_chan *sh_chan)
|
||||
{
|
||||
struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
|
||||
u32 chcr = chcr_read(sh_chan);
|
||||
|
||||
chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit);
|
||||
chcr_write(sh_chan, chcr);
|
||||
}
|
||||
|
||||
static int sh_dmae_desc_setup(struct shdma_chan *schan,
|
||||
struct shdma_desc *sdesc,
|
||||
dma_addr_t src, dma_addr_t dst, size_t *len)
|
||||
{
|
||||
struct sh_dmae_desc *sh_desc = container_of(sdesc,
|
||||
struct sh_dmae_desc, shdma_desc);
|
||||
|
||||
if (*len > schan->max_xfer_len)
|
||||
*len = schan->max_xfer_len;
|
||||
|
||||
sh_desc->hw.sar = src;
|
||||
sh_desc->hw.dar = dst;
|
||||
sh_desc->hw.tcr = *len;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sh_dmae_halt(struct shdma_chan *schan)
|
||||
{
|
||||
struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
|
||||
shdma_chan);
|
||||
dmae_halt(sh_chan);
|
||||
}
|
||||
|
||||
static bool sh_dmae_chan_irq(struct shdma_chan *schan, int irq)
|
||||
{
|
||||
struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
|
||||
shdma_chan);
|
||||
|
||||
if (!(chcr_read(sh_chan) & CHCR_TE))
|
||||
return false;
|
||||
|
||||
/* DMA stop */
|
||||
dmae_halt(sh_chan);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static size_t sh_dmae_get_partial(struct shdma_chan *schan,
|
||||
struct shdma_desc *sdesc)
|
||||
{
|
||||
struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
|
||||
shdma_chan);
|
||||
struct sh_dmae_desc *sh_desc = container_of(sdesc,
|
||||
struct sh_dmae_desc, shdma_desc);
|
||||
return sh_desc->hw.tcr -
|
||||
(sh_dmae_readl(sh_chan, TCR) << sh_chan->xmit_shift);
|
||||
}
|
||||
|
||||
/* Called from error IRQ or NMI */
|
||||
static bool sh_dmae_reset(struct sh_dmae_device *shdev)
|
||||
{
|
||||
bool ret;
|
||||
|
||||
/* halt the dma controller */
|
||||
sh_dmae_ctl_stop(shdev);
|
||||
|
||||
/* We cannot detect, which channel caused the error, have to reset all */
|
||||
ret = shdma_reset(&shdev->shdma_dev);
|
||||
|
||||
sh_dmae_rst(shdev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARM)
|
||||
static irqreturn_t sh_dmae_err(int irq, void *data)
|
||||
{
|
||||
struct sh_dmae_device *shdev = data;
|
||||
|
||||
if (!(dmaor_read(shdev) & DMAOR_AE))
|
||||
return IRQ_NONE;
|
||||
|
||||
sh_dmae_reset(shdev);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
#endif
|
||||
|
||||
static bool sh_dmae_desc_completed(struct shdma_chan *schan,
|
||||
struct shdma_desc *sdesc)
|
||||
{
|
||||
struct sh_dmae_chan *sh_chan = container_of(schan,
|
||||
struct sh_dmae_chan, shdma_chan);
|
||||
struct sh_dmae_desc *sh_desc = container_of(sdesc,
|
||||
struct sh_dmae_desc, shdma_desc);
|
||||
u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
|
||||
u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
|
||||
|
||||
return (sdesc->direction == DMA_DEV_TO_MEM &&
|
||||
(sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) ||
|
||||
(sdesc->direction != DMA_DEV_TO_MEM &&
|
||||
(sh_desc->hw.sar + sh_desc->hw.tcr) == sar_buf);
|
||||
}
|
||||
|
||||
static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev)
|
||||
{
|
||||
/* Fast path out if NMIF is not asserted for this controller */
|
||||
if ((dmaor_read(shdev) & DMAOR_NMIF) == 0)
|
||||
return false;
|
||||
|
||||
return sh_dmae_reset(shdev);
|
||||
}
|
||||
|
||||
static int sh_dmae_nmi_handler(struct notifier_block *self,
|
||||
unsigned long cmd, void *data)
|
||||
{
|
||||
struct sh_dmae_device *shdev;
|
||||
int ret = NOTIFY_DONE;
|
||||
bool triggered;
|
||||
|
||||
/*
|
||||
* Only concern ourselves with NMI events.
|
||||
*
|
||||
* Normally we would check the die chain value, but as this needs
|
||||
* to be architecture independent, check for NMI context instead.
|
||||
*/
|
||||
if (!in_nmi())
|
||||
return NOTIFY_DONE;
|
||||
|
||||
rcu_read_lock();
|
||||
list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) {
|
||||
/*
|
||||
* Only stop if one of the controllers has NMIF asserted,
|
||||
* we do not want to interfere with regular address error
|
||||
* handling or NMI events that don't concern the DMACs.
|
||||
*/
|
||||
triggered = sh_dmae_nmi_notify(shdev);
|
||||
if (triggered == true)
|
||||
ret = NOTIFY_OK;
|
||||
}
|
||||
rcu_read_unlock();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct notifier_block sh_dmae_nmi_notifier __read_mostly = {
|
||||
.notifier_call = sh_dmae_nmi_handler,
|
||||
|
||||
/* Run before NMI debug handler and KGDB */
|
||||
.priority = 1,
|
||||
};
|
||||
|
||||
static int sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
|
||||
int irq, unsigned long flags)
|
||||
{
|
||||
const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
|
||||
struct shdma_dev *sdev = &shdev->shdma_dev;
|
||||
struct platform_device *pdev = to_platform_device(sdev->dma_dev.dev);
|
||||
struct sh_dmae_chan *sh_chan;
|
||||
struct shdma_chan *schan;
|
||||
int err;
|
||||
|
||||
sh_chan = devm_kzalloc(sdev->dma_dev.dev, sizeof(struct sh_dmae_chan),
|
||||
GFP_KERNEL);
|
||||
if (!sh_chan) {
|
||||
dev_err(sdev->dma_dev.dev,
|
||||
"No free memory for allocating dma channels!\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
schan = &sh_chan->shdma_chan;
|
||||
schan->max_xfer_len = SH_DMA_TCR_MAX + 1;
|
||||
|
||||
shdma_chan_probe(sdev, schan, id);
|
||||
|
||||
sh_chan->base = shdev->chan_reg + chan_pdata->offset;
|
||||
|
||||
/* set up channel irq */
|
||||
if (pdev->id >= 0)
|
||||
snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
|
||||
"sh-dmae%d.%d", pdev->id, id);
|
||||
else
|
||||
snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
|
||||
"sh-dma%d", id);
|
||||
|
||||
err = shdma_request_irq(schan, irq, flags, sh_chan->dev_id);
|
||||
if (err) {
|
||||
dev_err(sdev->dma_dev.dev,
|
||||
"DMA channel %d request_irq error %d\n",
|
||||
id, err);
|
||||
goto err_no_irq;
|
||||
}
|
||||
|
||||
shdev->chan[id] = sh_chan;
|
||||
return 0;
|
||||
|
||||
err_no_irq:
|
||||
/* remove from dmaengine device node */
|
||||
shdma_chan_remove(schan);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
|
||||
{
|
||||
struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
|
||||
struct shdma_chan *schan;
|
||||
int i;
|
||||
|
||||
shdma_for_each_chan(schan, &shdev->shdma_dev, i) {
|
||||
BUG_ON(!schan);
|
||||
|
||||
shdma_chan_remove(schan);
|
||||
}
|
||||
dma_dev->chancnt = 0;
|
||||
}
|
||||
|
||||
static void sh_dmae_shutdown(struct platform_device *pdev)
|
||||
{
|
||||
struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
|
||||
sh_dmae_ctl_stop(shdev);
|
||||
}
|
||||
|
||||
static int sh_dmae_runtime_suspend(struct device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_dmae_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct sh_dmae_device *shdev = dev_get_drvdata(dev);
|
||||
|
||||
return sh_dmae_rst(shdev);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int sh_dmae_suspend(struct device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_dmae_resume(struct device *dev)
|
||||
{
|
||||
struct sh_dmae_device *shdev = dev_get_drvdata(dev);
|
||||
int i, ret;
|
||||
|
||||
ret = sh_dmae_rst(shdev);
|
||||
if (ret < 0)
|
||||
dev_err(dev, "Failed to reset!\n");
|
||||
|
||||
for (i = 0; i < shdev->pdata->channel_num; i++) {
|
||||
struct sh_dmae_chan *sh_chan = shdev->chan[i];
|
||||
|
||||
if (!sh_chan->shdma_chan.desc_num)
|
||||
continue;
|
||||
|
||||
if (sh_chan->shdma_chan.slave_id >= 0) {
|
||||
const struct sh_dmae_slave_config *cfg = sh_chan->config;
|
||||
dmae_set_dmars(sh_chan, cfg->mid_rid);
|
||||
dmae_set_chcr(sh_chan, cfg->chcr);
|
||||
} else {
|
||||
dmae_init(sh_chan);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define sh_dmae_suspend NULL
|
||||
#define sh_dmae_resume NULL
|
||||
#endif
|
||||
|
||||
static const struct dev_pm_ops sh_dmae_pm = {
|
||||
.suspend = sh_dmae_suspend,
|
||||
.resume = sh_dmae_resume,
|
||||
.runtime_suspend = sh_dmae_runtime_suspend,
|
||||
.runtime_resume = sh_dmae_runtime_resume,
|
||||
};
|
||||
|
||||
static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan)
|
||||
{
|
||||
struct sh_dmae_chan *sh_chan = container_of(schan,
|
||||
struct sh_dmae_chan, shdma_chan);
|
||||
|
||||
/*
|
||||
* Implicit BUG_ON(!sh_chan->config)
|
||||
* This is an exclusive slave DMA operation, may only be called after a
|
||||
* successful slave configuration.
|
||||
*/
|
||||
return sh_chan->slave_addr;
|
||||
}
|
||||
|
||||
static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i)
|
||||
{
|
||||
return &((struct sh_dmae_desc *)buf)[i].shdma_desc;
|
||||
}
|
||||
|
||||
static const struct shdma_ops sh_dmae_shdma_ops = {
|
||||
.desc_completed = sh_dmae_desc_completed,
|
||||
.halt_channel = sh_dmae_halt,
|
||||
.channel_busy = sh_dmae_channel_busy,
|
||||
.slave_addr = sh_dmae_slave_addr,
|
||||
.desc_setup = sh_dmae_desc_setup,
|
||||
.set_slave = sh_dmae_set_slave,
|
||||
.setup_xfer = sh_dmae_setup_xfer,
|
||||
.start_xfer = sh_dmae_start_xfer,
|
||||
.embedded_desc = sh_dmae_embedded_desc,
|
||||
.chan_irq = sh_dmae_chan_irq,
|
||||
.get_partial = sh_dmae_get_partial,
|
||||
};
|
||||
|
||||
static const struct of_device_id sh_dmae_of_match[] = {
|
||||
{.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,},
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sh_dmae_of_match);
|
||||
|
||||
static int sh_dmae_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct sh_dmae_pdata *pdata;
|
||||
unsigned long chan_flag[SH_DMAE_MAX_CHANNELS] = {};
|
||||
int chan_irq[SH_DMAE_MAX_CHANNELS];
|
||||
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARM)
|
||||
unsigned long irqflags = 0;
|
||||
int errirq;
|
||||
#endif
|
||||
int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
|
||||
struct sh_dmae_device *shdev;
|
||||
struct dma_device *dma_dev;
|
||||
struct resource *chan, *dmars, *errirq_res, *chanirq_res;
|
||||
|
||||
if (pdev->dev.of_node)
|
||||
pdata = of_match_device(sh_dmae_of_match, &pdev->dev)->data;
|
||||
else
|
||||
pdata = dev_get_platdata(&pdev->dev);
|
||||
|
||||
/* get platform data */
|
||||
if (!pdata || !pdata->channel_num)
|
||||
return -ENODEV;
|
||||
|
||||
chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
/* DMARS area is optional */
|
||||
dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
/*
|
||||
* IRQ resources:
|
||||
* 1. there always must be at least one IRQ IO-resource. On SH4 it is
|
||||
* the error IRQ, in which case it is the only IRQ in this resource:
|
||||
* start == end. If it is the only IRQ resource, all channels also
|
||||
* use the same IRQ.
|
||||
* 2. DMA channel IRQ resources can be specified one per resource or in
|
||||
* ranges (start != end)
|
||||
* 3. iff all events (channels and, optionally, error) on this
|
||||
* controller use the same IRQ, only one IRQ resource can be
|
||||
* specified, otherwise there must be one IRQ per channel, even if
|
||||
* some of them are equal
|
||||
* 4. if all IRQs on this controller are equal or if some specific IRQs
|
||||
* specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
|
||||
* requested with the IRQF_SHARED flag
|
||||
*/
|
||||
errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!chan || !errirq_res)
|
||||
return -ENODEV;
|
||||
|
||||
shdev = devm_kzalloc(&pdev->dev, sizeof(struct sh_dmae_device),
|
||||
GFP_KERNEL);
|
||||
if (!shdev) {
|
||||
dev_err(&pdev->dev, "Not enough memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dma_dev = &shdev->shdma_dev.dma_dev;
|
||||
|
||||
shdev->chan_reg = devm_ioremap_resource(&pdev->dev, chan);
|
||||
if (IS_ERR(shdev->chan_reg))
|
||||
return PTR_ERR(shdev->chan_reg);
|
||||
if (dmars) {
|
||||
shdev->dmars = devm_ioremap_resource(&pdev->dev, dmars);
|
||||
if (IS_ERR(shdev->dmars))
|
||||
return PTR_ERR(shdev->dmars);
|
||||
}
|
||||
|
||||
if (!pdata->slave_only)
|
||||
dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
|
||||
if (pdata->slave && pdata->slave_num)
|
||||
dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
|
||||
|
||||
/* Default transfer size of 32 bytes requires 32-byte alignment */
|
||||
dma_dev->copy_align = LOG2_DEFAULT_XFER_SIZE;
|
||||
|
||||
shdev->shdma_dev.ops = &sh_dmae_shdma_ops;
|
||||
shdev->shdma_dev.desc_size = sizeof(struct sh_dmae_desc);
|
||||
err = shdma_init(&pdev->dev, &shdev->shdma_dev,
|
||||
pdata->channel_num);
|
||||
if (err < 0)
|
||||
goto eshdma;
|
||||
|
||||
/* platform data */
|
||||
shdev->pdata = pdata;
|
||||
|
||||
if (pdata->chcr_offset)
|
||||
shdev->chcr_offset = pdata->chcr_offset;
|
||||
else
|
||||
shdev->chcr_offset = CHCR;
|
||||
|
||||
if (pdata->chcr_ie_bit)
|
||||
shdev->chcr_ie_bit = pdata->chcr_ie_bit;
|
||||
else
|
||||
shdev->chcr_ie_bit = CHCR_IE;
|
||||
|
||||
platform_set_drvdata(pdev, shdev);
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
err = pm_runtime_get_sync(&pdev->dev);
|
||||
if (err < 0)
|
||||
dev_err(&pdev->dev, "%s(): GET = %d\n", __func__, err);
|
||||
|
||||
spin_lock_irq(&sh_dmae_lock);
|
||||
list_add_tail_rcu(&shdev->node, &sh_dmae_devices);
|
||||
spin_unlock_irq(&sh_dmae_lock);
|
||||
|
||||
/* reset dma controller - only needed as a test */
|
||||
err = sh_dmae_rst(shdev);
|
||||
if (err)
|
||||
goto rst_err;
|
||||
|
||||
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
|
||||
chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
|
||||
|
||||
if (!chanirq_res)
|
||||
chanirq_res = errirq_res;
|
||||
else
|
||||
irqres++;
|
||||
|
||||
if (chanirq_res == errirq_res ||
|
||||
(errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
|
||||
irqflags = IRQF_SHARED;
|
||||
|
||||
errirq = errirq_res->start;
|
||||
|
||||
err = devm_request_irq(&pdev->dev, errirq, sh_dmae_err, irqflags,
|
||||
"DMAC Address Error", shdev);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev,
|
||||
"DMA failed requesting irq #%d, error %d\n",
|
||||
errirq, err);
|
||||
goto eirq_err;
|
||||
}
|
||||
|
||||
#else
|
||||
chanirq_res = errirq_res;
|
||||
#endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
|
||||
|
||||
if (chanirq_res->start == chanirq_res->end &&
|
||||
!platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
|
||||
/* Special case - all multiplexed */
|
||||
for (; irq_cnt < pdata->channel_num; irq_cnt++) {
|
||||
if (irq_cnt < SH_DMAE_MAX_CHANNELS) {
|
||||
chan_irq[irq_cnt] = chanirq_res->start;
|
||||
chan_flag[irq_cnt] = IRQF_SHARED;
|
||||
} else {
|
||||
irq_cap = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
do {
|
||||
for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
|
||||
if (irq_cnt >= SH_DMAE_MAX_CHANNELS) {
|
||||
irq_cap = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
if ((errirq_res->flags & IORESOURCE_BITS) ==
|
||||
IORESOURCE_IRQ_SHAREABLE)
|
||||
chan_flag[irq_cnt] = IRQF_SHARED;
|
||||
else
|
||||
chan_flag[irq_cnt] = 0;
|
||||
dev_dbg(&pdev->dev,
|
||||
"Found IRQ %d for channel %d\n",
|
||||
i, irq_cnt);
|
||||
chan_irq[irq_cnt++] = i;
|
||||
}
|
||||
|
||||
if (irq_cnt >= SH_DMAE_MAX_CHANNELS)
|
||||
break;
|
||||
|
||||
chanirq_res = platform_get_resource(pdev,
|
||||
IORESOURCE_IRQ, ++irqres);
|
||||
} while (irq_cnt < pdata->channel_num && chanirq_res);
|
||||
}
|
||||
|
||||
/* Create DMA Channel */
|
||||
for (i = 0; i < irq_cnt; i++) {
|
||||
err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
|
||||
if (err)
|
||||
goto chan_probe_err;
|
||||
}
|
||||
|
||||
if (irq_cap)
|
||||
dev_notice(&pdev->dev, "Attempting to register %d DMA "
|
||||
"channels when a maximum of %d are supported.\n",
|
||||
pdata->channel_num, SH_DMAE_MAX_CHANNELS);
|
||||
|
||||
pm_runtime_put(&pdev->dev);
|
||||
|
||||
err = dma_async_device_register(&shdev->shdma_dev.dma_dev);
|
||||
if (err < 0)
|
||||
goto edmadevreg;
|
||||
|
||||
return err;
|
||||
|
||||
edmadevreg:
|
||||
pm_runtime_get(&pdev->dev);
|
||||
|
||||
chan_probe_err:
|
||||
sh_dmae_chan_remove(shdev);
|
||||
|
||||
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
|
||||
eirq_err:
|
||||
#endif
|
||||
rst_err:
|
||||
spin_lock_irq(&sh_dmae_lock);
|
||||
list_del_rcu(&shdev->node);
|
||||
spin_unlock_irq(&sh_dmae_lock);
|
||||
|
||||
pm_runtime_put(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
shdma_cleanup(&shdev->shdma_dev);
|
||||
eshdma:
|
||||
synchronize_rcu();
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int sh_dmae_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
|
||||
struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
|
||||
|
||||
dma_async_device_unregister(dma_dev);
|
||||
|
||||
spin_lock_irq(&sh_dmae_lock);
|
||||
list_del_rcu(&shdev->node);
|
||||
spin_unlock_irq(&sh_dmae_lock);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
sh_dmae_chan_remove(shdev);
|
||||
shdma_cleanup(&shdev->shdma_dev);
|
||||
|
||||
synchronize_rcu();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver sh_dmae_driver = {
|
||||
.driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.pm = &sh_dmae_pm,
|
||||
.name = SH_DMAE_DRV_NAME,
|
||||
.of_match_table = sh_dmae_of_match,
|
||||
},
|
||||
.remove = sh_dmae_remove,
|
||||
.shutdown = sh_dmae_shutdown,
|
||||
};
|
||||
|
||||
static int __init sh_dmae_init(void)
|
||||
{
|
||||
/* Wire up NMI handling */
|
||||
int err = register_die_notifier(&sh_dmae_nmi_notifier);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
|
||||
}
|
||||
module_init(sh_dmae_init);
|
||||
|
||||
static void __exit sh_dmae_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&sh_dmae_driver);
|
||||
|
||||
unregister_die_notifier(&sh_dmae_nmi_notifier);
|
||||
}
|
||||
module_exit(sh_dmae_exit);
|
||||
|
||||
MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
|
||||
MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:" SH_DMAE_DRV_NAME);
|
||||
425
drivers/dma/sh/sudmac.c
Normal file
425
drivers/dma/sh/sudmac.c
Normal file
|
|
@ -0,0 +1,425 @@
|
|||
/*
|
||||
* Renesas SUDMAC support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
*
|
||||
* based on drivers/dma/sh/shdma.c:
|
||||
* Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
|
||||
* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
|
||||
* Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/sudmac.h>
|
||||
|
||||
struct sudmac_chan {
|
||||
struct shdma_chan shdma_chan;
|
||||
void __iomem *base;
|
||||
char dev_id[16]; /* unique name per DMAC of channel */
|
||||
|
||||
u32 offset; /* for CFG, BA, BBC, CA, CBC, DEN */
|
||||
u32 cfg;
|
||||
u32 dint_end_bit;
|
||||
};
|
||||
|
||||
struct sudmac_device {
|
||||
struct shdma_dev shdma_dev;
|
||||
struct sudmac_pdata *pdata;
|
||||
void __iomem *chan_reg;
|
||||
};
|
||||
|
||||
struct sudmac_regs {
|
||||
u32 base_addr;
|
||||
u32 base_byte_count;
|
||||
};
|
||||
|
||||
struct sudmac_desc {
|
||||
struct sudmac_regs hw;
|
||||
struct shdma_desc shdma_desc;
|
||||
};
|
||||
|
||||
#define to_chan(schan) container_of(schan, struct sudmac_chan, shdma_chan)
|
||||
#define to_desc(sdesc) container_of(sdesc, struct sudmac_desc, shdma_desc)
|
||||
#define to_sdev(sc) container_of(sc->shdma_chan.dma_chan.device, \
|
||||
struct sudmac_device, shdma_dev.dma_dev)
|
||||
|
||||
/* SUDMAC register */
|
||||
#define SUDMAC_CH0CFG 0x00
|
||||
#define SUDMAC_CH0BA 0x10
|
||||
#define SUDMAC_CH0BBC 0x18
|
||||
#define SUDMAC_CH0CA 0x20
|
||||
#define SUDMAC_CH0CBC 0x28
|
||||
#define SUDMAC_CH0DEN 0x30
|
||||
#define SUDMAC_DSTSCLR 0x38
|
||||
#define SUDMAC_DBUFCTRL 0x3C
|
||||
#define SUDMAC_DINTCTRL 0x40
|
||||
#define SUDMAC_DINTSTS 0x44
|
||||
#define SUDMAC_DINTSTSCLR 0x48
|
||||
#define SUDMAC_CH0SHCTRL 0x50
|
||||
|
||||
/* Definitions for the sudmac_channel.config */
|
||||
#define SUDMAC_SENDBUFM 0x1000 /* b12: Transmit Buffer Mode */
|
||||
#define SUDMAC_RCVENDM 0x0100 /* b8: Receive Data Transfer End Mode */
|
||||
#define SUDMAC_LBA_WAIT 0x0030 /* b5-4: Local Bus Access Wait */
|
||||
|
||||
/* Definitions for the sudmac_channel.dint_end_bit */
|
||||
#define SUDMAC_CH1ENDE 0x0002 /* b1: Ch1 DMA Transfer End Int Enable */
|
||||
#define SUDMAC_CH0ENDE 0x0001 /* b0: Ch0 DMA Transfer End Int Enable */
|
||||
|
||||
#define SUDMAC_DRV_NAME "sudmac"
|
||||
|
||||
static void sudmac_writel(struct sudmac_chan *sc, u32 data, u32 reg)
|
||||
{
|
||||
iowrite32(data, sc->base + reg);
|
||||
}
|
||||
|
||||
static u32 sudmac_readl(struct sudmac_chan *sc, u32 reg)
|
||||
{
|
||||
return ioread32(sc->base + reg);
|
||||
}
|
||||
|
||||
static bool sudmac_is_busy(struct sudmac_chan *sc)
|
||||
{
|
||||
u32 den = sudmac_readl(sc, SUDMAC_CH0DEN + sc->offset);
|
||||
|
||||
if (den)
|
||||
return true; /* working */
|
||||
|
||||
return false; /* waiting */
|
||||
}
|
||||
|
||||
static void sudmac_set_reg(struct sudmac_chan *sc, struct sudmac_regs *hw,
|
||||
struct shdma_desc *sdesc)
|
||||
{
|
||||
sudmac_writel(sc, sc->cfg, SUDMAC_CH0CFG + sc->offset);
|
||||
sudmac_writel(sc, hw->base_addr, SUDMAC_CH0BA + sc->offset);
|
||||
sudmac_writel(sc, hw->base_byte_count, SUDMAC_CH0BBC + sc->offset);
|
||||
}
|
||||
|
||||
static void sudmac_start(struct sudmac_chan *sc)
|
||||
{
|
||||
u32 dintctrl = sudmac_readl(sc, SUDMAC_DINTCTRL);
|
||||
|
||||
sudmac_writel(sc, dintctrl | sc->dint_end_bit, SUDMAC_DINTCTRL);
|
||||
sudmac_writel(sc, 1, SUDMAC_CH0DEN + sc->offset);
|
||||
}
|
||||
|
||||
static void sudmac_start_xfer(struct shdma_chan *schan,
|
||||
struct shdma_desc *sdesc)
|
||||
{
|
||||
struct sudmac_chan *sc = to_chan(schan);
|
||||
struct sudmac_desc *sd = to_desc(sdesc);
|
||||
|
||||
sudmac_set_reg(sc, &sd->hw, sdesc);
|
||||
sudmac_start(sc);
|
||||
}
|
||||
|
||||
static bool sudmac_channel_busy(struct shdma_chan *schan)
|
||||
{
|
||||
struct sudmac_chan *sc = to_chan(schan);
|
||||
|
||||
return sudmac_is_busy(sc);
|
||||
}
|
||||
|
||||
static void sudmac_setup_xfer(struct shdma_chan *schan, int slave_id)
|
||||
{
|
||||
}
|
||||
|
||||
static const struct sudmac_slave_config *sudmac_find_slave(
|
||||
struct sudmac_chan *sc, int slave_id)
|
||||
{
|
||||
struct sudmac_device *sdev = to_sdev(sc);
|
||||
struct sudmac_pdata *pdata = sdev->pdata;
|
||||
const struct sudmac_slave_config *cfg;
|
||||
int i;
|
||||
|
||||
for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
|
||||
if (cfg->slave_id == slave_id)
|
||||
return cfg;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int sudmac_set_slave(struct shdma_chan *schan, int slave_id,
|
||||
dma_addr_t slave_addr, bool try)
|
||||
{
|
||||
struct sudmac_chan *sc = to_chan(schan);
|
||||
const struct sudmac_slave_config *cfg = sudmac_find_slave(sc, slave_id);
|
||||
|
||||
if (!cfg)
|
||||
return -ENODEV;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void sudmac_dma_halt(struct sudmac_chan *sc)
|
||||
{
|
||||
u32 dintctrl = sudmac_readl(sc, SUDMAC_DINTCTRL);
|
||||
|
||||
sudmac_writel(sc, 0, SUDMAC_CH0DEN + sc->offset);
|
||||
sudmac_writel(sc, dintctrl & ~sc->dint_end_bit, SUDMAC_DINTCTRL);
|
||||
sudmac_writel(sc, sc->dint_end_bit, SUDMAC_DINTSTSCLR);
|
||||
}
|
||||
|
||||
static int sudmac_desc_setup(struct shdma_chan *schan,
|
||||
struct shdma_desc *sdesc,
|
||||
dma_addr_t src, dma_addr_t dst, size_t *len)
|
||||
{
|
||||
struct sudmac_chan *sc = to_chan(schan);
|
||||
struct sudmac_desc *sd = to_desc(sdesc);
|
||||
|
||||
dev_dbg(sc->shdma_chan.dev, "%s: src=%pad, dst=%pad, len=%zu\n",
|
||||
__func__, &src, &dst, *len);
|
||||
|
||||
if (*len > schan->max_xfer_len)
|
||||
*len = schan->max_xfer_len;
|
||||
|
||||
if (dst)
|
||||
sd->hw.base_addr = dst;
|
||||
else if (src)
|
||||
sd->hw.base_addr = src;
|
||||
sd->hw.base_byte_count = *len;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sudmac_halt(struct shdma_chan *schan)
|
||||
{
|
||||
struct sudmac_chan *sc = to_chan(schan);
|
||||
|
||||
sudmac_dma_halt(sc);
|
||||
}
|
||||
|
||||
static bool sudmac_chan_irq(struct shdma_chan *schan, int irq)
|
||||
{
|
||||
struct sudmac_chan *sc = to_chan(schan);
|
||||
u32 dintsts = sudmac_readl(sc, SUDMAC_DINTSTS);
|
||||
|
||||
if (!(dintsts & sc->dint_end_bit))
|
||||
return false;
|
||||
|
||||
/* DMA stop */
|
||||
sudmac_dma_halt(sc);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static size_t sudmac_get_partial(struct shdma_chan *schan,
|
||||
struct shdma_desc *sdesc)
|
||||
{
|
||||
struct sudmac_chan *sc = to_chan(schan);
|
||||
struct sudmac_desc *sd = to_desc(sdesc);
|
||||
u32 current_byte_count = sudmac_readl(sc, SUDMAC_CH0CBC + sc->offset);
|
||||
|
||||
return sd->hw.base_byte_count - current_byte_count;
|
||||
}
|
||||
|
||||
static bool sudmac_desc_completed(struct shdma_chan *schan,
|
||||
struct shdma_desc *sdesc)
|
||||
{
|
||||
struct sudmac_chan *sc = to_chan(schan);
|
||||
struct sudmac_desc *sd = to_desc(sdesc);
|
||||
u32 current_addr = sudmac_readl(sc, SUDMAC_CH0CA + sc->offset);
|
||||
|
||||
return sd->hw.base_addr + sd->hw.base_byte_count == current_addr;
|
||||
}
|
||||
|
||||
static int sudmac_chan_probe(struct sudmac_device *su_dev, int id, int irq,
|
||||
unsigned long flags)
|
||||
{
|
||||
struct shdma_dev *sdev = &su_dev->shdma_dev;
|
||||
struct platform_device *pdev = to_platform_device(sdev->dma_dev.dev);
|
||||
struct sudmac_chan *sc;
|
||||
struct shdma_chan *schan;
|
||||
int err;
|
||||
|
||||
sc = devm_kzalloc(&pdev->dev, sizeof(struct sudmac_chan), GFP_KERNEL);
|
||||
if (!sc) {
|
||||
dev_err(sdev->dma_dev.dev,
|
||||
"No free memory for allocating dma channels!\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
schan = &sc->shdma_chan;
|
||||
schan->max_xfer_len = 64 * 1024 * 1024 - 1;
|
||||
|
||||
shdma_chan_probe(sdev, schan, id);
|
||||
|
||||
sc->base = su_dev->chan_reg;
|
||||
|
||||
/* get platform_data */
|
||||
sc->offset = su_dev->pdata->channel->offset;
|
||||
if (su_dev->pdata->channel->config & SUDMAC_TX_BUFFER_MODE)
|
||||
sc->cfg |= SUDMAC_SENDBUFM;
|
||||
if (su_dev->pdata->channel->config & SUDMAC_RX_END_MODE)
|
||||
sc->cfg |= SUDMAC_RCVENDM;
|
||||
sc->cfg |= (su_dev->pdata->channel->wait << 4) & SUDMAC_LBA_WAIT;
|
||||
|
||||
if (su_dev->pdata->channel->dint_end_bit & SUDMAC_DMA_BIT_CH0)
|
||||
sc->dint_end_bit |= SUDMAC_CH0ENDE;
|
||||
if (su_dev->pdata->channel->dint_end_bit & SUDMAC_DMA_BIT_CH1)
|
||||
sc->dint_end_bit |= SUDMAC_CH1ENDE;
|
||||
|
||||
/* set up channel irq */
|
||||
if (pdev->id >= 0)
|
||||
snprintf(sc->dev_id, sizeof(sc->dev_id), "sudmac%d.%d",
|
||||
pdev->id, id);
|
||||
else
|
||||
snprintf(sc->dev_id, sizeof(sc->dev_id), "sudmac%d", id);
|
||||
|
||||
err = shdma_request_irq(schan, irq, flags, sc->dev_id);
|
||||
if (err) {
|
||||
dev_err(sdev->dma_dev.dev,
|
||||
"DMA channel %d request_irq failed %d\n", id, err);
|
||||
goto err_no_irq;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_no_irq:
|
||||
/* remove from dmaengine device node */
|
||||
shdma_chan_remove(schan);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void sudmac_chan_remove(struct sudmac_device *su_dev)
|
||||
{
|
||||
struct dma_device *dma_dev = &su_dev->shdma_dev.dma_dev;
|
||||
struct shdma_chan *schan;
|
||||
int i;
|
||||
|
||||
shdma_for_each_chan(schan, &su_dev->shdma_dev, i) {
|
||||
BUG_ON(!schan);
|
||||
|
||||
shdma_chan_remove(schan);
|
||||
}
|
||||
dma_dev->chancnt = 0;
|
||||
}
|
||||
|
||||
static dma_addr_t sudmac_slave_addr(struct shdma_chan *schan)
|
||||
{
|
||||
/* SUDMAC doesn't need the address */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct shdma_desc *sudmac_embedded_desc(void *buf, int i)
|
||||
{
|
||||
return &((struct sudmac_desc *)buf)[i].shdma_desc;
|
||||
}
|
||||
|
||||
static const struct shdma_ops sudmac_shdma_ops = {
|
||||
.desc_completed = sudmac_desc_completed,
|
||||
.halt_channel = sudmac_halt,
|
||||
.channel_busy = sudmac_channel_busy,
|
||||
.slave_addr = sudmac_slave_addr,
|
||||
.desc_setup = sudmac_desc_setup,
|
||||
.set_slave = sudmac_set_slave,
|
||||
.setup_xfer = sudmac_setup_xfer,
|
||||
.start_xfer = sudmac_start_xfer,
|
||||
.embedded_desc = sudmac_embedded_desc,
|
||||
.chan_irq = sudmac_chan_irq,
|
||||
.get_partial = sudmac_get_partial,
|
||||
};
|
||||
|
||||
static int sudmac_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct sudmac_pdata *pdata = dev_get_platdata(&pdev->dev);
|
||||
int err, i;
|
||||
struct sudmac_device *su_dev;
|
||||
struct dma_device *dma_dev;
|
||||
struct resource *chan, *irq_res;
|
||||
|
||||
/* get platform data */
|
||||
if (!pdata)
|
||||
return -ENODEV;
|
||||
|
||||
irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!irq_res)
|
||||
return -ENODEV;
|
||||
|
||||
err = -ENOMEM;
|
||||
su_dev = devm_kzalloc(&pdev->dev, sizeof(struct sudmac_device),
|
||||
GFP_KERNEL);
|
||||
if (!su_dev) {
|
||||
dev_err(&pdev->dev, "Not enough memory\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
dma_dev = &su_dev->shdma_dev.dma_dev;
|
||||
|
||||
chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
su_dev->chan_reg = devm_ioremap_resource(&pdev->dev, chan);
|
||||
if (IS_ERR(su_dev->chan_reg))
|
||||
return PTR_ERR(su_dev->chan_reg);
|
||||
|
||||
dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
|
||||
|
||||
su_dev->shdma_dev.ops = &sudmac_shdma_ops;
|
||||
su_dev->shdma_dev.desc_size = sizeof(struct sudmac_desc);
|
||||
err = shdma_init(&pdev->dev, &su_dev->shdma_dev, pdata->channel_num);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
/* platform data */
|
||||
su_dev->pdata = dev_get_platdata(&pdev->dev);
|
||||
|
||||
platform_set_drvdata(pdev, su_dev);
|
||||
|
||||
/* Create DMA Channel */
|
||||
for (i = 0; i < pdata->channel_num; i++) {
|
||||
err = sudmac_chan_probe(su_dev, i, irq_res->start, IRQF_SHARED);
|
||||
if (err)
|
||||
goto chan_probe_err;
|
||||
}
|
||||
|
||||
err = dma_async_device_register(&su_dev->shdma_dev.dma_dev);
|
||||
if (err < 0)
|
||||
goto chan_probe_err;
|
||||
|
||||
return err;
|
||||
|
||||
chan_probe_err:
|
||||
sudmac_chan_remove(su_dev);
|
||||
|
||||
shdma_cleanup(&su_dev->shdma_dev);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int sudmac_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sudmac_device *su_dev = platform_get_drvdata(pdev);
|
||||
struct dma_device *dma_dev = &su_dev->shdma_dev.dma_dev;
|
||||
|
||||
dma_async_device_unregister(dma_dev);
|
||||
sudmac_chan_remove(su_dev);
|
||||
shdma_cleanup(&su_dev->shdma_dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver sudmac_driver = {
|
||||
.driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = SUDMAC_DRV_NAME,
|
||||
},
|
||||
.probe = sudmac_probe,
|
||||
.remove = sudmac_remove,
|
||||
};
|
||||
module_platform_driver(sudmac_driver);
|
||||
|
||||
MODULE_AUTHOR("Yoshihiro Shimoda");
|
||||
MODULE_DESCRIPTION("Renesas SUDMAC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:" SUDMAC_DRV_NAME);
|
||||
958
drivers/dma/sirf-dma.c
Normal file
958
drivers/dma/sirf-dma.c
Normal file
|
|
@ -0,0 +1,958 @@
|
|||
/*
|
||||
* DMA controller driver for CSR SiRFprimaII
|
||||
*
|
||||
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/of_dma.h>
|
||||
#include <linux/sirfsoc_dma.h>
|
||||
|
||||
#include "dmaengine.h"
|
||||
|
||||
#define SIRFSOC_DMA_DESCRIPTORS 16
|
||||
#define SIRFSOC_DMA_CHANNELS 16
|
||||
|
||||
#define SIRFSOC_DMA_CH_ADDR 0x00
|
||||
#define SIRFSOC_DMA_CH_XLEN 0x04
|
||||
#define SIRFSOC_DMA_CH_YLEN 0x08
|
||||
#define SIRFSOC_DMA_CH_CTRL 0x0C
|
||||
|
||||
#define SIRFSOC_DMA_WIDTH_0 0x100
|
||||
#define SIRFSOC_DMA_CH_VALID 0x140
|
||||
#define SIRFSOC_DMA_CH_INT 0x144
|
||||
#define SIRFSOC_DMA_INT_EN 0x148
|
||||
#define SIRFSOC_DMA_INT_EN_CLR 0x14C
|
||||
#define SIRFSOC_DMA_CH_LOOP_CTRL 0x150
|
||||
#define SIRFSOC_DMA_CH_LOOP_CTRL_CLR 0x15C
|
||||
|
||||
#define SIRFSOC_DMA_MODE_CTRL_BIT 4
|
||||
#define SIRFSOC_DMA_DIR_CTRL_BIT 5
|
||||
|
||||
/* xlen and dma_width register is in 4 bytes boundary */
|
||||
#define SIRFSOC_DMA_WORD_LEN 4
|
||||
|
||||
struct sirfsoc_dma_desc {
|
||||
struct dma_async_tx_descriptor desc;
|
||||
struct list_head node;
|
||||
|
||||
/* SiRFprimaII 2D-DMA parameters */
|
||||
|
||||
int xlen; /* DMA xlen */
|
||||
int ylen; /* DMA ylen */
|
||||
int width; /* DMA width */
|
||||
int dir;
|
||||
bool cyclic; /* is loop DMA? */
|
||||
u32 addr; /* DMA buffer address */
|
||||
};
|
||||
|
||||
struct sirfsoc_dma_chan {
|
||||
struct dma_chan chan;
|
||||
struct list_head free;
|
||||
struct list_head prepared;
|
||||
struct list_head queued;
|
||||
struct list_head active;
|
||||
struct list_head completed;
|
||||
unsigned long happened_cyclic;
|
||||
unsigned long completed_cyclic;
|
||||
|
||||
/* Lock for this structure */
|
||||
spinlock_t lock;
|
||||
|
||||
int mode;
|
||||
};
|
||||
|
||||
struct sirfsoc_dma_regs {
|
||||
u32 ctrl[SIRFSOC_DMA_CHANNELS];
|
||||
u32 interrupt_en;
|
||||
};
|
||||
|
||||
struct sirfsoc_dma {
|
||||
struct dma_device dma;
|
||||
struct tasklet_struct tasklet;
|
||||
struct sirfsoc_dma_chan channels[SIRFSOC_DMA_CHANNELS];
|
||||
void __iomem *base;
|
||||
int irq;
|
||||
struct clk *clk;
|
||||
bool is_marco;
|
||||
struct sirfsoc_dma_regs regs_save;
|
||||
};
|
||||
|
||||
#define DRV_NAME "sirfsoc_dma"
|
||||
|
||||
static int sirfsoc_dma_runtime_suspend(struct device *dev);
|
||||
|
||||
/* Convert struct dma_chan to struct sirfsoc_dma_chan */
|
||||
static inline
|
||||
struct sirfsoc_dma_chan *dma_chan_to_sirfsoc_dma_chan(struct dma_chan *c)
|
||||
{
|
||||
return container_of(c, struct sirfsoc_dma_chan, chan);
|
||||
}
|
||||
|
||||
/* Convert struct dma_chan to struct sirfsoc_dma */
|
||||
static inline struct sirfsoc_dma *dma_chan_to_sirfsoc_dma(struct dma_chan *c)
|
||||
{
|
||||
struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(c);
|
||||
return container_of(schan, struct sirfsoc_dma, channels[c->chan_id]);
|
||||
}
|
||||
|
||||
/* Execute all queued DMA descriptors */
|
||||
static void sirfsoc_dma_execute(struct sirfsoc_dma_chan *schan)
|
||||
{
|
||||
struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan);
|
||||
int cid = schan->chan.chan_id;
|
||||
struct sirfsoc_dma_desc *sdesc = NULL;
|
||||
|
||||
/*
|
||||
* lock has been held by functions calling this, so we don't hold
|
||||
* lock again
|
||||
*/
|
||||
|
||||
sdesc = list_first_entry(&schan->queued, struct sirfsoc_dma_desc,
|
||||
node);
|
||||
/* Move the first queued descriptor to active list */
|
||||
list_move_tail(&sdesc->node, &schan->active);
|
||||
|
||||
/* Start the DMA transfer */
|
||||
writel_relaxed(sdesc->width, sdma->base + SIRFSOC_DMA_WIDTH_0 +
|
||||
cid * 4);
|
||||
writel_relaxed(cid | (schan->mode << SIRFSOC_DMA_MODE_CTRL_BIT) |
|
||||
(sdesc->dir << SIRFSOC_DMA_DIR_CTRL_BIT),
|
||||
sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_CTRL);
|
||||
writel_relaxed(sdesc->xlen, sdma->base + cid * 0x10 +
|
||||
SIRFSOC_DMA_CH_XLEN);
|
||||
writel_relaxed(sdesc->ylen, sdma->base + cid * 0x10 +
|
||||
SIRFSOC_DMA_CH_YLEN);
|
||||
writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) |
|
||||
(1 << cid), sdma->base + SIRFSOC_DMA_INT_EN);
|
||||
|
||||
/*
|
||||
* writel has an implict memory write barrier to make sure data is
|
||||
* flushed into memory before starting DMA
|
||||
*/
|
||||
writel(sdesc->addr >> 2, sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR);
|
||||
|
||||
if (sdesc->cyclic) {
|
||||
writel((1 << cid) | 1 << (cid + 16) |
|
||||
readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL),
|
||||
sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
|
||||
schan->happened_cyclic = schan->completed_cyclic = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* Interrupt handler */
|
||||
static irqreturn_t sirfsoc_dma_irq(int irq, void *data)
|
||||
{
|
||||
struct sirfsoc_dma *sdma = data;
|
||||
struct sirfsoc_dma_chan *schan;
|
||||
struct sirfsoc_dma_desc *sdesc = NULL;
|
||||
u32 is;
|
||||
int ch;
|
||||
|
||||
is = readl(sdma->base + SIRFSOC_DMA_CH_INT);
|
||||
while ((ch = fls(is) - 1) >= 0) {
|
||||
is &= ~(1 << ch);
|
||||
writel_relaxed(1 << ch, sdma->base + SIRFSOC_DMA_CH_INT);
|
||||
schan = &sdma->channels[ch];
|
||||
|
||||
spin_lock(&schan->lock);
|
||||
|
||||
sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc,
|
||||
node);
|
||||
if (!sdesc->cyclic) {
|
||||
/* Execute queued descriptors */
|
||||
list_splice_tail_init(&schan->active, &schan->completed);
|
||||
if (!list_empty(&schan->queued))
|
||||
sirfsoc_dma_execute(schan);
|
||||
} else
|
||||
schan->happened_cyclic++;
|
||||
|
||||
spin_unlock(&schan->lock);
|
||||
}
|
||||
|
||||
/* Schedule tasklet */
|
||||
tasklet_schedule(&sdma->tasklet);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/* process completed descriptors */
|
||||
static void sirfsoc_dma_process_completed(struct sirfsoc_dma *sdma)
|
||||
{
|
||||
dma_cookie_t last_cookie = 0;
|
||||
struct sirfsoc_dma_chan *schan;
|
||||
struct sirfsoc_dma_desc *sdesc;
|
||||
struct dma_async_tx_descriptor *desc;
|
||||
unsigned long flags;
|
||||
unsigned long happened_cyclic;
|
||||
LIST_HEAD(list);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < sdma->dma.chancnt; i++) {
|
||||
schan = &sdma->channels[i];
|
||||
|
||||
/* Get all completed descriptors */
|
||||
spin_lock_irqsave(&schan->lock, flags);
|
||||
if (!list_empty(&schan->completed)) {
|
||||
list_splice_tail_init(&schan->completed, &list);
|
||||
spin_unlock_irqrestore(&schan->lock, flags);
|
||||
|
||||
/* Execute callbacks and run dependencies */
|
||||
list_for_each_entry(sdesc, &list, node) {
|
||||
desc = &sdesc->desc;
|
||||
|
||||
if (desc->callback)
|
||||
desc->callback(desc->callback_param);
|
||||
|
||||
last_cookie = desc->cookie;
|
||||
dma_run_dependencies(desc);
|
||||
}
|
||||
|
||||
/* Free descriptors */
|
||||
spin_lock_irqsave(&schan->lock, flags);
|
||||
list_splice_tail_init(&list, &schan->free);
|
||||
schan->chan.completed_cookie = last_cookie;
|
||||
spin_unlock_irqrestore(&schan->lock, flags);
|
||||
} else {
|
||||
/* for cyclic channel, desc is always in active list */
|
||||
sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc,
|
||||
node);
|
||||
|
||||
if (!sdesc || (sdesc && !sdesc->cyclic)) {
|
||||
/* without active cyclic DMA */
|
||||
spin_unlock_irqrestore(&schan->lock, flags);
|
||||
continue;
|
||||
}
|
||||
|
||||
/* cyclic DMA */
|
||||
happened_cyclic = schan->happened_cyclic;
|
||||
spin_unlock_irqrestore(&schan->lock, flags);
|
||||
|
||||
desc = &sdesc->desc;
|
||||
while (happened_cyclic != schan->completed_cyclic) {
|
||||
if (desc->callback)
|
||||
desc->callback(desc->callback_param);
|
||||
schan->completed_cyclic++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* DMA Tasklet */
|
||||
static void sirfsoc_dma_tasklet(unsigned long data)
|
||||
{
|
||||
struct sirfsoc_dma *sdma = (void *)data;
|
||||
|
||||
sirfsoc_dma_process_completed(sdma);
|
||||
}
|
||||
|
||||
/* Submit descriptor to hardware */
|
||||
static dma_cookie_t sirfsoc_dma_tx_submit(struct dma_async_tx_descriptor *txd)
|
||||
{
|
||||
struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(txd->chan);
|
||||
struct sirfsoc_dma_desc *sdesc;
|
||||
unsigned long flags;
|
||||
dma_cookie_t cookie;
|
||||
|
||||
sdesc = container_of(txd, struct sirfsoc_dma_desc, desc);
|
||||
|
||||
spin_lock_irqsave(&schan->lock, flags);
|
||||
|
||||
/* Move descriptor to queue */
|
||||
list_move_tail(&sdesc->node, &schan->queued);
|
||||
|
||||
cookie = dma_cookie_assign(txd);
|
||||
|
||||
spin_unlock_irqrestore(&schan->lock, flags);
|
||||
|
||||
return cookie;
|
||||
}
|
||||
|
||||
static int sirfsoc_dma_slave_config(struct sirfsoc_dma_chan *schan,
|
||||
struct dma_slave_config *config)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if ((config->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
|
||||
(config->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES))
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&schan->lock, flags);
|
||||
schan->mode = (config->src_maxburst == 4 ? 1 : 0);
|
||||
spin_unlock_irqrestore(&schan->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sirfsoc_dma_terminate_all(struct sirfsoc_dma_chan *schan)
|
||||
{
|
||||
struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan);
|
||||
int cid = schan->chan.chan_id;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&schan->lock, flags);
|
||||
|
||||
if (!sdma->is_marco) {
|
||||
writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) &
|
||||
~(1 << cid), sdma->base + SIRFSOC_DMA_INT_EN);
|
||||
writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL)
|
||||
& ~((1 << cid) | 1 << (cid + 16)),
|
||||
sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
|
||||
} else {
|
||||
writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_INT_EN_CLR);
|
||||
writel_relaxed((1 << cid) | 1 << (cid + 16),
|
||||
sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL_CLR);
|
||||
}
|
||||
|
||||
writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_VALID);
|
||||
|
||||
list_splice_tail_init(&schan->active, &schan->free);
|
||||
list_splice_tail_init(&schan->queued, &schan->free);
|
||||
|
||||
spin_unlock_irqrestore(&schan->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sirfsoc_dma_pause_chan(struct sirfsoc_dma_chan *schan)
|
||||
{
|
||||
struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan);
|
||||
int cid = schan->chan.chan_id;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&schan->lock, flags);
|
||||
|
||||
if (!sdma->is_marco)
|
||||
writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL)
|
||||
& ~((1 << cid) | 1 << (cid + 16)),
|
||||
sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
|
||||
else
|
||||
writel_relaxed((1 << cid) | 1 << (cid + 16),
|
||||
sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL_CLR);
|
||||
|
||||
spin_unlock_irqrestore(&schan->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sirfsoc_dma_resume_chan(struct sirfsoc_dma_chan *schan)
|
||||
{
|
||||
struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan);
|
||||
int cid = schan->chan.chan_id;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&schan->lock, flags);
|
||||
|
||||
if (!sdma->is_marco)
|
||||
writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL)
|
||||
| ((1 << cid) | 1 << (cid + 16)),
|
||||
sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
|
||||
else
|
||||
writel_relaxed((1 << cid) | 1 << (cid + 16),
|
||||
sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
|
||||
|
||||
spin_unlock_irqrestore(&schan->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sirfsoc_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
struct dma_slave_config *config;
|
||||
struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
|
||||
|
||||
switch (cmd) {
|
||||
case DMA_PAUSE:
|
||||
return sirfsoc_dma_pause_chan(schan);
|
||||
case DMA_RESUME:
|
||||
return sirfsoc_dma_resume_chan(schan);
|
||||
case DMA_TERMINATE_ALL:
|
||||
return sirfsoc_dma_terminate_all(schan);
|
||||
case DMA_SLAVE_CONFIG:
|
||||
config = (struct dma_slave_config *)arg;
|
||||
return sirfsoc_dma_slave_config(schan, config);
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
/* Alloc channel resources */
|
||||
static int sirfsoc_dma_alloc_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
|
||||
struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
|
||||
struct sirfsoc_dma_desc *sdesc;
|
||||
unsigned long flags;
|
||||
LIST_HEAD(descs);
|
||||
int i;
|
||||
|
||||
pm_runtime_get_sync(sdma->dma.dev);
|
||||
|
||||
/* Alloc descriptors for this channel */
|
||||
for (i = 0; i < SIRFSOC_DMA_DESCRIPTORS; i++) {
|
||||
sdesc = kzalloc(sizeof(*sdesc), GFP_KERNEL);
|
||||
if (!sdesc) {
|
||||
dev_notice(sdma->dma.dev, "Memory allocation error. "
|
||||
"Allocated only %u descriptors\n", i);
|
||||
break;
|
||||
}
|
||||
|
||||
dma_async_tx_descriptor_init(&sdesc->desc, chan);
|
||||
sdesc->desc.flags = DMA_CTRL_ACK;
|
||||
sdesc->desc.tx_submit = sirfsoc_dma_tx_submit;
|
||||
|
||||
list_add_tail(&sdesc->node, &descs);
|
||||
}
|
||||
|
||||
/* Return error only if no descriptors were allocated */
|
||||
if (i == 0)
|
||||
return -ENOMEM;
|
||||
|
||||
spin_lock_irqsave(&schan->lock, flags);
|
||||
|
||||
list_splice_tail_init(&descs, &schan->free);
|
||||
spin_unlock_irqrestore(&schan->lock, flags);
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
/* Free channel resources */
|
||||
static void sirfsoc_dma_free_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
|
||||
struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
|
||||
struct sirfsoc_dma_desc *sdesc, *tmp;
|
||||
unsigned long flags;
|
||||
LIST_HEAD(descs);
|
||||
|
||||
spin_lock_irqsave(&schan->lock, flags);
|
||||
|
||||
/* Channel must be idle */
|
||||
BUG_ON(!list_empty(&schan->prepared));
|
||||
BUG_ON(!list_empty(&schan->queued));
|
||||
BUG_ON(!list_empty(&schan->active));
|
||||
BUG_ON(!list_empty(&schan->completed));
|
||||
|
||||
/* Move data */
|
||||
list_splice_tail_init(&schan->free, &descs);
|
||||
|
||||
spin_unlock_irqrestore(&schan->lock, flags);
|
||||
|
||||
/* Free descriptors */
|
||||
list_for_each_entry_safe(sdesc, tmp, &descs, node)
|
||||
kfree(sdesc);
|
||||
|
||||
pm_runtime_put(sdma->dma.dev);
|
||||
}
|
||||
|
||||
/* Send pending descriptor to hardware */
|
||||
static void sirfsoc_dma_issue_pending(struct dma_chan *chan)
|
||||
{
|
||||
struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&schan->lock, flags);
|
||||
|
||||
if (list_empty(&schan->active) && !list_empty(&schan->queued))
|
||||
sirfsoc_dma_execute(schan);
|
||||
|
||||
spin_unlock_irqrestore(&schan->lock, flags);
|
||||
}
|
||||
|
||||
/* Check request completion status */
|
||||
static enum dma_status
|
||||
sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
|
||||
struct dma_tx_state *txstate)
|
||||
{
|
||||
struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
|
||||
struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
|
||||
unsigned long flags;
|
||||
enum dma_status ret;
|
||||
struct sirfsoc_dma_desc *sdesc;
|
||||
int cid = schan->chan.chan_id;
|
||||
unsigned long dma_pos;
|
||||
unsigned long dma_request_bytes;
|
||||
unsigned long residue;
|
||||
|
||||
spin_lock_irqsave(&schan->lock, flags);
|
||||
|
||||
sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc,
|
||||
node);
|
||||
dma_request_bytes = (sdesc->xlen + 1) * (sdesc->ylen + 1) *
|
||||
(sdesc->width * SIRFSOC_DMA_WORD_LEN);
|
||||
|
||||
ret = dma_cookie_status(chan, cookie, txstate);
|
||||
dma_pos = readl_relaxed(sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR)
|
||||
<< 2;
|
||||
residue = dma_request_bytes - (dma_pos - sdesc->addr);
|
||||
dma_set_residue(txstate, residue);
|
||||
|
||||
spin_unlock_irqrestore(&schan->lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *sirfsoc_dma_prep_interleaved(
|
||||
struct dma_chan *chan, struct dma_interleaved_template *xt,
|
||||
unsigned long flags)
|
||||
{
|
||||
struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
|
||||
struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
|
||||
struct sirfsoc_dma_desc *sdesc = NULL;
|
||||
unsigned long iflags;
|
||||
int ret;
|
||||
|
||||
if ((xt->dir != DMA_MEM_TO_DEV) && (xt->dir != DMA_DEV_TO_MEM)) {
|
||||
ret = -EINVAL;
|
||||
goto err_dir;
|
||||
}
|
||||
|
||||
/* Get free descriptor */
|
||||
spin_lock_irqsave(&schan->lock, iflags);
|
||||
if (!list_empty(&schan->free)) {
|
||||
sdesc = list_first_entry(&schan->free, struct sirfsoc_dma_desc,
|
||||
node);
|
||||
list_del(&sdesc->node);
|
||||
}
|
||||
spin_unlock_irqrestore(&schan->lock, iflags);
|
||||
|
||||
if (!sdesc) {
|
||||
/* try to free completed descriptors */
|
||||
sirfsoc_dma_process_completed(sdma);
|
||||
ret = 0;
|
||||
goto no_desc;
|
||||
}
|
||||
|
||||
/* Place descriptor in prepared list */
|
||||
spin_lock_irqsave(&schan->lock, iflags);
|
||||
|
||||
/*
|
||||
* Number of chunks in a frame can only be 1 for prima2
|
||||
* and ylen (number of frame - 1) must be at least 0
|
||||
*/
|
||||
if ((xt->frame_size == 1) && (xt->numf > 0)) {
|
||||
sdesc->cyclic = 0;
|
||||
sdesc->xlen = xt->sgl[0].size / SIRFSOC_DMA_WORD_LEN;
|
||||
sdesc->width = (xt->sgl[0].size + xt->sgl[0].icg) /
|
||||
SIRFSOC_DMA_WORD_LEN;
|
||||
sdesc->ylen = xt->numf - 1;
|
||||
if (xt->dir == DMA_MEM_TO_DEV) {
|
||||
sdesc->addr = xt->src_start;
|
||||
sdesc->dir = 1;
|
||||
} else {
|
||||
sdesc->addr = xt->dst_start;
|
||||
sdesc->dir = 0;
|
||||
}
|
||||
|
||||
list_add_tail(&sdesc->node, &schan->prepared);
|
||||
} else {
|
||||
pr_err("sirfsoc DMA Invalid xfer\n");
|
||||
ret = -EINVAL;
|
||||
goto err_xfer;
|
||||
}
|
||||
spin_unlock_irqrestore(&schan->lock, iflags);
|
||||
|
||||
return &sdesc->desc;
|
||||
err_xfer:
|
||||
spin_unlock_irqrestore(&schan->lock, iflags);
|
||||
no_desc:
|
||||
err_dir:
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *
|
||||
sirfsoc_dma_prep_cyclic(struct dma_chan *chan, dma_addr_t addr,
|
||||
size_t buf_len, size_t period_len,
|
||||
enum dma_transfer_direction direction, unsigned long flags, void *context)
|
||||
{
|
||||
struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
|
||||
struct sirfsoc_dma_desc *sdesc = NULL;
|
||||
unsigned long iflags;
|
||||
|
||||
/*
|
||||
* we only support cycle transfer with 2 period
|
||||
* If the X-length is set to 0, it would be the loop mode.
|
||||
* The DMA address keeps increasing until reaching the end of a loop
|
||||
* area whose size is defined by (DMA_WIDTH x (Y_LENGTH + 1)). Then
|
||||
* the DMA address goes back to the beginning of this area.
|
||||
* In loop mode, the DMA data region is divided into two parts, BUFA
|
||||
* and BUFB. DMA controller generates interrupts twice in each loop:
|
||||
* when the DMA address reaches the end of BUFA or the end of the
|
||||
* BUFB
|
||||
*/
|
||||
if (buf_len != 2 * period_len)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
/* Get free descriptor */
|
||||
spin_lock_irqsave(&schan->lock, iflags);
|
||||
if (!list_empty(&schan->free)) {
|
||||
sdesc = list_first_entry(&schan->free, struct sirfsoc_dma_desc,
|
||||
node);
|
||||
list_del(&sdesc->node);
|
||||
}
|
||||
spin_unlock_irqrestore(&schan->lock, iflags);
|
||||
|
||||
if (!sdesc)
|
||||
return NULL;
|
||||
|
||||
/* Place descriptor in prepared list */
|
||||
spin_lock_irqsave(&schan->lock, iflags);
|
||||
sdesc->addr = addr;
|
||||
sdesc->cyclic = 1;
|
||||
sdesc->xlen = 0;
|
||||
sdesc->ylen = buf_len / SIRFSOC_DMA_WORD_LEN - 1;
|
||||
sdesc->width = 1;
|
||||
list_add_tail(&sdesc->node, &schan->prepared);
|
||||
spin_unlock_irqrestore(&schan->lock, iflags);
|
||||
|
||||
return &sdesc->desc;
|
||||
}
|
||||
|
||||
/*
|
||||
* The DMA controller consists of 16 independent DMA channels.
|
||||
* Each channel is allocated to a different function
|
||||
*/
|
||||
bool sirfsoc_dma_filter_id(struct dma_chan *chan, void *chan_id)
|
||||
{
|
||||
unsigned int ch_nr = (unsigned int) chan_id;
|
||||
|
||||
if (ch_nr == chan->chan_id +
|
||||
chan->device->dev_id * SIRFSOC_DMA_CHANNELS)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
EXPORT_SYMBOL(sirfsoc_dma_filter_id);
|
||||
|
||||
#define SIRFSOC_DMA_BUSWIDTHS \
|
||||
(BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
|
||||
BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
|
||||
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
|
||||
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
|
||||
BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
|
||||
|
||||
static int sirfsoc_dma_device_slave_caps(struct dma_chan *dchan,
|
||||
struct dma_slave_caps *caps)
|
||||
{
|
||||
caps->src_addr_widths = SIRFSOC_DMA_BUSWIDTHS;
|
||||
caps->dstn_addr_widths = SIRFSOC_DMA_BUSWIDTHS;
|
||||
caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
|
||||
caps->cmd_pause = true;
|
||||
caps->cmd_terminate = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct dma_chan *of_dma_sirfsoc_xlate(struct of_phandle_args *dma_spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
struct sirfsoc_dma *sdma = ofdma->of_dma_data;
|
||||
unsigned int request = dma_spec->args[0];
|
||||
|
||||
if (request >= SIRFSOC_DMA_CHANNELS)
|
||||
return NULL;
|
||||
|
||||
return dma_get_slave_channel(&sdma->channels[request].chan);
|
||||
}
|
||||
|
||||
static int sirfsoc_dma_probe(struct platform_device *op)
|
||||
{
|
||||
struct device_node *dn = op->dev.of_node;
|
||||
struct device *dev = &op->dev;
|
||||
struct dma_device *dma;
|
||||
struct sirfsoc_dma *sdma;
|
||||
struct sirfsoc_dma_chan *schan;
|
||||
struct resource res;
|
||||
ulong regs_start, regs_size;
|
||||
u32 id;
|
||||
int ret, i;
|
||||
|
||||
sdma = devm_kzalloc(dev, sizeof(*sdma), GFP_KERNEL);
|
||||
if (!sdma) {
|
||||
dev_err(dev, "Memory exhausted!\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (of_device_is_compatible(dn, "sirf,marco-dmac"))
|
||||
sdma->is_marco = true;
|
||||
|
||||
if (of_property_read_u32(dn, "cell-index", &id)) {
|
||||
dev_err(dev, "Fail to get DMAC index\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
sdma->irq = irq_of_parse_and_map(dn, 0);
|
||||
if (sdma->irq == NO_IRQ) {
|
||||
dev_err(dev, "Error mapping IRQ!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
sdma->clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(sdma->clk)) {
|
||||
dev_err(dev, "failed to get a clock.\n");
|
||||
return PTR_ERR(sdma->clk);
|
||||
}
|
||||
|
||||
ret = of_address_to_resource(dn, 0, &res);
|
||||
if (ret) {
|
||||
dev_err(dev, "Error parsing memory region!\n");
|
||||
goto irq_dispose;
|
||||
}
|
||||
|
||||
regs_start = res.start;
|
||||
regs_size = resource_size(&res);
|
||||
|
||||
sdma->base = devm_ioremap(dev, regs_start, regs_size);
|
||||
if (!sdma->base) {
|
||||
dev_err(dev, "Error mapping memory region!\n");
|
||||
ret = -ENOMEM;
|
||||
goto irq_dispose;
|
||||
}
|
||||
|
||||
ret = request_irq(sdma->irq, &sirfsoc_dma_irq, 0, DRV_NAME, sdma);
|
||||
if (ret) {
|
||||
dev_err(dev, "Error requesting IRQ!\n");
|
||||
ret = -EINVAL;
|
||||
goto irq_dispose;
|
||||
}
|
||||
|
||||
dma = &sdma->dma;
|
||||
dma->dev = dev;
|
||||
dma->chancnt = SIRFSOC_DMA_CHANNELS;
|
||||
|
||||
dma->device_alloc_chan_resources = sirfsoc_dma_alloc_chan_resources;
|
||||
dma->device_free_chan_resources = sirfsoc_dma_free_chan_resources;
|
||||
dma->device_issue_pending = sirfsoc_dma_issue_pending;
|
||||
dma->device_control = sirfsoc_dma_control;
|
||||
dma->device_tx_status = sirfsoc_dma_tx_status;
|
||||
dma->device_prep_interleaved_dma = sirfsoc_dma_prep_interleaved;
|
||||
dma->device_prep_dma_cyclic = sirfsoc_dma_prep_cyclic;
|
||||
dma->device_slave_caps = sirfsoc_dma_device_slave_caps;
|
||||
|
||||
INIT_LIST_HEAD(&dma->channels);
|
||||
dma_cap_set(DMA_SLAVE, dma->cap_mask);
|
||||
dma_cap_set(DMA_CYCLIC, dma->cap_mask);
|
||||
dma_cap_set(DMA_INTERLEAVE, dma->cap_mask);
|
||||
dma_cap_set(DMA_PRIVATE, dma->cap_mask);
|
||||
|
||||
for (i = 0; i < dma->chancnt; i++) {
|
||||
schan = &sdma->channels[i];
|
||||
|
||||
schan->chan.device = dma;
|
||||
dma_cookie_init(&schan->chan);
|
||||
|
||||
INIT_LIST_HEAD(&schan->free);
|
||||
INIT_LIST_HEAD(&schan->prepared);
|
||||
INIT_LIST_HEAD(&schan->queued);
|
||||
INIT_LIST_HEAD(&schan->active);
|
||||
INIT_LIST_HEAD(&schan->completed);
|
||||
|
||||
spin_lock_init(&schan->lock);
|
||||
list_add_tail(&schan->chan.device_node, &dma->channels);
|
||||
}
|
||||
|
||||
tasklet_init(&sdma->tasklet, sirfsoc_dma_tasklet, (unsigned long)sdma);
|
||||
|
||||
/* Register DMA engine */
|
||||
dev_set_drvdata(dev, sdma);
|
||||
|
||||
ret = dma_async_device_register(dma);
|
||||
if (ret)
|
||||
goto free_irq;
|
||||
|
||||
/* Device-tree DMA controller registration */
|
||||
ret = of_dma_controller_register(dn, of_dma_sirfsoc_xlate, sdma);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to register DMA controller\n");
|
||||
goto unreg_dma_dev;
|
||||
}
|
||||
|
||||
pm_runtime_enable(&op->dev);
|
||||
dev_info(dev, "initialized SIRFSOC DMAC driver\n");
|
||||
|
||||
return 0;
|
||||
|
||||
unreg_dma_dev:
|
||||
dma_async_device_unregister(dma);
|
||||
free_irq:
|
||||
free_irq(sdma->irq, sdma);
|
||||
irq_dispose:
|
||||
irq_dispose_mapping(sdma->irq);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sirfsoc_dma_remove(struct platform_device *op)
|
||||
{
|
||||
struct device *dev = &op->dev;
|
||||
struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
|
||||
|
||||
of_dma_controller_free(op->dev.of_node);
|
||||
dma_async_device_unregister(&sdma->dma);
|
||||
free_irq(sdma->irq, sdma);
|
||||
irq_dispose_mapping(sdma->irq);
|
||||
pm_runtime_disable(&op->dev);
|
||||
if (!pm_runtime_status_suspended(&op->dev))
|
||||
sirfsoc_dma_runtime_suspend(&op->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sirfsoc_dma_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
|
||||
|
||||
clk_disable_unprepare(sdma->clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sirfsoc_dma_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(sdma->clk);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "clk_enable failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sirfsoc_dma_pm_suspend(struct device *dev)
|
||||
{
|
||||
struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
|
||||
struct sirfsoc_dma_regs *save = &sdma->regs_save;
|
||||
struct sirfsoc_dma_desc *sdesc;
|
||||
struct sirfsoc_dma_chan *schan;
|
||||
int ch;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* if we were runtime-suspended before, resume to enable clock
|
||||
* before accessing register
|
||||
*/
|
||||
if (pm_runtime_status_suspended(dev)) {
|
||||
ret = sirfsoc_dma_runtime_resume(dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* DMA controller will lose all registers while suspending
|
||||
* so we need to save registers for active channels
|
||||
*/
|
||||
for (ch = 0; ch < SIRFSOC_DMA_CHANNELS; ch++) {
|
||||
schan = &sdma->channels[ch];
|
||||
if (list_empty(&schan->active))
|
||||
continue;
|
||||
sdesc = list_first_entry(&schan->active,
|
||||
struct sirfsoc_dma_desc,
|
||||
node);
|
||||
save->ctrl[ch] = readl_relaxed(sdma->base +
|
||||
ch * 0x10 + SIRFSOC_DMA_CH_CTRL);
|
||||
}
|
||||
save->interrupt_en = readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN);
|
||||
|
||||
/* Disable clock */
|
||||
sirfsoc_dma_runtime_suspend(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sirfsoc_dma_pm_resume(struct device *dev)
|
||||
{
|
||||
struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
|
||||
struct sirfsoc_dma_regs *save = &sdma->regs_save;
|
||||
struct sirfsoc_dma_desc *sdesc;
|
||||
struct sirfsoc_dma_chan *schan;
|
||||
int ch;
|
||||
int ret;
|
||||
|
||||
/* Enable clock before accessing register */
|
||||
ret = sirfsoc_dma_runtime_resume(dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
writel_relaxed(save->interrupt_en, sdma->base + SIRFSOC_DMA_INT_EN);
|
||||
for (ch = 0; ch < SIRFSOC_DMA_CHANNELS; ch++) {
|
||||
schan = &sdma->channels[ch];
|
||||
if (list_empty(&schan->active))
|
||||
continue;
|
||||
sdesc = list_first_entry(&schan->active,
|
||||
struct sirfsoc_dma_desc,
|
||||
node);
|
||||
writel_relaxed(sdesc->width,
|
||||
sdma->base + SIRFSOC_DMA_WIDTH_0 + ch * 4);
|
||||
writel_relaxed(sdesc->xlen,
|
||||
sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_XLEN);
|
||||
writel_relaxed(sdesc->ylen,
|
||||
sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_YLEN);
|
||||
writel_relaxed(save->ctrl[ch],
|
||||
sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_CTRL);
|
||||
writel_relaxed(sdesc->addr >> 2,
|
||||
sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_ADDR);
|
||||
}
|
||||
|
||||
/* if we were runtime-suspended before, suspend again */
|
||||
if (pm_runtime_status_suspended(dev))
|
||||
sirfsoc_dma_runtime_suspend(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops sirfsoc_dma_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(sirfsoc_dma_runtime_suspend, sirfsoc_dma_runtime_resume, NULL)
|
||||
SET_SYSTEM_SLEEP_PM_OPS(sirfsoc_dma_pm_suspend, sirfsoc_dma_pm_resume)
|
||||
};
|
||||
|
||||
static struct of_device_id sirfsoc_dma_match[] = {
|
||||
{ .compatible = "sirf,prima2-dmac", },
|
||||
{ .compatible = "sirf,marco-dmac", },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver sirfsoc_dma_driver = {
|
||||
.probe = sirfsoc_dma_probe,
|
||||
.remove = sirfsoc_dma_remove,
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.pm = &sirfsoc_dma_pm_ops,
|
||||
.of_match_table = sirfsoc_dma_match,
|
||||
},
|
||||
};
|
||||
|
||||
static __init int sirfsoc_dma_init(void)
|
||||
{
|
||||
return platform_driver_register(&sirfsoc_dma_driver);
|
||||
}
|
||||
|
||||
static void __exit sirfsoc_dma_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&sirfsoc_dma_driver);
|
||||
}
|
||||
|
||||
subsys_initcall(sirfsoc_dma_init);
|
||||
module_exit(sirfsoc_dma_exit);
|
||||
|
||||
MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
|
||||
"Barry Song <baohua.song@csr.com>");
|
||||
MODULE_DESCRIPTION("SIRFSOC DMA control driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
3764
drivers/dma/ste_dma40.c
Normal file
3764
drivers/dma/ste_dma40.c
Normal file
File diff suppressed because it is too large
Load diff
448
drivers/dma/ste_dma40_ll.c
Normal file
448
drivers/dma/ste_dma40_ll.c
Normal file
|
|
@ -0,0 +1,448 @@
|
|||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2007-2010
|
||||
* Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
|
||||
* Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_data/dma-ste-dma40.h>
|
||||
|
||||
#include "ste_dma40_ll.h"
|
||||
|
||||
u8 d40_width_to_bits(enum dma_slave_buswidth width)
|
||||
{
|
||||
if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
|
||||
return STEDMA40_ESIZE_8_BIT;
|
||||
else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
|
||||
return STEDMA40_ESIZE_16_BIT;
|
||||
else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
|
||||
return STEDMA40_ESIZE_64_BIT;
|
||||
else
|
||||
return STEDMA40_ESIZE_32_BIT;
|
||||
}
|
||||
|
||||
/* Sets up proper LCSP1 and LCSP3 register for a logical channel */
|
||||
void d40_log_cfg(struct stedma40_chan_cfg *cfg,
|
||||
u32 *lcsp1, u32 *lcsp3)
|
||||
{
|
||||
u32 l3 = 0; /* dst */
|
||||
u32 l1 = 0; /* src */
|
||||
|
||||
/* src is mem? -> increase address pos */
|
||||
if (cfg->dir == DMA_MEM_TO_DEV ||
|
||||
cfg->dir == DMA_MEM_TO_MEM)
|
||||
l1 |= BIT(D40_MEM_LCSP1_SCFG_INCR_POS);
|
||||
|
||||
/* dst is mem? -> increase address pos */
|
||||
if (cfg->dir == DMA_DEV_TO_MEM ||
|
||||
cfg->dir == DMA_MEM_TO_MEM)
|
||||
l3 |= BIT(D40_MEM_LCSP3_DCFG_INCR_POS);
|
||||
|
||||
/* src is hw? -> master port 1 */
|
||||
if (cfg->dir == DMA_DEV_TO_MEM ||
|
||||
cfg->dir == DMA_DEV_TO_DEV)
|
||||
l1 |= BIT(D40_MEM_LCSP1_SCFG_MST_POS);
|
||||
|
||||
/* dst is hw? -> master port 1 */
|
||||
if (cfg->dir == DMA_MEM_TO_DEV ||
|
||||
cfg->dir == DMA_DEV_TO_DEV)
|
||||
l3 |= BIT(D40_MEM_LCSP3_DCFG_MST_POS);
|
||||
|
||||
l3 |= BIT(D40_MEM_LCSP3_DCFG_EIM_POS);
|
||||
l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
|
||||
l3 |= d40_width_to_bits(cfg->dst_info.data_width)
|
||||
<< D40_MEM_LCSP3_DCFG_ESIZE_POS;
|
||||
|
||||
l1 |= BIT(D40_MEM_LCSP1_SCFG_EIM_POS);
|
||||
l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
|
||||
l1 |= d40_width_to_bits(cfg->src_info.data_width)
|
||||
<< D40_MEM_LCSP1_SCFG_ESIZE_POS;
|
||||
|
||||
*lcsp1 = l1;
|
||||
*lcsp3 = l3;
|
||||
|
||||
}
|
||||
|
||||
void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
|
||||
{
|
||||
u32 src = 0;
|
||||
u32 dst = 0;
|
||||
|
||||
if ((cfg->dir == DMA_DEV_TO_MEM) ||
|
||||
(cfg->dir == DMA_DEV_TO_DEV)) {
|
||||
/* Set master port to 1 */
|
||||
src |= BIT(D40_SREG_CFG_MST_POS);
|
||||
src |= D40_TYPE_TO_EVENT(cfg->dev_type);
|
||||
|
||||
if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
|
||||
src |= BIT(D40_SREG_CFG_PHY_TM_POS);
|
||||
else
|
||||
src |= 3 << D40_SREG_CFG_PHY_TM_POS;
|
||||
}
|
||||
if ((cfg->dir == DMA_MEM_TO_DEV) ||
|
||||
(cfg->dir == DMA_DEV_TO_DEV)) {
|
||||
/* Set master port to 1 */
|
||||
dst |= BIT(D40_SREG_CFG_MST_POS);
|
||||
dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
|
||||
|
||||
if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
|
||||
dst |= BIT(D40_SREG_CFG_PHY_TM_POS);
|
||||
else
|
||||
dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
|
||||
}
|
||||
/* Interrupt on end of transfer for destination */
|
||||
dst |= BIT(D40_SREG_CFG_TIM_POS);
|
||||
|
||||
/* Generate interrupt on error */
|
||||
src |= BIT(D40_SREG_CFG_EIM_POS);
|
||||
dst |= BIT(D40_SREG_CFG_EIM_POS);
|
||||
|
||||
/* PSIZE */
|
||||
if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
|
||||
src |= BIT(D40_SREG_CFG_PHY_PEN_POS);
|
||||
src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
|
||||
}
|
||||
if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
|
||||
dst |= BIT(D40_SREG_CFG_PHY_PEN_POS);
|
||||
dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
|
||||
}
|
||||
|
||||
/* Element size */
|
||||
src |= d40_width_to_bits(cfg->src_info.data_width)
|
||||
<< D40_SREG_CFG_ESIZE_POS;
|
||||
dst |= d40_width_to_bits(cfg->dst_info.data_width)
|
||||
<< D40_SREG_CFG_ESIZE_POS;
|
||||
|
||||
/* Set the priority bit to high for the physical channel */
|
||||
if (cfg->high_priority) {
|
||||
src |= BIT(D40_SREG_CFG_PRI_POS);
|
||||
dst |= BIT(D40_SREG_CFG_PRI_POS);
|
||||
}
|
||||
|
||||
if (cfg->src_info.big_endian)
|
||||
src |= BIT(D40_SREG_CFG_LBE_POS);
|
||||
if (cfg->dst_info.big_endian)
|
||||
dst |= BIT(D40_SREG_CFG_LBE_POS);
|
||||
|
||||
*src_cfg = src;
|
||||
*dst_cfg = dst;
|
||||
}
|
||||
|
||||
static int d40_phy_fill_lli(struct d40_phy_lli *lli,
|
||||
dma_addr_t data,
|
||||
u32 data_size,
|
||||
dma_addr_t next_lli,
|
||||
u32 reg_cfg,
|
||||
struct stedma40_half_channel_info *info,
|
||||
unsigned int flags)
|
||||
{
|
||||
bool addr_inc = flags & LLI_ADDR_INC;
|
||||
bool term_int = flags & LLI_TERM_INT;
|
||||
unsigned int data_width = info->data_width;
|
||||
int psize = info->psize;
|
||||
int num_elems;
|
||||
|
||||
if (psize == STEDMA40_PSIZE_PHY_1)
|
||||
num_elems = 1;
|
||||
else
|
||||
num_elems = 2 << psize;
|
||||
|
||||
/* Must be aligned */
|
||||
if (!IS_ALIGNED(data, data_width))
|
||||
return -EINVAL;
|
||||
|
||||
/* Transfer size can't be smaller than (num_elms * elem_size) */
|
||||
if (data_size < num_elems * data_width)
|
||||
return -EINVAL;
|
||||
|
||||
/* The number of elements. IE now many chunks */
|
||||
lli->reg_elt = (data_size / data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
|
||||
|
||||
/*
|
||||
* Distance to next element sized entry.
|
||||
* Usually the size of the element unless you want gaps.
|
||||
*/
|
||||
if (addr_inc)
|
||||
lli->reg_elt |= data_width << D40_SREG_ELEM_PHY_EIDX_POS;
|
||||
|
||||
/* Where the data is */
|
||||
lli->reg_ptr = data;
|
||||
lli->reg_cfg = reg_cfg;
|
||||
|
||||
/* If this scatter list entry is the last one, no next link */
|
||||
if (next_lli == 0)
|
||||
lli->reg_lnk = BIT(D40_SREG_LNK_PHY_TCP_POS);
|
||||
else
|
||||
lli->reg_lnk = next_lli;
|
||||
|
||||
/* Set/clear interrupt generation on this link item.*/
|
||||
if (term_int)
|
||||
lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS);
|
||||
else
|
||||
lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
|
||||
|
||||
/*
|
||||
* Post link - D40_SREG_LNK_PHY_PRE_POS = 0
|
||||
* Relink happens after transfer completion.
|
||||
*/
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int d40_seg_size(int size, int data_width1, int data_width2)
|
||||
{
|
||||
u32 max_w = max(data_width1, data_width2);
|
||||
u32 min_w = min(data_width1, data_width2);
|
||||
u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
|
||||
|
||||
if (seg_max > STEDMA40_MAX_SEG_SIZE)
|
||||
seg_max -= max_w;
|
||||
|
||||
if (size <= seg_max)
|
||||
return size;
|
||||
|
||||
if (size <= 2 * seg_max)
|
||||
return ALIGN(size / 2, max_w);
|
||||
|
||||
return seg_max;
|
||||
}
|
||||
|
||||
static struct d40_phy_lli *
|
||||
d40_phy_buf_to_lli(struct d40_phy_lli *lli, dma_addr_t addr, u32 size,
|
||||
dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg,
|
||||
struct stedma40_half_channel_info *info,
|
||||
struct stedma40_half_channel_info *otherinfo,
|
||||
unsigned long flags)
|
||||
{
|
||||
bool lastlink = flags & LLI_LAST_LINK;
|
||||
bool addr_inc = flags & LLI_ADDR_INC;
|
||||
bool term_int = flags & LLI_TERM_INT;
|
||||
bool cyclic = flags & LLI_CYCLIC;
|
||||
int err;
|
||||
dma_addr_t next = lli_phys;
|
||||
int size_rest = size;
|
||||
int size_seg = 0;
|
||||
|
||||
/*
|
||||
* This piece may be split up based on d40_seg_size(); we only want the
|
||||
* term int on the last part.
|
||||
*/
|
||||
if (term_int)
|
||||
flags &= ~LLI_TERM_INT;
|
||||
|
||||
do {
|
||||
size_seg = d40_seg_size(size_rest, info->data_width,
|
||||
otherinfo->data_width);
|
||||
size_rest -= size_seg;
|
||||
|
||||
if (size_rest == 0 && term_int)
|
||||
flags |= LLI_TERM_INT;
|
||||
|
||||
if (size_rest == 0 && lastlink)
|
||||
next = cyclic ? first_phys : 0;
|
||||
else
|
||||
next = ALIGN(next + sizeof(struct d40_phy_lli),
|
||||
D40_LLI_ALIGN);
|
||||
|
||||
err = d40_phy_fill_lli(lli, addr, size_seg, next,
|
||||
reg_cfg, info, flags);
|
||||
|
||||
if (err)
|
||||
goto err;
|
||||
|
||||
lli++;
|
||||
if (addr_inc)
|
||||
addr += size_seg;
|
||||
} while (size_rest);
|
||||
|
||||
return lli;
|
||||
|
||||
err:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int d40_phy_sg_to_lli(struct scatterlist *sg,
|
||||
int sg_len,
|
||||
dma_addr_t target,
|
||||
struct d40_phy_lli *lli_sg,
|
||||
dma_addr_t lli_phys,
|
||||
u32 reg_cfg,
|
||||
struct stedma40_half_channel_info *info,
|
||||
struct stedma40_half_channel_info *otherinfo,
|
||||
unsigned long flags)
|
||||
{
|
||||
int total_size = 0;
|
||||
int i;
|
||||
struct scatterlist *current_sg = sg;
|
||||
struct d40_phy_lli *lli = lli_sg;
|
||||
dma_addr_t l_phys = lli_phys;
|
||||
|
||||
if (!target)
|
||||
flags |= LLI_ADDR_INC;
|
||||
|
||||
for_each_sg(sg, current_sg, sg_len, i) {
|
||||
dma_addr_t sg_addr = sg_dma_address(current_sg);
|
||||
unsigned int len = sg_dma_len(current_sg);
|
||||
dma_addr_t dst = target ?: sg_addr;
|
||||
|
||||
total_size += sg_dma_len(current_sg);
|
||||
|
||||
if (i == sg_len - 1)
|
||||
flags |= LLI_TERM_INT | LLI_LAST_LINK;
|
||||
|
||||
l_phys = ALIGN(lli_phys + (lli - lli_sg) *
|
||||
sizeof(struct d40_phy_lli), D40_LLI_ALIGN);
|
||||
|
||||
lli = d40_phy_buf_to_lli(lli, dst, len, l_phys, lli_phys,
|
||||
reg_cfg, info, otherinfo, flags);
|
||||
|
||||
if (lli == NULL)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return total_size;
|
||||
}
|
||||
|
||||
|
||||
/* DMA logical lli operations */
|
||||
|
||||
static void d40_log_lli_link(struct d40_log_lli *lli_dst,
|
||||
struct d40_log_lli *lli_src,
|
||||
int next, unsigned int flags)
|
||||
{
|
||||
bool interrupt = flags & LLI_TERM_INT;
|
||||
u32 slos = 0;
|
||||
u32 dlos = 0;
|
||||
|
||||
if (next != -EINVAL) {
|
||||
slos = next * 2;
|
||||
dlos = next * 2 + 1;
|
||||
}
|
||||
|
||||
if (interrupt) {
|
||||
lli_dst->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
|
||||
lli_dst->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
|
||||
}
|
||||
|
||||
lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
|
||||
(slos << D40_MEM_LCSP1_SLOS_POS);
|
||||
|
||||
lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
|
||||
(dlos << D40_MEM_LCSP1_SLOS_POS);
|
||||
}
|
||||
|
||||
void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
|
||||
struct d40_log_lli *lli_dst,
|
||||
struct d40_log_lli *lli_src,
|
||||
int next, unsigned int flags)
|
||||
{
|
||||
d40_log_lli_link(lli_dst, lli_src, next, flags);
|
||||
|
||||
writel_relaxed(lli_src->lcsp02, &lcpa[0].lcsp0);
|
||||
writel_relaxed(lli_src->lcsp13, &lcpa[0].lcsp1);
|
||||
writel_relaxed(lli_dst->lcsp02, &lcpa[0].lcsp2);
|
||||
writel_relaxed(lli_dst->lcsp13, &lcpa[0].lcsp3);
|
||||
}
|
||||
|
||||
void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
|
||||
struct d40_log_lli *lli_dst,
|
||||
struct d40_log_lli *lli_src,
|
||||
int next, unsigned int flags)
|
||||
{
|
||||
d40_log_lli_link(lli_dst, lli_src, next, flags);
|
||||
|
||||
writel_relaxed(lli_src->lcsp02, &lcla[0].lcsp02);
|
||||
writel_relaxed(lli_src->lcsp13, &lcla[0].lcsp13);
|
||||
writel_relaxed(lli_dst->lcsp02, &lcla[1].lcsp02);
|
||||
writel_relaxed(lli_dst->lcsp13, &lcla[1].lcsp13);
|
||||
}
|
||||
|
||||
static void d40_log_fill_lli(struct d40_log_lli *lli,
|
||||
dma_addr_t data, u32 data_size,
|
||||
u32 reg_cfg,
|
||||
u32 data_width,
|
||||
unsigned int flags)
|
||||
{
|
||||
bool addr_inc = flags & LLI_ADDR_INC;
|
||||
|
||||
lli->lcsp13 = reg_cfg;
|
||||
|
||||
/* The number of elements to transfer */
|
||||
lli->lcsp02 = ((data_size / data_width) <<
|
||||
D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
|
||||
|
||||
BUG_ON((data_size / data_width) > STEDMA40_MAX_SEG_SIZE);
|
||||
|
||||
/* 16 LSBs address of the current element */
|
||||
lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
|
||||
/* 16 MSBs address of the current element */
|
||||
lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;
|
||||
|
||||
if (addr_inc)
|
||||
lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;
|
||||
|
||||
}
|
||||
|
||||
static struct d40_log_lli *d40_log_buf_to_lli(struct d40_log_lli *lli_sg,
|
||||
dma_addr_t addr,
|
||||
int size,
|
||||
u32 lcsp13, /* src or dst*/
|
||||
u32 data_width1,
|
||||
u32 data_width2,
|
||||
unsigned int flags)
|
||||
{
|
||||
bool addr_inc = flags & LLI_ADDR_INC;
|
||||
struct d40_log_lli *lli = lli_sg;
|
||||
int size_rest = size;
|
||||
int size_seg = 0;
|
||||
|
||||
do {
|
||||
size_seg = d40_seg_size(size_rest, data_width1, data_width2);
|
||||
size_rest -= size_seg;
|
||||
|
||||
d40_log_fill_lli(lli,
|
||||
addr,
|
||||
size_seg,
|
||||
lcsp13, data_width1,
|
||||
flags);
|
||||
if (addr_inc)
|
||||
addr += size_seg;
|
||||
lli++;
|
||||
} while (size_rest);
|
||||
|
||||
return lli;
|
||||
}
|
||||
|
||||
int d40_log_sg_to_lli(struct scatterlist *sg,
|
||||
int sg_len,
|
||||
dma_addr_t dev_addr,
|
||||
struct d40_log_lli *lli_sg,
|
||||
u32 lcsp13, /* src or dst*/
|
||||
u32 data_width1, u32 data_width2)
|
||||
{
|
||||
int total_size = 0;
|
||||
struct scatterlist *current_sg = sg;
|
||||
int i;
|
||||
struct d40_log_lli *lli = lli_sg;
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (!dev_addr)
|
||||
flags |= LLI_ADDR_INC;
|
||||
|
||||
for_each_sg(sg, current_sg, sg_len, i) {
|
||||
dma_addr_t sg_addr = sg_dma_address(current_sg);
|
||||
unsigned int len = sg_dma_len(current_sg);
|
||||
dma_addr_t addr = dev_addr ?: sg_addr;
|
||||
|
||||
total_size += sg_dma_len(current_sg);
|
||||
|
||||
lli = d40_log_buf_to_lli(lli, addr, len,
|
||||
lcsp13,
|
||||
data_width1,
|
||||
data_width2,
|
||||
flags);
|
||||
}
|
||||
|
||||
return total_size;
|
||||
}
|
||||
470
drivers/dma/ste_dma40_ll.h
Normal file
470
drivers/dma/ste_dma40_ll.h
Normal file
|
|
@ -0,0 +1,470 @@
|
|||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2007-2010
|
||||
* Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson SA
|
||||
* Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson SA
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
*/
|
||||
#ifndef STE_DMA40_LL_H
|
||||
#define STE_DMA40_LL_H
|
||||
|
||||
#define D40_DREG_PCBASE 0x400
|
||||
#define D40_DREG_PCDELTA (8 * 4)
|
||||
#define D40_LLI_ALIGN 16 /* LLI alignment must be 16 bytes. */
|
||||
|
||||
#define D40_LCPA_CHAN_SIZE 32
|
||||
#define D40_LCPA_CHAN_DST_DELTA 16
|
||||
|
||||
#define D40_TYPE_TO_GROUP(type) (type / 16)
|
||||
#define D40_TYPE_TO_EVENT(type) (type % 16)
|
||||
#define D40_GROUP_SIZE 8
|
||||
#define D40_PHYS_TO_GROUP(phys) ((phys & (D40_GROUP_SIZE - 1)) / 2)
|
||||
|
||||
/* Most bits of the CFG register are the same in log as in phy mode */
|
||||
#define D40_SREG_CFG_MST_POS 15
|
||||
#define D40_SREG_CFG_TIM_POS 14
|
||||
#define D40_SREG_CFG_EIM_POS 13
|
||||
#define D40_SREG_CFG_LOG_INCR_POS 12
|
||||
#define D40_SREG_CFG_PHY_PEN_POS 12
|
||||
#define D40_SREG_CFG_PSIZE_POS 10
|
||||
#define D40_SREG_CFG_ESIZE_POS 8
|
||||
#define D40_SREG_CFG_PRI_POS 7
|
||||
#define D40_SREG_CFG_LBE_POS 6
|
||||
#define D40_SREG_CFG_LOG_GIM_POS 5
|
||||
#define D40_SREG_CFG_LOG_MFU_POS 4
|
||||
#define D40_SREG_CFG_PHY_TM_POS 4
|
||||
#define D40_SREG_CFG_PHY_EVTL_POS 0
|
||||
|
||||
|
||||
/* Standard channel parameters - basic mode (element register) */
|
||||
#define D40_SREG_ELEM_PHY_ECNT_POS 16
|
||||
#define D40_SREG_ELEM_PHY_EIDX_POS 0
|
||||
|
||||
#define D40_SREG_ELEM_PHY_ECNT_MASK (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)
|
||||
|
||||
/* Standard channel parameters - basic mode (Link register) */
|
||||
#define D40_SREG_LNK_PHY_TCP_POS 0
|
||||
#define D40_SREG_LNK_PHY_LMP_POS 1
|
||||
#define D40_SREG_LNK_PHY_PRE_POS 2
|
||||
/*
|
||||
* Source destination link address. Contains the
|
||||
* 29-bit byte word aligned address of the reload area.
|
||||
*/
|
||||
#define D40_SREG_LNK_PHYS_LNK_MASK 0xFFFFFFF8UL
|
||||
|
||||
/* Standard basic channel logical mode */
|
||||
|
||||
/* Element register */
|
||||
#define D40_SREG_ELEM_LOG_ECNT_POS 16
|
||||
#define D40_SREG_ELEM_LOG_LIDX_POS 8
|
||||
#define D40_SREG_ELEM_LOG_LOS_POS 1
|
||||
#define D40_SREG_ELEM_LOG_TCP_POS 0
|
||||
|
||||
#define D40_SREG_ELEM_LOG_LIDX_MASK (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
|
||||
|
||||
/* Link register */
|
||||
#define D40_EVENTLINE_POS(i) (2 * i)
|
||||
#define D40_EVENTLINE_MASK(i) (0x3 << D40_EVENTLINE_POS(i))
|
||||
|
||||
/* Standard basic channel logical params in memory */
|
||||
|
||||
/* LCSP0 */
|
||||
#define D40_MEM_LCSP0_ECNT_POS 16
|
||||
#define D40_MEM_LCSP0_SPTR_POS 0
|
||||
|
||||
#define D40_MEM_LCSP0_ECNT_MASK (0xFFFF << D40_MEM_LCSP0_ECNT_POS)
|
||||
#define D40_MEM_LCSP0_SPTR_MASK (0xFFFF << D40_MEM_LCSP0_SPTR_POS)
|
||||
|
||||
/* LCSP1 */
|
||||
#define D40_MEM_LCSP1_SPTR_POS 16
|
||||
#define D40_MEM_LCSP1_SCFG_MST_POS 15
|
||||
#define D40_MEM_LCSP1_SCFG_TIM_POS 14
|
||||
#define D40_MEM_LCSP1_SCFG_EIM_POS 13
|
||||
#define D40_MEM_LCSP1_SCFG_INCR_POS 12
|
||||
#define D40_MEM_LCSP1_SCFG_PSIZE_POS 10
|
||||
#define D40_MEM_LCSP1_SCFG_ESIZE_POS 8
|
||||
#define D40_MEM_LCSP1_SLOS_POS 1
|
||||
#define D40_MEM_LCSP1_STCP_POS 0
|
||||
|
||||
#define D40_MEM_LCSP1_SPTR_MASK (0xFFFF << D40_MEM_LCSP1_SPTR_POS)
|
||||
#define D40_MEM_LCSP1_SCFG_TIM_MASK (0x1 << D40_MEM_LCSP1_SCFG_TIM_POS)
|
||||
#define D40_MEM_LCSP1_SCFG_INCR_MASK (0x1 << D40_MEM_LCSP1_SCFG_INCR_POS)
|
||||
#define D40_MEM_LCSP1_SCFG_PSIZE_MASK (0x3 << D40_MEM_LCSP1_SCFG_PSIZE_POS)
|
||||
#define D40_MEM_LCSP1_SLOS_MASK (0x7F << D40_MEM_LCSP1_SLOS_POS)
|
||||
#define D40_MEM_LCSP1_STCP_MASK (0x1 << D40_MEM_LCSP1_STCP_POS)
|
||||
|
||||
/* LCSP2 */
|
||||
#define D40_MEM_LCSP2_ECNT_POS 16
|
||||
|
||||
#define D40_MEM_LCSP2_ECNT_MASK (0xFFFF << D40_MEM_LCSP2_ECNT_POS)
|
||||
|
||||
/* LCSP3 */
|
||||
#define D40_MEM_LCSP3_DCFG_MST_POS 15
|
||||
#define D40_MEM_LCSP3_DCFG_TIM_POS 14
|
||||
#define D40_MEM_LCSP3_DCFG_EIM_POS 13
|
||||
#define D40_MEM_LCSP3_DCFG_INCR_POS 12
|
||||
#define D40_MEM_LCSP3_DCFG_PSIZE_POS 10
|
||||
#define D40_MEM_LCSP3_DCFG_ESIZE_POS 8
|
||||
#define D40_MEM_LCSP3_DLOS_POS 1
|
||||
#define D40_MEM_LCSP3_DTCP_POS 0
|
||||
|
||||
#define D40_MEM_LCSP3_DLOS_MASK (0x7F << D40_MEM_LCSP3_DLOS_POS)
|
||||
#define D40_MEM_LCSP3_DTCP_MASK (0x1 << D40_MEM_LCSP3_DTCP_POS)
|
||||
|
||||
|
||||
/* Standard channel parameter register offsets */
|
||||
#define D40_CHAN_REG_SSCFG 0x00
|
||||
#define D40_CHAN_REG_SSELT 0x04
|
||||
#define D40_CHAN_REG_SSPTR 0x08
|
||||
#define D40_CHAN_REG_SSLNK 0x0C
|
||||
#define D40_CHAN_REG_SDCFG 0x10
|
||||
#define D40_CHAN_REG_SDELT 0x14
|
||||
#define D40_CHAN_REG_SDPTR 0x18
|
||||
#define D40_CHAN_REG_SDLNK 0x1C
|
||||
|
||||
/* DMA Register Offsets */
|
||||
#define D40_DREG_GCC 0x000
|
||||
#define D40_DREG_GCC_ENA 0x1
|
||||
/* This assumes that there are only 4 event groups */
|
||||
#define D40_DREG_GCC_ENABLE_ALL 0x3ff01
|
||||
#define D40_DREG_GCC_EVTGRP_POS 8
|
||||
#define D40_DREG_GCC_SRC 0
|
||||
#define D40_DREG_GCC_DST 1
|
||||
#define D40_DREG_GCC_EVTGRP_ENA(x, y) \
|
||||
(1 << (D40_DREG_GCC_EVTGRP_POS + 2 * x + y))
|
||||
|
||||
#define D40_DREG_PRTYP 0x004
|
||||
#define D40_DREG_PRSME 0x008
|
||||
#define D40_DREG_PRSMO 0x00C
|
||||
#define D40_DREG_PRMSE 0x010
|
||||
#define D40_DREG_PRMSO 0x014
|
||||
#define D40_DREG_PRMOE 0x018
|
||||
#define D40_DREG_PRMOO 0x01C
|
||||
#define D40_DREG_PRMO_PCHAN_BASIC 0x1
|
||||
#define D40_DREG_PRMO_PCHAN_MODULO 0x2
|
||||
#define D40_DREG_PRMO_PCHAN_DOUBLE_DST 0x3
|
||||
#define D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG 0x1
|
||||
#define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY 0x2
|
||||
#define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG 0x3
|
||||
|
||||
#define D40_DREG_LCPA 0x020
|
||||
#define D40_DREG_LCLA 0x024
|
||||
|
||||
#define D40_DREG_SSEG1 0x030
|
||||
#define D40_DREG_SSEG2 0x034
|
||||
#define D40_DREG_SSEG3 0x038
|
||||
#define D40_DREG_SSEG4 0x03C
|
||||
|
||||
#define D40_DREG_SCEG1 0x040
|
||||
#define D40_DREG_SCEG2 0x044
|
||||
#define D40_DREG_SCEG3 0x048
|
||||
#define D40_DREG_SCEG4 0x04C
|
||||
|
||||
#define D40_DREG_ACTIVE 0x050
|
||||
#define D40_DREG_ACTIVO 0x054
|
||||
#define D40_DREG_CIDMOD 0x058
|
||||
#define D40_DREG_TCIDV 0x05C
|
||||
#define D40_DREG_PCMIS 0x060
|
||||
#define D40_DREG_PCICR 0x064
|
||||
#define D40_DREG_PCTIS 0x068
|
||||
#define D40_DREG_PCEIS 0x06C
|
||||
|
||||
#define D40_DREG_SPCMIS 0x070
|
||||
#define D40_DREG_SPCICR 0x074
|
||||
#define D40_DREG_SPCTIS 0x078
|
||||
#define D40_DREG_SPCEIS 0x07C
|
||||
|
||||
#define D40_DREG_LCMIS0 0x080
|
||||
#define D40_DREG_LCMIS1 0x084
|
||||
#define D40_DREG_LCMIS2 0x088
|
||||
#define D40_DREG_LCMIS3 0x08C
|
||||
#define D40_DREG_LCICR0 0x090
|
||||
#define D40_DREG_LCICR1 0x094
|
||||
#define D40_DREG_LCICR2 0x098
|
||||
#define D40_DREG_LCICR3 0x09C
|
||||
#define D40_DREG_LCTIS0 0x0A0
|
||||
#define D40_DREG_LCTIS1 0x0A4
|
||||
#define D40_DREG_LCTIS2 0x0A8
|
||||
#define D40_DREG_LCTIS3 0x0AC
|
||||
#define D40_DREG_LCEIS0 0x0B0
|
||||
#define D40_DREG_LCEIS1 0x0B4
|
||||
#define D40_DREG_LCEIS2 0x0B8
|
||||
#define D40_DREG_LCEIS3 0x0BC
|
||||
|
||||
#define D40_DREG_SLCMIS1 0x0C0
|
||||
#define D40_DREG_SLCMIS2 0x0C4
|
||||
#define D40_DREG_SLCMIS3 0x0C8
|
||||
#define D40_DREG_SLCMIS4 0x0CC
|
||||
|
||||
#define D40_DREG_SLCICR1 0x0D0
|
||||
#define D40_DREG_SLCICR2 0x0D4
|
||||
#define D40_DREG_SLCICR3 0x0D8
|
||||
#define D40_DREG_SLCICR4 0x0DC
|
||||
|
||||
#define D40_DREG_SLCTIS1 0x0E0
|
||||
#define D40_DREG_SLCTIS2 0x0E4
|
||||
#define D40_DREG_SLCTIS3 0x0E8
|
||||
#define D40_DREG_SLCTIS4 0x0EC
|
||||
|
||||
#define D40_DREG_SLCEIS1 0x0F0
|
||||
#define D40_DREG_SLCEIS2 0x0F4
|
||||
#define D40_DREG_SLCEIS3 0x0F8
|
||||
#define D40_DREG_SLCEIS4 0x0FC
|
||||
|
||||
#define D40_DREG_FSESS1 0x100
|
||||
#define D40_DREG_FSESS2 0x104
|
||||
|
||||
#define D40_DREG_FSEBS1 0x108
|
||||
#define D40_DREG_FSEBS2 0x10C
|
||||
|
||||
#define D40_DREG_PSEG1 0x110
|
||||
#define D40_DREG_PSEG2 0x114
|
||||
#define D40_DREG_PSEG3 0x118
|
||||
#define D40_DREG_PSEG4 0x11C
|
||||
#define D40_DREG_PCEG1 0x120
|
||||
#define D40_DREG_PCEG2 0x124
|
||||
#define D40_DREG_PCEG3 0x128
|
||||
#define D40_DREG_PCEG4 0x12C
|
||||
#define D40_DREG_RSEG1 0x130
|
||||
#define D40_DREG_RSEG2 0x134
|
||||
#define D40_DREG_RSEG3 0x138
|
||||
#define D40_DREG_RSEG4 0x13C
|
||||
#define D40_DREG_RCEG1 0x140
|
||||
#define D40_DREG_RCEG2 0x144
|
||||
#define D40_DREG_RCEG3 0x148
|
||||
#define D40_DREG_RCEG4 0x14C
|
||||
|
||||
#define D40_DREG_PREFOT 0x15C
|
||||
#define D40_DREG_EXTCFG 0x160
|
||||
|
||||
#define D40_DREG_CPSEG1 0x200
|
||||
#define D40_DREG_CPSEG2 0x204
|
||||
#define D40_DREG_CPSEG3 0x208
|
||||
#define D40_DREG_CPSEG4 0x20C
|
||||
#define D40_DREG_CPSEG5 0x210
|
||||
|
||||
#define D40_DREG_CPCEG1 0x220
|
||||
#define D40_DREG_CPCEG2 0x224
|
||||
#define D40_DREG_CPCEG3 0x228
|
||||
#define D40_DREG_CPCEG4 0x22C
|
||||
#define D40_DREG_CPCEG5 0x230
|
||||
|
||||
#define D40_DREG_CRSEG1 0x240
|
||||
#define D40_DREG_CRSEG2 0x244
|
||||
#define D40_DREG_CRSEG3 0x248
|
||||
#define D40_DREG_CRSEG4 0x24C
|
||||
#define D40_DREG_CRSEG5 0x250
|
||||
|
||||
#define D40_DREG_CRCEG1 0x260
|
||||
#define D40_DREG_CRCEG2 0x264
|
||||
#define D40_DREG_CRCEG3 0x268
|
||||
#define D40_DREG_CRCEG4 0x26C
|
||||
#define D40_DREG_CRCEG5 0x270
|
||||
|
||||
#define D40_DREG_CFSESS1 0x280
|
||||
#define D40_DREG_CFSESS2 0x284
|
||||
#define D40_DREG_CFSESS3 0x288
|
||||
|
||||
#define D40_DREG_CFSEBS1 0x290
|
||||
#define D40_DREG_CFSEBS2 0x294
|
||||
#define D40_DREG_CFSEBS3 0x298
|
||||
|
||||
#define D40_DREG_CLCMIS1 0x300
|
||||
#define D40_DREG_CLCMIS2 0x304
|
||||
#define D40_DREG_CLCMIS3 0x308
|
||||
#define D40_DREG_CLCMIS4 0x30C
|
||||
#define D40_DREG_CLCMIS5 0x310
|
||||
|
||||
#define D40_DREG_CLCICR1 0x320
|
||||
#define D40_DREG_CLCICR2 0x324
|
||||
#define D40_DREG_CLCICR3 0x328
|
||||
#define D40_DREG_CLCICR4 0x32C
|
||||
#define D40_DREG_CLCICR5 0x330
|
||||
|
||||
#define D40_DREG_CLCTIS1 0x340
|
||||
#define D40_DREG_CLCTIS2 0x344
|
||||
#define D40_DREG_CLCTIS3 0x348
|
||||
#define D40_DREG_CLCTIS4 0x34C
|
||||
#define D40_DREG_CLCTIS5 0x350
|
||||
|
||||
#define D40_DREG_CLCEIS1 0x360
|
||||
#define D40_DREG_CLCEIS2 0x364
|
||||
#define D40_DREG_CLCEIS3 0x368
|
||||
#define D40_DREG_CLCEIS4 0x36C
|
||||
#define D40_DREG_CLCEIS5 0x370
|
||||
|
||||
#define D40_DREG_CPCMIS 0x380
|
||||
#define D40_DREG_CPCICR 0x384
|
||||
#define D40_DREG_CPCTIS 0x388
|
||||
#define D40_DREG_CPCEIS 0x38C
|
||||
|
||||
#define D40_DREG_SCCIDA1 0xE80
|
||||
#define D40_DREG_SCCIDA2 0xE90
|
||||
#define D40_DREG_SCCIDA3 0xEA0
|
||||
#define D40_DREG_SCCIDA4 0xEB0
|
||||
#define D40_DREG_SCCIDA5 0xEC0
|
||||
|
||||
#define D40_DREG_SCCIDB1 0xE84
|
||||
#define D40_DREG_SCCIDB2 0xE94
|
||||
#define D40_DREG_SCCIDB3 0xEA4
|
||||
#define D40_DREG_SCCIDB4 0xEB4
|
||||
#define D40_DREG_SCCIDB5 0xEC4
|
||||
|
||||
#define D40_DREG_PRSCCIDA 0xF80
|
||||
#define D40_DREG_PRSCCIDB 0xF84
|
||||
|
||||
#define D40_DREG_STFU 0xFC8
|
||||
#define D40_DREG_ICFG 0xFCC
|
||||
#define D40_DREG_PERIPHID0 0xFE0
|
||||
#define D40_DREG_PERIPHID1 0xFE4
|
||||
#define D40_DREG_PERIPHID2 0xFE8
|
||||
#define D40_DREG_PERIPHID3 0xFEC
|
||||
#define D40_DREG_CELLID0 0xFF0
|
||||
#define D40_DREG_CELLID1 0xFF4
|
||||
#define D40_DREG_CELLID2 0xFF8
|
||||
#define D40_DREG_CELLID3 0xFFC
|
||||
|
||||
/* LLI related structures */
|
||||
|
||||
/**
|
||||
* struct d40_phy_lli - The basic configuration register for each physical
|
||||
* channel.
|
||||
*
|
||||
* @reg_cfg: The configuration register.
|
||||
* @reg_elt: The element register.
|
||||
* @reg_ptr: The pointer register.
|
||||
* @reg_lnk: The link register.
|
||||
*
|
||||
* These registers are set up for both physical and logical transfers
|
||||
* Note that the bit in each register means differently in logical and
|
||||
* physical(standard) mode.
|
||||
*
|
||||
* This struct must be 16 bytes aligned, and only contain physical registers
|
||||
* since it will be directly accessed by the DMA.
|
||||
*/
|
||||
struct d40_phy_lli {
|
||||
u32 reg_cfg;
|
||||
u32 reg_elt;
|
||||
u32 reg_ptr;
|
||||
u32 reg_lnk;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct d40_phy_lli_bidir - struct for a transfer.
|
||||
*
|
||||
* @src: Register settings for src channel.
|
||||
* @dst: Register settings for dst channel.
|
||||
*
|
||||
* All DMA transfers have a source and a destination.
|
||||
*/
|
||||
|
||||
struct d40_phy_lli_bidir {
|
||||
struct d40_phy_lli *src;
|
||||
struct d40_phy_lli *dst;
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* struct d40_log_lli - logical lli configuration
|
||||
*
|
||||
* @lcsp02: Either maps to register lcsp0 if src or lcsp2 if dst.
|
||||
* @lcsp13: Either maps to register lcsp1 if src or lcsp3 if dst.
|
||||
*
|
||||
* This struct must be 8 bytes aligned since it will be accessed directy by
|
||||
* the DMA. Never add any none hw mapped registers to this struct.
|
||||
*/
|
||||
|
||||
struct d40_log_lli {
|
||||
u32 lcsp02;
|
||||
u32 lcsp13;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct d40_log_lli_bidir - For both src and dst
|
||||
*
|
||||
* @src: pointer to src lli configuration.
|
||||
* @dst: pointer to dst lli configuration.
|
||||
*
|
||||
* You always have a src and a dst when doing DMA transfers.
|
||||
*/
|
||||
|
||||
struct d40_log_lli_bidir {
|
||||
struct d40_log_lli *src;
|
||||
struct d40_log_lli *dst;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct d40_log_lli_full - LCPA layout
|
||||
*
|
||||
* @lcsp0: Logical Channel Standard Param 0 - Src.
|
||||
* @lcsp1: Logical Channel Standard Param 1 - Src.
|
||||
* @lcsp2: Logical Channel Standard Param 2 - Dst.
|
||||
* @lcsp3: Logical Channel Standard Param 3 - Dst.
|
||||
*
|
||||
* This struct maps to LCPA physical memory layout. Must map to
|
||||
* the hw.
|
||||
*/
|
||||
struct d40_log_lli_full {
|
||||
u32 lcsp0;
|
||||
u32 lcsp1;
|
||||
u32 lcsp2;
|
||||
u32 lcsp3;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct d40_def_lcsp - Default LCSP1 and LCSP3 settings
|
||||
*
|
||||
* @lcsp3: The default configuration for dst.
|
||||
* @lcsp1: The default configuration for src.
|
||||
*/
|
||||
struct d40_def_lcsp {
|
||||
u32 lcsp3;
|
||||
u32 lcsp1;
|
||||
};
|
||||
|
||||
/* Physical channels */
|
||||
|
||||
enum d40_lli_flags {
|
||||
LLI_ADDR_INC = 1 << 0,
|
||||
LLI_TERM_INT = 1 << 1,
|
||||
LLI_CYCLIC = 1 << 2,
|
||||
LLI_LAST_LINK = 1 << 3,
|
||||
};
|
||||
|
||||
void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
|
||||
u32 *src_cfg,
|
||||
u32 *dst_cfg);
|
||||
|
||||
void d40_log_cfg(struct stedma40_chan_cfg *cfg,
|
||||
u32 *lcsp1,
|
||||
u32 *lcsp2);
|
||||
|
||||
int d40_phy_sg_to_lli(struct scatterlist *sg,
|
||||
int sg_len,
|
||||
dma_addr_t target,
|
||||
struct d40_phy_lli *lli,
|
||||
dma_addr_t lli_phys,
|
||||
u32 reg_cfg,
|
||||
struct stedma40_half_channel_info *info,
|
||||
struct stedma40_half_channel_info *otherinfo,
|
||||
unsigned long flags);
|
||||
|
||||
/* Logical channels */
|
||||
|
||||
int d40_log_sg_to_lli(struct scatterlist *sg,
|
||||
int sg_len,
|
||||
dma_addr_t dev_addr,
|
||||
struct d40_log_lli *lli_sg,
|
||||
u32 lcsp13, /* src or dst*/
|
||||
u32 data_width1, u32 data_width2);
|
||||
|
||||
void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
|
||||
struct d40_log_lli *lli_dst,
|
||||
struct d40_log_lli *lli_src,
|
||||
int next, unsigned int flags);
|
||||
|
||||
void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
|
||||
struct d40_log_lli *lli_dst,
|
||||
struct d40_log_lli *lli_src,
|
||||
int next, unsigned int flags);
|
||||
|
||||
#endif /* STE_DMA40_LLI_H */
|
||||
1029
drivers/dma/sun6i-dma.c
Normal file
1029
drivers/dma/sun6i-dma.c
Normal file
File diff suppressed because it is too large
Load diff
1613
drivers/dma/tegra20-apb-dma.c
Normal file
1613
drivers/dma/tegra20-apb-dma.c
Normal file
File diff suppressed because it is too large
Load diff
Some files were not shown because too many files have changed in this diff Show more
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Add table
Add a link
Reference in a new issue