mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
386
drivers/gpio/gpio-cs5535.c
Normal file
386
drivers/gpio/gpio-cs5535.c
Normal file
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@ -0,0 +1,386 @@
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/*
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* AMD CS5535/CS5536 GPIO driver
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* Copyright (C) 2006 Advanced Micro Devices, Inc.
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* Copyright (C) 2007-2009 Andres Salomon <dilinger@collabora.co.uk>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/cs5535.h>
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#include <asm/msr.h>
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#define DRV_NAME "cs5535-gpio"
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/*
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* Some GPIO pins
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* 31-29,23 : reserved (always mask out)
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* 28 : Power Button
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* 26 : PME#
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* 22-16 : LPC
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* 14,15 : SMBus
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* 9,8 : UART1
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* 7 : PCI INTB
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* 3,4 : UART2/DDC
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* 2 : IDE_IRQ0
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* 1 : AC_BEEP
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* 0 : PCI INTA
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*
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* If a mask was not specified, allow all except
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* reserved and Power Button
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*/
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#define GPIO_DEFAULT_MASK 0x0F7FFFFF
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static ulong mask = GPIO_DEFAULT_MASK;
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module_param_named(mask, mask, ulong, 0444);
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MODULE_PARM_DESC(mask, "GPIO channel mask.");
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static struct cs5535_gpio_chip {
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struct gpio_chip chip;
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resource_size_t base;
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struct platform_device *pdev;
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spinlock_t lock;
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} cs5535_gpio_chip;
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/*
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* The CS5535/CS5536 GPIOs support a number of extra features not defined
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* by the gpio_chip API, so these are exported. For a full list of the
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* registers, see include/linux/cs5535.h.
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*/
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static void errata_outl(struct cs5535_gpio_chip *chip, u32 val,
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unsigned int reg)
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{
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unsigned long addr = chip->base + 0x80 + reg;
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/*
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* According to the CS5536 errata (#36), after suspend
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* a write to the high bank GPIO register will clear all
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* non-selected bits; the recommended workaround is a
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* read-modify-write operation.
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*
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* Don't apply this errata to the edge status GPIOs, as writing
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* to their lower bits will clear them.
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*/
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if (reg != GPIO_POSITIVE_EDGE_STS && reg != GPIO_NEGATIVE_EDGE_STS) {
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if (val & 0xffff)
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val |= (inl(addr) & 0xffff); /* ignore the high bits */
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else
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val |= (inl(addr) ^ (val >> 16));
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}
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outl(val, addr);
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}
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static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset,
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unsigned int reg)
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{
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if (offset < 16)
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/* low bank register */
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outl(1 << offset, chip->base + reg);
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else
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/* high bank register */
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errata_outl(chip, 1 << (offset - 16), reg);
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}
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void cs5535_gpio_set(unsigned offset, unsigned int reg)
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{
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struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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__cs5535_gpio_set(chip, offset, reg);
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spin_unlock_irqrestore(&chip->lock, flags);
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}
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EXPORT_SYMBOL_GPL(cs5535_gpio_set);
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static void __cs5535_gpio_clear(struct cs5535_gpio_chip *chip, unsigned offset,
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unsigned int reg)
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{
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if (offset < 16)
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/* low bank register */
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outl(1 << (offset + 16), chip->base + reg);
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else
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/* high bank register */
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errata_outl(chip, 1 << offset, reg);
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}
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void cs5535_gpio_clear(unsigned offset, unsigned int reg)
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{
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struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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__cs5535_gpio_clear(chip, offset, reg);
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spin_unlock_irqrestore(&chip->lock, flags);
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}
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EXPORT_SYMBOL_GPL(cs5535_gpio_clear);
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int cs5535_gpio_isset(unsigned offset, unsigned int reg)
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{
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struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
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unsigned long flags;
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long val;
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spin_lock_irqsave(&chip->lock, flags);
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if (offset < 16)
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/* low bank register */
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val = inl(chip->base + reg);
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else {
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/* high bank register */
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val = inl(chip->base + 0x80 + reg);
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offset -= 16;
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}
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spin_unlock_irqrestore(&chip->lock, flags);
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return (val & (1 << offset)) ? 1 : 0;
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}
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EXPORT_SYMBOL_GPL(cs5535_gpio_isset);
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int cs5535_gpio_set_irq(unsigned group, unsigned irq)
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{
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uint32_t lo, hi;
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if (group > 7 || irq > 15)
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return -EINVAL;
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rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
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lo &= ~(0xF << (group * 4));
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lo |= (irq & 0xF) << (group * 4);
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wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
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return 0;
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}
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EXPORT_SYMBOL_GPL(cs5535_gpio_set_irq);
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void cs5535_gpio_setup_event(unsigned offset, int pair, int pme)
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{
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struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
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uint32_t shift = (offset % 8) * 4;
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unsigned long flags;
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uint32_t val;
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if (offset >= 24)
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offset = GPIO_MAP_W;
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else if (offset >= 16)
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offset = GPIO_MAP_Z;
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else if (offset >= 8)
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offset = GPIO_MAP_Y;
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else
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offset = GPIO_MAP_X;
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spin_lock_irqsave(&chip->lock, flags);
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val = inl(chip->base + offset);
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/* Clear whatever was there before */
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val &= ~(0xF << shift);
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/* Set the new value */
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val |= ((pair & 7) << shift);
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/* Set the PME bit if this is a PME event */
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if (pme)
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val |= (1 << (shift + 3));
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outl(val, chip->base + offset);
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spin_unlock_irqrestore(&chip->lock, flags);
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}
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EXPORT_SYMBOL_GPL(cs5535_gpio_setup_event);
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/*
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* Generic gpio_chip API support.
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*/
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static int chip_gpio_request(struct gpio_chip *c, unsigned offset)
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{
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struct cs5535_gpio_chip *chip =
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container_of(c, struct cs5535_gpio_chip, chip);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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/* check if this pin is available */
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if ((mask & (1 << offset)) == 0) {
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dev_info(&chip->pdev->dev,
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"pin %u is not available (check mask)\n", offset);
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spin_unlock_irqrestore(&chip->lock, flags);
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return -EINVAL;
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}
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/* disable output aux 1 & 2 on this pin */
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__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX1);
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__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX2);
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/* disable input aux 1 on this pin */
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__cs5535_gpio_clear(chip, offset, GPIO_INPUT_AUX1);
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static int chip_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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return cs5535_gpio_isset(offset, GPIO_READ_BACK);
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}
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static void chip_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
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{
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if (val)
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cs5535_gpio_set(offset, GPIO_OUTPUT_VAL);
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else
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cs5535_gpio_clear(offset, GPIO_OUTPUT_VAL);
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}
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static int chip_direction_input(struct gpio_chip *c, unsigned offset)
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{
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struct cs5535_gpio_chip *chip =
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container_of(c, struct cs5535_gpio_chip, chip);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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__cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
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__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_ENABLE);
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static int chip_direction_output(struct gpio_chip *c, unsigned offset, int val)
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{
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struct cs5535_gpio_chip *chip =
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container_of(c, struct cs5535_gpio_chip, chip);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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__cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
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__cs5535_gpio_set(chip, offset, GPIO_OUTPUT_ENABLE);
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if (val)
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__cs5535_gpio_set(chip, offset, GPIO_OUTPUT_VAL);
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else
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__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_VAL);
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static const char * const cs5535_gpio_names[] = {
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"GPIO0", "GPIO1", "GPIO2", "GPIO3",
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"GPIO4", "GPIO5", "GPIO6", "GPIO7",
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"GPIO8", "GPIO9", "GPIO10", "GPIO11",
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"GPIO12", "GPIO13", "GPIO14", "GPIO15",
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"GPIO16", "GPIO17", "GPIO18", "GPIO19",
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"GPIO20", "GPIO21", "GPIO22", NULL,
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"GPIO24", "GPIO25", "GPIO26", "GPIO27",
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"GPIO28", NULL, NULL, NULL,
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};
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static struct cs5535_gpio_chip cs5535_gpio_chip = {
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.chip = {
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.owner = THIS_MODULE,
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.label = DRV_NAME,
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.base = 0,
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.ngpio = 32,
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.names = cs5535_gpio_names,
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.request = chip_gpio_request,
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.get = chip_gpio_get,
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.set = chip_gpio_set,
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.direction_input = chip_direction_input,
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.direction_output = chip_direction_output,
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},
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};
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static int cs5535_gpio_probe(struct platform_device *pdev)
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{
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struct resource *res;
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int err = -EIO;
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ulong mask_orig = mask;
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/* There are two ways to get the GPIO base address; one is by
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* fetching it from MSR_LBAR_GPIO, the other is by reading the
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* PCI BAR info. The latter method is easier (especially across
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* different architectures), so we'll stick with that for now. If
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* it turns out to be unreliable in the face of crappy BIOSes, we
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* can always go back to using MSRs.. */
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res = platform_get_resource(pdev, IORESOURCE_IO, 0);
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if (!res) {
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dev_err(&pdev->dev, "can't fetch device resource info\n");
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goto done;
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}
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if (!request_region(res->start, resource_size(res), pdev->name)) {
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dev_err(&pdev->dev, "can't request region\n");
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goto done;
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}
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/* set up the driver-specific struct */
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cs5535_gpio_chip.base = res->start;
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cs5535_gpio_chip.pdev = pdev;
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spin_lock_init(&cs5535_gpio_chip.lock);
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dev_info(&pdev->dev, "reserved resource region %pR\n", res);
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/* mask out reserved pins */
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mask &= 0x1F7FFFFF;
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/* do not allow pin 28, Power Button, as there's special handling
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* in the PMC needed. (note 12, p. 48) */
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mask &= ~(1 << 28);
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if (mask_orig != mask)
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dev_info(&pdev->dev, "mask changed from 0x%08lX to 0x%08lX\n",
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mask_orig, mask);
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/* finally, register with the generic GPIO API */
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err = gpiochip_add(&cs5535_gpio_chip.chip);
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if (err)
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goto release_region;
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return 0;
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release_region:
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release_region(res->start, resource_size(res));
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done:
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return err;
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}
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static int cs5535_gpio_remove(struct platform_device *pdev)
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{
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struct resource *r;
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gpiochip_remove(&cs5535_gpio_chip.chip);
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r = platform_get_resource(pdev, IORESOURCE_IO, 0);
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release_region(r->start, resource_size(r));
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return 0;
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}
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static struct platform_driver cs5535_gpio_driver = {
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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},
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.probe = cs5535_gpio_probe,
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.remove = cs5535_gpio_remove,
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};
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module_platform_driver(cs5535_gpio_driver);
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MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
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MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:" DRV_NAME);
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