mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
400
drivers/gpio/gpio-pl061.c
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400
drivers/gpio/gpio-pl061.c
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/*
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* Copyright (C) 2008, 2009 Provigent Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
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*
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* Data sheet: ARM DDI 0190B, September 2000
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*/
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/bitops.h>
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#include <linux/gpio.h>
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#include <linux/device.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/pl061.h>
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#include <linux/slab.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pm.h>
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#define GPIODIR 0x400
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#define GPIOIS 0x404
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#define GPIOIBE 0x408
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#define GPIOIEV 0x40C
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#define GPIOIE 0x410
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#define GPIORIS 0x414
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#define GPIOMIS 0x418
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#define GPIOIC 0x41C
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#define PL061_GPIO_NR 8
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#ifdef CONFIG_PM
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struct pl061_context_save_regs {
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u8 gpio_data;
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u8 gpio_dir;
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u8 gpio_is;
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u8 gpio_ibe;
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u8 gpio_iev;
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u8 gpio_ie;
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};
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#endif
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struct pl061_gpio {
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spinlock_t lock;
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void __iomem *base;
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struct gpio_chip gc;
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#ifdef CONFIG_PM
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struct pl061_context_save_regs csave_regs;
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#endif
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};
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static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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/*
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* Map back to global GPIO space and request muxing, the direction
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* parameter does not matter for this controller.
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*/
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int gpio = chip->base + offset;
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return pinctrl_request_gpio(gpio);
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}
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static void pl061_gpio_free(struct gpio_chip *chip, unsigned offset)
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{
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int gpio = chip->base + offset;
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pinctrl_free_gpio(gpio);
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}
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static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
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{
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struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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unsigned long flags;
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unsigned char gpiodir;
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if (offset >= gc->ngpio)
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return -EINVAL;
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spin_lock_irqsave(&chip->lock, flags);
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gpiodir = readb(chip->base + GPIODIR);
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gpiodir &= ~(BIT(offset));
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writeb(gpiodir, chip->base + GPIODIR);
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
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int value)
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{
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struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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unsigned long flags;
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unsigned char gpiodir;
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if (offset >= gc->ngpio)
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return -EINVAL;
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spin_lock_irqsave(&chip->lock, flags);
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writeb(!!value << offset, chip->base + (BIT(offset + 2)));
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gpiodir = readb(chip->base + GPIODIR);
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gpiodir |= BIT(offset);
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writeb(gpiodir, chip->base + GPIODIR);
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/*
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* gpio value is set again, because pl061 doesn't allow to set value of
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* a gpio pin before configuring it in OUT mode.
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*/
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writeb(!!value << offset, chip->base + (BIT(offset + 2)));
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
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{
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struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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return !!readb(chip->base + (BIT(offset + 2)));
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}
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static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
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{
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struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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writeb(!!value << offset, chip->base + (BIT(offset + 2)));
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}
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static int pl061_irq_type(struct irq_data *d, unsigned trigger)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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int offset = irqd_to_hwirq(d);
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unsigned long flags;
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u8 gpiois, gpioibe, gpioiev;
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u8 bit = BIT(offset);
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if (offset < 0 || offset >= PL061_GPIO_NR)
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return -EINVAL;
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spin_lock_irqsave(&chip->lock, flags);
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gpioiev = readb(chip->base + GPIOIEV);
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gpiois = readb(chip->base + GPIOIS);
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gpioibe = readb(chip->base + GPIOIBE);
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if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
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gpiois |= bit;
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if (trigger & IRQ_TYPE_LEVEL_HIGH)
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gpioiev |= bit;
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else
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gpioiev &= ~bit;
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} else
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gpiois &= ~bit;
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if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
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/* Setting this makes GPIOEV be ignored */
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gpioibe |= bit;
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else {
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gpioibe &= ~bit;
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if (trigger & IRQ_TYPE_EDGE_RISING)
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gpioiev |= bit;
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else if (trigger & IRQ_TYPE_EDGE_FALLING)
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gpioiev &= ~bit;
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}
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writeb(gpiois, chip->base + GPIOIS);
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writeb(gpioibe, chip->base + GPIOIBE);
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writeb(gpioiev, chip->base + GPIOIEV);
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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unsigned long pending;
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int offset;
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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chained_irq_enter(irqchip, desc);
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pending = readb(chip->base + GPIOMIS);
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writeb(pending, chip->base + GPIOIC);
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if (pending) {
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for_each_set_bit(offset, &pending, PL061_GPIO_NR)
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generic_handle_irq(irq_find_mapping(gc->irqdomain,
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offset));
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}
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chained_irq_exit(irqchip, desc);
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}
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static void pl061_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
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u8 gpioie;
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spin_lock(&chip->lock);
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gpioie = readb(chip->base + GPIOIE) & ~mask;
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writeb(gpioie, chip->base + GPIOIE);
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spin_unlock(&chip->lock);
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}
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static void pl061_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
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u8 gpioie;
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spin_lock(&chip->lock);
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gpioie = readb(chip->base + GPIOIE) | mask;
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writeb(gpioie, chip->base + GPIOIE);
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spin_unlock(&chip->lock);
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}
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static struct irq_chip pl061_irqchip = {
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.name = "pl061",
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.irq_mask = pl061_irq_mask,
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.irq_unmask = pl061_irq_unmask,
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.irq_set_type = pl061_irq_type,
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};
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static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
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{
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struct device *dev = &adev->dev;
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struct pl061_platform_data *pdata = dev_get_platdata(dev);
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struct pl061_gpio *chip;
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int ret, irq, i, irq_base;
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chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
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if (chip == NULL)
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return -ENOMEM;
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if (pdata) {
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chip->gc.base = pdata->gpio_base;
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irq_base = pdata->irq_base;
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if (irq_base <= 0) {
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dev_err(&adev->dev, "invalid IRQ base in pdata\n");
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return -ENODEV;
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}
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} else {
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chip->gc.base = -1;
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irq_base = 0;
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}
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chip->base = devm_ioremap_resource(dev, &adev->res);
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if (IS_ERR(chip->base))
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return PTR_ERR(chip->base);
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spin_lock_init(&chip->lock);
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chip->gc.request = pl061_gpio_request;
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chip->gc.free = pl061_gpio_free;
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chip->gc.direction_input = pl061_direction_input;
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chip->gc.direction_output = pl061_direction_output;
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chip->gc.get = pl061_get_value;
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chip->gc.set = pl061_set_value;
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chip->gc.ngpio = PL061_GPIO_NR;
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chip->gc.label = dev_name(dev);
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chip->gc.dev = dev;
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chip->gc.owner = THIS_MODULE;
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ret = gpiochip_add(&chip->gc);
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if (ret)
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return ret;
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/*
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* irq_chip support
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*/
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writeb(0, chip->base + GPIOIE); /* disable irqs */
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irq = adev->irq[0];
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if (irq < 0) {
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dev_err(&adev->dev, "invalid IRQ\n");
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return -ENODEV;
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}
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ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip,
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irq_base, handle_simple_irq,
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IRQ_TYPE_NONE);
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if (ret) {
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dev_info(&adev->dev, "could not add irqchip\n");
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return ret;
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}
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gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip,
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irq, pl061_irq_handler);
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for (i = 0; i < PL061_GPIO_NR; i++) {
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if (pdata) {
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if (pdata->directions & (BIT(i)))
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pl061_direction_output(&chip->gc, i,
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pdata->values & (BIT(i)));
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else
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pl061_direction_input(&chip->gc, i);
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}
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}
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amba_set_drvdata(adev, chip);
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dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
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&adev->res.start);
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return 0;
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}
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#ifdef CONFIG_PM
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static int pl061_suspend(struct device *dev)
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{
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struct pl061_gpio *chip = dev_get_drvdata(dev);
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int offset;
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chip->csave_regs.gpio_data = 0;
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chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
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chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
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chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
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chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
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chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
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for (offset = 0; offset < PL061_GPIO_NR; offset++) {
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if (chip->csave_regs.gpio_dir & (BIT(offset)))
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chip->csave_regs.gpio_data |=
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pl061_get_value(&chip->gc, offset) << offset;
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}
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return 0;
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}
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static int pl061_resume(struct device *dev)
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{
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struct pl061_gpio *chip = dev_get_drvdata(dev);
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int offset;
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for (offset = 0; offset < PL061_GPIO_NR; offset++) {
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if (chip->csave_regs.gpio_dir & (BIT(offset)))
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pl061_direction_output(&chip->gc, offset,
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chip->csave_regs.gpio_data &
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(BIT(offset)));
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else
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pl061_direction_input(&chip->gc, offset);
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}
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writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
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writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
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writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
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writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
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return 0;
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}
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static const struct dev_pm_ops pl061_dev_pm_ops = {
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.suspend = pl061_suspend,
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.resume = pl061_resume,
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.freeze = pl061_suspend,
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.restore = pl061_resume,
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};
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#endif
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static struct amba_id pl061_ids[] = {
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{
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.id = 0x00041061,
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.mask = 0x000fffff,
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},
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{ 0, 0 },
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};
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MODULE_DEVICE_TABLE(amba, pl061_ids);
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static struct amba_driver pl061_gpio_driver = {
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.drv = {
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.name = "pl061_gpio",
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#ifdef CONFIG_PM
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.pm = &pl061_dev_pm_ops,
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#endif
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},
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.id_table = pl061_ids,
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.probe = pl061_probe,
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};
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static int __init pl061_gpio_init(void)
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{
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return amba_driver_register(&pl061_gpio_driver);
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}
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module_init(pl061_gpio_init);
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MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
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MODULE_DESCRIPTION("PL061 GPIO driver");
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MODULE_LICENSE("GPL");
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