mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
684
drivers/gpu/drm/gma500/psb_irq.c
Normal file
684
drivers/gpu/drm/gma500/psb_irq.c
Normal file
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@ -0,0 +1,684 @@
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/**************************************************************************
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* Copyright (c) 2007, Intel Corporation.
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
|
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
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* develop this driver.
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*
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**************************************************************************/
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/*
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*/
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#include <drm/drmP.h>
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#include "psb_drv.h"
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#include "psb_reg.h"
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#include "psb_intel_reg.h"
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#include "power.h"
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#include "psb_irq.h"
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#include "mdfld_output.h"
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/*
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* inline functions
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*/
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static inline u32
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psb_pipestat(int pipe)
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{
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if (pipe == 0)
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return PIPEASTAT;
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if (pipe == 1)
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return PIPEBSTAT;
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if (pipe == 2)
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return PIPECSTAT;
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BUG();
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}
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static inline u32
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mid_pipe_event(int pipe)
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{
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if (pipe == 0)
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return _PSB_PIPEA_EVENT_FLAG;
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if (pipe == 1)
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return _MDFLD_PIPEB_EVENT_FLAG;
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if (pipe == 2)
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return _MDFLD_PIPEC_EVENT_FLAG;
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BUG();
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}
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static inline u32
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mid_pipe_vsync(int pipe)
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{
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if (pipe == 0)
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return _PSB_VSYNC_PIPEA_FLAG;
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if (pipe == 1)
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return _PSB_VSYNC_PIPEB_FLAG;
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if (pipe == 2)
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return _MDFLD_PIPEC_VBLANK_FLAG;
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BUG();
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}
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static inline u32
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mid_pipeconf(int pipe)
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{
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if (pipe == 0)
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return PIPEACONF;
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if (pipe == 1)
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return PIPEBCONF;
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if (pipe == 2)
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return PIPECCONF;
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BUG();
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}
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void
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psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
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{
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if ((dev_priv->pipestat[pipe] & mask) != mask) {
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u32 reg = psb_pipestat(pipe);
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dev_priv->pipestat[pipe] |= mask;
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/* Enable the interrupt, clear any pending status */
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if (gma_power_begin(dev_priv->dev, false)) {
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u32 writeVal = PSB_RVDC32(reg);
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writeVal |= (mask | (mask >> 16));
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PSB_WVDC32(writeVal, reg);
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(void) PSB_RVDC32(reg);
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gma_power_end(dev_priv->dev);
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}
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}
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}
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void
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psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
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{
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if ((dev_priv->pipestat[pipe] & mask) != 0) {
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u32 reg = psb_pipestat(pipe);
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dev_priv->pipestat[pipe] &= ~mask;
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if (gma_power_begin(dev_priv->dev, false)) {
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u32 writeVal = PSB_RVDC32(reg);
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writeVal &= ~mask;
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PSB_WVDC32(writeVal, reg);
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(void) PSB_RVDC32(reg);
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gma_power_end(dev_priv->dev);
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}
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}
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}
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static void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
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{
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if (gma_power_begin(dev_priv->dev, false)) {
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u32 pipe_event = mid_pipe_event(pipe);
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dev_priv->vdc_irq_mask |= pipe_event;
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PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
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PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
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gma_power_end(dev_priv->dev);
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}
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}
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static void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
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{
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if (dev_priv->pipestat[pipe] == 0) {
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if (gma_power_begin(dev_priv->dev, false)) {
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u32 pipe_event = mid_pipe_event(pipe);
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dev_priv->vdc_irq_mask &= ~pipe_event;
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PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
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PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
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gma_power_end(dev_priv->dev);
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}
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}
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}
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/**
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* Display controller interrupt handler for pipe event.
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*
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*/
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static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
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{
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struct drm_psb_private *dev_priv =
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(struct drm_psb_private *) dev->dev_private;
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uint32_t pipe_stat_val = 0;
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uint32_t pipe_stat_reg = psb_pipestat(pipe);
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uint32_t pipe_enable = dev_priv->pipestat[pipe];
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uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
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uint32_t pipe_clear;
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uint32_t i = 0;
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spin_lock(&dev_priv->irqmask_lock);
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pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
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pipe_stat_val &= pipe_enable | pipe_status;
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pipe_stat_val &= pipe_stat_val >> 16;
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spin_unlock(&dev_priv->irqmask_lock);
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/* Clear the 2nd level interrupt status bits
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* Sometimes the bits are very sticky so we repeat until they unstick */
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for (i = 0; i < 0xffff; i++) {
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PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
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pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
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if (pipe_clear == 0)
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break;
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}
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if (pipe_clear)
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dev_err(dev->dev,
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"%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
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__func__, pipe, PSB_RVDC32(pipe_stat_reg));
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if (pipe_stat_val & PIPE_VBLANK_STATUS)
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drm_handle_vblank(dev, pipe);
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if (pipe_stat_val & PIPE_TE_STATUS)
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drm_handle_vblank(dev, pipe);
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}
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/*
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* Display controller interrupt handler.
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*/
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static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
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{
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if (vdc_stat & _PSB_IRQ_ASLE)
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psb_intel_opregion_asle_intr(dev);
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if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
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mid_pipe_event_handler(dev, 0);
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if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
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mid_pipe_event_handler(dev, 1);
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}
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/*
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* SGX interrupt handler
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*/
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static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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u32 val, addr;
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int error = false;
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if (stat_1 & _PSB_CE_TWOD_COMPLETE)
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val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS);
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if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) {
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val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
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addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
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if (val) {
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if (val & _PSB_CBI_STAT_PF_N_RW)
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DRM_ERROR("SGX MMU page fault:");
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else
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DRM_ERROR("SGX MMU read / write protection fault:");
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if (val & _PSB_CBI_STAT_FAULT_CACHE)
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DRM_ERROR("\tCache requestor");
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if (val & _PSB_CBI_STAT_FAULT_TA)
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DRM_ERROR("\tTA requestor");
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if (val & _PSB_CBI_STAT_FAULT_VDM)
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DRM_ERROR("\tVDM requestor");
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if (val & _PSB_CBI_STAT_FAULT_2D)
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DRM_ERROR("\t2D requestor");
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if (val & _PSB_CBI_STAT_FAULT_PBE)
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DRM_ERROR("\tPBE requestor");
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if (val & _PSB_CBI_STAT_FAULT_TSP)
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DRM_ERROR("\tTSP requestor");
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if (val & _PSB_CBI_STAT_FAULT_ISP)
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DRM_ERROR("\tISP requestor");
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if (val & _PSB_CBI_STAT_FAULT_USSEPDS)
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DRM_ERROR("\tUSSEPDS requestor");
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if (val & _PSB_CBI_STAT_FAULT_HOST)
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DRM_ERROR("\tHost requestor");
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DRM_ERROR("\tMMU failing address is 0x%08x.\n",
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(unsigned int)addr);
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error = true;
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}
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}
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/* Clear bits */
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PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR);
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PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2);
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PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2);
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}
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irqreturn_t psb_irq_handler(int irq, void *arg)
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{
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struct drm_device *dev = arg;
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struct drm_psb_private *dev_priv = dev->dev_private;
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uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0;
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u32 sgx_stat_1, sgx_stat_2;
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int handled = 0;
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spin_lock(&dev_priv->irqmask_lock);
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vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
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if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE))
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dsp_int = 1;
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/* FIXME: Handle Medfield
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if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG)
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dsp_int = 1;
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*/
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if (vdc_stat & _PSB_IRQ_SGX_FLAG)
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sgx_int = 1;
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if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC)
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hotplug_int = 1;
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vdc_stat &= dev_priv->vdc_irq_mask;
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spin_unlock(&dev_priv->irqmask_lock);
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if (dsp_int && gma_power_is_on(dev)) {
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psb_vdc_interrupt(dev, vdc_stat);
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handled = 1;
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}
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if (sgx_int) {
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sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS);
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sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
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psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2);
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handled = 1;
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}
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/* Note: this bit has other meanings on some devices, so we will
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need to address that later if it ever matters */
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if (hotplug_int && dev_priv->ops->hotplug) {
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handled = dev_priv->ops->hotplug(dev);
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REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
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}
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PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
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(void) PSB_RVDC32(PSB_INT_IDENTITY_R);
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rmb();
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if (!handled)
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return IRQ_NONE;
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return IRQ_HANDLED;
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}
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void psb_irq_preinstall(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv =
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(struct drm_psb_private *) dev->dev_private;
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unsigned long irqflags;
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spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
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if (gma_power_is_on(dev)) {
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PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
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PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
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PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
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PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
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PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
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}
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if (dev->vblank[0].enabled)
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dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
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if (dev->vblank[1].enabled)
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dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
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/* FIXME: Handle Medfield irq mask
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if (dev->vblank[1].enabled)
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dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
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if (dev->vblank[2].enabled)
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dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
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*/
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/* Revisit this area - want per device masks ? */
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if (dev_priv->ops->hotplug)
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dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC;
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dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG;
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/* This register is safe even if display island is off */
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PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
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spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
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}
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int psb_irq_postinstall(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
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unsigned long irqflags;
|
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spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
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|
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/* Enable 2D and MMU fault interrupts */
|
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PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2);
|
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PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE);
|
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PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */
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/* This register is safe even if display island is off */
|
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PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
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PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
|
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|
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if (dev->vblank[0].enabled)
|
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psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
|
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else
|
||||
psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
if (dev->vblank[1].enabled)
|
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psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
|
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else
|
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psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
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if (dev->vblank[2].enabled)
|
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psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
else
|
||||
psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
if (dev_priv->ops->hotplug_enable)
|
||||
dev_priv->ops->hotplug_enable(dev, true);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void psb_irq_uninstall(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
if (dev_priv->ops->hotplug_enable)
|
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dev_priv->ops->hotplug_enable(dev, false);
|
||||
|
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PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
|
||||
|
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if (dev->vblank[0].enabled)
|
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psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
if (dev->vblank[1].enabled)
|
||||
psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
if (dev->vblank[2].enabled)
|
||||
psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
|
||||
_PSB_IRQ_MSVDX_FLAG |
|
||||
_LNC_IRQ_TOPAZ_FLAG;
|
||||
|
||||
/* These two registers are safe even if display island is off */
|
||||
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
|
||||
PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
|
||||
|
||||
wmb();
|
||||
|
||||
/* This register is safe even if display island is off */
|
||||
PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
}
|
||||
|
||||
void psb_irq_turn_on_dpst(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
u32 hist_reg;
|
||||
u32 pwm_reg;
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
|
||||
hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
|
||||
PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
|
||||
hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
|
||||
|
||||
PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
|
||||
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
||||
PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
|
||||
| PWM_PHASEIN_INT_ENABLE,
|
||||
PWM_CONTROL_LOGIC);
|
||||
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
||||
|
||||
psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
|
||||
|
||||
hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
|
||||
PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
|
||||
HISTOGRAM_INT_CONTROL);
|
||||
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
||||
PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
|
||||
PWM_CONTROL_LOGIC);
|
||||
|
||||
gma_power_end(dev);
|
||||
}
|
||||
}
|
||||
|
||||
int psb_irq_enable_dpst(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
/* enable DPST */
|
||||
mid_enable_pipe_event(dev_priv, 0);
|
||||
psb_irq_turn_on_dpst(dev);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void psb_irq_turn_off_dpst(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
u32 hist_reg;
|
||||
u32 pwm_reg;
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
|
||||
hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
|
||||
|
||||
psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
|
||||
|
||||
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
||||
PSB_WVDC32(pwm_reg & ~PWM_PHASEIN_INT_ENABLE,
|
||||
PWM_CONTROL_LOGIC);
|
||||
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
||||
|
||||
gma_power_end(dev);
|
||||
}
|
||||
}
|
||||
|
||||
int psb_irq_disable_dpst(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
mid_disable_pipe_event(dev_priv, 0);
|
||||
psb_irq_turn_off_dpst(dev);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* It is used to enable VBLANK interrupt
|
||||
*/
|
||||
int psb_enable_vblank(struct drm_device *dev, int pipe)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
uint32_t reg_val = 0;
|
||||
uint32_t pipeconf_reg = mid_pipeconf(pipe);
|
||||
|
||||
/* Medfield is different - we should perhaps extract out vblank
|
||||
and blacklight etc ops */
|
||||
if (IS_MFLD(dev))
|
||||
return mdfld_enable_te(dev, pipe);
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
reg_val = REG_READ(pipeconf_reg);
|
||||
gma_power_end(dev);
|
||||
}
|
||||
|
||||
if (!(reg_val & PIPEACONF_ENABLE))
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
if (pipe == 0)
|
||||
dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
|
||||
else if (pipe == 1)
|
||||
dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
|
||||
|
||||
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
|
||||
PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
|
||||
psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* It is used to disable VBLANK interrupt
|
||||
*/
|
||||
void psb_disable_vblank(struct drm_device *dev, int pipe)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
if (IS_MFLD(dev))
|
||||
mdfld_disable_te(dev, pipe);
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
if (pipe == 0)
|
||||
dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
|
||||
else if (pipe == 1)
|
||||
dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
|
||||
|
||||
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
|
||||
PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
|
||||
psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
}
|
||||
|
||||
/*
|
||||
* It is used to enable TE interrupt
|
||||
*/
|
||||
int mdfld_enable_te(struct drm_device *dev, int pipe)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
uint32_t reg_val = 0;
|
||||
uint32_t pipeconf_reg = mid_pipeconf(pipe);
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
reg_val = REG_READ(pipeconf_reg);
|
||||
gma_power_end(dev);
|
||||
}
|
||||
|
||||
if (!(reg_val & PIPEACONF_ENABLE))
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
mid_enable_pipe_event(dev_priv, pipe);
|
||||
psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* It is used to disable TE interrupt
|
||||
*/
|
||||
void mdfld_disable_te(struct drm_device *dev, int pipe)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
if (!dev_priv->dsr_enable)
|
||||
return;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
mid_disable_pipe_event(dev_priv, pipe);
|
||||
psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
}
|
||||
|
||||
/* Called from drm generic code, passed a 'crtc', which
|
||||
* we use as a pipe index
|
||||
*/
|
||||
u32 psb_get_vblank_counter(struct drm_device *dev, int pipe)
|
||||
{
|
||||
uint32_t high_frame = PIPEAFRAMEHIGH;
|
||||
uint32_t low_frame = PIPEAFRAMEPIXEL;
|
||||
uint32_t pipeconf_reg = PIPEACONF;
|
||||
uint32_t reg_val = 0;
|
||||
uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
|
||||
|
||||
switch (pipe) {
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
high_frame = PIPEBFRAMEHIGH;
|
||||
low_frame = PIPEBFRAMEPIXEL;
|
||||
pipeconf_reg = PIPEBCONF;
|
||||
break;
|
||||
case 2:
|
||||
high_frame = PIPECFRAMEHIGH;
|
||||
low_frame = PIPECFRAMEPIXEL;
|
||||
pipeconf_reg = PIPECCONF;
|
||||
break;
|
||||
default:
|
||||
dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!gma_power_begin(dev, false))
|
||||
return 0;
|
||||
|
||||
reg_val = REG_READ(pipeconf_reg);
|
||||
|
||||
if (!(reg_val & PIPEACONF_ENABLE)) {
|
||||
dev_err(dev->dev, "trying to get vblank count for disabled pipe %d\n",
|
||||
pipe);
|
||||
goto psb_get_vblank_counter_exit;
|
||||
}
|
||||
|
||||
/*
|
||||
* High & low register fields aren't synchronized, so make sure
|
||||
* we get a low value that's stable across two reads of the high
|
||||
* register.
|
||||
*/
|
||||
do {
|
||||
high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
|
||||
PIPE_FRAME_HIGH_SHIFT);
|
||||
low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
|
||||
PIPE_FRAME_LOW_SHIFT);
|
||||
high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
|
||||
PIPE_FRAME_HIGH_SHIFT);
|
||||
} while (high1 != high2);
|
||||
|
||||
count = (high1 << 8) | low;
|
||||
|
||||
psb_get_vblank_counter_exit:
|
||||
|
||||
gma_power_end(dev);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue