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Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
163
drivers/gpu/drm/nouveau/dispnv04/tvnv17.h
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163
drivers/gpu/drm/nouveau/dispnv04/tvnv17.h
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/*
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* Copyright (C) 2009 Francisco Jerez.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __NV17_TV_H__
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#define __NV17_TV_H__
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struct nv17_tv_state {
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uint8_t tv_enc[0x40];
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uint32_t hfilter[4][7];
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uint32_t hfilter2[4][7];
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uint32_t vfilter[4][7];
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uint32_t ptv_200;
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uint32_t ptv_204;
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uint32_t ptv_208;
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uint32_t ptv_20c;
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uint32_t ptv_304;
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uint32_t ptv_500;
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uint32_t ptv_504;
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uint32_t ptv_508;
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uint32_t ptv_600;
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uint32_t ptv_604;
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uint32_t ptv_608;
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uint32_t ptv_60c;
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uint32_t ptv_610;
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uint32_t ptv_614;
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};
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enum nv17_tv_norm{
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TV_NORM_PAL,
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TV_NORM_PAL_M,
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TV_NORM_PAL_N,
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TV_NORM_PAL_NC,
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TV_NORM_NTSC_M,
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TV_NORM_NTSC_J,
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NUM_LD_TV_NORMS,
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TV_NORM_HD480I = NUM_LD_TV_NORMS,
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TV_NORM_HD480P,
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TV_NORM_HD576I,
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TV_NORM_HD576P,
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TV_NORM_HD720P,
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TV_NORM_HD1080I,
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NUM_TV_NORMS
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};
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struct nv17_tv_encoder {
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struct nouveau_encoder base;
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struct nv17_tv_state state;
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struct nv17_tv_state saved_state;
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int overscan;
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int flicker;
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int saturation;
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int hue;
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enum nv17_tv_norm tv_norm;
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int subconnector;
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int select_subconnector;
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uint32_t pin_mask;
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};
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#define to_tv_enc(x) container_of(nouveau_encoder(x), \
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struct nv17_tv_encoder, base)
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extern char *nv17_tv_norm_names[NUM_TV_NORMS];
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extern struct nv17_tv_norm_params {
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enum {
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TV_ENC_MODE,
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CTV_ENC_MODE,
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} kind;
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union {
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struct {
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int hdisplay;
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int vdisplay;
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int vrefresh; /* mHz */
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uint8_t tv_enc[0x40];
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} tv_enc_mode;
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struct {
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struct drm_display_mode mode;
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uint32_t ctv_regs[38];
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} ctv_enc_mode;
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};
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} nv17_tv_norms[NUM_TV_NORMS];
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#define get_tv_norm(enc) (&nv17_tv_norms[to_tv_enc(enc)->tv_norm])
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extern const struct drm_display_mode nv17_tv_modes[];
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static inline int interpolate(int y0, int y1, int y2, int x)
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{
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return y1 + (x < 50 ? y1 - y0 : y2 - y1) * (x - 50) / 50;
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}
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void nv17_tv_state_save(struct drm_device *dev, struct nv17_tv_state *state);
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void nv17_tv_state_load(struct drm_device *dev, struct nv17_tv_state *state);
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void nv17_tv_update_properties(struct drm_encoder *encoder);
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void nv17_tv_update_rescaler(struct drm_encoder *encoder);
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void nv17_ctv_update_rescaler(struct drm_encoder *encoder);
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/* TV hardware access functions */
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static inline void nv_write_ptv(struct drm_device *dev, uint32_t reg,
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uint32_t val)
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{
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struct nvif_device *device = &nouveau_drm(dev)->device;
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nvif_wr32(device, reg, val);
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}
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static inline uint32_t nv_read_ptv(struct drm_device *dev, uint32_t reg)
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{
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struct nvif_device *device = &nouveau_drm(dev)->device;
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return nvif_rd32(device, reg);
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}
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static inline void nv_write_tv_enc(struct drm_device *dev, uint8_t reg,
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uint8_t val)
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{
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nv_write_ptv(dev, NV_PTV_TV_INDEX, reg);
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nv_write_ptv(dev, NV_PTV_TV_DATA, val);
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}
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static inline uint8_t nv_read_tv_enc(struct drm_device *dev, uint8_t reg)
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{
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nv_write_ptv(dev, NV_PTV_TV_INDEX, reg);
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return nv_read_ptv(dev, NV_PTV_TV_DATA);
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}
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#define nv_load_ptv(dev, state, reg) \
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nv_write_ptv(dev, NV_PTV_OFFSET + 0x##reg, state->ptv_##reg)
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#define nv_save_ptv(dev, state, reg) \
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state->ptv_##reg = nv_read_ptv(dev, NV_PTV_OFFSET + 0x##reg)
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#define nv_load_tv_enc(dev, state, reg) \
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nv_write_tv_enc(dev, 0x##reg, state->tv_enc[0x##reg])
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#endif
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