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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
227
drivers/gpu/drm/radeon/radeon_ucode.h
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227
drivers/gpu/drm/radeon/radeon_ucode.h
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/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __RADEON_UCODE_H__
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#define __RADEON_UCODE_H__
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/* CP */
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#define R600_PFP_UCODE_SIZE 576
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#define R600_PM4_UCODE_SIZE 1792
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#define R700_PFP_UCODE_SIZE 848
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#define R700_PM4_UCODE_SIZE 1360
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#define EVERGREEN_PFP_UCODE_SIZE 1120
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#define EVERGREEN_PM4_UCODE_SIZE 1376
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#define CAYMAN_PFP_UCODE_SIZE 2176
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#define CAYMAN_PM4_UCODE_SIZE 2176
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#define SI_PFP_UCODE_SIZE 2144
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#define SI_PM4_UCODE_SIZE 2144
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#define SI_CE_UCODE_SIZE 2144
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#define CIK_PFP_UCODE_SIZE 2144
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#define CIK_ME_UCODE_SIZE 2144
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#define CIK_CE_UCODE_SIZE 2144
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/* MEC */
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#define CIK_MEC_UCODE_SIZE 4192
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/* RLC */
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#define R600_RLC_UCODE_SIZE 768
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#define R700_RLC_UCODE_SIZE 1024
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#define EVERGREEN_RLC_UCODE_SIZE 768
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#define CAYMAN_RLC_UCODE_SIZE 1024
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#define ARUBA_RLC_UCODE_SIZE 1536
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#define SI_RLC_UCODE_SIZE 2048
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#define BONAIRE_RLC_UCODE_SIZE 2048
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#define KB_RLC_UCODE_SIZE 2560
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#define KV_RLC_UCODE_SIZE 2560
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#define ML_RLC_UCODE_SIZE 2560
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/* MC */
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#define BTC_MC_UCODE_SIZE 6024
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#define CAYMAN_MC_UCODE_SIZE 6037
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#define SI_MC_UCODE_SIZE 7769
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#define TAHITI_MC_UCODE_SIZE 7808
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#define PITCAIRN_MC_UCODE_SIZE 7775
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#define VERDE_MC_UCODE_SIZE 7875
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#define OLAND_MC_UCODE_SIZE 7863
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#define BONAIRE_MC_UCODE_SIZE 7866
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#define BONAIRE_MC2_UCODE_SIZE 7948
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#define HAWAII_MC_UCODE_SIZE 7933
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#define HAWAII_MC2_UCODE_SIZE 8091
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/* SDMA */
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#define CIK_SDMA_UCODE_SIZE 1050
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#define CIK_SDMA_UCODE_VERSION 64
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/* SMC */
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#define RV770_SMC_UCODE_START 0x0100
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#define RV770_SMC_UCODE_SIZE 0x410d
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#define RV770_SMC_INT_VECTOR_START 0xffc0
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#define RV770_SMC_INT_VECTOR_SIZE 0x0040
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#define RV730_SMC_UCODE_START 0x0100
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#define RV730_SMC_UCODE_SIZE 0x412c
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#define RV730_SMC_INT_VECTOR_START 0xffc0
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#define RV730_SMC_INT_VECTOR_SIZE 0x0040
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#define RV710_SMC_UCODE_START 0x0100
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#define RV710_SMC_UCODE_SIZE 0x3f1f
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#define RV710_SMC_INT_VECTOR_START 0xffc0
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#define RV710_SMC_INT_VECTOR_SIZE 0x0040
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#define RV740_SMC_UCODE_START 0x0100
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#define RV740_SMC_UCODE_SIZE 0x41c5
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#define RV740_SMC_INT_VECTOR_START 0xffc0
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#define RV740_SMC_INT_VECTOR_SIZE 0x0040
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#define CEDAR_SMC_UCODE_START 0x0100
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#define CEDAR_SMC_UCODE_SIZE 0x5d50
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#define CEDAR_SMC_INT_VECTOR_START 0xffc0
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#define CEDAR_SMC_INT_VECTOR_SIZE 0x0040
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#define REDWOOD_SMC_UCODE_START 0x0100
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#define REDWOOD_SMC_UCODE_SIZE 0x5f0a
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#define REDWOOD_SMC_INT_VECTOR_START 0xffc0
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#define REDWOOD_SMC_INT_VECTOR_SIZE 0x0040
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#define JUNIPER_SMC_UCODE_START 0x0100
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#define JUNIPER_SMC_UCODE_SIZE 0x5f1f
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#define JUNIPER_SMC_INT_VECTOR_START 0xffc0
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#define JUNIPER_SMC_INT_VECTOR_SIZE 0x0040
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#define CYPRESS_SMC_UCODE_START 0x0100
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#define CYPRESS_SMC_UCODE_SIZE 0x61f7
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#define CYPRESS_SMC_INT_VECTOR_START 0xffc0
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#define CYPRESS_SMC_INT_VECTOR_SIZE 0x0040
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#define BARTS_SMC_UCODE_START 0x0100
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#define BARTS_SMC_UCODE_SIZE 0x6107
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#define BARTS_SMC_INT_VECTOR_START 0xffc0
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#define BARTS_SMC_INT_VECTOR_SIZE 0x0040
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#define TURKS_SMC_UCODE_START 0x0100
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#define TURKS_SMC_UCODE_SIZE 0x605b
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#define TURKS_SMC_INT_VECTOR_START 0xffc0
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#define TURKS_SMC_INT_VECTOR_SIZE 0x0040
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#define CAICOS_SMC_UCODE_START 0x0100
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#define CAICOS_SMC_UCODE_SIZE 0x5fbd
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#define CAICOS_SMC_INT_VECTOR_START 0xffc0
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#define CAICOS_SMC_INT_VECTOR_SIZE 0x0040
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#define CAYMAN_SMC_UCODE_START 0x0100
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#define CAYMAN_SMC_UCODE_SIZE 0x79ec
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#define CAYMAN_SMC_INT_VECTOR_START 0xffc0
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#define CAYMAN_SMC_INT_VECTOR_SIZE 0x0040
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#define TAHITI_SMC_UCODE_START 0x10000
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#define TAHITI_SMC_UCODE_SIZE 0xf458
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#define PITCAIRN_SMC_UCODE_START 0x10000
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#define PITCAIRN_SMC_UCODE_SIZE 0xe9f4
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#define VERDE_SMC_UCODE_START 0x10000
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#define VERDE_SMC_UCODE_SIZE 0xebe4
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#define OLAND_SMC_UCODE_START 0x10000
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#define OLAND_SMC_UCODE_SIZE 0xe7b4
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#define HAINAN_SMC_UCODE_START 0x10000
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#define HAINAN_SMC_UCODE_SIZE 0xe67C
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#define BONAIRE_SMC_UCODE_START 0x20000
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#define BONAIRE_SMC_UCODE_SIZE 0x1FDEC
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#define HAWAII_SMC_UCODE_START 0x20000
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#define HAWAII_SMC_UCODE_SIZE 0x1FDEC
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struct common_firmware_header {
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uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
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uint32_t header_size_bytes; /* size of just the header in bytes */
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uint16_t header_version_major; /* header version */
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uint16_t header_version_minor; /* header version */
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uint16_t ip_version_major; /* IP version */
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uint16_t ip_version_minor; /* IP version */
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uint32_t ucode_version;
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uint32_t ucode_size_bytes; /* size of ucode in bytes */
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uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
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uint32_t crc32; /* crc32 checksum of the payload */
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};
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/* version_major=1, version_minor=0 */
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struct mc_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t io_debug_size_bytes; /* size of debug array in dwords */
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uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
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};
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/* version_major=1, version_minor=0 */
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struct smc_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t ucode_start_addr;
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};
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/* version_major=1, version_minor=0 */
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struct gfx_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t ucode_feature_version;
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uint32_t jt_offset; /* jt location */
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uint32_t jt_size; /* size of jt */
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};
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/* version_major=1, version_minor=0 */
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struct rlc_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t ucode_feature_version;
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uint32_t save_and_restore_offset;
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uint32_t clear_state_descriptor_offset;
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uint32_t avail_scratch_ram_locations;
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uint32_t master_pkt_description_offset;
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};
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/* version_major=1, version_minor=0 */
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struct sdma_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t ucode_feature_version;
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uint32_t ucode_change_version;
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uint32_t jt_offset; /* jt location */
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uint32_t jt_size; /* size of jt */
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};
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/* header is fixed size */
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union radeon_firmware_header {
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struct common_firmware_header common;
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struct mc_firmware_header_v1_0 mc;
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struct smc_firmware_header_v1_0 smc;
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struct gfx_firmware_header_v1_0 gfx;
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struct rlc_firmware_header_v1_0 rlc;
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struct sdma_firmware_header_v1_0 sdma;
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uint8_t raw[0x100];
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};
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void radeon_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
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void radeon_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
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void radeon_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
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void radeon_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
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void radeon_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
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int radeon_ucode_validate(const struct firmware *fw);
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#endif
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