mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
314
drivers/gpu/host1x/hw/debug_hw.c
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314
drivers/gpu/host1x/hw/debug_hw.c
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/*
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* Copyright (C) 2010 Google, Inc.
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* Author: Erik Gilling <konkers@android.com>
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*
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* Copyright (C) 2011-2013 NVIDIA Corporation
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "../dev.h"
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#include "../debug.h"
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#include "../cdma.h"
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#include "../channel.h"
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#define HOST1X_DEBUG_MAX_PAGE_OFFSET 102400
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enum {
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HOST1X_OPCODE_SETCLASS = 0x00,
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HOST1X_OPCODE_INCR = 0x01,
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HOST1X_OPCODE_NONINCR = 0x02,
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HOST1X_OPCODE_MASK = 0x03,
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HOST1X_OPCODE_IMM = 0x04,
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HOST1X_OPCODE_RESTART = 0x05,
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HOST1X_OPCODE_GATHER = 0x06,
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HOST1X_OPCODE_EXTEND = 0x0e,
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};
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enum {
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HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK = 0x00,
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HOST1X_OPCODE_EXTEND_RELEASE_MLOCK = 0x01,
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};
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static unsigned int show_channel_command(struct output *o, u32 val)
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{
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unsigned mask;
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unsigned subop;
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switch (val >> 28) {
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case HOST1X_OPCODE_SETCLASS:
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mask = val & 0x3f;
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if (mask) {
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host1x_debug_output(o, "SETCL(class=%03x, offset=%03x, mask=%02x, [",
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val >> 6 & 0x3ff,
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val >> 16 & 0xfff, mask);
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return hweight8(mask);
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} else {
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host1x_debug_output(o, "SETCL(class=%03x)\n",
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val >> 6 & 0x3ff);
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return 0;
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}
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case HOST1X_OPCODE_INCR:
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host1x_debug_output(o, "INCR(offset=%03x, [",
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val >> 16 & 0xfff);
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return val & 0xffff;
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case HOST1X_OPCODE_NONINCR:
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host1x_debug_output(o, "NONINCR(offset=%03x, [",
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val >> 16 & 0xfff);
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return val & 0xffff;
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case HOST1X_OPCODE_MASK:
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mask = val & 0xffff;
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host1x_debug_output(o, "MASK(offset=%03x, mask=%03x, [",
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val >> 16 & 0xfff, mask);
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return hweight16(mask);
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case HOST1X_OPCODE_IMM:
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host1x_debug_output(o, "IMM(offset=%03x, data=%03x)\n",
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val >> 16 & 0xfff, val & 0xffff);
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return 0;
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case HOST1X_OPCODE_RESTART:
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host1x_debug_output(o, "RESTART(offset=%08x)\n", val << 4);
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return 0;
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case HOST1X_OPCODE_GATHER:
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host1x_debug_output(o, "GATHER(offset=%03x, insert=%d, type=%d, count=%04x, addr=[",
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val >> 16 & 0xfff, val >> 15 & 0x1,
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val >> 14 & 0x1, val & 0x3fff);
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return 1;
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case HOST1X_OPCODE_EXTEND:
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subop = val >> 24 & 0xf;
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if (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK)
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host1x_debug_output(o, "ACQUIRE_MLOCK(index=%d)\n",
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val & 0xff);
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else if (subop == HOST1X_OPCODE_EXTEND_RELEASE_MLOCK)
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host1x_debug_output(o, "RELEASE_MLOCK(index=%d)\n",
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val & 0xff);
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else
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host1x_debug_output(o, "EXTEND_UNKNOWN(%08x)\n", val);
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return 0;
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default:
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return 0;
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}
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}
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static void show_gather(struct output *o, phys_addr_t phys_addr,
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unsigned int words, struct host1x_cdma *cdma,
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phys_addr_t pin_addr, u32 *map_addr)
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{
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/* Map dmaget cursor to corresponding mem handle */
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u32 offset = phys_addr - pin_addr;
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unsigned int data_count = 0, i;
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/*
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* Sometimes we're given different hardware address to the same
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* page - in these cases the offset will get an invalid number and
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* we just have to bail out.
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*/
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if (offset > HOST1X_DEBUG_MAX_PAGE_OFFSET) {
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host1x_debug_output(o, "[address mismatch]\n");
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return;
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}
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for (i = 0; i < words; i++) {
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u32 addr = phys_addr + i * 4;
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u32 val = *(map_addr + offset / 4 + i);
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if (!data_count) {
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host1x_debug_output(o, "%08x: %08x:", addr, val);
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data_count = show_channel_command(o, val);
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} else {
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host1x_debug_output(o, "%08x%s", val,
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data_count > 0 ? ", " : "])\n");
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data_count--;
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}
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}
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}
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static void show_channel_gathers(struct output *o, struct host1x_cdma *cdma)
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{
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struct host1x_job *job;
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list_for_each_entry(job, &cdma->sync_queue, list) {
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int i;
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host1x_debug_output(o, "\n%p: JOB, syncpt_id=%d, syncpt_val=%d, first_get=%08x, timeout=%d num_slots=%d, num_handles=%d\n",
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job, job->syncpt_id, job->syncpt_end,
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job->first_get, job->timeout,
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job->num_slots, job->num_unpins);
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for (i = 0; i < job->num_gathers; i++) {
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struct host1x_job_gather *g = &job->gathers[i];
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u32 *mapped;
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if (job->gather_copy_mapped)
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mapped = (u32 *)job->gather_copy_mapped;
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else
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mapped = host1x_bo_mmap(g->bo);
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if (!mapped) {
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host1x_debug_output(o, "[could not mmap]\n");
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continue;
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}
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host1x_debug_output(o, " GATHER at %#llx+%04x, %d words\n",
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(u64)g->base, g->offset, g->words);
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show_gather(o, g->base + g->offset, g->words, cdma,
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g->base, mapped);
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if (!job->gather_copy_mapped)
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host1x_bo_munmap(g->bo, mapped);
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}
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}
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}
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static void host1x_debug_show_channel_cdma(struct host1x *host,
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struct host1x_channel *ch,
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struct output *o)
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{
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struct host1x_cdma *cdma = &ch->cdma;
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u32 dmaput, dmaget, dmactrl;
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u32 cbstat, cbread;
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u32 val, base, baseval;
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dmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);
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dmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);
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dmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);
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cbread = host1x_sync_readl(host, HOST1X_SYNC_CBREAD(ch->id));
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cbstat = host1x_sync_readl(host, HOST1X_SYNC_CBSTAT(ch->id));
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host1x_debug_output(o, "%d-%s: ", ch->id, dev_name(ch->dev));
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if (HOST1X_CHANNEL_DMACTRL_DMASTOP_V(dmactrl) ||
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!ch->cdma.push_buffer.mapped) {
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host1x_debug_output(o, "inactive\n\n");
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return;
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}
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if (HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat) == HOST1X_CLASS_HOST1X &&
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HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat) ==
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HOST1X_UCLASS_WAIT_SYNCPT)
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host1x_debug_output(o, "waiting on syncpt %d val %d\n",
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cbread >> 24, cbread & 0xffffff);
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else if (HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat) ==
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HOST1X_CLASS_HOST1X &&
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HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat) ==
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HOST1X_UCLASS_WAIT_SYNCPT_BASE) {
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base = (cbread >> 16) & 0xff;
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baseval =
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host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(base));
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val = cbread & 0xffff;
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host1x_debug_output(o, "waiting on syncpt %d val %d (base %d = %d; offset = %d)\n",
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cbread >> 24, baseval + val, base,
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baseval, val);
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} else
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host1x_debug_output(o, "active class %02x, offset %04x, val %08x\n",
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HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat),
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HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat),
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cbread);
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host1x_debug_output(o, "DMAPUT %08x, DMAGET %08x, DMACTL %08x\n",
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dmaput, dmaget, dmactrl);
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host1x_debug_output(o, "CBREAD %08x, CBSTAT %08x\n", cbread, cbstat);
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show_channel_gathers(o, cdma);
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host1x_debug_output(o, "\n");
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}
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static void host1x_debug_show_channel_fifo(struct host1x *host,
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struct host1x_channel *ch,
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struct output *o)
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{
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u32 val, rd_ptr, wr_ptr, start, end;
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unsigned int data_count = 0;
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host1x_debug_output(o, "%d: fifo:\n", ch->id);
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val = host1x_ch_readl(ch, HOST1X_CHANNEL_FIFOSTAT);
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host1x_debug_output(o, "FIFOSTAT %08x\n", val);
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if (HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(val)) {
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host1x_debug_output(o, "[empty]\n");
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return;
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}
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host1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);
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host1x_sync_writel(host, HOST1X_SYNC_CFPEEK_CTRL_ENA_F(1) |
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HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(ch->id),
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HOST1X_SYNC_CFPEEK_CTRL);
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val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_PTRS);
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rd_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(val);
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wr_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(val);
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val = host1x_sync_readl(host, HOST1X_SYNC_CF_SETUP(ch->id));
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start = HOST1X_SYNC_CF_SETUP_BASE_V(val);
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end = HOST1X_SYNC_CF_SETUP_LIMIT_V(val);
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do {
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host1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);
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host1x_sync_writel(host, HOST1X_SYNC_CFPEEK_CTRL_ENA_F(1) |
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HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(ch->id) |
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HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(rd_ptr),
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HOST1X_SYNC_CFPEEK_CTRL);
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val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_READ);
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if (!data_count) {
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host1x_debug_output(o, "%08x:", val);
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data_count = show_channel_command(o, val);
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} else {
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host1x_debug_output(o, "%08x%s", val,
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data_count > 0 ? ", " : "])\n");
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data_count--;
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}
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if (rd_ptr == end)
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rd_ptr = start;
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else
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rd_ptr++;
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} while (rd_ptr != wr_ptr);
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if (data_count)
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host1x_debug_output(o, ", ...])\n");
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host1x_debug_output(o, "\n");
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host1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);
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}
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static void host1x_debug_show_mlocks(struct host1x *host, struct output *o)
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{
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int i;
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host1x_debug_output(o, "---- mlocks ----\n");
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for (i = 0; i < host1x_syncpt_nb_mlocks(host); i++) {
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u32 owner =
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host1x_sync_readl(host, HOST1X_SYNC_MLOCK_OWNER(i));
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if (HOST1X_SYNC_MLOCK_OWNER_CH_OWNS_V(owner))
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host1x_debug_output(o, "%d: locked by channel %d\n",
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i, HOST1X_SYNC_MLOCK_OWNER_CHID_F(owner));
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else if (HOST1X_SYNC_MLOCK_OWNER_CPU_OWNS_V(owner))
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host1x_debug_output(o, "%d: locked by cpu\n", i);
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else
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host1x_debug_output(o, "%d: unlocked\n", i);
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}
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host1x_debug_output(o, "\n");
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}
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static const struct host1x_debug_ops host1x_debug_ops = {
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.show_channel_cdma = host1x_debug_show_channel_cdma,
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.show_channel_fifo = host1x_debug_show_channel_fifo,
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.show_mlocks = host1x_debug_show_mlocks,
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};
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