mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 01:08:03 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
376
drivers/i2c/busses/i2c-designware-pcidrv.c
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376
drivers/i2c/busses/i2c-designware-pcidrv.c
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@ -0,0 +1,376 @@
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/*
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* Synopsys DesignWare I2C adapter driver (master only).
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*
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* Based on the TI DAVINCI I2C adapter driver.
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*
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* Copyright (C) 2006 Texas Instruments.
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* Copyright (C) 2007 MontaVista Software Inc.
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* Copyright (C) 2009 Provigent Ltd.
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* Copyright (C) 2011 Intel corporation.
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*
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* ----------------------------------------------------------------------------
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <linux/pm_runtime.h>
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#include "i2c-designware-core.h"
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#define DRIVER_NAME "i2c-designware-pci"
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enum dw_pci_ctl_id_t {
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moorestown_0,
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moorestown_1,
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moorestown_2,
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medfield_0,
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medfield_1,
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medfield_2,
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medfield_3,
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medfield_4,
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medfield_5,
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baytrail,
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haswell,
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};
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struct dw_scl_sda_cfg {
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u32 ss_hcnt;
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u32 fs_hcnt;
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u32 ss_lcnt;
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u32 fs_lcnt;
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u32 sda_hold;
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};
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struct dw_pci_controller {
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u32 bus_num;
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u32 bus_cfg;
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u32 tx_fifo_depth;
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u32 rx_fifo_depth;
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u32 clk_khz;
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u32 functionality;
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struct dw_scl_sda_cfg *scl_sda_cfg;
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};
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#define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \
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DW_IC_CON_SLAVE_DISABLE | \
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DW_IC_CON_RESTART_EN)
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#define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \
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I2C_FUNC_SMBUS_BYTE | \
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I2C_FUNC_SMBUS_BYTE_DATA | \
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I2C_FUNC_SMBUS_WORD_DATA | \
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I2C_FUNC_SMBUS_I2C_BLOCK)
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/* BayTrail HCNT/LCNT/SDA hold time */
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static struct dw_scl_sda_cfg byt_config = {
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.ss_hcnt = 0x200,
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.fs_hcnt = 0x55,
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.ss_lcnt = 0x200,
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.fs_lcnt = 0x99,
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.sda_hold = 0x6,
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};
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/* Haswell HCNT/LCNT/SDA hold time */
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static struct dw_scl_sda_cfg hsw_config = {
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.ss_hcnt = 0x01b0,
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.fs_hcnt = 0x48,
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.ss_lcnt = 0x01fb,
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.fs_lcnt = 0xa0,
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.sda_hold = 0x9,
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};
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static struct dw_pci_controller dw_pci_controllers[] = {
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[moorestown_0] = {
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.bus_num = 0,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.clk_khz = 25000,
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},
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[moorestown_1] = {
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.bus_num = 1,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.clk_khz = 25000,
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},
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[moorestown_2] = {
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.bus_num = 2,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.clk_khz = 25000,
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},
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[medfield_0] = {
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.bus_num = 0,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.clk_khz = 25000,
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},
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[medfield_1] = {
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.bus_num = 1,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.clk_khz = 25000,
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},
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[medfield_2] = {
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.bus_num = 2,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.clk_khz = 25000,
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},
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[medfield_3] = {
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.bus_num = 3,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.clk_khz = 25000,
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},
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[medfield_4] = {
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.bus_num = 4,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.clk_khz = 25000,
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},
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[medfield_5] = {
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.bus_num = 5,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.clk_khz = 25000,
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},
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[baytrail] = {
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.bus_num = -1,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.clk_khz = 100000,
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.functionality = I2C_FUNC_10BIT_ADDR,
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.scl_sda_cfg = &byt_config,
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},
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[haswell] = {
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.bus_num = -1,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.clk_khz = 100000,
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.functionality = I2C_FUNC_10BIT_ADDR,
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.scl_sda_cfg = &hsw_config,
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},
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};
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static struct i2c_algorithm i2c_dw_algo = {
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.master_xfer = i2c_dw_xfer,
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.functionality = i2c_dw_func,
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};
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#ifdef CONFIG_PM
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static int i2c_dw_pci_suspend(struct device *dev)
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{
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struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
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i2c_dw_disable(pci_get_drvdata(pdev));
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return 0;
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}
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static int i2c_dw_pci_resume(struct device *dev)
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{
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struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
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return i2c_dw_init(pci_get_drvdata(pdev));
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}
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#endif
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static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
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i2c_dw_pci_resume, NULL);
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static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
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{
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return dev->controller->clk_khz;
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}
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static int i2c_dw_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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struct dw_i2c_dev *dev;
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struct i2c_adapter *adap;
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int r;
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struct dw_pci_controller *controller;
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struct dw_scl_sda_cfg *cfg;
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if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
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dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
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id->driver_data);
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return -EINVAL;
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}
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controller = &dw_pci_controllers[id->driver_data];
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r = pcim_enable_device(pdev);
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if (r) {
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dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
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r);
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return r;
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}
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r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
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if (r) {
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dev_err(&pdev->dev, "I/O memory remapping failed\n");
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return r;
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}
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dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
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if (!dev)
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return -ENOMEM;
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init_completion(&dev->cmd_complete);
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mutex_init(&dev->lock);
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dev->clk = NULL;
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dev->controller = controller;
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dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
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dev->base = pcim_iomap_table(pdev)[0];
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dev->dev = &pdev->dev;
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dev->functionality = controller->functionality |
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DW_DEFAULT_FUNCTIONALITY;
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dev->master_cfg = controller->bus_cfg;
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if (controller->scl_sda_cfg) {
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cfg = controller->scl_sda_cfg;
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dev->ss_hcnt = cfg->ss_hcnt;
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dev->fs_hcnt = cfg->fs_hcnt;
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dev->ss_lcnt = cfg->ss_lcnt;
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dev->fs_lcnt = cfg->fs_lcnt;
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dev->sda_hold_time = cfg->sda_hold;
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}
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pci_set_drvdata(pdev, dev);
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dev->tx_fifo_depth = controller->tx_fifo_depth;
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dev->rx_fifo_depth = controller->rx_fifo_depth;
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r = i2c_dw_init(dev);
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if (r)
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return r;
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adap = &dev->adapter;
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i2c_set_adapdata(adap, dev);
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adap->owner = THIS_MODULE;
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adap->class = 0;
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adap->algo = &i2c_dw_algo;
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adap->dev.parent = &pdev->dev;
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adap->nr = controller->bus_num;
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snprintf(adap->name, sizeof(adap->name), "i2c-designware-pci");
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r = devm_request_irq(&pdev->dev, pdev->irq, i2c_dw_isr, IRQF_SHARED,
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adap->name, dev);
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if (r) {
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dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
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return r;
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}
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i2c_dw_disable_int(dev);
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i2c_dw_clear_int(dev);
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r = i2c_add_numbered_adapter(adap);
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if (r) {
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dev_err(&pdev->dev, "failure adding adapter\n");
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return r;
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}
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pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
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pm_runtime_use_autosuspend(&pdev->dev);
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pm_runtime_put_autosuspend(&pdev->dev);
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pm_runtime_allow(&pdev->dev);
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return 0;
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}
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static void i2c_dw_pci_remove(struct pci_dev *pdev)
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{
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struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
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i2c_dw_disable(dev);
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pm_runtime_forbid(&pdev->dev);
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pm_runtime_get_noresume(&pdev->dev);
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i2c_del_adapter(&dev->adapter);
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}
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/* work with hotplug and coldplug */
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MODULE_ALIAS("i2c_designware-pci");
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static const struct pci_device_id i2_designware_pci_ids[] = {
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/* Moorestown */
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{ PCI_VDEVICE(INTEL, 0x0802), moorestown_0 },
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{ PCI_VDEVICE(INTEL, 0x0803), moorestown_1 },
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{ PCI_VDEVICE(INTEL, 0x0804), moorestown_2 },
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/* Medfield */
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{ PCI_VDEVICE(INTEL, 0x0817), medfield_3,},
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{ PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
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{ PCI_VDEVICE(INTEL, 0x0819), medfield_5 },
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{ PCI_VDEVICE(INTEL, 0x082C), medfield_0 },
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{ PCI_VDEVICE(INTEL, 0x082D), medfield_1 },
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{ PCI_VDEVICE(INTEL, 0x082E), medfield_2 },
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/* Baytrail */
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{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
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{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
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{ PCI_VDEVICE(INTEL, 0x0F43), baytrail },
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{ PCI_VDEVICE(INTEL, 0x0F44), baytrail },
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{ PCI_VDEVICE(INTEL, 0x0F45), baytrail },
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{ PCI_VDEVICE(INTEL, 0x0F46), baytrail },
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{ PCI_VDEVICE(INTEL, 0x0F47), baytrail },
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/* Haswell */
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{ PCI_VDEVICE(INTEL, 0x9c61), haswell },
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{ PCI_VDEVICE(INTEL, 0x9c62), haswell },
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/* Braswell / Cherrytrail */
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{ PCI_VDEVICE(INTEL, 0x22C1), baytrail,},
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{ PCI_VDEVICE(INTEL, 0x22C2), baytrail },
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{ PCI_VDEVICE(INTEL, 0x22C3), baytrail },
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{ PCI_VDEVICE(INTEL, 0x22C4), baytrail },
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{ PCI_VDEVICE(INTEL, 0x22C5), baytrail },
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{ PCI_VDEVICE(INTEL, 0x22C6), baytrail },
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{ PCI_VDEVICE(INTEL, 0x22C7), baytrail },
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{ 0,}
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};
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MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
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static struct pci_driver dw_i2c_driver = {
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.name = DRIVER_NAME,
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.id_table = i2_designware_pci_ids,
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.probe = i2c_dw_pci_probe,
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.remove = i2c_dw_pci_remove,
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.driver = {
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.pm = &i2c_dw_pm_ops,
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},
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};
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module_pci_driver(dw_i2c_driver);
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MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
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MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
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MODULE_LICENSE("GPL");
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