mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 01:12:45 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
796
drivers/i2c/busses/i2c-imx.c
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796
drivers/i2c/busses/i2c-imx.c
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@ -0,0 +1,796 @@
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/*
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* Copyright (C) 2002 Motorola GSG-China
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Author:
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* Darius Augulis, Teltonika Inc.
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*
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* Desc.:
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* Implementation of I2C Adapter/Algorithm Driver
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* for I2C Bus integrated in Freescale i.MX/MXC processors
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*
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* Derived from Motorola GSG China I2C example driver
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*
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* Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
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* Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
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* Copyright (C) 2007 RightHand Technologies, Inc.
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* Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
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*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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*/
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/** Includes *******************************************************************
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*******************************************************************************/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/sched.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_data/i2c-imx.h>
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/** Defines ********************************************************************
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*******************************************************************************/
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/* This will be the driver name the kernel reports */
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#define DRIVER_NAME "imx-i2c"
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/* Default value */
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#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
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/* IMX I2C registers:
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* the I2C register offset is different between SoCs,
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* to provid support for all these chips, split the
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* register offset into a fixed base address and a
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* variable shift value, then the full register offset
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* will be calculated by
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* reg_off = ( reg_base_addr << reg_shift)
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*/
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#define IMX_I2C_IADR 0x00 /* i2c slave address */
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#define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
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#define IMX_I2C_I2CR 0x02 /* i2c control */
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#define IMX_I2C_I2SR 0x03 /* i2c status */
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#define IMX_I2C_I2DR 0x04 /* i2c transfer data */
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#define IMX_I2C_REGSHIFT 2
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#define VF610_I2C_REGSHIFT 0
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/* Bits of IMX I2C registers */
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#define I2SR_RXAK 0x01
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#define I2SR_IIF 0x02
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#define I2SR_SRW 0x04
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#define I2SR_IAL 0x10
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#define I2SR_IBB 0x20
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#define I2SR_IAAS 0x40
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#define I2SR_ICF 0x80
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#define I2CR_RSTA 0x04
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#define I2CR_TXAK 0x08
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#define I2CR_MTX 0x10
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#define I2CR_MSTA 0x20
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#define I2CR_IIEN 0x40
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#define I2CR_IEN 0x80
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/* register bits different operating codes definition:
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* 1) I2SR: Interrupt flags clear operation differ between SoCs:
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* - write zero to clear(w0c) INT flag on i.MX,
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* - but write one to clear(w1c) INT flag on Vybrid.
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* 2) I2CR: I2C module enable operation also differ between SoCs:
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* - set I2CR_IEN bit enable the module on i.MX,
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* - but clear I2CR_IEN bit enable the module on Vybrid.
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*/
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#define I2SR_CLR_OPCODE_W0C 0x0
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#define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
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#define I2CR_IEN_OPCODE_0 0x0
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#define I2CR_IEN_OPCODE_1 I2CR_IEN
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/** Variables ******************************************************************
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*******************************************************************************/
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/*
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* sorted list of clock divider, register value pairs
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* taken from table 26-5, p.26-9, Freescale i.MX
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* Integrated Portable System Processor Reference Manual
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* Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
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*
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* Duplicated divider values removed from list
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*/
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struct imx_i2c_clk_pair {
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u16 div;
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u16 val;
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};
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static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
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{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
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{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
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{ 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
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{ 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
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{ 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
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{ 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
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{ 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
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{ 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
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{ 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
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{ 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
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{ 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
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{ 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
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{ 3072, 0x1E }, { 3840, 0x1F }
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};
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/* Vybrid VF610 clock divider, register value pairs */
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static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
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{ 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
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{ 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
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{ 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
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{ 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
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{ 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
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{ 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
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{ 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
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{ 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
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{ 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
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{ 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
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{ 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
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{ 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
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{ 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
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{ 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
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{ 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
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};
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enum imx_i2c_type {
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IMX1_I2C,
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IMX21_I2C,
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VF610_I2C,
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};
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struct imx_i2c_hwdata {
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enum imx_i2c_type devtype;
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unsigned regshift;
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struct imx_i2c_clk_pair *clk_div;
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unsigned ndivs;
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unsigned i2sr_clr_opcode;
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unsigned i2cr_ien_opcode;
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};
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struct imx_i2c_struct {
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struct i2c_adapter adapter;
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struct clk *clk;
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void __iomem *base;
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wait_queue_head_t queue;
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unsigned long i2csr;
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unsigned int disable_delay;
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int stopped;
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unsigned int ifdr; /* IMX_I2C_IFDR */
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unsigned int cur_clk;
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unsigned int bitrate;
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const struct imx_i2c_hwdata *hwdata;
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};
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static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
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.devtype = IMX1_I2C,
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.regshift = IMX_I2C_REGSHIFT,
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.clk_div = imx_i2c_clk_div,
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.ndivs = ARRAY_SIZE(imx_i2c_clk_div),
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.i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
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.i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
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};
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static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
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.devtype = IMX21_I2C,
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.regshift = IMX_I2C_REGSHIFT,
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.clk_div = imx_i2c_clk_div,
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.ndivs = ARRAY_SIZE(imx_i2c_clk_div),
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.i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
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.i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
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};
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static struct imx_i2c_hwdata vf610_i2c_hwdata = {
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.devtype = VF610_I2C,
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.regshift = VF610_I2C_REGSHIFT,
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.clk_div = vf610_i2c_clk_div,
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.ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
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.i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
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.i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
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};
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static struct platform_device_id imx_i2c_devtype[] = {
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{
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.name = "imx1-i2c",
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.driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
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}, {
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.name = "imx21-i2c",
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.driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
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}, {
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/* sentinel */
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}
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};
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MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
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static const struct of_device_id i2c_imx_dt_ids[] = {
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{ .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
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{ .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
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{ .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
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static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
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{
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return i2c_imx->hwdata->devtype == IMX1_I2C;
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}
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static inline void imx_i2c_write_reg(unsigned int val,
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struct imx_i2c_struct *i2c_imx, unsigned int reg)
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{
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writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
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}
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static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
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unsigned int reg)
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{
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return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
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}
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/** Functions for IMX I2C adapter driver ***************************************
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*******************************************************************************/
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static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
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{
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unsigned long orig_jiffies = jiffies;
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unsigned int temp;
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dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
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while (1) {
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temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
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/* check for arbitration lost */
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if (temp & I2SR_IAL) {
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temp &= ~I2SR_IAL;
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
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return -EAGAIN;
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}
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if (for_busy && (temp & I2SR_IBB))
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break;
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if (!for_busy && !(temp & I2SR_IBB))
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break;
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if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
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dev_dbg(&i2c_imx->adapter.dev,
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"<%s> I2C bus is busy\n", __func__);
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return -ETIMEDOUT;
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}
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schedule();
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}
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return 0;
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}
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static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
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{
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wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
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if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
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dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
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return -ETIMEDOUT;
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}
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dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
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i2c_imx->i2csr = 0;
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return 0;
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}
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static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
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{
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if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
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dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
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return -EIO; /* No ACK */
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}
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dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
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return 0;
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}
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static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx)
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{
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struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
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unsigned int i2c_clk_rate;
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unsigned int div;
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int i;
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/* Divider value calculation */
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i2c_clk_rate = clk_get_rate(i2c_imx->clk);
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if (i2c_imx->cur_clk == i2c_clk_rate)
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return;
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else
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i2c_imx->cur_clk = i2c_clk_rate;
|
||||
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div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
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if (div < i2c_clk_div[0].div)
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i = 0;
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else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
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i = i2c_imx->hwdata->ndivs - 1;
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else
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for (i = 0; i2c_clk_div[i].div < div; i++);
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/* Store divider value */
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i2c_imx->ifdr = i2c_clk_div[i].val;
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||||
|
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/*
|
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* There dummy delay is calculated.
|
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* It should be about one I2C clock period long.
|
||||
* This delay is used in I2C bus disable function
|
||||
* to fix chip hardware bug.
|
||||
*/
|
||||
i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
|
||||
+ (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
|
||||
|
||||
#ifdef CONFIG_I2C_DEBUG_BUS
|
||||
dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
|
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i2c_clk_rate, div);
|
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dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
|
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i2c_clk_div[i].val, i2c_clk_div[i].div);
|
||||
#endif
|
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}
|
||||
|
||||
static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
|
||||
{
|
||||
unsigned int temp = 0;
|
||||
int result;
|
||||
|
||||
dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
|
||||
|
||||
i2c_imx_set_clk(i2c_imx);
|
||||
|
||||
result = clk_prepare_enable(i2c_imx->clk);
|
||||
if (result)
|
||||
return result;
|
||||
imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
|
||||
/* Enable I2C controller */
|
||||
imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
|
||||
imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
|
||||
|
||||
/* Wait controller to be stable */
|
||||
udelay(50);
|
||||
|
||||
/* Start I2C transaction */
|
||||
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
||||
temp |= I2CR_MSTA;
|
||||
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
||||
result = i2c_imx_bus_busy(i2c_imx, 1);
|
||||
if (result)
|
||||
return result;
|
||||
i2c_imx->stopped = 0;
|
||||
|
||||
temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
|
||||
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
||||
return result;
|
||||
}
|
||||
|
||||
static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
|
||||
{
|
||||
unsigned int temp = 0;
|
||||
|
||||
if (!i2c_imx->stopped) {
|
||||
/* Stop I2C transaction */
|
||||
dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
|
||||
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
||||
temp &= ~(I2CR_MSTA | I2CR_MTX);
|
||||
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
||||
}
|
||||
if (is_imx1_i2c(i2c_imx)) {
|
||||
/*
|
||||
* This delay caused by an i.MXL hardware bug.
|
||||
* If no (or too short) delay, no "STOP" bit will be generated.
|
||||
*/
|
||||
udelay(i2c_imx->disable_delay);
|
||||
}
|
||||
|
||||
if (!i2c_imx->stopped) {
|
||||
i2c_imx_bus_busy(i2c_imx, 0);
|
||||
i2c_imx->stopped = 1;
|
||||
}
|
||||
|
||||
/* Disable I2C controller */
|
||||
temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
|
||||
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
||||
clk_disable_unprepare(i2c_imx->clk);
|
||||
}
|
||||
|
||||
static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
|
||||
{
|
||||
struct imx_i2c_struct *i2c_imx = dev_id;
|
||||
unsigned int temp;
|
||||
|
||||
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
|
||||
if (temp & I2SR_IIF) {
|
||||
/* save status register */
|
||||
i2c_imx->i2csr = temp;
|
||||
temp &= ~I2SR_IIF;
|
||||
temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
|
||||
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
|
||||
wake_up(&i2c_imx->queue);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
|
||||
{
|
||||
int i, result;
|
||||
|
||||
dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
|
||||
__func__, msgs->addr << 1);
|
||||
|
||||
/* write slave address */
|
||||
imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
|
||||
result = i2c_imx_trx_complete(i2c_imx);
|
||||
if (result)
|
||||
return result;
|
||||
result = i2c_imx_acked(i2c_imx);
|
||||
if (result)
|
||||
return result;
|
||||
dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
|
||||
|
||||
/* write data */
|
||||
for (i = 0; i < msgs->len; i++) {
|
||||
dev_dbg(&i2c_imx->adapter.dev,
|
||||
"<%s> write byte: B%d=0x%X\n",
|
||||
__func__, i, msgs->buf[i]);
|
||||
imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
|
||||
result = i2c_imx_trx_complete(i2c_imx);
|
||||
if (result)
|
||||
return result;
|
||||
result = i2c_imx_acked(i2c_imx);
|
||||
if (result)
|
||||
return result;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg)
|
||||
{
|
||||
int i, result;
|
||||
unsigned int temp;
|
||||
int block_data = msgs->flags & I2C_M_RECV_LEN;
|
||||
|
||||
dev_dbg(&i2c_imx->adapter.dev,
|
||||
"<%s> write slave address: addr=0x%x\n",
|
||||
__func__, (msgs->addr << 1) | 0x01);
|
||||
|
||||
/* write slave address */
|
||||
imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR);
|
||||
result = i2c_imx_trx_complete(i2c_imx);
|
||||
if (result)
|
||||
return result;
|
||||
result = i2c_imx_acked(i2c_imx);
|
||||
if (result)
|
||||
return result;
|
||||
|
||||
dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
|
||||
|
||||
/* setup bus to read data */
|
||||
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
||||
temp &= ~I2CR_MTX;
|
||||
|
||||
/*
|
||||
* Reset the I2CR_TXAK flag initially for SMBus block read since the
|
||||
* length is unknown
|
||||
*/
|
||||
if ((msgs->len - 1) || block_data)
|
||||
temp &= ~I2CR_TXAK;
|
||||
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
||||
imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
|
||||
|
||||
dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
|
||||
|
||||
/* read data */
|
||||
for (i = 0; i < msgs->len; i++) {
|
||||
u8 len = 0;
|
||||
result = i2c_imx_trx_complete(i2c_imx);
|
||||
if (result)
|
||||
return result;
|
||||
/*
|
||||
* First byte is the length of remaining packet
|
||||
* in the SMBus block data read. Add it to
|
||||
* msgs->len.
|
||||
*/
|
||||
if ((!i) && block_data) {
|
||||
len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
|
||||
if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
|
||||
return -EPROTO;
|
||||
dev_dbg(&i2c_imx->adapter.dev,
|
||||
"<%s> read length: 0x%X\n",
|
||||
__func__, len);
|
||||
msgs->len += len;
|
||||
}
|
||||
if (i == (msgs->len - 1)) {
|
||||
if (is_lastmsg) {
|
||||
/*
|
||||
* It must generate STOP before read I2DR to prevent
|
||||
* controller from generating another clock cycle
|
||||
*/
|
||||
dev_dbg(&i2c_imx->adapter.dev,
|
||||
"<%s> clear MSTA\n", __func__);
|
||||
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
||||
temp &= ~(I2CR_MSTA | I2CR_MTX);
|
||||
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
||||
i2c_imx_bus_busy(i2c_imx, 0);
|
||||
i2c_imx->stopped = 1;
|
||||
} else {
|
||||
/*
|
||||
* For i2c master receiver repeat restart operation like:
|
||||
* read -> repeat MSTA -> read/write
|
||||
* The controller must set MTX before read the last byte in
|
||||
* the first read operation, otherwise the first read cost
|
||||
* one extra clock cycle.
|
||||
*/
|
||||
temp = readb(i2c_imx->base + IMX_I2C_I2CR);
|
||||
temp |= I2CR_MTX;
|
||||
writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
|
||||
}
|
||||
} else if (i == (msgs->len - 2)) {
|
||||
dev_dbg(&i2c_imx->adapter.dev,
|
||||
"<%s> set TXAK\n", __func__);
|
||||
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
||||
temp |= I2CR_TXAK;
|
||||
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
||||
}
|
||||
if ((!i) && block_data)
|
||||
msgs->buf[0] = len;
|
||||
else
|
||||
msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
|
||||
dev_dbg(&i2c_imx->adapter.dev,
|
||||
"<%s> read byte: B%d=0x%X\n",
|
||||
__func__, i, msgs->buf[i]);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int i2c_imx_xfer(struct i2c_adapter *adapter,
|
||||
struct i2c_msg *msgs, int num)
|
||||
{
|
||||
unsigned int i, temp;
|
||||
int result;
|
||||
bool is_lastmsg = false;
|
||||
struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
|
||||
|
||||
dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
|
||||
|
||||
/* Start I2C transfer */
|
||||
result = i2c_imx_start(i2c_imx);
|
||||
if (result)
|
||||
goto fail0;
|
||||
|
||||
/* read/write data */
|
||||
for (i = 0; i < num; i++) {
|
||||
if (i == num - 1)
|
||||
is_lastmsg = true;
|
||||
|
||||
if (i) {
|
||||
dev_dbg(&i2c_imx->adapter.dev,
|
||||
"<%s> repeated start\n", __func__);
|
||||
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
||||
temp |= I2CR_RSTA;
|
||||
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
||||
result = i2c_imx_bus_busy(i2c_imx, 1);
|
||||
if (result)
|
||||
goto fail0;
|
||||
}
|
||||
dev_dbg(&i2c_imx->adapter.dev,
|
||||
"<%s> transfer message: %d\n", __func__, i);
|
||||
/* write/read data */
|
||||
#ifdef CONFIG_I2C_DEBUG_BUS
|
||||
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
||||
dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
|
||||
"MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
|
||||
(temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
|
||||
(temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
|
||||
(temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
|
||||
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
|
||||
dev_dbg(&i2c_imx->adapter.dev,
|
||||
"<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
|
||||
"IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
|
||||
(temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
|
||||
(temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
|
||||
(temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
|
||||
(temp & I2SR_RXAK ? 1 : 0));
|
||||
#endif
|
||||
if (msgs[i].flags & I2C_M_RD)
|
||||
result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
|
||||
else
|
||||
result = i2c_imx_write(i2c_imx, &msgs[i]);
|
||||
if (result)
|
||||
goto fail0;
|
||||
}
|
||||
|
||||
fail0:
|
||||
/* Stop I2C transfer */
|
||||
i2c_imx_stop(i2c_imx);
|
||||
|
||||
dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
|
||||
(result < 0) ? "error" : "success msg",
|
||||
(result < 0) ? result : num);
|
||||
return (result < 0) ? result : num;
|
||||
}
|
||||
|
||||
static u32 i2c_imx_func(struct i2c_adapter *adapter)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
|
||||
| I2C_FUNC_SMBUS_READ_BLOCK_DATA;
|
||||
}
|
||||
|
||||
static struct i2c_algorithm i2c_imx_algo = {
|
||||
.master_xfer = i2c_imx_xfer,
|
||||
.functionality = i2c_imx_func,
|
||||
};
|
||||
|
||||
static int i2c_imx_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
|
||||
&pdev->dev);
|
||||
struct imx_i2c_struct *i2c_imx;
|
||||
struct resource *res;
|
||||
struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
|
||||
void __iomem *base;
|
||||
int irq, ret;
|
||||
|
||||
dev_dbg(&pdev->dev, "<%s>\n", __func__);
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "can't get irq number\n");
|
||||
return irq;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
i2c_imx = devm_kzalloc(&pdev->dev, sizeof(struct imx_i2c_struct),
|
||||
GFP_KERNEL);
|
||||
if (!i2c_imx)
|
||||
return -ENOMEM;
|
||||
|
||||
if (of_id)
|
||||
i2c_imx->hwdata = of_id->data;
|
||||
else
|
||||
i2c_imx->hwdata = (struct imx_i2c_hwdata *)
|
||||
platform_get_device_id(pdev)->driver_data;
|
||||
|
||||
/* Setup i2c_imx driver structure */
|
||||
strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
|
||||
i2c_imx->adapter.owner = THIS_MODULE;
|
||||
i2c_imx->adapter.algo = &i2c_imx_algo;
|
||||
i2c_imx->adapter.dev.parent = &pdev->dev;
|
||||
i2c_imx->adapter.nr = pdev->id;
|
||||
i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
|
||||
i2c_imx->base = base;
|
||||
|
||||
/* Get I2C clock */
|
||||
i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(i2c_imx->clk)) {
|
||||
dev_err(&pdev->dev, "can't get I2C clock\n");
|
||||
return PTR_ERR(i2c_imx->clk);
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(i2c_imx->clk);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "can't enable I2C clock\n");
|
||||
return ret;
|
||||
}
|
||||
/* Request IRQ */
|
||||
ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
|
||||
pdev->name, i2c_imx);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "can't claim irq %d\n", irq);
|
||||
goto clk_disable;
|
||||
}
|
||||
|
||||
/* Init queue */
|
||||
init_waitqueue_head(&i2c_imx->queue);
|
||||
|
||||
/* Set up adapter data */
|
||||
i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
|
||||
|
||||
/* Set up clock divider */
|
||||
i2c_imx->bitrate = IMX_I2C_BIT_RATE;
|
||||
ret = of_property_read_u32(pdev->dev.of_node,
|
||||
"clock-frequency", &i2c_imx->bitrate);
|
||||
if (ret < 0 && pdata && pdata->bitrate)
|
||||
i2c_imx->bitrate = pdata->bitrate;
|
||||
|
||||
/* Set up chip registers to defaults */
|
||||
imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
|
||||
i2c_imx, IMX_I2C_I2CR);
|
||||
imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
|
||||
|
||||
/* Add I2C adapter */
|
||||
ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "registration failed\n");
|
||||
goto clk_disable;
|
||||
}
|
||||
|
||||
/* Set up platform driver data */
|
||||
platform_set_drvdata(pdev, i2c_imx);
|
||||
clk_disable_unprepare(i2c_imx->clk);
|
||||
|
||||
dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
|
||||
dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
|
||||
dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
|
||||
i2c_imx->adapter.name);
|
||||
dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
|
||||
|
||||
return 0; /* Return OK */
|
||||
|
||||
clk_disable:
|
||||
clk_disable_unprepare(i2c_imx->clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int i2c_imx_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
|
||||
|
||||
/* remove adapter */
|
||||
dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
|
||||
i2c_del_adapter(&i2c_imx->adapter);
|
||||
|
||||
/* setup chip registers to defaults */
|
||||
imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
|
||||
imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
|
||||
imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
|
||||
imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver i2c_imx_driver = {
|
||||
.probe = i2c_imx_probe,
|
||||
.remove = i2c_imx_remove,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = i2c_imx_dt_ids,
|
||||
},
|
||||
.id_table = imx_i2c_devtype,
|
||||
};
|
||||
|
||||
static int __init i2c_adap_imx_init(void)
|
||||
{
|
||||
return platform_driver_register(&i2c_imx_driver);
|
||||
}
|
||||
subsys_initcall(i2c_adap_imx_init);
|
||||
|
||||
static void __exit i2c_adap_imx_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&i2c_imx_driver);
|
||||
}
|
||||
module_exit(i2c_adap_imx_exit);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Darius Augulis");
|
||||
MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
|
||||
MODULE_ALIAS("platform:" DRIVER_NAME);
|
||||
Loading…
Add table
Add a link
Reference in a new issue