mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
564
drivers/infiniband/hw/mlx5/mlx5_ib.h
Normal file
564
drivers/infiniband/hw/mlx5/mlx5_ib.h
Normal file
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@ -0,0 +1,564 @@
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/*
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* Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MLX5_IB_H
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#define MLX5_IB_H
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <rdma/ib_verbs.h>
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#include <rdma/ib_smi.h>
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#include <linux/mlx5/driver.h>
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#include <linux/mlx5/cq.h>
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#include <linux/mlx5/qp.h>
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#include <linux/mlx5/srq.h>
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#include <linux/types.h>
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#define mlx5_ib_dbg(dev, format, arg...) \
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pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
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__LINE__, current->pid, ##arg)
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#define mlx5_ib_err(dev, format, arg...) \
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pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
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__LINE__, current->pid, ##arg)
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#define mlx5_ib_warn(dev, format, arg...) \
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pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
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__LINE__, current->pid, ##arg)
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enum {
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MLX5_IB_MMAP_CMD_SHIFT = 8,
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MLX5_IB_MMAP_CMD_MASK = 0xff,
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};
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enum mlx5_ib_mmap_cmd {
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MLX5_IB_MMAP_REGULAR_PAGE = 0,
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MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, /* always last */
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};
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enum {
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MLX5_RES_SCAT_DATA32_CQE = 0x1,
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MLX5_RES_SCAT_DATA64_CQE = 0x2,
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MLX5_REQ_SCAT_DATA32_CQE = 0x11,
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MLX5_REQ_SCAT_DATA64_CQE = 0x22,
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};
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enum mlx5_ib_latency_class {
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MLX5_IB_LATENCY_CLASS_LOW,
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MLX5_IB_LATENCY_CLASS_MEDIUM,
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MLX5_IB_LATENCY_CLASS_HIGH,
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MLX5_IB_LATENCY_CLASS_FAST_PATH
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};
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enum mlx5_ib_mad_ifc_flags {
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MLX5_MAD_IFC_IGNORE_MKEY = 1,
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MLX5_MAD_IFC_IGNORE_BKEY = 2,
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MLX5_MAD_IFC_NET_VIEW = 4,
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};
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struct mlx5_ib_ucontext {
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struct ib_ucontext ibucontext;
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struct list_head db_page_list;
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/* protect doorbell record alloc/free
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*/
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struct mutex db_page_mutex;
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struct mlx5_uuar_info uuari;
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};
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static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
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{
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return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
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}
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struct mlx5_ib_pd {
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struct ib_pd ibpd;
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u32 pdn;
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u32 pa_lkey;
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};
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/* Use macros here so that don't have to duplicate
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* enum ib_send_flags and enum ib_qp_type for low-level driver
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*/
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#define MLX5_IB_SEND_UMR_UNREG IB_SEND_RESERVED_START
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#define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
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#define MLX5_IB_WR_UMR IB_WR_RESERVED1
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struct wr_list {
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u16 opcode;
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u16 next;
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};
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struct mlx5_ib_wq {
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u64 *wrid;
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u32 *wr_data;
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struct wr_list *w_list;
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unsigned *wqe_head;
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u16 unsig_count;
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/* serialize post to the work queue
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*/
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spinlock_t lock;
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int wqe_cnt;
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int max_post;
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int max_gs;
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int offset;
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int wqe_shift;
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unsigned head;
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unsigned tail;
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u16 cur_post;
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u16 last_poll;
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void *qend;
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};
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enum {
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MLX5_QP_USER,
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MLX5_QP_KERNEL,
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MLX5_QP_EMPTY
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};
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struct mlx5_ib_qp {
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struct ib_qp ibqp;
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struct mlx5_core_qp mqp;
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struct mlx5_buf buf;
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struct mlx5_db db;
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struct mlx5_ib_wq rq;
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u32 doorbell_qpn;
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u8 sq_signal_bits;
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u8 fm_cache;
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int sq_max_wqes_per_wr;
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int sq_spare_wqes;
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struct mlx5_ib_wq sq;
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struct ib_umem *umem;
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int buf_size;
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/* serialize qp state modifications
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*/
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struct mutex mutex;
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u16 xrcdn;
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u32 flags;
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u8 port;
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u8 alt_port;
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u8 atomic_rd_en;
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u8 resp_depth;
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u8 state;
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int mlx_type;
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int wq_sig;
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int scat_cqe;
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int max_inline_data;
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struct mlx5_bf *bf;
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int has_rq;
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/* only for user space QPs. For kernel
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* we have it from the bf object
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*/
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int uuarn;
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int create_type;
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u32 pa_lkey;
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/* Store signature errors */
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bool signature_en;
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};
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struct mlx5_ib_cq_buf {
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struct mlx5_buf buf;
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struct ib_umem *umem;
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int cqe_size;
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int nent;
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};
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enum mlx5_ib_qp_flags {
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MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = 1 << 0,
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MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 1,
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};
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struct mlx5_shared_mr_info {
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int mr_id;
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struct ib_umem *umem;
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};
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struct mlx5_ib_cq {
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struct ib_cq ibcq;
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struct mlx5_core_cq mcq;
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struct mlx5_ib_cq_buf buf;
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struct mlx5_db db;
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/* serialize access to the CQ
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*/
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spinlock_t lock;
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/* protect resize cq
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*/
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struct mutex resize_mutex;
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struct mlx5_ib_cq_buf *resize_buf;
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struct ib_umem *resize_umem;
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int cqe_size;
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};
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struct mlx5_ib_srq {
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struct ib_srq ibsrq;
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struct mlx5_core_srq msrq;
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struct mlx5_buf buf;
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struct mlx5_db db;
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u64 *wrid;
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/* protect SRQ hanlding
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*/
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spinlock_t lock;
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int head;
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int tail;
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u16 wqe_ctr;
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struct ib_umem *umem;
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/* serialize arming a SRQ
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*/
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struct mutex mutex;
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int wq_sig;
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};
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struct mlx5_ib_xrcd {
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struct ib_xrcd ibxrcd;
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u32 xrcdn;
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};
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struct mlx5_ib_mr {
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struct ib_mr ibmr;
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struct mlx5_core_mr mmr;
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struct ib_umem *umem;
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struct mlx5_shared_mr_info *smr_info;
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struct list_head list;
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int order;
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int umred;
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__be64 *pas;
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dma_addr_t dma;
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int npages;
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struct mlx5_ib_dev *dev;
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struct mlx5_create_mkey_mbox_out out;
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struct mlx5_core_sig_ctx *sig;
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};
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struct mlx5_ib_fast_reg_page_list {
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struct ib_fast_reg_page_list ibfrpl;
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__be64 *mapped_page_list;
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dma_addr_t map;
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};
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struct mlx5_ib_umr_context {
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enum ib_wc_status status;
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struct completion done;
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};
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static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context)
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{
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context->status = -1;
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init_completion(&context->done);
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}
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struct umr_common {
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struct ib_pd *pd;
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struct ib_cq *cq;
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struct ib_qp *qp;
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struct ib_mr *mr;
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/* control access to UMR QP
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*/
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struct semaphore sem;
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};
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enum {
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MLX5_FMR_INVALID,
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MLX5_FMR_VALID,
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MLX5_FMR_BUSY,
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};
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struct mlx5_ib_fmr {
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struct ib_fmr ibfmr;
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struct mlx5_core_mr mr;
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int access_flags;
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int state;
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/* protect fmr state
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*/
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spinlock_t lock;
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u64 wrid;
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struct ib_send_wr wr[2];
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u8 page_shift;
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struct ib_fast_reg_page_list page_list;
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};
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struct mlx5_cache_ent {
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struct list_head head;
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/* sync access to the cahce entry
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*/
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spinlock_t lock;
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struct dentry *dir;
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char name[4];
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u32 order;
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u32 size;
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u32 cur;
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u32 miss;
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u32 limit;
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struct dentry *fsize;
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struct dentry *fcur;
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struct dentry *fmiss;
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struct dentry *flimit;
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struct mlx5_ib_dev *dev;
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struct work_struct work;
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struct delayed_work dwork;
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int pending;
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};
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struct mlx5_mr_cache {
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struct workqueue_struct *wq;
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struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
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int stopped;
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struct dentry *root;
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unsigned long last_add;
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};
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struct mlx5_ib_resources {
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struct ib_cq *c0;
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struct ib_xrcd *x0;
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struct ib_xrcd *x1;
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struct ib_pd *p0;
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struct ib_srq *s0;
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};
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struct mlx5_ib_dev {
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struct ib_device ib_dev;
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struct mlx5_core_dev *mdev;
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MLX5_DECLARE_DOORBELL_LOCK(uar_lock);
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struct list_head eqs_list;
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int num_ports;
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int num_comp_vectors;
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/* serialize update of capability mask
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*/
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struct mutex cap_mask_mutex;
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bool ib_active;
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struct umr_common umrc;
|
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/* sync used page count stats
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*/
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spinlock_t mr_lock;
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struct mlx5_ib_resources devr;
|
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struct mlx5_mr_cache cache;
|
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struct timer_list delay_timer;
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int fill_delay;
|
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};
|
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|
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static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
|
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{
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return container_of(mcq, struct mlx5_ib_cq, mcq);
|
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}
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|
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static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
|
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{
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return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
|
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}
|
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|
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static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
|
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{
|
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return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
|
||||
}
|
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|
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static inline struct mlx5_ib_fmr *to_mfmr(struct ib_fmr *ibfmr)
|
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{
|
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return container_of(ibfmr, struct mlx5_ib_fmr, ibfmr);
|
||||
}
|
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|
||||
static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
|
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{
|
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return container_of(ibcq, struct mlx5_ib_cq, ibcq);
|
||||
}
|
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|
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static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
|
||||
{
|
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return container_of(mqp, struct mlx5_ib_qp, mqp);
|
||||
}
|
||||
|
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static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mr *mmr)
|
||||
{
|
||||
return container_of(mmr, struct mlx5_ib_mr, mmr);
|
||||
}
|
||||
|
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static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
|
||||
{
|
||||
return container_of(ibpd, struct mlx5_ib_pd, ibpd);
|
||||
}
|
||||
|
||||
static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
|
||||
{
|
||||
return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
|
||||
}
|
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|
||||
static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
|
||||
{
|
||||
return container_of(ibqp, struct mlx5_ib_qp, ibqp);
|
||||
}
|
||||
|
||||
static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
|
||||
{
|
||||
return container_of(msrq, struct mlx5_ib_srq, msrq);
|
||||
}
|
||||
|
||||
static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
|
||||
{
|
||||
return container_of(ibmr, struct mlx5_ib_mr, ibmr);
|
||||
}
|
||||
|
||||
static inline struct mlx5_ib_fast_reg_page_list *to_mfrpl(struct ib_fast_reg_page_list *ibfrpl)
|
||||
{
|
||||
return container_of(ibfrpl, struct mlx5_ib_fast_reg_page_list, ibfrpl);
|
||||
}
|
||||
|
||||
struct mlx5_ib_ah {
|
||||
struct ib_ah ibah;
|
||||
struct mlx5_av av;
|
||||
};
|
||||
|
||||
static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah)
|
||||
{
|
||||
return container_of(ibah, struct mlx5_ib_ah, ibah);
|
||||
}
|
||||
|
||||
int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
|
||||
struct mlx5_db *db);
|
||||
void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
|
||||
void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
|
||||
void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
|
||||
void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
|
||||
int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey,
|
||||
u8 port, struct ib_wc *in_wc, struct ib_grh *in_grh,
|
||||
void *in_mad, void *response_mad);
|
||||
struct ib_ah *create_ib_ah(struct ib_ah_attr *ah_attr,
|
||||
struct mlx5_ib_ah *ah);
|
||||
struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr);
|
||||
int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr);
|
||||
int mlx5_ib_destroy_ah(struct ib_ah *ah);
|
||||
struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd,
|
||||
struct ib_srq_init_attr *init_attr,
|
||||
struct ib_udata *udata);
|
||||
int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
|
||||
enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
|
||||
int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
|
||||
int mlx5_ib_destroy_srq(struct ib_srq *srq);
|
||||
int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
|
||||
struct ib_recv_wr **bad_wr);
|
||||
struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
|
||||
struct ib_qp_init_attr *init_attr,
|
||||
struct ib_udata *udata);
|
||||
int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
|
||||
int attr_mask, struct ib_udata *udata);
|
||||
int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
|
||||
struct ib_qp_init_attr *qp_init_attr);
|
||||
int mlx5_ib_destroy_qp(struct ib_qp *qp);
|
||||
int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
|
||||
struct ib_send_wr **bad_wr);
|
||||
int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
|
||||
struct ib_recv_wr **bad_wr);
|
||||
void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n);
|
||||
struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, int entries,
|
||||
int vector, struct ib_ucontext *context,
|
||||
struct ib_udata *udata);
|
||||
int mlx5_ib_destroy_cq(struct ib_cq *cq);
|
||||
int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
|
||||
int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
|
||||
int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
|
||||
int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
|
||||
struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
|
||||
struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
|
||||
u64 virt_addr, int access_flags,
|
||||
struct ib_udata *udata);
|
||||
int mlx5_ib_dereg_mr(struct ib_mr *ibmr);
|
||||
int mlx5_ib_destroy_mr(struct ib_mr *ibmr);
|
||||
struct ib_mr *mlx5_ib_create_mr(struct ib_pd *pd,
|
||||
struct ib_mr_init_attr *mr_init_attr);
|
||||
struct ib_mr *mlx5_ib_alloc_fast_reg_mr(struct ib_pd *pd,
|
||||
int max_page_list_len);
|
||||
struct ib_fast_reg_page_list *mlx5_ib_alloc_fast_reg_page_list(struct ib_device *ibdev,
|
||||
int page_list_len);
|
||||
void mlx5_ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list);
|
||||
struct ib_fmr *mlx5_ib_fmr_alloc(struct ib_pd *pd, int acc,
|
||||
struct ib_fmr_attr *fmr_attr);
|
||||
int mlx5_ib_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
|
||||
int npages, u64 iova);
|
||||
int mlx5_ib_unmap_fmr(struct list_head *fmr_list);
|
||||
int mlx5_ib_fmr_dealloc(struct ib_fmr *ibfmr);
|
||||
int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
|
||||
struct ib_wc *in_wc, struct ib_grh *in_grh,
|
||||
struct ib_mad *in_mad, struct ib_mad *out_mad);
|
||||
struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
|
||||
struct ib_ucontext *context,
|
||||
struct ib_udata *udata);
|
||||
int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd);
|
||||
int mlx5_vector2eqn(struct mlx5_ib_dev *dev, int vector, int *eqn, int *irqn);
|
||||
int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
|
||||
int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
|
||||
int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
|
||||
struct ib_port_attr *props);
|
||||
int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
|
||||
void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
|
||||
void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift,
|
||||
int *ncont, int *order);
|
||||
void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
|
||||
int page_shift, __be64 *pas, int umr);
|
||||
void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
|
||||
int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq);
|
||||
int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
|
||||
int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
|
||||
int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift);
|
||||
void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context);
|
||||
int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
|
||||
struct ib_mr_status *mr_status);
|
||||
|
||||
static inline void init_query_mad(struct ib_smp *mad)
|
||||
{
|
||||
mad->base_version = 1;
|
||||
mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
|
||||
mad->class_version = 1;
|
||||
mad->method = IB_MGMT_METHOD_GET;
|
||||
}
|
||||
|
||||
static inline u8 convert_access(int acc)
|
||||
{
|
||||
return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
|
||||
(acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
|
||||
(acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
|
||||
(acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
|
||||
MLX5_PERM_LOCAL_READ;
|
||||
}
|
||||
|
||||
#endif /* MLX5_IB_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue