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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 09:08:05 -04:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
227
drivers/iommu/omap-iommu.h
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227
drivers/iommu/omap-iommu.h
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/*
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* omap iommu: main structures
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*
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* Copyright (C) 2008-2009 Nokia Corporation
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*
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* Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#if defined(CONFIG_ARCH_OMAP1)
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#error "iommu for this processor not implemented yet"
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#endif
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struct iotlb_entry {
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u32 da;
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u32 pa;
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u32 pgsz, prsvd, valid;
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union {
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u16 ap;
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struct {
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u32 endian, elsz, mixed;
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};
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};
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};
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struct omap_iommu {
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const char *name;
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void __iomem *regbase;
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struct device *dev;
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void *isr_priv;
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struct iommu_domain *domain;
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unsigned int refcount;
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spinlock_t iommu_lock; /* global for this whole object */
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/*
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* We don't change iopgd for a situation like pgd for a task,
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* but share it globally for each iommu.
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*/
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u32 *iopgd;
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spinlock_t page_table_lock; /* protect iopgd */
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int nr_tlb_entries;
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void *ctx; /* iommu context: registres saved area */
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int has_bus_err_back;
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};
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struct cr_regs {
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union {
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struct {
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u16 cam_l;
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u16 cam_h;
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};
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u32 cam;
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};
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union {
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struct {
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u16 ram_l;
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u16 ram_h;
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};
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u32 ram;
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};
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};
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/* architecture specific functions */
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struct iommu_functions {
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unsigned long version;
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int (*enable)(struct omap_iommu *obj);
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void (*disable)(struct omap_iommu *obj);
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void (*set_twl)(struct omap_iommu *obj, bool on);
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u32 (*fault_isr)(struct omap_iommu *obj, u32 *ra);
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void (*tlb_read_cr)(struct omap_iommu *obj, struct cr_regs *cr);
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void (*tlb_load_cr)(struct omap_iommu *obj, struct cr_regs *cr);
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struct cr_regs *(*alloc_cr)(struct omap_iommu *obj,
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struct iotlb_entry *e);
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int (*cr_valid)(struct cr_regs *cr);
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u32 (*cr_to_virt)(struct cr_regs *cr);
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void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
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ssize_t (*dump_cr)(struct omap_iommu *obj, struct cr_regs *cr,
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char *buf);
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u32 (*get_pte_attr)(struct iotlb_entry *e);
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void (*save_ctx)(struct omap_iommu *obj);
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void (*restore_ctx)(struct omap_iommu *obj);
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ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len);
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};
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#ifdef CONFIG_IOMMU_API
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/**
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* dev_to_omap_iommu() - retrieves an omap iommu object from a user device
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* @dev: iommu client device
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*/
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static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
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{
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struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
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return arch_data->iommu_dev;
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}
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#endif
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/*
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* MMU Register offsets
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*/
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#define MMU_REVISION 0x00
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#define MMU_IRQSTATUS 0x18
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#define MMU_IRQENABLE 0x1c
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#define MMU_WALKING_ST 0x40
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#define MMU_CNTL 0x44
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#define MMU_FAULT_AD 0x48
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#define MMU_TTB 0x4c
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#define MMU_LOCK 0x50
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#define MMU_LD_TLB 0x54
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#define MMU_CAM 0x58
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#define MMU_RAM 0x5c
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#define MMU_GFLUSH 0x60
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#define MMU_FLUSH_ENTRY 0x64
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#define MMU_READ_CAM 0x68
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#define MMU_READ_RAM 0x6c
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#define MMU_EMU_FAULT_AD 0x70
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#define MMU_GP_REG 0x88
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#define MMU_REG_SIZE 256
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/*
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* MMU Register bit definitions
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*/
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#define MMU_CAM_VATAG_SHIFT 12
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#define MMU_CAM_VATAG_MASK \
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((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
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#define MMU_CAM_P (1 << 3)
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#define MMU_CAM_V (1 << 2)
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#define MMU_CAM_PGSZ_MASK 3
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#define MMU_CAM_PGSZ_1M (0 << 0)
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#define MMU_CAM_PGSZ_64K (1 << 0)
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#define MMU_CAM_PGSZ_4K (2 << 0)
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#define MMU_CAM_PGSZ_16M (3 << 0)
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#define MMU_RAM_PADDR_SHIFT 12
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#define MMU_RAM_PADDR_MASK \
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((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
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#define MMU_RAM_ENDIAN_SHIFT 9
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#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
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#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
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#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
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#define MMU_RAM_ELSZ_SHIFT 7
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#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
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#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
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#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
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#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
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#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
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#define MMU_RAM_MIXED_SHIFT 6
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#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
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#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
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#define MMU_GP_REG_BUS_ERR_BACK_EN 0x1
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/*
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* utilities for super page(16MB, 1MB, 64KB and 4KB)
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*/
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#define iopgsz_max(bytes) \
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(((bytes) >= SZ_16M) ? SZ_16M : \
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((bytes) >= SZ_1M) ? SZ_1M : \
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((bytes) >= SZ_64K) ? SZ_64K : \
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((bytes) >= SZ_4K) ? SZ_4K : 0)
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#define bytes_to_iopgsz(bytes) \
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(((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
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((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
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((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
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((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
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#define iopgsz_to_bytes(iopgsz) \
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(((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
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((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
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((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
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((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
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#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
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/*
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* global functions
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*/
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extern u32 omap_iommu_arch_version(void);
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extern void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
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extern int
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omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e);
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extern void omap_iommu_save_ctx(struct device *dev);
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extern void omap_iommu_restore_ctx(struct device *dev);
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extern int omap_foreach_iommu_device(void *data,
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int (*fn)(struct device *, void *));
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extern int omap_install_iommu_arch(const struct iommu_functions *ops);
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extern void omap_uninstall_iommu_arch(const struct iommu_functions *ops);
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extern ssize_t
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omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len);
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extern size_t
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omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len);
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/*
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* register accessors
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*/
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static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
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{
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return __raw_readl(obj->regbase + offs);
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}
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static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
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{
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__raw_writel(val, obj->regbase + offs);
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}
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