mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
405
drivers/isdn/hardware/mISDN/ipac.h
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405
drivers/isdn/hardware/mISDN/ipac.h
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@ -0,0 +1,405 @@
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/*
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*
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* ipac.h Defines for the Infineon (former Siemens) ISDN
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* chip series
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*
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* Author Karsten Keil <keil@isdn4linux.de>
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*
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* Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include "iohelper.h"
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struct isac_hw {
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struct dchannel dch;
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u32 type;
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u32 off; /* offset to isac regs */
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char *name;
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spinlock_t *hwlock; /* lock HW access */
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read_reg_func *read_reg;
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write_reg_func *write_reg;
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fifo_func *read_fifo;
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fifo_func *write_fifo;
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int (*monitor)(void *, u32, u8 *, int);
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void (*release)(struct isac_hw *);
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int (*init)(struct isac_hw *);
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int (*ctrl)(struct isac_hw *, u32, u_long);
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int (*open)(struct isac_hw *, struct channel_req *);
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u8 *mon_tx;
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u8 *mon_rx;
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int mon_txp;
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int mon_txc;
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int mon_rxp;
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struct arcofi_msg *arcofi_list;
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struct timer_list arcofitimer;
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wait_queue_head_t arcofi_wait;
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u8 arcofi_bc;
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u8 arcofi_state;
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u8 mocr;
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u8 adf2;
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u8 state;
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};
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struct ipac_hw;
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struct hscx_hw {
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struct bchannel bch;
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struct ipac_hw *ip;
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u8 fifo_size;
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u8 off; /* offset to ICA or ICB */
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u8 slot;
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char log[64];
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};
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struct ipac_hw {
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struct isac_hw isac;
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struct hscx_hw hscx[2];
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char *name;
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void *hw;
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spinlock_t *hwlock; /* lock HW access */
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struct module *owner;
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u32 type;
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read_reg_func *read_reg;
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write_reg_func *write_reg;
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fifo_func *read_fifo;
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fifo_func *write_fifo;
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void (*release)(struct ipac_hw *);
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int (*init)(struct ipac_hw *);
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int (*ctrl)(struct ipac_hw *, u32, u_long);
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u8 conf;
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};
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#define IPAC_TYPE_ISAC 0x0010
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#define IPAC_TYPE_IPAC 0x0020
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#define IPAC_TYPE_ISACX 0x0040
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#define IPAC_TYPE_IPACX 0x0080
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#define IPAC_TYPE_HSCX 0x0100
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#define ISAC_USE_ARCOFI 0x1000
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/* Monitor functions */
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#define MONITOR_RX_0 0x1000
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#define MONITOR_RX_1 0x1001
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#define MONITOR_TX_0 0x2000
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#define MONITOR_TX_1 0x2001
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/* All registers original Siemens Spec */
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/* IPAC/ISAC registers */
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#define ISAC_MASK 0x20
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#define ISAC_ISTA 0x20
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#define ISAC_STAR 0x21
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#define ISAC_CMDR 0x21
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#define ISAC_EXIR 0x24
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#define ISAC_ADF2 0x39
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#define ISAC_SPCR 0x30
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#define ISAC_ADF1 0x38
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#define ISAC_CIR0 0x31
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#define ISAC_CIX0 0x31
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#define ISAC_CIR1 0x33
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#define ISAC_CIX1 0x33
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#define ISAC_STCR 0x37
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#define ISAC_MODE 0x22
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#define ISAC_RSTA 0x27
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#define ISAC_RBCL 0x25
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#define ISAC_RBCH 0x2A
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#define ISAC_TIMR 0x23
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#define ISAC_SQXR 0x3b
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#define ISAC_SQRR 0x3b
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#define ISAC_MOSR 0x3a
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#define ISAC_MOCR 0x3a
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#define ISAC_MOR0 0x32
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#define ISAC_MOX0 0x32
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#define ISAC_MOR1 0x34
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#define ISAC_MOX1 0x34
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#define ISAC_RBCH_XAC 0x80
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#define IPAC_D_TIN2 0x01
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/* IPAC/HSCX */
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#define IPAC_ISTAB 0x20 /* RD */
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#define IPAC_MASKB 0x20 /* WR */
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#define IPAC_STARB 0x21 /* RD */
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#define IPAC_CMDRB 0x21 /* WR */
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#define IPAC_MODEB 0x22 /* R/W */
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#define IPAC_EXIRB 0x24 /* RD */
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#define IPAC_RBCLB 0x25 /* RD */
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#define IPAC_RAH1 0x26 /* WR */
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#define IPAC_RAH2 0x27 /* WR */
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#define IPAC_RSTAB 0x27 /* RD */
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#define IPAC_RAL1 0x28 /* R/W */
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#define IPAC_RAL2 0x29 /* WR */
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#define IPAC_RHCRB 0x29 /* RD */
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#define IPAC_XBCL 0x2A /* WR */
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#define IPAC_CCR2 0x2C /* R/W */
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#define IPAC_RBCHB 0x2D /* RD */
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#define IPAC_XBCH 0x2D /* WR */
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#define HSCX_VSTR 0x2E /* RD */
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#define IPAC_RLCR 0x2E /* WR */
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#define IPAC_CCR1 0x2F /* R/W */
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#define IPAC_TSAX 0x30 /* WR */
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#define IPAC_TSAR 0x31 /* WR */
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#define IPAC_XCCR 0x32 /* WR */
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#define IPAC_RCCR 0x33 /* WR */
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/* IPAC_ISTAB/IPAC_MASKB bits */
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#define IPAC_B_XPR 0x10
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#define IPAC_B_RPF 0x40
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#define IPAC_B_RME 0x80
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#define IPAC_B_ON 0x2F
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/* IPAC_EXIRB bits */
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#define IPAC_B_RFS 0x04
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#define IPAC_B_RFO 0x10
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#define IPAC_B_XDU 0x40
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#define IPAC_B_XMR 0x80
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/* IPAC special registers */
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#define IPAC_CONF 0xC0 /* R/W */
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#define IPAC_ISTA 0xC1 /* RD */
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#define IPAC_MASK 0xC1 /* WR */
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#define IPAC_ID 0xC2 /* RD */
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#define IPAC_ACFG 0xC3 /* R/W */
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#define IPAC_AOE 0xC4 /* R/W */
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#define IPAC_ARX 0xC5 /* RD */
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#define IPAC_ATX 0xC5 /* WR */
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#define IPAC_PITA1 0xC6 /* R/W */
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#define IPAC_PITA2 0xC7 /* R/W */
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#define IPAC_POTA1 0xC8 /* R/W */
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#define IPAC_POTA2 0xC9 /* R/W */
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#define IPAC_PCFG 0xCA /* R/W */
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#define IPAC_SCFG 0xCB /* R/W */
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#define IPAC_TIMR2 0xCC /* R/W */
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/* IPAC_ISTA/_MASK bits */
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#define IPAC__EXB 0x01
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#define IPAC__ICB 0x02
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#define IPAC__EXA 0x04
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#define IPAC__ICA 0x08
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#define IPAC__EXD 0x10
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#define IPAC__ICD 0x20
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#define IPAC__INT0 0x40
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#define IPAC__INT1 0x80
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#define IPAC__ON 0xC0
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/* HSCX ISTA/MASK bits */
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#define HSCX__EXB 0x01
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#define HSCX__EXA 0x02
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#define HSCX__ICA 0x04
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/* ISAC/ISACX/IPAC/IPACX L1 commands */
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#define ISAC_CMD_TIM 0x0
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#define ISAC_CMD_RS 0x1
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#define ISAC_CMD_SCZ 0x4
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#define ISAC_CMD_SSZ 0x2
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#define ISAC_CMD_AR8 0x8
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#define ISAC_CMD_AR10 0x9
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#define ISAC_CMD_ARL 0xA
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#define ISAC_CMD_DUI 0xF
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/* ISAC/ISACX/IPAC/IPACX L1 indications */
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#define ISAC_IND_RS 0x1
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#define ISAC_IND_PU 0x7
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#define ISAC_IND_DR 0x0
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#define ISAC_IND_SD 0x2
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#define ISAC_IND_DIS 0x3
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#define ISAC_IND_EI 0x6
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#define ISAC_IND_RSY 0x4
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#define ISAC_IND_ARD 0x8
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#define ISAC_IND_TI 0xA
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#define ISAC_IND_ATI 0xB
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#define ISAC_IND_AI8 0xC
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#define ISAC_IND_AI10 0xD
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#define ISAC_IND_DID 0xF
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/* the new ISACX / IPACX */
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/* D-channel registers */
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#define ISACX_RFIFOD 0x00 /* RD */
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#define ISACX_XFIFOD 0x00 /* WR */
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#define ISACX_ISTAD 0x20 /* RD */
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#define ISACX_MASKD 0x20 /* WR */
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#define ISACX_STARD 0x21 /* RD */
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#define ISACX_CMDRD 0x21 /* WR */
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#define ISACX_MODED 0x22 /* R/W */
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#define ISACX_EXMD1 0x23 /* R/W */
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#define ISACX_TIMR1 0x24 /* R/W */
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#define ISACX_SAP1 0x25 /* WR */
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#define ISACX_SAP2 0x26 /* WR */
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#define ISACX_RBCLD 0x26 /* RD */
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#define ISACX_RBCHD 0x27 /* RD */
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#define ISACX_TEI1 0x27 /* WR */
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#define ISACX_TEI2 0x28 /* WR */
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#define ISACX_RSTAD 0x28 /* RD */
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#define ISACX_TMD 0x29 /* R/W */
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#define ISACX_CIR0 0x2E /* RD */
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#define ISACX_CIX0 0x2E /* WR */
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#define ISACX_CIR1 0x2F /* RD */
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#define ISACX_CIX1 0x2F /* WR */
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/* Transceiver registers */
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#define ISACX_TR_CONF0 0x30 /* R/W */
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#define ISACX_TR_CONF1 0x31 /* R/W */
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#define ISACX_TR_CONF2 0x32 /* R/W */
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#define ISACX_TR_STA 0x33 /* RD */
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#define ISACX_TR_CMD 0x34 /* R/W */
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#define ISACX_SQRR1 0x35 /* RD */
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#define ISACX_SQXR1 0x35 /* WR */
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#define ISACX_SQRR2 0x36 /* RD */
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#define ISACX_SQXR2 0x36 /* WR */
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#define ISACX_SQRR3 0x37 /* RD */
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#define ISACX_SQXR3 0x37 /* WR */
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#define ISACX_ISTATR 0x38 /* RD */
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#define ISACX_MASKTR 0x39 /* R/W */
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#define ISACX_TR_MODE 0x3A /* R/W */
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#define ISACX_ACFG1 0x3C /* R/W */
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#define ISACX_ACFG2 0x3D /* R/W */
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#define ISACX_AOE 0x3E /* R/W */
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#define ISACX_ARX 0x3F /* RD */
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#define ISACX_ATX 0x3F /* WR */
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/* IOM: Timeslot, DPS, CDA */
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#define ISACX_CDA10 0x40 /* R/W */
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#define ISACX_CDA11 0x41 /* R/W */
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#define ISACX_CDA20 0x42 /* R/W */
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#define ISACX_CDA21 0x43 /* R/W */
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#define ISACX_CDA_TSDP10 0x44 /* R/W */
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#define ISACX_CDA_TSDP11 0x45 /* R/W */
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#define ISACX_CDA_TSDP20 0x46 /* R/W */
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#define ISACX_CDA_TSDP21 0x47 /* R/W */
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#define ISACX_BCHA_TSDP_BC1 0x48 /* R/W */
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#define ISACX_BCHA_TSDP_BC2 0x49 /* R/W */
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#define ISACX_BCHB_TSDP_BC1 0x4A /* R/W */
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#define ISACX_BCHB_TSDP_BC2 0x4B /* R/W */
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#define ISACX_TR_TSDP_BC1 0x4C /* R/W */
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#define ISACX_TR_TSDP_BC2 0x4D /* R/W */
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#define ISACX_CDA1_CR 0x4E /* R/W */
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#define ISACX_CDA2_CR 0x4F /* R/W */
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/* IOM: Contol, Sync transfer, Monitor */
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#define ISACX_TR_CR 0x50 /* R/W */
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#define ISACX_TRC_CR 0x50 /* R/W */
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#define ISACX_BCHA_CR 0x51 /* R/W */
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#define ISACX_BCHB_CR 0x52 /* R/W */
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#define ISACX_DCI_CR 0x53 /* R/W */
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#define ISACX_DCIC_CR 0x53 /* R/W */
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#define ISACX_MON_CR 0x54 /* R/W */
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#define ISACX_SDS1_CR 0x55 /* R/W */
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#define ISACX_SDS2_CR 0x56 /* R/W */
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#define ISACX_IOM_CR 0x57 /* R/W */
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#define ISACX_STI 0x58 /* RD */
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#define ISACX_ASTI 0x58 /* WR */
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#define ISACX_MSTI 0x59 /* R/W */
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#define ISACX_SDS_CONF 0x5A /* R/W */
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#define ISACX_MCDA 0x5B /* RD */
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#define ISACX_MOR 0x5C /* RD */
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#define ISACX_MOX 0x5C /* WR */
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#define ISACX_MOSR 0x5D /* RD */
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#define ISACX_MOCR 0x5E /* R/W */
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#define ISACX_MSTA 0x5F /* RD */
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||||
#define ISACX_MCONF 0x5F /* WR */
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||||
|
||||
/* Interrupt and general registers */
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||||
#define ISACX_ISTA 0x60 /* RD */
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||||
#define ISACX_MASK 0x60 /* WR */
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||||
#define ISACX_AUXI 0x61 /* RD */
|
||||
#define ISACX_AUXM 0x61 /* WR */
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||||
#define ISACX_MODE1 0x62 /* R/W */
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||||
#define ISACX_MODE2 0x63 /* R/W */
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||||
#define ISACX_ID 0x64 /* RD */
|
||||
#define ISACX_SRES 0x64 /* WR */
|
||||
#define ISACX_TIMR2 0x65 /* R/W */
|
||||
|
||||
/* Register Bits */
|
||||
/* ISACX/IPACX _ISTAD (R) and _MASKD (W) */
|
||||
#define ISACX_D_XDU 0x04
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||||
#define ISACX_D_XMR 0x08
|
||||
#define ISACX_D_XPR 0x10
|
||||
#define ISACX_D_RFO 0x20
|
||||
#define ISACX_D_RPF 0x40
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||||
#define ISACX_D_RME 0x80
|
||||
|
||||
/* ISACX/IPACX _ISTA (R) and _MASK (W) */
|
||||
#define ISACX__ICD 0x01
|
||||
#define ISACX__MOS 0x02
|
||||
#define ISACX__TRAN 0x04
|
||||
#define ISACX__AUX 0x08
|
||||
#define ISACX__CIC 0x10
|
||||
#define ISACX__ST 0x20
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||||
#define IPACX__ICB 0x40
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||||
#define IPACX__ICA 0x80
|
||||
#define IPACX__ON 0x2C
|
||||
|
||||
/* ISACX/IPACX _CMDRD (W) */
|
||||
#define ISACX_CMDRD_XRES 0x01
|
||||
#define ISACX_CMDRD_XME 0x02
|
||||
#define ISACX_CMDRD_XTF 0x08
|
||||
#define ISACX_CMDRD_STI 0x10
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||||
#define ISACX_CMDRD_RRES 0x40
|
||||
#define ISACX_CMDRD_RMC 0x80
|
||||
|
||||
/* ISACX/IPACX _RSTAD (R) */
|
||||
#define ISACX_RSTAD_TA 0x01
|
||||
#define ISACX_RSTAD_CR 0x02
|
||||
#define ISACX_RSTAD_SA0 0x04
|
||||
#define ISACX_RSTAD_SA1 0x08
|
||||
#define ISACX_RSTAD_RAB 0x10
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||||
#define ISACX_RSTAD_CRC 0x20
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||||
#define ISACX_RSTAD_RDO 0x40
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||||
#define ISACX_RSTAD_VFR 0x80
|
||||
|
||||
/* ISACX/IPACX _CIR0 (R) */
|
||||
#define ISACX_CIR0_BAS 0x01
|
||||
#define ISACX_CIR0_SG 0x08
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||||
#define ISACX_CIR0_CIC1 0x08
|
||||
#define ISACX_CIR0_CIC0 0x08
|
||||
|
||||
/* B-channel registers */
|
||||
#define IPACX_OFF_ICA 0x70
|
||||
#define IPACX_OFF_ICB 0x80
|
||||
|
||||
/* ICA: IPACX_OFF_ICA + Reg ICB: IPACX_OFF_ICB + Reg */
|
||||
|
||||
#define IPACX_ISTAB 0x00 /* RD */
|
||||
#define IPACX_MASKB 0x00 /* WR */
|
||||
#define IPACX_STARB 0x01 /* RD */
|
||||
#define IPACX_CMDRB 0x01 /* WR */
|
||||
#define IPACX_MODEB 0x02 /* R/W */
|
||||
#define IPACX_EXMB 0x03 /* R/W */
|
||||
#define IPACX_RAH1 0x05 /* WR */
|
||||
#define IPACX_RAH2 0x06 /* WR */
|
||||
#define IPACX_RBCLB 0x06 /* RD */
|
||||
#define IPACX_RBCHB 0x07 /* RD */
|
||||
#define IPACX_RAL1 0x07 /* WR */
|
||||
#define IPACX_RAL2 0x08 /* WR */
|
||||
#define IPACX_RSTAB 0x08 /* RD */
|
||||
#define IPACX_TMB 0x09 /* R/W */
|
||||
#define IPACX_RFIFOB 0x0A /* RD */
|
||||
#define IPACX_XFIFOB 0x0A /* WR */
|
||||
|
||||
/* IPACX_ISTAB / IPACX_MASKB bits */
|
||||
#define IPACX_B_XDU 0x04
|
||||
#define IPACX_B_XPR 0x10
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||||
#define IPACX_B_RFO 0x20
|
||||
#define IPACX_B_RPF 0x40
|
||||
#define IPACX_B_RME 0x80
|
||||
|
||||
#define IPACX_B_ON 0x0B
|
||||
|
||||
extern int mISDNisac_init(struct isac_hw *, void *);
|
||||
extern irqreturn_t mISDNisac_irq(struct isac_hw *, u8);
|
||||
extern u32 mISDNipac_init(struct ipac_hw *, void *);
|
||||
extern irqreturn_t mISDNipac_irq(struct ipac_hw *, int);
|
||||
Loading…
Add table
Add a link
Reference in a new issue