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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
305
drivers/isdn/hisax/jade.c
Normal file
305
drivers/isdn/hisax/jade.c
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/* $Id: jade.c,v 1.9.2.4 2004/01/14 16:04:48 keil Exp $
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*
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* JADE stuff (derived from original hscx.c)
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*
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* Author Roland Klabunde
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* Copyright by Roland Klabunde <R.Klabunde@Berkom.de>
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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*/
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#include <linux/init.h>
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#include "hisax.h"
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#include "hscx.h"
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#include "jade.h"
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#include "isdnl1.h"
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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int
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JadeVersion(struct IsdnCardState *cs, char *s)
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{
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int ver;
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int to = 50;
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cs->BC_Write_Reg(cs, -1, 0x50, 0x19);
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while (to) {
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udelay(1);
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ver = cs->BC_Read_Reg(cs, -1, 0x60);
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to--;
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if (ver)
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break;
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if (!to) {
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printk(KERN_INFO "%s JADE version not obtainable\n", s);
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return (0);
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}
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}
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/* Wait for the JADE */
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udelay(10);
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/* Read version */
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ver = cs->BC_Read_Reg(cs, -1, 0x60);
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printk(KERN_INFO "%s JADE version: %d\n", s, ver);
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return (1);
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}
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/* Write to indirect accessible jade register set */
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static void
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jade_write_indirect(struct IsdnCardState *cs, u_char reg, u_char value)
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{
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int to = 50;
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u_char ret;
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/* Write the data */
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cs->BC_Write_Reg(cs, -1, COMM_JADE + 1, value);
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/* Say JADE we wanna write indirect reg 'reg' */
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cs->BC_Write_Reg(cs, -1, COMM_JADE, reg);
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to = 50;
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/* Wait for RDY goes high */
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while (to) {
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udelay(1);
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ret = cs->BC_Read_Reg(cs, -1, COMM_JADE);
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to--;
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if (ret & 1)
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/* Got acknowledge */
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break;
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if (!to) {
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printk(KERN_INFO "Can not see ready bit from JADE DSP (reg=0x%X, value=0x%X)\n", reg, value);
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return;
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}
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}
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}
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static void
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modejade(struct BCState *bcs, int mode, int bc)
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{
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struct IsdnCardState *cs = bcs->cs;
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int jade = bcs->hw.hscx.hscx;
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if (cs->debug & L1_DEB_HSCX) {
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debugl1(cs, "jade %c mode %d ichan %d", 'A' + jade, mode, bc);
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}
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bcs->mode = mode;
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bcs->channel = bc;
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cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (mode == L1_MODE_TRANS ? jadeMODE_TMO : 0x00));
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cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR0, (jadeCCR0_PU | jadeCCR0_ITF));
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cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR1, 0x00);
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jade_write_indirect(cs, jade_HDLC1SERRXPATH, 0x08);
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jade_write_indirect(cs, jade_HDLC2SERRXPATH, 0x08);
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jade_write_indirect(cs, jade_HDLC1SERTXPATH, 0x00);
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jade_write_indirect(cs, jade_HDLC2SERTXPATH, 0x00);
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cs->BC_Write_Reg(cs, jade, jade_HDLC_XCCR, 0x07);
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cs->BC_Write_Reg(cs, jade, jade_HDLC_RCCR, 0x07);
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if (bc == 0) {
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cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x00);
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cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x00);
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} else {
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cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x04);
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cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x04);
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}
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switch (mode) {
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case (L1_MODE_NULL):
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cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, jadeMODE_TMO);
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break;
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case (L1_MODE_TRANS):
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cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_TMO | jadeMODE_RAC | jadeMODE_XAC));
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break;
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case (L1_MODE_HDLC):
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cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_RAC | jadeMODE_XAC));
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break;
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}
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if (mode) {
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cs->BC_Write_Reg(cs, jade, jade_HDLC_RCMD, (jadeRCMD_RRES | jadeRCMD_RMC));
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cs->BC_Write_Reg(cs, jade, jade_HDLC_XCMD, jadeXCMD_XRES);
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/* Unmask ints */
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cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0xF8);
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}
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else
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/* Mask ints */
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cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0x00);
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}
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static void
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jade_l2l1(struct PStack *st, int pr, void *arg)
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{
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struct BCState *bcs = st->l1.bcs;
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struct sk_buff *skb = arg;
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u_long flags;
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switch (pr) {
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case (PH_DATA | REQUEST):
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spin_lock_irqsave(&bcs->cs->lock, flags);
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if (bcs->tx_skb) {
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skb_queue_tail(&bcs->squeue, skb);
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} else {
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bcs->tx_skb = skb;
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test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
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bcs->hw.hscx.count = 0;
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bcs->cs->BC_Send_Data(bcs);
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}
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spin_unlock_irqrestore(&bcs->cs->lock, flags);
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break;
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case (PH_PULL | INDICATION):
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spin_lock_irqsave(&bcs->cs->lock, flags);
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if (bcs->tx_skb) {
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printk(KERN_WARNING "jade_l2l1: this shouldn't happen\n");
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} else {
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test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
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bcs->tx_skb = skb;
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bcs->hw.hscx.count = 0;
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bcs->cs->BC_Send_Data(bcs);
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}
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spin_unlock_irqrestore(&bcs->cs->lock, flags);
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break;
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case (PH_PULL | REQUEST):
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if (!bcs->tx_skb) {
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test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
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st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
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} else
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test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
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break;
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case (PH_ACTIVATE | REQUEST):
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spin_lock_irqsave(&bcs->cs->lock, flags);
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test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
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modejade(bcs, st->l1.mode, st->l1.bc);
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spin_unlock_irqrestore(&bcs->cs->lock, flags);
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l1_msg_b(st, pr, arg);
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break;
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case (PH_DEACTIVATE | REQUEST):
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l1_msg_b(st, pr, arg);
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break;
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case (PH_DEACTIVATE | CONFIRM):
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spin_lock_irqsave(&bcs->cs->lock, flags);
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test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
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test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
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modejade(bcs, 0, st->l1.bc);
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spin_unlock_irqrestore(&bcs->cs->lock, flags);
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st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
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break;
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}
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}
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static void
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close_jadestate(struct BCState *bcs)
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{
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modejade(bcs, 0, bcs->channel);
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if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
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kfree(bcs->hw.hscx.rcvbuf);
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bcs->hw.hscx.rcvbuf = NULL;
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kfree(bcs->blog);
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bcs->blog = NULL;
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skb_queue_purge(&bcs->rqueue);
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skb_queue_purge(&bcs->squeue);
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if (bcs->tx_skb) {
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dev_kfree_skb_any(bcs->tx_skb);
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bcs->tx_skb = NULL;
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test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
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}
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}
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}
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static int
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open_jadestate(struct IsdnCardState *cs, struct BCState *bcs)
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{
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if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
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if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
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printk(KERN_WARNING
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"HiSax: No memory for hscx.rcvbuf\n");
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test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
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return (1);
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}
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if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
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printk(KERN_WARNING
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"HiSax: No memory for bcs->blog\n");
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test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
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kfree(bcs->hw.hscx.rcvbuf);
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bcs->hw.hscx.rcvbuf = NULL;
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return (2);
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}
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skb_queue_head_init(&bcs->rqueue);
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skb_queue_head_init(&bcs->squeue);
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}
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bcs->tx_skb = NULL;
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test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
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bcs->event = 0;
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bcs->hw.hscx.rcvidx = 0;
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bcs->tx_cnt = 0;
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return (0);
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}
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static int
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setstack_jade(struct PStack *st, struct BCState *bcs)
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{
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bcs->channel = st->l1.bc;
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if (open_jadestate(st->l1.hardware, bcs))
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return (-1);
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st->l1.bcs = bcs;
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st->l2.l2l1 = jade_l2l1;
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setstack_manager(st);
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bcs->st = st;
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setstack_l1_B(st);
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return (0);
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}
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void
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clear_pending_jade_ints(struct IsdnCardState *cs)
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{
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int val;
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cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00);
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cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00);
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val = cs->BC_Read_Reg(cs, 1, jade_HDLC_ISR);
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debugl1(cs, "jade B ISTA %x", val);
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val = cs->BC_Read_Reg(cs, 0, jade_HDLC_ISR);
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debugl1(cs, "jade A ISTA %x", val);
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val = cs->BC_Read_Reg(cs, 1, jade_HDLC_STAR);
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debugl1(cs, "jade B STAR %x", val);
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val = cs->BC_Read_Reg(cs, 0, jade_HDLC_STAR);
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debugl1(cs, "jade A STAR %x", val);
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/* Unmask ints */
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cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0xF8);
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cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0xF8);
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}
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void
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initjade(struct IsdnCardState *cs)
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{
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cs->bcs[0].BC_SetStack = setstack_jade;
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cs->bcs[1].BC_SetStack = setstack_jade;
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cs->bcs[0].BC_Close = close_jadestate;
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cs->bcs[1].BC_Close = close_jadestate;
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cs->bcs[0].hw.hscx.hscx = 0;
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cs->bcs[1].hw.hscx.hscx = 1;
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/* Stop DSP audio tx/rx */
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jade_write_indirect(cs, 0x11, 0x0f);
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jade_write_indirect(cs, 0x17, 0x2f);
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/* Transparent Mode, RxTx inactive, No Test, No RFS/TFS */
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cs->BC_Write_Reg(cs, 0, jade_HDLC_MODE, jadeMODE_TMO);
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cs->BC_Write_Reg(cs, 1, jade_HDLC_MODE, jadeMODE_TMO);
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/* Power down, 1-Idle, RxTx least significant bit first */
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cs->BC_Write_Reg(cs, 0, jade_HDLC_CCR0, 0x00);
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cs->BC_Write_Reg(cs, 1, jade_HDLC_CCR0, 0x00);
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/* Mask all interrupts */
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cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00);
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cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00);
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/* Setup host access to hdlc controller */
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jade_write_indirect(cs, jade_HDLCCNTRACCESS, (jadeINDIRECT_HAH1 | jadeINDIRECT_HAH2));
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/* Unmask HDLC int (don't forget DSP int later on)*/
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cs->BC_Write_Reg(cs, -1, jade_INT, (jadeINT_HDLC1 | jadeINT_HDLC2));
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/* once again TRANSPARENT */
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modejade(cs->bcs, 0, 0);
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modejade(cs->bcs + 1, 0, 0);
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}
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