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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
349
drivers/isdn/hisax/telespci.c
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349
drivers/isdn/hisax/telespci.c
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/* $Id: telespci.c,v 2.23.2.3 2004/01/13 14:31:26 keil Exp $
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*
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* low level stuff for Teles PCI isdn cards
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*
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* Author Ton van Rosmalen
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* Karsten Keil
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* Copyright by Ton van Rosmalen
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* by Karsten Keil <keil@isdn4linux.de>
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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*/
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#include <linux/init.h>
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#include "hisax.h"
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#include "isac.h"
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#include "hscx.h"
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#include "isdnl1.h"
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#include <linux/pci.h>
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static const char *telespci_revision = "$Revision: 2.23.2.3 $";
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#define ZORAN_PO_RQ_PEN 0x02000000
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#define ZORAN_PO_WR 0x00800000
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#define ZORAN_PO_GID0 0x00000000
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#define ZORAN_PO_GID1 0x00100000
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#define ZORAN_PO_GREG0 0x00000000
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#define ZORAN_PO_GREG1 0x00010000
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#define ZORAN_PO_DMASK 0xFF
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#define WRITE_ADDR_ISAC (ZORAN_PO_WR | ZORAN_PO_GID0 | ZORAN_PO_GREG0)
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#define READ_DATA_ISAC (ZORAN_PO_GID0 | ZORAN_PO_GREG1)
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#define WRITE_DATA_ISAC (ZORAN_PO_WR | ZORAN_PO_GID0 | ZORAN_PO_GREG1)
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#define WRITE_ADDR_HSCX (ZORAN_PO_WR | ZORAN_PO_GID1 | ZORAN_PO_GREG0)
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#define READ_DATA_HSCX (ZORAN_PO_GID1 | ZORAN_PO_GREG1)
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#define WRITE_DATA_HSCX (ZORAN_PO_WR | ZORAN_PO_GID1 | ZORAN_PO_GREG1)
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#define ZORAN_WAIT_NOBUSY do { \
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portdata = readl(adr + 0x200); \
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} while (portdata & ZORAN_PO_RQ_PEN)
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static inline u_char
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readisac(void __iomem *adr, u_char off)
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{
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register unsigned int portdata;
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ZORAN_WAIT_NOBUSY;
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/* set address for ISAC */
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writel(WRITE_ADDR_ISAC | off, adr + 0x200);
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ZORAN_WAIT_NOBUSY;
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/* read data from ISAC */
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writel(READ_DATA_ISAC, adr + 0x200);
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ZORAN_WAIT_NOBUSY;
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return ((u_char)(portdata & ZORAN_PO_DMASK));
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}
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static inline void
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writeisac(void __iomem *adr, u_char off, u_char data)
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{
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register unsigned int portdata;
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ZORAN_WAIT_NOBUSY;
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/* set address for ISAC */
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writel(WRITE_ADDR_ISAC | off, adr + 0x200);
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ZORAN_WAIT_NOBUSY;
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/* write data to ISAC */
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writel(WRITE_DATA_ISAC | data, adr + 0x200);
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ZORAN_WAIT_NOBUSY;
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}
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static inline u_char
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readhscx(void __iomem *adr, int hscx, u_char off)
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{
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register unsigned int portdata;
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ZORAN_WAIT_NOBUSY;
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/* set address for HSCX */
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writel(WRITE_ADDR_HSCX | ((hscx ? 0x40 : 0) + off), adr + 0x200);
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ZORAN_WAIT_NOBUSY;
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/* read data from HSCX */
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writel(READ_DATA_HSCX, adr + 0x200);
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ZORAN_WAIT_NOBUSY;
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return ((u_char)(portdata & ZORAN_PO_DMASK));
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}
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static inline void
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writehscx(void __iomem *adr, int hscx, u_char off, u_char data)
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{
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register unsigned int portdata;
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ZORAN_WAIT_NOBUSY;
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/* set address for HSCX */
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writel(WRITE_ADDR_HSCX | ((hscx ? 0x40 : 0) + off), adr + 0x200);
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ZORAN_WAIT_NOBUSY;
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/* write data to HSCX */
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writel(WRITE_DATA_HSCX | data, adr + 0x200);
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ZORAN_WAIT_NOBUSY;
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}
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static inline void
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read_fifo_isac(void __iomem *adr, u_char *data, int size)
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{
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register unsigned int portdata;
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register int i;
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ZORAN_WAIT_NOBUSY;
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/* read data from ISAC */
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for (i = 0; i < size; i++) {
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/* set address for ISAC fifo */
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writel(WRITE_ADDR_ISAC | 0x1E, adr + 0x200);
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ZORAN_WAIT_NOBUSY;
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writel(READ_DATA_ISAC, adr + 0x200);
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ZORAN_WAIT_NOBUSY;
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data[i] = (u_char)(portdata & ZORAN_PO_DMASK);
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}
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}
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static void
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write_fifo_isac(void __iomem *adr, u_char *data, int size)
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{
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register unsigned int portdata;
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register int i;
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ZORAN_WAIT_NOBUSY;
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/* write data to ISAC */
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for (i = 0; i < size; i++) {
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/* set address for ISAC fifo */
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writel(WRITE_ADDR_ISAC | 0x1E, adr + 0x200);
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ZORAN_WAIT_NOBUSY;
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writel(WRITE_DATA_ISAC | data[i], adr + 0x200);
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ZORAN_WAIT_NOBUSY;
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}
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}
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static inline void
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read_fifo_hscx(void __iomem *adr, int hscx, u_char *data, int size)
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{
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register unsigned int portdata;
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register int i;
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ZORAN_WAIT_NOBUSY;
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/* read data from HSCX */
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for (i = 0; i < size; i++) {
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/* set address for HSCX fifo */
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writel(WRITE_ADDR_HSCX | (hscx ? 0x5F : 0x1F), adr + 0x200);
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ZORAN_WAIT_NOBUSY;
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writel(READ_DATA_HSCX, adr + 0x200);
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ZORAN_WAIT_NOBUSY;
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data[i] = (u_char) (portdata & ZORAN_PO_DMASK);
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}
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}
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static inline void
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write_fifo_hscx(void __iomem *adr, int hscx, u_char *data, int size)
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{
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unsigned int portdata;
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register int i;
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ZORAN_WAIT_NOBUSY;
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/* write data to HSCX */
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for (i = 0; i < size; i++) {
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/* set address for HSCX fifo */
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writel(WRITE_ADDR_HSCX | (hscx ? 0x5F : 0x1F), adr + 0x200);
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ZORAN_WAIT_NOBUSY;
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writel(WRITE_DATA_HSCX | data[i], adr + 0x200);
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ZORAN_WAIT_NOBUSY;
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udelay(10);
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}
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}
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/* Interface functions */
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static u_char
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ReadISAC(struct IsdnCardState *cs, u_char offset)
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{
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return (readisac(cs->hw.teles0.membase, offset));
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}
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static void
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WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
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{
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writeisac(cs->hw.teles0.membase, offset, value);
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}
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static void
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ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size)
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{
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read_fifo_isac(cs->hw.teles0.membase, data, size);
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}
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static void
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WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size)
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{
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write_fifo_isac(cs->hw.teles0.membase, data, size);
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}
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static u_char
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ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
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{
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return (readhscx(cs->hw.teles0.membase, hscx, offset));
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}
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static void
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WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
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{
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writehscx(cs->hw.teles0.membase, hscx, offset, value);
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}
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/*
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* fast interrupt HSCX stuff goes here
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*/
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#define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
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#define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
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#define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
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#define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
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#include "hscx_irq.c"
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static irqreturn_t
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telespci_interrupt(int intno, void *dev_id)
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{
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struct IsdnCardState *cs = dev_id;
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u_char hval, ival;
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u_long flags;
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spin_lock_irqsave(&cs->lock, flags);
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hval = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA);
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if (hval)
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hscx_int_main(cs, hval);
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ival = readisac(cs->hw.teles0.membase, ISAC_ISTA);
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if ((hval | ival) == 0) {
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spin_unlock_irqrestore(&cs->lock, flags);
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return IRQ_NONE;
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}
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if (ival)
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isac_interrupt(cs, ival);
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/* Clear interrupt register for Zoran PCI controller */
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writel(0x70000000, cs->hw.teles0.membase + 0x3C);
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writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0xFF);
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writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0xFF);
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writeisac(cs->hw.teles0.membase, ISAC_MASK, 0xFF);
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writeisac(cs->hw.teles0.membase, ISAC_MASK, 0x0);
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writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0x0);
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writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0x0);
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spin_unlock_irqrestore(&cs->lock, flags);
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return IRQ_HANDLED;
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}
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static void
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release_io_telespci(struct IsdnCardState *cs)
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{
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iounmap(cs->hw.teles0.membase);
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}
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static int
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TelesPCI_card_msg(struct IsdnCardState *cs, int mt, void *arg)
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{
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u_long flags;
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switch (mt) {
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case CARD_RESET:
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return (0);
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case CARD_RELEASE:
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release_io_telespci(cs);
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return (0);
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case CARD_INIT:
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spin_lock_irqsave(&cs->lock, flags);
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inithscxisac(cs, 3);
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spin_unlock_irqrestore(&cs->lock, flags);
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return (0);
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case CARD_TEST:
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return (0);
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}
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return (0);
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}
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static struct pci_dev *dev_tel = NULL;
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int setup_telespci(struct IsdnCard *card)
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{
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struct IsdnCardState *cs = card->cs;
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char tmp[64];
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strcpy(tmp, telespci_revision);
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printk(KERN_INFO "HiSax: Teles/PCI driver Rev. %s\n", HiSax_getrev(tmp));
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if (cs->typ != ISDN_CTYPE_TELESPCI)
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return (0);
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if ((dev_tel = hisax_find_pci_device(PCI_VENDOR_ID_ZORAN, PCI_DEVICE_ID_ZORAN_36120, dev_tel))) {
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if (pci_enable_device(dev_tel))
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return (0);
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cs->irq = dev_tel->irq;
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if (!cs->irq) {
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printk(KERN_WARNING "Teles: No IRQ for PCI card found\n");
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return (0);
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}
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cs->hw.teles0.membase = ioremap(pci_resource_start(dev_tel, 0),
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PAGE_SIZE);
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printk(KERN_INFO "Found: Zoran, base-address: 0x%llx, irq: 0x%x\n",
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(unsigned long long)pci_resource_start(dev_tel, 0),
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dev_tel->irq);
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} else {
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printk(KERN_WARNING "TelesPCI: No PCI card found\n");
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return (0);
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}
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/* Initialize Zoran PCI controller */
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writel(0x00000000, cs->hw.teles0.membase + 0x28);
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writel(0x01000000, cs->hw.teles0.membase + 0x28);
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writel(0x01000000, cs->hw.teles0.membase + 0x28);
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writel(0x7BFFFFFF, cs->hw.teles0.membase + 0x2C);
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writel(0x70000000, cs->hw.teles0.membase + 0x3C);
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writel(0x61000000, cs->hw.teles0.membase + 0x40);
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/* writel(0x00800000, cs->hw.teles0.membase + 0x200); */
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printk(KERN_INFO
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"HiSax: Teles PCI config irq:%d mem:%p\n",
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cs->irq,
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cs->hw.teles0.membase);
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setup_isac(cs);
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cs->readisac = &ReadISAC;
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cs->writeisac = &WriteISAC;
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cs->readisacfifo = &ReadISACfifo;
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cs->writeisacfifo = &WriteISACfifo;
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cs->BC_Read_Reg = &ReadHSCX;
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cs->BC_Write_Reg = &WriteHSCX;
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cs->BC_Send_Data = &hscx_fill_fifo;
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cs->cardmsg = &TelesPCI_card_msg;
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cs->irq_func = &telespci_interrupt;
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cs->irq_flags |= IRQF_SHARED;
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ISACVersion(cs, "TelesPCI:");
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if (HscxVersion(cs, "TelesPCI:")) {
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printk(KERN_WARNING
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"TelesPCI: wrong HSCX versions check IO/MEM addresses\n");
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release_io_telespci(cs);
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return (0);
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}
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return (1);
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}
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