mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 08:08:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
471
drivers/media/pci/cx18/cx18-av-audio.c
Normal file
471
drivers/media/pci/cx18/cx18-av-audio.c
Normal file
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@ -0,0 +1,471 @@
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/*
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* cx18 ADEC audio functions
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*
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* Derived from cx25840-audio.c
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*
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* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
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* Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#include "cx18-driver.h"
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static int set_audclk_freq(struct cx18 *cx, u32 freq)
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{
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struct cx18_av_state *state = &cx->av_state;
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if (freq != 32000 && freq != 44100 && freq != 48000)
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return -EINVAL;
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/*
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* The PLL parameters are based on the external crystal frequency that
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* would ideally be:
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*
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* NTSC Color subcarrier freq * 8 =
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* 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
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*
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* The accidents of history and rationale that explain from where this
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* combination of magic numbers originate can be found in:
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*
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* [1] Abrahams, I. C., "Choice of Chrominance Subcarrier Frequency in
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* the NTSC Standards", Proceedings of the I-R-E, January 1954, pp 79-80
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*
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* [2] Abrahams, I. C., "The 'Frequency Interleaving' Principle in the
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* NTSC Standards", Proceedings of the I-R-E, January 1954, pp 81-83
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*
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* As Mike Bradley has rightly pointed out, it's not the exact crystal
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* frequency that matters, only that all parts of the driver and
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* firmware are using the same value (close to the ideal value).
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*
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* Since I have a strong suspicion that, if the firmware ever assumes a
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* crystal value at all, it will assume 28.636360 MHz, the crystal
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* freq used in calculations in this driver will be:
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*
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* xtal_freq = 28.636360 MHz
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*
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* an error of less than 0.13 ppm which is way, way better than any off
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* the shelf crystal will have for accuracy anyway.
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*
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* Below I aim to run the PLLs' VCOs near 400 MHz to minimze error.
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*
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* Many thanks to Jeff Campbell and Mike Bradley for their extensive
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* investigation, experimentation, testing, and suggested solutions of
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* of audio/video sync problems with SVideo and CVBS captures.
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*/
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if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
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switch (freq) {
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case 32000:
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20
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*/
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cx18_av_write4(cx, 0x108, 0x200d040f);
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/* VID_PLL Fraction = 0x2be2fe */
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/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
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cx18_av_write4(cx, 0x10c, 0x002be2fe);
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/* AUX_PLL Fraction = 0x176740c */
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/* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/
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cx18_av_write4(cx, 0x110, 0x0176740c);
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/* src3/4/6_ctl */
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/* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */
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cx18_av_write4(cx, 0x900, 0x0801f77f);
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cx18_av_write4(cx, 0x904, 0x0801f77f);
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cx18_av_write4(cx, 0x90c, 0x0801f77f);
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/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x20 */
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cx18_av_write(cx, 0x127, 0x60);
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/* AUD_COUNT = 0x2fff = 8 samples * 4 * 384 - 1 */
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cx18_av_write4(cx, 0x12c, 0x11202fff);
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/*
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* EN_AV_LOCK = 0
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* VID_COUNT = 0x0d2ef8 = 107999.000 * 8 =
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* ((8 samples/32,000) * (13,500,000 * 8) * 4 - 1) * 8
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*/
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cx18_av_write4(cx, 0x128, 0xa00d2ef8);
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break;
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case 44100:
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x18
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*/
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cx18_av_write4(cx, 0x108, 0x180e040f);
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/* VID_PLL Fraction = 0x2be2fe */
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/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
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cx18_av_write4(cx, 0x10c, 0x002be2fe);
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/* AUX_PLL Fraction = 0x062a1f2 */
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/* xtal * 0xe.3150f90/0x18 = 44100 * 384: 406 MHz p-pd*/
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cx18_av_write4(cx, 0x110, 0x0062a1f2);
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/* src3/4/6_ctl */
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/* 0x1.6d59 = (4 * xtal/8*2/455) / 44100 */
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cx18_av_write4(cx, 0x900, 0x08016d59);
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cx18_av_write4(cx, 0x904, 0x08016d59);
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cx18_av_write4(cx, 0x90c, 0x08016d59);
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/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x18 */
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cx18_av_write(cx, 0x127, 0x58);
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/* AUD_COUNT = 0x92ff = 49 samples * 2 * 384 - 1 */
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cx18_av_write4(cx, 0x12c, 0x112092ff);
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/*
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* EN_AV_LOCK = 0
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* VID_COUNT = 0x1d4bf8 = 239999.000 * 8 =
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* ((49 samples/44,100) * (13,500,000 * 8) * 2 - 1) * 8
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*/
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cx18_av_write4(cx, 0x128, 0xa01d4bf8);
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break;
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case 48000:
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x16
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*/
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cx18_av_write4(cx, 0x108, 0x160e040f);
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/* VID_PLL Fraction = 0x2be2fe */
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/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
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cx18_av_write4(cx, 0x10c, 0x002be2fe);
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/* AUX_PLL Fraction = 0x05227ad */
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/* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz p-pd*/
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cx18_av_write4(cx, 0x110, 0x005227ad);
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/* src3/4/6_ctl */
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/* 0x1.4faa = (4 * xtal/8*2/455) / 48000 */
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cx18_av_write4(cx, 0x900, 0x08014faa);
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cx18_av_write4(cx, 0x904, 0x08014faa);
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cx18_av_write4(cx, 0x90c, 0x08014faa);
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/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */
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cx18_av_write(cx, 0x127, 0x56);
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/* AUD_COUNT = 0x5fff = 4 samples * 16 * 384 - 1 */
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cx18_av_write4(cx, 0x12c, 0x11205fff);
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/*
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* EN_AV_LOCK = 0
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* VID_COUNT = 0x1193f8 = 143999.000 * 8 =
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* ((4 samples/48,000) * (13,500,000 * 8) * 16 - 1) * 8
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*/
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cx18_av_write4(cx, 0x128, 0xa01193f8);
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break;
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}
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} else {
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switch (freq) {
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case 32000:
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x30
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*/
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cx18_av_write4(cx, 0x108, 0x300d040f);
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/* VID_PLL Fraction = 0x2be2fe */
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/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
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cx18_av_write4(cx, 0x10c, 0x002be2fe);
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/* AUX_PLL Fraction = 0x176740c */
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/* xtal * 0xd.bb3a060/0x30 = 32000 * 256: 393 MHz p-pd*/
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cx18_av_write4(cx, 0x110, 0x0176740c);
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/* src1_ctl */
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/* 0x1.0000 = 32000/32000 */
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cx18_av_write4(cx, 0x8f8, 0x08010000);
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/* src3/4/6_ctl */
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/* 0x2.0000 = 2 * (32000/32000) */
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cx18_av_write4(cx, 0x900, 0x08020000);
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cx18_av_write4(cx, 0x904, 0x08020000);
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cx18_av_write4(cx, 0x90c, 0x08020000);
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/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x30 */
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cx18_av_write(cx, 0x127, 0x70);
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/* AUD_COUNT = 0x1fff = 8 samples * 4 * 256 - 1 */
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cx18_av_write4(cx, 0x12c, 0x11201fff);
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/*
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* EN_AV_LOCK = 0
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* VID_COUNT = 0x0d2ef8 = 107999.000 * 8 =
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* ((8 samples/32,000) * (13,500,000 * 8) * 4 - 1) * 8
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*/
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cx18_av_write4(cx, 0x128, 0xa00d2ef8);
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break;
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case 44100:
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x24
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*/
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cx18_av_write4(cx, 0x108, 0x240e040f);
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/* VID_PLL Fraction = 0x2be2fe */
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/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
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cx18_av_write4(cx, 0x10c, 0x002be2fe);
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/* AUX_PLL Fraction = 0x062a1f2 */
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/* xtal * 0xe.3150f90/0x24 = 44100 * 256: 406 MHz p-pd*/
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cx18_av_write4(cx, 0x110, 0x0062a1f2);
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/* src1_ctl */
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/* 0x1.60cd = 44100/32000 */
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cx18_av_write4(cx, 0x8f8, 0x080160cd);
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/* src3/4/6_ctl */
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/* 0x1.7385 = 2 * (32000/44100) */
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cx18_av_write4(cx, 0x900, 0x08017385);
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cx18_av_write4(cx, 0x904, 0x08017385);
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cx18_av_write4(cx, 0x90c, 0x08017385);
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/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x24 */
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cx18_av_write(cx, 0x127, 0x64);
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/* AUD_COUNT = 0x61ff = 49 samples * 2 * 256 - 1 */
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cx18_av_write4(cx, 0x12c, 0x112061ff);
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/*
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* EN_AV_LOCK = 0
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* VID_COUNT = 0x1d4bf8 = 239999.000 * 8 =
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* ((49 samples/44,100) * (13,500,000 * 8) * 2 - 1) * 8
|
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*/
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cx18_av_write4(cx, 0x128, 0xa01d4bf8);
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break;
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case 48000:
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20
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*/
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cx18_av_write4(cx, 0x108, 0x200d040f);
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/* VID_PLL Fraction = 0x2be2fe */
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/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
|
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cx18_av_write4(cx, 0x10c, 0x002be2fe);
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|
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/* AUX_PLL Fraction = 0x176740c */
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/* xtal * 0xd.bb3a060/0x20 = 48000 * 256: 393 MHz p-pd*/
|
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cx18_av_write4(cx, 0x110, 0x0176740c);
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/* src1_ctl */
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/* 0x1.8000 = 48000/32000 */
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cx18_av_write4(cx, 0x8f8, 0x08018000);
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/* src3/4/6_ctl */
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/* 0x1.5555 = 2 * (32000/48000) */
|
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cx18_av_write4(cx, 0x900, 0x08015555);
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cx18_av_write4(cx, 0x904, 0x08015555);
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cx18_av_write4(cx, 0x90c, 0x08015555);
|
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/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x20 */
|
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cx18_av_write(cx, 0x127, 0x60);
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/* AUD_COUNT = 0x3fff = 4 samples * 16 * 256 - 1 */
|
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cx18_av_write4(cx, 0x12c, 0x11203fff);
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/*
|
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* EN_AV_LOCK = 0
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* VID_COUNT = 0x1193f8 = 143999.000 * 8 =
|
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* ((4 samples/48,000) * (13,500,000 * 8) * 16 - 1) * 8
|
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*/
|
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cx18_av_write4(cx, 0x128, 0xa01193f8);
|
||||
break;
|
||||
}
|
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}
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|
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state->audclk_freq = freq;
|
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return 0;
|
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}
|
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|
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void cx18_av_audio_set_path(struct cx18 *cx)
|
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{
|
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struct cx18_av_state *state = &cx->av_state;
|
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u8 v;
|
||||
|
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/* stop microcontroller */
|
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v = cx18_av_read(cx, 0x803) & ~0x10;
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cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
|
||||
|
||||
/* assert soft reset */
|
||||
v = cx18_av_read(cx, 0x810) | 0x01;
|
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cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
|
||||
|
||||
/* Mute everything to prevent the PFFT! */
|
||||
cx18_av_write(cx, 0x8d3, 0x1f);
|
||||
|
||||
if (state->aud_input <= CX18_AV_AUDIO_SERIAL2) {
|
||||
/* Set Path1 to Serial Audio Input */
|
||||
cx18_av_write4(cx, 0x8d0, 0x01011012);
|
||||
|
||||
/* The microcontroller should not be started for the
|
||||
* non-tuner inputs: autodetection is specific for
|
||||
* TV audio. */
|
||||
} else {
|
||||
/* Set Path1 to Analog Demod Main Channel */
|
||||
cx18_av_write4(cx, 0x8d0, 0x1f063870);
|
||||
}
|
||||
|
||||
set_audclk_freq(cx, state->audclk_freq);
|
||||
|
||||
/* deassert soft reset */
|
||||
v = cx18_av_read(cx, 0x810) & ~0x01;
|
||||
cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
|
||||
|
||||
if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
|
||||
/* When the microcontroller detects the
|
||||
* audio format, it will unmute the lines */
|
||||
v = cx18_av_read(cx, 0x803) | 0x10;
|
||||
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
|
||||
}
|
||||
}
|
||||
|
||||
static void set_volume(struct cx18 *cx, int volume)
|
||||
{
|
||||
/* First convert the volume to msp3400 values (0-127) */
|
||||
int vol = volume >> 9;
|
||||
/* now scale it up to cx18_av values
|
||||
* -114dB to -96dB maps to 0
|
||||
* this should be 19, but in my testing that was 4dB too loud */
|
||||
if (vol <= 23)
|
||||
vol = 0;
|
||||
else
|
||||
vol -= 23;
|
||||
|
||||
/* PATH1_VOLUME */
|
||||
cx18_av_write(cx, 0x8d4, 228 - (vol * 2));
|
||||
}
|
||||
|
||||
static void set_bass(struct cx18 *cx, int bass)
|
||||
{
|
||||
/* PATH1_EQ_BASS_VOL */
|
||||
cx18_av_and_or(cx, 0x8d9, ~0x3f, 48 - (bass * 48 / 0xffff));
|
||||
}
|
||||
|
||||
static void set_treble(struct cx18 *cx, int treble)
|
||||
{
|
||||
/* PATH1_EQ_TREBLE_VOL */
|
||||
cx18_av_and_or(cx, 0x8db, ~0x3f, 48 - (treble * 48 / 0xffff));
|
||||
}
|
||||
|
||||
static void set_balance(struct cx18 *cx, int balance)
|
||||
{
|
||||
int bal = balance >> 8;
|
||||
if (bal > 0x80) {
|
||||
/* PATH1_BAL_LEFT */
|
||||
cx18_av_and_or(cx, 0x8d5, 0x7f, 0x80);
|
||||
/* PATH1_BAL_LEVEL */
|
||||
cx18_av_and_or(cx, 0x8d5, ~0x7f, bal & 0x7f);
|
||||
} else {
|
||||
/* PATH1_BAL_LEFT */
|
||||
cx18_av_and_or(cx, 0x8d5, 0x7f, 0x00);
|
||||
/* PATH1_BAL_LEVEL */
|
||||
cx18_av_and_or(cx, 0x8d5, ~0x7f, 0x80 - bal);
|
||||
}
|
||||
}
|
||||
|
||||
static void set_mute(struct cx18 *cx, int mute)
|
||||
{
|
||||
struct cx18_av_state *state = &cx->av_state;
|
||||
u8 v;
|
||||
|
||||
if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
|
||||
/* Must turn off microcontroller in order to mute sound.
|
||||
* Not sure if this is the best method, but it does work.
|
||||
* If the microcontroller is running, then it will undo any
|
||||
* changes to the mute register. */
|
||||
v = cx18_av_read(cx, 0x803);
|
||||
if (mute) {
|
||||
/* disable microcontroller */
|
||||
v &= ~0x10;
|
||||
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
|
||||
cx18_av_write(cx, 0x8d3, 0x1f);
|
||||
} else {
|
||||
/* enable microcontroller */
|
||||
v |= 0x10;
|
||||
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
|
||||
}
|
||||
} else {
|
||||
/* SRC1_MUTE_EN */
|
||||
cx18_av_and_or(cx, 0x8d3, ~0x2, mute ? 0x02 : 0x00);
|
||||
}
|
||||
}
|
||||
|
||||
int cx18_av_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
|
||||
{
|
||||
struct cx18 *cx = v4l2_get_subdevdata(sd);
|
||||
struct cx18_av_state *state = &cx->av_state;
|
||||
int retval;
|
||||
u8 v;
|
||||
|
||||
if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
|
||||
v = cx18_av_read(cx, 0x803) & ~0x10;
|
||||
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
|
||||
cx18_av_write(cx, 0x8d3, 0x1f);
|
||||
}
|
||||
v = cx18_av_read(cx, 0x810) | 0x1;
|
||||
cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
|
||||
|
||||
retval = set_audclk_freq(cx, freq);
|
||||
|
||||
v = cx18_av_read(cx, 0x810) & ~0x1;
|
||||
cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
|
||||
if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
|
||||
v = cx18_av_read(cx, 0x803) | 0x10;
|
||||
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int cx18_av_audio_s_ctrl(struct v4l2_ctrl *ctrl)
|
||||
{
|
||||
struct v4l2_subdev *sd = to_sd(ctrl);
|
||||
struct cx18 *cx = v4l2_get_subdevdata(sd);
|
||||
|
||||
switch (ctrl->id) {
|
||||
case V4L2_CID_AUDIO_VOLUME:
|
||||
set_volume(cx, ctrl->val);
|
||||
break;
|
||||
case V4L2_CID_AUDIO_BASS:
|
||||
set_bass(cx, ctrl->val);
|
||||
break;
|
||||
case V4L2_CID_AUDIO_TREBLE:
|
||||
set_treble(cx, ctrl->val);
|
||||
break;
|
||||
case V4L2_CID_AUDIO_BALANCE:
|
||||
set_balance(cx, ctrl->val);
|
||||
break;
|
||||
case V4L2_CID_AUDIO_MUTE:
|
||||
set_mute(cx, ctrl->val);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct v4l2_ctrl_ops cx18_av_audio_ctrl_ops = {
|
||||
.s_ctrl = cx18_av_audio_s_ctrl,
|
||||
};
|
||||
Loading…
Add table
Add a link
Reference in a new issue