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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-30 23:58:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
311
drivers/media/platform/ti-vpe/sc.c
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311
drivers/media/platform/ti-vpe/sc.c
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/*
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* Scaler library
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*
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* Copyright (c) 2013 Texas Instruments Inc.
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*
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* David Griego, <dagriego@biglakesoftware.com>
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* Dale Farnsworth, <dale@farnsworth.org>
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* Archit Taneja, <archit@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "sc.h"
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#include "sc_coeff.h"
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void sc_dump_regs(struct sc_data *sc)
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{
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struct device *dev = &sc->pdev->dev;
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u32 read_reg(struct sc_data *sc, int offset)
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{
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return ioread32(sc->base + offset);
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}
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#define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, read_reg(sc, CFG_##r))
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DUMPREG(SC0);
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DUMPREG(SC1);
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DUMPREG(SC2);
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DUMPREG(SC3);
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DUMPREG(SC4);
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DUMPREG(SC5);
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DUMPREG(SC6);
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DUMPREG(SC8);
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DUMPREG(SC9);
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DUMPREG(SC10);
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DUMPREG(SC11);
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DUMPREG(SC12);
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DUMPREG(SC13);
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DUMPREG(SC17);
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DUMPREG(SC18);
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DUMPREG(SC19);
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DUMPREG(SC20);
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DUMPREG(SC21);
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DUMPREG(SC22);
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DUMPREG(SC23);
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DUMPREG(SC24);
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DUMPREG(SC25);
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#undef DUMPREG
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}
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/*
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* set the horizontal scaler coefficients according to the ratio of output to
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* input widths, after accounting for up to two levels of decimation
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*/
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void sc_set_hs_coeffs(struct sc_data *sc, void *addr, unsigned int src_w,
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unsigned int dst_w)
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{
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int sixteenths;
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int idx;
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int i, j;
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u16 *coeff_h = addr;
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const u16 *cp;
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if (dst_w > src_w) {
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idx = HS_UP_SCALE;
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} else {
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if ((dst_w << 1) < src_w)
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dst_w <<= 1; /* first level decimation */
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if ((dst_w << 1) < src_w)
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dst_w <<= 1; /* second level decimation */
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if (dst_w == src_w) {
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idx = HS_LE_16_16_SCALE;
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} else {
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sixteenths = (dst_w << 4) / src_w;
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if (sixteenths < 8)
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sixteenths = 8;
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idx = HS_LT_9_16_SCALE + sixteenths - 8;
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}
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}
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if (idx == sc->hs_index)
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return;
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cp = scaler_hs_coeffs[idx];
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for (i = 0; i < SC_NUM_PHASES * 2; i++) {
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for (j = 0; j < SC_H_NUM_TAPS; j++)
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*coeff_h++ = *cp++;
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/*
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* for each phase, the scaler expects space for 8 coefficients
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* in it's memory. For the horizontal scaler, we copy the first
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* 7 coefficients and skip the last slot to move to the next
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* row to hold coefficients for the next phase
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*/
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coeff_h += SC_NUM_TAPS_MEM_ALIGN - SC_H_NUM_TAPS;
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}
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sc->hs_index = idx;
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sc->load_coeff_h = true;
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}
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/*
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* set the vertical scaler coefficients according to the ratio of output to
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* input heights
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*/
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void sc_set_vs_coeffs(struct sc_data *sc, void *addr, unsigned int src_h,
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unsigned int dst_h)
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{
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int sixteenths;
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int idx;
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int i, j;
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u16 *coeff_v = addr;
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const u16 *cp;
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if (dst_h > src_h) {
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idx = VS_UP_SCALE;
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} else if (dst_h == src_h) {
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idx = VS_1_TO_1_SCALE;
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} else {
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sixteenths = (dst_h << 4) / src_h;
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if (sixteenths < 8)
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sixteenths = 8;
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idx = VS_LT_9_16_SCALE + sixteenths - 8;
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}
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if (idx == sc->vs_index)
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return;
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cp = scaler_vs_coeffs[idx];
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for (i = 0; i < SC_NUM_PHASES * 2; i++) {
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for (j = 0; j < SC_V_NUM_TAPS; j++)
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*coeff_v++ = *cp++;
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/*
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* for the vertical scaler, we copy the first 5 coefficients and
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* skip the last 3 slots to move to the next row to hold
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* coefficients for the next phase
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*/
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coeff_v += SC_NUM_TAPS_MEM_ALIGN - SC_V_NUM_TAPS;
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}
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sc->vs_index = idx;
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sc->load_coeff_v = true;
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}
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void sc_config_scaler(struct sc_data *sc, u32 *sc_reg0, u32 *sc_reg8,
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u32 *sc_reg17, unsigned int src_w, unsigned int src_h,
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unsigned int dst_w, unsigned int dst_h)
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{
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struct device *dev = &sc->pdev->dev;
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u32 val;
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int dcm_x, dcm_shift;
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bool use_rav;
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unsigned long lltmp;
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u32 lin_acc_inc, lin_acc_inc_u;
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u32 col_acc_offset;
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u16 factor = 0;
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int row_acc_init_rav = 0, row_acc_init_rav_b = 0;
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u32 row_acc_inc = 0, row_acc_offset = 0, row_acc_offset_b = 0;
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/*
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* location of SC register in payload memory with respect to the first
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* register in the mmr address data block
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*/
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u32 *sc_reg9 = sc_reg8 + 1;
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u32 *sc_reg12 = sc_reg8 + 4;
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u32 *sc_reg13 = sc_reg8 + 5;
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u32 *sc_reg24 = sc_reg17 + 7;
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val = sc_reg0[0];
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/* clear all the features(they may get enabled elsewhere later) */
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val &= ~(CFG_SELFGEN_FID | CFG_TRIM | CFG_ENABLE_SIN2_VER_INTP |
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CFG_INTERLACE_I | CFG_DCM_4X | CFG_DCM_2X | CFG_AUTO_HS |
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CFG_ENABLE_EV | CFG_USE_RAV | CFG_INVT_FID | CFG_SC_BYPASS |
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CFG_INTERLACE_O | CFG_Y_PK_EN | CFG_HP_BYPASS | CFG_LINEAR);
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if (src_w == dst_w && src_h == dst_h) {
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val |= CFG_SC_BYPASS;
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sc_reg0[0] = val;
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return;
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}
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/* we only support linear scaling for now */
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val |= CFG_LINEAR;
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/* configure horizontal scaler */
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/* enable 2X or 4X decimation */
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dcm_x = src_w / dst_w;
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if (dcm_x > 4) {
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val |= CFG_DCM_4X;
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dcm_shift = 2;
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} else if (dcm_x > 2) {
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val |= CFG_DCM_2X;
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dcm_shift = 1;
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} else {
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dcm_shift = 0;
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}
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lltmp = dst_w - 1;
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lin_acc_inc = div64_u64(((u64)(src_w >> dcm_shift) - 1) << 24, lltmp);
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lin_acc_inc_u = 0;
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col_acc_offset = 0;
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dev_dbg(dev, "hs config: src_w = %d, dst_w = %d, decimation = %s, lin_acc_inc = %08x\n",
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src_w, dst_w, dcm_shift == 2 ? "4x" :
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(dcm_shift == 1 ? "2x" : "none"), lin_acc_inc);
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/* configure vertical scaler */
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/* use RAV for vertical scaler if vertical downscaling is > 4x */
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if (dst_h < (src_h >> 2)) {
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use_rav = true;
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val |= CFG_USE_RAV;
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} else {
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use_rav = false;
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}
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if (use_rav) {
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/* use RAV */
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factor = (u16) ((dst_h << 10) / src_h);
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row_acc_init_rav = factor + ((1 + factor) >> 1);
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if (row_acc_init_rav >= 1024)
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row_acc_init_rav -= 1024;
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row_acc_init_rav_b = row_acc_init_rav +
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(1 + (row_acc_init_rav >> 1)) -
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(1024 >> 1);
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if (row_acc_init_rav_b < 0) {
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row_acc_init_rav_b += row_acc_init_rav;
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row_acc_init_rav *= 2;
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}
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dev_dbg(dev, "vs config(RAV): src_h = %d, dst_h = %d, factor = %d, acc_init = %08x, acc_init_b = %08x\n",
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src_h, dst_h, factor, row_acc_init_rav,
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row_acc_init_rav_b);
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} else {
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/* use polyphase */
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row_acc_inc = ((src_h - 1) << 16) / (dst_h - 1);
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row_acc_offset = 0;
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row_acc_offset_b = 0;
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dev_dbg(dev, "vs config(POLY): src_h = %d, dst_h = %d,row_acc_inc = %08x\n",
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src_h, dst_h, row_acc_inc);
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}
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sc_reg0[0] = val;
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sc_reg0[1] = row_acc_inc;
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sc_reg0[2] = row_acc_offset;
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sc_reg0[3] = row_acc_offset_b;
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sc_reg0[4] = ((lin_acc_inc_u & CFG_LIN_ACC_INC_U_MASK) <<
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CFG_LIN_ACC_INC_U_SHIFT) | (dst_w << CFG_TAR_W_SHIFT) |
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(dst_h << CFG_TAR_H_SHIFT);
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sc_reg0[5] = (src_w << CFG_SRC_W_SHIFT) | (src_h << CFG_SRC_H_SHIFT);
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sc_reg0[6] = (row_acc_init_rav_b << CFG_ROW_ACC_INIT_RAV_B_SHIFT) |
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(row_acc_init_rav << CFG_ROW_ACC_INIT_RAV_SHIFT);
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*sc_reg9 = lin_acc_inc;
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*sc_reg12 = col_acc_offset << CFG_COL_ACC_OFFSET_SHIFT;
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*sc_reg13 = factor;
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*sc_reg24 = (src_w << CFG_ORG_W_SHIFT) | (src_h << CFG_ORG_H_SHIFT);
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}
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struct sc_data *sc_create(struct platform_device *pdev)
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{
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struct sc_data *sc;
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dev_dbg(&pdev->dev, "sc_create\n");
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sc = devm_kzalloc(&pdev->dev, sizeof(*sc), GFP_KERNEL);
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if (!sc) {
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dev_err(&pdev->dev, "couldn't alloc sc_data\n");
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return ERR_PTR(-ENOMEM);
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}
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sc->pdev = pdev;
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sc->res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sc");
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if (!sc->res) {
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dev_err(&pdev->dev, "missing platform resources data\n");
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return ERR_PTR(-ENODEV);
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}
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sc->base = devm_ioremap_resource(&pdev->dev, sc->res);
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if (IS_ERR(sc->base)) {
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dev_err(&pdev->dev, "failed to ioremap\n");
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return sc->base;
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}
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return sc;
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}
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