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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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277
drivers/media/tuners/Kconfig Normal file
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# Analog TV tuners, auto-loaded via tuner.ko
config MEDIA_TUNER
tristate
depends on (MEDIA_ANALOG_TV_SUPPORT || MEDIA_DIGITAL_TV_SUPPORT || MEDIA_RADIO_SUPPORT || MEDIA_SDR_SUPPORT) && I2C
default y
select MEDIA_TUNER_XC2028 if MEDIA_SUBDRV_AUTOSELECT
select MEDIA_TUNER_XC5000 if MEDIA_SUBDRV_AUTOSELECT
select MEDIA_TUNER_XC4000 if MEDIA_SUBDRV_AUTOSELECT
select MEDIA_TUNER_MT20XX if MEDIA_SUBDRV_AUTOSELECT
select MEDIA_TUNER_TDA8290 if MEDIA_SUBDRV_AUTOSELECT
select MEDIA_TUNER_TEA5761 if MEDIA_SUBDRV_AUTOSELECT && MEDIA_RADIO_SUPPORT
select MEDIA_TUNER_TEA5767 if MEDIA_SUBDRV_AUTOSELECT && MEDIA_RADIO_SUPPORT
select MEDIA_TUNER_SIMPLE if MEDIA_SUBDRV_AUTOSELECT
select MEDIA_TUNER_TDA9887 if MEDIA_SUBDRV_AUTOSELECT
select MEDIA_TUNER_MC44S803 if MEDIA_SUBDRV_AUTOSELECT
menu "Customize TV tuners"
visible if !MEDIA_SUBDRV_AUTOSELECT
depends on MEDIA_ANALOG_TV_SUPPORT || MEDIA_DIGITAL_TV_SUPPORT || MEDIA_RADIO_SUPPORT || MEDIA_SDR_SUPPORT
config MEDIA_TUNER_SIMPLE
tristate "Simple tuner support"
depends on MEDIA_SUPPORT && I2C
select MEDIA_TUNER_TDA9887
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Say Y here to include support for various simple tuners.
config MEDIA_TUNER_TDA8290
tristate "TDA 8290/8295 + 8275(a)/18271 tuner combo"
depends on MEDIA_SUPPORT && I2C
select MEDIA_TUNER_TDA827X
select MEDIA_TUNER_TDA18271
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Say Y here to include support for Philips TDA8290+8275(a) tuner.
config MEDIA_TUNER_TDA827X
tristate "Philips TDA827X silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
A DVB-T silicon tuner module. Say Y when you want to support this tuner.
config MEDIA_TUNER_TDA18271
tristate "NXP TDA18271 silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
A silicon tuner module. Say Y when you want to support this tuner.
config MEDIA_TUNER_TDA9887
tristate "TDA 9885/6/7 analog IF demodulator"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Say Y here to include support for Philips TDA9885/6/7
analog IF demodulator.
config MEDIA_TUNER_TEA5761
tristate "TEA 5761 radio tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Say Y here to include support for the Philips TEA5761 radio tuner.
config MEDIA_TUNER_TEA5767
tristate "TEA 5767 radio tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Say Y here to include support for the Philips TEA5767 radio tuner.
config MEDIA_TUNER_MSI001
tristate "Mirics MSi001"
depends on MEDIA_SUPPORT && SPI && VIDEO_V4L2
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Mirics MSi001 silicon tuner driver.
config MEDIA_TUNER_MT20XX
tristate "Microtune 2032 / 2050 tuners"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Say Y here to include support for the MT2032 / MT2050 tuner.
config MEDIA_TUNER_MT2060
tristate "Microtune MT2060 silicon IF tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
A driver for the silicon IF tuner MT2060 from Microtune.
config MEDIA_TUNER_MT2063
tristate "Microtune MT2063 silicon IF tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
A driver for the silicon IF tuner MT2063 from Microtune.
config MEDIA_TUNER_MT2266
tristate "Microtune MT2266 silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
A driver for the silicon baseband tuner MT2266 from Microtune.
config MEDIA_TUNER_MT2131
tristate "Microtune MT2131 silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
A driver for the silicon baseband tuner MT2131 from Microtune.
config MEDIA_TUNER_QT1010
tristate "Quantek QT1010 silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
A driver for the silicon tuner QT1010 from Quantek.
config MEDIA_TUNER_XC2028
tristate "XCeive xc2028/xc3028 tuners"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Say Y here to include support for the xc2028/xc3028 tuners.
config MEDIA_TUNER_XC5000
tristate "Xceive XC5000 silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
A driver for the silicon tuner XC5000 from Xceive.
This device is only used inside a SiP called together with a
demodulator for now.
config MEDIA_TUNER_XC4000
tristate "Xceive XC4000 silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
A driver for the silicon tuner XC4000 from Xceive.
This device is only used inside a SiP called together with a
demodulator for now.
config MEDIA_TUNER_MXL5005S
tristate "MaxLinear MSL5005S silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
A driver for the silicon tuner MXL5005S from MaxLinear.
config MEDIA_TUNER_MXL5007T
tristate "MaxLinear MxL5007T silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
A driver for the silicon tuner MxL5007T from MaxLinear.
config MEDIA_TUNER_MC44S803
tristate "Freescale MC44S803 Low Power CMOS Broadband tuners"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Say Y here to support the Freescale MC44S803 based tuners
config MEDIA_TUNER_MAX2165
tristate "Maxim MAX2165 silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
A driver for the silicon tuner MAX2165 from Maxim.
config MEDIA_TUNER_TDA18218
tristate "NXP TDA18218 silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
NXP TDA18218 silicon tuner driver.
config MEDIA_TUNER_FC0011
tristate "Fitipower FC0011 silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Fitipower FC0011 silicon tuner driver.
config MEDIA_TUNER_FC0012
tristate "Fitipower FC0012 silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Fitipower FC0012 silicon tuner driver.
config MEDIA_TUNER_FC0013
tristate "Fitipower FC0013 silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Fitipower FC0013 silicon tuner driver.
config MEDIA_TUNER_TDA18212
tristate "NXP TDA18212 silicon tuner"
depends on MEDIA_SUPPORT && I2C
select REGMAP_I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
NXP TDA18212 silicon tuner driver.
config MEDIA_TUNER_E4000
tristate "Elonics E4000 silicon tuner"
depends on MEDIA_SUPPORT && I2C
select REGMAP_I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Elonics E4000 silicon tuner driver.
config MEDIA_TUNER_FC2580
tristate "FCI FC2580 silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
FCI FC2580 silicon tuner driver.
config MEDIA_TUNER_M88TS2022
tristate "Montage M88TS2022 silicon tuner"
depends on MEDIA_SUPPORT && I2C
select REGMAP_I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Montage M88TS2022 silicon tuner driver.
config MEDIA_TUNER_TUA9001
tristate "Infineon TUA 9001 silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Infineon TUA 9001 silicon tuner driver.
config MEDIA_TUNER_SI2157
tristate "Silicon Labs Si2157 silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Silicon Labs Si2157 silicon tuner driver.
config MEDIA_TUNER_IT913X
tristate "ITE Tech IT913x silicon tuner"
depends on MEDIA_SUPPORT && I2C
select REGMAP_I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
ITE Tech IT913x silicon tuner driver.
config MEDIA_TUNER_R820T
tristate "Rafael Micro R820T silicon tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Rafael Micro R820T silicon tuner driver.
config MEDIA_TUNER_MXL301RF
tristate "MaxLinear MxL301RF tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
MaxLinear MxL301RF OFDM tuner driver.
config MEDIA_TUNER_QM1D1C0042
tristate "Sharp QM1D1C0042 tuner"
depends on MEDIA_SUPPORT && I2C
default m if !MEDIA_SUBDRV_AUTOSELECT
help
Sharp QM1D1C0042 trellis coded 8PSK tuner driver.
endmenu

46
drivers/media/tuners/Makefile Normal file
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#
# Makefile for common V4L/DVB tuners
#
tda18271-objs := tda18271-maps.o tda18271-common.o tda18271-fe.o
obj-$(CONFIG_MEDIA_TUNER_XC2028) += tuner-xc2028.o
obj-$(CONFIG_MEDIA_TUNER_SIMPLE) += tuner-simple.o
# tuner-types will be merged into tuner-simple, in the future
obj-$(CONFIG_MEDIA_TUNER_SIMPLE) += tuner-types.o
obj-$(CONFIG_MEDIA_TUNER_MT20XX) += mt20xx.o
obj-$(CONFIG_MEDIA_TUNER_TDA8290) += tda8290.o
obj-$(CONFIG_MEDIA_TUNER_TEA5767) += tea5767.o
obj-$(CONFIG_MEDIA_TUNER_TEA5761) += tea5761.o
obj-$(CONFIG_MEDIA_TUNER_TDA9887) += tda9887.o
obj-$(CONFIG_MEDIA_TUNER_TDA827X) += tda827x.o
obj-$(CONFIG_MEDIA_TUNER_TDA18271) += tda18271.o
obj-$(CONFIG_MEDIA_TUNER_XC5000) += xc5000.o
obj-$(CONFIG_MEDIA_TUNER_XC4000) += xc4000.o
obj-$(CONFIG_MEDIA_TUNER_MSI001) += msi001.o
obj-$(CONFIG_MEDIA_TUNER_MT2060) += mt2060.o
obj-$(CONFIG_MEDIA_TUNER_MT2063) += mt2063.o
obj-$(CONFIG_MEDIA_TUNER_MT2266) += mt2266.o
obj-$(CONFIG_MEDIA_TUNER_QT1010) += qt1010.o
obj-$(CONFIG_MEDIA_TUNER_MT2131) += mt2131.o
obj-$(CONFIG_MEDIA_TUNER_MXL5005S) += mxl5005s.o
obj-$(CONFIG_MEDIA_TUNER_MXL5007T) += mxl5007t.o
obj-$(CONFIG_MEDIA_TUNER_MC44S803) += mc44s803.o
obj-$(CONFIG_MEDIA_TUNER_MAX2165) += max2165.o
obj-$(CONFIG_MEDIA_TUNER_TDA18218) += tda18218.o
obj-$(CONFIG_MEDIA_TUNER_TDA18212) += tda18212.o
obj-$(CONFIG_MEDIA_TUNER_E4000) += e4000.o
obj-$(CONFIG_MEDIA_TUNER_FC2580) += fc2580.o
obj-$(CONFIG_MEDIA_TUNER_TUA9001) += tua9001.o
obj-$(CONFIG_MEDIA_TUNER_SI2157) += si2157.o
obj-$(CONFIG_MEDIA_TUNER_M88TS2022) += m88ts2022.o
obj-$(CONFIG_MEDIA_TUNER_FC0011) += fc0011.o
obj-$(CONFIG_MEDIA_TUNER_FC0012) += fc0012.o
obj-$(CONFIG_MEDIA_TUNER_FC0013) += fc0013.o
obj-$(CONFIG_MEDIA_TUNER_IT913X) += it913x.o
obj-$(CONFIG_MEDIA_TUNER_R820T) += r820t.o
obj-$(CONFIG_MEDIA_TUNER_MXL301RF) += mxl301rf.o
obj-$(CONFIG_MEDIA_TUNER_QM1D1C0042) += qm1d1c0042.o
ccflags-y += -I$(srctree)/drivers/media/dvb-core
ccflags-y += -I$(srctree)/drivers/media/dvb-frontends

614
drivers/media/tuners/e4000.c Normal file
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/*
* Elonics E4000 silicon tuner driver
*
* Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include "e4000_priv.h"
#include <linux/math64.h>
static int e4000_init(struct dvb_frontend *fe)
{
struct e4000 *s = fe->tuner_priv;
int ret;
dev_dbg(&s->client->dev, "\n");
/* dummy I2C to ensure I2C wakes up */
ret = regmap_write(s->regmap, 0x02, 0x40);
/* reset */
ret = regmap_write(s->regmap, 0x00, 0x01);
if (ret)
goto err;
/* disable output clock */
ret = regmap_write(s->regmap, 0x06, 0x00);
if (ret)
goto err;
ret = regmap_write(s->regmap, 0x7a, 0x96);
if (ret)
goto err;
/* configure gains */
ret = regmap_bulk_write(s->regmap, 0x7e, "\x01\xfe", 2);
if (ret)
goto err;
ret = regmap_write(s->regmap, 0x82, 0x00);
if (ret)
goto err;
ret = regmap_write(s->regmap, 0x24, 0x05);
if (ret)
goto err;
ret = regmap_bulk_write(s->regmap, 0x87, "\x20\x01", 2);
if (ret)
goto err;
ret = regmap_bulk_write(s->regmap, 0x9f, "\x7f\x07", 2);
if (ret)
goto err;
/* DC offset control */
ret = regmap_write(s->regmap, 0x2d, 0x1f);
if (ret)
goto err;
ret = regmap_bulk_write(s->regmap, 0x70, "\x01\x01", 2);
if (ret)
goto err;
/* gain control */
ret = regmap_write(s->regmap, 0x1a, 0x17);
if (ret)
goto err;
ret = regmap_write(s->regmap, 0x1f, 0x1a);
if (ret)
goto err;
s->active = true;
err:
if (ret)
dev_dbg(&s->client->dev, "failed=%d\n", ret);
return ret;
}
static int e4000_sleep(struct dvb_frontend *fe)
{
struct e4000 *s = fe->tuner_priv;
int ret;
dev_dbg(&s->client->dev, "\n");
s->active = false;
ret = regmap_write(s->regmap, 0x00, 0x00);
if (ret)
goto err;
err:
if (ret)
dev_dbg(&s->client->dev, "failed=%d\n", ret);
return ret;
}
static int e4000_set_params(struct dvb_frontend *fe)
{
struct e4000 *s = fe->tuner_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i, sigma_delta;
unsigned int pll_n, pll_f;
u64 f_vco;
u8 buf[5], i_data[4], q_data[4];
dev_dbg(&s->client->dev,
"delivery_system=%d frequency=%u bandwidth_hz=%u\n",
c->delivery_system, c->frequency, c->bandwidth_hz);
/* gain control manual */
ret = regmap_write(s->regmap, 0x1a, 0x00);
if (ret)
goto err;
/* PLL */
for (i = 0; i < ARRAY_SIZE(e4000_pll_lut); i++) {
if (c->frequency <= e4000_pll_lut[i].freq)
break;
}
if (i == ARRAY_SIZE(e4000_pll_lut)) {
ret = -EINVAL;
goto err;
}
f_vco = 1ull * c->frequency * e4000_pll_lut[i].mul;
pll_n = div_u64_rem(f_vco, s->clock, &pll_f);
sigma_delta = div_u64(0x10000ULL * pll_f, s->clock);
buf[0] = pll_n;
buf[1] = (sigma_delta >> 0) & 0xff;
buf[2] = (sigma_delta >> 8) & 0xff;
buf[3] = 0x00;
buf[4] = e4000_pll_lut[i].div;
dev_dbg(&s->client->dev, "f_vco=%llu pll div=%d sigma_delta=%04x\n",
f_vco, buf[0], sigma_delta);
ret = regmap_bulk_write(s->regmap, 0x09, buf, 5);
if (ret)
goto err;
/* LNA filter (RF filter) */
for (i = 0; i < ARRAY_SIZE(e400_lna_filter_lut); i++) {
if (c->frequency <= e400_lna_filter_lut[i].freq)
break;
}
if (i == ARRAY_SIZE(e400_lna_filter_lut)) {
ret = -EINVAL;
goto err;
}
ret = regmap_write(s->regmap, 0x10, e400_lna_filter_lut[i].val);
if (ret)
goto err;
/* IF filters */
for (i = 0; i < ARRAY_SIZE(e4000_if_filter_lut); i++) {
if (c->bandwidth_hz <= e4000_if_filter_lut[i].freq)
break;
}
if (i == ARRAY_SIZE(e4000_if_filter_lut)) {
ret = -EINVAL;
goto err;
}
buf[0] = e4000_if_filter_lut[i].reg11_val;
buf[1] = e4000_if_filter_lut[i].reg12_val;
ret = regmap_bulk_write(s->regmap, 0x11, buf, 2);
if (ret)
goto err;
/* frequency band */
for (i = 0; i < ARRAY_SIZE(e4000_band_lut); i++) {
if (c->frequency <= e4000_band_lut[i].freq)
break;
}
if (i == ARRAY_SIZE(e4000_band_lut)) {
ret = -EINVAL;
goto err;
}
ret = regmap_write(s->regmap, 0x07, e4000_band_lut[i].reg07_val);
if (ret)
goto err;
ret = regmap_write(s->regmap, 0x78, e4000_band_lut[i].reg78_val);
if (ret)
goto err;
/* DC offset */
for (i = 0; i < 4; i++) {
if (i == 0)
ret = regmap_bulk_write(s->regmap, 0x15, "\x00\x7e\x24", 3);
else if (i == 1)
ret = regmap_bulk_write(s->regmap, 0x15, "\x00\x7f", 2);
else if (i == 2)
ret = regmap_bulk_write(s->regmap, 0x15, "\x01", 1);
else
ret = regmap_bulk_write(s->regmap, 0x16, "\x7e", 1);
if (ret)
goto err;
ret = regmap_write(s->regmap, 0x29, 0x01);
if (ret)
goto err;
ret = regmap_bulk_read(s->regmap, 0x2a, buf, 3);
if (ret)
goto err;
i_data[i] = (((buf[2] >> 0) & 0x3) << 6) | (buf[0] & 0x3f);
q_data[i] = (((buf[2] >> 4) & 0x3) << 6) | (buf[1] & 0x3f);
}
swap(q_data[2], q_data[3]);
swap(i_data[2], i_data[3]);
ret = regmap_bulk_write(s->regmap, 0x50, q_data, 4);
if (ret)
goto err;
ret = regmap_bulk_write(s->regmap, 0x60, i_data, 4);
if (ret)
goto err;
/* gain control auto */
ret = regmap_write(s->regmap, 0x1a, 0x17);
if (ret)
goto err;
err:
if (ret)
dev_dbg(&s->client->dev, "failed=%d\n", ret);
return ret;
}
static int e4000_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct e4000 *s = fe->tuner_priv;
dev_dbg(&s->client->dev, "\n");
*frequency = 0; /* Zero-IF */
return 0;
}
#if IS_ENABLED(CONFIG_VIDEO_V4L2)
static int e4000_set_lna_gain(struct dvb_frontend *fe)
{
struct e4000 *s = fe->tuner_priv;
int ret;
u8 u8tmp;
dev_dbg(&s->client->dev, "lna auto=%d->%d val=%d->%d\n",
s->lna_gain_auto->cur.val, s->lna_gain_auto->val,
s->lna_gain->cur.val, s->lna_gain->val);
if (s->lna_gain_auto->val && s->if_gain_auto->cur.val)
u8tmp = 0x17;
else if (s->lna_gain_auto->val)
u8tmp = 0x19;
else if (s->if_gain_auto->cur.val)
u8tmp = 0x16;
else
u8tmp = 0x10;
ret = regmap_write(s->regmap, 0x1a, u8tmp);
if (ret)
goto err;
if (s->lna_gain_auto->val == false) {
ret = regmap_write(s->regmap, 0x14, s->lna_gain->val);
if (ret)
goto err;
}
err:
if (ret)
dev_dbg(&s->client->dev, "failed=%d\n", ret);
return ret;
}
static int e4000_set_mixer_gain(struct dvb_frontend *fe)
{
struct e4000 *s = fe->tuner_priv;
int ret;
u8 u8tmp;
dev_dbg(&s->client->dev, "mixer auto=%d->%d val=%d->%d\n",
s->mixer_gain_auto->cur.val, s->mixer_gain_auto->val,
s->mixer_gain->cur.val, s->mixer_gain->val);
if (s->mixer_gain_auto->val)
u8tmp = 0x15;
else
u8tmp = 0x14;
ret = regmap_write(s->regmap, 0x20, u8tmp);
if (ret)
goto err;
if (s->mixer_gain_auto->val == false) {
ret = regmap_write(s->regmap, 0x15, s->mixer_gain->val);
if (ret)
goto err;
}
err:
if (ret)
dev_dbg(&s->client->dev, "failed=%d\n", ret);
return ret;
}
static int e4000_set_if_gain(struct dvb_frontend *fe)
{
struct e4000 *s = fe->tuner_priv;
int ret;
u8 buf[2];
u8 u8tmp;
dev_dbg(&s->client->dev, "if auto=%d->%d val=%d->%d\n",
s->if_gain_auto->cur.val, s->if_gain_auto->val,
s->if_gain->cur.val, s->if_gain->val);
if (s->if_gain_auto->val && s->lna_gain_auto->cur.val)
u8tmp = 0x17;
else if (s->lna_gain_auto->cur.val)
u8tmp = 0x19;
else if (s->if_gain_auto->val)
u8tmp = 0x16;
else
u8tmp = 0x10;
ret = regmap_write(s->regmap, 0x1a, u8tmp);
if (ret)
goto err;
if (s->if_gain_auto->val == false) {
buf[0] = e4000_if_gain_lut[s->if_gain->val].reg16_val;
buf[1] = e4000_if_gain_lut[s->if_gain->val].reg17_val;
ret = regmap_bulk_write(s->regmap, 0x16, buf, 2);
if (ret)
goto err;
}
err:
if (ret)
dev_dbg(&s->client->dev, "failed=%d\n", ret);
return ret;
}
static int e4000_pll_lock(struct dvb_frontend *fe)
{
struct e4000 *s = fe->tuner_priv;
int ret;
unsigned int utmp;
ret = regmap_read(s->regmap, 0x07, &utmp);
if (ret)
goto err;
s->pll_lock->val = (utmp & 0x01);
err:
if (ret)
dev_dbg(&s->client->dev, "failed=%d\n", ret);
return ret;
}
static int e4000_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
{
struct e4000 *s = container_of(ctrl->handler, struct e4000, hdl);
int ret;
if (!s->active)
return 0;
switch (ctrl->id) {
case V4L2_CID_RF_TUNER_PLL_LOCK:
ret = e4000_pll_lock(s->fe);
break;
default:
dev_dbg(&s->client->dev, "unknown ctrl: id=%d name=%s\n",
ctrl->id, ctrl->name);
ret = -EINVAL;
}
return ret;
}
static int e4000_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct e4000 *s = container_of(ctrl->handler, struct e4000, hdl);
struct dvb_frontend *fe = s->fe;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
if (!s->active)
return 0;
switch (ctrl->id) {
case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO:
case V4L2_CID_RF_TUNER_BANDWIDTH:
c->bandwidth_hz = s->bandwidth->val;
ret = e4000_set_params(s->fe);
break;
case V4L2_CID_RF_TUNER_LNA_GAIN_AUTO:
case V4L2_CID_RF_TUNER_LNA_GAIN:
ret = e4000_set_lna_gain(s->fe);
break;
case V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO:
case V4L2_CID_RF_TUNER_MIXER_GAIN:
ret = e4000_set_mixer_gain(s->fe);
break;
case V4L2_CID_RF_TUNER_IF_GAIN_AUTO:
case V4L2_CID_RF_TUNER_IF_GAIN:
ret = e4000_set_if_gain(s->fe);
break;
default:
dev_dbg(&s->client->dev, "unknown ctrl: id=%d name=%s\n",
ctrl->id, ctrl->name);
ret = -EINVAL;
}
return ret;
}
static const struct v4l2_ctrl_ops e4000_ctrl_ops = {
.g_volatile_ctrl = e4000_g_volatile_ctrl,
.s_ctrl = e4000_s_ctrl,
};
#endif
static const struct dvb_tuner_ops e4000_tuner_ops = {
.info = {
.name = "Elonics E4000",
.frequency_min = 174000000,
.frequency_max = 862000000,
},
.init = e4000_init,
.sleep = e4000_sleep,
.set_params = e4000_set_params,
.get_if_frequency = e4000_get_if_frequency,
};
/*
* Use V4L2 subdev to carry V4L2 control handler, even we don't implement
* subdev itself, just to avoid reinventing the wheel.
*/
static int e4000_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct e4000_config *cfg = client->dev.platform_data;
struct dvb_frontend *fe = cfg->fe;
struct e4000 *s;
int ret;
unsigned int utmp;
static const struct regmap_config regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0xff,
};
s = kzalloc(sizeof(struct e4000), GFP_KERNEL);
if (!s) {
ret = -ENOMEM;
dev_err(&client->dev, "kzalloc() failed\n");
goto err;
}
s->clock = cfg->clock;
s->client = client;
s->fe = cfg->fe;
s->regmap = devm_regmap_init_i2c(client, &regmap_config);
if (IS_ERR(s->regmap)) {
ret = PTR_ERR(s->regmap);
goto err;
}
/* check if the tuner is there */
ret = regmap_read(s->regmap, 0x02, &utmp);
if (ret)
goto err;
dev_dbg(&s->client->dev, "chip id=%02x\n", utmp);
if (utmp != 0x40) {
ret = -ENODEV;
goto err;
}
/* put sleep as chip seems to be in normal mode by default */
ret = regmap_write(s->regmap, 0x00, 0x00);
if (ret)
goto err;
#if IS_ENABLED(CONFIG_VIDEO_V4L2)
/* Register controls */
v4l2_ctrl_handler_init(&s->hdl, 9);
s->bandwidth_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops,
V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1);
s->bandwidth = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops,
V4L2_CID_RF_TUNER_BANDWIDTH, 4300000, 11000000, 100000, 4300000);
v4l2_ctrl_auto_cluster(2, &s->bandwidth_auto, 0, false);
s->lna_gain_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops,
V4L2_CID_RF_TUNER_LNA_GAIN_AUTO, 0, 1, 1, 1);
s->lna_gain = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops,
V4L2_CID_RF_TUNER_LNA_GAIN, 0, 15, 1, 10);
v4l2_ctrl_auto_cluster(2, &s->lna_gain_auto, 0, false);
s->mixer_gain_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops,
V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO, 0, 1, 1, 1);
s->mixer_gain = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops,
V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1);
v4l2_ctrl_auto_cluster(2, &s->mixer_gain_auto, 0, false);
s->if_gain_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops,
V4L2_CID_RF_TUNER_IF_GAIN_AUTO, 0, 1, 1, 1);
s->if_gain = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops,
V4L2_CID_RF_TUNER_IF_GAIN, 0, 54, 1, 0);
v4l2_ctrl_auto_cluster(2, &s->if_gain_auto, 0, false);
s->pll_lock = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops,
V4L2_CID_RF_TUNER_PLL_LOCK, 0, 1, 1, 0);
if (s->hdl.error) {
ret = s->hdl.error;
dev_err(&s->client->dev, "Could not initialize controls\n");
v4l2_ctrl_handler_free(&s->hdl);
goto err;
}
s->sd.ctrl_handler = &s->hdl;
#endif
dev_info(&s->client->dev, "Elonics E4000 successfully identified\n");
fe->tuner_priv = s;
memcpy(&fe->ops.tuner_ops, &e4000_tuner_ops,
sizeof(struct dvb_tuner_ops));
v4l2_set_subdevdata(&s->sd, client);
i2c_set_clientdata(client, &s->sd);
return 0;
err:
if (ret) {
dev_dbg(&client->dev, "failed=%d\n", ret);
kfree(s);
}
return ret;
}
static int e4000_remove(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct e4000 *s = container_of(sd, struct e4000, sd);
struct dvb_frontend *fe = s->fe;
dev_dbg(&client->dev, "\n");
#if IS_ENABLED(CONFIG_VIDEO_V4L2)
v4l2_ctrl_handler_free(&s->hdl);
#endif
memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops));
fe->tuner_priv = NULL;
kfree(s);
return 0;
}
static const struct i2c_device_id e4000_id[] = {
{"e4000", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, e4000_id);
static struct i2c_driver e4000_driver = {
.driver = {
.owner = THIS_MODULE,
.name = "e4000",
},
.probe = e4000_probe,
.remove = e4000_remove,
.id_table = e4000_id,
};
module_i2c_driver(e4000_driver);
MODULE_DESCRIPTION("Elonics E4000 silicon tuner driver");
MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
MODULE_LICENSE("GPL");

43
drivers/media/tuners/e4000.h Normal file
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/*
* Elonics E4000 silicon tuner driver
*
* Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef E4000_H
#define E4000_H
#include <linux/kconfig.h>
#include "dvb_frontend.h"
/*
* I2C address
* 0x64, 0x65, 0x66, 0x67
*/
struct e4000_config {
/*
* frontend
*/
struct dvb_frontend *fe;
/*
* clock
*/
u32 clock;
};
#endif

229
drivers/media/tuners/e4000_priv.h Normal file
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/*
* Elonics E4000 silicon tuner driver
*
* Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef E4000_PRIV_H
#define E4000_PRIV_H
#include "e4000.h"
#include <media/v4l2-ctrls.h>
#include <media/v4l2-subdev.h>
#include <linux/regmap.h>
struct e4000 {
struct i2c_client *client;
struct regmap *regmap;
u32 clock;
struct dvb_frontend *fe;
struct v4l2_subdev sd;
bool active;
/* Controls */
struct v4l2_ctrl_handler hdl;
struct v4l2_ctrl *bandwidth_auto;
struct v4l2_ctrl *bandwidth;
struct v4l2_ctrl *lna_gain_auto;
struct v4l2_ctrl *lna_gain;
struct v4l2_ctrl *mixer_gain_auto;
struct v4l2_ctrl *mixer_gain;
struct v4l2_ctrl *if_gain_auto;
struct v4l2_ctrl *if_gain;
struct v4l2_ctrl *pll_lock;
};
struct e4000_pll {
u32 freq;
u8 div;
u8 mul;
};
static const struct e4000_pll e4000_pll_lut[] = {
/* VCO min VCO max */
{ 72400000, 0x0f, 48 }, /* .......... 3475200000 */
{ 81200000, 0x0e, 40 }, /* 2896000000 3248000000 */
{ 108300000, 0x0d, 32 }, /* 2598400000 3465600000 */
{ 162500000, 0x0c, 24 }, /* 2599200000 3900000000 */
{ 216600000, 0x0b, 16 }, /* 2600000000 3465600000 */
{ 325000000, 0x0a, 12 }, /* 2599200000 3900000000 */
{ 350000000, 0x09, 8 }, /* 2600000000 2800000000 */
{ 432000000, 0x03, 8 }, /* 2800000000 3456000000 */
{ 667000000, 0x02, 6 }, /* 2592000000 4002000000 */
{ 1200000000, 0x01, 4 }, /* 2668000000 4800000000 */
{ 0xffffffff, 0x00, 2 }, /* 2400000000 .......... */
};
struct e4000_lna_filter {
u32 freq;
u8 val;
};
static const struct e4000_lna_filter e400_lna_filter_lut[] = {
{ 370000000, 0 },
{ 392500000, 1 },
{ 415000000, 2 },
{ 437500000, 3 },
{ 462500000, 4 },
{ 490000000, 5 },
{ 522500000, 6 },
{ 557500000, 7 },
{ 595000000, 8 },
{ 642500000, 9 },
{ 695000000, 10 },
{ 740000000, 11 },
{ 800000000, 12 },
{ 865000000, 13 },
{ 930000000, 14 },
{ 1000000000, 15 },
{ 1310000000, 0 },
{ 1340000000, 1 },
{ 1385000000, 2 },
{ 1427500000, 3 },
{ 1452500000, 4 },
{ 1475000000, 5 },
{ 1510000000, 6 },
{ 1545000000, 7 },
{ 1575000000, 8 },
{ 1615000000, 9 },
{ 1650000000, 10 },
{ 1670000000, 11 },
{ 1690000000, 12 },
{ 1710000000, 13 },
{ 1735000000, 14 },
{ 0xffffffff, 15 },
};
struct e4000_band {
u32 freq;
u8 reg07_val;
u8 reg78_val;
};
static const struct e4000_band e4000_band_lut[] = {
{ 140000000, 0x01, 0x03 },
{ 350000000, 0x03, 0x03 },
{ 1000000000, 0x05, 0x03 },
{ 0xffffffff, 0x07, 0x00 },
};
struct e4000_if_filter {
u32 freq;
u8 reg11_val;
u8 reg12_val;
};
static const struct e4000_if_filter e4000_if_filter_lut[] = {
{ 4300000, 0xfd, 0x1f },
{ 4400000, 0xfd, 0x1e },
{ 4480000, 0xfc, 0x1d },
{ 4560000, 0xfc, 0x1c },
{ 4600000, 0xfc, 0x1b },
{ 4800000, 0xfc, 0x1a },
{ 4900000, 0xfc, 0x19 },
{ 5000000, 0xfc, 0x18 },
{ 5100000, 0xfc, 0x17 },
{ 5200000, 0xfc, 0x16 },
{ 5400000, 0xfc, 0x15 },
{ 5500000, 0xfc, 0x14 },
{ 5600000, 0xfc, 0x13 },
{ 5800000, 0xfb, 0x12 },
{ 5900000, 0xfb, 0x11 },
{ 6000000, 0xfb, 0x10 },
{ 6200000, 0xfb, 0x0f },
{ 6400000, 0xfa, 0x0e },
{ 6600000, 0xfa, 0x0d },
{ 6800000, 0xf9, 0x0c },
{ 7200000, 0xf9, 0x0b },
{ 7400000, 0xf9, 0x0a },
{ 7600000, 0xf8, 0x09 },
{ 7800000, 0xf8, 0x08 },
{ 8200000, 0xf8, 0x07 },
{ 8600000, 0xf7, 0x06 },
{ 8800000, 0xf7, 0x05 },
{ 9200000, 0xf7, 0x04 },
{ 9600000, 0xf6, 0x03 },
{ 10000000, 0xf6, 0x02 },
{ 10600000, 0xf5, 0x01 },
{ 11000000, 0xf5, 0x00 },
{ 0xffffffff, 0x00, 0x20 },
};
struct e4000_if_gain {
u8 reg16_val;
u8 reg17_val;
};
static const struct e4000_if_gain e4000_if_gain_lut[] = {
{0x00, 0x00},
{0x20, 0x00},
{0x40, 0x00},
{0x02, 0x00},
{0x22, 0x00},
{0x42, 0x00},
{0x04, 0x00},
{0x24, 0x00},
{0x44, 0x00},
{0x01, 0x00},
{0x21, 0x00},
{0x41, 0x00},
{0x03, 0x00},
{0x23, 0x00},
{0x43, 0x00},
{0x05, 0x00},
{0x25, 0x00},
{0x45, 0x00},
{0x07, 0x00},
{0x27, 0x00},
{0x47, 0x00},
{0x0f, 0x00},
{0x2f, 0x00},
{0x4f, 0x00},
{0x17, 0x00},
{0x37, 0x00},
{0x57, 0x00},
{0x1f, 0x00},
{0x3f, 0x00},
{0x5f, 0x00},
{0x1f, 0x01},
{0x3f, 0x01},
{0x5f, 0x01},
{0x1f, 0x02},
{0x3f, 0x02},
{0x5f, 0x02},
{0x1f, 0x03},
{0x3f, 0x03},
{0x5f, 0x03},
{0x1f, 0x04},
{0x3f, 0x04},
{0x5f, 0x04},
{0x1f, 0x0c},
{0x3f, 0x0c},
{0x5f, 0x0c},
{0x1f, 0x14},
{0x3f, 0x14},
{0x5f, 0x14},
{0x1f, 0x1c},
{0x3f, 0x1c},
{0x5f, 0x1c},
{0x1f, 0x24},
{0x3f, 0x24},
{0x5f, 0x24},
{0x7f, 0x24},
};
#endif

523
drivers/media/tuners/fc0011.c Normal file
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/*
* Fitipower FC0011 tuner driver
*
* Copyright (C) 2012 Michael Buesch <m@bues.ch>
*
* Derived from FC0012 tuner driver:
* Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include "fc0011.h"
/* Tuner registers */
enum {
FC11_REG_0,
FC11_REG_FA, /* FA */
FC11_REG_FP, /* FP */
FC11_REG_XINHI, /* XIN high 8 bit */
FC11_REG_XINLO, /* XIN low 8 bit */
FC11_REG_VCO, /* VCO */
FC11_REG_VCOSEL, /* VCO select */
FC11_REG_7, /* Unknown tuner reg 7 */
FC11_REG_8, /* Unknown tuner reg 8 */
FC11_REG_9,
FC11_REG_10, /* Unknown tuner reg 10 */
FC11_REG_11, /* Unknown tuner reg 11 */
FC11_REG_12,
FC11_REG_RCCAL, /* RC calibrate */
FC11_REG_VCOCAL, /* VCO calibrate */
FC11_REG_15,
FC11_REG_16, /* Unknown tuner reg 16 */
FC11_REG_17,
FC11_NR_REGS, /* Number of registers */
};
enum FC11_REG_VCOSEL_bits {
FC11_VCOSEL_2 = 0x08, /* VCO select 2 */
FC11_VCOSEL_1 = 0x10, /* VCO select 1 */
FC11_VCOSEL_CLKOUT = 0x20, /* Fix clock out */
FC11_VCOSEL_BW7M = 0x40, /* 7MHz bw */
FC11_VCOSEL_BW6M = 0x80, /* 6MHz bw */
};
enum FC11_REG_RCCAL_bits {
FC11_RCCAL_FORCE = 0x10, /* force */
};
enum FC11_REG_VCOCAL_bits {
FC11_VCOCAL_RUN = 0, /* VCO calibration run */
FC11_VCOCAL_VALUEMASK = 0x3F, /* VCO calibration value mask */
FC11_VCOCAL_OK = 0x40, /* VCO calibration Ok */
FC11_VCOCAL_RESET = 0x80, /* VCO calibration reset */
};
struct fc0011_priv {
struct i2c_adapter *i2c;
u8 addr;
u32 frequency;
u32 bandwidth;
};
static int fc0011_writereg(struct fc0011_priv *priv, u8 reg, u8 val)
{
u8 buf[2] = { reg, val };
struct i2c_msg msg = { .addr = priv->addr,
.flags = 0, .buf = buf, .len = 2 };
if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
dev_err(&priv->i2c->dev,
"I2C write reg failed, reg: %02x, val: %02x\n",
reg, val);
return -EIO;
}
return 0;
}
static int fc0011_readreg(struct fc0011_priv *priv, u8 reg, u8 *val)
{
u8 dummy;
struct i2c_msg msg[2] = {
{ .addr = priv->addr,
.flags = 0, .buf = &reg, .len = 1 },
{ .addr = priv->addr,
.flags = I2C_M_RD, .buf = val ? : &dummy, .len = 1 },
};
if (i2c_transfer(priv->i2c, msg, 2) != 2) {
dev_err(&priv->i2c->dev,
"I2C read failed, reg: %02x\n", reg);
return -EIO;
}
return 0;
}
static int fc0011_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
return 0;
}
static int fc0011_init(struct dvb_frontend *fe)
{
struct fc0011_priv *priv = fe->tuner_priv;
int err;
if (WARN_ON(!fe->callback))
return -EINVAL;
err = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
FC0011_FE_CALLBACK_POWER, priv->addr);
if (err) {
dev_err(&priv->i2c->dev, "Power-on callback failed\n");
return err;
}
err = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
FC0011_FE_CALLBACK_RESET, priv->addr);
if (err) {
dev_err(&priv->i2c->dev, "Reset callback failed\n");
return err;
}
return 0;
}
/* Initiate VCO calibration */
static int fc0011_vcocal_trigger(struct fc0011_priv *priv)
{
int err;
err = fc0011_writereg(priv, FC11_REG_VCOCAL, FC11_VCOCAL_RESET);
if (err)
return err;
err = fc0011_writereg(priv, FC11_REG_VCOCAL, FC11_VCOCAL_RUN);
if (err)
return err;
return 0;
}
/* Read VCO calibration value */
static int fc0011_vcocal_read(struct fc0011_priv *priv, u8 *value)
{
int err;
err = fc0011_writereg(priv, FC11_REG_VCOCAL, FC11_VCOCAL_RUN);
if (err)
return err;
usleep_range(10000, 20000);
err = fc0011_readreg(priv, FC11_REG_VCOCAL, value);
if (err)
return err;
return 0;
}
static int fc0011_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct fc0011_priv *priv = fe->tuner_priv;
int err;
unsigned int i, vco_retries;
u32 freq = p->frequency / 1000;
u32 bandwidth = p->bandwidth_hz / 1000;
u32 fvco, xin, frac, xdiv, xdivr;
u8 fa, fp, vco_sel, vco_cal;
u8 regs[FC11_NR_REGS] = { };
regs[FC11_REG_7] = 0x0F;
regs[FC11_REG_8] = 0x3E;
regs[FC11_REG_10] = 0xB8;
regs[FC11_REG_11] = 0x80;
regs[FC11_REG_RCCAL] = 0x04;
err = fc0011_writereg(priv, FC11_REG_7, regs[FC11_REG_7]);
err |= fc0011_writereg(priv, FC11_REG_8, regs[FC11_REG_8]);
err |= fc0011_writereg(priv, FC11_REG_10, regs[FC11_REG_10]);
err |= fc0011_writereg(priv, FC11_REG_11, regs[FC11_REG_11]);
err |= fc0011_writereg(priv, FC11_REG_RCCAL, regs[FC11_REG_RCCAL]);
if (err)
return -EIO;
/* Set VCO freq and VCO div */
if (freq < 54000) {
fvco = freq * 64;
regs[FC11_REG_VCO] = 0x82;
} else if (freq < 108000) {
fvco = freq * 32;
regs[FC11_REG_VCO] = 0x42;
} else if (freq < 216000) {
fvco = freq * 16;
regs[FC11_REG_VCO] = 0x22;
} else if (freq < 432000) {
fvco = freq * 8;
regs[FC11_REG_VCO] = 0x12;
} else {
fvco = freq * 4;
regs[FC11_REG_VCO] = 0x0A;
}
/* Calc XIN. The PLL reference frequency is 18 MHz. */
xdiv = fvco / 18000;
WARN_ON(xdiv > 0xFF);
frac = fvco - xdiv * 18000;
frac = (frac << 15) / 18000;
if (frac >= 16384)
frac += 32786;
if (!frac)
xin = 0;
else
xin = clamp_t(u32, frac, 512, 65024);
regs[FC11_REG_XINHI] = xin >> 8;
regs[FC11_REG_XINLO] = xin;
/* Calc FP and FA */
xdivr = xdiv;
if (fvco - xdiv * 18000 >= 9000)
xdivr += 1; /* round */
fp = xdivr / 8;
fa = xdivr - fp * 8;
if (fa < 2) {
fp -= 1;
fa += 8;
}
if (fp > 0x1F) {
fp = 0x1F;
fa = 0xF;
}
if (fa >= fp) {
dev_warn(&priv->i2c->dev,
"fa %02X >= fp %02X, but trying to continue\n",
(unsigned int)(u8)fa, (unsigned int)(u8)fp);
}
regs[FC11_REG_FA] = fa;
regs[FC11_REG_FP] = fp;
/* Select bandwidth */
switch (bandwidth) {
case 8000:
break;
case 7000:
regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_BW7M;
break;
default:
dev_warn(&priv->i2c->dev, "Unsupported bandwidth %u kHz. "
"Using 6000 kHz.\n",
bandwidth);
bandwidth = 6000;
/* fallthrough */
case 6000:
regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_BW6M;
break;
}
/* Pre VCO select */
if (fvco < 2320000) {
vco_sel = 0;
regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
} else if (fvco < 3080000) {
vco_sel = 1;
regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_1;
} else {
vco_sel = 2;
regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_2;
}
/* Fix for low freqs */
if (freq < 45000) {
regs[FC11_REG_FA] = 0x6;
regs[FC11_REG_FP] = 0x11;
}
/* Clock out fix */
regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_CLKOUT;
/* Write the cached registers */
for (i = FC11_REG_FA; i <= FC11_REG_VCOSEL; i++) {
err = fc0011_writereg(priv, i, regs[i]);
if (err)
return err;
}
/* VCO calibration */
err = fc0011_vcocal_trigger(priv);
if (err)
return err;
err = fc0011_vcocal_read(priv, &vco_cal);
if (err)
return err;
vco_retries = 0;
while (!(vco_cal & FC11_VCOCAL_OK) && vco_retries < 3) {
/* Reset the tuner and try again */
err = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
FC0011_FE_CALLBACK_RESET, priv->addr);
if (err) {
dev_err(&priv->i2c->dev, "Failed to reset tuner\n");
return err;
}
/* Reinit tuner config */
err = 0;
for (i = FC11_REG_FA; i <= FC11_REG_VCOSEL; i++)
err |= fc0011_writereg(priv, i, regs[i]);
err |= fc0011_writereg(priv, FC11_REG_7, regs[FC11_REG_7]);
err |= fc0011_writereg(priv, FC11_REG_8, regs[FC11_REG_8]);
err |= fc0011_writereg(priv, FC11_REG_10, regs[FC11_REG_10]);
err |= fc0011_writereg(priv, FC11_REG_11, regs[FC11_REG_11]);
err |= fc0011_writereg(priv, FC11_REG_RCCAL, regs[FC11_REG_RCCAL]);
if (err)
return -EIO;
/* VCO calibration */
err = fc0011_vcocal_trigger(priv);
if (err)
return err;
err = fc0011_vcocal_read(priv, &vco_cal);
if (err)
return err;
vco_retries++;
}
if (!(vco_cal & FC11_VCOCAL_OK)) {
dev_err(&priv->i2c->dev,
"Failed to read VCO calibration value (got %02X)\n",
(unsigned int)vco_cal);
return -EIO;
}
vco_cal &= FC11_VCOCAL_VALUEMASK;
switch (vco_sel) {
default:
WARN_ON(1);
case 0:
if (vco_cal < 8) {
regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_1;
err = fc0011_writereg(priv, FC11_REG_VCOSEL,
regs[FC11_REG_VCOSEL]);
if (err)
return err;
err = fc0011_vcocal_trigger(priv);
if (err)
return err;
} else {
regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
err = fc0011_writereg(priv, FC11_REG_VCOSEL,
regs[FC11_REG_VCOSEL]);
if (err)
return err;
}
break;
case 1:
if (vco_cal < 5) {
regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_2;
err = fc0011_writereg(priv, FC11_REG_VCOSEL,
regs[FC11_REG_VCOSEL]);
if (err)
return err;
err = fc0011_vcocal_trigger(priv);
if (err)
return err;
} else if (vco_cal <= 48) {
regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_1;
err = fc0011_writereg(priv, FC11_REG_VCOSEL,
regs[FC11_REG_VCOSEL]);
if (err)
return err;
} else {
regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
err = fc0011_writereg(priv, FC11_REG_VCOSEL,
regs[FC11_REG_VCOSEL]);
if (err)
return err;
err = fc0011_vcocal_trigger(priv);
if (err)
return err;
}
break;
case 2:
if (vco_cal > 53) {
regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_1;
err = fc0011_writereg(priv, FC11_REG_VCOSEL,
regs[FC11_REG_VCOSEL]);
if (err)
return err;
err = fc0011_vcocal_trigger(priv);
if (err)
return err;
} else {
regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_2;
err = fc0011_writereg(priv, FC11_REG_VCOSEL,
regs[FC11_REG_VCOSEL]);
if (err)
return err;
}
break;
}
err = fc0011_vcocal_read(priv, NULL);
if (err)
return err;
usleep_range(10000, 50000);
err = fc0011_readreg(priv, FC11_REG_RCCAL, &regs[FC11_REG_RCCAL]);
if (err)
return err;
regs[FC11_REG_RCCAL] |= FC11_RCCAL_FORCE;
err = fc0011_writereg(priv, FC11_REG_RCCAL, regs[FC11_REG_RCCAL]);
if (err)
return err;
regs[FC11_REG_16] = 0xB;
err = fc0011_writereg(priv, FC11_REG_16, regs[FC11_REG_16]);
if (err)
return err;
dev_dbg(&priv->i2c->dev, "Tuned to "
"fa=%02X fp=%02X xin=%02X%02X vco=%02X vcosel=%02X "
"vcocal=%02X(%u) bw=%u\n",
(unsigned int)regs[FC11_REG_FA],
(unsigned int)regs[FC11_REG_FP],
(unsigned int)regs[FC11_REG_XINHI],
(unsigned int)regs[FC11_REG_XINLO],
(unsigned int)regs[FC11_REG_VCO],
(unsigned int)regs[FC11_REG_VCOSEL],
(unsigned int)vco_cal, vco_retries,
(unsigned int)bandwidth);
priv->frequency = p->frequency;
priv->bandwidth = p->bandwidth_hz;
return 0;
}
static int fc0011_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct fc0011_priv *priv = fe->tuner_priv;
*frequency = priv->frequency;
return 0;
}
static int fc0011_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
*frequency = 0;
return 0;
}
static int fc0011_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
{
struct fc0011_priv *priv = fe->tuner_priv;
*bandwidth = priv->bandwidth;
return 0;
}
static const struct dvb_tuner_ops fc0011_tuner_ops = {
.info = {
.name = "Fitipower FC0011",
.frequency_min = 45000000,
.frequency_max = 1000000000,
},
.release = fc0011_release,
.init = fc0011_init,
.set_params = fc0011_set_params,
.get_frequency = fc0011_get_frequency,
.get_if_frequency = fc0011_get_if_frequency,
.get_bandwidth = fc0011_get_bandwidth,
};
struct dvb_frontend *fc0011_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
const struct fc0011_config *config)
{
struct fc0011_priv *priv;
priv = kzalloc(sizeof(struct fc0011_priv), GFP_KERNEL);
if (!priv)
return NULL;
priv->i2c = i2c;
priv->addr = config->i2c_address;
fe->tuner_priv = priv;
fe->ops.tuner_ops = fc0011_tuner_ops;
dev_info(&priv->i2c->dev, "Fitipower FC0011 tuner attached\n");
return fe;
}
EXPORT_SYMBOL(fc0011_attach);
MODULE_DESCRIPTION("Fitipower FC0011 silicon tuner driver");
MODULE_AUTHOR("Michael Buesch <m@bues.ch>");
MODULE_LICENSE("GPL");

41
drivers/media/tuners/fc0011.h Normal file
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@ -0,0 +1,41 @@
#ifndef LINUX_FC0011_H_
#define LINUX_FC0011_H_
#include <linux/kconfig.h>
#include "dvb_frontend.h"
/** struct fc0011_config - fc0011 hardware config
*
* @i2c_address: I2C bus address.
*/
struct fc0011_config {
u8 i2c_address;
};
/** enum fc0011_fe_callback_commands - Frontend callbacks
*
* @FC0011_FE_CALLBACK_POWER: Power on tuner hardware.
* @FC0011_FE_CALLBACK_RESET: Request a tuner reset.
*/
enum fc0011_fe_callback_commands {
FC0011_FE_CALLBACK_POWER,
FC0011_FE_CALLBACK_RESET,
};
#if IS_ENABLED(CONFIG_MEDIA_TUNER_FC0011)
struct dvb_frontend *fc0011_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
const struct fc0011_config *config);
#else
static inline
struct dvb_frontend *fc0011_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
const struct fc0011_config *config)
{
dev_err(&i2c->dev, "fc0011 driver disabled in Kconfig\n");
return NULL;
}
#endif
#endif /* LINUX_FC0011_H_ */

32
drivers/media/tuners/fc0012-priv.h Normal file
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/*
* Fitipower FC0012 tuner driver - private includes
*
* Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _FC0012_PRIV_H_
#define _FC0012_PRIV_H_
struct fc0012_priv {
struct i2c_adapter *i2c;
const struct fc0012_config *cfg;
u32 frequency;
u32 bandwidth;
};
#endif

518
drivers/media/tuners/fc0012.c Normal file
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/*
* Fitipower FC0012 tuner driver
*
* Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include "fc0012.h"
#include "fc0012-priv.h"
static int fc0012_writereg(struct fc0012_priv *priv, u8 reg, u8 val)
{
u8 buf[2] = {reg, val};
struct i2c_msg msg = {
.addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2
};
if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
dev_err(&priv->i2c->dev,
"%s: I2C write reg failed, reg: %02x, val: %02x\n",
KBUILD_MODNAME, reg, val);
return -EREMOTEIO;
}
return 0;
}
static int fc0012_readreg(struct fc0012_priv *priv, u8 reg, u8 *val)
{
struct i2c_msg msg[2] = {
{ .addr = priv->cfg->i2c_address, .flags = 0,
.buf = &reg, .len = 1 },
{ .addr = priv->cfg->i2c_address, .flags = I2C_M_RD,
.buf = val, .len = 1 },
};
if (i2c_transfer(priv->i2c, msg, 2) != 2) {
dev_err(&priv->i2c->dev,
"%s: I2C read reg failed, reg: %02x\n",
KBUILD_MODNAME, reg);
return -EREMOTEIO;
}
return 0;
}
static int fc0012_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
return 0;
}
static int fc0012_init(struct dvb_frontend *fe)
{
struct fc0012_priv *priv = fe->tuner_priv;
int i, ret = 0;
unsigned char reg[] = {
0x00, /* dummy reg. 0 */
0x05, /* reg. 0x01 */
0x10, /* reg. 0x02 */
0x00, /* reg. 0x03 */
0x00, /* reg. 0x04 */
0x0f, /* reg. 0x05: may also be 0x0a */
0x00, /* reg. 0x06: divider 2, VCO slow */
0x00, /* reg. 0x07: may also be 0x0f */
0xff, /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256,
Loop Bw 1/8 */
0x6e, /* reg. 0x09: Disable LoopThrough, Enable LoopThrough: 0x6f */
0xb8, /* reg. 0x0a: Disable LO Test Buffer */
0x82, /* reg. 0x0b: Output Clock is same as clock frequency,
may also be 0x83 */
0xfc, /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */
0x02, /* reg. 0x0d: AGC Not Forcing & LNA Forcing, 0x02 for DVB-T */
0x00, /* reg. 0x0e */
0x00, /* reg. 0x0f */
0x00, /* reg. 0x10: may also be 0x0d */
0x00, /* reg. 0x11 */
0x1f, /* reg. 0x12: Set to maximum gain */
0x08, /* reg. 0x13: Set to Middle Gain: 0x08,
Low Gain: 0x00, High Gain: 0x10, enable IX2: 0x80 */
0x00, /* reg. 0x14 */
0x04, /* reg. 0x15: Enable LNA COMPS */
};
switch (priv->cfg->xtal_freq) {
case FC_XTAL_27_MHZ:
case FC_XTAL_28_8_MHZ:
reg[0x07] |= 0x20;
break;
case FC_XTAL_36_MHZ:
default:
break;
}
if (priv->cfg->dual_master)
reg[0x0c] |= 0x02;
if (priv->cfg->loop_through)
reg[0x09] |= 0x01;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
for (i = 1; i < sizeof(reg); i++) {
ret = fc0012_writereg(priv, i, reg[i]);
if (ret)
break;
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
if (ret)
dev_err(&priv->i2c->dev, "%s: fc0012_writereg failed: %d\n",
KBUILD_MODNAME, ret);
return ret;
}
static int fc0012_set_params(struct dvb_frontend *fe)
{
struct fc0012_priv *priv = fe->tuner_priv;
int i, ret = 0;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u32 freq = p->frequency / 1000;
u32 delsys = p->delivery_system;
unsigned char reg[7], am, pm, multi, tmp;
unsigned long f_vco;
unsigned short xtal_freq_khz_2, xin, xdiv;
bool vco_select = false;
if (fe->callback) {
ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
FC_FE_CALLBACK_VHF_ENABLE, (freq > 300000 ? 0 : 1));
if (ret)
goto exit;
}
switch (priv->cfg->xtal_freq) {
case FC_XTAL_27_MHZ:
xtal_freq_khz_2 = 27000 / 2;
break;
case FC_XTAL_36_MHZ:
xtal_freq_khz_2 = 36000 / 2;
break;
case FC_XTAL_28_8_MHZ:
default:
xtal_freq_khz_2 = 28800 / 2;
break;
}
/* select frequency divider and the frequency of VCO */
if (freq < 37084) { /* freq * 96 < 3560000 */
multi = 96;
reg[5] = 0x82;
reg[6] = 0x00;
} else if (freq < 55625) { /* freq * 64 < 3560000 */
multi = 64;
reg[5] = 0x82;
reg[6] = 0x02;
} else if (freq < 74167) { /* freq * 48 < 3560000 */
multi = 48;
reg[5] = 0x42;
reg[6] = 0x00;
} else if (freq < 111250) { /* freq * 32 < 3560000 */
multi = 32;
reg[5] = 0x42;
reg[6] = 0x02;
} else if (freq < 148334) { /* freq * 24 < 3560000 */
multi = 24;
reg[5] = 0x22;
reg[6] = 0x00;
} else if (freq < 222500) { /* freq * 16 < 3560000 */
multi = 16;
reg[5] = 0x22;
reg[6] = 0x02;
} else if (freq < 296667) { /* freq * 12 < 3560000 */
multi = 12;
reg[5] = 0x12;
reg[6] = 0x00;
} else if (freq < 445000) { /* freq * 8 < 3560000 */
multi = 8;
reg[5] = 0x12;
reg[6] = 0x02;
} else if (freq < 593334) { /* freq * 6 < 3560000 */
multi = 6;
reg[5] = 0x0a;
reg[6] = 0x00;
} else {
multi = 4;
reg[5] = 0x0a;
reg[6] = 0x02;
}
f_vco = freq * multi;
if (f_vco >= 3060000) {
reg[6] |= 0x08;
vco_select = true;
}
if (freq >= 45000) {
/* From divided value (XDIV) determined the FA and FP value */
xdiv = (unsigned short)(f_vco / xtal_freq_khz_2);
if ((f_vco - xdiv * xtal_freq_khz_2) >= (xtal_freq_khz_2 / 2))
xdiv++;
pm = (unsigned char)(xdiv / 8);
am = (unsigned char)(xdiv - (8 * pm));
if (am < 2) {
reg[1] = am + 8;
reg[2] = pm - 1;
} else {
reg[1] = am;
reg[2] = pm;
}
} else {
/* fix for frequency less than 45 MHz */
reg[1] = 0x06;
reg[2] = 0x11;
}
/* fix clock out */
reg[6] |= 0x20;
/* From VCO frequency determines the XIN ( fractional part of Delta
Sigma PLL) and divided value (XDIV) */
xin = (unsigned short)(f_vco - (f_vco / xtal_freq_khz_2) * xtal_freq_khz_2);
xin = (xin << 15) / xtal_freq_khz_2;
if (xin >= 16384)
xin += 32768;
reg[3] = xin >> 8; /* xin with 9 bit resolution */
reg[4] = xin & 0xff;
if (delsys == SYS_DVBT) {
reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */
switch (p->bandwidth_hz) {
case 6000000:
reg[6] |= 0x80;
break;
case 7000000:
reg[6] |= 0x40;
break;
case 8000000:
default:
break;
}
} else {
dev_err(&priv->i2c->dev, "%s: modulation type not supported!\n",
KBUILD_MODNAME);
return -EINVAL;
}
/* modified for Realtek demod */
reg[5] |= 0x07;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
for (i = 1; i <= 6; i++) {
ret = fc0012_writereg(priv, i, reg[i]);
if (ret)
goto exit;
}
/* VCO Calibration */
ret = fc0012_writereg(priv, 0x0e, 0x80);
if (!ret)
ret = fc0012_writereg(priv, 0x0e, 0x00);
/* VCO Re-Calibration if needed */
if (!ret)
ret = fc0012_writereg(priv, 0x0e, 0x00);
if (!ret) {
msleep(10);
ret = fc0012_readreg(priv, 0x0e, &tmp);
}
if (ret)
goto exit;
/* vco selection */
tmp &= 0x3f;
if (vco_select) {
if (tmp > 0x3c) {
reg[6] &= ~0x08;
ret = fc0012_writereg(priv, 0x06, reg[6]);
if (!ret)
ret = fc0012_writereg(priv, 0x0e, 0x80);
if (!ret)
ret = fc0012_writereg(priv, 0x0e, 0x00);
}
} else {
if (tmp < 0x02) {
reg[6] |= 0x08;
ret = fc0012_writereg(priv, 0x06, reg[6]);
if (!ret)
ret = fc0012_writereg(priv, 0x0e, 0x80);
if (!ret)
ret = fc0012_writereg(priv, 0x0e, 0x00);
}
}
priv->frequency = p->frequency;
priv->bandwidth = p->bandwidth_hz;
exit:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
if (ret)
dev_warn(&priv->i2c->dev, "%s: %s failed: %d\n",
KBUILD_MODNAME, __func__, ret);
return ret;
}
static int fc0012_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct fc0012_priv *priv = fe->tuner_priv;
*frequency = priv->frequency;
return 0;
}
static int fc0012_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
*frequency = 0; /* Zero-IF */
return 0;
}
static int fc0012_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
{
struct fc0012_priv *priv = fe->tuner_priv;
*bandwidth = priv->bandwidth;
return 0;
}
#define INPUT_ADC_LEVEL -8
static int fc0012_get_rf_strength(struct dvb_frontend *fe, u16 *strength)
{
struct fc0012_priv *priv = fe->tuner_priv;
int ret;
unsigned char tmp;
int int_temp, lna_gain, int_lna, tot_agc_gain, power;
const int fc0012_lna_gain_table[] = {
/* low gain */
-63, -58, -99, -73,
-63, -65, -54, -60,
/* middle gain */
71, 70, 68, 67,
65, 63, 61, 58,
/* high gain */
197, 191, 188, 186,
184, 182, 181, 179,
};
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
ret = fc0012_writereg(priv, 0x12, 0x00);
if (ret)
goto err;
ret = fc0012_readreg(priv, 0x12, &tmp);
if (ret)
goto err;
int_temp = tmp;
ret = fc0012_readreg(priv, 0x13, &tmp);
if (ret)
goto err;
lna_gain = tmp & 0x1f;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
if (lna_gain < ARRAY_SIZE(fc0012_lna_gain_table)) {
int_lna = fc0012_lna_gain_table[lna_gain];
tot_agc_gain = (abs((int_temp >> 5) - 7) - 2 +
(int_temp & 0x1f)) * 2;
power = INPUT_ADC_LEVEL - tot_agc_gain - int_lna / 10;
if (power >= 45)
*strength = 255; /* 100% */
else if (power < -95)
*strength = 0;
else
*strength = (power + 95) * 255 / 140;
*strength |= *strength << 8;
} else {
ret = -1;
}
goto exit;
err:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
exit:
if (ret)
dev_warn(&priv->i2c->dev, "%s: %s failed: %d\n",
KBUILD_MODNAME, __func__, ret);
return ret;
}
static const struct dvb_tuner_ops fc0012_tuner_ops = {
.info = {
.name = "Fitipower FC0012",
.frequency_min = 37000000, /* estimate */
.frequency_max = 862000000, /* estimate */
.frequency_step = 0,
},
.release = fc0012_release,
.init = fc0012_init,
.set_params = fc0012_set_params,
.get_frequency = fc0012_get_frequency,
.get_if_frequency = fc0012_get_if_frequency,
.get_bandwidth = fc0012_get_bandwidth,
.get_rf_strength = fc0012_get_rf_strength,
};
struct dvb_frontend *fc0012_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, const struct fc0012_config *cfg)
{
struct fc0012_priv *priv;
int ret;
u8 chip_id;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
priv = kzalloc(sizeof(struct fc0012_priv), GFP_KERNEL);
if (!priv) {
ret = -ENOMEM;
dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
goto err;
}
priv->cfg = cfg;
priv->i2c = i2c;
/* check if the tuner is there */
ret = fc0012_readreg(priv, 0x00, &chip_id);
if (ret < 0)
goto err;
dev_dbg(&i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
switch (chip_id) {
case 0xa1:
break;
default:
ret = -ENODEV;
goto err;
}
dev_info(&i2c->dev, "%s: Fitipower FC0012 successfully identified\n",
KBUILD_MODNAME);
if (priv->cfg->loop_through) {
ret = fc0012_writereg(priv, 0x09, 0x6f);
if (ret < 0)
goto err;
}
/*
* TODO: Clock out en or div?
* For dual tuner configuration clearing bit [0] is required.
*/
if (priv->cfg->clock_out) {
ret = fc0012_writereg(priv, 0x0b, 0x82);
if (ret < 0)
goto err;
}
fe->tuner_priv = priv;
memcpy(&fe->ops.tuner_ops, &fc0012_tuner_ops,
sizeof(struct dvb_tuner_ops));
err:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
if (ret) {
dev_dbg(&i2c->dev, "%s: failed: %d\n", __func__, ret);
kfree(priv);
return NULL;
}
return fe;
}
EXPORT_SYMBOL(fc0012_attach);
MODULE_DESCRIPTION("Fitipower FC0012 silicon tuner driver");
MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>");
MODULE_LICENSE("GPL");
MODULE_VERSION("0.6");

66
drivers/media/tuners/fc0012.h Normal file
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@ -0,0 +1,66 @@
/*
* Fitipower FC0012 tuner driver - include
*
* Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _FC0012_H_
#define _FC0012_H_
#include <linux/kconfig.h>
#include "dvb_frontend.h"
#include "fc001x-common.h"
struct fc0012_config {
/*
* I2C address
*/
u8 i2c_address;
/*
* clock
*/
enum fc001x_xtal_freq xtal_freq;
bool dual_master;
/*
* RF loop-through
*/
bool loop_through;
/*
* clock output
*/
bool clock_out;
};
#if IS_ENABLED(CONFIG_MEDIA_TUNER_FC0012)
extern struct dvb_frontend *fc0012_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
const struct fc0012_config *cfg);
#else
static inline struct dvb_frontend *fc0012_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
const struct fc0012_config *cfg)
{
pr_warn("%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif

44
drivers/media/tuners/fc0013-priv.h Normal file
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/*
* Fitipower FC0013 tuner driver
*
* Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef _FC0013_PRIV_H_
#define _FC0013_PRIV_H_
#define LOG_PREFIX "fc0013"
#undef err
#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg)
#undef info
#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
#undef warn
#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg)
struct fc0013_priv {
struct i2c_adapter *i2c;
u8 addr;
u8 dual_master;
u8 xtal_freq;
u32 frequency;
u32 bandwidth;
};
#endif

634
drivers/media/tuners/fc0013.c Normal file
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@ -0,0 +1,634 @@
/*
* Fitipower FC0013 tuner driver
*
* Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
* partially based on driver code from Fitipower
* Copyright (C) 2010 Fitipower Integrated Technology Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include "fc0013.h"
#include "fc0013-priv.h"
static int fc0013_writereg(struct fc0013_priv *priv, u8 reg, u8 val)
{
u8 buf[2] = {reg, val};
struct i2c_msg msg = {
.addr = priv->addr, .flags = 0, .buf = buf, .len = 2
};
if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
err("I2C write reg failed, reg: %02x, val: %02x", reg, val);
return -EREMOTEIO;
}
return 0;
}
static int fc0013_readreg(struct fc0013_priv *priv, u8 reg, u8 *val)
{
struct i2c_msg msg[2] = {
{ .addr = priv->addr, .flags = 0, .buf = &reg, .len = 1 },
{ .addr = priv->addr, .flags = I2C_M_RD, .buf = val, .len = 1 },
};
if (i2c_transfer(priv->i2c, msg, 2) != 2) {
err("I2C read reg failed, reg: %02x", reg);
return -EREMOTEIO;
}
return 0;
}
static int fc0013_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
return 0;
}
static int fc0013_init(struct dvb_frontend *fe)
{
struct fc0013_priv *priv = fe->tuner_priv;
int i, ret = 0;
unsigned char reg[] = {
0x00, /* reg. 0x00: dummy */
0x09, /* reg. 0x01 */
0x16, /* reg. 0x02 */
0x00, /* reg. 0x03 */
0x00, /* reg. 0x04 */
0x17, /* reg. 0x05 */
0x02, /* reg. 0x06 */
0x0a, /* reg. 0x07: CHECK */
0xff, /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256,
Loop Bw 1/8 */
0x6f, /* reg. 0x09: enable LoopThrough */
0xb8, /* reg. 0x0a: Disable LO Test Buffer */
0x82, /* reg. 0x0b: CHECK */
0xfc, /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */
0x01, /* reg. 0x0d: AGC Not Forcing & LNA Forcing, may need 0x02 */
0x00, /* reg. 0x0e */
0x00, /* reg. 0x0f */
0x00, /* reg. 0x10 */
0x00, /* reg. 0x11 */
0x00, /* reg. 0x12 */
0x00, /* reg. 0x13 */
0x50, /* reg. 0x14: DVB-t High Gain, UHF.
Middle Gain: 0x48, Low Gain: 0x40 */
0x01, /* reg. 0x15 */
};
switch (priv->xtal_freq) {
case FC_XTAL_27_MHZ:
case FC_XTAL_28_8_MHZ:
reg[0x07] |= 0x20;
break;
case FC_XTAL_36_MHZ:
default:
break;
}
if (priv->dual_master)
reg[0x0c] |= 0x02;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
for (i = 1; i < sizeof(reg); i++) {
ret = fc0013_writereg(priv, i, reg[i]);
if (ret)
break;
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
if (ret)
err("fc0013_writereg failed: %d", ret);
return ret;
}
static int fc0013_sleep(struct dvb_frontend *fe)
{
/* nothing to do here */
return 0;
}
int fc0013_rc_cal_add(struct dvb_frontend *fe, int rc_val)
{
struct fc0013_priv *priv = fe->tuner_priv;
int ret;
u8 rc_cal;
int val;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
/* push rc_cal value, get rc_cal value */
ret = fc0013_writereg(priv, 0x10, 0x00);
if (ret)
goto error_out;
/* get rc_cal value */
ret = fc0013_readreg(priv, 0x10, &rc_cal);
if (ret)
goto error_out;
rc_cal &= 0x0f;
val = (int)rc_cal + rc_val;
/* forcing rc_cal */
ret = fc0013_writereg(priv, 0x0d, 0x11);
if (ret)
goto error_out;
/* modify rc_cal value */
if (val > 15)
ret = fc0013_writereg(priv, 0x10, 0x0f);
else if (val < 0)
ret = fc0013_writereg(priv, 0x10, 0x00);
else
ret = fc0013_writereg(priv, 0x10, (u8)val);
error_out:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
return ret;
}
EXPORT_SYMBOL(fc0013_rc_cal_add);
int fc0013_rc_cal_reset(struct dvb_frontend *fe)
{
struct fc0013_priv *priv = fe->tuner_priv;
int ret;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
ret = fc0013_writereg(priv, 0x0d, 0x01);
if (!ret)
ret = fc0013_writereg(priv, 0x10, 0x00);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
return ret;
}
EXPORT_SYMBOL(fc0013_rc_cal_reset);
static int fc0013_set_vhf_track(struct fc0013_priv *priv, u32 freq)
{
int ret;
u8 tmp;
ret = fc0013_readreg(priv, 0x1d, &tmp);
if (ret)
goto error_out;
tmp &= 0xe3;
if (freq <= 177500) { /* VHF Track: 7 */
ret = fc0013_writereg(priv, 0x1d, tmp | 0x1c);
} else if (freq <= 184500) { /* VHF Track: 6 */
ret = fc0013_writereg(priv, 0x1d, tmp | 0x18);
} else if (freq <= 191500) { /* VHF Track: 5 */
ret = fc0013_writereg(priv, 0x1d, tmp | 0x14);
} else if (freq <= 198500) { /* VHF Track: 4 */
ret = fc0013_writereg(priv, 0x1d, tmp | 0x10);
} else if (freq <= 205500) { /* VHF Track: 3 */
ret = fc0013_writereg(priv, 0x1d, tmp | 0x0c);
} else if (freq <= 219500) { /* VHF Track: 2 */
ret = fc0013_writereg(priv, 0x1d, tmp | 0x08);
} else if (freq < 300000) { /* VHF Track: 1 */
ret = fc0013_writereg(priv, 0x1d, tmp | 0x04);
} else { /* UHF and GPS */
ret = fc0013_writereg(priv, 0x1d, tmp | 0x1c);
}
if (ret)
goto error_out;
error_out:
return ret;
}
static int fc0013_set_params(struct dvb_frontend *fe)
{
struct fc0013_priv *priv = fe->tuner_priv;
int i, ret = 0;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u32 freq = p->frequency / 1000;
u32 delsys = p->delivery_system;
unsigned char reg[7], am, pm, multi, tmp;
unsigned long f_vco;
unsigned short xtal_freq_khz_2, xin, xdiv;
bool vco_select = false;
if (fe->callback) {
ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
FC_FE_CALLBACK_VHF_ENABLE, (freq > 300000 ? 0 : 1));
if (ret)
goto exit;
}
switch (priv->xtal_freq) {
case FC_XTAL_27_MHZ:
xtal_freq_khz_2 = 27000 / 2;
break;
case FC_XTAL_36_MHZ:
xtal_freq_khz_2 = 36000 / 2;
break;
case FC_XTAL_28_8_MHZ:
default:
xtal_freq_khz_2 = 28800 / 2;
break;
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
/* set VHF track */
ret = fc0013_set_vhf_track(priv, freq);
if (ret)
goto exit;
if (freq < 300000) {
/* enable VHF filter */
ret = fc0013_readreg(priv, 0x07, &tmp);
if (ret)
goto exit;
ret = fc0013_writereg(priv, 0x07, tmp | 0x10);
if (ret)
goto exit;
/* disable UHF & disable GPS */
ret = fc0013_readreg(priv, 0x14, &tmp);
if (ret)
goto exit;
ret = fc0013_writereg(priv, 0x14, tmp & 0x1f);
if (ret)
goto exit;
} else if (freq <= 862000) {
/* disable VHF filter */
ret = fc0013_readreg(priv, 0x07, &tmp);
if (ret)
goto exit;
ret = fc0013_writereg(priv, 0x07, tmp & 0xef);
if (ret)
goto exit;
/* enable UHF & disable GPS */
ret = fc0013_readreg(priv, 0x14, &tmp);
if (ret)
goto exit;
ret = fc0013_writereg(priv, 0x14, (tmp & 0x1f) | 0x40);
if (ret)
goto exit;
} else {
/* disable VHF filter */
ret = fc0013_readreg(priv, 0x07, &tmp);
if (ret)
goto exit;
ret = fc0013_writereg(priv, 0x07, tmp & 0xef);
if (ret)
goto exit;
/* disable UHF & enable GPS */
ret = fc0013_readreg(priv, 0x14, &tmp);
if (ret)
goto exit;
ret = fc0013_writereg(priv, 0x14, (tmp & 0x1f) | 0x20);
if (ret)
goto exit;
}
/* select frequency divider and the frequency of VCO */
if (freq < 37084) { /* freq * 96 < 3560000 */
multi = 96;
reg[5] = 0x82;
reg[6] = 0x00;
} else if (freq < 55625) { /* freq * 64 < 3560000 */
multi = 64;
reg[5] = 0x02;
reg[6] = 0x02;
} else if (freq < 74167) { /* freq * 48 < 3560000 */
multi = 48;
reg[5] = 0x42;
reg[6] = 0x00;
} else if (freq < 111250) { /* freq * 32 < 3560000 */
multi = 32;
reg[5] = 0x82;
reg[6] = 0x02;
} else if (freq < 148334) { /* freq * 24 < 3560000 */
multi = 24;
reg[5] = 0x22;
reg[6] = 0x00;
} else if (freq < 222500) { /* freq * 16 < 3560000 */
multi = 16;
reg[5] = 0x42;
reg[6] = 0x02;
} else if (freq < 296667) { /* freq * 12 < 3560000 */
multi = 12;
reg[5] = 0x12;
reg[6] = 0x00;
} else if (freq < 445000) { /* freq * 8 < 3560000 */
multi = 8;
reg[5] = 0x22;
reg[6] = 0x02;
} else if (freq < 593334) { /* freq * 6 < 3560000 */
multi = 6;
reg[5] = 0x0a;
reg[6] = 0x00;
} else if (freq < 950000) { /* freq * 4 < 3800000 */
multi = 4;
reg[5] = 0x12;
reg[6] = 0x02;
} else {
multi = 2;
reg[5] = 0x0a;
reg[6] = 0x02;
}
f_vco = freq * multi;
if (f_vco >= 3060000) {
reg[6] |= 0x08;
vco_select = true;
}
if (freq >= 45000) {
/* From divided value (XDIV) determined the FA and FP value */
xdiv = (unsigned short)(f_vco / xtal_freq_khz_2);
if ((f_vco - xdiv * xtal_freq_khz_2) >= (xtal_freq_khz_2 / 2))
xdiv++;
pm = (unsigned char)(xdiv / 8);
am = (unsigned char)(xdiv - (8 * pm));
if (am < 2) {
reg[1] = am + 8;
reg[2] = pm - 1;
} else {
reg[1] = am;
reg[2] = pm;
}
} else {
/* fix for frequency less than 45 MHz */
reg[1] = 0x06;
reg[2] = 0x11;
}
/* fix clock out */
reg[6] |= 0x20;
/* From VCO frequency determines the XIN ( fractional part of Delta
Sigma PLL) and divided value (XDIV) */
xin = (unsigned short)(f_vco - (f_vco / xtal_freq_khz_2) * xtal_freq_khz_2);
xin = (xin << 15) / xtal_freq_khz_2;
if (xin >= 16384)
xin += 32768;
reg[3] = xin >> 8;
reg[4] = xin & 0xff;
if (delsys == SYS_DVBT) {
reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */
switch (p->bandwidth_hz) {
case 6000000:
reg[6] |= 0x80;
break;
case 7000000:
reg[6] |= 0x40;
break;
case 8000000:
default:
break;
}
} else {
err("%s: modulation type not supported!", __func__);
return -EINVAL;
}
/* modified for Realtek demod */
reg[5] |= 0x07;
for (i = 1; i <= 6; i++) {
ret = fc0013_writereg(priv, i, reg[i]);
if (ret)
goto exit;
}
ret = fc0013_readreg(priv, 0x11, &tmp);
if (ret)
goto exit;
if (multi == 64)
ret = fc0013_writereg(priv, 0x11, tmp | 0x04);
else
ret = fc0013_writereg(priv, 0x11, tmp & 0xfb);
if (ret)
goto exit;
/* VCO Calibration */
ret = fc0013_writereg(priv, 0x0e, 0x80);
if (!ret)
ret = fc0013_writereg(priv, 0x0e, 0x00);
/* VCO Re-Calibration if needed */
if (!ret)
ret = fc0013_writereg(priv, 0x0e, 0x00);
if (!ret) {
msleep(10);
ret = fc0013_readreg(priv, 0x0e, &tmp);
}
if (ret)
goto exit;
/* vco selection */
tmp &= 0x3f;
if (vco_select) {
if (tmp > 0x3c) {
reg[6] &= ~0x08;
ret = fc0013_writereg(priv, 0x06, reg[6]);
if (!ret)
ret = fc0013_writereg(priv, 0x0e, 0x80);
if (!ret)
ret = fc0013_writereg(priv, 0x0e, 0x00);
}
} else {
if (tmp < 0x02) {
reg[6] |= 0x08;
ret = fc0013_writereg(priv, 0x06, reg[6]);
if (!ret)
ret = fc0013_writereg(priv, 0x0e, 0x80);
if (!ret)
ret = fc0013_writereg(priv, 0x0e, 0x00);
}
}
priv->frequency = p->frequency;
priv->bandwidth = p->bandwidth_hz;
exit:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
if (ret)
warn("%s: failed: %d", __func__, ret);
return ret;
}
static int fc0013_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct fc0013_priv *priv = fe->tuner_priv;
*frequency = priv->frequency;
return 0;
}
static int fc0013_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
/* always ? */
*frequency = 0;
return 0;
}
static int fc0013_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
{
struct fc0013_priv *priv = fe->tuner_priv;
*bandwidth = priv->bandwidth;
return 0;
}
#define INPUT_ADC_LEVEL -8
static int fc0013_get_rf_strength(struct dvb_frontend *fe, u16 *strength)
{
struct fc0013_priv *priv = fe->tuner_priv;
int ret;
unsigned char tmp;
int int_temp, lna_gain, int_lna, tot_agc_gain, power;
const int fc0013_lna_gain_table[] = {
/* low gain */
-63, -58, -99, -73,
-63, -65, -54, -60,
/* middle gain */
71, 70, 68, 67,
65, 63, 61, 58,
/* high gain */
197, 191, 188, 186,
184, 182, 181, 179,
};
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
ret = fc0013_writereg(priv, 0x13, 0x00);
if (ret)
goto err;
ret = fc0013_readreg(priv, 0x13, &tmp);
if (ret)
goto err;
int_temp = tmp;
ret = fc0013_readreg(priv, 0x14, &tmp);
if (ret)
goto err;
lna_gain = tmp & 0x1f;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
if (lna_gain < ARRAY_SIZE(fc0013_lna_gain_table)) {
int_lna = fc0013_lna_gain_table[lna_gain];
tot_agc_gain = (abs((int_temp >> 5) - 7) - 2 +
(int_temp & 0x1f)) * 2;
power = INPUT_ADC_LEVEL - tot_agc_gain - int_lna / 10;
if (power >= 45)
*strength = 255; /* 100% */
else if (power < -95)
*strength = 0;
else
*strength = (power + 95) * 255 / 140;
*strength |= *strength << 8;
} else {
ret = -1;
}
goto exit;
err:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
exit:
if (ret)
warn("%s: failed: %d", __func__, ret);
return ret;
}
static const struct dvb_tuner_ops fc0013_tuner_ops = {
.info = {
.name = "Fitipower FC0013",
.frequency_min = 37000000, /* estimate */
.frequency_max = 1680000000, /* CHECK */
.frequency_step = 0,
},
.release = fc0013_release,
.init = fc0013_init,
.sleep = fc0013_sleep,
.set_params = fc0013_set_params,
.get_frequency = fc0013_get_frequency,
.get_if_frequency = fc0013_get_if_frequency,
.get_bandwidth = fc0013_get_bandwidth,
.get_rf_strength = fc0013_get_rf_strength,
};
struct dvb_frontend *fc0013_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 i2c_address, int dual_master,
enum fc001x_xtal_freq xtal_freq)
{
struct fc0013_priv *priv = NULL;
priv = kzalloc(sizeof(struct fc0013_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->i2c = i2c;
priv->dual_master = dual_master;
priv->addr = i2c_address;
priv->xtal_freq = xtal_freq;
info("Fitipower FC0013 successfully attached.");
fe->tuner_priv = priv;
memcpy(&fe->ops.tuner_ops, &fc0013_tuner_ops,
sizeof(struct dvb_tuner_ops));
return fe;
}
EXPORT_SYMBOL(fc0013_attach);
MODULE_DESCRIPTION("Fitipower FC0013 silicon tuner driver");
MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>");
MODULE_LICENSE("GPL");
MODULE_VERSION("0.2");

57
drivers/media/tuners/fc0013.h Normal file
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/*
* Fitipower FC0013 tuner driver
*
* Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef _FC0013_H_
#define _FC0013_H_
#include <linux/kconfig.h>
#include "dvb_frontend.h"
#include "fc001x-common.h"
#if IS_ENABLED(CONFIG_MEDIA_TUNER_FC0013)
extern struct dvb_frontend *fc0013_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
u8 i2c_address, int dual_master,
enum fc001x_xtal_freq xtal_freq);
extern int fc0013_rc_cal_add(struct dvb_frontend *fe, int rc_val);
extern int fc0013_rc_cal_reset(struct dvb_frontend *fe);
#else
static inline struct dvb_frontend *fc0013_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
u8 i2c_address, int dual_master,
enum fc001x_xtal_freq xtal_freq)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
static inline int fc0013_rc_cal_add(struct dvb_frontend *fe, int rc_val)
{
return 0;
}
static inline int fc0013_rc_cal_reset(struct dvb_frontend *fe)
{
return 0;
}
#endif
#endif

39
drivers/media/tuners/fc001x-common.h Normal file
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/*
* Fitipower FC0012 & FC0013 tuner driver - common defines
*
* Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _FC001X_COMMON_H_
#define _FC001X_COMMON_H_
enum fc001x_xtal_freq {
FC_XTAL_27_MHZ, /* 27000000 */
FC_XTAL_28_8_MHZ, /* 28800000 */
FC_XTAL_36_MHZ, /* 36000000 */
};
/*
* enum fc001x_fe_callback_commands - Frontend callbacks
*
* @FC_FE_CALLBACK_VHF_ENABLE: enable VHF or UHF
*/
enum fc001x_fe_callback_commands {
FC_FE_CALLBACK_VHF_ENABLE,
};
#endif

555
drivers/media/tuners/fc2580.c Normal file
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/*
* FCI FC2580 silicon tuner driver
*
* Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include "fc2580_priv.h"
/* Max transfer size done by I2C transfer functions */
#define MAX_XFER_SIZE 64
/*
* TODO:
* I2C write and read works only for one single register. Multiple registers
* could not be accessed using normal register address auto-increment.
* There could be (very likely) register to change that behavior....
*
* Due to that limitation functions:
* fc2580_wr_regs()
* fc2580_rd_regs()
* could not be used for accessing more than one register at once.
*
* TODO:
* Currently it blind writes bunch of static registers from the
* fc2580_freq_regs_lut[] when fc2580_set_params() is called. Add some
* logic to reduce unneeded register writes.
*/
/* write multiple registers */
static int fc2580_wr_regs(struct fc2580_priv *priv, u8 reg, u8 *val, int len)
{
int ret;
u8 buf[MAX_XFER_SIZE];
struct i2c_msg msg[1] = {
{
.addr = priv->cfg->i2c_addr,
.flags = 0,
.len = 1 + len,
.buf = buf,
}
};
if (1 + len > sizeof(buf)) {
dev_warn(&priv->i2c->dev,
"%s: i2c wr reg=%04x: len=%d is too big!\n",
KBUILD_MODNAME, reg, len);
return -EINVAL;
}
buf[0] = reg;
memcpy(&buf[1], val, len);
ret = i2c_transfer(priv->i2c, msg, 1);
if (ret == 1) {
ret = 0;
} else {
dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d reg=%02x " \
"len=%d\n", KBUILD_MODNAME, ret, reg, len);
ret = -EREMOTEIO;
}
return ret;
}
/* read multiple registers */
static int fc2580_rd_regs(struct fc2580_priv *priv, u8 reg, u8 *val, int len)
{
int ret;
u8 buf[MAX_XFER_SIZE];
struct i2c_msg msg[2] = {
{
.addr = priv->cfg->i2c_addr,
.flags = 0,
.len = 1,
.buf = &reg,
}, {
.addr = priv->cfg->i2c_addr,
.flags = I2C_M_RD,
.len = len,
.buf = buf,
}
};
if (len > sizeof(buf)) {
dev_warn(&priv->i2c->dev,
"%s: i2c rd reg=%04x: len=%d is too big!\n",
KBUILD_MODNAME, reg, len);
return -EINVAL;
}
ret = i2c_transfer(priv->i2c, msg, 2);
if (ret == 2) {
memcpy(val, buf, len);
ret = 0;
} else {
dev_warn(&priv->i2c->dev, "%s: i2c rd failed=%d reg=%02x " \
"len=%d\n", KBUILD_MODNAME, ret, reg, len);
ret = -EREMOTEIO;
}
return ret;
}
/* write single register */
static int fc2580_wr_reg(struct fc2580_priv *priv, u8 reg, u8 val)
{
return fc2580_wr_regs(priv, reg, &val, 1);
}
/* read single register */
static int fc2580_rd_reg(struct fc2580_priv *priv, u8 reg, u8 *val)
{
return fc2580_rd_regs(priv, reg, val, 1);
}
/* write single register conditionally only when value differs from 0xff
* XXX: This is special routine meant only for writing fc2580_freq_regs_lut[]
* values. Do not use for the other purposes. */
static int fc2580_wr_reg_ff(struct fc2580_priv *priv, u8 reg, u8 val)
{
if (val == 0xff)
return 0;
else
return fc2580_wr_regs(priv, reg, &val, 1);
}
static int fc2580_set_params(struct dvb_frontend *fe)
{
struct fc2580_priv *priv = fe->tuner_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret = 0, i;
unsigned int r_val, n_val, k_val, k_val_reg, f_ref;
u8 tmp_val, r18_val;
u64 f_vco;
/*
* Fractional-N synthesizer/PLL.
* Most likely all those PLL calculations are not correct. I am not
* sure, but it looks like it is divider based Fractional-N synthesizer.
* There is divider for reference clock too?
* Anyhow, synthesizer calculation results seems to be quite correct.
*/
dev_dbg(&priv->i2c->dev, "%s: delivery_system=%d frequency=%d " \
"bandwidth_hz=%d\n", __func__,
c->delivery_system, c->frequency, c->bandwidth_hz);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
/* PLL */
for (i = 0; i < ARRAY_SIZE(fc2580_pll_lut); i++) {
if (c->frequency <= fc2580_pll_lut[i].freq)
break;
}
if (i == ARRAY_SIZE(fc2580_pll_lut))
goto err;
f_vco = c->frequency;
f_vco *= fc2580_pll_lut[i].div;
if (f_vco >= 2600000000UL)
tmp_val = 0x0e | fc2580_pll_lut[i].band;
else
tmp_val = 0x06 | fc2580_pll_lut[i].band;
ret = fc2580_wr_reg(priv, 0x02, tmp_val);
if (ret < 0)
goto err;
if (f_vco >= 2UL * 76 * priv->cfg->clock) {
r_val = 1;
r18_val = 0x00;
} else if (f_vco >= 1UL * 76 * priv->cfg->clock) {
r_val = 2;
r18_val = 0x10;
} else {
r_val = 4;
r18_val = 0x20;
}
f_ref = 2UL * priv->cfg->clock / r_val;
n_val = div_u64_rem(f_vco, f_ref, &k_val);
k_val_reg = div_u64(1ULL * k_val * (1 << 20), f_ref);
ret = fc2580_wr_reg(priv, 0x18, r18_val | ((k_val_reg >> 16) & 0xff));
if (ret < 0)
goto err;
ret = fc2580_wr_reg(priv, 0x1a, (k_val_reg >> 8) & 0xff);
if (ret < 0)
goto err;
ret = fc2580_wr_reg(priv, 0x1b, (k_val_reg >> 0) & 0xff);
if (ret < 0)
goto err;
ret = fc2580_wr_reg(priv, 0x1c, n_val);
if (ret < 0)
goto err;
if (priv->cfg->clock >= 28000000) {
ret = fc2580_wr_reg(priv, 0x4b, 0x22);
if (ret < 0)
goto err;
}
if (fc2580_pll_lut[i].band == 0x00) {
if (c->frequency <= 794000000)
tmp_val = 0x9f;
else
tmp_val = 0x8f;
ret = fc2580_wr_reg(priv, 0x2d, tmp_val);
if (ret < 0)
goto err;
}
/* registers */
for (i = 0; i < ARRAY_SIZE(fc2580_freq_regs_lut); i++) {
if (c->frequency <= fc2580_freq_regs_lut[i].freq)
break;
}
if (i == ARRAY_SIZE(fc2580_freq_regs_lut))
goto err;
ret = fc2580_wr_reg_ff(priv, 0x25, fc2580_freq_regs_lut[i].r25_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x27, fc2580_freq_regs_lut[i].r27_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x28, fc2580_freq_regs_lut[i].r28_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x29, fc2580_freq_regs_lut[i].r29_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x2b, fc2580_freq_regs_lut[i].r2b_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x2c, fc2580_freq_regs_lut[i].r2c_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x2d, fc2580_freq_regs_lut[i].r2d_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x30, fc2580_freq_regs_lut[i].r30_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x44, fc2580_freq_regs_lut[i].r44_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x50, fc2580_freq_regs_lut[i].r50_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x53, fc2580_freq_regs_lut[i].r53_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x5f, fc2580_freq_regs_lut[i].r5f_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x61, fc2580_freq_regs_lut[i].r61_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x62, fc2580_freq_regs_lut[i].r62_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x63, fc2580_freq_regs_lut[i].r63_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x67, fc2580_freq_regs_lut[i].r67_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x68, fc2580_freq_regs_lut[i].r68_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x69, fc2580_freq_regs_lut[i].r69_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x6a, fc2580_freq_regs_lut[i].r6a_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x6b, fc2580_freq_regs_lut[i].r6b_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x6c, fc2580_freq_regs_lut[i].r6c_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x6d, fc2580_freq_regs_lut[i].r6d_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x6e, fc2580_freq_regs_lut[i].r6e_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg_ff(priv, 0x6f, fc2580_freq_regs_lut[i].r6f_val);
if (ret < 0)
goto err;
/* IF filters */
for (i = 0; i < ARRAY_SIZE(fc2580_if_filter_lut); i++) {
if (c->bandwidth_hz <= fc2580_if_filter_lut[i].freq)
break;
}
if (i == ARRAY_SIZE(fc2580_if_filter_lut))
goto err;
ret = fc2580_wr_reg(priv, 0x36, fc2580_if_filter_lut[i].r36_val);
if (ret < 0)
goto err;
ret = fc2580_wr_reg(priv, 0x37, div_u64(1ULL * priv->cfg->clock *
fc2580_if_filter_lut[i].mul, 1000000000));
if (ret < 0)
goto err;
ret = fc2580_wr_reg(priv, 0x39, fc2580_if_filter_lut[i].r39_val);
if (ret < 0)
goto err;
/* calibration? */
ret = fc2580_wr_reg(priv, 0x2e, 0x09);
if (ret < 0)
goto err;
for (i = 0; i < 5; i++) {
ret = fc2580_rd_reg(priv, 0x2f, &tmp_val);
if (ret < 0)
goto err;
/* done when [7:6] are set */
if ((tmp_val & 0xc0) == 0xc0)
break;
ret = fc2580_wr_reg(priv, 0x2e, 0x01);
if (ret < 0)
goto err;
ret = fc2580_wr_reg(priv, 0x2e, 0x09);
if (ret < 0)
goto err;
usleep_range(5000, 25000);
}
dev_dbg(&priv->i2c->dev, "%s: loop=%i\n", __func__, i);
ret = fc2580_wr_reg(priv, 0x2e, 0x01);
if (ret < 0)
goto err;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return 0;
err:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
return ret;
}
static int fc2580_init(struct dvb_frontend *fe)
{
struct fc2580_priv *priv = fe->tuner_priv;
int ret, i;
dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
for (i = 0; i < ARRAY_SIZE(fc2580_init_reg_vals); i++) {
ret = fc2580_wr_reg(priv, fc2580_init_reg_vals[i].reg,
fc2580_init_reg_vals[i].val);
if (ret < 0)
goto err;
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return 0;
err:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
return ret;
}
static int fc2580_sleep(struct dvb_frontend *fe)
{
struct fc2580_priv *priv = fe->tuner_priv;
int ret;
dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
ret = fc2580_wr_reg(priv, 0x02, 0x0a);
if (ret < 0)
goto err;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return 0;
err:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
return ret;
}
static int fc2580_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct fc2580_priv *priv = fe->tuner_priv;
dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
*frequency = 0; /* Zero-IF */
return 0;
}
static int fc2580_release(struct dvb_frontend *fe)
{
struct fc2580_priv *priv = fe->tuner_priv;
dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
kfree(fe->tuner_priv);
return 0;
}
static const struct dvb_tuner_ops fc2580_tuner_ops = {
.info = {
.name = "FCI FC2580",
.frequency_min = 174000000,
.frequency_max = 862000000,
},
.release = fc2580_release,
.init = fc2580_init,
.sleep = fc2580_sleep,
.set_params = fc2580_set_params,
.get_if_frequency = fc2580_get_if_frequency,
};
struct dvb_frontend *fc2580_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, const struct fc2580_config *cfg)
{
struct fc2580_priv *priv;
int ret;
u8 chip_id;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
priv = kzalloc(sizeof(struct fc2580_priv), GFP_KERNEL);
if (!priv) {
ret = -ENOMEM;
dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
goto err;
}
priv->cfg = cfg;
priv->i2c = i2c;
/* check if the tuner is there */
ret = fc2580_rd_reg(priv, 0x01, &chip_id);
if (ret < 0)
goto err;
dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
switch (chip_id) {
case 0x56:
case 0x5a:
break;
default:
goto err;
}
dev_info(&priv->i2c->dev,
"%s: FCI FC2580 successfully identified\n",
KBUILD_MODNAME);
fe->tuner_priv = priv;
memcpy(&fe->ops.tuner_ops, &fc2580_tuner_ops,
sizeof(struct dvb_tuner_ops));
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return fe;
err:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
kfree(priv);
return NULL;
}
EXPORT_SYMBOL(fc2580_attach);
MODULE_DESCRIPTION("FCI FC2580 silicon tuner driver");
MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
MODULE_LICENSE("GPL");

52
drivers/media/tuners/fc2580.h Normal file
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@ -0,0 +1,52 @@
/*
* FCI FC2580 silicon tuner driver
*
* Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef FC2580_H
#define FC2580_H
#include <linux/kconfig.h>
#include "dvb_frontend.h"
struct fc2580_config {
/*
* I2C address
* 0x56, ...
*/
u8 i2c_addr;
/*
* clock
*/
u32 clock;
};
#if IS_ENABLED(CONFIG_MEDIA_TUNER_FC2580)
extern struct dvb_frontend *fc2580_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, const struct fc2580_config *cfg);
#else
static inline struct dvb_frontend *fc2580_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, const struct fc2580_config *cfg)
{
pr_warn("%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif

135
drivers/media/tuners/fc2580_priv.h Normal file
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/*
* FCI FC2580 silicon tuner driver
*
* Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef FC2580_PRIV_H
#define FC2580_PRIV_H
#include "fc2580.h"
#include <linux/math64.h>
struct fc2580_reg_val {
u8 reg;
u8 val;
};
static const struct fc2580_reg_val fc2580_init_reg_vals[] = {
{0x00, 0x00},
{0x12, 0x86},
{0x14, 0x5c},
{0x16, 0x3c},
{0x1f, 0xd2},
{0x09, 0xd7},
{0x0b, 0xd5},
{0x0c, 0x32},
{0x0e, 0x43},
{0x21, 0x0a},
{0x22, 0x82},
{0x45, 0x10},
{0x4c, 0x00},
{0x3f, 0x88},
{0x02, 0x0e},
{0x58, 0x14},
};
struct fc2580_pll {
u32 freq;
u8 div;
u8 band;
};
static const struct fc2580_pll fc2580_pll_lut[] = {
/* VCO min VCO max */
{ 400000000, 12, 0x80}, /* .......... 4800000000 */
{1000000000, 4, 0x00}, /* 1600000000 4000000000 */
{0xffffffff, 2, 0x40}, /* 2000000000 .......... */
};
struct fc2580_if_filter {
u32 freq;
u16 mul;
u8 r36_val;
u8 r39_val;
};
static const struct fc2580_if_filter fc2580_if_filter_lut[] = {
{ 6000000, 4400, 0x18, 0x00},
{ 7000000, 3910, 0x18, 0x80},
{ 8000000, 3300, 0x18, 0x80},
{0xffffffff, 3300, 0x18, 0x80},
};
struct fc2580_freq_regs {
u32 freq;
u8 r25_val;
u8 r27_val;
u8 r28_val;
u8 r29_val;
u8 r2b_val;
u8 r2c_val;
u8 r2d_val;
u8 r30_val;
u8 r44_val;
u8 r50_val;
u8 r53_val;
u8 r5f_val;
u8 r61_val;
u8 r62_val;
u8 r63_val;
u8 r67_val;
u8 r68_val;
u8 r69_val;
u8 r6a_val;
u8 r6b_val;
u8 r6c_val;
u8 r6d_val;
u8 r6e_val;
u8 r6f_val;
};
/* XXX: 0xff is used for don't-care! */
static const struct fc2580_freq_regs fc2580_freq_regs_lut[] = {
{ 400000000,
0xff, 0x77, 0x33, 0x40, 0xff, 0xff, 0xff, 0x09, 0xff, 0x8c,
0x50, 0x0f, 0x07, 0x00, 0x15, 0x03, 0x05, 0x10, 0x12, 0x08,
0x0a, 0x78, 0x32, 0x54},
{ 538000000,
0xf0, 0x77, 0x53, 0x60, 0xff, 0xff, 0xff, 0x09, 0xff, 0x8c,
0x50, 0x13, 0x07, 0x06, 0x15, 0x06, 0x08, 0x10, 0x12, 0x0b,
0x0c, 0x78, 0x32, 0x14},
{ 794000000,
0xf0, 0x77, 0x53, 0x60, 0xff, 0xff, 0xff, 0x09, 0xff, 0x8c,
0x50, 0x15, 0x03, 0x03, 0x15, 0x03, 0x05, 0x0c, 0x0e, 0x0b,
0x0c, 0x78, 0x32, 0x14},
{1000000000,
0xf0, 0x77, 0x53, 0x60, 0xff, 0xff, 0xff, 0x09, 0xff, 0x8c,
0x50, 0x15, 0x07, 0x06, 0x15, 0x07, 0x09, 0x10, 0x12, 0x0b,
0x0c, 0x78, 0x32, 0x14},
{0xffffffff,
0xff, 0xff, 0xff, 0xff, 0x70, 0x37, 0xe7, 0x09, 0x20, 0x8c,
0x50, 0x0f, 0x0f, 0x00, 0x13, 0x00, 0x02, 0x0c, 0x0e, 0x08,
0x0a, 0xa0, 0x50, 0x14},
};
struct fc2580_priv {
const struct fc2580_config *cfg;
struct i2c_adapter *i2c;
};
#endif

478
drivers/media/tuners/it913x.c Normal file
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/*
* ITE IT913X silicon tuner driver
*
* Copyright (C) 2011 Malcolm Priestley (tvboxspy@gmail.com)
* IT9137 Copyright (C) ITE Tech Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
*/
#include "it913x.h"
#include <linux/regmap.h>
struct it913x_dev {
struct i2c_client *client;
struct regmap *regmap;
struct dvb_frontend *fe;
u8 chip_ver:2;
u8 role:2;
u16 xtal;
u8 fdiv;
u8 clk_mode;
u32 fn_min;
bool active;
};
static int it913x_init(struct dvb_frontend *fe)
{
struct it913x_dev *dev = fe->tuner_priv;
int ret;
unsigned int utmp;
u8 iqik_m_cal, nv_val, buf[2];
static const u8 nv[] = {48, 32, 24, 16, 12, 8, 6, 4, 2};
unsigned long timeout;
dev_dbg(&dev->client->dev, "role %u\n", dev->role);
ret = regmap_write(dev->regmap, 0x80ec4c, 0x68);
if (ret)
goto err;
usleep_range(10000, 100000);
ret = regmap_read(dev->regmap, 0x80ec86, &utmp);
if (ret)
goto err;
switch (utmp) {
case 0:
/* 12.000 MHz */
dev->clk_mode = utmp;
dev->xtal = 2000;
dev->fdiv = 3;
iqik_m_cal = 16;
break;
case 1:
/* 20.480 MHz */
dev->clk_mode = utmp;
dev->xtal = 640;
dev->fdiv = 1;
iqik_m_cal = 6;
break;
default:
dev_err(&dev->client->dev, "unknown clock identifier %d\n", utmp);
goto err;
}
ret = regmap_read(dev->regmap, 0x80ed03, &utmp);
if (ret)
goto err;
else if (utmp < ARRAY_SIZE(nv))
nv_val = nv[utmp];
else
nv_val = 2;
#define TIMEOUT 50
timeout = jiffies + msecs_to_jiffies(TIMEOUT);
while (!time_after(jiffies, timeout)) {
ret = regmap_bulk_read(dev->regmap, 0x80ed23, buf, 2);
if (ret)
goto err;
utmp = (buf[1] << 8) | (buf[0] << 0);
if (utmp)
break;
}
dev_dbg(&dev->client->dev, "r_fbc_m_bdry took %u ms, val %u\n",
jiffies_to_msecs(jiffies) -
(jiffies_to_msecs(timeout) - TIMEOUT), utmp);
dev->fn_min = dev->xtal * utmp;
dev->fn_min /= (dev->fdiv * nv_val);
dev->fn_min *= 1000;
dev_dbg(&dev->client->dev, "fn_min %u\n", dev->fn_min);
/*
* Chip version BX never sets that flag so we just wait 50ms in that
* case. It is possible poll BX similarly than AX and then timeout in
* order to get 50ms delay, but that causes about 120 extra I2C
* messages. As for now, we just wait and reduce IO.
*/
if (dev->chip_ver == 1) {
#define TIMEOUT 50
timeout = jiffies + msecs_to_jiffies(TIMEOUT);
while (!time_after(jiffies, timeout)) {
ret = regmap_read(dev->regmap, 0x80ec82, &utmp);
if (ret)
goto err;
if (utmp)
break;
}
dev_dbg(&dev->client->dev, "p_tsm_init_mode took %u ms, val %u\n",
jiffies_to_msecs(jiffies) -
(jiffies_to_msecs(timeout) - TIMEOUT), utmp);
} else {
msleep(50);
}
ret = regmap_write(dev->regmap, 0x80ed81, iqik_m_cal);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x80ec57, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x80ec58, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x80ec40, 0x01);
if (ret)
goto err;
dev->active = true;
return 0;
err:
dev_dbg(&dev->client->dev, "failed %d\n", ret);
return ret;
}
static int it913x_sleep(struct dvb_frontend *fe)
{
struct it913x_dev *dev = fe->tuner_priv;
int ret, len;
dev_dbg(&dev->client->dev, "role %u\n", dev->role);
dev->active = false;
ret = regmap_bulk_write(dev->regmap, 0x80ec40, "\x00", 1);
if (ret)
goto err;
/*
* Writing '0x00' to master tuner register '0x80ec08' causes slave tuner
* communication lost. Due to that, we cannot put master full sleep.
*/
if (dev->role == IT913X_ROLE_DUAL_MASTER)
len = 4;
else
len = 15;
dev_dbg(&dev->client->dev, "role %u, len %d\n", dev->role, len);
ret = regmap_bulk_write(dev->regmap, 0x80ec02,
"\x3f\x1f\x3f\x3e\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00",
len);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x80ec12, "\x00\x00\x00\x00", 4);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x80ec17,
"\x00\x00\x00\x00\x00\x00\x00\x00\x00", 9);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x80ec22,
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 10);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x80ec20, "\x00", 1);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x80ec3f, "\x01", 1);
if (ret)
goto err;
return 0;
err:
dev_dbg(&dev->client->dev, "failed %d\n", ret);
return ret;
}
static int it913x_set_params(struct dvb_frontend *fe)
{
struct it913x_dev *dev = fe->tuner_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
unsigned int utmp;
u32 pre_lo_freq, t_cal_freq;
u16 iqik_m_cal, n_div;
u8 u8tmp, n, l_band, lna_band;
dev_dbg(&dev->client->dev, "role=%u, frequency %u, bandwidth_hz %u\n",
dev->role, c->frequency, c->bandwidth_hz);
if (!dev->active) {
ret = -EINVAL;
goto err;
}
if (c->frequency <= 74000000) {
n_div = 48;
n = 0;
} else if (c->frequency <= 111000000) {
n_div = 32;
n = 1;
} else if (c->frequency <= 148000000) {
n_div = 24;
n = 2;
} else if (c->frequency <= 222000000) {
n_div = 16;
n = 3;
} else if (c->frequency <= 296000000) {
n_div = 12;
n = 4;
} else if (c->frequency <= 445000000) {
n_div = 8;
n = 5;
} else if (c->frequency <= dev->fn_min) {
n_div = 6;
n = 6;
} else if (c->frequency <= 950000000) {
n_div = 4;
n = 7;
} else {
n_div = 2;
n = 0;
}
ret = regmap_read(dev->regmap, 0x80ed81, &utmp);
if (ret)
goto err;
iqik_m_cal = utmp * n_div;
if (utmp < 0x20) {
if (dev->clk_mode == 0)
iqik_m_cal = (iqik_m_cal * 9) >> 5;
else
iqik_m_cal >>= 1;
} else {
iqik_m_cal = 0x40 - iqik_m_cal;
if (dev->clk_mode == 0)
iqik_m_cal = ~((iqik_m_cal * 9) >> 5);
else
iqik_m_cal = ~(iqik_m_cal >> 1);
}
t_cal_freq = (c->frequency / 1000) * n_div * dev->fdiv;
pre_lo_freq = t_cal_freq / dev->xtal;
utmp = pre_lo_freq * dev->xtal;
if ((t_cal_freq - utmp) >= (dev->xtal >> 1))
pre_lo_freq++;
pre_lo_freq += (u32) n << 13;
/* Frequency OMEGA_IQIK_M_CAL_MID*/
t_cal_freq = pre_lo_freq + (u32)iqik_m_cal;
dev_dbg(&dev->client->dev, "t_cal_freq %u, pre_lo_freq %u\n",
t_cal_freq, pre_lo_freq);
if (c->frequency <= 440000000) {
l_band = 0;
lna_band = 0;
} else if (c->frequency <= 484000000) {
l_band = 1;
lna_band = 1;
} else if (c->frequency <= 533000000) {
l_band = 1;
lna_band = 2;
} else if (c->frequency <= 587000000) {
l_band = 1;
lna_band = 3;
} else if (c->frequency <= 645000000) {
l_band = 1;
lna_band = 4;
} else if (c->frequency <= 710000000) {
l_band = 1;
lna_band = 5;
} else if (c->frequency <= 782000000) {
l_band = 1;
lna_band = 6;
} else if (c->frequency <= 860000000) {
l_band = 1;
lna_band = 7;
} else if (c->frequency <= 1492000000) {
l_band = 1;
lna_band = 0;
} else if (c->frequency <= 1685000000) {
l_band = 1;
lna_band = 1;
} else {
ret = -EINVAL;
goto err;
}
/* XXX: latest windows driver does not set that at all */
ret = regmap_write(dev->regmap, 0x80ee06, lna_band);
if (ret)
goto err;
if (c->bandwidth_hz <= 5000000)
u8tmp = 0;
else if (c->bandwidth_hz <= 6000000)
u8tmp = 2;
else if (c->bandwidth_hz <= 7000000)
u8tmp = 4;
else
u8tmp = 6; /* 8000000 */
ret = regmap_write(dev->regmap, 0x80ec56, u8tmp);
if (ret)
goto err;
/* XXX: latest windows driver sets different value (a8 != 68) */
ret = regmap_write(dev->regmap, 0x80ec4c, 0xa0 | (l_band << 3));
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x80ec4d, (t_cal_freq >> 0) & 0xff);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x80ec4e, (t_cal_freq >> 8) & 0xff);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x80011e, (pre_lo_freq >> 0) & 0xff);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x80011f, (pre_lo_freq >> 8) & 0xff);
if (ret)
goto err;
return 0;
err:
dev_dbg(&dev->client->dev, "failed %d\n", ret);
return ret;
}
static const struct dvb_tuner_ops it913x_tuner_ops = {
.info = {
.name = "ITE IT913X",
.frequency_min = 174000000,
.frequency_max = 862000000,
},
.init = it913x_init,
.sleep = it913x_sleep,
.set_params = it913x_set_params,
};
static int it913x_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct it913x_config *cfg = client->dev.platform_data;
struct dvb_frontend *fe = cfg->fe;
struct it913x_dev *dev;
int ret;
char *chip_ver_str;
static const struct regmap_config regmap_config = {
.reg_bits = 24,
.val_bits = 8,
};
dev = kzalloc(sizeof(struct it913x_dev), GFP_KERNEL);
if (dev == NULL) {
ret = -ENOMEM;
dev_err(&client->dev, "kzalloc() failed\n");
goto err;
}
dev->client = client;
dev->fe = cfg->fe;
dev->chip_ver = cfg->chip_ver;
dev->role = cfg->role;
dev->regmap = regmap_init_i2c(client, &regmap_config);
if (IS_ERR(dev->regmap)) {
ret = PTR_ERR(dev->regmap);
goto err_kfree;
}
fe->tuner_priv = dev;
memcpy(&fe->ops.tuner_ops, &it913x_tuner_ops,
sizeof(struct dvb_tuner_ops));
i2c_set_clientdata(client, dev);
if (dev->chip_ver == 1)
chip_ver_str = "AX";
else if (dev->chip_ver == 2)
chip_ver_str = "BX";
else
chip_ver_str = "??";
dev_info(&dev->client->dev, "ITE IT913X %s successfully attached\n",
chip_ver_str);
dev_dbg(&dev->client->dev, "chip_ver %u, role %u\n",
dev->chip_ver, dev->role);
return 0;
err_kfree:
kfree(dev);
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int it913x_remove(struct i2c_client *client)
{
struct it913x_dev *dev = i2c_get_clientdata(client);
struct dvb_frontend *fe = dev->fe;
dev_dbg(&client->dev, "\n");
memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops));
fe->tuner_priv = NULL;
regmap_exit(dev->regmap);
kfree(dev);
return 0;
}
static const struct i2c_device_id it913x_id_table[] = {
{"it913x", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, it913x_id_table);
static struct i2c_driver it913x_driver = {
.driver = {
.owner = THIS_MODULE,
.name = "it913x",
},
.probe = it913x_probe,
.remove = it913x_remove,
.id_table = it913x_id_table,
};
module_i2c_driver(it913x_driver);
MODULE_DESCRIPTION("ITE IT913X silicon tuner driver");
MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
MODULE_LICENSE("GPL");

54
drivers/media/tuners/it913x.h Normal file
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/*
* ITE Tech IT9137 silicon tuner driver
*
* Copyright (C) 2011 Malcolm Priestley (tvboxspy@gmail.com)
* IT9137 Copyright (C) ITE Tech Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
*/
#ifndef IT913X_H
#define IT913X_H
#include "dvb_frontend.h"
/*
* I2C address
* 0x38, 0x3a, 0x3c, 0x3e
*/
struct it913x_config {
/*
* pointer to DVB frontend
*/
struct dvb_frontend *fe;
/*
* chip version
* 1 = IT9135 AX
* 2 = IT9135 BX
*/
unsigned int chip_ver:2;
/*
* tuner role
*/
#define IT913X_ROLE_SINGLE 0
#define IT913X_ROLE_DUAL_MASTER 1
#define IT913X_ROLE_DUAL_SLAVE 2
unsigned int role:2;
};
#endif

577
drivers/media/tuners/m88ts2022.c Normal file
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@ -0,0 +1,577 @@
/*
* Montage M88TS2022 silicon tuner driver
*
* Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Some calculations are taken from existing TS2020 driver.
*/
#include "m88ts2022_priv.h"
static int m88ts2022_cmd(struct m88ts2022_dev *dev, int op, int sleep, u8 reg,
u8 mask, u8 val, u8 *reg_val)
{
int ret, i;
unsigned int utmp;
struct m88ts2022_reg_val reg_vals[] = {
{0x51, 0x1f - op},
{0x51, 0x1f},
{0x50, 0x00 + op},
{0x50, 0x00},
};
for (i = 0; i < 2; i++) {
dev_dbg(&dev->client->dev,
"i=%d op=%02x reg=%02x mask=%02x val=%02x\n",
i, op, reg, mask, val);
for (i = 0; i < ARRAY_SIZE(reg_vals); i++) {
ret = regmap_write(dev->regmap, reg_vals[i].reg,
reg_vals[i].val);
if (ret)
goto err;
}
usleep_range(sleep * 1000, sleep * 10000);
ret = regmap_read(dev->regmap, reg, &utmp);
if (ret)
goto err;
if ((utmp & mask) != val)
break;
}
if (reg_val)
*reg_val = utmp;
err:
return ret;
}
static int m88ts2022_set_params(struct dvb_frontend *fe)
{
struct m88ts2022_dev *dev = fe->tuner_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
unsigned int utmp, frequency_khz, frequency_offset_khz, f_3db_hz;
unsigned int f_ref_khz, f_vco_khz, div_ref, div_out, pll_n, gdiv28;
u8 buf[3], u8tmp, cap_code, lpf_gm, lpf_mxdiv, div_max, div_min;
u16 u16tmp;
dev_dbg(&dev->client->dev,
"frequency=%d symbol_rate=%d rolloff=%d\n",
c->frequency, c->symbol_rate, c->rolloff);
/*
* Integer-N PLL synthesizer
* kHz is used for all calculations to keep calculations within 32-bit
*/
f_ref_khz = DIV_ROUND_CLOSEST(dev->cfg.clock, 1000);
div_ref = DIV_ROUND_CLOSEST(f_ref_khz, 2000);
if (c->symbol_rate < 5000000)
frequency_offset_khz = 3000; /* 3 MHz */
else
frequency_offset_khz = 0;
frequency_khz = c->frequency + frequency_offset_khz;
if (frequency_khz < 1103000) {
div_out = 4;
u8tmp = 0x1b;
} else {
div_out = 2;
u8tmp = 0x0b;
}
buf[0] = u8tmp;
buf[1] = 0x40;
ret = regmap_bulk_write(dev->regmap, 0x10, buf, 2);
if (ret)
goto err;
f_vco_khz = frequency_khz * div_out;
pll_n = f_vco_khz * div_ref / f_ref_khz;
pll_n += pll_n % 2;
dev->frequency_khz = pll_n * f_ref_khz / div_ref / div_out;
if (pll_n < 4095)
u16tmp = pll_n - 1024;
else if (pll_n < 6143)
u16tmp = pll_n + 1024;
else
u16tmp = pll_n + 3072;
buf[0] = (u16tmp >> 8) & 0x3f;
buf[1] = (u16tmp >> 0) & 0xff;
buf[2] = div_ref - 8;
ret = regmap_bulk_write(dev->regmap, 0x01, buf, 3);
if (ret)
goto err;
dev_dbg(&dev->client->dev,
"frequency=%u offset=%d f_vco_khz=%u pll_n=%u div_ref=%u div_out=%u\n",
dev->frequency_khz, dev->frequency_khz - c->frequency,
f_vco_khz, pll_n, div_ref, div_out);
ret = m88ts2022_cmd(dev, 0x10, 5, 0x15, 0x40, 0x00, NULL);
if (ret)
goto err;
ret = regmap_read(dev->regmap, 0x14, &utmp);
if (ret)
goto err;
utmp &= 0x7f;
if (utmp < 64) {
ret = regmap_update_bits(dev->regmap, 0x10, 0x80, 0x80);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x11, 0x6f);
if (ret)
goto err;
ret = m88ts2022_cmd(dev, 0x10, 5, 0x15, 0x40, 0x00, NULL);
if (ret)
goto err;
}
ret = regmap_read(dev->regmap, 0x14, &utmp);
if (ret)
goto err;
utmp &= 0x1f;
if (utmp > 19) {
ret = regmap_update_bits(dev->regmap, 0x10, 0x02, 0x00);
if (ret)
goto err;
}
ret = m88ts2022_cmd(dev, 0x08, 5, 0x3c, 0xff, 0x00, NULL);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x25, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x27, 0x70);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x41, 0x09);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x08, 0x0b);
if (ret)
goto err;
/* filters */
gdiv28 = DIV_ROUND_CLOSEST(f_ref_khz * 1694U, 1000000U);
ret = regmap_write(dev->regmap, 0x04, gdiv28);
if (ret)
goto err;
ret = m88ts2022_cmd(dev, 0x04, 2, 0x26, 0xff, 0x00, &u8tmp);
if (ret)
goto err;
cap_code = u8tmp & 0x3f;
ret = regmap_write(dev->regmap, 0x41, 0x0d);
if (ret)
goto err;
ret = m88ts2022_cmd(dev, 0x04, 2, 0x26, 0xff, 0x00, &u8tmp);
if (ret)
goto err;
u8tmp &= 0x3f;
cap_code = (cap_code + u8tmp) / 2;
gdiv28 = gdiv28 * 207 / (cap_code * 2 + 151);
div_max = gdiv28 * 135 / 100;
div_min = gdiv28 * 78 / 100;
div_max = clamp_val(div_max, 0U, 63U);
f_3db_hz = mult_frac(c->symbol_rate, 135, 200);
f_3db_hz += 2000000U + (frequency_offset_khz * 1000U);
f_3db_hz = clamp(f_3db_hz, 7000000U, 40000000U);
#define LPF_COEFF 3200U
lpf_gm = DIV_ROUND_CLOSEST(f_3db_hz * gdiv28, LPF_COEFF * f_ref_khz);
lpf_gm = clamp_val(lpf_gm, 1U, 23U);
lpf_mxdiv = DIV_ROUND_CLOSEST(lpf_gm * LPF_COEFF * f_ref_khz, f_3db_hz);
if (lpf_mxdiv < div_min)
lpf_mxdiv = DIV_ROUND_CLOSEST(++lpf_gm * LPF_COEFF * f_ref_khz, f_3db_hz);
lpf_mxdiv = clamp_val(lpf_mxdiv, 0U, div_max);
ret = regmap_write(dev->regmap, 0x04, lpf_mxdiv);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x06, lpf_gm);
if (ret)
goto err;
ret = m88ts2022_cmd(dev, 0x04, 2, 0x26, 0xff, 0x00, &u8tmp);
if (ret)
goto err;
cap_code = u8tmp & 0x3f;
ret = regmap_write(dev->regmap, 0x41, 0x09);
if (ret)
goto err;
ret = m88ts2022_cmd(dev, 0x04, 2, 0x26, 0xff, 0x00, &u8tmp);
if (ret)
goto err;
u8tmp &= 0x3f;
cap_code = (cap_code + u8tmp) / 2;
u8tmp = cap_code | 0x80;
ret = regmap_write(dev->regmap, 0x25, u8tmp);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x27, 0x30);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x08, 0x09);
if (ret)
goto err;
ret = m88ts2022_cmd(dev, 0x01, 20, 0x21, 0xff, 0x00, NULL);
if (ret)
goto err;
err:
if (ret)
dev_dbg(&dev->client->dev, "failed=%d\n", ret);
return ret;
}
static int m88ts2022_init(struct dvb_frontend *fe)
{
struct m88ts2022_dev *dev = fe->tuner_priv;
int ret, i;
u8 u8tmp;
static const struct m88ts2022_reg_val reg_vals[] = {
{0x7d, 0x9d},
{0x7c, 0x9a},
{0x7a, 0x76},
{0x3b, 0x01},
{0x63, 0x88},
{0x61, 0x85},
{0x22, 0x30},
{0x30, 0x40},
{0x20, 0x23},
{0x24, 0x02},
{0x12, 0xa0},
};
dev_dbg(&dev->client->dev, "\n");
ret = regmap_write(dev->regmap, 0x00, 0x01);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x00, 0x03);
if (ret)
goto err;
switch (dev->cfg.clock_out) {
case M88TS2022_CLOCK_OUT_DISABLED:
u8tmp = 0x60;
break;
case M88TS2022_CLOCK_OUT_ENABLED:
u8tmp = 0x70;
ret = regmap_write(dev->regmap, 0x05, dev->cfg.clock_out_div);
if (ret)
goto err;
break;
case M88TS2022_CLOCK_OUT_ENABLED_XTALOUT:
u8tmp = 0x6c;
break;
default:
goto err;
}
ret = regmap_write(dev->regmap, 0x42, u8tmp);
if (ret)
goto err;
if (dev->cfg.loop_through)
u8tmp = 0xec;
else
u8tmp = 0x6c;
ret = regmap_write(dev->regmap, 0x62, u8tmp);
if (ret)
goto err;
for (i = 0; i < ARRAY_SIZE(reg_vals); i++) {
ret = regmap_write(dev->regmap, reg_vals[i].reg, reg_vals[i].val);
if (ret)
goto err;
}
err:
if (ret)
dev_dbg(&dev->client->dev, "failed=%d\n", ret);
return ret;
}
static int m88ts2022_sleep(struct dvb_frontend *fe)
{
struct m88ts2022_dev *dev = fe->tuner_priv;
int ret;
dev_dbg(&dev->client->dev, "\n");
ret = regmap_write(dev->regmap, 0x00, 0x00);
if (ret)
goto err;
err:
if (ret)
dev_dbg(&dev->client->dev, "failed=%d\n", ret);
return ret;
}
static int m88ts2022_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct m88ts2022_dev *dev = fe->tuner_priv;
dev_dbg(&dev->client->dev, "\n");
*frequency = dev->frequency_khz;
return 0;
}
static int m88ts2022_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct m88ts2022_dev *dev = fe->tuner_priv;
dev_dbg(&dev->client->dev, "\n");
*frequency = 0; /* Zero-IF */
return 0;
}
static int m88ts2022_get_rf_strength(struct dvb_frontend *fe, u16 *strength)
{
struct m88ts2022_dev *dev = fe->tuner_priv;
int ret;
u16 gain, u16tmp;
unsigned int utmp, gain1, gain2, gain3;
ret = regmap_read(dev->regmap, 0x3d, &utmp);
if (ret)
goto err;
gain1 = (utmp >> 0) & 0x1f;
gain1 = clamp(gain1, 0U, 15U);
ret = regmap_read(dev->regmap, 0x21, &utmp);
if (ret)
goto err;
gain2 = (utmp >> 0) & 0x1f;
gain2 = clamp(gain2, 2U, 16U);
ret = regmap_read(dev->regmap, 0x66, &utmp);
if (ret)
goto err;
gain3 = (utmp >> 3) & 0x07;
gain3 = clamp(gain3, 0U, 6U);
gain = gain1 * 265 + gain2 * 338 + gain3 * 285;
/* scale value to 0x0000-0xffff */
u16tmp = (0xffff - gain);
u16tmp = clamp_val(u16tmp, 59000U, 61500U);
*strength = (u16tmp - 59000) * 0xffff / (61500 - 59000);
err:
if (ret)
dev_dbg(&dev->client->dev, "failed=%d\n", ret);
return ret;
}
static const struct dvb_tuner_ops m88ts2022_tuner_ops = {
.info = {
.name = "Montage M88TS2022",
.frequency_min = 950000,
.frequency_max = 2150000,
},
.init = m88ts2022_init,
.sleep = m88ts2022_sleep,
.set_params = m88ts2022_set_params,
.get_frequency = m88ts2022_get_frequency,
.get_if_frequency = m88ts2022_get_if_frequency,
.get_rf_strength = m88ts2022_get_rf_strength,
};
static int m88ts2022_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct m88ts2022_config *cfg = client->dev.platform_data;
struct dvb_frontend *fe = cfg->fe;
struct m88ts2022_dev *dev;
int ret;
u8 u8tmp;
unsigned int utmp;
static const struct regmap_config regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev) {
ret = -ENOMEM;
dev_err(&client->dev, "kzalloc() failed\n");
goto err;
}
memcpy(&dev->cfg, cfg, sizeof(struct m88ts2022_config));
dev->client = client;
dev->regmap = devm_regmap_init_i2c(client, &regmap_config);
if (IS_ERR(dev->regmap)) {
ret = PTR_ERR(dev->regmap);
goto err;
}
/* check if the tuner is there */
ret = regmap_read(dev->regmap, 0x00, &utmp);
if (ret)
goto err;
if ((utmp & 0x03) == 0x00) {
ret = regmap_write(dev->regmap, 0x00, 0x01);
if (ret)
goto err;
usleep_range(2000, 50000);
}
ret = regmap_write(dev->regmap, 0x00, 0x03);
if (ret)
goto err;
usleep_range(2000, 50000);
ret = regmap_read(dev->regmap, 0x00, &utmp);
if (ret)
goto err;
dev_dbg(&dev->client->dev, "chip_id=%02x\n", utmp);
switch (utmp) {
case 0xc3:
case 0x83:
break;
default:
goto err;
}
switch (dev->cfg.clock_out) {
case M88TS2022_CLOCK_OUT_DISABLED:
u8tmp = 0x60;
break;
case M88TS2022_CLOCK_OUT_ENABLED:
u8tmp = 0x70;
ret = regmap_write(dev->regmap, 0x05, dev->cfg.clock_out_div);
if (ret)
goto err;
break;
case M88TS2022_CLOCK_OUT_ENABLED_XTALOUT:
u8tmp = 0x6c;
break;
default:
goto err;
}
ret = regmap_write(dev->regmap, 0x42, u8tmp);
if (ret)
goto err;
if (dev->cfg.loop_through)
u8tmp = 0xec;
else
u8tmp = 0x6c;
ret = regmap_write(dev->regmap, 0x62, u8tmp);
if (ret)
goto err;
/* sleep */
ret = regmap_write(dev->regmap, 0x00, 0x00);
if (ret)
goto err;
dev_info(&dev->client->dev, "Montage M88TS2022 successfully identified\n");
fe->tuner_priv = dev;
memcpy(&fe->ops.tuner_ops, &m88ts2022_tuner_ops,
sizeof(struct dvb_tuner_ops));
i2c_set_clientdata(client, dev);
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
kfree(dev);
return ret;
}
static int m88ts2022_remove(struct i2c_client *client)
{
struct m88ts2022_dev *dev = i2c_get_clientdata(client);
struct dvb_frontend *fe = dev->cfg.fe;
dev_dbg(&client->dev, "\n");
memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops));
fe->tuner_priv = NULL;
kfree(dev);
return 0;
}
static const struct i2c_device_id m88ts2022_id[] = {
{"m88ts2022", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, m88ts2022_id);
static struct i2c_driver m88ts2022_driver = {
.driver = {
.owner = THIS_MODULE,
.name = "m88ts2022",
},
.probe = m88ts2022_probe,
.remove = m88ts2022_remove,
.id_table = m88ts2022_id,
};
module_i2c_driver(m88ts2022_driver);
MODULE_DESCRIPTION("Montage M88TS2022 silicon tuner driver");
MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
MODULE_LICENSE("GPL");

54
drivers/media/tuners/m88ts2022.h Normal file
View file

@ -0,0 +1,54 @@
/*
* Montage M88TS2022 silicon tuner driver
*
* Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef M88TS2022_H
#define M88TS2022_H
#include "dvb_frontend.h"
struct m88ts2022_config {
/*
* clock
* 16000000 - 32000000
*/
u32 clock;
/*
* RF loop-through
*/
u8 loop_through:1;
/*
* clock output
*/
#define M88TS2022_CLOCK_OUT_DISABLED 0
#define M88TS2022_CLOCK_OUT_ENABLED 1
#define M88TS2022_CLOCK_OUT_ENABLED_XTALOUT 2
u8 clock_out:2;
/*
* clock output divider
* 1 - 31
*/
u8 clock_out_div:5;
/*
* pointer to DVB frontend
*/
struct dvb_frontend *fe;
};
#endif

35
drivers/media/tuners/m88ts2022_priv.h Normal file
View file

@ -0,0 +1,35 @@
/*
* Montage M88TS2022 silicon tuner driver
*
* Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef M88TS2022_PRIV_H
#define M88TS2022_PRIV_H
#include "m88ts2022.h"
#include <linux/regmap.h>
struct m88ts2022_dev {
struct m88ts2022_config cfg;
struct i2c_client *client;
struct regmap *regmap;
u32 frequency_khz;
};
struct m88ts2022_reg_val {
u8 reg;
u8 val;
};
#endif

433
drivers/media/tuners/max2165.c Normal file
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@ -0,0 +1,433 @@
/*
* Driver for Maxim MAX2165 silicon tuner
*
* Copyright (c) 2009 David T. L. Wong <davidtlwong@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/videodev2.h>
#include <linux/delay.h>
#include <linux/dvb/frontend.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include "dvb_frontend.h"
#include "max2165.h"
#include "max2165_priv.h"
#include "tuner-i2c.h"
#define dprintk(args...) \
do { \
if (debug) \
printk(KERN_DEBUG "max2165: " args); \
} while (0)
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
static int max2165_write_reg(struct max2165_priv *priv, u8 reg, u8 data)
{
int ret;
u8 buf[] = { reg, data };
struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
msg.addr = priv->config->i2c_address;
if (debug >= 2)
dprintk("%s: reg=0x%02X, data=0x%02X\n", __func__, reg, data);
ret = i2c_transfer(priv->i2c, &msg, 1);
if (ret != 1)
dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
__func__, reg, data, ret);
return (ret != 1) ? -EIO : 0;
}
static int max2165_read_reg(struct max2165_priv *priv, u8 reg, u8 *p_data)
{
int ret;
u8 dev_addr = priv->config->i2c_address;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{ .addr = dev_addr, .flags = 0, .buf = b0, .len = 1 },
{ .addr = dev_addr, .flags = I2C_M_RD, .buf = b1, .len = 1 },
};
ret = i2c_transfer(priv->i2c, msg, 2);
if (ret != 2) {
dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg, ret);
return -EIO;
}
*p_data = b1[0];
if (debug >= 2)
dprintk("%s: reg=0x%02X, data=0x%02X\n",
__func__, reg, b1[0]);
return 0;
}
static int max2165_mask_write_reg(struct max2165_priv *priv, u8 reg,
u8 mask, u8 data)
{
int ret;
u8 v;
data &= mask;
ret = max2165_read_reg(priv, reg, &v);
if (ret != 0)
return ret;
v &= ~mask;
v |= data;
ret = max2165_write_reg(priv, reg, v);
return ret;
}
static int max2165_read_rom_table(struct max2165_priv *priv)
{
u8 dat[3];
int i;
for (i = 0; i < 3; i++) {
max2165_write_reg(priv, REG_ROM_TABLE_ADDR, i + 1);
max2165_read_reg(priv, REG_ROM_TABLE_DATA, &dat[i]);
}
priv->tf_ntch_low_cfg = dat[0] >> 4;
priv->tf_ntch_hi_cfg = dat[0] & 0x0F;
priv->tf_balun_low_ref = dat[1] & 0x0F;
priv->tf_balun_hi_ref = dat[1] >> 4;
priv->bb_filter_7mhz_cfg = dat[2] & 0x0F;
priv->bb_filter_8mhz_cfg = dat[2] >> 4;
dprintk("tf_ntch_low_cfg = 0x%X\n", priv->tf_ntch_low_cfg);
dprintk("tf_ntch_hi_cfg = 0x%X\n", priv->tf_ntch_hi_cfg);
dprintk("tf_balun_low_ref = 0x%X\n", priv->tf_balun_low_ref);
dprintk("tf_balun_hi_ref = 0x%X\n", priv->tf_balun_hi_ref);
dprintk("bb_filter_7mhz_cfg = 0x%X\n", priv->bb_filter_7mhz_cfg);
dprintk("bb_filter_8mhz_cfg = 0x%X\n", priv->bb_filter_8mhz_cfg);
return 0;
}
static int max2165_set_osc(struct max2165_priv *priv, u8 osc /*MHz*/)
{
u8 v;
v = (osc / 2);
if (v == 2)
v = 0x7;
else
v -= 8;
max2165_mask_write_reg(priv, REG_PLL_CFG, 0x07, v);
return 0;
}
static int max2165_set_bandwidth(struct max2165_priv *priv, u32 bw)
{
u8 val;
if (bw == 8000000)
val = priv->bb_filter_8mhz_cfg;
else
val = priv->bb_filter_7mhz_cfg;
max2165_mask_write_reg(priv, REG_BASEBAND_CTRL, 0xF0, val << 4);
return 0;
}
static int fixpt_div32(u32 dividend, u32 divisor, u32 *quotient, u32 *fraction)
{
u32 remainder;
u32 q, f = 0;
int i;
if (0 == divisor)
return -EINVAL;
q = dividend / divisor;
remainder = dividend - q * divisor;
for (i = 0; i < 31; i++) {
remainder <<= 1;
if (remainder >= divisor) {
f += 1;
remainder -= divisor;
}
f <<= 1;
}
*quotient = q;
*fraction = f;
return 0;
}
static int max2165_set_rf(struct max2165_priv *priv, u32 freq)
{
u8 tf;
u8 tf_ntch;
u32 t;
u32 quotient, fraction;
int ret;
/* Set PLL divider according to RF frequency */
ret = fixpt_div32(freq / 1000, priv->config->osc_clk * 1000,
&quotient, &fraction);
if (ret != 0)
return ret;
/* 20-bit fraction */
fraction >>= 12;
max2165_write_reg(priv, REG_NDIV_INT, quotient);
max2165_mask_write_reg(priv, REG_NDIV_FRAC2, 0x0F, fraction >> 16);
max2165_write_reg(priv, REG_NDIV_FRAC1, fraction >> 8);
max2165_write_reg(priv, REG_NDIV_FRAC0, fraction);
/* Norch Filter */
tf_ntch = (freq < 725000000) ?
priv->tf_ntch_low_cfg : priv->tf_ntch_hi_cfg;
/* Tracking filter balun */
t = priv->tf_balun_low_ref;
t += (priv->tf_balun_hi_ref - priv->tf_balun_low_ref)
* (freq / 1000 - 470000) / (780000 - 470000);
tf = t;
dprintk("tf = %X\n", tf);
tf |= tf_ntch << 4;
max2165_write_reg(priv, REG_TRACK_FILTER, tf);
return 0;
}
static void max2165_debug_status(struct max2165_priv *priv)
{
u8 status, autotune;
u8 auto_vco_success, auto_vco_active;
u8 pll_locked;
u8 dc_offset_low, dc_offset_hi;
u8 signal_lv_over_threshold;
u8 vco, vco_sub_band, adc;
max2165_read_reg(priv, REG_STATUS, &status);
max2165_read_reg(priv, REG_AUTOTUNE, &autotune);
auto_vco_success = (status >> 6) & 0x01;
auto_vco_active = (status >> 5) & 0x01;
pll_locked = (status >> 4) & 0x01;
dc_offset_low = (status >> 3) & 0x01;
dc_offset_hi = (status >> 2) & 0x01;
signal_lv_over_threshold = status & 0x01;
vco = autotune >> 6;
vco_sub_band = (autotune >> 3) & 0x7;
adc = autotune & 0x7;
dprintk("auto VCO active: %d, auto VCO success: %d\n",
auto_vco_active, auto_vco_success);
dprintk("PLL locked: %d\n", pll_locked);
dprintk("DC offset low: %d, DC offset high: %d\n",
dc_offset_low, dc_offset_hi);
dprintk("Signal lvl over threshold: %d\n", signal_lv_over_threshold);
dprintk("VCO: %d, VCO Sub-band: %d, ADC: %d\n", vco, vco_sub_band, adc);
}
static int max2165_set_params(struct dvb_frontend *fe)
{
struct max2165_priv *priv = fe->tuner_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
switch (c->bandwidth_hz) {
case 7000000:
case 8000000:
priv->frequency = c->frequency;
break;
default:
printk(KERN_INFO "MAX2165: bandwidth %d Hz not supported.\n",
c->bandwidth_hz);
return -EINVAL;
}
dprintk("%s() frequency=%d\n", __func__, c->frequency);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
max2165_set_bandwidth(priv, c->bandwidth_hz);
ret = max2165_set_rf(priv, priv->frequency);
mdelay(50);
max2165_debug_status(priv);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
if (ret != 0)
return -EREMOTEIO;
return 0;
}
static int max2165_get_frequency(struct dvb_frontend *fe, u32 *freq)
{
struct max2165_priv *priv = fe->tuner_priv;
dprintk("%s()\n", __func__);
*freq = priv->frequency;
return 0;
}
static int max2165_get_bandwidth(struct dvb_frontend *fe, u32 *bw)
{
struct max2165_priv *priv = fe->tuner_priv;
dprintk("%s()\n", __func__);
*bw = priv->bandwidth;
return 0;
}
static int max2165_get_status(struct dvb_frontend *fe, u32 *status)
{
struct max2165_priv *priv = fe->tuner_priv;
u16 lock_status = 0;
dprintk("%s()\n", __func__);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
max2165_debug_status(priv);
*status = lock_status;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return 0;
}
static int max2165_sleep(struct dvb_frontend *fe)
{
dprintk("%s()\n", __func__);
return 0;
}
static int max2165_init(struct dvb_frontend *fe)
{
struct max2165_priv *priv = fe->tuner_priv;
dprintk("%s()\n", __func__);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
/* Setup initial values */
/* Fractional Mode on */
max2165_write_reg(priv, REG_NDIV_FRAC2, 0x18);
/* LNA on */
max2165_write_reg(priv, REG_LNA, 0x01);
max2165_write_reg(priv, REG_PLL_CFG, 0x7A);
max2165_write_reg(priv, REG_TEST, 0x08);
max2165_write_reg(priv, REG_SHUTDOWN, 0x40);
max2165_write_reg(priv, REG_VCO_CTRL, 0x84);
max2165_write_reg(priv, REG_BASEBAND_CTRL, 0xC3);
max2165_write_reg(priv, REG_DC_OFFSET_CTRL, 0x75);
max2165_write_reg(priv, REG_DC_OFFSET_DAC, 0x00);
max2165_write_reg(priv, REG_ROM_TABLE_ADDR, 0x00);
max2165_set_osc(priv, priv->config->osc_clk);
max2165_read_rom_table(priv);
max2165_set_bandwidth(priv, 8000000);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return 0;
}
static int max2165_release(struct dvb_frontend *fe)
{
struct max2165_priv *priv = fe->tuner_priv;
dprintk("%s()\n", __func__);
kfree(priv);
fe->tuner_priv = NULL;
return 0;
}
static const struct dvb_tuner_ops max2165_tuner_ops = {
.info = {
.name = "Maxim MAX2165",
.frequency_min = 470000000,
.frequency_max = 780000000,
.frequency_step = 50000,
},
.release = max2165_release,
.init = max2165_init,
.sleep = max2165_sleep,
.set_params = max2165_set_params,
.set_analog_params = NULL,
.get_frequency = max2165_get_frequency,
.get_bandwidth = max2165_get_bandwidth,
.get_status = max2165_get_status
};
struct dvb_frontend *max2165_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
struct max2165_config *cfg)
{
struct max2165_priv *priv = NULL;
dprintk("%s(%d-%04x)\n", __func__,
i2c ? i2c_adapter_id(i2c) : -1,
cfg ? cfg->i2c_address : -1);
priv = kzalloc(sizeof(struct max2165_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
memcpy(&fe->ops.tuner_ops, &max2165_tuner_ops,
sizeof(struct dvb_tuner_ops));
priv->config = cfg;
priv->i2c = i2c;
fe->tuner_priv = priv;
max2165_init(fe);
max2165_debug_status(priv);
return fe;
}
EXPORT_SYMBOL(max2165_attach);
MODULE_AUTHOR("David T. L. Wong <davidtlwong@gmail.com>");
MODULE_DESCRIPTION("Maxim MAX2165 silicon tuner driver");
MODULE_LICENSE("GPL");

49
drivers/media/tuners/max2165.h Normal file
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/*
* Driver for Maxim MAX2165 silicon tuner
*
* Copyright (c) 2009 David T. L. Wong <davidtlwong@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MAX2165_H__
#define __MAX2165_H__
#include <linux/kconfig.h>
struct dvb_frontend;
struct i2c_adapter;
struct max2165_config {
u8 i2c_address;
u8 osc_clk; /* in MHz, selectable values: 4,16,18,20,22,24,26,28 */
};
#if IS_ENABLED(CONFIG_MEDIA_TUNER_MAX2165)
extern struct dvb_frontend *max2165_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
struct max2165_config *cfg);
#else
static inline struct dvb_frontend *max2165_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
struct max2165_config *cfg)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif

60
drivers/media/tuners/max2165_priv.h Normal file
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/*
* Driver for Maxim MAX2165 silicon tuner
*
* Copyright (c) 2009 David T. L. Wong <davidtlwong@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MAX2165_PRIV_H__
#define __MAX2165_PRIV_H__
#define REG_NDIV_INT 0x00
#define REG_NDIV_FRAC2 0x01
#define REG_NDIV_FRAC1 0x02
#define REG_NDIV_FRAC0 0x03
#define REG_TRACK_FILTER 0x04
#define REG_LNA 0x05
#define REG_PLL_CFG 0x06
#define REG_TEST 0x07
#define REG_SHUTDOWN 0x08
#define REG_VCO_CTRL 0x09
#define REG_BASEBAND_CTRL 0x0A
#define REG_DC_OFFSET_CTRL 0x0B
#define REG_DC_OFFSET_DAC 0x0C
#define REG_ROM_TABLE_ADDR 0x0D
/* Read Only Registers */
#define REG_ROM_TABLE_DATA 0x10
#define REG_STATUS 0x11
#define REG_AUTOTUNE 0x12
struct max2165_priv {
struct max2165_config *config;
struct i2c_adapter *i2c;
u32 frequency;
u32 bandwidth;
u8 tf_ntch_low_cfg;
u8 tf_ntch_hi_cfg;
u8 tf_balun_low_ref;
u8 tf_balun_hi_ref;
u8 bb_filter_7mhz_cfg;
u8 bb_filter_8mhz_cfg;
};
#endif

379
drivers/media/tuners/mc44s803.c Normal file
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/*
* Driver for Freescale MC44S803 Low Power CMOS Broadband Tuner
*
* Copyright (c) 2009 Jochen Friedrich <jochen@scram.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/dvb/frontend.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include "dvb_frontend.h"
#include "mc44s803.h"
#include "mc44s803_priv.h"
#define mc_printk(level, format, arg...) \
printk(level "mc44s803: " format , ## arg)
/* Writes a single register */
static int mc44s803_writereg(struct mc44s803_priv *priv, u32 val)
{
u8 buf[3];
struct i2c_msg msg = {
.addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 3
};
buf[0] = (val & 0xff0000) >> 16;
buf[1] = (val & 0xff00) >> 8;
buf[2] = (val & 0xff);
if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
mc_printk(KERN_WARNING, "I2C write failed\n");
return -EREMOTEIO;
}
return 0;
}
/* Reads a single register */
static int mc44s803_readreg(struct mc44s803_priv *priv, u8 reg, u32 *val)
{
u32 wval;
u8 buf[3];
int ret;
struct i2c_msg msg[] = {
{ .addr = priv->cfg->i2c_address, .flags = I2C_M_RD,
.buf = buf, .len = 3 },
};
wval = MC44S803_REG_SM(MC44S803_REG_DATAREG, MC44S803_ADDR) |
MC44S803_REG_SM(reg, MC44S803_D);
ret = mc44s803_writereg(priv, wval);
if (ret)
return ret;
if (i2c_transfer(priv->i2c, msg, 1) != 1) {
mc_printk(KERN_WARNING, "I2C read failed\n");
return -EREMOTEIO;
}
*val = (buf[0] << 16) | (buf[1] << 8) | buf[2];
return 0;
}
static int mc44s803_release(struct dvb_frontend *fe)
{
struct mc44s803_priv *priv = fe->tuner_priv;
fe->tuner_priv = NULL;
kfree(priv);
return 0;
}
static int mc44s803_init(struct dvb_frontend *fe)
{
struct mc44s803_priv *priv = fe->tuner_priv;
u32 val;
int err;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
/* Reset chip */
val = MC44S803_REG_SM(MC44S803_REG_RESET, MC44S803_ADDR) |
MC44S803_REG_SM(1, MC44S803_RS);
err = mc44s803_writereg(priv, val);
if (err)
goto exit;
val = MC44S803_REG_SM(MC44S803_REG_RESET, MC44S803_ADDR);
err = mc44s803_writereg(priv, val);
if (err)
goto exit;
/* Power Up and Start Osc */
val = MC44S803_REG_SM(MC44S803_REG_REFOSC, MC44S803_ADDR) |
MC44S803_REG_SM(0xC0, MC44S803_REFOSC) |
MC44S803_REG_SM(1, MC44S803_OSCSEL);
err = mc44s803_writereg(priv, val);
if (err)
goto exit;
val = MC44S803_REG_SM(MC44S803_REG_POWER, MC44S803_ADDR) |
MC44S803_REG_SM(0x200, MC44S803_POWER);
err = mc44s803_writereg(priv, val);
if (err)
goto exit;
msleep(10);
val = MC44S803_REG_SM(MC44S803_REG_REFOSC, MC44S803_ADDR) |
MC44S803_REG_SM(0x40, MC44S803_REFOSC) |
MC44S803_REG_SM(1, MC44S803_OSCSEL);
err = mc44s803_writereg(priv, val);
if (err)
goto exit;
msleep(20);
/* Setup Mixer */
val = MC44S803_REG_SM(MC44S803_REG_MIXER, MC44S803_ADDR) |
MC44S803_REG_SM(1, MC44S803_TRI_STATE) |
MC44S803_REG_SM(0x7F, MC44S803_MIXER_RES);
err = mc44s803_writereg(priv, val);
if (err)
goto exit;
/* Setup Cirquit Adjust */
val = MC44S803_REG_SM(MC44S803_REG_CIRCADJ, MC44S803_ADDR) |
MC44S803_REG_SM(1, MC44S803_G1) |
MC44S803_REG_SM(1, MC44S803_G3) |
MC44S803_REG_SM(0x3, MC44S803_CIRCADJ_RES) |
MC44S803_REG_SM(1, MC44S803_G6) |
MC44S803_REG_SM(priv->cfg->dig_out, MC44S803_S1) |
MC44S803_REG_SM(0x3, MC44S803_LP) |
MC44S803_REG_SM(1, MC44S803_CLRF) |
MC44S803_REG_SM(1, MC44S803_CLIF);
err = mc44s803_writereg(priv, val);
if (err)
goto exit;
val = MC44S803_REG_SM(MC44S803_REG_CIRCADJ, MC44S803_ADDR) |
MC44S803_REG_SM(1, MC44S803_G1) |
MC44S803_REG_SM(1, MC44S803_G3) |
MC44S803_REG_SM(0x3, MC44S803_CIRCADJ_RES) |
MC44S803_REG_SM(1, MC44S803_G6) |
MC44S803_REG_SM(priv->cfg->dig_out, MC44S803_S1) |
MC44S803_REG_SM(0x3, MC44S803_LP);
err = mc44s803_writereg(priv, val);
if (err)
goto exit;
/* Setup Digtune */
val = MC44S803_REG_SM(MC44S803_REG_DIGTUNE, MC44S803_ADDR) |
MC44S803_REG_SM(3, MC44S803_XOD);
err = mc44s803_writereg(priv, val);
if (err)
goto exit;
/* Setup AGC */
val = MC44S803_REG_SM(MC44S803_REG_LNAAGC, MC44S803_ADDR) |
MC44S803_REG_SM(1, MC44S803_AT1) |
MC44S803_REG_SM(1, MC44S803_AT2) |
MC44S803_REG_SM(1, MC44S803_AGC_AN_DIG) |
MC44S803_REG_SM(1, MC44S803_AGC_READ_EN) |
MC44S803_REG_SM(1, MC44S803_LNA0);
err = mc44s803_writereg(priv, val);
if (err)
goto exit;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return 0;
exit:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
mc_printk(KERN_WARNING, "I/O Error\n");
return err;
}
static int mc44s803_set_params(struct dvb_frontend *fe)
{
struct mc44s803_priv *priv = fe->tuner_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u32 r1, r2, n1, n2, lo1, lo2, freq, val;
int err;
priv->frequency = c->frequency;
r1 = MC44S803_OSC / 1000000;
r2 = MC44S803_OSC / 100000;
n1 = (c->frequency + MC44S803_IF1 + 500000) / 1000000;
freq = MC44S803_OSC / r1 * n1;
lo1 = ((60 * n1) + (r1 / 2)) / r1;
freq = freq - c->frequency;
n2 = (freq - MC44S803_IF2 + 50000) / 100000;
lo2 = ((60 * n2) + (r2 / 2)) / r2;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
val = MC44S803_REG_SM(MC44S803_REG_REFDIV, MC44S803_ADDR) |
MC44S803_REG_SM(r1-1, MC44S803_R1) |
MC44S803_REG_SM(r2-1, MC44S803_R2) |
MC44S803_REG_SM(1, MC44S803_REFBUF_EN);
err = mc44s803_writereg(priv, val);
if (err)
goto exit;
val = MC44S803_REG_SM(MC44S803_REG_LO1, MC44S803_ADDR) |
MC44S803_REG_SM(n1-2, MC44S803_LO1);
err = mc44s803_writereg(priv, val);
if (err)
goto exit;
val = MC44S803_REG_SM(MC44S803_REG_LO2, MC44S803_ADDR) |
MC44S803_REG_SM(n2-2, MC44S803_LO2);
err = mc44s803_writereg(priv, val);
if (err)
goto exit;
val = MC44S803_REG_SM(MC44S803_REG_DIGTUNE, MC44S803_ADDR) |
MC44S803_REG_SM(1, MC44S803_DA) |
MC44S803_REG_SM(lo1, MC44S803_LO_REF) |
MC44S803_REG_SM(1, MC44S803_AT);
err = mc44s803_writereg(priv, val);
if (err)
goto exit;
val = MC44S803_REG_SM(MC44S803_REG_DIGTUNE, MC44S803_ADDR) |
MC44S803_REG_SM(2, MC44S803_DA) |
MC44S803_REG_SM(lo2, MC44S803_LO_REF) |
MC44S803_REG_SM(1, MC44S803_AT);
err = mc44s803_writereg(priv, val);
if (err)
goto exit;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return 0;
exit:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
mc_printk(KERN_WARNING, "I/O Error\n");
return err;
}
static int mc44s803_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct mc44s803_priv *priv = fe->tuner_priv;
*frequency = priv->frequency;
return 0;
}
static int mc44s803_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
*frequency = MC44S803_IF2; /* 36.125 MHz */
return 0;
}
static const struct dvb_tuner_ops mc44s803_tuner_ops = {
.info = {
.name = "Freescale MC44S803",
.frequency_min = 48000000,
.frequency_max = 1000000000,
.frequency_step = 100000,
},
.release = mc44s803_release,
.init = mc44s803_init,
.set_params = mc44s803_set_params,
.get_frequency = mc44s803_get_frequency,
.get_if_frequency = mc44s803_get_if_frequency,
};
/* This functions tries to identify a MC44S803 tuner by reading the ID
register. This is hasty. */
struct dvb_frontend *mc44s803_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, struct mc44s803_config *cfg)
{
struct mc44s803_priv *priv;
u32 reg;
u8 id;
int ret;
reg = 0;
priv = kzalloc(sizeof(struct mc44s803_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->cfg = cfg;
priv->i2c = i2c;
priv->fe = fe;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
ret = mc44s803_readreg(priv, MC44S803_REG_ID, &reg);
if (ret)
goto error;
id = MC44S803_REG_MS(reg, MC44S803_ID);
if (id != 0x14) {
mc_printk(KERN_ERR, "unsupported ID "
"(%x should be 0x14)\n", id);
goto error;
}
mc_printk(KERN_INFO, "successfully identified (ID = %x)\n", id);
memcpy(&fe->ops.tuner_ops, &mc44s803_tuner_ops,
sizeof(struct dvb_tuner_ops));
fe->tuner_priv = priv;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
return fe;
error:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
kfree(priv);
return NULL;
}
EXPORT_SYMBOL(mc44s803_attach);
MODULE_AUTHOR("Jochen Friedrich");
MODULE_DESCRIPTION("Freescale MC44S803 silicon tuner driver");
MODULE_LICENSE("GPL");

47
drivers/media/tuners/mc44s803.h Normal file
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@ -0,0 +1,47 @@
/*
* Driver for Freescale MC44S803 Low Power CMOS Broadband Tuner
*
* Copyright (c) 2009 Jochen Friedrich <jochen@scram.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
*/
#ifndef MC44S803_H
#define MC44S803_H
#include <linux/kconfig.h>
struct dvb_frontend;
struct i2c_adapter;
struct mc44s803_config {
u8 i2c_address;
u8 dig_out;
};
#if IS_ENABLED(CONFIG_MEDIA_TUNER_MC44S803)
extern struct dvb_frontend *mc44s803_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, struct mc44s803_config *cfg);
#else
static inline struct dvb_frontend *mc44s803_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, struct mc44s803_config *cfg)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif /* CONFIG_MEDIA_TUNER_MC44S803 */
#endif

208
drivers/media/tuners/mc44s803_priv.h Normal file
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/*
* Driver for Freescale MC44S803 Low Power CMOS Broadband Tuner
*
* Copyright (c) 2009 Jochen Friedrich <jochen@scram.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
*/
#ifndef MC44S803_PRIV_H
#define MC44S803_PRIV_H
/* This driver is based on the information available in the datasheet
http://www.freescale.com/files/rf_if/doc/data_sheet/MC44S803.pdf
SPI or I2C Address : 0xc0-0xc6
Reg.No | Function
-------------------------------------------
00 | Power Down
01 | Reference Oszillator
02 | Reference Dividers
03 | Mixer and Reference Buffer
04 | Reset/Serial Out
05 | LO 1
06 | LO 2
07 | Circuit Adjust
08 | Test
09 | Digital Tune
0A | LNA AGC
0B | Data Register Address
0C | Regulator Test
0D | VCO Test
0E | LNA Gain/Input Power
0F | ID Bits
*/
#define MC44S803_OSC 26000000 /* 26 MHz */
#define MC44S803_IF1 1086000000 /* 1086 MHz */
#define MC44S803_IF2 36125000 /* 36.125 MHz */
#define MC44S803_REG_POWER 0
#define MC44S803_REG_REFOSC 1
#define MC44S803_REG_REFDIV 2
#define MC44S803_REG_MIXER 3
#define MC44S803_REG_RESET 4
#define MC44S803_REG_LO1 5
#define MC44S803_REG_LO2 6
#define MC44S803_REG_CIRCADJ 7
#define MC44S803_REG_TEST 8
#define MC44S803_REG_DIGTUNE 9
#define MC44S803_REG_LNAAGC 0x0A
#define MC44S803_REG_DATAREG 0x0B
#define MC44S803_REG_REGTEST 0x0C
#define MC44S803_REG_VCOTEST 0x0D
#define MC44S803_REG_LNAGAIN 0x0E
#define MC44S803_REG_ID 0x0F
/* Register definitions */
#define MC44S803_ADDR 0x0F
#define MC44S803_ADDR_S 0
/* REG_POWER */
#define MC44S803_POWER 0xFFFFF0
#define MC44S803_POWER_S 4
/* REG_REFOSC */
#define MC44S803_REFOSC 0x1FF0
#define MC44S803_REFOSC_S 4
#define MC44S803_OSCSEL 0x2000
#define MC44S803_OSCSEL_S 13
/* REG_REFDIV */
#define MC44S803_R2 0x1FF0
#define MC44S803_R2_S 4
#define MC44S803_REFBUF_EN 0x2000
#define MC44S803_REFBUF_EN_S 13
#define MC44S803_R1 0x7C000
#define MC44S803_R1_S 14
/* REG_MIXER */
#define MC44S803_R3 0x70
#define MC44S803_R3_S 4
#define MC44S803_MUX3 0x80
#define MC44S803_MUX3_S 7
#define MC44S803_MUX4 0x100
#define MC44S803_MUX4_S 8
#define MC44S803_OSC_SCR 0x200
#define MC44S803_OSC_SCR_S 9
#define MC44S803_TRI_STATE 0x400
#define MC44S803_TRI_STATE_S 10
#define MC44S803_BUF_GAIN 0x800
#define MC44S803_BUF_GAIN_S 11
#define MC44S803_BUF_IO 0x1000
#define MC44S803_BUF_IO_S 12
#define MC44S803_MIXER_RES 0xFE000
#define MC44S803_MIXER_RES_S 13
/* REG_RESET */
#define MC44S803_RS 0x10
#define MC44S803_RS_S 4
#define MC44S803_SO 0x20
#define MC44S803_SO_S 5
/* REG_LO1 */
#define MC44S803_LO1 0xFFF0
#define MC44S803_LO1_S 4
/* REG_LO2 */
#define MC44S803_LO2 0x7FFF0
#define MC44S803_LO2_S 4
/* REG_CIRCADJ */
#define MC44S803_G1 0x20
#define MC44S803_G1_S 5
#define MC44S803_G3 0x80
#define MC44S803_G3_S 7
#define MC44S803_CIRCADJ_RES 0x300
#define MC44S803_CIRCADJ_RES_S 8
#define MC44S803_G6 0x400
#define MC44S803_G6_S 10
#define MC44S803_G7 0x800
#define MC44S803_G7_S 11
#define MC44S803_S1 0x1000
#define MC44S803_S1_S 12
#define MC44S803_LP 0x7E000
#define MC44S803_LP_S 13
#define MC44S803_CLRF 0x80000
#define MC44S803_CLRF_S 19
#define MC44S803_CLIF 0x100000
#define MC44S803_CLIF_S 20
/* REG_TEST */
/* REG_DIGTUNE */
#define MC44S803_DA 0xF0
#define MC44S803_DA_S 4
#define MC44S803_XOD 0x300
#define MC44S803_XOD_S 8
#define MC44S803_RST 0x10000
#define MC44S803_RST_S 16
#define MC44S803_LO_REF 0x1FFF00
#define MC44S803_LO_REF_S 8
#define MC44S803_AT 0x200000
#define MC44S803_AT_S 21
#define MC44S803_MT 0x400000
#define MC44S803_MT_S 22
/* REG_LNAAGC */
#define MC44S803_G 0x3F0
#define MC44S803_G_S 4
#define MC44S803_AT1 0x400
#define MC44S803_AT1_S 10
#define MC44S803_AT2 0x800
#define MC44S803_AT2_S 11
#define MC44S803_HL_GR_EN 0x8000
#define MC44S803_HL_GR_EN_S 15
#define MC44S803_AGC_AN_DIG 0x10000
#define MC44S803_AGC_AN_DIG_S 16
#define MC44S803_ATTEN_EN 0x20000
#define MC44S803_ATTEN_EN_S 17
#define MC44S803_AGC_READ_EN 0x40000
#define MC44S803_AGC_READ_EN_S 18
#define MC44S803_LNA0 0x80000
#define MC44S803_LNA0_S 19
#define MC44S803_AGC_SEL 0x100000
#define MC44S803_AGC_SEL_S 20
#define MC44S803_AT0 0x200000
#define MC44S803_AT0_S 21
#define MC44S803_B 0xC00000
#define MC44S803_B_S 22
/* REG_DATAREG */
#define MC44S803_D 0xF0
#define MC44S803_D_S 4
/* REG_REGTEST */
/* REG_VCOTEST */
/* REG_LNAGAIN */
#define MC44S803_IF_PWR 0x700
#define MC44S803_IF_PWR_S 8
#define MC44S803_RF_PWR 0x3800
#define MC44S803_RF_PWR_S 11
#define MC44S803_LNA_GAIN 0xFC000
#define MC44S803_LNA_GAIN_S 14
/* REG_ID */
#define MC44S803_ID 0x3E00
#define MC44S803_ID_S 9
/* Some macros to read/write fields */
/* First shift, then mask */
#define MC44S803_REG_SM(_val, _reg) \
(((_val) << _reg##_S) & (_reg))
/* First mask, then shift */
#define MC44S803_REG_MS(_val, _reg) \
(((_val) & (_reg)) >> _reg##_S)
struct mc44s803_priv {
struct mc44s803_config *cfg;
struct i2c_adapter *i2c;
struct dvb_frontend *fe;
u32 frequency;
};
#endif

506
drivers/media/tuners/msi001.c Normal file
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/*
* Mirics MSi001 silicon tuner driver
*
* Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
* Copyright (C) 2014 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/gcd.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
static const struct v4l2_frequency_band bands[] = {
{
.type = V4L2_TUNER_RF,
.index = 0,
.capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
.rangelow = 49000000,
.rangehigh = 263000000,
}, {
.type = V4L2_TUNER_RF,
.index = 1,
.capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
.rangelow = 390000000,
.rangehigh = 960000000,
},
};
struct msi001 {
struct spi_device *spi;
struct v4l2_subdev sd;
/* Controls */
struct v4l2_ctrl_handler hdl;
struct v4l2_ctrl *bandwidth_auto;
struct v4l2_ctrl *bandwidth;
struct v4l2_ctrl *lna_gain;
struct v4l2_ctrl *mixer_gain;
struct v4l2_ctrl *if_gain;
unsigned int f_tuner;
};
static inline struct msi001 *sd_to_msi001(struct v4l2_subdev *sd)
{
return container_of(sd, struct msi001, sd);
}
static int msi001_wreg(struct msi001 *s, u32 data)
{
/* Register format: 4 bits addr + 20 bits value */
return spi_write(s->spi, &data, 3);
};
static int msi001_set_gain(struct msi001 *s, int lna_gain, int mixer_gain,
int if_gain)
{
int ret;
u32 reg;
dev_dbg(&s->spi->dev, "lna=%d mixer=%d if=%d\n",
lna_gain, mixer_gain, if_gain);
reg = 1 << 0;
reg |= (59 - if_gain) << 4;
reg |= 0 << 10;
reg |= (1 - mixer_gain) << 12;
reg |= (1 - lna_gain) << 13;
reg |= 4 << 14;
reg |= 0 << 17;
ret = msi001_wreg(s, reg);
if (ret)
goto err;
return 0;
err:
dev_dbg(&s->spi->dev, "failed %d\n", ret);
return ret;
};
static int msi001_set_tuner(struct msi001 *s)
{
int ret, i;
unsigned int n, m, thresh, frac, vco_step, tmp, f_if1;
u32 reg;
u64 f_vco, tmp64;
u8 mode, filter_mode, lo_div;
static const struct {
u32 rf;
u8 mode;
u8 lo_div;
} band_lut[] = {
{ 50000000, 0xe1, 16}, /* AM_MODE2, antenna 2 */
{108000000, 0x42, 32}, /* VHF_MODE */
{330000000, 0x44, 16}, /* B3_MODE */
{960000000, 0x48, 4}, /* B45_MODE */
{ ~0U, 0x50, 2}, /* BL_MODE */
};
static const struct {
u32 freq;
u8 filter_mode;
} if_freq_lut[] = {
{ 0, 0x03}, /* Zero IF */
{ 450000, 0x02}, /* 450 kHz IF */
{1620000, 0x01}, /* 1.62 MHz IF */
{2048000, 0x00}, /* 2.048 MHz IF */
};
static const struct {
u32 freq;
u8 val;
} bandwidth_lut[] = {
{ 200000, 0x00}, /* 200 kHz */
{ 300000, 0x01}, /* 300 kHz */
{ 600000, 0x02}, /* 600 kHz */
{1536000, 0x03}, /* 1.536 MHz */
{5000000, 0x04}, /* 5 MHz */
{6000000, 0x05}, /* 6 MHz */
{7000000, 0x06}, /* 7 MHz */
{8000000, 0x07}, /* 8 MHz */
};
unsigned int f_rf = s->f_tuner;
/*
* bandwidth (Hz)
* 200000, 300000, 600000, 1536000, 5000000, 6000000, 7000000, 8000000
*/
unsigned int bandwidth;
/*
* intermediate frequency (Hz)
* 0, 450000, 1620000, 2048000
*/
unsigned int f_if = 0;
#define F_REF 24000000
#define R_REF 4
#define F_OUT_STEP 1
dev_dbg(&s->spi->dev, "f_rf=%d f_if=%d\n", f_rf, f_if);
for (i = 0; i < ARRAY_SIZE(band_lut); i++) {
if (f_rf <= band_lut[i].rf) {
mode = band_lut[i].mode;
lo_div = band_lut[i].lo_div;
break;
}
}
if (i == ARRAY_SIZE(band_lut)) {
ret = -EINVAL;
goto err;
}
/* AM_MODE is upconverted */
if ((mode >> 0) & 0x1)
f_if1 = 5 * F_REF;
else
f_if1 = 0;
for (i = 0; i < ARRAY_SIZE(if_freq_lut); i++) {
if (f_if == if_freq_lut[i].freq) {
filter_mode = if_freq_lut[i].filter_mode;
break;
}
}
if (i == ARRAY_SIZE(if_freq_lut)) {
ret = -EINVAL;
goto err;
}
/* filters */
bandwidth = s->bandwidth->val;
bandwidth = clamp(bandwidth, 200000U, 8000000U);
for (i = 0; i < ARRAY_SIZE(bandwidth_lut); i++) {
if (bandwidth <= bandwidth_lut[i].freq) {
bandwidth = bandwidth_lut[i].val;
break;
}
}
if (i == ARRAY_SIZE(bandwidth_lut)) {
ret = -EINVAL;
goto err;
}
s->bandwidth->val = bandwidth_lut[i].freq;
dev_dbg(&s->spi->dev, "bandwidth selected=%d\n", bandwidth_lut[i].freq);
f_vco = (u64) (f_rf + f_if + f_if1) * lo_div;
tmp64 = f_vco;
m = do_div(tmp64, F_REF * R_REF);
n = (unsigned int) tmp64;
vco_step = F_OUT_STEP * lo_div;
thresh = (F_REF * R_REF) / vco_step;
frac = 1ul * thresh * m / (F_REF * R_REF);
/* Find out greatest common divisor and divide to smaller. */
tmp = gcd(thresh, frac);
thresh /= tmp;
frac /= tmp;
/* Force divide to reg max. Resolution will be reduced. */
tmp = DIV_ROUND_UP(thresh, 4095);
thresh = DIV_ROUND_CLOSEST(thresh, tmp);
frac = DIV_ROUND_CLOSEST(frac, tmp);
/* calc real RF set */
tmp = 1ul * F_REF * R_REF * n;
tmp += 1ul * F_REF * R_REF * frac / thresh;
tmp /= lo_div;
dev_dbg(&s->spi->dev, "rf=%u:%u n=%d thresh=%d frac=%d\n",
f_rf, tmp, n, thresh, frac);
ret = msi001_wreg(s, 0x00000e);
if (ret)
goto err;
ret = msi001_wreg(s, 0x000003);
if (ret)
goto err;
reg = 0 << 0;
reg |= mode << 4;
reg |= filter_mode << 12;
reg |= bandwidth << 14;
reg |= 0x02 << 17;
reg |= 0x00 << 20;
ret = msi001_wreg(s, reg);
if (ret)
goto err;
reg = 5 << 0;
reg |= thresh << 4;
reg |= 1 << 19;
reg |= 1 << 21;
ret = msi001_wreg(s, reg);
if (ret)
goto err;
reg = 2 << 0;
reg |= frac << 4;
reg |= n << 16;
ret = msi001_wreg(s, reg);
if (ret)
goto err;
ret = msi001_set_gain(s, s->lna_gain->cur.val, s->mixer_gain->cur.val,
s->if_gain->cur.val);
if (ret)
goto err;
reg = 6 << 0;
reg |= 63 << 4;
reg |= 4095 << 10;
ret = msi001_wreg(s, reg);
if (ret)
goto err;
return 0;
err:
dev_dbg(&s->spi->dev, "failed %d\n", ret);
return ret;
};
static int msi001_s_power(struct v4l2_subdev *sd, int on)
{
struct msi001 *s = sd_to_msi001(sd);
int ret;
dev_dbg(&s->spi->dev, "on=%d\n", on);
if (on)
ret = 0;
else
ret = msi001_wreg(s, 0x000000);
return ret;
}
static const struct v4l2_subdev_core_ops msi001_core_ops = {
.s_power = msi001_s_power,
};
static int msi001_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *v)
{
struct msi001 *s = sd_to_msi001(sd);
dev_dbg(&s->spi->dev, "index=%d\n", v->index);
strlcpy(v->name, "Mirics MSi001", sizeof(v->name));
v->type = V4L2_TUNER_RF;
v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
v->rangelow = 49000000;
v->rangehigh = 960000000;
return 0;
}
static int msi001_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *v)
{
struct msi001 *s = sd_to_msi001(sd);
dev_dbg(&s->spi->dev, "index=%d\n", v->index);
return 0;
}
static int msi001_g_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *f)
{
struct msi001 *s = sd_to_msi001(sd);
dev_dbg(&s->spi->dev, "tuner=%d\n", f->tuner);
f->frequency = s->f_tuner;
return 0;
}
static int msi001_s_frequency(struct v4l2_subdev *sd,
const struct v4l2_frequency *f)
{
struct msi001 *s = sd_to_msi001(sd);
unsigned int band;
dev_dbg(&s->spi->dev, "tuner=%d type=%d frequency=%u\n",
f->tuner, f->type, f->frequency);
if (f->frequency < ((bands[0].rangehigh + bands[1].rangelow) / 2))
band = 0;
else
band = 1;
s->f_tuner = clamp_t(unsigned int, f->frequency,
bands[band].rangelow, bands[band].rangehigh);
return msi001_set_tuner(s);
}
static int msi001_enum_freq_bands(struct v4l2_subdev *sd,
struct v4l2_frequency_band *band)
{
struct msi001 *s = sd_to_msi001(sd);
dev_dbg(&s->spi->dev, "tuner=%d type=%d index=%d\n",
band->tuner, band->type, band->index);
if (band->index >= ARRAY_SIZE(bands))
return -EINVAL;
band->capability = bands[band->index].capability;
band->rangelow = bands[band->index].rangelow;
band->rangehigh = bands[band->index].rangehigh;
return 0;
}
static const struct v4l2_subdev_tuner_ops msi001_tuner_ops = {
.g_tuner = msi001_g_tuner,
.s_tuner = msi001_s_tuner,
.g_frequency = msi001_g_frequency,
.s_frequency = msi001_s_frequency,
.enum_freq_bands = msi001_enum_freq_bands,
};
static const struct v4l2_subdev_ops msi001_ops = {
.core = &msi001_core_ops,
.tuner = &msi001_tuner_ops,
};
static int msi001_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct msi001 *s = container_of(ctrl->handler, struct msi001, hdl);
int ret;
dev_dbg(&s->spi->dev,
"id=%d name=%s val=%d min=%lld max=%lld step=%lld\n",
ctrl->id, ctrl->name, ctrl->val,
ctrl->minimum, ctrl->maximum, ctrl->step);
switch (ctrl->id) {
case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO:
case V4L2_CID_RF_TUNER_BANDWIDTH:
ret = msi001_set_tuner(s);
break;
case V4L2_CID_RF_TUNER_LNA_GAIN:
ret = msi001_set_gain(s, s->lna_gain->val,
s->mixer_gain->cur.val, s->if_gain->cur.val);
break;
case V4L2_CID_RF_TUNER_MIXER_GAIN:
ret = msi001_set_gain(s, s->lna_gain->cur.val,
s->mixer_gain->val, s->if_gain->cur.val);
break;
case V4L2_CID_RF_TUNER_IF_GAIN:
ret = msi001_set_gain(s, s->lna_gain->cur.val,
s->mixer_gain->cur.val, s->if_gain->val);
break;
default:
dev_dbg(&s->spi->dev, "unkown control %d\n", ctrl->id);
ret = -EINVAL;
}
return ret;
}
static const struct v4l2_ctrl_ops msi001_ctrl_ops = {
.s_ctrl = msi001_s_ctrl,
};
static int msi001_probe(struct spi_device *spi)
{
struct msi001 *s;
int ret;
dev_dbg(&spi->dev, "\n");
s = kzalloc(sizeof(struct msi001), GFP_KERNEL);
if (s == NULL) {
ret = -ENOMEM;
dev_dbg(&spi->dev, "Could not allocate memory for msi001\n");
goto err_kfree;
}
s->spi = spi;
s->f_tuner = bands[0].rangelow;
v4l2_spi_subdev_init(&s->sd, spi, &msi001_ops);
/* Register controls */
v4l2_ctrl_handler_init(&s->hdl, 5);
s->bandwidth_auto = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops,
V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1);
s->bandwidth = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops,
V4L2_CID_RF_TUNER_BANDWIDTH, 200000, 8000000, 1, 200000);
v4l2_ctrl_auto_cluster(2, &s->bandwidth_auto, 0, false);
s->lna_gain = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops,
V4L2_CID_RF_TUNER_LNA_GAIN, 0, 1, 1, 1);
s->mixer_gain = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops,
V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1);
s->if_gain = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops,
V4L2_CID_RF_TUNER_IF_GAIN, 0, 59, 1, 0);
if (s->hdl.error) {
ret = s->hdl.error;
dev_err(&s->spi->dev, "Could not initialize controls\n");
/* control init failed, free handler */
goto err_ctrl_handler_free;
}
s->sd.ctrl_handler = &s->hdl;
return 0;
err_ctrl_handler_free:
v4l2_ctrl_handler_free(&s->hdl);
err_kfree:
kfree(s);
return ret;
}
static int msi001_remove(struct spi_device *spi)
{
struct v4l2_subdev *sd = spi_get_drvdata(spi);
struct msi001 *s = sd_to_msi001(sd);
dev_dbg(&spi->dev, "\n");
/*
* Registered by v4l2_spi_new_subdev() from master driver, but we must
* unregister it from here. Weird.
*/
v4l2_device_unregister_subdev(&s->sd);
v4l2_ctrl_handler_free(&s->hdl);
kfree(s);
return 0;
}
static const struct spi_device_id msi001_id[] = {
{"msi001", 0},
{}
};
MODULE_DEVICE_TABLE(spi, msi001_id);
static struct spi_driver msi001_driver = {
.driver = {
.name = "msi001",
.owner = THIS_MODULE,
},
.probe = msi001_probe,
.remove = msi001_remove,
.id_table = msi001_id,
};
module_spi_driver(msi001_driver);
MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
MODULE_DESCRIPTION("Mirics MSi001");
MODULE_LICENSE("GPL");

402
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/*
* Driver for Microtune MT2060 "Single chip dual conversion broadband tuner"
*
* Copyright (c) 2006 Olivier DANET <odanet@caramail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
*/
/* In that file, frequencies are expressed in kiloHertz to avoid 32 bits overflows */
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/dvb/frontend.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include "dvb_frontend.h"
#include "mt2060.h"
#include "mt2060_priv.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
#define dprintk(args...) do { if (debug) {printk(KERN_DEBUG "MT2060: " args); printk("\n"); }} while (0)
// Reads a single register
static int mt2060_readreg(struct mt2060_priv *priv, u8 reg, u8 *val)
{
struct i2c_msg msg[2] = {
{ .addr = priv->cfg->i2c_address, .flags = 0, .buf = &reg, .len = 1 },
{ .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, .buf = val, .len = 1 },
};
if (i2c_transfer(priv->i2c, msg, 2) != 2) {
printk(KERN_WARNING "mt2060 I2C read failed\n");
return -EREMOTEIO;
}
return 0;
}
// Writes a single register
static int mt2060_writereg(struct mt2060_priv *priv, u8 reg, u8 val)
{
u8 buf[2] = { reg, val };
struct i2c_msg msg = {
.addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2
};
if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
printk(KERN_WARNING "mt2060 I2C write failed\n");
return -EREMOTEIO;
}
return 0;
}
// Writes a set of consecutive registers
static int mt2060_writeregs(struct mt2060_priv *priv,u8 *buf, u8 len)
{
struct i2c_msg msg = {
.addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = len
};
if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
printk(KERN_WARNING "mt2060 I2C write failed (len=%i)\n",(int)len);
return -EREMOTEIO;
}
return 0;
}
// Initialisation sequences
// LNABAND=3, NUM1=0x3C, DIV1=0x74, NUM2=0x1080, DIV2=0x49
static u8 mt2060_config1[] = {
REG_LO1C1,
0x3F, 0x74, 0x00, 0x08, 0x93
};
// FMCG=2, GP2=0, GP1=0
static u8 mt2060_config2[] = {
REG_MISC_CTRL,
0x20, 0x1E, 0x30, 0xff, 0x80, 0xff, 0x00, 0x2c, 0x42
};
// VGAG=3, V1CSE=1
#ifdef MT2060_SPURCHECK
/* The function below calculates the frequency offset between the output frequency if2
and the closer cross modulation subcarrier between lo1 and lo2 up to the tenth harmonic */
static int mt2060_spurcalc(u32 lo1,u32 lo2,u32 if2)
{
int I,J;
int dia,diamin,diff;
diamin=1000000;
for (I = 1; I < 10; I++) {
J = ((2*I*lo1)/lo2+1)/2;
diff = I*(int)lo1-J*(int)lo2;
if (diff < 0) diff=-diff;
dia = (diff-(int)if2);
if (dia < 0) dia=-dia;
if (diamin > dia) diamin=dia;
}
return diamin;
}
#define BANDWIDTH 4000 // kHz
/* Calculates the frequency offset to add to avoid spurs. Returns 0 if no offset is needed */
static int mt2060_spurcheck(u32 lo1,u32 lo2,u32 if2)
{
u32 Spur,Sp1,Sp2;
int I,J;
I=0;
J=1000;
Spur=mt2060_spurcalc(lo1,lo2,if2);
if (Spur < BANDWIDTH) {
/* Potential spurs detected */
dprintk("Spurs before : f_lo1: %d f_lo2: %d (kHz)",
(int)lo1,(int)lo2);
I=1000;
Sp1 = mt2060_spurcalc(lo1+I,lo2+I,if2);
Sp2 = mt2060_spurcalc(lo1-I,lo2-I,if2);
if (Sp1 < Sp2) {
J=-J; I=-I; Spur=Sp2;
} else
Spur=Sp1;
while (Spur < BANDWIDTH) {
I += J;
Spur = mt2060_spurcalc(lo1+I,lo2+I,if2);
}
dprintk("Spurs after : f_lo1: %d f_lo2: %d (kHz)",
(int)(lo1+I),(int)(lo2+I));
}
return I;
}
#endif
#define IF2 36150 // IF2 frequency = 36.150 MHz
#define FREF 16000 // Quartz oscillator 16 MHz
static int mt2060_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct mt2060_priv *priv;
int i=0;
u32 freq;
u8 lnaband;
u32 f_lo1,f_lo2;
u32 div1,num1,div2,num2;
u8 b[8];
u32 if1;
priv = fe->tuner_priv;
if1 = priv->if1_freq;
b[0] = REG_LO1B1;
b[1] = 0xFF;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
mt2060_writeregs(priv,b,2);
freq = c->frequency / 1000; /* Hz -> kHz */
f_lo1 = freq + if1 * 1000;
f_lo1 = (f_lo1 / 250) * 250;
f_lo2 = f_lo1 - freq - IF2;
// From the Comtech datasheet, the step used is 50kHz. The tuner chip could be more precise
f_lo2 = ((f_lo2 + 25) / 50) * 50;
priv->frequency = (f_lo1 - f_lo2 - IF2) * 1000,
#ifdef MT2060_SPURCHECK
// LO-related spurs detection and correction
num1 = mt2060_spurcheck(f_lo1,f_lo2,IF2);
f_lo1 += num1;
f_lo2 += num1;
#endif
//Frequency LO1 = 16MHz * (DIV1 + NUM1/64 )
num1 = f_lo1 / (FREF / 64);
div1 = num1 / 64;
num1 &= 0x3f;
// Frequency LO2 = 16MHz * (DIV2 + NUM2/8192 )
num2 = f_lo2 * 64 / (FREF / 128);
div2 = num2 / 8192;
num2 &= 0x1fff;
if (freq <= 95000) lnaband = 0xB0; else
if (freq <= 180000) lnaband = 0xA0; else
if (freq <= 260000) lnaband = 0x90; else
if (freq <= 335000) lnaband = 0x80; else
if (freq <= 425000) lnaband = 0x70; else
if (freq <= 480000) lnaband = 0x60; else
if (freq <= 570000) lnaband = 0x50; else
if (freq <= 645000) lnaband = 0x40; else
if (freq <= 730000) lnaband = 0x30; else
if (freq <= 810000) lnaband = 0x20; else lnaband = 0x10;
b[0] = REG_LO1C1;
b[1] = lnaband | ((num1 >>2) & 0x0F);
b[2] = div1;
b[3] = (num2 & 0x0F) | ((num1 & 3) << 4);
b[4] = num2 >> 4;
b[5] = ((num2 >>12) & 1) | (div2 << 1);
dprintk("IF1: %dMHz",(int)if1);
dprintk("PLL freq=%dkHz f_lo1=%dkHz f_lo2=%dkHz",(int)freq,(int)f_lo1,(int)f_lo2);
dprintk("PLL div1=%d num1=%d div2=%d num2=%d",(int)div1,(int)num1,(int)div2,(int)num2);
dprintk("PLL [1..5]: %2x %2x %2x %2x %2x",(int)b[1],(int)b[2],(int)b[3],(int)b[4],(int)b[5]);
mt2060_writeregs(priv,b,6);
//Waits for pll lock or timeout
i = 0;
do {
mt2060_readreg(priv,REG_LO_STATUS,b);
if ((b[0] & 0x88)==0x88)
break;
msleep(4);
i++;
} while (i<10);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
return 0;
}
static void mt2060_calibrate(struct mt2060_priv *priv)
{
u8 b = 0;
int i = 0;
if (mt2060_writeregs(priv,mt2060_config1,sizeof(mt2060_config1)))
return;
if (mt2060_writeregs(priv,mt2060_config2,sizeof(mt2060_config2)))
return;
/* initialize the clock output */
mt2060_writereg(priv, REG_VGAG, (priv->cfg->clock_out << 6) | 0x30);
do {
b |= (1 << 6); // FM1SS;
mt2060_writereg(priv, REG_LO2C1,b);
msleep(20);
if (i == 0) {
b |= (1 << 7); // FM1CA;
mt2060_writereg(priv, REG_LO2C1,b);
b &= ~(1 << 7); // FM1CA;
msleep(20);
}
b &= ~(1 << 6); // FM1SS
mt2060_writereg(priv, REG_LO2C1,b);
msleep(20);
i++;
} while (i < 9);
i = 0;
while (i++ < 10 && mt2060_readreg(priv, REG_MISC_STAT, &b) == 0 && (b & (1 << 6)) == 0)
msleep(20);
if (i <= 10) {
mt2060_readreg(priv, REG_FM_FREQ, &priv->fmfreq); // now find out, what is fmreq used for :)
dprintk("calibration was successful: %d", (int)priv->fmfreq);
} else
dprintk("FMCAL timed out");
}
static int mt2060_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct mt2060_priv *priv = fe->tuner_priv;
*frequency = priv->frequency;
return 0;
}
static int mt2060_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
*frequency = IF2 * 1000;
return 0;
}
static int mt2060_init(struct dvb_frontend *fe)
{
struct mt2060_priv *priv = fe->tuner_priv;
int ret;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
ret = mt2060_writereg(priv, REG_VGAG,
(priv->cfg->clock_out << 6) | 0x33);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
return ret;
}
static int mt2060_sleep(struct dvb_frontend *fe)
{
struct mt2060_priv *priv = fe->tuner_priv;
int ret;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
ret = mt2060_writereg(priv, REG_VGAG,
(priv->cfg->clock_out << 6) | 0x30);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
return ret;
}
static int mt2060_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
return 0;
}
static const struct dvb_tuner_ops mt2060_tuner_ops = {
.info = {
.name = "Microtune MT2060",
.frequency_min = 48000000,
.frequency_max = 860000000,
.frequency_step = 50000,
},
.release = mt2060_release,
.init = mt2060_init,
.sleep = mt2060_sleep,
.set_params = mt2060_set_params,
.get_frequency = mt2060_get_frequency,
.get_if_frequency = mt2060_get_if_frequency,
};
/* This functions tries to identify a MT2060 tuner by reading the PART/REV register. This is hasty. */
struct dvb_frontend * mt2060_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2060_config *cfg, u16 if1)
{
struct mt2060_priv *priv = NULL;
u8 id = 0;
priv = kzalloc(sizeof(struct mt2060_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->cfg = cfg;
priv->i2c = i2c;
priv->if1_freq = if1;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
if (mt2060_readreg(priv,REG_PART_REV,&id) != 0) {
kfree(priv);
return NULL;
}
if (id != PART_REV) {
kfree(priv);
return NULL;
}
printk(KERN_INFO "MT2060: successfully identified (IF1 = %d)\n", if1);
memcpy(&fe->ops.tuner_ops, &mt2060_tuner_ops, sizeof(struct dvb_tuner_ops));
fe->tuner_priv = priv;
mt2060_calibrate(priv);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
return fe;
}
EXPORT_SYMBOL(mt2060_attach);
MODULE_AUTHOR("Olivier DANET");
MODULE_DESCRIPTION("Microtune MT2060 silicon tuner driver");
MODULE_LICENSE("GPL");

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/*
* Driver for Microtune MT2060 "Single chip dual conversion broadband tuner"
*
* Copyright (c) 2006 Olivier DANET <odanet@caramail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
*/
#ifndef MT2060_H
#define MT2060_H
struct dvb_frontend;
struct i2c_adapter;
struct mt2060_config {
u8 i2c_address;
u8 clock_out; /* 0 = off, 1 = CLK/4, 2 = CLK/2, 3 = CLK/1 */
};
#if IS_ENABLED(CONFIG_MEDIA_TUNER_MT2060)
extern struct dvb_frontend * mt2060_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2060_config *cfg, u16 if1);
#else
static inline struct dvb_frontend * mt2060_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2060_config *cfg, u16 if1)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif // CONFIG_MEDIA_TUNER_MT2060
#endif

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/*
* Driver for Microtune MT2060 "Single chip dual conversion broadband tuner"
*
* Copyright (c) 2006 Olivier DANET <odanet@caramail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
*/
#ifndef MT2060_PRIV_H
#define MT2060_PRIV_H
// Uncomment the #define below to enable spurs checking. The results where quite unconvincing.
// #define MT2060_SPURCHECK
/* This driver is based on the information available in the datasheet of the
"Comtech SDVBT-3K6M" tuner ( K1000737843.pdf ) which features the MT2060 register map :
I2C Address : 0x60
Reg.No | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | ( defaults )
--------------------------------------------------------------------------------
00 | [ PART ] | [ REV ] | R = 0x63
01 | [ LNABAND ] | [ NUM1(5:2) ] | RW = 0x3F
02 | [ DIV1 ] | RW = 0x74
03 | FM1CA | FM1SS | [ NUM1(1:0) ] | [ NUM2(3:0) ] | RW = 0x00
04 | NUM2(11:4) ] | RW = 0x08
05 | [ DIV2 ] |NUM2(12)| RW = 0x93
06 | L1LK | [ TAD1 ] | L2LK | [ TAD2 ] | R
07 | [ FMF ] | R
08 | ? | FMCAL | ? | ? | ? | ? | ? | TEMP | R
09 | 0 | 0 | [ FMGC ] | 0 | GP02 | GP01 | 0 | RW = 0x20
0A | ??
0B | 0 | 0 | 1 | 1 | 0 | 0 | [ VGAG ] | RW = 0x30
0C | V1CSE | 1 | 1 | 1 | 1 | 1 | 1 | 1 | RW = 0xFF
0D | 1 | 0 | [ V1CS ] | RW = 0xB0
0E | ??
0F | ??
10 | ??
11 | [ LOTO ] | 0 | 0 | 1 | 0 | RW = 0x42
PART : Part code : 6 for MT2060
REV : Revision code : 3 for current revision
LNABAND : Input frequency range : ( See code for details )
NUM1 / DIV1 / NUM2 / DIV2 : Frequencies programming ( See code for details )
FM1CA : Calibration Start Bit
FM1SS : Calibration Single Step bit
L1LK : LO1 Lock Detect
TAD1 : Tune Line ADC ( ? )
L2LK : LO2 Lock Detect
TAD2 : Tune Line ADC ( ? )
FMF : Estimated first IF Center frequency Offset ( ? )
FM1CAL : Calibration done bit
TEMP : On chip temperature sensor
FMCG : Mixer 1 Cap Gain ( ? )
GP01 / GP02 : Programmable digital outputs. Unconnected pins ?
V1CSE : LO1 VCO Automatic Capacitor Select Enable ( ? )
V1CS : LO1 Capacitor Selection Value ( ? )
LOTO : LO Timeout ( ? )
VGAG : Tuner Output gain
*/
#define I2C_ADDRESS 0x60
#define REG_PART_REV 0
#define REG_LO1C1 1
#define REG_LO1C2 2
#define REG_LO2C1 3
#define REG_LO2C2 4
#define REG_LO2C3 5
#define REG_LO_STATUS 6
#define REG_FM_FREQ 7
#define REG_MISC_STAT 8
#define REG_MISC_CTRL 9
#define REG_RESERVED_A 0x0A
#define REG_VGAG 0x0B
#define REG_LO1B1 0x0C
#define REG_LO1B2 0x0D
#define REG_LOTO 0x11
#define PART_REV 0x63 // The current driver works only with PART=6 and REV=3 chips
struct mt2060_priv {
struct mt2060_config *cfg;
struct i2c_adapter *i2c;
u32 frequency;
u16 if1_freq;
u8 fmfreq;
};
#endif

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#ifndef __MT2063_H__
#define __MT2063_H__
#include "dvb_frontend.h"
struct mt2063_config {
u8 tuner_address;
u32 refclock;
};
#if IS_ENABLED(CONFIG_MEDIA_TUNER_MT2063)
struct dvb_frontend *mt2063_attach(struct dvb_frontend *fe,
struct mt2063_config *config,
struct i2c_adapter *i2c);
#else
static inline struct dvb_frontend *mt2063_attach(struct dvb_frontend *fe,
struct mt2063_config *config,
struct i2c_adapter *i2c)
{
printk(KERN_WARNING "%s: Driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif /* CONFIG_DVB_MT2063 */
#endif /* __MT2063_H__ */

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/*
* i2c tv tuner chip device driver
* controls microtune tuners, mt2032 + mt2050 at the moment.
*
* This "mt20xx" module was split apart from the original "tuner" module.
*/
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/videodev2.h>
#include "tuner-i2c.h"
#include "mt20xx.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "enable verbose debug messages");
/* ---------------------------------------------------------------------- */
static unsigned int optimize_vco = 1;
module_param(optimize_vco, int, 0644);
static unsigned int tv_antenna = 1;
module_param(tv_antenna, int, 0644);
static unsigned int radio_antenna;
module_param(radio_antenna, int, 0644);
/* ---------------------------------------------------------------------- */
#define MT2032 0x04
#define MT2030 0x06
#define MT2040 0x07
#define MT2050 0x42
static char *microtune_part[] = {
[ MT2030 ] = "MT2030",
[ MT2032 ] = "MT2032",
[ MT2040 ] = "MT2040",
[ MT2050 ] = "MT2050",
};
struct microtune_priv {
struct tuner_i2c_props i2c_props;
unsigned int xogc;
//unsigned int radio_if2;
u32 frequency;
};
static int microtune_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
return 0;
}
static int microtune_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct microtune_priv *priv = fe->tuner_priv;
*frequency = priv->frequency;
return 0;
}
// IsSpurInBand()?
static int mt2032_spurcheck(struct dvb_frontend *fe,
int f1, int f2, int spectrum_from,int spectrum_to)
{
struct microtune_priv *priv = fe->tuner_priv;
int n1=1,n2,f;
f1=f1/1000; //scale to kHz to avoid 32bit overflows
f2=f2/1000;
spectrum_from/=1000;
spectrum_to/=1000;
tuner_dbg("spurcheck f1=%d f2=%d from=%d to=%d\n",
f1,f2,spectrum_from,spectrum_to);
do {
n2=-n1;
f=n1*(f1-f2);
do {
n2--;
f=f-f2;
tuner_dbg("spurtest n1=%d n2=%d ftest=%d\n",n1,n2,f);
if( (f>spectrum_from) && (f<spectrum_to))
tuner_dbg("mt2032 spurcheck triggered: %d\n",n1);
} while ( (f>(f2-spectrum_to)) || (n2>-5));
n1++;
} while (n1<5);
return 1;
}
static int mt2032_compute_freq(struct dvb_frontend *fe,
unsigned int rfin,
unsigned int if1, unsigned int if2,
unsigned int spectrum_from,
unsigned int spectrum_to,
unsigned char *buf,
int *ret_sel,
unsigned int xogc) //all in Hz
{
struct microtune_priv *priv = fe->tuner_priv;
unsigned int fref,lo1,lo1n,lo1a,s,sel,lo1freq, desired_lo1,
desired_lo2,lo2,lo2n,lo2a,lo2num,lo2freq;
fref= 5250 *1000; //5.25MHz
desired_lo1=rfin+if1;
lo1=(2*(desired_lo1/1000)+(fref/1000)) / (2*fref/1000);
lo1n=lo1/8;
lo1a=lo1-(lo1n*8);
s=rfin/1000/1000+1090;
if(optimize_vco) {
if(s>1890) sel=0;
else if(s>1720) sel=1;
else if(s>1530) sel=2;
else if(s>1370) sel=3;
else sel=4; // >1090
}
else {
if(s>1790) sel=0; // <1958
else if(s>1617) sel=1;
else if(s>1449) sel=2;
else if(s>1291) sel=3;
else sel=4; // >1090
}
*ret_sel=sel;
lo1freq=(lo1a+8*lo1n)*fref;
tuner_dbg("mt2032: rfin=%d lo1=%d lo1n=%d lo1a=%d sel=%d, lo1freq=%d\n",
rfin,lo1,lo1n,lo1a,sel,lo1freq);
desired_lo2=lo1freq-rfin-if2;
lo2=(desired_lo2)/fref;
lo2n=lo2/8;
lo2a=lo2-(lo2n*8);
lo2num=((desired_lo2/1000)%(fref/1000))* 3780/(fref/1000); //scale to fit in 32bit arith
lo2freq=(lo2a+8*lo2n)*fref + lo2num*(fref/1000)/3780*1000;
tuner_dbg("mt2032: rfin=%d lo2=%d lo2n=%d lo2a=%d num=%d lo2freq=%d\n",
rfin,lo2,lo2n,lo2a,lo2num,lo2freq);
if (lo1a > 7 || lo1n < 17 || lo1n > 48 || lo2a > 7 || lo2n < 17 ||
lo2n > 30) {
tuner_info("mt2032: frequency parameters out of range: %d %d %d %d\n",
lo1a, lo1n, lo2a,lo2n);
return(-1);
}
mt2032_spurcheck(fe, lo1freq, desired_lo2, spectrum_from, spectrum_to);
// should recalculate lo1 (one step up/down)
// set up MT2032 register map for transfer over i2c
buf[0]=lo1n-1;
buf[1]=lo1a | (sel<<4);
buf[2]=0x86; // LOGC
buf[3]=0x0f; //reserved
buf[4]=0x1f;
buf[5]=(lo2n-1) | (lo2a<<5);
if(rfin >400*1000*1000)
buf[6]=0xe4;
else
buf[6]=0xf4; // set PKEN per rev 1.2
buf[7]=8+xogc;
buf[8]=0xc3; //reserved
buf[9]=0x4e; //reserved
buf[10]=0xec; //reserved
buf[11]=(lo2num&0xff);
buf[12]=(lo2num>>8) |0x80; // Lo2RST
return 0;
}
static int mt2032_check_lo_lock(struct dvb_frontend *fe)
{
struct microtune_priv *priv = fe->tuner_priv;
int try,lock=0;
unsigned char buf[2];
for(try=0;try<10;try++) {
buf[0]=0x0e;
tuner_i2c_xfer_send(&priv->i2c_props,buf,1);
tuner_i2c_xfer_recv(&priv->i2c_props,buf,1);
tuner_dbg("mt2032 Reg.E=0x%02x\n",buf[0]);
lock=buf[0] &0x06;
if (lock==6)
break;
tuner_dbg("mt2032: pll wait 1ms for lock (0x%2x)\n",buf[0]);
udelay(1000);
}
return lock;
}
static int mt2032_optimize_vco(struct dvb_frontend *fe,int sel,int lock)
{
struct microtune_priv *priv = fe->tuner_priv;
unsigned char buf[2];
int tad1;
buf[0]=0x0f;
tuner_i2c_xfer_send(&priv->i2c_props,buf,1);
tuner_i2c_xfer_recv(&priv->i2c_props,buf,1);
tuner_dbg("mt2032 Reg.F=0x%02x\n",buf[0]);
tad1=buf[0]&0x07;
if(tad1 ==0) return lock;
if(tad1 ==1) return lock;
if(tad1==2) {
if(sel==0)
return lock;
else sel--;
}
else {
if(sel<4)
sel++;
else
return lock;
}
tuner_dbg("mt2032 optimize_vco: sel=%d\n",sel);
buf[0]=0x0f;
buf[1]=sel;
tuner_i2c_xfer_send(&priv->i2c_props,buf,2);
lock=mt2032_check_lo_lock(fe);
return lock;
}
static void mt2032_set_if_freq(struct dvb_frontend *fe, unsigned int rfin,
unsigned int if1, unsigned int if2,
unsigned int from, unsigned int to)
{
unsigned char buf[21];
int lint_try,ret,sel,lock=0;
struct microtune_priv *priv = fe->tuner_priv;
tuner_dbg("mt2032_set_if_freq rfin=%d if1=%d if2=%d from=%d to=%d\n",
rfin,if1,if2,from,to);
buf[0]=0;
ret=tuner_i2c_xfer_send(&priv->i2c_props,buf,1);
tuner_i2c_xfer_recv(&priv->i2c_props,buf,21);
buf[0]=0;
ret=mt2032_compute_freq(fe,rfin,if1,if2,from,to,&buf[1],&sel,priv->xogc);
if (ret<0)
return;
// send only the relevant registers per Rev. 1.2
buf[0]=0;
ret=tuner_i2c_xfer_send(&priv->i2c_props,buf,4);
buf[5]=5;
ret=tuner_i2c_xfer_send(&priv->i2c_props,buf+5,4);
buf[11]=11;
ret=tuner_i2c_xfer_send(&priv->i2c_props,buf+11,3);
if(ret!=3)
tuner_warn("i2c i/o error: rc == %d (should be 3)\n",ret);
// wait for PLLs to lock (per manual), retry LINT if not.
for(lint_try=0; lint_try<2; lint_try++) {
lock=mt2032_check_lo_lock(fe);
if(optimize_vco)
lock=mt2032_optimize_vco(fe,sel,lock);
if(lock==6) break;
tuner_dbg("mt2032: re-init PLLs by LINT\n");
buf[0]=7;
buf[1]=0x80 +8+priv->xogc; // set LINT to re-init PLLs
tuner_i2c_xfer_send(&priv->i2c_props,buf,2);
mdelay(10);
buf[1]=8+priv->xogc;
tuner_i2c_xfer_send(&priv->i2c_props,buf,2);
}
if (lock!=6)
tuner_warn("MT2032 Fatal Error: PLLs didn't lock.\n");
buf[0]=2;
buf[1]=0x20; // LOGC for optimal phase noise
ret=tuner_i2c_xfer_send(&priv->i2c_props,buf,2);
if (ret!=2)
tuner_warn("i2c i/o error: rc == %d (should be 2)\n",ret);
}
static int mt2032_set_tv_freq(struct dvb_frontend *fe,
struct analog_parameters *params)
{
int if2,from,to;
// signal bandwidth and picture carrier
if (params->std & V4L2_STD_525_60) {
// NTSC
from = 40750*1000;
to = 46750*1000;
if2 = 45750*1000;
} else {
// PAL
from = 32900*1000;
to = 39900*1000;
if2 = 38900*1000;
}
mt2032_set_if_freq(fe, params->frequency*62500,
1090*1000*1000, if2, from, to);
return 0;
}
static int mt2032_set_radio_freq(struct dvb_frontend *fe,
struct analog_parameters *params)
{
struct microtune_priv *priv = fe->tuner_priv;
int if2;
if (params->std & V4L2_STD_525_60) {
tuner_dbg("pinnacle ntsc\n");
if2 = 41300 * 1000;
} else {
tuner_dbg("pinnacle pal\n");
if2 = 33300 * 1000;
}
// per Manual for FM tuning: first if center freq. 1085 MHz
mt2032_set_if_freq(fe, params->frequency * 125 / 2,
1085*1000*1000,if2,if2,if2);
return 0;
}
static int mt2032_set_params(struct dvb_frontend *fe,
struct analog_parameters *params)
{
struct microtune_priv *priv = fe->tuner_priv;
int ret = -EINVAL;
switch (params->mode) {
case V4L2_TUNER_RADIO:
ret = mt2032_set_radio_freq(fe, params);
priv->frequency = params->frequency * 125 / 2;
break;
case V4L2_TUNER_ANALOG_TV:
case V4L2_TUNER_DIGITAL_TV:
ret = mt2032_set_tv_freq(fe, params);
priv->frequency = params->frequency * 62500;
break;
}
return ret;
}
static struct dvb_tuner_ops mt2032_tuner_ops = {
.set_analog_params = mt2032_set_params,
.release = microtune_release,
.get_frequency = microtune_get_frequency,
};
// Initialization as described in "MT203x Programming Procedures", Rev 1.2, Feb.2001
static int mt2032_init(struct dvb_frontend *fe)
{
struct microtune_priv *priv = fe->tuner_priv;
unsigned char buf[21];
int ret,xogc,xok=0;
// Initialize Registers per spec.
buf[1]=2; // Index to register 2
buf[2]=0xff;
buf[3]=0x0f;
buf[4]=0x1f;
ret=tuner_i2c_xfer_send(&priv->i2c_props,buf+1,4);
buf[5]=6; // Index register 6
buf[6]=0xe4;
buf[7]=0x8f;
buf[8]=0xc3;
buf[9]=0x4e;
buf[10]=0xec;
ret=tuner_i2c_xfer_send(&priv->i2c_props,buf+5,6);
buf[12]=13; // Index register 13
buf[13]=0x32;
ret=tuner_i2c_xfer_send(&priv->i2c_props,buf+12,2);
// Adjust XOGC (register 7), wait for XOK
xogc=7;
do {
tuner_dbg("mt2032: xogc = 0x%02x\n",xogc&0x07);
mdelay(10);
buf[0]=0x0e;
tuner_i2c_xfer_send(&priv->i2c_props,buf,1);
tuner_i2c_xfer_recv(&priv->i2c_props,buf,1);
xok=buf[0]&0x01;
tuner_dbg("mt2032: xok = 0x%02x\n",xok);
if (xok == 1) break;
xogc--;
tuner_dbg("mt2032: xogc = 0x%02x\n",xogc&0x07);
if (xogc == 3) {
xogc=4; // min. 4 per spec
break;
}
buf[0]=0x07;
buf[1]=0x88 + xogc;
ret=tuner_i2c_xfer_send(&priv->i2c_props,buf,2);
if (ret!=2)
tuner_warn("i2c i/o error: rc == %d (should be 2)\n",ret);
} while (xok != 1 );
priv->xogc=xogc;
memcpy(&fe->ops.tuner_ops, &mt2032_tuner_ops, sizeof(struct dvb_tuner_ops));
return(1);
}
static void mt2050_set_antenna(struct dvb_frontend *fe, unsigned char antenna)
{
struct microtune_priv *priv = fe->tuner_priv;
unsigned char buf[2];
buf[0] = 6;
buf[1] = antenna ? 0x11 : 0x10;
tuner_i2c_xfer_send(&priv->i2c_props, buf, 2);
tuner_dbg("mt2050: enabled antenna connector %d\n", antenna);
}
static void mt2050_set_if_freq(struct dvb_frontend *fe,unsigned int freq, unsigned int if2)
{
struct microtune_priv *priv = fe->tuner_priv;
unsigned int if1=1218*1000*1000;
unsigned int f_lo1,f_lo2,lo1,lo2,f_lo1_modulo,f_lo2_modulo,num1,num2,div1a,div1b,div2a,div2b;
int ret;
unsigned char buf[6];
tuner_dbg("mt2050_set_if_freq freq=%d if1=%d if2=%d\n",
freq,if1,if2);
f_lo1=freq+if1;
f_lo1=(f_lo1/1000000)*1000000;
f_lo2=f_lo1-freq-if2;
f_lo2=(f_lo2/50000)*50000;
lo1=f_lo1/4000000;
lo2=f_lo2/4000000;
f_lo1_modulo= f_lo1-(lo1*4000000);
f_lo2_modulo= f_lo2-(lo2*4000000);
num1=4*f_lo1_modulo/4000000;
num2=4096*(f_lo2_modulo/1000)/4000;
// todo spurchecks
div1a=(lo1/12)-1;
div1b=lo1-(div1a+1)*12;
div2a=(lo2/8)-1;
div2b=lo2-(div2a+1)*8;
if (debug > 1) {
tuner_dbg("lo1 lo2 = %d %d\n", lo1, lo2);
tuner_dbg("num1 num2 div1a div1b div2a div2b= %x %x %x %x %x %x\n",
num1,num2,div1a,div1b,div2a,div2b);
}
buf[0]=1;
buf[1]= 4*div1b + num1;
if(freq<275*1000*1000) buf[1] = buf[1]|0x80;
buf[2]=div1a;
buf[3]=32*div2b + num2/256;
buf[4]=num2-(num2/256)*256;
buf[5]=div2a;
if(num2!=0) buf[5]=buf[5]|0x40;
if (debug > 1) {
int i;
tuner_dbg("bufs is: ");
for(i=0;i<6;i++)
printk("%x ",buf[i]);
printk("\n");
}
ret=tuner_i2c_xfer_send(&priv->i2c_props,buf,6);
if (ret!=6)
tuner_warn("i2c i/o error: rc == %d (should be 6)\n",ret);
}
static int mt2050_set_tv_freq(struct dvb_frontend *fe,
struct analog_parameters *params)
{
unsigned int if2;
if (params->std & V4L2_STD_525_60) {
// NTSC
if2 = 45750*1000;
} else {
// PAL
if2 = 38900*1000;
}
if (V4L2_TUNER_DIGITAL_TV == params->mode) {
// DVB (pinnacle 300i)
if2 = 36150*1000;
}
mt2050_set_if_freq(fe, params->frequency*62500, if2);
mt2050_set_antenna(fe, tv_antenna);
return 0;
}
static int mt2050_set_radio_freq(struct dvb_frontend *fe,
struct analog_parameters *params)
{
struct microtune_priv *priv = fe->tuner_priv;
int if2;
if (params->std & V4L2_STD_525_60) {
tuner_dbg("pinnacle ntsc\n");
if2 = 41300 * 1000;
} else {
tuner_dbg("pinnacle pal\n");
if2 = 33300 * 1000;
}
mt2050_set_if_freq(fe, params->frequency * 125 / 2, if2);
mt2050_set_antenna(fe, radio_antenna);
return 0;
}
static int mt2050_set_params(struct dvb_frontend *fe,
struct analog_parameters *params)
{
struct microtune_priv *priv = fe->tuner_priv;
int ret = -EINVAL;
switch (params->mode) {
case V4L2_TUNER_RADIO:
ret = mt2050_set_radio_freq(fe, params);
priv->frequency = params->frequency * 125 / 2;
break;
case V4L2_TUNER_ANALOG_TV:
case V4L2_TUNER_DIGITAL_TV:
ret = mt2050_set_tv_freq(fe, params);
priv->frequency = params->frequency * 62500;
break;
}
return ret;
}
static struct dvb_tuner_ops mt2050_tuner_ops = {
.set_analog_params = mt2050_set_params,
.release = microtune_release,
.get_frequency = microtune_get_frequency,
};
static int mt2050_init(struct dvb_frontend *fe)
{
struct microtune_priv *priv = fe->tuner_priv;
unsigned char buf[2];
buf[0] = 6;
buf[1] = 0x10;
tuner_i2c_xfer_send(&priv->i2c_props, buf, 2); /* power */
buf[0] = 0x0f;
buf[1] = 0x0f;
tuner_i2c_xfer_send(&priv->i2c_props, buf, 2); /* m1lo */
buf[0] = 0x0d;
tuner_i2c_xfer_send(&priv->i2c_props, buf, 1);
tuner_i2c_xfer_recv(&priv->i2c_props, buf, 1);
tuner_dbg("mt2050: sro is %x\n", buf[0]);
memcpy(&fe->ops.tuner_ops, &mt2050_tuner_ops, sizeof(struct dvb_tuner_ops));
return 0;
}
struct dvb_frontend *microtune_attach(struct dvb_frontend *fe,
struct i2c_adapter* i2c_adap,
u8 i2c_addr)
{
struct microtune_priv *priv = NULL;
char *name;
unsigned char buf[21];
int company_code;
priv = kzalloc(sizeof(struct microtune_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
fe->tuner_priv = priv;
priv->i2c_props.addr = i2c_addr;
priv->i2c_props.adap = i2c_adap;
priv->i2c_props.name = "mt20xx";
//priv->radio_if2 = 10700 * 1000; /* 10.7MHz - FM radio */
memset(buf,0,sizeof(buf));
name = "unknown";
tuner_i2c_xfer_send(&priv->i2c_props,buf,1);
tuner_i2c_xfer_recv(&priv->i2c_props,buf,21);
if (debug) {
int i;
tuner_dbg("MT20xx hexdump:");
for(i=0;i<21;i++) {
printk(" %02x",buf[i]);
if(((i+1)%8)==0) printk(" ");
}
printk("\n");
}
company_code = buf[0x11] << 8 | buf[0x12];
tuner_info("microtune: companycode=%04x part=%02x rev=%02x\n",
company_code,buf[0x13],buf[0x14]);
if (buf[0x13] < ARRAY_SIZE(microtune_part) &&
NULL != microtune_part[buf[0x13]])
name = microtune_part[buf[0x13]];
switch (buf[0x13]) {
case MT2032:
mt2032_init(fe);
break;
case MT2050:
mt2050_init(fe);
break;
default:
tuner_info("microtune %s found, not (yet?) supported, sorry :-/\n",
name);
return NULL;
}
strlcpy(fe->ops.tuner_ops.info.name, name,
sizeof(fe->ops.tuner_ops.info.name));
tuner_info("microtune %s found, OK\n",name);
return fe;
}
EXPORT_SYMBOL_GPL(microtune_attach);
MODULE_DESCRIPTION("Microtune tuner driver");
MODULE_AUTHOR("Ralph Metzler, Gerd Knorr, Gunther Mayer");
MODULE_LICENSE("GPL");
/*
* Overrides for Emacs so that we follow Linus's tabbing style.
* ---------------------------------------------------------------------------
* Local variables:
* c-basic-offset: 8
* End:
*/

37
drivers/media/tuners/mt20xx.h Normal file
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@ -0,0 +1,37 @@
/*
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MT20XX_H__
#define __MT20XX_H__
#include <linux/i2c.h>
#include "dvb_frontend.h"
#if IS_ENABLED(CONFIG_MEDIA_TUNER_MT20XX)
extern struct dvb_frontend *microtune_attach(struct dvb_frontend *fe,
struct i2c_adapter* i2c_adap,
u8 i2c_addr);
#else
static inline struct dvb_frontend *microtune_attach(struct dvb_frontend *fe,
struct i2c_adapter* i2c_adap,
u8 i2c_addr)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif /* __MT20XX_H__ */

301
drivers/media/tuners/mt2131.c Normal file
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/*
* Driver for Microtune MT2131 "QAM/8VSB single chip tuner"
*
* Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/dvb/frontend.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include "dvb_frontend.h"
#include "mt2131.h"
#include "mt2131_priv.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
#define dprintk(level,fmt, arg...) if (debug >= level) \
printk(KERN_INFO "%s: " fmt, "mt2131", ## arg)
static u8 mt2131_config1[] = {
0x01,
0x50, 0x00, 0x50, 0x80, 0x00, 0x49, 0xfa, 0x88,
0x08, 0x77, 0x41, 0x04, 0x00, 0x00, 0x00, 0x32,
0x7f, 0xda, 0x4c, 0x00, 0x10, 0xaa, 0x78, 0x80,
0xff, 0x68, 0xa0, 0xff, 0xdd, 0x00, 0x00
};
static u8 mt2131_config2[] = {
0x10,
0x7f, 0xc8, 0x0a, 0x5f, 0x00, 0x04
};
static int mt2131_readreg(struct mt2131_priv *priv, u8 reg, u8 *val)
{
struct i2c_msg msg[2] = {
{ .addr = priv->cfg->i2c_address, .flags = 0,
.buf = &reg, .len = 1 },
{ .addr = priv->cfg->i2c_address, .flags = I2C_M_RD,
.buf = val, .len = 1 },
};
if (i2c_transfer(priv->i2c, msg, 2) != 2) {
printk(KERN_WARNING "mt2131 I2C read failed\n");
return -EREMOTEIO;
}
return 0;
}
static int mt2131_writereg(struct mt2131_priv *priv, u8 reg, u8 val)
{
u8 buf[2] = { reg, val };
struct i2c_msg msg = { .addr = priv->cfg->i2c_address, .flags = 0,
.buf = buf, .len = 2 };
if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
printk(KERN_WARNING "mt2131 I2C write failed\n");
return -EREMOTEIO;
}
return 0;
}
static int mt2131_writeregs(struct mt2131_priv *priv,u8 *buf, u8 len)
{
struct i2c_msg msg = { .addr = priv->cfg->i2c_address,
.flags = 0, .buf = buf, .len = len };
if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
printk(KERN_WARNING "mt2131 I2C write failed (len=%i)\n",
(int)len);
return -EREMOTEIO;
}
return 0;
}
static int mt2131_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct mt2131_priv *priv;
int ret=0, i;
u32 freq;
u8 if_band_center;
u32 f_lo1, f_lo2;
u32 div1, num1, div2, num2;
u8 b[8];
u8 lockval = 0;
priv = fe->tuner_priv;
freq = c->frequency / 1000; /* Hz -> kHz */
dprintk(1, "%s() freq=%d\n", __func__, freq);
f_lo1 = freq + MT2131_IF1 * 1000;
f_lo1 = (f_lo1 / 250) * 250;
f_lo2 = f_lo1 - freq - MT2131_IF2;
priv->frequency = (f_lo1 - f_lo2 - MT2131_IF2) * 1000;
/* Frequency LO1 = 16MHz * (DIV1 + NUM1/8192 ) */
num1 = f_lo1 * 64 / (MT2131_FREF / 128);
div1 = num1 / 8192;
num1 &= 0x1fff;
/* Frequency LO2 = 16MHz * (DIV2 + NUM2/8192 ) */
num2 = f_lo2 * 64 / (MT2131_FREF / 128);
div2 = num2 / 8192;
num2 &= 0x1fff;
if (freq <= 82500) if_band_center = 0x00; else
if (freq <= 137500) if_band_center = 0x01; else
if (freq <= 192500) if_band_center = 0x02; else
if (freq <= 247500) if_band_center = 0x03; else
if (freq <= 302500) if_band_center = 0x04; else
if (freq <= 357500) if_band_center = 0x05; else
if (freq <= 412500) if_band_center = 0x06; else
if (freq <= 467500) if_band_center = 0x07; else
if (freq <= 522500) if_band_center = 0x08; else
if (freq <= 577500) if_band_center = 0x09; else
if (freq <= 632500) if_band_center = 0x0A; else
if (freq <= 687500) if_band_center = 0x0B; else
if (freq <= 742500) if_band_center = 0x0C; else
if (freq <= 797500) if_band_center = 0x0D; else
if (freq <= 852500) if_band_center = 0x0E; else
if (freq <= 907500) if_band_center = 0x0F; else
if (freq <= 962500) if_band_center = 0x10; else
if (freq <= 1017500) if_band_center = 0x11; else
if (freq <= 1072500) if_band_center = 0x12; else if_band_center = 0x13;
b[0] = 1;
b[1] = (num1 >> 5) & 0xFF;
b[2] = (num1 & 0x1F);
b[3] = div1;
b[4] = (num2 >> 5) & 0xFF;
b[5] = num2 & 0x1F;
b[6] = div2;
dprintk(1, "IF1: %dMHz IF2: %dMHz\n", MT2131_IF1, MT2131_IF2);
dprintk(1, "PLL freq=%dkHz band=%d\n", (int)freq, (int)if_band_center);
dprintk(1, "PLL f_lo1=%dkHz f_lo2=%dkHz\n", (int)f_lo1, (int)f_lo2);
dprintk(1, "PLL div1=%d num1=%d div2=%d num2=%d\n",
(int)div1, (int)num1, (int)div2, (int)num2);
dprintk(1, "PLL [1..6]: %2x %2x %2x %2x %2x %2x\n",
(int)b[1], (int)b[2], (int)b[3], (int)b[4], (int)b[5],
(int)b[6]);
ret = mt2131_writeregs(priv,b,7);
if (ret < 0)
return ret;
mt2131_writereg(priv, 0x0b, if_band_center);
/* Wait for lock */
i = 0;
do {
mt2131_readreg(priv, 0x08, &lockval);
if ((lockval & 0x88) == 0x88)
break;
msleep(4);
i++;
} while (i < 10);
return ret;
}
static int mt2131_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct mt2131_priv *priv = fe->tuner_priv;
dprintk(1, "%s()\n", __func__);
*frequency = priv->frequency;
return 0;
}
static int mt2131_get_status(struct dvb_frontend *fe, u32 *status)
{
struct mt2131_priv *priv = fe->tuner_priv;
u8 lock_status = 0;
u8 afc_status = 0;
*status = 0;
mt2131_readreg(priv, 0x08, &lock_status);
if ((lock_status & 0x88) == 0x88)
*status = TUNER_STATUS_LOCKED;
mt2131_readreg(priv, 0x09, &afc_status);
dprintk(1, "%s() - LO Status = 0x%x, AFC Status = 0x%x\n",
__func__, lock_status, afc_status);
return 0;
}
static int mt2131_init(struct dvb_frontend *fe)
{
struct mt2131_priv *priv = fe->tuner_priv;
int ret;
dprintk(1, "%s()\n", __func__);
if ((ret = mt2131_writeregs(priv, mt2131_config1,
sizeof(mt2131_config1))) < 0)
return ret;
mt2131_writereg(priv, 0x0b, 0x09);
mt2131_writereg(priv, 0x15, 0x47);
mt2131_writereg(priv, 0x07, 0xf2);
mt2131_writereg(priv, 0x0b, 0x01);
if ((ret = mt2131_writeregs(priv, mt2131_config2,
sizeof(mt2131_config2))) < 0)
return ret;
return ret;
}
static int mt2131_release(struct dvb_frontend *fe)
{
dprintk(1, "%s()\n", __func__);
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
return 0;
}
static const struct dvb_tuner_ops mt2131_tuner_ops = {
.info = {
.name = "Microtune MT2131",
.frequency_min = 48000000,
.frequency_max = 860000000,
.frequency_step = 50000,
},
.release = mt2131_release,
.init = mt2131_init,
.set_params = mt2131_set_params,
.get_frequency = mt2131_get_frequency,
.get_status = mt2131_get_status
};
struct dvb_frontend * mt2131_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
struct mt2131_config *cfg, u16 if1)
{
struct mt2131_priv *priv = NULL;
u8 id = 0;
dprintk(1, "%s()\n", __func__);
priv = kzalloc(sizeof(struct mt2131_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->cfg = cfg;
priv->i2c = i2c;
if (mt2131_readreg(priv, 0, &id) != 0) {
kfree(priv);
return NULL;
}
if ( (id != 0x3E) && (id != 0x3F) ) {
printk(KERN_ERR "MT2131: Device not found at addr 0x%02x\n",
cfg->i2c_address);
kfree(priv);
return NULL;
}
printk(KERN_INFO "MT2131: successfully identified at address 0x%02x\n",
cfg->i2c_address);
memcpy(&fe->ops.tuner_ops, &mt2131_tuner_ops,
sizeof(struct dvb_tuner_ops));
fe->tuner_priv = priv;
return fe;
}
EXPORT_SYMBOL(mt2131_attach);
MODULE_AUTHOR("Steven Toth");
MODULE_DESCRIPTION("Microtune MT2131 silicon tuner driver");
MODULE_LICENSE("GPL");
/*
* Local variables:
* c-basic-offset: 8
*/

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/*
* Driver for Microtune MT2131 "QAM/8VSB single chip tuner"
*
* Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MT2131_H__
#define __MT2131_H__
struct dvb_frontend;
struct i2c_adapter;
struct mt2131_config {
u8 i2c_address;
u8 clock_out; /* 0 = off, 1 = CLK/4, 2 = CLK/2, 3 = CLK/1 */
};
#if IS_ENABLED(CONFIG_MEDIA_TUNER_MT2131)
extern struct dvb_frontend* mt2131_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
struct mt2131_config *cfg,
u16 if1);
#else
static inline struct dvb_frontend* mt2131_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
struct mt2131_config *cfg,
u16 if1)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif /* CONFIG_MEDIA_TUNER_MT2131 */
#endif /* __MT2131_H__ */
/*
* Local variables:
* c-basic-offset: 8
*/

48
drivers/media/tuners/mt2131_priv.h Normal file
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/*
* Driver for Microtune MT2131 "QAM/8VSB single chip tuner"
*
* Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MT2131_PRIV_H__
#define __MT2131_PRIV_H__
/* Regs */
#define MT2131_PWR 0x07
#define MT2131_UPC_1 0x0b
#define MT2131_AGC_RL 0x10
#define MT2131_MISC_2 0x15
/* frequency values in KHz */
#define MT2131_IF1 1220
#define MT2131_IF2 44000
#define MT2131_FREF 16000
struct mt2131_priv {
struct mt2131_config *cfg;
struct i2c_adapter *i2c;
u32 frequency;
};
#endif /* __MT2131_PRIV_H__ */
/*
* Local variables:
* c-basic-offset: 8
*/

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/*
* Driver for Microtune MT2266 "Direct conversion low power broadband tuner"
*
* Copyright (c) 2007 Olivier DANET <odanet@caramail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/dvb/frontend.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include "dvb_frontend.h"
#include "mt2266.h"
#define I2C_ADDRESS 0x60
#define REG_PART_REV 0
#define REG_TUNE 1
#define REG_BAND 6
#define REG_BANDWIDTH 8
#define REG_LOCK 0x12
#define PART_REV 0x85
struct mt2266_priv {
struct mt2266_config *cfg;
struct i2c_adapter *i2c;
u32 frequency;
u32 bandwidth;
u8 band;
};
#define MT2266_VHF 1
#define MT2266_UHF 0
/* Here, frequencies are expressed in kiloHertz to avoid 32 bits overflows */
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
#define dprintk(args...) do { if (debug) {printk(KERN_DEBUG "MT2266: " args); printk("\n"); }} while (0)
// Reads a single register
static int mt2266_readreg(struct mt2266_priv *priv, u8 reg, u8 *val)
{
struct i2c_msg msg[2] = {
{ .addr = priv->cfg->i2c_address, .flags = 0, .buf = &reg, .len = 1 },
{ .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, .buf = val, .len = 1 },
};
if (i2c_transfer(priv->i2c, msg, 2) != 2) {
printk(KERN_WARNING "MT2266 I2C read failed\n");
return -EREMOTEIO;
}
return 0;
}
// Writes a single register
static int mt2266_writereg(struct mt2266_priv *priv, u8 reg, u8 val)
{
u8 buf[2] = { reg, val };
struct i2c_msg msg = {
.addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2
};
if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
printk(KERN_WARNING "MT2266 I2C write failed\n");
return -EREMOTEIO;
}
return 0;
}
// Writes a set of consecutive registers
static int mt2266_writeregs(struct mt2266_priv *priv,u8 *buf, u8 len)
{
struct i2c_msg msg = {
.addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = len
};
if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
printk(KERN_WARNING "MT2266 I2C write failed (len=%i)\n",(int)len);
return -EREMOTEIO;
}
return 0;
}
// Initialisation sequences
static u8 mt2266_init1[] = { REG_TUNE, 0x00, 0x00, 0x28,
0x00, 0x52, 0x99, 0x3f };
static u8 mt2266_init2[] = {
0x17, 0x6d, 0x71, 0x61, 0xc0, 0xbf, 0xff, 0xdc, 0x00, 0x0a, 0xd4,
0x03, 0x64, 0x64, 0x64, 0x64, 0x22, 0xaa, 0xf2, 0x1e, 0x80, 0x14,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x7f, 0x5e, 0x3f, 0xff, 0xff,
0xff, 0x00, 0x77, 0x0f, 0x2d
};
static u8 mt2266_init_8mhz[] = { REG_BANDWIDTH, 0x22, 0x22, 0x22, 0x22,
0x22, 0x22, 0x22, 0x22 };
static u8 mt2266_init_7mhz[] = { REG_BANDWIDTH, 0x32, 0x32, 0x32, 0x32,
0x32, 0x32, 0x32, 0x32 };
static u8 mt2266_init_6mhz[] = { REG_BANDWIDTH, 0xa7, 0xa7, 0xa7, 0xa7,
0xa7, 0xa7, 0xa7, 0xa7 };
static u8 mt2266_uhf[] = { 0x1d, 0xdc, 0x00, 0x0a, 0xd4, 0x03, 0x64, 0x64,
0x64, 0x64, 0x22, 0xaa, 0xf2, 0x1e, 0x80, 0x14 };
static u8 mt2266_vhf[] = { 0x1d, 0xfe, 0x00, 0x00, 0xb4, 0x03, 0xa5, 0xa5,
0xa5, 0xa5, 0x82, 0xaa, 0xf1, 0x17, 0x80, 0x1f };
#define FREF 30000 // Quartz oscillator 30 MHz
static int mt2266_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct mt2266_priv *priv;
int ret=0;
u32 freq;
u32 tune;
u8 lnaband;
u8 b[10];
int i;
u8 band;
priv = fe->tuner_priv;
freq = priv->frequency / 1000; /* Hz -> kHz */
if (freq < 470000 && freq > 230000)
return -EINVAL; /* Gap between VHF and UHF bands */
priv->frequency = c->frequency;
tune = 2 * freq * (8192/16) / (FREF/16);
band = (freq < 300000) ? MT2266_VHF : MT2266_UHF;
if (band == MT2266_VHF)
tune *= 2;
switch (c->bandwidth_hz) {
case 6000000:
mt2266_writeregs(priv, mt2266_init_6mhz,
sizeof(mt2266_init_6mhz));
break;
case 8000000:
mt2266_writeregs(priv, mt2266_init_8mhz,
sizeof(mt2266_init_8mhz));
break;
case 7000000:
default:
mt2266_writeregs(priv, mt2266_init_7mhz,
sizeof(mt2266_init_7mhz));
break;
}
priv->bandwidth = c->bandwidth_hz;
if (band == MT2266_VHF && priv->band == MT2266_UHF) {
dprintk("Switch from UHF to VHF");
mt2266_writereg(priv, 0x05, 0x04);
mt2266_writereg(priv, 0x19, 0x61);
mt2266_writeregs(priv, mt2266_vhf, sizeof(mt2266_vhf));
} else if (band == MT2266_UHF && priv->band == MT2266_VHF) {
dprintk("Switch from VHF to UHF");
mt2266_writereg(priv, 0x05, 0x52);
mt2266_writereg(priv, 0x19, 0x61);
mt2266_writeregs(priv, mt2266_uhf, sizeof(mt2266_uhf));
}
msleep(10);
if (freq <= 495000)
lnaband = 0xEE;
else if (freq <= 525000)
lnaband = 0xDD;
else if (freq <= 550000)
lnaband = 0xCC;
else if (freq <= 580000)
lnaband = 0xBB;
else if (freq <= 605000)
lnaband = 0xAA;
else if (freq <= 630000)
lnaband = 0x99;
else if (freq <= 655000)
lnaband = 0x88;
else if (freq <= 685000)
lnaband = 0x77;
else if (freq <= 710000)
lnaband = 0x66;
else if (freq <= 735000)
lnaband = 0x55;
else if (freq <= 765000)
lnaband = 0x44;
else if (freq <= 802000)
lnaband = 0x33;
else if (freq <= 840000)
lnaband = 0x22;
else
lnaband = 0x11;
b[0] = REG_TUNE;
b[1] = (tune >> 8) & 0x1F;
b[2] = tune & 0xFF;
b[3] = tune >> 13;
mt2266_writeregs(priv,b,4);
dprintk("set_parms: tune=%d band=%d %s",
(int) tune, (int) lnaband,
(band == MT2266_UHF) ? "UHF" : "VHF");
dprintk("set_parms: [1..3]: %2x %2x %2x",
(int) b[1], (int) b[2], (int)b[3]);
if (band == MT2266_UHF) {
b[0] = 0x05;
b[1] = (priv->band == MT2266_VHF) ? 0x52 : 0x62;
b[2] = lnaband;
mt2266_writeregs(priv, b, 3);
}
/* Wait for pll lock or timeout */
i = 0;
do {
mt2266_readreg(priv,REG_LOCK,b);
if (b[0] & 0x40)
break;
msleep(10);
i++;
} while (i<10);
dprintk("Lock when i=%i",(int)i);
if (band == MT2266_UHF && priv->band == MT2266_VHF)
mt2266_writereg(priv, 0x05, 0x62);
priv->band = band;
return ret;
}
static void mt2266_calibrate(struct mt2266_priv *priv)
{
mt2266_writereg(priv, 0x11, 0x03);
mt2266_writereg(priv, 0x11, 0x01);
mt2266_writeregs(priv, mt2266_init1, sizeof(mt2266_init1));
mt2266_writeregs(priv, mt2266_init2, sizeof(mt2266_init2));
mt2266_writereg(priv, 0x33, 0x5e);
mt2266_writereg(priv, 0x10, 0x10);
mt2266_writereg(priv, 0x10, 0x00);
mt2266_writeregs(priv, mt2266_init_8mhz, sizeof(mt2266_init_8mhz));
msleep(25);
mt2266_writereg(priv, 0x17, 0x6d);
mt2266_writereg(priv, 0x1c, 0x00);
msleep(75);
mt2266_writereg(priv, 0x17, 0x6d);
mt2266_writereg(priv, 0x1c, 0xff);
}
static int mt2266_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct mt2266_priv *priv = fe->tuner_priv;
*frequency = priv->frequency;
return 0;
}
static int mt2266_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
{
struct mt2266_priv *priv = fe->tuner_priv;
*bandwidth = priv->bandwidth;
return 0;
}
static int mt2266_init(struct dvb_frontend *fe)
{
int ret;
struct mt2266_priv *priv = fe->tuner_priv;
ret = mt2266_writereg(priv, 0x17, 0x6d);
if (ret < 0)
return ret;
ret = mt2266_writereg(priv, 0x1c, 0xff);
if (ret < 0)
return ret;
return 0;
}
static int mt2266_sleep(struct dvb_frontend *fe)
{
struct mt2266_priv *priv = fe->tuner_priv;
mt2266_writereg(priv, 0x17, 0x6d);
mt2266_writereg(priv, 0x1c, 0x00);
return 0;
}
static int mt2266_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
return 0;
}
static const struct dvb_tuner_ops mt2266_tuner_ops = {
.info = {
.name = "Microtune MT2266",
.frequency_min = 174000000,
.frequency_max = 862000000,
.frequency_step = 50000,
},
.release = mt2266_release,
.init = mt2266_init,
.sleep = mt2266_sleep,
.set_params = mt2266_set_params,
.get_frequency = mt2266_get_frequency,
.get_bandwidth = mt2266_get_bandwidth
};
struct dvb_frontend * mt2266_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2266_config *cfg)
{
struct mt2266_priv *priv = NULL;
u8 id = 0;
priv = kzalloc(sizeof(struct mt2266_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->cfg = cfg;
priv->i2c = i2c;
priv->band = MT2266_UHF;
if (mt2266_readreg(priv, 0, &id)) {
kfree(priv);
return NULL;
}
if (id != PART_REV) {
kfree(priv);
return NULL;
}
printk(KERN_INFO "MT2266: successfully identified\n");
memcpy(&fe->ops.tuner_ops, &mt2266_tuner_ops, sizeof(struct dvb_tuner_ops));
fe->tuner_priv = priv;
mt2266_calibrate(priv);
return fe;
}
EXPORT_SYMBOL(mt2266_attach);
MODULE_AUTHOR("Olivier DANET");
MODULE_DESCRIPTION("Microtune MT2266 silicon tuner driver");
MODULE_LICENSE("GPL");

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/*
* Driver for Microtune MT2266 "Direct conversion low power broadband tuner"
*
* Copyright (c) 2007 Olivier DANET <odanet@caramail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MT2266_H
#define MT2266_H
struct dvb_frontend;
struct i2c_adapter;
struct mt2266_config {
u8 i2c_address;
};
#if IS_ENABLED(CONFIG_MEDIA_TUNER_MT2266)
extern struct dvb_frontend * mt2266_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2266_config *cfg);
#else
static inline struct dvb_frontend * mt2266_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2266_config *cfg)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif // CONFIG_MEDIA_TUNER_MT2266
#endif

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/*
* MaxLinear MxL301RF OFDM tuner driver
*
* Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* NOTICE:
* This driver is incomplete and lacks init/config of the chips,
* as the necessary info is not disclosed.
* Other features like get_if_frequency() are missing as well.
* It assumes that users of this driver (such as a PCI bridge of
* DTV receiver cards) properly init and configure the chip
* via I2C *before* calling this driver's init() function.
*
* Currently, PT3 driver is the only one that uses this driver,
* and contains init/config code in its firmware.
* Thus some part of the code might be dependent on PT3 specific config.
*/
#include <linux/kernel.h>
#include "mxl301rf.h"
struct mxl301rf_state {
struct mxl301rf_config cfg;
struct i2c_client *i2c;
};
static struct mxl301rf_state *cfg_to_state(struct mxl301rf_config *c)
{
return container_of(c, struct mxl301rf_state, cfg);
}
static int raw_write(struct mxl301rf_state *state, const u8 *buf, int len)
{
int ret;
ret = i2c_master_send(state->i2c, buf, len);
if (ret >= 0 && ret < len)
ret = -EIO;
return (ret == len) ? 0 : ret;
}
static int reg_write(struct mxl301rf_state *state, u8 reg, u8 val)
{
u8 buf[2] = { reg, val };
return raw_write(state, buf, 2);
}
static int reg_read(struct mxl301rf_state *state, u8 reg, u8 *val)
{
u8 wbuf[2] = { 0xfb, reg };
int ret;
ret = raw_write(state, wbuf, sizeof(wbuf));
if (ret == 0)
ret = i2c_master_recv(state->i2c, val, 1);
if (ret >= 0 && ret < 1)
ret = -EIO;
return (ret == 1) ? 0 : ret;
}
/* tuner_ops */
/* get RSSI and update propery cache, set to *out in % */
static int mxl301rf_get_rf_strength(struct dvb_frontend *fe, u16 *out)
{
struct mxl301rf_state *state;
int ret;
u8 rf_in1, rf_in2, rf_off1, rf_off2;
u16 rf_in, rf_off;
s64 level;
struct dtv_fe_stats *rssi;
rssi = &fe->dtv_property_cache.strength;
rssi->len = 1;
rssi->stat[0].scale = FE_SCALE_NOT_AVAILABLE;
*out = 0;
state = fe->tuner_priv;
ret = reg_write(state, 0x14, 0x01);
if (ret < 0)
return ret;
usleep_range(1000, 2000);
ret = reg_read(state, 0x18, &rf_in1);
if (ret == 0)
ret = reg_read(state, 0x19, &rf_in2);
if (ret == 0)
ret = reg_read(state, 0xd6, &rf_off1);
if (ret == 0)
ret = reg_read(state, 0xd7, &rf_off2);
if (ret != 0)
return ret;
rf_in = (rf_in2 & 0x07) << 8 | rf_in1;
rf_off = (rf_off2 & 0x0f) << 5 | (rf_off1 >> 3);
level = rf_in - rf_off - (113 << 3); /* x8 dBm */
level = level * 1000 / 8;
rssi->stat[0].svalue = level;
rssi->stat[0].scale = FE_SCALE_DECIBEL;
/* *out = (level - min) * 100 / (max - min) */
*out = (rf_in - rf_off + (1 << 9) - 1) * 100 / ((5 << 9) - 2);
return 0;
}
/* spur shift parameters */
struct shf {
u32 freq; /* Channel center frequency */
u32 ofst_th; /* Offset frequency threshold */
u8 shf_val; /* Spur shift value */
u8 shf_dir; /* Spur shift direction */
};
static const struct shf shf_tab[] = {
{ 64500, 500, 0x92, 0x07 },
{ 191500, 300, 0xe2, 0x07 },
{ 205500, 500, 0x2c, 0x04 },
{ 212500, 500, 0x1e, 0x04 },
{ 226500, 500, 0xd4, 0x07 },
{ 99143, 500, 0x9c, 0x07 },
{ 173143, 500, 0xd4, 0x07 },
{ 191143, 300, 0xd4, 0x07 },
{ 207143, 500, 0xce, 0x07 },
{ 225143, 500, 0xce, 0x07 },
{ 243143, 500, 0xd4, 0x07 },
{ 261143, 500, 0xd4, 0x07 },
{ 291143, 500, 0xd4, 0x07 },
{ 339143, 500, 0x2c, 0x04 },
{ 117143, 500, 0x7a, 0x07 },
{ 135143, 300, 0x7a, 0x07 },
{ 153143, 500, 0x01, 0x07 }
};
struct reg_val {
u8 reg;
u8 val;
} __attribute__ ((__packed__));
static const struct reg_val set_idac[] = {
{ 0x0d, 0x00 },
{ 0x0c, 0x67 },
{ 0x6f, 0x89 },
{ 0x70, 0x0c },
{ 0x6f, 0x8a },
{ 0x70, 0x0e },
{ 0x6f, 0x8b },
{ 0x70, 0x1c },
};
static int mxl301rf_set_params(struct dvb_frontend *fe)
{
struct reg_val tune0[] = {
{ 0x13, 0x00 }, /* abort tuning */
{ 0x3b, 0xc0 },
{ 0x3b, 0x80 },
{ 0x10, 0x95 }, /* BW */
{ 0x1a, 0x05 },
{ 0x61, 0x00 }, /* spur shift value (placeholder) */
{ 0x62, 0xa0 } /* spur shift direction (placeholder) */
};
struct reg_val tune1[] = {
{ 0x11, 0x40 }, /* RF frequency L (placeholder) */
{ 0x12, 0x0e }, /* RF frequency H (placeholder) */
{ 0x13, 0x01 } /* start tune */
};
struct mxl301rf_state *state;
u32 freq;
u16 f;
u32 tmp, div;
int i, ret;
state = fe->tuner_priv;
freq = fe->dtv_property_cache.frequency;
/* spur shift function (for analog) */
for (i = 0; i < ARRAY_SIZE(shf_tab); i++) {
if (freq >= (shf_tab[i].freq - shf_tab[i].ofst_th) * 1000 &&
freq <= (shf_tab[i].freq + shf_tab[i].ofst_th) * 1000) {
tune0[5].val = shf_tab[i].shf_val;
tune0[6].val = 0xa0 | shf_tab[i].shf_dir;
break;
}
}
ret = raw_write(state, (u8 *) tune0, sizeof(tune0));
if (ret < 0)
goto failed;
usleep_range(3000, 4000);
/* convert freq to 10.6 fixed point float [MHz] */
f = freq / 1000000;
tmp = freq % 1000000;
div = 1000000;
for (i = 0; i < 6; i++) {
f <<= 1;
div >>= 1;
if (tmp > div) {
tmp -= div;
f |= 1;
}
}
if (tmp > 7812)
f++;
tune1[0].val = f & 0xff;
tune1[1].val = f >> 8;
ret = raw_write(state, (u8 *) tune1, sizeof(tune1));
if (ret < 0)
goto failed;
msleep(31);
ret = reg_write(state, 0x1a, 0x0d);
if (ret < 0)
goto failed;
ret = raw_write(state, (u8 *) set_idac, sizeof(set_idac));
if (ret < 0)
goto failed;
return 0;
failed:
dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
__func__, fe->dvb->num, fe->id);
return ret;
}
static const struct reg_val standby_data[] = {
{ 0x01, 0x00 },
{ 0x13, 0x00 }
};
static int mxl301rf_sleep(struct dvb_frontend *fe)
{
struct mxl301rf_state *state;
int ret;
state = fe->tuner_priv;
ret = raw_write(state, (u8 *)standby_data, sizeof(standby_data));
if (ret < 0)
dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
__func__, fe->dvb->num, fe->id);
return ret;
}
/* init sequence is not public.
* the parent must have init'ed the device.
* just wake up here.
*/
static int mxl301rf_init(struct dvb_frontend *fe)
{
struct mxl301rf_state *state;
int ret;
state = fe->tuner_priv;
ret = reg_write(state, 0x01, 0x01);
if (ret < 0) {
dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
__func__, fe->dvb->num, fe->id);
return ret;
}
return 0;
}
/* I2C driver functions */
static const struct dvb_tuner_ops mxl301rf_ops = {
.info = {
.name = "MaxLinear MxL301RF",
.frequency_min = 93000000,
.frequency_max = 803142857,
},
.init = mxl301rf_init,
.sleep = mxl301rf_sleep,
.set_params = mxl301rf_set_params,
.get_rf_strength = mxl301rf_get_rf_strength,
};
static int mxl301rf_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct mxl301rf_state *state;
struct mxl301rf_config *cfg;
struct dvb_frontend *fe;
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return -ENOMEM;
state->i2c = client;
cfg = client->dev.platform_data;
memcpy(&state->cfg, cfg, sizeof(state->cfg));
fe = cfg->fe;
fe->tuner_priv = state;
memcpy(&fe->ops.tuner_ops, &mxl301rf_ops, sizeof(mxl301rf_ops));
i2c_set_clientdata(client, &state->cfg);
dev_info(&client->dev, "MaxLinear MxL301RF attached.\n");
return 0;
}
static int mxl301rf_remove(struct i2c_client *client)
{
struct mxl301rf_state *state;
state = cfg_to_state(i2c_get_clientdata(client));
state->cfg.fe->tuner_priv = NULL;
kfree(state);
return 0;
}
static const struct i2c_device_id mxl301rf_id[] = {
{"mxl301rf", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, mxl301rf_id);
static struct i2c_driver mxl301rf_driver = {
.driver = {
.name = "mxl301rf",
},
.probe = mxl301rf_probe,
.remove = mxl301rf_remove,
.id_table = mxl301rf_id,
};
module_i2c_driver(mxl301rf_driver);
MODULE_DESCRIPTION("MaxLinear MXL301RF tuner");
MODULE_AUTHOR("Akihiro TSUKADA");
MODULE_LICENSE("GPL");

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/*
* MaxLinear MxL301RF OFDM tuner driver
*
* Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MXL301RF_H
#define MXL301RF_H
#include "dvb_frontend.h"
struct mxl301rf_config {
struct dvb_frontend *fe;
};
#endif /* MXL301RF_H */

4119
drivers/media/tuners/mxl5005s.c Normal file
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136
drivers/media/tuners/mxl5005s.h Normal file
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/*
MaxLinear MXL5005S VSB/QAM/DVBT tuner driver
Copyright (C) 2008 MaxLinear
Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MXL5005S_H
#define __MXL5005S_H
#include <linux/kconfig.h>
#include <linux/i2c.h>
#include "dvb_frontend.h"
struct mxl5005s_config {
/* 7 bit i2c address */
u8 i2c_address;
#define IF_FREQ_4570000HZ 4570000
#define IF_FREQ_4571429HZ 4571429
#define IF_FREQ_5380000HZ 5380000
#define IF_FREQ_36000000HZ 36000000
#define IF_FREQ_36125000HZ 36125000
#define IF_FREQ_36166667HZ 36166667
#define IF_FREQ_44000000HZ 44000000
u32 if_freq;
#define CRYSTAL_FREQ_4000000HZ 4000000
#define CRYSTAL_FREQ_16000000HZ 16000000
#define CRYSTAL_FREQ_25000000HZ 25000000
#define CRYSTAL_FREQ_28800000HZ 28800000
u32 xtal_freq;
#define MXL_DUAL_AGC 0
#define MXL_SINGLE_AGC 1
u8 agc_mode;
#define MXL_TF_DEFAULT 0
#define MXL_TF_OFF 1
#define MXL_TF_C 2
#define MXL_TF_C_H 3
#define MXL_TF_D 4
#define MXL_TF_D_L 5
#define MXL_TF_E 6
#define MXL_TF_F 7
#define MXL_TF_E_2 8
#define MXL_TF_E_NA 9
#define MXL_TF_G 10
u8 tracking_filter;
#define MXL_RSSI_DISABLE 0
#define MXL_RSSI_ENABLE 1
u8 rssi_enable;
#define MXL_CAP_SEL_DISABLE 0
#define MXL_CAP_SEL_ENABLE 1
u8 cap_select;
#define MXL_DIV_OUT_1 0
#define MXL_DIV_OUT_4 1
u8 div_out;
#define MXL_CLOCK_OUT_DISABLE 0
#define MXL_CLOCK_OUT_ENABLE 1
u8 clock_out;
#define MXL5005S_IF_OUTPUT_LOAD_200_OHM 200
#define MXL5005S_IF_OUTPUT_LOAD_300_OHM 300
u32 output_load;
#define MXL5005S_TOP_5P5 55
#define MXL5005S_TOP_7P2 72
#define MXL5005S_TOP_9P2 92
#define MXL5005S_TOP_11P0 110
#define MXL5005S_TOP_12P9 129
#define MXL5005S_TOP_14P7 147
#define MXL5005S_TOP_16P8 168
#define MXL5005S_TOP_19P4 194
#define MXL5005S_TOP_21P2 212
#define MXL5005S_TOP_23P2 232
#define MXL5005S_TOP_25P2 252
#define MXL5005S_TOP_27P1 271
#define MXL5005S_TOP_29P2 292
#define MXL5005S_TOP_31P7 317
#define MXL5005S_TOP_34P9 349
u32 top;
#define MXL_ANALOG_MODE 0
#define MXL_DIGITAL_MODE 1
u8 mod_mode;
#define MXL_ZERO_IF 0
#define MXL_LOW_IF 1
u8 if_mode;
/* Some boards need to override the built-in logic for determining
the gain when in QAM mode (the HVR-1600 is one such case) */
u8 qam_gain;
/* Stuff I don't know what to do with */
u8 AgcMasterByte;
};
#if IS_ENABLED(CONFIG_MEDIA_TUNER_MXL5005S)
extern struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
struct mxl5005s_config *config);
#else
static inline struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
struct mxl5005s_config *config)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif /* CONFIG_DVB_TUNER_MXL5005S */
#endif /* __MXL5005S_H */

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drivers/media/tuners/mxl5007t.c Normal file
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/*
* mxl5007t.c - driver for the MaxLinear MxL5007T silicon tuner
*
* Copyright (C) 2008, 2009 Michael Krufky <mkrufky@linuxtv.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/i2c.h>
#include <linux/types.h>
#include <linux/videodev2.h>
#include "tuner-i2c.h"
#include "mxl5007t.h"
static DEFINE_MUTEX(mxl5007t_list_mutex);
static LIST_HEAD(hybrid_tuner_instance_list);
static int mxl5007t_debug;
module_param_named(debug, mxl5007t_debug, int, 0644);
MODULE_PARM_DESC(debug, "set debug level");
/* ------------------------------------------------------------------------- */
#define mxl_printk(kern, fmt, arg...) \
printk(kern "%s: " fmt "\n", __func__, ##arg)
#define mxl_err(fmt, arg...) \
mxl_printk(KERN_ERR, "%d: " fmt, __LINE__, ##arg)
#define mxl_warn(fmt, arg...) \
mxl_printk(KERN_WARNING, fmt, ##arg)
#define mxl_info(fmt, arg...) \
mxl_printk(KERN_INFO, fmt, ##arg)
#define mxl_debug(fmt, arg...) \
({ \
if (mxl5007t_debug) \
mxl_printk(KERN_DEBUG, fmt, ##arg); \
})
#define mxl_fail(ret) \
({ \
int __ret; \
__ret = (ret < 0); \
if (__ret) \
mxl_printk(KERN_ERR, "error %d on line %d", \
ret, __LINE__); \
__ret; \
})
/* ------------------------------------------------------------------------- */
#define MHz 1000000
enum mxl5007t_mode {
MxL_MODE_ISDBT = 0,
MxL_MODE_DVBT = 1,
MxL_MODE_ATSC = 2,
MxL_MODE_CABLE = 0x10,
};
enum mxl5007t_chip_version {
MxL_UNKNOWN_ID = 0x00,
MxL_5007_V1_F1 = 0x11,
MxL_5007_V1_F2 = 0x12,
MxL_5007_V4 = 0x14,
MxL_5007_V2_100_F1 = 0x21,
MxL_5007_V2_100_F2 = 0x22,
MxL_5007_V2_200_F1 = 0x23,
MxL_5007_V2_200_F2 = 0x24,
};
struct reg_pair_t {
u8 reg;
u8 val;
};
/* ------------------------------------------------------------------------- */
static struct reg_pair_t init_tab[] = {
{ 0x02, 0x06 },
{ 0x03, 0x48 },
{ 0x05, 0x04 },
{ 0x06, 0x10 },
{ 0x2e, 0x15 }, /* OVERRIDE */
{ 0x30, 0x10 }, /* OVERRIDE */
{ 0x45, 0x58 }, /* OVERRIDE */
{ 0x48, 0x19 }, /* OVERRIDE */
{ 0x52, 0x03 }, /* OVERRIDE */
{ 0x53, 0x44 }, /* OVERRIDE */
{ 0x6a, 0x4b }, /* OVERRIDE */
{ 0x76, 0x00 }, /* OVERRIDE */
{ 0x78, 0x18 }, /* OVERRIDE */
{ 0x7a, 0x17 }, /* OVERRIDE */
{ 0x85, 0x06 }, /* OVERRIDE */
{ 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
{ 0, 0 }
};
static struct reg_pair_t init_tab_cable[] = {
{ 0x02, 0x06 },
{ 0x03, 0x48 },
{ 0x05, 0x04 },
{ 0x06, 0x10 },
{ 0x09, 0x3f },
{ 0x0a, 0x3f },
{ 0x0b, 0x3f },
{ 0x2e, 0x15 }, /* OVERRIDE */
{ 0x30, 0x10 }, /* OVERRIDE */
{ 0x45, 0x58 }, /* OVERRIDE */
{ 0x48, 0x19 }, /* OVERRIDE */
{ 0x52, 0x03 }, /* OVERRIDE */
{ 0x53, 0x44 }, /* OVERRIDE */
{ 0x6a, 0x4b }, /* OVERRIDE */
{ 0x76, 0x00 }, /* OVERRIDE */
{ 0x78, 0x18 }, /* OVERRIDE */
{ 0x7a, 0x17 }, /* OVERRIDE */
{ 0x85, 0x06 }, /* OVERRIDE */
{ 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
{ 0, 0 }
};
/* ------------------------------------------------------------------------- */
static struct reg_pair_t reg_pair_rftune[] = {
{ 0x0f, 0x00 }, /* abort tune */
{ 0x0c, 0x15 },
{ 0x0d, 0x40 },
{ 0x0e, 0x0e },
{ 0x1f, 0x87 }, /* OVERRIDE */
{ 0x20, 0x1f }, /* OVERRIDE */
{ 0x21, 0x87 }, /* OVERRIDE */
{ 0x22, 0x1f }, /* OVERRIDE */
{ 0x80, 0x01 }, /* freq dependent */
{ 0x0f, 0x01 }, /* start tune */
{ 0, 0 }
};
/* ------------------------------------------------------------------------- */
struct mxl5007t_state {
struct list_head hybrid_tuner_instance_list;
struct tuner_i2c_props i2c_props;
struct mutex lock;
struct mxl5007t_config *config;
enum mxl5007t_chip_version chip_id;
struct reg_pair_t tab_init[ARRAY_SIZE(init_tab)];
struct reg_pair_t tab_init_cable[ARRAY_SIZE(init_tab_cable)];
struct reg_pair_t tab_rftune[ARRAY_SIZE(reg_pair_rftune)];
enum mxl5007t_if_freq if_freq;
u32 frequency;
u32 bandwidth;
};
/* ------------------------------------------------------------------------- */
/* called by _init and _rftun to manipulate the register arrays */
static void set_reg_bits(struct reg_pair_t *reg_pair, u8 reg, u8 mask, u8 val)
{
unsigned int i = 0;
while (reg_pair[i].reg || reg_pair[i].val) {
if (reg_pair[i].reg == reg) {
reg_pair[i].val &= ~mask;
reg_pair[i].val |= val;
}
i++;
}
return;
}
static void copy_reg_bits(struct reg_pair_t *reg_pair1,
struct reg_pair_t *reg_pair2)
{
unsigned int i, j;
i = j = 0;
while (reg_pair1[i].reg || reg_pair1[i].val) {
while (reg_pair2[j].reg || reg_pair2[j].val) {
if (reg_pair1[i].reg != reg_pair2[j].reg) {
j++;
continue;
}
reg_pair2[j].val = reg_pair1[i].val;
break;
}
i++;
}
return;
}
/* ------------------------------------------------------------------------- */
static void mxl5007t_set_mode_bits(struct mxl5007t_state *state,
enum mxl5007t_mode mode,
s32 if_diff_out_level)
{
switch (mode) {
case MxL_MODE_ATSC:
set_reg_bits(state->tab_init, 0x06, 0x1f, 0x12);
break;
case MxL_MODE_DVBT:
set_reg_bits(state->tab_init, 0x06, 0x1f, 0x11);
break;
case MxL_MODE_ISDBT:
set_reg_bits(state->tab_init, 0x06, 0x1f, 0x10);
break;
case MxL_MODE_CABLE:
set_reg_bits(state->tab_init_cable, 0x09, 0xff, 0xc1);
set_reg_bits(state->tab_init_cable, 0x0a, 0xff,
8 - if_diff_out_level);
set_reg_bits(state->tab_init_cable, 0x0b, 0xff, 0x17);
break;
default:
mxl_fail(-EINVAL);
}
return;
}
static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state,
enum mxl5007t_if_freq if_freq,
int invert_if)
{
u8 val;
switch (if_freq) {
case MxL_IF_4_MHZ:
val = 0x00;
break;
case MxL_IF_4_5_MHZ:
val = 0x02;
break;
case MxL_IF_4_57_MHZ:
val = 0x03;
break;
case MxL_IF_5_MHZ:
val = 0x04;
break;
case MxL_IF_5_38_MHZ:
val = 0x05;
break;
case MxL_IF_6_MHZ:
val = 0x06;
break;
case MxL_IF_6_28_MHZ:
val = 0x07;
break;
case MxL_IF_9_1915_MHZ:
val = 0x08;
break;
case MxL_IF_35_25_MHZ:
val = 0x09;
break;
case MxL_IF_36_15_MHZ:
val = 0x0a;
break;
case MxL_IF_44_MHZ:
val = 0x0b;
break;
default:
mxl_fail(-EINVAL);
return;
}
set_reg_bits(state->tab_init, 0x02, 0x0f, val);
/* set inverted IF or normal IF */
set_reg_bits(state->tab_init, 0x02, 0x10, invert_if ? 0x10 : 0x00);
state->if_freq = if_freq;
return;
}
static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state,
enum mxl5007t_xtal_freq xtal_freq)
{
switch (xtal_freq) {
case MxL_XTAL_16_MHZ:
/* select xtal freq & ref freq */
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x00);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x00);
break;
case MxL_XTAL_20_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x10);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x01);
break;
case MxL_XTAL_20_25_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x20);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x02);
break;
case MxL_XTAL_20_48_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x30);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x03);
break;
case MxL_XTAL_24_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x40);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x04);
break;
case MxL_XTAL_25_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x50);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x05);
break;
case MxL_XTAL_25_14_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x60);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x06);
break;
case MxL_XTAL_27_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x70);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x07);
break;
case MxL_XTAL_28_8_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x80);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x08);
break;
case MxL_XTAL_32_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x90);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x09);
break;
case MxL_XTAL_40_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0xa0);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0a);
break;
case MxL_XTAL_44_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0xb0);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0b);
break;
case MxL_XTAL_48_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0xc0);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0c);
break;
case MxL_XTAL_49_3811_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0xd0);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0d);
break;
default:
mxl_fail(-EINVAL);
return;
}
return;
}
static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state,
enum mxl5007t_mode mode)
{
struct mxl5007t_config *cfg = state->config;
memcpy(&state->tab_init, &init_tab, sizeof(init_tab));
memcpy(&state->tab_init_cable, &init_tab_cable, sizeof(init_tab_cable));
mxl5007t_set_mode_bits(state, mode, cfg->if_diff_out_level);
mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if);
mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz);
set_reg_bits(state->tab_init, 0x04, 0x01, cfg->loop_thru_enable);
set_reg_bits(state->tab_init, 0x03, 0x08, cfg->clk_out_enable << 3);
set_reg_bits(state->tab_init, 0x03, 0x07, cfg->clk_out_amp);
if (mode >= MxL_MODE_CABLE) {
copy_reg_bits(state->tab_init, state->tab_init_cable);
return state->tab_init_cable;
} else
return state->tab_init;
}
/* ------------------------------------------------------------------------- */
enum mxl5007t_bw_mhz {
MxL_BW_6MHz = 6,
MxL_BW_7MHz = 7,
MxL_BW_8MHz = 8,
};
static void mxl5007t_set_bw_bits(struct mxl5007t_state *state,
enum mxl5007t_bw_mhz bw)
{
u8 val;
switch (bw) {
case MxL_BW_6MHz:
val = 0x15; /* set DIG_MODEINDEX, DIG_MODEINDEX_A,
* and DIG_MODEINDEX_CSF */
break;
case MxL_BW_7MHz:
val = 0x2a;
break;
case MxL_BW_8MHz:
val = 0x3f;
break;
default:
mxl_fail(-EINVAL);
return;
}
set_reg_bits(state->tab_rftune, 0x0c, 0x3f, val);
return;
}
static struct
reg_pair_t *mxl5007t_calc_rf_tune_regs(struct mxl5007t_state *state,
u32 rf_freq, enum mxl5007t_bw_mhz bw)
{
u32 dig_rf_freq = 0;
u32 temp;
u32 frac_divider = 1000000;
unsigned int i;
memcpy(&state->tab_rftune, &reg_pair_rftune, sizeof(reg_pair_rftune));
mxl5007t_set_bw_bits(state, bw);
/* Convert RF frequency into 16 bits =>
* 10 bit integer (MHz) + 6 bit fraction */
dig_rf_freq = rf_freq / MHz;
temp = rf_freq % MHz;
for (i = 0; i < 6; i++) {
dig_rf_freq <<= 1;
frac_divider /= 2;
if (temp > frac_divider) {
temp -= frac_divider;
dig_rf_freq++;
}
}
/* add to have shift center point by 7.8124 kHz */
if (temp > 7812)
dig_rf_freq++;
set_reg_bits(state->tab_rftune, 0x0d, 0xff, (u8) dig_rf_freq);
set_reg_bits(state->tab_rftune, 0x0e, 0xff, (u8) (dig_rf_freq >> 8));
if (rf_freq >= 333000000)
set_reg_bits(state->tab_rftune, 0x80, 0x40, 0x40);
return state->tab_rftune;
}
/* ------------------------------------------------------------------------- */
static int mxl5007t_write_reg(struct mxl5007t_state *state, u8 reg, u8 val)
{
u8 buf[] = { reg, val };
struct i2c_msg msg = { .addr = state->i2c_props.addr, .flags = 0,
.buf = buf, .len = 2 };
int ret;
ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
if (ret != 1) {
mxl_err("failed!");
return -EREMOTEIO;
}
return 0;
}
static int mxl5007t_write_regs(struct mxl5007t_state *state,
struct reg_pair_t *reg_pair)
{
unsigned int i = 0;
int ret = 0;
while ((ret == 0) && (reg_pair[i].reg || reg_pair[i].val)) {
ret = mxl5007t_write_reg(state,
reg_pair[i].reg, reg_pair[i].val);
i++;
}
return ret;
}
static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val)
{
u8 buf[2] = { 0xfb, reg };
struct i2c_msg msg[] = {
{ .addr = state->i2c_props.addr, .flags = 0,
.buf = buf, .len = 2 },
{ .addr = state->i2c_props.addr, .flags = I2C_M_RD,
.buf = val, .len = 1 },
};
int ret;
ret = i2c_transfer(state->i2c_props.adap, msg, 2);
if (ret != 2) {
mxl_err("failed!");
return -EREMOTEIO;
}
return 0;
}
static int mxl5007t_soft_reset(struct mxl5007t_state *state)
{
u8 d = 0xff;
struct i2c_msg msg = {
.addr = state->i2c_props.addr, .flags = 0,
.buf = &d, .len = 1
};
int ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
if (ret != 1) {
mxl_err("failed!");
return -EREMOTEIO;
}
return 0;
}
static int mxl5007t_tuner_init(struct mxl5007t_state *state,
enum mxl5007t_mode mode)
{
struct reg_pair_t *init_regs;
int ret;
ret = mxl5007t_soft_reset(state);
if (mxl_fail(ret))
goto fail;
/* calculate initialization reg array */
init_regs = mxl5007t_calc_init_regs(state, mode);
ret = mxl5007t_write_regs(state, init_regs);
if (mxl_fail(ret))
goto fail;
mdelay(1);
fail:
return ret;
}
static int mxl5007t_tuner_rf_tune(struct mxl5007t_state *state, u32 rf_freq_hz,
enum mxl5007t_bw_mhz bw)
{
struct reg_pair_t *rf_tune_regs;
int ret;
/* calculate channel change reg array */
rf_tune_regs = mxl5007t_calc_rf_tune_regs(state, rf_freq_hz, bw);
ret = mxl5007t_write_regs(state, rf_tune_regs);
if (mxl_fail(ret))
goto fail;
msleep(3);
fail:
return ret;
}
/* ------------------------------------------------------------------------- */
static int mxl5007t_synth_lock_status(struct mxl5007t_state *state,
int *rf_locked, int *ref_locked)
{
u8 d;
int ret;
*rf_locked = 0;
*ref_locked = 0;
ret = mxl5007t_read_reg(state, 0xd8, &d);
if (mxl_fail(ret))
goto fail;
if ((d & 0x0c) == 0x0c)
*rf_locked = 1;
if ((d & 0x03) == 0x03)
*ref_locked = 1;
fail:
return ret;
}
/* ------------------------------------------------------------------------- */
static int mxl5007t_get_status(struct dvb_frontend *fe, u32 *status)
{
struct mxl5007t_state *state = fe->tuner_priv;
int rf_locked, ref_locked, ret;
*status = 0;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
ret = mxl5007t_synth_lock_status(state, &rf_locked, &ref_locked);
if (mxl_fail(ret))
goto fail;
mxl_debug("%s%s", rf_locked ? "rf locked " : "",
ref_locked ? "ref locked" : "");
if ((rf_locked) || (ref_locked))
*status |= TUNER_STATUS_LOCKED;
fail:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return ret;
}
/* ------------------------------------------------------------------------- */
static int mxl5007t_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u32 delsys = c->delivery_system;
struct mxl5007t_state *state = fe->tuner_priv;
enum mxl5007t_bw_mhz bw;
enum mxl5007t_mode mode;
int ret;
u32 freq = c->frequency;
switch (delsys) {
case SYS_ATSC:
mode = MxL_MODE_ATSC;
bw = MxL_BW_6MHz;
break;
case SYS_DVBC_ANNEX_B:
mode = MxL_MODE_CABLE;
bw = MxL_BW_6MHz;
break;
case SYS_DVBT:
case SYS_DVBT2:
mode = MxL_MODE_DVBT;
switch (c->bandwidth_hz) {
case 6000000:
bw = MxL_BW_6MHz;
break;
case 7000000:
bw = MxL_BW_7MHz;
break;
case 8000000:
bw = MxL_BW_8MHz;
break;
default:
return -EINVAL;
}
break;
default:
mxl_err("modulation type not supported!");
return -EINVAL;
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
mutex_lock(&state->lock);
ret = mxl5007t_tuner_init(state, mode);
if (mxl_fail(ret))
goto fail;
ret = mxl5007t_tuner_rf_tune(state, freq, bw);
if (mxl_fail(ret))
goto fail;
state->frequency = freq;
state->bandwidth = c->bandwidth_hz;
fail:
mutex_unlock(&state->lock);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return ret;
}
/* ------------------------------------------------------------------------- */
static int mxl5007t_init(struct dvb_frontend *fe)
{
struct mxl5007t_state *state = fe->tuner_priv;
int ret;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
/* wake from standby */
ret = mxl5007t_write_reg(state, 0x01, 0x01);
mxl_fail(ret);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return ret;
}
static int mxl5007t_sleep(struct dvb_frontend *fe)
{
struct mxl5007t_state *state = fe->tuner_priv;
int ret;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
/* enter standby mode */
ret = mxl5007t_write_reg(state, 0x01, 0x00);
mxl_fail(ret);
ret = mxl5007t_write_reg(state, 0x0f, 0x00);
mxl_fail(ret);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return ret;
}
/* ------------------------------------------------------------------------- */
static int mxl5007t_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct mxl5007t_state *state = fe->tuner_priv;
*frequency = state->frequency;
return 0;
}
static int mxl5007t_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
{
struct mxl5007t_state *state = fe->tuner_priv;
*bandwidth = state->bandwidth;
return 0;
}
static int mxl5007t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct mxl5007t_state *state = fe->tuner_priv;
*frequency = 0;
switch (state->if_freq) {
case MxL_IF_4_MHZ:
*frequency = 4000000;
break;
case MxL_IF_4_5_MHZ:
*frequency = 4500000;
break;
case MxL_IF_4_57_MHZ:
*frequency = 4570000;
break;
case MxL_IF_5_MHZ:
*frequency = 5000000;
break;
case MxL_IF_5_38_MHZ:
*frequency = 5380000;
break;
case MxL_IF_6_MHZ:
*frequency = 6000000;
break;
case MxL_IF_6_28_MHZ:
*frequency = 6280000;
break;
case MxL_IF_9_1915_MHZ:
*frequency = 9191500;
break;
case MxL_IF_35_25_MHZ:
*frequency = 35250000;
break;
case MxL_IF_36_15_MHZ:
*frequency = 36150000;
break;
case MxL_IF_44_MHZ:
*frequency = 44000000;
break;
}
return 0;
}
static int mxl5007t_release(struct dvb_frontend *fe)
{
struct mxl5007t_state *state = fe->tuner_priv;
mutex_lock(&mxl5007t_list_mutex);
if (state)
hybrid_tuner_release_state(state);
mutex_unlock(&mxl5007t_list_mutex);
fe->tuner_priv = NULL;
return 0;
}
/* ------------------------------------------------------------------------- */
static struct dvb_tuner_ops mxl5007t_tuner_ops = {
.info = {
.name = "MaxLinear MxL5007T",
},
.init = mxl5007t_init,
.sleep = mxl5007t_sleep,
.set_params = mxl5007t_set_params,
.get_status = mxl5007t_get_status,
.get_frequency = mxl5007t_get_frequency,
.get_bandwidth = mxl5007t_get_bandwidth,
.release = mxl5007t_release,
.get_if_frequency = mxl5007t_get_if_frequency,
};
static int mxl5007t_get_chip_id(struct mxl5007t_state *state)
{
char *name;
int ret;
u8 id;
ret = mxl5007t_read_reg(state, 0xd9, &id);
if (mxl_fail(ret))
goto fail;
switch (id) {
case MxL_5007_V1_F1:
name = "MxL5007.v1.f1";
break;
case MxL_5007_V1_F2:
name = "MxL5007.v1.f2";
break;
case MxL_5007_V2_100_F1:
name = "MxL5007.v2.100.f1";
break;
case MxL_5007_V2_100_F2:
name = "MxL5007.v2.100.f2";
break;
case MxL_5007_V2_200_F1:
name = "MxL5007.v2.200.f1";
break;
case MxL_5007_V2_200_F2:
name = "MxL5007.v2.200.f2";
break;
case MxL_5007_V4:
name = "MxL5007T.v4";
break;
default:
name = "MxL5007T";
printk(KERN_WARNING "%s: unknown rev (%02x)\n", __func__, id);
id = MxL_UNKNOWN_ID;
}
state->chip_id = id;
mxl_info("%s detected @ %d-%04x", name,
i2c_adapter_id(state->i2c_props.adap),
state->i2c_props.addr);
return 0;
fail:
mxl_warn("unable to identify device @ %d-%04x",
i2c_adapter_id(state->i2c_props.adap),
state->i2c_props.addr);
state->chip_id = MxL_UNKNOWN_ID;
return ret;
}
struct dvb_frontend *mxl5007t_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 addr,
struct mxl5007t_config *cfg)
{
struct mxl5007t_state *state = NULL;
int instance, ret;
mutex_lock(&mxl5007t_list_mutex);
instance = hybrid_tuner_request_state(struct mxl5007t_state, state,
hybrid_tuner_instance_list,
i2c, addr, "mxl5007t");
switch (instance) {
case 0:
goto fail;
case 1:
/* new tuner instance */
state->config = cfg;
mutex_init(&state->lock);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
ret = mxl5007t_get_chip_id(state);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
/* check return value of mxl5007t_get_chip_id */
if (mxl_fail(ret))
goto fail;
break;
default:
/* existing tuner instance */
break;
}
fe->tuner_priv = state;
mutex_unlock(&mxl5007t_list_mutex);
memcpy(&fe->ops.tuner_ops, &mxl5007t_tuner_ops,
sizeof(struct dvb_tuner_ops));
return fe;
fail:
mutex_unlock(&mxl5007t_list_mutex);
mxl5007t_release(fe);
return NULL;
}
EXPORT_SYMBOL_GPL(mxl5007t_attach);
MODULE_DESCRIPTION("MaxLinear MxL5007T Silicon IC tuner driver");
MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
MODULE_LICENSE("GPL");
MODULE_VERSION("0.2");
/*
* Overrides for Emacs so that we follow Linus's tabbing style.
* ---------------------------------------------------------------------------
* Local variables:
* c-basic-offset: 8
* End:
*/

104
drivers/media/tuners/mxl5007t.h Normal file
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@ -0,0 +1,104 @@
/*
* mxl5007t.h - driver for the MaxLinear MxL5007T silicon tuner
*
* Copyright (C) 2008 Michael Krufky <mkrufky@linuxtv.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MXL5007T_H__
#define __MXL5007T_H__
#include "dvb_frontend.h"
/* ------------------------------------------------------------------------- */
enum mxl5007t_if_freq {
MxL_IF_4_MHZ, /* 4000000 */
MxL_IF_4_5_MHZ, /* 4500000 */
MxL_IF_4_57_MHZ, /* 4570000 */
MxL_IF_5_MHZ, /* 5000000 */
MxL_IF_5_38_MHZ, /* 5380000 */
MxL_IF_6_MHZ, /* 6000000 */
MxL_IF_6_28_MHZ, /* 6280000 */
MxL_IF_9_1915_MHZ, /* 9191500 */
MxL_IF_35_25_MHZ, /* 35250000 */
MxL_IF_36_15_MHZ, /* 36150000 */
MxL_IF_44_MHZ, /* 44000000 */
};
enum mxl5007t_xtal_freq {
MxL_XTAL_16_MHZ, /* 16000000 */
MxL_XTAL_20_MHZ, /* 20000000 */
MxL_XTAL_20_25_MHZ, /* 20250000 */
MxL_XTAL_20_48_MHZ, /* 20480000 */
MxL_XTAL_24_MHZ, /* 24000000 */
MxL_XTAL_25_MHZ, /* 25000000 */
MxL_XTAL_25_14_MHZ, /* 25140000 */
MxL_XTAL_27_MHZ, /* 27000000 */
MxL_XTAL_28_8_MHZ, /* 28800000 */
MxL_XTAL_32_MHZ, /* 32000000 */
MxL_XTAL_40_MHZ, /* 40000000 */
MxL_XTAL_44_MHZ, /* 44000000 */
MxL_XTAL_48_MHZ, /* 48000000 */
MxL_XTAL_49_3811_MHZ, /* 49381100 */
};
enum mxl5007t_clkout_amp {
MxL_CLKOUT_AMP_0_94V = 0,
MxL_CLKOUT_AMP_0_53V = 1,
MxL_CLKOUT_AMP_0_37V = 2,
MxL_CLKOUT_AMP_0_28V = 3,
MxL_CLKOUT_AMP_0_23V = 4,
MxL_CLKOUT_AMP_0_20V = 5,
MxL_CLKOUT_AMP_0_17V = 6,
MxL_CLKOUT_AMP_0_15V = 7,
};
struct mxl5007t_config {
s32 if_diff_out_level;
enum mxl5007t_clkout_amp clk_out_amp;
enum mxl5007t_xtal_freq xtal_freq_hz;
enum mxl5007t_if_freq if_freq_hz;
unsigned int invert_if:1;
unsigned int loop_thru_enable:1;
unsigned int clk_out_enable:1;
};
#if IS_ENABLED(CONFIG_MEDIA_TUNER_MXL5007T)
extern struct dvb_frontend *mxl5007t_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 addr,
struct mxl5007t_config *cfg);
#else
static inline struct dvb_frontend *mxl5007t_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
u8 addr,
struct mxl5007t_config *cfg)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif /* __MXL5007T_H__ */
/*
* Overrides for Emacs so that we follow Linus's tabbing style.
* ---------------------------------------------------------------------------
* Local variables:
* c-basic-offset: 8
* End:
*/

448
drivers/media/tuners/qm1d1c0042.c Normal file
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@ -0,0 +1,448 @@
/*
* Sharp QM1D1C0042 8PSK tuner driver
*
* Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* NOTICE:
* As the disclosed information on the chip is very limited,
* this driver lacks some features, including chip config like IF freq.
* It assumes that users of this driver (such as a PCI bridge of
* DTV receiver cards) know the relevant info and
* configure the chip via I2C if necessary.
*
* Currently, PT3 driver is the only one that uses this driver,
* and contains init/config code in its firmware.
* Thus some part of the code might be dependent on PT3 specific config.
*/
#include <linux/kernel.h>
#include <linux/math64.h>
#include "qm1d1c0042.h"
#define QM1D1C0042_NUM_REGS 0x20
static const u8 reg_initval[QM1D1C0042_NUM_REGS] = {
0x48, 0x1c, 0xa0, 0x10, 0xbc, 0xc5, 0x20, 0x33,
0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
0x00, 0xff, 0xf3, 0x00, 0x2a, 0x64, 0xa6, 0x86,
0x8c, 0xcf, 0xb8, 0xf1, 0xa8, 0xf2, 0x89, 0x00
};
static const struct qm1d1c0042_config default_cfg = {
.xtal_freq = 16000,
.lpf = 1,
.fast_srch = 0,
.lpf_wait = 20,
.fast_srch_wait = 4,
.normal_srch_wait = 15,
};
struct qm1d1c0042_state {
struct qm1d1c0042_config cfg;
struct i2c_client *i2c;
u8 regs[QM1D1C0042_NUM_REGS];
};
static struct qm1d1c0042_state *cfg_to_state(struct qm1d1c0042_config *c)
{
return container_of(c, struct qm1d1c0042_state, cfg);
}
static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val)
{
u8 wbuf[2] = { reg, val };
int ret;
ret = i2c_master_send(state->i2c, wbuf, sizeof(wbuf));
if (ret >= 0 && ret < sizeof(wbuf))
ret = -EIO;
return (ret == sizeof(wbuf)) ? 0 : ret;
}
static int reg_read(struct qm1d1c0042_state *state, u8 reg, u8 *val)
{
struct i2c_msg msgs[2] = {
{
.addr = state->i2c->addr,
.flags = 0,
.buf = &reg,
.len = 1,
},
{
.addr = state->i2c->addr,
.flags = I2C_M_RD,
.buf = val,
.len = 1,
},
};
int ret;
ret = i2c_transfer(state->i2c->adapter, msgs, ARRAY_SIZE(msgs));
if (ret >= 0 && ret < ARRAY_SIZE(msgs))
ret = -EIO;
return (ret == ARRAY_SIZE(msgs)) ? 0 : ret;
}
static int qm1d1c0042_set_srch_mode(struct qm1d1c0042_state *state, bool fast)
{
if (fast)
state->regs[0x03] |= 0x01; /* set fast search mode */
else
state->regs[0x03] &= ~0x01 & 0xff;
return reg_write(state, 0x03, state->regs[0x03]);
}
static int qm1d1c0042_wakeup(struct qm1d1c0042_state *state)
{
int ret;
state->regs[0x01] |= 1 << 3; /* BB_Reg_enable */
state->regs[0x01] &= (~(1 << 0)) & 0xff; /* NORMAL (wake-up) */
state->regs[0x05] &= (~(1 << 3)) & 0xff; /* pfd_rst NORMAL */
ret = reg_write(state, 0x01, state->regs[0x01]);
if (ret == 0)
ret = reg_write(state, 0x05, state->regs[0x05]);
if (ret < 0)
dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
__func__, state->cfg.fe->dvb->num, state->cfg.fe->id);
return ret;
}
/* tuner_ops */
static int qm1d1c0042_set_config(struct dvb_frontend *fe, void *priv_cfg)
{
struct qm1d1c0042_state *state;
struct qm1d1c0042_config *cfg;
state = fe->tuner_priv;
cfg = priv_cfg;
if (cfg->fe)
state->cfg.fe = cfg->fe;
if (cfg->xtal_freq != QM1D1C0042_CFG_XTAL_DFLT)
dev_warn(&state->i2c->dev,
"(%s) changing xtal_freq not supported. ", __func__);
state->cfg.xtal_freq = default_cfg.xtal_freq;
state->cfg.lpf = cfg->lpf;
state->cfg.fast_srch = cfg->fast_srch;
if (cfg->lpf_wait != QM1D1C0042_CFG_WAIT_DFLT)
state->cfg.lpf_wait = cfg->lpf_wait;
else
state->cfg.lpf_wait = default_cfg.lpf_wait;
if (cfg->fast_srch_wait != QM1D1C0042_CFG_WAIT_DFLT)
state->cfg.fast_srch_wait = cfg->fast_srch_wait;
else
state->cfg.fast_srch_wait = default_cfg.fast_srch_wait;
if (cfg->normal_srch_wait != QM1D1C0042_CFG_WAIT_DFLT)
state->cfg.normal_srch_wait = cfg->normal_srch_wait;
else
state->cfg.normal_srch_wait = default_cfg.normal_srch_wait;
return 0;
}
/* divisor, vco_band parameters */
/* {maxfreq, param1(band?), param2(div?) */
static const u32 conv_table[9][3] = {
{ 2151000, 1, 7 },
{ 1950000, 1, 6 },
{ 1800000, 1, 5 },
{ 1600000, 1, 4 },
{ 1450000, 1, 3 },
{ 1250000, 1, 2 },
{ 1200000, 0, 7 },
{ 975000, 0, 6 },
{ 950000, 0, 0 }
};
static int qm1d1c0042_set_params(struct dvb_frontend *fe)
{
struct qm1d1c0042_state *state;
u32 freq;
int i, ret;
u8 val, mask;
u32 a, sd;
s32 b;
state = fe->tuner_priv;
freq = fe->dtv_property_cache.frequency;
state->regs[0x08] &= 0xf0;
state->regs[0x08] |= 0x09;
state->regs[0x13] &= 0x9f;
state->regs[0x13] |= 0x20;
/* div2/vco_band */
val = state->regs[0x02] & 0x0f;
for (i = 0; i < 8; i++)
if (freq < conv_table[i][0] && freq >= conv_table[i + 1][0]) {
val |= conv_table[i][1] << 7;
val |= conv_table[i][2] << 4;
break;
}
ret = reg_write(state, 0x02, val);
if (ret < 0)
return ret;
a = (freq + state->cfg.xtal_freq / 2) / state->cfg.xtal_freq;
state->regs[0x06] &= 0x40;
state->regs[0x06] |= (a - 12) / 4;
ret = reg_write(state, 0x06, state->regs[0x06]);
if (ret < 0)
return ret;
state->regs[0x07] &= 0xf0;
state->regs[0x07] |= (a - 4 * ((a - 12) / 4 + 1) - 5) & 0x0f;
ret = reg_write(state, 0x07, state->regs[0x07]);
if (ret < 0)
return ret;
/* LPF */
val = state->regs[0x08];
if (state->cfg.lpf) {
/* LPF_CLK, LPF_FC */
val &= 0xf0;
val |= 0x02;
}
ret = reg_write(state, 0x08, val);
if (ret < 0)
return ret;
/*
* b = (freq / state->cfg.xtal_freq - a) << 20;
* sd = b (b >= 0)
* 1<<22 + b (b < 0)
*/
b = (s32)div64_s64(((s64) freq) << 20, state->cfg.xtal_freq)
- (((s64) a) << 20);
if (b >= 0)
sd = b;
else
sd = (1 << 22) + b;
state->regs[0x09] &= 0xc0;
state->regs[0x09] |= (sd >> 16) & 0x3f;
state->regs[0x0a] = (sd >> 8) & 0xff;
state->regs[0x0b] = sd & 0xff;
ret = reg_write(state, 0x09, state->regs[0x09]);
if (ret == 0)
ret = reg_write(state, 0x0a, state->regs[0x0a]);
if (ret == 0)
ret = reg_write(state, 0x0b, state->regs[0x0b]);
if (ret != 0)
return ret;
if (!state->cfg.lpf) {
/* CSEL_Offset */
ret = reg_write(state, 0x13, state->regs[0x13]);
if (ret < 0)
return ret;
}
/* VCO_TM, LPF_TM */
mask = state->cfg.lpf ? 0x3f : 0x7f;
val = state->regs[0x0c] & mask;
ret = reg_write(state, 0x0c, val);
if (ret < 0)
return ret;
usleep_range(2000, 3000);
val = state->regs[0x0c] | ~mask;
ret = reg_write(state, 0x0c, val);
if (ret < 0)
return ret;
if (state->cfg.lpf)
msleep(state->cfg.lpf_wait);
else if (state->regs[0x03] & 0x01)
msleep(state->cfg.fast_srch_wait);
else
msleep(state->cfg.normal_srch_wait);
if (state->cfg.lpf) {
/* LPF_FC */
ret = reg_write(state, 0x08, 0x09);
if (ret < 0)
return ret;
/* CSEL_Offset */
ret = reg_write(state, 0x13, state->regs[0x13]);
if (ret < 0)
return ret;
}
return 0;
}
static int qm1d1c0042_sleep(struct dvb_frontend *fe)
{
struct qm1d1c0042_state *state;
int ret;
state = fe->tuner_priv;
state->regs[0x01] &= (~(1 << 3)) & 0xff; /* BB_Reg_disable */
state->regs[0x01] |= 1 << 0; /* STDBY */
state->regs[0x05] |= 1 << 3; /* pfd_rst STANDBY */
ret = reg_write(state, 0x05, state->regs[0x05]);
if (ret == 0)
ret = reg_write(state, 0x01, state->regs[0x01]);
if (ret < 0)
dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
__func__, fe->dvb->num, fe->id);
return ret;
}
static int qm1d1c0042_init(struct dvb_frontend *fe)
{
struct qm1d1c0042_state *state;
u8 val;
int i, ret;
state = fe->tuner_priv;
memcpy(state->regs, reg_initval, sizeof(reg_initval));
reg_write(state, 0x01, 0x0c);
reg_write(state, 0x01, 0x0c);
ret = reg_write(state, 0x01, 0x0c); /* soft reset on */
if (ret < 0)
goto failed;
usleep_range(2000, 3000);
val = state->regs[0x01] | 0x10;
ret = reg_write(state, 0x01, val); /* soft reset off */
if (ret < 0)
goto failed;
/* check ID */
ret = reg_read(state, 0x00, &val);
if (ret < 0 || val != 0x48)
goto failed;
usleep_range(2000, 3000);
state->regs[0x0c] |= 0x40;
ret = reg_write(state, 0x0c, state->regs[0x0c]);
if (ret < 0)
goto failed;
msleep(state->cfg.lpf_wait);
/* set all writable registers */
for (i = 1; i <= 0x0c ; i++) {
ret = reg_write(state, i, state->regs[i]);
if (ret < 0)
goto failed;
}
for (i = 0x11; i < QM1D1C0042_NUM_REGS; i++) {
ret = reg_write(state, i, state->regs[i]);
if (ret < 0)
goto failed;
}
ret = qm1d1c0042_wakeup(state);
if (ret < 0)
goto failed;
ret = qm1d1c0042_set_srch_mode(state, state->cfg.fast_srch);
if (ret < 0)
goto failed;
return ret;
failed:
dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
__func__, fe->dvb->num, fe->id);
return ret;
}
/* I2C driver functions */
static const struct dvb_tuner_ops qm1d1c0042_ops = {
.info = {
.name = "Sharp QM1D1C0042",
.frequency_min = 950000,
.frequency_max = 2150000,
},
.init = qm1d1c0042_init,
.sleep = qm1d1c0042_sleep,
.set_config = qm1d1c0042_set_config,
.set_params = qm1d1c0042_set_params,
};
static int qm1d1c0042_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct qm1d1c0042_state *state;
struct qm1d1c0042_config *cfg;
struct dvb_frontend *fe;
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return -ENOMEM;
state->i2c = client;
cfg = client->dev.platform_data;
fe = cfg->fe;
fe->tuner_priv = state;
qm1d1c0042_set_config(fe, cfg);
memcpy(&fe->ops.tuner_ops, &qm1d1c0042_ops, sizeof(qm1d1c0042_ops));
i2c_set_clientdata(client, &state->cfg);
dev_info(&client->dev, "Sharp QM1D1C0042 attached.\n");
return 0;
}
static int qm1d1c0042_remove(struct i2c_client *client)
{
struct qm1d1c0042_state *state;
state = cfg_to_state(i2c_get_clientdata(client));
state->cfg.fe->tuner_priv = NULL;
kfree(state);
return 0;
}
static const struct i2c_device_id qm1d1c0042_id[] = {
{"qm1d1c0042", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, qm1d1c0042_id);
static struct i2c_driver qm1d1c0042_driver = {
.driver = {
.name = "qm1d1c0042",
},
.probe = qm1d1c0042_probe,
.remove = qm1d1c0042_remove,
.id_table = qm1d1c0042_id,
};
module_i2c_driver(qm1d1c0042_driver);
MODULE_DESCRIPTION("Sharp QM1D1C0042 tuner");
MODULE_AUTHOR("Akihiro TSUKADA");
MODULE_LICENSE("GPL");

37
drivers/media/tuners/qm1d1c0042.h Normal file
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@ -0,0 +1,37 @@
/*
* Sharp QM1D1C0042 8PSK tuner driver
*
* Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef QM1D1C0042_H
#define QM1D1C0042_H
#include "dvb_frontend.h"
struct qm1d1c0042_config {
struct dvb_frontend *fe;
u32 xtal_freq; /* [kHz] */ /* currently ignored */
bool lpf; /* enable LPF */
bool fast_srch; /* enable fast search mode, no LPF */
u32 lpf_wait; /* wait in tuning with LPF enabled. [ms] */
u32 fast_srch_wait; /* with fast-search mode, no LPF. [ms] */
u32 normal_srch_wait; /* with no LPF/fast-search mode. [ms] */
};
/* special values indicating to use the default in qm1d1c0042_config */
#define QM1D1C0042_CFG_XTAL_DFLT 0
#define QM1D1C0042_CFG_WAIT_DFLT 0
#endif /* QM1D1C0042_H */

456
drivers/media/tuners/qt1010.c Normal file
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/*
* Driver for Quantek QT1010 silicon tuner
*
* Copyright (C) 2006 Antti Palosaari <crope@iki.fi>
* Aapo Tahkola <aet@rasterburn.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include "qt1010.h"
#include "qt1010_priv.h"
/* read single register */
static int qt1010_readreg(struct qt1010_priv *priv, u8 reg, u8 *val)
{
struct i2c_msg msg[2] = {
{ .addr = priv->cfg->i2c_address,
.flags = 0, .buf = &reg, .len = 1 },
{ .addr = priv->cfg->i2c_address,
.flags = I2C_M_RD, .buf = val, .len = 1 },
};
if (i2c_transfer(priv->i2c, msg, 2) != 2) {
dev_warn(&priv->i2c->dev, "%s: i2c rd failed reg=%02x\n",
KBUILD_MODNAME, reg);
return -EREMOTEIO;
}
return 0;
}
/* write single register */
static int qt1010_writereg(struct qt1010_priv *priv, u8 reg, u8 val)
{
u8 buf[2] = { reg, val };
struct i2c_msg msg = { .addr = priv->cfg->i2c_address,
.flags = 0, .buf = buf, .len = 2 };
if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
dev_warn(&priv->i2c->dev, "%s: i2c wr failed reg=%02x\n",
KBUILD_MODNAME, reg);
return -EREMOTEIO;
}
return 0;
}
static int qt1010_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct qt1010_priv *priv;
int err;
u32 freq, div, mod1, mod2;
u8 i, tmpval, reg05;
qt1010_i2c_oper_t rd[48] = {
{ QT1010_WR, 0x01, 0x80 },
{ QT1010_WR, 0x02, 0x3f },
{ QT1010_WR, 0x05, 0xff }, /* 02 c write */
{ QT1010_WR, 0x06, 0x44 },
{ QT1010_WR, 0x07, 0xff }, /* 04 c write */
{ QT1010_WR, 0x08, 0x08 },
{ QT1010_WR, 0x09, 0xff }, /* 06 c write */
{ QT1010_WR, 0x0a, 0xff }, /* 07 c write */
{ QT1010_WR, 0x0b, 0xff }, /* 08 c write */
{ QT1010_WR, 0x0c, 0xe1 },
{ QT1010_WR, 0x1a, 0xff }, /* 10 c write */
{ QT1010_WR, 0x1b, 0x00 },
{ QT1010_WR, 0x1c, 0x89 },
{ QT1010_WR, 0x11, 0xff }, /* 13 c write */
{ QT1010_WR, 0x12, 0xff }, /* 14 c write */
{ QT1010_WR, 0x22, 0xff }, /* 15 c write */
{ QT1010_WR, 0x1e, 0x00 },
{ QT1010_WR, 0x1e, 0xd0 },
{ QT1010_RD, 0x22, 0xff }, /* 16 c read */
{ QT1010_WR, 0x1e, 0x00 },
{ QT1010_RD, 0x05, 0xff }, /* 20 c read */
{ QT1010_RD, 0x22, 0xff }, /* 21 c read */
{ QT1010_WR, 0x23, 0xd0 },
{ QT1010_WR, 0x1e, 0x00 },
{ QT1010_WR, 0x1e, 0xe0 },
{ QT1010_RD, 0x23, 0xff }, /* 25 c read */
{ QT1010_RD, 0x23, 0xff }, /* 26 c read */
{ QT1010_WR, 0x1e, 0x00 },
{ QT1010_WR, 0x24, 0xd0 },
{ QT1010_WR, 0x1e, 0x00 },
{ QT1010_WR, 0x1e, 0xf0 },
{ QT1010_RD, 0x24, 0xff }, /* 31 c read */
{ QT1010_WR, 0x1e, 0x00 },
{ QT1010_WR, 0x14, 0x7f },
{ QT1010_WR, 0x15, 0x7f },
{ QT1010_WR, 0x05, 0xff }, /* 35 c write */
{ QT1010_WR, 0x06, 0x00 },
{ QT1010_WR, 0x15, 0x1f },
{ QT1010_WR, 0x16, 0xff },
{ QT1010_WR, 0x18, 0xff },
{ QT1010_WR, 0x1f, 0xff }, /* 40 c write */
{ QT1010_WR, 0x20, 0xff }, /* 41 c write */
{ QT1010_WR, 0x21, 0x53 },
{ QT1010_WR, 0x25, 0xff }, /* 43 c write */
{ QT1010_WR, 0x26, 0x15 },
{ QT1010_WR, 0x00, 0xff }, /* 45 c write */
{ QT1010_WR, 0x02, 0x00 },
{ QT1010_WR, 0x01, 0x00 }
};
#define FREQ1 32000000 /* 32 MHz */
#define FREQ2 4000000 /* 4 MHz Quartz oscillator in the stick? */
priv = fe->tuner_priv;
freq = c->frequency;
div = (freq + QT1010_OFFSET) / QT1010_STEP;
freq = (div * QT1010_STEP) - QT1010_OFFSET;
mod1 = (freq + QT1010_OFFSET) % FREQ1;
mod2 = (freq + QT1010_OFFSET) % FREQ2;
priv->frequency = freq;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
/* reg 05 base value */
if (freq < 290000000) reg05 = 0x14; /* 290 MHz */
else if (freq < 610000000) reg05 = 0x34; /* 610 MHz */
else if (freq < 802000000) reg05 = 0x54; /* 802 MHz */
else reg05 = 0x74;
/* 0x5 */
rd[2].val = reg05;
/* 07 - set frequency: 32 MHz scale */
rd[4].val = (freq + QT1010_OFFSET) / FREQ1;
/* 09 - changes every 8/24 MHz */
if (mod1 < 8000000) rd[6].val = 0x1d;
else rd[6].val = 0x1c;
/* 0a - set frequency: 4 MHz scale (max 28 MHz) */
if (mod1 < 1*FREQ2) rd[7].val = 0x09; /* +0 MHz */
else if (mod1 < 2*FREQ2) rd[7].val = 0x08; /* +4 MHz */
else if (mod1 < 3*FREQ2) rd[7].val = 0x0f; /* +8 MHz */
else if (mod1 < 4*FREQ2) rd[7].val = 0x0e; /* +12 MHz */
else if (mod1 < 5*FREQ2) rd[7].val = 0x0d; /* +16 MHz */
else if (mod1 < 6*FREQ2) rd[7].val = 0x0c; /* +20 MHz */
else if (mod1 < 7*FREQ2) rd[7].val = 0x0b; /* +24 MHz */
else rd[7].val = 0x0a; /* +28 MHz */
/* 0b - changes every 2/2 MHz */
if (mod2 < 2000000) rd[8].val = 0x45;
else rd[8].val = 0x44;
/* 1a - set frequency: 125 kHz scale (max 3875 kHz)*/
tmpval = 0x78; /* byte, overflows intentionally */
rd[10].val = tmpval-((mod2/QT1010_STEP)*0x08);
/* 11 */
rd[13].val = 0xfd; /* TODO: correct value calculation */
/* 12 */
rd[14].val = 0x91; /* TODO: correct value calculation */
/* 22 */
if (freq < 450000000) rd[15].val = 0xd0; /* 450 MHz */
else if (freq < 482000000) rd[15].val = 0xd1; /* 482 MHz */
else if (freq < 514000000) rd[15].val = 0xd4; /* 514 MHz */
else if (freq < 546000000) rd[15].val = 0xd7; /* 546 MHz */
else if (freq < 610000000) rd[15].val = 0xda; /* 610 MHz */
else rd[15].val = 0xd0;
/* 05 */
rd[35].val = (reg05 & 0xf0);
/* 1f */
if (mod1 < 8000000) tmpval = 0x00;
else if (mod1 < 12000000) tmpval = 0x01;
else if (mod1 < 16000000) tmpval = 0x02;
else if (mod1 < 24000000) tmpval = 0x03;
else if (mod1 < 28000000) tmpval = 0x04;
else tmpval = 0x05;
rd[40].val = (priv->reg1f_init_val + 0x0e + tmpval);
/* 20 */
if (mod1 < 8000000) tmpval = 0x00;
else if (mod1 < 12000000) tmpval = 0x01;
else if (mod1 < 20000000) tmpval = 0x02;
else if (mod1 < 24000000) tmpval = 0x03;
else if (mod1 < 28000000) tmpval = 0x04;
else tmpval = 0x05;
rd[41].val = (priv->reg20_init_val + 0x0d + tmpval);
/* 25 */
rd[43].val = priv->reg25_init_val;
/* 00 */
rd[45].val = 0x92; /* TODO: correct value calculation */
dev_dbg(&priv->i2c->dev,
"%s: freq:%u 05:%02x 07:%02x 09:%02x 0a:%02x 0b:%02x " \
"1a:%02x 11:%02x 12:%02x 22:%02x 05:%02x 1f:%02x " \
"20:%02x 25:%02x 00:%02x\n", __func__, \
freq, rd[2].val, rd[4].val, rd[6].val, rd[7].val, \
rd[8].val, rd[10].val, rd[13].val, rd[14].val, \
rd[15].val, rd[35].val, rd[40].val, rd[41].val, \
rd[43].val, rd[45].val);
for (i = 0; i < ARRAY_SIZE(rd); i++) {
if (rd[i].oper == QT1010_WR) {
err = qt1010_writereg(priv, rd[i].reg, rd[i].val);
} else { /* read is required to proper locking */
err = qt1010_readreg(priv, rd[i].reg, &tmpval);
}
if (err) return err;
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
return 0;
}
static int qt1010_init_meas1(struct qt1010_priv *priv,
u8 oper, u8 reg, u8 reg_init_val, u8 *retval)
{
u8 i, val1, val2;
int err;
qt1010_i2c_oper_t i2c_data[] = {
{ QT1010_WR, reg, reg_init_val },
{ QT1010_WR, 0x1e, 0x00 },
{ QT1010_WR, 0x1e, oper },
{ QT1010_RD, reg, 0xff }
};
for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
if (i2c_data[i].oper == QT1010_WR) {
err = qt1010_writereg(priv, i2c_data[i].reg,
i2c_data[i].val);
} else {
err = qt1010_readreg(priv, i2c_data[i].reg, &val2);
}
if (err) return err;
}
do {
val1 = val2;
err = qt1010_readreg(priv, reg, &val2);
if (err) return err;
dev_dbg(&priv->i2c->dev, "%s: compare reg:%02x %02x %02x\n",
__func__, reg, val1, val2);
} while (val1 != val2);
*retval = val1;
return qt1010_writereg(priv, 0x1e, 0x00);
}
static int qt1010_init_meas2(struct qt1010_priv *priv,
u8 reg_init_val, u8 *retval)
{
u8 i, val;
int err;
qt1010_i2c_oper_t i2c_data[] = {
{ QT1010_WR, 0x07, reg_init_val },
{ QT1010_WR, 0x22, 0xd0 },
{ QT1010_WR, 0x1e, 0x00 },
{ QT1010_WR, 0x1e, 0xd0 },
{ QT1010_RD, 0x22, 0xff },
{ QT1010_WR, 0x1e, 0x00 },
{ QT1010_WR, 0x22, 0xff }
};
for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
if (i2c_data[i].oper == QT1010_WR) {
err = qt1010_writereg(priv, i2c_data[i].reg,
i2c_data[i].val);
} else {
err = qt1010_readreg(priv, i2c_data[i].reg, &val);
}
if (err) return err;
}
*retval = val;
return 0;
}
static int qt1010_init(struct dvb_frontend *fe)
{
struct qt1010_priv *priv = fe->tuner_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int err = 0;
u8 i, tmpval, *valptr = NULL;
qt1010_i2c_oper_t i2c_data[] = {
{ QT1010_WR, 0x01, 0x80 },
{ QT1010_WR, 0x0d, 0x84 },
{ QT1010_WR, 0x0e, 0xb7 },
{ QT1010_WR, 0x2a, 0x23 },
{ QT1010_WR, 0x2c, 0xdc },
{ QT1010_M1, 0x25, 0x40 }, /* get reg 25 init value */
{ QT1010_M1, 0x81, 0xff }, /* get reg 25 init value */
{ QT1010_WR, 0x2b, 0x70 },
{ QT1010_WR, 0x2a, 0x23 },
{ QT1010_M1, 0x26, 0x08 },
{ QT1010_M1, 0x82, 0xff },
{ QT1010_WR, 0x05, 0x14 },
{ QT1010_WR, 0x06, 0x44 },
{ QT1010_WR, 0x07, 0x28 },
{ QT1010_WR, 0x08, 0x0b },
{ QT1010_WR, 0x11, 0xfd },
{ QT1010_M1, 0x22, 0x0d },
{ QT1010_M1, 0xd0, 0xff },
{ QT1010_WR, 0x06, 0x40 },
{ QT1010_WR, 0x16, 0xf0 },
{ QT1010_WR, 0x02, 0x38 },
{ QT1010_WR, 0x03, 0x18 },
{ QT1010_WR, 0x20, 0xe0 },
{ QT1010_M1, 0x1f, 0x20 }, /* get reg 1f init value */
{ QT1010_M1, 0x84, 0xff }, /* get reg 1f init value */
{ QT1010_RD, 0x20, 0x20 }, /* get reg 20 init value */
{ QT1010_WR, 0x03, 0x19 },
{ QT1010_WR, 0x02, 0x3f },
{ QT1010_WR, 0x21, 0x53 },
{ QT1010_RD, 0x21, 0xff },
{ QT1010_WR, 0x11, 0xfd },
{ QT1010_WR, 0x05, 0x34 },
{ QT1010_WR, 0x06, 0x44 },
{ QT1010_WR, 0x08, 0x08 }
};
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
switch (i2c_data[i].oper) {
case QT1010_WR:
err = qt1010_writereg(priv, i2c_data[i].reg,
i2c_data[i].val);
break;
case QT1010_RD:
if (i2c_data[i].val == 0x20)
valptr = &priv->reg20_init_val;
else
valptr = &tmpval;
err = qt1010_readreg(priv, i2c_data[i].reg, valptr);
break;
case QT1010_M1:
if (i2c_data[i].val == 0x25)
valptr = &priv->reg25_init_val;
else if (i2c_data[i].val == 0x1f)
valptr = &priv->reg1f_init_val;
else
valptr = &tmpval;
err = qt1010_init_meas1(priv, i2c_data[i+1].reg,
i2c_data[i].reg,
i2c_data[i].val, valptr);
i++;
break;
}
if (err) return err;
}
for (i = 0x31; i < 0x3a; i++) /* 0x31 - 0x39 */
if ((err = qt1010_init_meas2(priv, i, &tmpval)))
return err;
if (!c->frequency)
c->frequency = 545000000; /* Sigmatek DVB-110 545000000 */
/* MSI Megasky 580 GL861 533000000 */
return qt1010_set_params(fe);
}
static int qt1010_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
return 0;
}
static int qt1010_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct qt1010_priv *priv = fe->tuner_priv;
*frequency = priv->frequency;
return 0;
}
static int qt1010_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
*frequency = 36125000;
return 0;
}
static const struct dvb_tuner_ops qt1010_tuner_ops = {
.info = {
.name = "Quantek QT1010",
.frequency_min = QT1010_MIN_FREQ,
.frequency_max = QT1010_MAX_FREQ,
.frequency_step = QT1010_STEP,
},
.release = qt1010_release,
.init = qt1010_init,
/* TODO: implement sleep */
.set_params = qt1010_set_params,
.get_frequency = qt1010_get_frequency,
.get_if_frequency = qt1010_get_if_frequency,
};
struct dvb_frontend * qt1010_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
struct qt1010_config *cfg)
{
struct qt1010_priv *priv = NULL;
u8 id;
priv = kzalloc(sizeof(struct qt1010_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->cfg = cfg;
priv->i2c = i2c;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
/* Try to detect tuner chip. Probably this is not correct register. */
if (qt1010_readreg(priv, 0x29, &id) != 0 || (id != 0x39)) {
kfree(priv);
return NULL;
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
dev_info(&priv->i2c->dev,
"%s: Quantek QT1010 successfully identified\n",
KBUILD_MODNAME);
memcpy(&fe->ops.tuner_ops, &qt1010_tuner_ops,
sizeof(struct dvb_tuner_ops));
fe->tuner_priv = priv;
return fe;
}
EXPORT_SYMBOL(qt1010_attach);
MODULE_DESCRIPTION("Quantek QT1010 silicon tuner driver");
MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
MODULE_AUTHOR("Aapo Tahkola <aet@rasterburn.org>");
MODULE_VERSION("0.1");
MODULE_LICENSE("GPL");

53
drivers/media/tuners/qt1010.h Normal file
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/*
* Driver for Quantek QT1010 silicon tuner
*
* Copyright (C) 2006 Antti Palosaari <crope@iki.fi>
* Aapo Tahkola <aet@rasterburn.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef QT1010_H
#define QT1010_H
#include "dvb_frontend.h"
struct qt1010_config {
u8 i2c_address;
};
/**
* Attach a qt1010 tuner to the supplied frontend structure.
*
* @param fe frontend to attach to
* @param i2c i2c adapter to use
* @param cfg tuner hw based configuration
* @return fe pointer on success, NULL on failure
*/
#if IS_ENABLED(CONFIG_MEDIA_TUNER_QT1010)
extern struct dvb_frontend *qt1010_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
struct qt1010_config *cfg);
#else
static inline struct dvb_frontend *qt1010_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
struct qt1010_config *cfg)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif // CONFIG_MEDIA_TUNER_QT1010
#endif

104
drivers/media/tuners/qt1010_priv.h Normal file
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/*
* Driver for Quantek QT1010 silicon tuner
*
* Copyright (C) 2006 Antti Palosaari <crope@iki.fi>
* Aapo Tahkola <aet@rasterburn.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef QT1010_PRIV_H
#define QT1010_PRIV_H
/*
reg def meaning
=== === =======
00 00 ?
01 a0 ? operation start/stop; start=80, stop=00
02 00 ?
03 19 ?
04 00 ?
05 00 ? maybe band selection
06 00 ?
07 2b set frequency: 32 MHz scale, n*32 MHz
08 0b ?
09 10 ? changes every 8/24 MHz; values 1d/1c
0a 08 set frequency: 4 MHz scale, n*4 MHz
0b 41 ? changes every 2/2 MHz; values 45/45
0c e1 ?
0d 94 ?
0e b6 ?
0f 2c ?
10 10 ?
11 f1 ? maybe device specified adjustment
12 11 ? maybe device specified adjustment
13 3f ?
14 1f ?
15 3f ?
16 ff ?
17 ff ?
18 f7 ?
19 80 ?
1a d0 set frequency: 125 kHz scale, n*125 kHz
1b 00 ?
1c 89 ?
1d 00 ?
1e 00 ? looks like operation register; write cmd here, read result from 1f-26
1f 20 ? chip initialization
20 e0 ? chip initialization
21 20 ?
22 d0 ?
23 d0 ?
24 d0 ?
25 40 ? chip initialization
26 08 ?
27 29 ?
28 55 ?
29 39 ?
2a 13 ?
2b 01 ?
2c ea ?
2d 00 ?
2e 00 ? not used?
2f 00 ? not used?
*/
#define QT1010_STEP 125000 /* 125 kHz used by Windows drivers,
hw could be more precise but we don't
know how to use */
#define QT1010_MIN_FREQ 48000000 /* 48 MHz */
#define QT1010_MAX_FREQ 860000000 /* 860 MHz */
#define QT1010_OFFSET 1246000000 /* 1246 MHz */
#define QT1010_WR 0
#define QT1010_RD 1
#define QT1010_M1 3
typedef struct {
u8 oper, reg, val;
} qt1010_i2c_oper_t;
struct qt1010_priv {
struct qt1010_config *cfg;
struct i2c_adapter *i2c;
u8 reg1f_init_val;
u8 reg20_init_val;
u8 reg25_init_val;
u32 frequency;
};
#endif

2355
drivers/media/tuners/r820t.c Normal file
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File diff suppressed because it is too large Load diff

59
drivers/media/tuners/r820t.h Normal file
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/*
* Elonics R820T silicon tuner driver
*
* Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef R820T_H
#define R820T_H
#include <linux/kconfig.h>
#include "dvb_frontend.h"
enum r820t_chip {
CHIP_R820T,
CHIP_R620D,
CHIP_R828D,
CHIP_R828,
CHIP_R828S,
CHIP_R820C,
};
struct r820t_config {
u8 i2c_addr; /* 0x34 */
u32 xtal;
enum r820t_chip rafael_chip;
unsigned max_i2c_msg_len;
bool use_diplexer;
bool use_predetect;
};
#if IS_ENABLED(CONFIG_MEDIA_TUNER_R820T)
struct dvb_frontend *r820t_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
const struct r820t_config *cfg);
#else
static inline struct dvb_frontend *r820t_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
const struct r820t_config *cfg)
{
pr_warn("%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif

399
drivers/media/tuners/si2157.c Normal file
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/*
* Silicon Labs Si2147/2157/2158 silicon tuner driver
*
* Copyright (C) 2014 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "si2157_priv.h"
static const struct dvb_tuner_ops si2157_ops;
/* execute firmware command */
static int si2157_cmd_execute(struct si2157 *s, struct si2157_cmd *cmd)
{
int ret;
unsigned long timeout;
mutex_lock(&s->i2c_mutex);
if (cmd->wlen) {
/* write cmd and args for firmware */
ret = i2c_master_send(s->client, cmd->args, cmd->wlen);
if (ret < 0) {
goto err_mutex_unlock;
} else if (ret != cmd->wlen) {
ret = -EREMOTEIO;
goto err_mutex_unlock;
}
}
if (cmd->rlen) {
/* wait cmd execution terminate */
#define TIMEOUT 80
timeout = jiffies + msecs_to_jiffies(TIMEOUT);
while (!time_after(jiffies, timeout)) {
ret = i2c_master_recv(s->client, cmd->args, cmd->rlen);
if (ret < 0) {
goto err_mutex_unlock;
} else if (ret != cmd->rlen) {
ret = -EREMOTEIO;
goto err_mutex_unlock;
}
/* firmware ready? */
if ((cmd->args[0] >> 7) & 0x01)
break;
}
dev_dbg(&s->client->dev, "cmd execution took %d ms\n",
jiffies_to_msecs(jiffies) -
(jiffies_to_msecs(timeout) - TIMEOUT));
if (!((cmd->args[0] >> 7) & 0x01)) {
ret = -ETIMEDOUT;
goto err_mutex_unlock;
}
}
ret = 0;
err_mutex_unlock:
mutex_unlock(&s->i2c_mutex);
if (ret)
goto err;
return 0;
err:
dev_dbg(&s->client->dev, "failed=%d\n", ret);
return ret;
}
static int si2157_init(struct dvb_frontend *fe)
{
struct si2157 *s = fe->tuner_priv;
int ret, len, remaining;
struct si2157_cmd cmd;
const struct firmware *fw = NULL;
u8 *fw_file;
unsigned int chip_id;
dev_dbg(&s->client->dev, "\n");
if (s->fw_loaded)
goto warm;
/* power up */
memcpy(cmd.args, "\xc0\x00\x0c\x00\x00\x01\x01\x01\x01\x01\x01\x02\x00\x00\x01", 15);
cmd.wlen = 15;
cmd.rlen = 1;
ret = si2157_cmd_execute(s, &cmd);
if (ret)
goto err;
/* query chip revision */
memcpy(cmd.args, "\x02", 1);
cmd.wlen = 1;
cmd.rlen = 13;
ret = si2157_cmd_execute(s, &cmd);
if (ret)
goto err;
chip_id = cmd.args[1] << 24 | cmd.args[2] << 16 | cmd.args[3] << 8 |
cmd.args[4] << 0;
#define SI2158_A20 ('A' << 24 | 58 << 16 | '2' << 8 | '0' << 0)
#define SI2157_A30 ('A' << 24 | 57 << 16 | '3' << 8 | '0' << 0)
#define SI2147_A30 ('A' << 24 | 47 << 16 | '3' << 8 | '0' << 0)
switch (chip_id) {
case SI2158_A20:
fw_file = SI2158_A20_FIRMWARE;
break;
case SI2157_A30:
case SI2147_A30:
goto skip_fw_download;
break;
default:
dev_err(&s->client->dev,
"unknown chip version Si21%d-%c%c%c\n",
cmd.args[2], cmd.args[1],
cmd.args[3], cmd.args[4]);
ret = -EINVAL;
goto err;
}
/* cold state - try to download firmware */
dev_info(&s->client->dev, "found a '%s' in cold state\n",
si2157_ops.info.name);
/* request the firmware, this will block and timeout */
ret = request_firmware(&fw, fw_file, &s->client->dev);
if (ret) {
dev_err(&s->client->dev, "firmware file '%s' not found\n",
fw_file);
goto err;
}
/* firmware should be n chunks of 17 bytes */
if (fw->size % 17 != 0) {
dev_err(&s->client->dev, "firmware file '%s' is invalid\n",
fw_file);
ret = -EINVAL;
goto err;
}
dev_info(&s->client->dev, "downloading firmware from file '%s'\n",
fw_file);
for (remaining = fw->size; remaining > 0; remaining -= 17) {
len = fw->data[fw->size - remaining];
memcpy(cmd.args, &fw->data[(fw->size - remaining) + 1], len);
cmd.wlen = len;
cmd.rlen = 1;
ret = si2157_cmd_execute(s, &cmd);
if (ret) {
dev_err(&s->client->dev,
"firmware download failed=%d\n",
ret);
goto err;
}
}
release_firmware(fw);
fw = NULL;
skip_fw_download:
/* reboot the tuner with new firmware? */
memcpy(cmd.args, "\x01\x01", 2);
cmd.wlen = 2;
cmd.rlen = 1;
ret = si2157_cmd_execute(s, &cmd);
if (ret)
goto err;
s->fw_loaded = true;
warm:
s->active = true;
return 0;
err:
if (fw)
release_firmware(fw);
dev_dbg(&s->client->dev, "failed=%d\n", ret);
return ret;
}
static int si2157_sleep(struct dvb_frontend *fe)
{
struct si2157 *s = fe->tuner_priv;
int ret;
struct si2157_cmd cmd;
dev_dbg(&s->client->dev, "\n");
s->active = false;
/* standby */
memcpy(cmd.args, "\x16\x00", 2);
cmd.wlen = 2;
cmd.rlen = 1;
ret = si2157_cmd_execute(s, &cmd);
if (ret)
goto err;
return 0;
err:
dev_dbg(&s->client->dev, "failed=%d\n", ret);
return ret;
}
static int si2157_set_params(struct dvb_frontend *fe)
{
struct si2157 *s = fe->tuner_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
struct si2157_cmd cmd;
u8 bandwidth, delivery_system;
dev_dbg(&s->client->dev,
"delivery_system=%d frequency=%u bandwidth_hz=%u\n",
c->delivery_system, c->frequency,
c->bandwidth_hz);
if (!s->active) {
ret = -EAGAIN;
goto err;
}
if (c->bandwidth_hz <= 6000000)
bandwidth = 0x06;
else if (c->bandwidth_hz <= 7000000)
bandwidth = 0x07;
else if (c->bandwidth_hz <= 8000000)
bandwidth = 0x08;
else
bandwidth = 0x0f;
switch (c->delivery_system) {
case SYS_ATSC:
delivery_system = 0x00;
break;
case SYS_DVBT:
case SYS_DVBT2: /* it seems DVB-T and DVB-T2 both are 0x20 here */
delivery_system = 0x20;
break;
case SYS_DVBC_ANNEX_A:
delivery_system = 0x30;
break;
default:
ret = -EINVAL;
goto err;
}
memcpy(cmd.args, "\x14\x00\x03\x07\x00\x00", 6);
cmd.args[4] = delivery_system | bandwidth;
if (s->inversion)
cmd.args[5] = 0x01;
cmd.wlen = 6;
cmd.rlen = 4;
ret = si2157_cmd_execute(s, &cmd);
if (ret)
goto err;
memcpy(cmd.args, "\x14\x00\x02\x07\x01\x00", 6);
cmd.wlen = 6;
cmd.rlen = 4;
ret = si2157_cmd_execute(s, &cmd);
if (ret)
goto err;
/* set frequency */
memcpy(cmd.args, "\x41\x00\x00\x00\x00\x00\x00\x00", 8);
cmd.args[4] = (c->frequency >> 0) & 0xff;
cmd.args[5] = (c->frequency >> 8) & 0xff;
cmd.args[6] = (c->frequency >> 16) & 0xff;
cmd.args[7] = (c->frequency >> 24) & 0xff;
cmd.wlen = 8;
cmd.rlen = 1;
ret = si2157_cmd_execute(s, &cmd);
if (ret)
goto err;
return 0;
err:
dev_dbg(&s->client->dev, "failed=%d\n", ret);
return ret;
}
static int si2157_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
*frequency = 5000000; /* default value of property 0x0706 */
return 0;
}
static const struct dvb_tuner_ops si2157_ops = {
.info = {
.name = "Silicon Labs Si2157/Si2158",
.frequency_min = 110000000,
.frequency_max = 862000000,
},
.init = si2157_init,
.sleep = si2157_sleep,
.set_params = si2157_set_params,
.get_if_frequency = si2157_get_if_frequency,
};
static int si2157_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct si2157_config *cfg = client->dev.platform_data;
struct dvb_frontend *fe = cfg->fe;
struct si2157 *s;
struct si2157_cmd cmd;
int ret;
s = kzalloc(sizeof(struct si2157), GFP_KERNEL);
if (!s) {
ret = -ENOMEM;
dev_err(&client->dev, "kzalloc() failed\n");
goto err;
}
s->client = client;
s->fe = cfg->fe;
s->inversion = cfg->inversion;
s->fw_loaded = false;
mutex_init(&s->i2c_mutex);
/* check if the tuner is there */
cmd.wlen = 0;
cmd.rlen = 1;
ret = si2157_cmd_execute(s, &cmd);
if (ret)
goto err;
fe->tuner_priv = s;
memcpy(&fe->ops.tuner_ops, &si2157_ops,
sizeof(struct dvb_tuner_ops));
i2c_set_clientdata(client, s);
dev_info(&s->client->dev,
"Silicon Labs Si2157/Si2158 successfully attached\n");
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
kfree(s);
return ret;
}
static int si2157_remove(struct i2c_client *client)
{
struct si2157 *s = i2c_get_clientdata(client);
struct dvb_frontend *fe = s->fe;
dev_dbg(&client->dev, "\n");
memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops));
fe->tuner_priv = NULL;
kfree(s);
return 0;
}
static const struct i2c_device_id si2157_id[] = {
{"si2157", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, si2157_id);
static struct i2c_driver si2157_driver = {
.driver = {
.owner = THIS_MODULE,
.name = "si2157",
},
.probe = si2157_probe,
.remove = si2157_remove,
.id_table = si2157_id,
};
module_i2c_driver(si2157_driver);
MODULE_DESCRIPTION("Silicon Labs Si2157/Si2158 silicon tuner driver");
MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE(SI2158_A20_FIRMWARE);

39
drivers/media/tuners/si2157.h Normal file
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@ -0,0 +1,39 @@
/*
* Silicon Labs Si2147/2157/2158 silicon tuner driver
*
* Copyright (C) 2014 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SI2157_H
#define SI2157_H
#include <linux/kconfig.h>
#include "dvb_frontend.h"
/*
* I2C address
* 0x60
*/
struct si2157_config {
/*
* frontend
*/
struct dvb_frontend *fe;
/*
* Spectral Inversion
*/
bool inversion;
};
#endif

43
drivers/media/tuners/si2157_priv.h Normal file
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@ -0,0 +1,43 @@
/*
* Silicon Labs Si2147/2157/2158 silicon tuner driver
*
* Copyright (C) 2014 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SI2157_PRIV_H
#define SI2157_PRIV_H
#include <linux/firmware.h>
#include "si2157.h"
/* state struct */
struct si2157 {
struct mutex i2c_mutex;
struct i2c_client *client;
struct dvb_frontend *fe;
bool active;
bool fw_loaded;
bool inversion;
};
/* firmare command struct */
#define SI2157_ARGLEN 30
struct si2157_cmd {
u8 args[SI2157_ARGLEN];
unsigned wlen;
unsigned rlen;
};
#define SI2158_A20_FIRMWARE "dvb-tuner-si2158-a20-01.fw"
#endif

292
drivers/media/tuners/tda18212.c Normal file
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@ -0,0 +1,292 @@
/*
* NXP TDA18212HN silicon tuner driver
*
* Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include "tda18212.h"
#include <linux/regmap.h>
struct tda18212_dev {
struct tda18212_config cfg;
struct i2c_client *client;
struct regmap *regmap;
u32 if_frequency;
};
static int tda18212_set_params(struct dvb_frontend *fe)
{
struct tda18212_dev *dev = fe->tuner_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i;
u32 if_khz;
u8 buf[9];
#define DVBT_6 0
#define DVBT_7 1
#define DVBT_8 2
#define DVBT2_6 3
#define DVBT2_7 4
#define DVBT2_8 5
#define DVBC_6 6
#define DVBC_8 7
#define ATSC_VSB 8
#define ATSC_QAM 9
static const u8 bw_params[][3] = {
/* reg: 0f 13 23 */
[DVBT_6] = { 0xb3, 0x20, 0x03 },
[DVBT_7] = { 0xb3, 0x31, 0x01 },
[DVBT_8] = { 0xb3, 0x22, 0x01 },
[DVBT2_6] = { 0xbc, 0x20, 0x03 },
[DVBT2_7] = { 0xbc, 0x72, 0x03 },
[DVBT2_8] = { 0xbc, 0x22, 0x01 },
[DVBC_6] = { 0x92, 0x50, 0x03 },
[DVBC_8] = { 0x92, 0x53, 0x03 },
[ATSC_VSB] = { 0x7d, 0x20, 0x63 },
[ATSC_QAM] = { 0x7d, 0x20, 0x63 },
};
dev_dbg(&dev->client->dev,
"delivery_system=%d frequency=%d bandwidth_hz=%d\n",
c->delivery_system, c->frequency,
c->bandwidth_hz);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
switch (c->delivery_system) {
case SYS_ATSC:
if_khz = dev->cfg.if_atsc_vsb;
i = ATSC_VSB;
break;
case SYS_DVBC_ANNEX_B:
if_khz = dev->cfg.if_atsc_qam;
i = ATSC_QAM;
break;
case SYS_DVBT:
switch (c->bandwidth_hz) {
case 6000000:
if_khz = dev->cfg.if_dvbt_6;
i = DVBT_6;
break;
case 7000000:
if_khz = dev->cfg.if_dvbt_7;
i = DVBT_7;
break;
case 8000000:
if_khz = dev->cfg.if_dvbt_8;
i = DVBT_8;
break;
default:
ret = -EINVAL;
goto error;
}
break;
case SYS_DVBT2:
switch (c->bandwidth_hz) {
case 6000000:
if_khz = dev->cfg.if_dvbt2_6;
i = DVBT2_6;
break;
case 7000000:
if_khz = dev->cfg.if_dvbt2_7;
i = DVBT2_7;
break;
case 8000000:
if_khz = dev->cfg.if_dvbt2_8;
i = DVBT2_8;
break;
default:
ret = -EINVAL;
goto error;
}
break;
case SYS_DVBC_ANNEX_A:
case SYS_DVBC_ANNEX_C:
if_khz = dev->cfg.if_dvbc;
i = DVBC_8;
break;
default:
ret = -EINVAL;
goto error;
}
ret = regmap_write(dev->regmap, 0x23, bw_params[i][2]);
if (ret)
goto error;
ret = regmap_write(dev->regmap, 0x06, 0x00);
if (ret)
goto error;
ret = regmap_write(dev->regmap, 0x0f, bw_params[i][0]);
if (ret)
goto error;
buf[0] = 0x02;
buf[1] = bw_params[i][1];
buf[2] = 0x03; /* default value */
buf[3] = DIV_ROUND_CLOSEST(if_khz, 50);
buf[4] = ((c->frequency / 1000) >> 16) & 0xff;
buf[5] = ((c->frequency / 1000) >> 8) & 0xff;
buf[6] = ((c->frequency / 1000) >> 0) & 0xff;
buf[7] = 0xc1;
buf[8] = 0x01;
ret = regmap_bulk_write(dev->regmap, 0x12, buf, sizeof(buf));
if (ret)
goto error;
/* actual IF rounded as it is on register */
dev->if_frequency = buf[3] * 50 * 1000;
exit:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
return ret;
error:
dev_dbg(&dev->client->dev, "failed=%d\n", ret);
goto exit;
}
static int tda18212_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct tda18212_dev *dev = fe->tuner_priv;
*frequency = dev->if_frequency;
return 0;
}
static const struct dvb_tuner_ops tda18212_tuner_ops = {
.info = {
.name = "NXP TDA18212",
.frequency_min = 48000000,
.frequency_max = 864000000,
.frequency_step = 1000,
},
.set_params = tda18212_set_params,
.get_if_frequency = tda18212_get_if_frequency,
};
static int tda18212_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct tda18212_config *cfg = client->dev.platform_data;
struct dvb_frontend *fe = cfg->fe;
struct tda18212_dev *dev;
int ret;
unsigned int chip_id;
char *version;
static const struct regmap_config regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (dev == NULL) {
ret = -ENOMEM;
dev_err(&client->dev, "kzalloc() failed\n");
goto err;
}
memcpy(&dev->cfg, cfg, sizeof(struct tda18212_config));
dev->client = client;
dev->regmap = devm_regmap_init_i2c(client, &regmap_config);
if (IS_ERR(dev->regmap)) {
ret = PTR_ERR(dev->regmap);
goto err;
}
/* check if the tuner is there */
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
ret = regmap_read(dev->regmap, 0x00, &chip_id);
dev_dbg(&dev->client->dev, "chip_id=%02x\n", chip_id);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
if (ret)
goto err;
switch (chip_id) {
case 0xc7:
version = "M"; /* master */
break;
case 0x47:
version = "S"; /* slave */
break;
default:
ret = -ENODEV;
goto err;
}
dev_info(&dev->client->dev,
"NXP TDA18212HN/%s successfully identified\n", version);
fe->tuner_priv = dev;
memcpy(&fe->ops.tuner_ops, &tda18212_tuner_ops,
sizeof(struct dvb_tuner_ops));
i2c_set_clientdata(client, dev);
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
kfree(dev);
return ret;
}
static int tda18212_remove(struct i2c_client *client)
{
struct tda18212_dev *dev = i2c_get_clientdata(client);
struct dvb_frontend *fe = dev->cfg.fe;
dev_dbg(&client->dev, "\n");
memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops));
fe->tuner_priv = NULL;
kfree(dev);
return 0;
}
static const struct i2c_device_id tda18212_id[] = {
{"tda18212", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, tda18212_id);
static struct i2c_driver tda18212_driver = {
.driver = {
.owner = THIS_MODULE,
.name = "tda18212",
},
.probe = tda18212_probe,
.remove = tda18212_remove,
.id_table = tda18212_id,
};
module_i2c_driver(tda18212_driver);
MODULE_DESCRIPTION("NXP TDA18212HN silicon tuner driver");
MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
MODULE_LICENSE("GPL");

45
drivers/media/tuners/tda18212.h Normal file
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@ -0,0 +1,45 @@
/*
* NXP TDA18212HN silicon tuner driver
*
* Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef TDA18212_H
#define TDA18212_H
#include <linux/kconfig.h>
#include "dvb_frontend.h"
struct tda18212_config {
u16 if_dvbt_6;
u16 if_dvbt_7;
u16 if_dvbt_8;
u16 if_dvbt2_5;
u16 if_dvbt2_6;
u16 if_dvbt2_7;
u16 if_dvbt2_8;
u16 if_dvbc;
u16 if_atsc_vsb;
u16 if_atsc_qam;
/*
* pointer to DVB frontend
*/
struct dvb_frontend *fe;
};
#endif

357
drivers/media/tuners/tda18218.c Normal file
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@ -0,0 +1,357 @@
/*
* NXP TDA18218HN silicon tuner driver
*
* Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include "tda18218_priv.h"
/* Max transfer size done by I2C transfer functions */
#define MAX_XFER_SIZE 64
/* write multiple registers */
static int tda18218_wr_regs(struct tda18218_priv *priv, u8 reg, u8 *val, u8 len)
{
int ret = 0, len2, remaining;
u8 buf[MAX_XFER_SIZE];
struct i2c_msg msg[1] = {
{
.addr = priv->cfg->i2c_address,
.flags = 0,
.buf = buf,
}
};
if (1 + len > sizeof(buf)) {
dev_warn(&priv->i2c->dev,
"%s: i2c wr reg=%04x: len=%d is too big!\n",
KBUILD_MODNAME, reg, len);
return -EINVAL;
}
for (remaining = len; remaining > 0;
remaining -= (priv->cfg->i2c_wr_max - 1)) {
len2 = remaining;
if (len2 > (priv->cfg->i2c_wr_max - 1))
len2 = (priv->cfg->i2c_wr_max - 1);
msg[0].len = 1 + len2;
buf[0] = reg + len - remaining;
memcpy(&buf[1], &val[len - remaining], len2);
ret = i2c_transfer(priv->i2c, msg, 1);
if (ret != 1)
break;
}
if (ret == 1) {
ret = 0;
} else {
dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d reg=%02x " \
"len=%d\n", KBUILD_MODNAME, ret, reg, len);
ret = -EREMOTEIO;
}
return ret;
}
/* read multiple registers */
static int tda18218_rd_regs(struct tda18218_priv *priv, u8 reg, u8 *val, u8 len)
{
int ret;
u8 buf[MAX_XFER_SIZE]; /* we must start read always from reg 0x00 */
struct i2c_msg msg[2] = {
{
.addr = priv->cfg->i2c_address,
.flags = 0,
.len = 1,
.buf = "\x00",
}, {
.addr = priv->cfg->i2c_address,
.flags = I2C_M_RD,
.len = reg + len,
.buf = buf,
}
};
if (reg + len > sizeof(buf)) {
dev_warn(&priv->i2c->dev,
"%s: i2c wr reg=%04x: len=%d is too big!\n",
KBUILD_MODNAME, reg, len);
return -EINVAL;
}
ret = i2c_transfer(priv->i2c, msg, 2);
if (ret == 2) {
memcpy(val, &buf[reg], len);
ret = 0;
} else {
dev_warn(&priv->i2c->dev, "%s: i2c rd failed=%d reg=%02x " \
"len=%d\n", KBUILD_MODNAME, ret, reg, len);
ret = -EREMOTEIO;
}
return ret;
}
/* write single register */
static int tda18218_wr_reg(struct tda18218_priv *priv, u8 reg, u8 val)
{
return tda18218_wr_regs(priv, reg, &val, 1);
}
/* read single register */
static int tda18218_rd_reg(struct tda18218_priv *priv, u8 reg, u8 *val)
{
return tda18218_rd_regs(priv, reg, val, 1);
}
static int tda18218_set_params(struct dvb_frontend *fe)
{
struct tda18218_priv *priv = fe->tuner_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u32 bw = c->bandwidth_hz;
int ret;
u8 buf[3], i, BP_Filter, LP_Fc;
u32 LO_Frac;
/* TODO: find out correct AGC algorithm */
u8 agc[][2] = {
{ R20_AGC11, 0x60 },
{ R23_AGC21, 0x02 },
{ R20_AGC11, 0xa0 },
{ R23_AGC21, 0x09 },
{ R20_AGC11, 0xe0 },
{ R23_AGC21, 0x0c },
{ R20_AGC11, 0x40 },
{ R23_AGC21, 0x01 },
{ R20_AGC11, 0x80 },
{ R23_AGC21, 0x08 },
{ R20_AGC11, 0xc0 },
{ R23_AGC21, 0x0b },
{ R24_AGC22, 0x1c },
{ R24_AGC22, 0x0c },
};
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
/* low-pass filter cut-off frequency */
if (bw <= 6000000) {
LP_Fc = 0;
priv->if_frequency = 3000000;
} else if (bw <= 7000000) {
LP_Fc = 1;
priv->if_frequency = 3500000;
} else {
LP_Fc = 2;
priv->if_frequency = 4000000;
}
LO_Frac = c->frequency + priv->if_frequency;
/* band-pass filter */
if (LO_Frac < 188000000)
BP_Filter = 3;
else if (LO_Frac < 253000000)
BP_Filter = 4;
else if (LO_Frac < 343000000)
BP_Filter = 5;
else
BP_Filter = 6;
buf[0] = (priv->regs[R1A_IF1] & ~7) | BP_Filter; /* BP_Filter */
buf[1] = (priv->regs[R1B_IF2] & ~3) | LP_Fc; /* LP_Fc */
buf[2] = priv->regs[R1C_AGC2B];
ret = tda18218_wr_regs(priv, R1A_IF1, buf, 3);
if (ret)
goto error;
buf[0] = (LO_Frac / 1000) >> 12; /* LO_Frac_0 */
buf[1] = (LO_Frac / 1000) >> 4; /* LO_Frac_1 */
buf[2] = (LO_Frac / 1000) << 4 |
(priv->regs[R0C_MD5] & 0x0f); /* LO_Frac_2 */
ret = tda18218_wr_regs(priv, R0A_MD3, buf, 3);
if (ret)
goto error;
buf[0] = priv->regs[R0F_MD8] | (1 << 6); /* Freq_prog_Start */
ret = tda18218_wr_regs(priv, R0F_MD8, buf, 1);
if (ret)
goto error;
buf[0] = priv->regs[R0F_MD8] & ~(1 << 6); /* Freq_prog_Start */
ret = tda18218_wr_regs(priv, R0F_MD8, buf, 1);
if (ret)
goto error;
/* trigger AGC */
for (i = 0; i < ARRAY_SIZE(agc); i++) {
ret = tda18218_wr_reg(priv, agc[i][0], agc[i][1]);
if (ret)
goto error;
}
error:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
if (ret)
dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
return ret;
}
static int tda18218_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct tda18218_priv *priv = fe->tuner_priv;
*frequency = priv->if_frequency;
dev_dbg(&priv->i2c->dev, "%s: if_frequency=%d\n", __func__, *frequency);
return 0;
}
static int tda18218_sleep(struct dvb_frontend *fe)
{
struct tda18218_priv *priv = fe->tuner_priv;
int ret;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
/* standby */
ret = tda18218_wr_reg(priv, R17_PD1, priv->regs[R17_PD1] | (1 << 0));
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
if (ret)
dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
return ret;
}
static int tda18218_init(struct dvb_frontend *fe)
{
struct tda18218_priv *priv = fe->tuner_priv;
int ret;
/* TODO: calibrations */
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
ret = tda18218_wr_regs(priv, R00_ID, priv->regs, TDA18218_NUM_REGS);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
if (ret)
dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
return ret;
}
static int tda18218_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
return 0;
}
static const struct dvb_tuner_ops tda18218_tuner_ops = {
.info = {
.name = "NXP TDA18218",
.frequency_min = 174000000,
.frequency_max = 864000000,
.frequency_step = 1000,
},
.release = tda18218_release,
.init = tda18218_init,
.sleep = tda18218_sleep,
.set_params = tda18218_set_params,
.get_if_frequency = tda18218_get_if_frequency,
};
struct dvb_frontend *tda18218_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, struct tda18218_config *cfg)
{
struct tda18218_priv *priv = NULL;
u8 val;
int ret;
/* chip default registers values */
static u8 def_regs[] = {
0xc0, 0x88, 0x00, 0x8e, 0x03, 0x00, 0x00, 0xd0, 0x00, 0x40,
0x00, 0x00, 0x07, 0xff, 0x84, 0x09, 0x00, 0x13, 0x00, 0x00,
0x01, 0x84, 0x09, 0xf0, 0x19, 0x0a, 0x8e, 0x69, 0x98, 0x01,
0x00, 0x58, 0x10, 0x40, 0x8c, 0x00, 0x0c, 0x48, 0x85, 0xc9,
0xa7, 0x00, 0x00, 0x00, 0x30, 0x81, 0x80, 0x00, 0x39, 0x00,
0x8a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf6, 0xf6
};
priv = kzalloc(sizeof(struct tda18218_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->cfg = cfg;
priv->i2c = i2c;
fe->tuner_priv = priv;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
/* check if the tuner is there */
ret = tda18218_rd_reg(priv, R00_ID, &val);
if (!ret)
dev_dbg(&priv->i2c->dev, "%s: chip id=%02x\n", __func__, val);
if (ret || val != def_regs[R00_ID]) {
kfree(priv);
return NULL;
}
dev_info(&priv->i2c->dev,
"%s: NXP TDA18218HN successfully identified\n",
KBUILD_MODNAME);
memcpy(&fe->ops.tuner_ops, &tda18218_tuner_ops,
sizeof(struct dvb_tuner_ops));
memcpy(priv->regs, def_regs, sizeof(def_regs));
/* loop-through enabled chip default register values */
if (priv->cfg->loop_through) {
priv->regs[R17_PD1] = 0xb0;
priv->regs[R18_PD2] = 0x59;
}
/* standby */
ret = tda18218_wr_reg(priv, R17_PD1, priv->regs[R17_PD1] | (1 << 0));
if (ret)
dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
return fe;
}
EXPORT_SYMBOL(tda18218_attach);
MODULE_DESCRIPTION("NXP TDA18218HN silicon tuner driver");
MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
MODULE_LICENSE("GPL");

45
drivers/media/tuners/tda18218.h Normal file
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/*
* NXP TDA18218HN silicon tuner driver
*
* Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef TDA18218_H
#define TDA18218_H
#include <linux/kconfig.h>
#include "dvb_frontend.h"
struct tda18218_config {
u8 i2c_address;
u8 i2c_wr_max;
u8 loop_through:1;
};
#if IS_ENABLED(CONFIG_MEDIA_TUNER_TDA18218)
extern struct dvb_frontend *tda18218_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, struct tda18218_config *cfg);
#else
static inline struct dvb_frontend *tda18218_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, struct tda18218_config *cfg)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif

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drivers/media/tuners/tda18218_priv.h Normal file
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/*
* NXP TDA18218HN silicon tuner driver
*
* Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef TDA18218_PRIV_H
#define TDA18218_PRIV_H
#include "tda18218.h"
#define R00_ID 0x00 /* ID byte */
#define R01_R1 0x01 /* Read byte 1 */
#define R02_R2 0x02 /* Read byte 2 */
#define R03_R3 0x03 /* Read byte 3 */
#define R04_R4 0x04 /* Read byte 4 */
#define R05_R5 0x05 /* Read byte 5 */
#define R06_R6 0x06 /* Read byte 6 */
#define R07_MD1 0x07 /* Main divider byte 1 */
#define R08_PSM1 0x08 /* PSM byte 1 */
#define R09_MD2 0x09 /* Main divider byte 2 */
#define R0A_MD3 0x0a /* Main divider byte 1 */
#define R0B_MD4 0x0b /* Main divider byte 4 */
#define R0C_MD5 0x0c /* Main divider byte 5 */
#define R0D_MD6 0x0d /* Main divider byte 6 */
#define R0E_MD7 0x0e /* Main divider byte 7 */
#define R0F_MD8 0x0f /* Main divider byte 8 */
#define R10_CD1 0x10 /* Call divider byte 1 */
#define R11_CD2 0x11 /* Call divider byte 2 */
#define R12_CD3 0x12 /* Call divider byte 3 */
#define R13_CD4 0x13 /* Call divider byte 4 */
#define R14_CD5 0x14 /* Call divider byte 5 */
#define R15_CD6 0x15 /* Call divider byte 6 */
#define R16_CD7 0x16 /* Call divider byte 7 */
#define R17_PD1 0x17 /* Power-down byte 1 */
#define R18_PD2 0x18 /* Power-down byte 2 */
#define R19_XTOUT 0x19 /* XTOUT byte */
#define R1A_IF1 0x1a /* IF byte 1 */
#define R1B_IF2 0x1b /* IF byte 2 */
#define R1C_AGC2B 0x1c /* AGC2b byte */
#define R1D_PSM2 0x1d /* PSM byte 2 */
#define R1E_PSM3 0x1e /* PSM byte 3 */
#define R1F_PSM4 0x1f /* PSM byte 4 */
#define R20_AGC11 0x20 /* AGC1 byte 1 */
#define R21_AGC12 0x21 /* AGC1 byte 2 */
#define R22_AGC13 0x22 /* AGC1 byte 3 */
#define R23_AGC21 0x23 /* AGC2 byte 1 */
#define R24_AGC22 0x24 /* AGC2 byte 2 */
#define R25_AAGC 0x25 /* Analog AGC byte */
#define R26_RC 0x26 /* RC byte */
#define R27_RSSI 0x27 /* RSSI byte */
#define R28_IRCAL1 0x28 /* IR CAL byte 1 */
#define R29_IRCAL2 0x29 /* IR CAL byte 2 */
#define R2A_IRCAL3 0x2a /* IR CAL byte 3 */
#define R2B_IRCAL4 0x2b /* IR CAL byte 4 */
#define R2C_RFCAL1 0x2c /* RF CAL byte 1 */
#define R2D_RFCAL2 0x2d /* RF CAL byte 2 */
#define R2E_RFCAL3 0x2e /* RF CAL byte 3 */
#define R2F_RFCAL4 0x2f /* RF CAL byte 4 */
#define R30_RFCAL5 0x30 /* RF CAL byte 5 */
#define R31_RFCAL6 0x31 /* RF CAL byte 6 */
#define R32_RFCAL7 0x32 /* RF CAL byte 7 */
#define R33_RFCAL8 0x33 /* RF CAL byte 8 */
#define R34_RFCAL9 0x34 /* RF CAL byte 9 */
#define R35_RFCAL10 0x35 /* RF CAL byte 10 */
#define R36_RFCALRAM1 0x36 /* RF CAL RAM byte 1 */
#define R37_RFCALRAM2 0x37 /* RF CAL RAM byte 2 */
#define R38_MARGIN 0x38 /* Margin byte */
#define R39_FMAX1 0x39 /* Fmax byte 1 */
#define R3A_FMAX2 0x3a /* Fmax byte 2 */
#define TDA18218_NUM_REGS 59
struct tda18218_priv {
struct tda18218_config *cfg;
struct i2c_adapter *i2c;
u32 if_frequency;
u8 regs[TDA18218_NUM_REGS];
};
#endif

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drivers/media/tuners/tda18271-common.c Normal file
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/*
tda18271-common.c - driver for the Philips / NXP TDA18271 silicon tuner
Copyright (C) 2007, 2008 Michael Krufky <mkrufky@linuxtv.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include "tda18271-priv.h"
static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct tda18271_priv *priv = fe->tuner_priv;
enum tda18271_i2c_gate gate;
int ret = 0;
switch (priv->gate) {
case TDA18271_GATE_DIGITAL:
case TDA18271_GATE_ANALOG:
gate = priv->gate;
break;
case TDA18271_GATE_AUTO:
default:
switch (priv->mode) {
case TDA18271_DIGITAL:
gate = TDA18271_GATE_DIGITAL;
break;
case TDA18271_ANALOG:
default:
gate = TDA18271_GATE_ANALOG;
break;
}
}
switch (gate) {
case TDA18271_GATE_ANALOG:
if (fe->ops.analog_ops.i2c_gate_ctrl)
ret = fe->ops.analog_ops.i2c_gate_ctrl(fe, enable);
break;
case TDA18271_GATE_DIGITAL:
if (fe->ops.i2c_gate_ctrl)
ret = fe->ops.i2c_gate_ctrl(fe, enable);
break;
default:
ret = -EINVAL;
break;
}
return ret;
};
/*---------------------------------------------------------------------*/
static void tda18271_dump_regs(struct dvb_frontend *fe, int extended)
{
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
tda_reg("=== TDA18271 REG DUMP ===\n");
tda_reg("ID_BYTE = 0x%02x\n", 0xff & regs[R_ID]);
tda_reg("THERMO_BYTE = 0x%02x\n", 0xff & regs[R_TM]);
tda_reg("POWER_LEVEL_BYTE = 0x%02x\n", 0xff & regs[R_PL]);
tda_reg("EASY_PROG_BYTE_1 = 0x%02x\n", 0xff & regs[R_EP1]);
tda_reg("EASY_PROG_BYTE_2 = 0x%02x\n", 0xff & regs[R_EP2]);
tda_reg("EASY_PROG_BYTE_3 = 0x%02x\n", 0xff & regs[R_EP3]);
tda_reg("EASY_PROG_BYTE_4 = 0x%02x\n", 0xff & regs[R_EP4]);
tda_reg("EASY_PROG_BYTE_5 = 0x%02x\n", 0xff & regs[R_EP5]);
tda_reg("CAL_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_CPD]);
tda_reg("CAL_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_CD1]);
tda_reg("CAL_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_CD2]);
tda_reg("CAL_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_CD3]);
tda_reg("MAIN_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_MPD]);
tda_reg("MAIN_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_MD1]);
tda_reg("MAIN_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_MD2]);
tda_reg("MAIN_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_MD3]);
/* only dump extended regs if DBG_ADV is set */
if (!(tda18271_debug & DBG_ADV))
return;
/* W indicates write-only registers.
* Register dump for write-only registers shows last value written. */
tda_reg("EXTENDED_BYTE_1 = 0x%02x\n", 0xff & regs[R_EB1]);
tda_reg("EXTENDED_BYTE_2 = 0x%02x\n", 0xff & regs[R_EB2]);
tda_reg("EXTENDED_BYTE_3 = 0x%02x\n", 0xff & regs[R_EB3]);
tda_reg("EXTENDED_BYTE_4 = 0x%02x\n", 0xff & regs[R_EB4]);
tda_reg("EXTENDED_BYTE_5 = 0x%02x\n", 0xff & regs[R_EB5]);
tda_reg("EXTENDED_BYTE_6 = 0x%02x\n", 0xff & regs[R_EB6]);
tda_reg("EXTENDED_BYTE_7 = 0x%02x\n", 0xff & regs[R_EB7]);
tda_reg("EXTENDED_BYTE_8 = 0x%02x\n", 0xff & regs[R_EB8]);
tda_reg("EXTENDED_BYTE_9 W = 0x%02x\n", 0xff & regs[R_EB9]);
tda_reg("EXTENDED_BYTE_10 = 0x%02x\n", 0xff & regs[R_EB10]);
tda_reg("EXTENDED_BYTE_11 = 0x%02x\n", 0xff & regs[R_EB11]);
tda_reg("EXTENDED_BYTE_12 = 0x%02x\n", 0xff & regs[R_EB12]);
tda_reg("EXTENDED_BYTE_13 = 0x%02x\n", 0xff & regs[R_EB13]);
tda_reg("EXTENDED_BYTE_14 = 0x%02x\n", 0xff & regs[R_EB14]);
tda_reg("EXTENDED_BYTE_15 = 0x%02x\n", 0xff & regs[R_EB15]);
tda_reg("EXTENDED_BYTE_16 W = 0x%02x\n", 0xff & regs[R_EB16]);
tda_reg("EXTENDED_BYTE_17 W = 0x%02x\n", 0xff & regs[R_EB17]);
tda_reg("EXTENDED_BYTE_18 = 0x%02x\n", 0xff & regs[R_EB18]);
tda_reg("EXTENDED_BYTE_19 W = 0x%02x\n", 0xff & regs[R_EB19]);
tda_reg("EXTENDED_BYTE_20 W = 0x%02x\n", 0xff & regs[R_EB20]);
tda_reg("EXTENDED_BYTE_21 = 0x%02x\n", 0xff & regs[R_EB21]);
tda_reg("EXTENDED_BYTE_22 = 0x%02x\n", 0xff & regs[R_EB22]);
tda_reg("EXTENDED_BYTE_23 = 0x%02x\n", 0xff & regs[R_EB23]);
}
int tda18271_read_regs(struct dvb_frontend *fe)
{
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
unsigned char buf = 0x00;
int ret;
struct i2c_msg msg[] = {
{ .addr = priv->i2c_props.addr, .flags = 0,
.buf = &buf, .len = 1 },
{ .addr = priv->i2c_props.addr, .flags = I2C_M_RD,
.buf = regs, .len = 16 }
};
tda18271_i2c_gate_ctrl(fe, 1);
/* read all registers */
ret = i2c_transfer(priv->i2c_props.adap, msg, 2);
tda18271_i2c_gate_ctrl(fe, 0);
if (ret != 2)
tda_err("ERROR: i2c_transfer returned: %d\n", ret);
if (tda18271_debug & DBG_REG)
tda18271_dump_regs(fe, 0);
return (ret == 2 ? 0 : ret);
}
int tda18271_read_extended(struct dvb_frontend *fe)
{
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
unsigned char regdump[TDA18271_NUM_REGS];
unsigned char buf = 0x00;
int ret, i;
struct i2c_msg msg[] = {
{ .addr = priv->i2c_props.addr, .flags = 0,
.buf = &buf, .len = 1 },
{ .addr = priv->i2c_props.addr, .flags = I2C_M_RD,
.buf = regdump, .len = TDA18271_NUM_REGS }
};
tda18271_i2c_gate_ctrl(fe, 1);
/* read all registers */
ret = i2c_transfer(priv->i2c_props.adap, msg, 2);
tda18271_i2c_gate_ctrl(fe, 0);
if (ret != 2)
tda_err("ERROR: i2c_transfer returned: %d\n", ret);
for (i = 0; i < TDA18271_NUM_REGS; i++) {
/* don't update write-only registers */
if ((i != R_EB9) &&
(i != R_EB16) &&
(i != R_EB17) &&
(i != R_EB19) &&
(i != R_EB20))
regs[i] = regdump[i];
}
if (tda18271_debug & DBG_REG)
tda18271_dump_regs(fe, 1);
return (ret == 2 ? 0 : ret);
}
static int __tda18271_write_regs(struct dvb_frontend *fe, int idx, int len,
bool lock_i2c)
{
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
unsigned char buf[TDA18271_NUM_REGS + 1];
struct i2c_msg msg = { .addr = priv->i2c_props.addr, .flags = 0,
.buf = buf };
int i, ret = 1, max;
BUG_ON((len == 0) || (idx + len > sizeof(buf)));
switch (priv->small_i2c) {
case TDA18271_03_BYTE_CHUNK_INIT:
max = 3;
break;
case TDA18271_08_BYTE_CHUNK_INIT:
max = 8;
break;
case TDA18271_16_BYTE_CHUNK_INIT:
max = 16;
break;
case TDA18271_39_BYTE_CHUNK_INIT:
default:
max = 39;
}
/*
* If lock_i2c is true, it will take the I2C bus for tda18271 private
* usage during the entire write ops, as otherwise, bad things could
* happen.
* During device init, several write operations will happen. So,
* tda18271_init_regs controls the I2C lock directly,
* disabling lock_i2c here.
*/
if (lock_i2c) {
tda18271_i2c_gate_ctrl(fe, 1);
i2c_lock_adapter(priv->i2c_props.adap);
}
while (len) {
if (max > len)
max = len;
buf[0] = idx;
for (i = 1; i <= max; i++)
buf[i] = regs[idx - 1 + i];
msg.len = max + 1;
/* write registers */
ret = __i2c_transfer(priv->i2c_props.adap, &msg, 1);
if (ret != 1)
break;
idx += max;
len -= max;
}
if (lock_i2c) {
i2c_unlock_adapter(priv->i2c_props.adap);
tda18271_i2c_gate_ctrl(fe, 0);
}
if (ret != 1)
tda_err("ERROR: idx = 0x%x, len = %d, "
"i2c_transfer returned: %d\n", idx, max, ret);
return (ret == 1 ? 0 : ret);
}
int tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
{
return __tda18271_write_regs(fe, idx, len, true);
}
/*---------------------------------------------------------------------*/
static int __tda18271_charge_pump_source(struct dvb_frontend *fe,
enum tda18271_pll pll, int force,
bool lock_i2c)
{
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
int r_cp = (pll == TDA18271_CAL_PLL) ? R_EB7 : R_EB4;
regs[r_cp] &= ~0x20;
regs[r_cp] |= ((force & 1) << 5);
return __tda18271_write_regs(fe, r_cp, 1, lock_i2c);
}
int tda18271_charge_pump_source(struct dvb_frontend *fe,
enum tda18271_pll pll, int force)
{
return __tda18271_charge_pump_source(fe, pll, force, true);
}
int tda18271_init_regs(struct dvb_frontend *fe)
{
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
tda_dbg("initializing registers for device @ %d-%04x\n",
i2c_adapter_id(priv->i2c_props.adap),
priv->i2c_props.addr);
/*
* Don't let any other I2C transfer to happen at adapter during init,
* as those could cause bad things
*/
tda18271_i2c_gate_ctrl(fe, 1);
i2c_lock_adapter(priv->i2c_props.adap);
/* initialize registers */
switch (priv->id) {
case TDA18271HDC1:
regs[R_ID] = 0x83;
break;
case TDA18271HDC2:
regs[R_ID] = 0x84;
break;
}
regs[R_TM] = 0x08;
regs[R_PL] = 0x80;
regs[R_EP1] = 0xc6;
regs[R_EP2] = 0xdf;
regs[R_EP3] = 0x16;
regs[R_EP4] = 0x60;
regs[R_EP5] = 0x80;
regs[R_CPD] = 0x80;
regs[R_CD1] = 0x00;
regs[R_CD2] = 0x00;
regs[R_CD3] = 0x00;
regs[R_MPD] = 0x00;
regs[R_MD1] = 0x00;
regs[R_MD2] = 0x00;
regs[R_MD3] = 0x00;
switch (priv->id) {
case TDA18271HDC1:
regs[R_EB1] = 0xff;
break;
case TDA18271HDC2:
regs[R_EB1] = 0xfc;
break;
}
regs[R_EB2] = 0x01;
regs[R_EB3] = 0x84;
regs[R_EB4] = 0x41;
regs[R_EB5] = 0x01;
regs[R_EB6] = 0x84;
regs[R_EB7] = 0x40;
regs[R_EB8] = 0x07;
regs[R_EB9] = 0x00;
regs[R_EB10] = 0x00;
regs[R_EB11] = 0x96;
switch (priv->id) {
case TDA18271HDC1:
regs[R_EB12] = 0x0f;
break;
case TDA18271HDC2:
regs[R_EB12] = 0x33;
break;
}
regs[R_EB13] = 0xc1;
regs[R_EB14] = 0x00;
regs[R_EB15] = 0x8f;
regs[R_EB16] = 0x00;
regs[R_EB17] = 0x00;
switch (priv->id) {
case TDA18271HDC1:
regs[R_EB18] = 0x00;
break;
case TDA18271HDC2:
regs[R_EB18] = 0x8c;
break;
}
regs[R_EB19] = 0x00;
regs[R_EB20] = 0x20;
switch (priv->id) {
case TDA18271HDC1:
regs[R_EB21] = 0x33;
break;
case TDA18271HDC2:
regs[R_EB21] = 0xb3;
break;
}
regs[R_EB22] = 0x48;
regs[R_EB23] = 0xb0;
__tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS, false);
/* setup agc1 gain */
regs[R_EB17] = 0x00;
__tda18271_write_regs(fe, R_EB17, 1, false);
regs[R_EB17] = 0x03;
__tda18271_write_regs(fe, R_EB17, 1, false);
regs[R_EB17] = 0x43;
__tda18271_write_regs(fe, R_EB17, 1, false);
regs[R_EB17] = 0x4c;
__tda18271_write_regs(fe, R_EB17, 1, false);
/* setup agc2 gain */
if ((priv->id) == TDA18271HDC1) {
regs[R_EB20] = 0xa0;
__tda18271_write_regs(fe, R_EB20, 1, false);
regs[R_EB20] = 0xa7;
__tda18271_write_regs(fe, R_EB20, 1, false);
regs[R_EB20] = 0xe7;
__tda18271_write_regs(fe, R_EB20, 1, false);
regs[R_EB20] = 0xec;
__tda18271_write_regs(fe, R_EB20, 1, false);
}
/* image rejection calibration */
/* low-band */
regs[R_EP3] = 0x1f;
regs[R_EP4] = 0x66;
regs[R_EP5] = 0x81;
regs[R_CPD] = 0xcc;
regs[R_CD1] = 0x6c;
regs[R_CD2] = 0x00;
regs[R_CD3] = 0x00;
regs[R_MPD] = 0xcd;
regs[R_MD1] = 0x77;
regs[R_MD2] = 0x08;
regs[R_MD3] = 0x00;
__tda18271_write_regs(fe, R_EP3, 11, false);
if ((priv->id) == TDA18271HDC2) {
/* main pll cp source on */
__tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 1, false);
msleep(1);
/* main pll cp source off */
__tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 0, false);
}
msleep(5); /* pll locking */
/* launch detector */
__tda18271_write_regs(fe, R_EP1, 1, false);
msleep(5); /* wanted low measurement */
regs[R_EP5] = 0x85;
regs[R_CPD] = 0xcb;
regs[R_CD1] = 0x66;
regs[R_CD2] = 0x70;
__tda18271_write_regs(fe, R_EP3, 7, false);
msleep(5); /* pll locking */
/* launch optimization algorithm */
__tda18271_write_regs(fe, R_EP2, 1, false);
msleep(30); /* image low optimization completion */
/* mid-band */
regs[R_EP5] = 0x82;
regs[R_CPD] = 0xa8;
regs[R_CD2] = 0x00;
regs[R_MPD] = 0xa9;
regs[R_MD1] = 0x73;
regs[R_MD2] = 0x1a;
__tda18271_write_regs(fe, R_EP3, 11, false);
msleep(5); /* pll locking */
/* launch detector */
__tda18271_write_regs(fe, R_EP1, 1, false);
msleep(5); /* wanted mid measurement */
regs[R_EP5] = 0x86;
regs[R_CPD] = 0xa8;
regs[R_CD1] = 0x66;
regs[R_CD2] = 0xa0;
__tda18271_write_regs(fe, R_EP3, 7, false);
msleep(5); /* pll locking */
/* launch optimization algorithm */
__tda18271_write_regs(fe, R_EP2, 1, false);
msleep(30); /* image mid optimization completion */
/* high-band */
regs[R_EP5] = 0x83;
regs[R_CPD] = 0x98;
regs[R_CD1] = 0x65;
regs[R_CD2] = 0x00;
regs[R_MPD] = 0x99;
regs[R_MD1] = 0x71;
regs[R_MD2] = 0xcd;
__tda18271_write_regs(fe, R_EP3, 11, false);
msleep(5); /* pll locking */
/* launch detector */
__tda18271_write_regs(fe, R_EP1, 1, false);
msleep(5); /* wanted high measurement */
regs[R_EP5] = 0x87;
regs[R_CD1] = 0x65;
regs[R_CD2] = 0x50;
__tda18271_write_regs(fe, R_EP3, 7, false);
msleep(5); /* pll locking */
/* launch optimization algorithm */
__tda18271_write_regs(fe, R_EP2, 1, false);
msleep(30); /* image high optimization completion */
/* return to normal mode */
regs[R_EP4] = 0x64;
__tda18271_write_regs(fe, R_EP4, 1, false);
/* synchronize */
__tda18271_write_regs(fe, R_EP1, 1, false);
i2c_unlock_adapter(priv->i2c_props.adap);
tda18271_i2c_gate_ctrl(fe, 0);
return 0;
}
/*---------------------------------------------------------------------*/
/*
* Standby modes, EP3 [7:5]
*
* | SM || SM_LT || SM_XT || mode description
* |=====\\=======\\=======\\===================================
* | 0 || 0 || 0 || normal mode
* |-----||-------||-------||-----------------------------------
* | || || || standby mode w/ slave tuner output
* | 1 || 0 || 0 || & loop thru & xtal oscillator on
* |-----||-------||-------||-----------------------------------
* | 1 || 1 || 0 || standby mode w/ xtal oscillator on
* |-----||-------||-------||-----------------------------------
* | 1 || 1 || 1 || power off
*
*/
int tda18271_set_standby_mode(struct dvb_frontend *fe,
int sm, int sm_lt, int sm_xt)
{
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
if (tda18271_debug & DBG_ADV)
tda_dbg("sm = %d, sm_lt = %d, sm_xt = %d\n", sm, sm_lt, sm_xt);
regs[R_EP3] &= ~0xe0; /* clear sm, sm_lt, sm_xt */
regs[R_EP3] |= (sm ? (1 << 7) : 0) |
(sm_lt ? (1 << 6) : 0) |
(sm_xt ? (1 << 5) : 0);
return tda18271_write_regs(fe, R_EP3, 1);
}
/*---------------------------------------------------------------------*/
int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq)
{
/* sets main post divider & divider bytes, but does not write them */
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
u8 d, pd;
u32 div;
int ret = tda18271_lookup_pll_map(fe, MAIN_PLL, &freq, &pd, &d);
if (tda_fail(ret))
goto fail;
regs[R_MPD] = (0x7f & pd);
div = ((d * (freq / 1000)) << 7) / 125;
regs[R_MD1] = 0x7f & (div >> 16);
regs[R_MD2] = 0xff & (div >> 8);
regs[R_MD3] = 0xff & div;
fail:
return ret;
}
int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq)
{
/* sets cal post divider & divider bytes, but does not write them */
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
u8 d, pd;
u32 div;
int ret = tda18271_lookup_pll_map(fe, CAL_PLL, &freq, &pd, &d);
if (tda_fail(ret))
goto fail;
regs[R_CPD] = pd;
div = ((d * (freq / 1000)) << 7) / 125;
regs[R_CD1] = 0x7f & (div >> 16);
regs[R_CD2] = 0xff & (div >> 8);
regs[R_CD3] = 0xff & div;
fail:
return ret;
}
/*---------------------------------------------------------------------*/
int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq)
{
/* sets bp filter bits, but does not write them */
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
u8 val;
int ret = tda18271_lookup_map(fe, BP_FILTER, freq, &val);
if (tda_fail(ret))
goto fail;
regs[R_EP1] &= ~0x07; /* clear bp filter bits */
regs[R_EP1] |= (0x07 & val);
fail:
return ret;
}
int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq)
{
/* sets K & M bits, but does not write them */
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
u8 val;
int ret = tda18271_lookup_map(fe, RF_CAL_KMCO, freq, &val);
if (tda_fail(ret))
goto fail;
regs[R_EB13] &= ~0x7c; /* clear k & m bits */
regs[R_EB13] |= (0x7c & val);
fail:
return ret;
}
int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq)
{
/* sets rf band bits, but does not write them */
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
u8 val;
int ret = tda18271_lookup_map(fe, RF_BAND, freq, &val);
if (tda_fail(ret))
goto fail;
regs[R_EP2] &= ~0xe0; /* clear rf band bits */
regs[R_EP2] |= (0xe0 & (val << 5));
fail:
return ret;
}
int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq)
{
/* sets gain taper bits, but does not write them */
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
u8 val;
int ret = tda18271_lookup_map(fe, GAIN_TAPER, freq, &val);
if (tda_fail(ret))
goto fail;
regs[R_EP2] &= ~0x1f; /* clear gain taper bits */
regs[R_EP2] |= (0x1f & val);
fail:
return ret;
}
int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq)
{
/* sets IR Meas bits, but does not write them */
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
u8 val;
int ret = tda18271_lookup_map(fe, IR_MEASURE, freq, &val);
if (tda_fail(ret))
goto fail;
regs[R_EP5] &= ~0x07;
regs[R_EP5] |= (0x07 & val);
fail:
return ret;
}
int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq)
{
/* sets rf cal byte (RFC_Cprog), but does not write it */
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
u8 val;
int ret = tda18271_lookup_map(fe, RF_CAL, freq, &val);
/* The TDA18271HD/C1 rf_cal map lookup is expected to go out of range
* for frequencies above 61.1 MHz. In these cases, the internal RF
* tracking filters calibration mechanism is used.
*
* There is no need to warn the user about this.
*/
if (ret < 0)
goto fail;
regs[R_EB14] = val;
fail:
return ret;
}
void _tda_printk(struct tda18271_priv *state, const char *level,
const char *func, const char *fmt, ...)
{
struct va_format vaf;
va_list args;
va_start(args, fmt);
vaf.fmt = fmt;
vaf.va = &args;
if (state)
printk("%s%s: [%d-%04x|%c] %pV",
level, func, i2c_adapter_id(state->i2c_props.adap),
state->i2c_props.addr,
(state->role == TDA18271_MASTER) ? 'M' : 'S',
&vaf);
else
printk("%s%s: %pV", level, func, &vaf);
va_end(args);
}

1365
drivers/media/tuners/tda18271-fe.c Normal file
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1315
drivers/media/tuners/tda18271-maps.c Normal file
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236
drivers/media/tuners/tda18271-priv.h Normal file
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/*
tda18271-priv.h - private header for the NXP TDA18271 silicon tuner
Copyright (C) 2007, 2008 Michael Krufky <mkrufky@linuxtv.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __TDA18271_PRIV_H__
#define __TDA18271_PRIV_H__
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mutex.h>
#include "tuner-i2c.h"
#include "tda18271.h"
#define R_ID 0x00 /* ID byte */
#define R_TM 0x01 /* Thermo byte */
#define R_PL 0x02 /* Power level byte */
#define R_EP1 0x03 /* Easy Prog byte 1 */
#define R_EP2 0x04 /* Easy Prog byte 2 */
#define R_EP3 0x05 /* Easy Prog byte 3 */
#define R_EP4 0x06 /* Easy Prog byte 4 */
#define R_EP5 0x07 /* Easy Prog byte 5 */
#define R_CPD 0x08 /* Cal Post-Divider byte */
#define R_CD1 0x09 /* Cal Divider byte 1 */
#define R_CD2 0x0a /* Cal Divider byte 2 */
#define R_CD3 0x0b /* Cal Divider byte 3 */
#define R_MPD 0x0c /* Main Post-Divider byte */
#define R_MD1 0x0d /* Main Divider byte 1 */
#define R_MD2 0x0e /* Main Divider byte 2 */
#define R_MD3 0x0f /* Main Divider byte 3 */
#define R_EB1 0x10 /* Extended byte 1 */
#define R_EB2 0x11 /* Extended byte 2 */
#define R_EB3 0x12 /* Extended byte 3 */
#define R_EB4 0x13 /* Extended byte 4 */
#define R_EB5 0x14 /* Extended byte 5 */
#define R_EB6 0x15 /* Extended byte 6 */
#define R_EB7 0x16 /* Extended byte 7 */
#define R_EB8 0x17 /* Extended byte 8 */
#define R_EB9 0x18 /* Extended byte 9 */
#define R_EB10 0x19 /* Extended byte 10 */
#define R_EB11 0x1a /* Extended byte 11 */
#define R_EB12 0x1b /* Extended byte 12 */
#define R_EB13 0x1c /* Extended byte 13 */
#define R_EB14 0x1d /* Extended byte 14 */
#define R_EB15 0x1e /* Extended byte 15 */
#define R_EB16 0x1f /* Extended byte 16 */
#define R_EB17 0x20 /* Extended byte 17 */
#define R_EB18 0x21 /* Extended byte 18 */
#define R_EB19 0x22 /* Extended byte 19 */
#define R_EB20 0x23 /* Extended byte 20 */
#define R_EB21 0x24 /* Extended byte 21 */
#define R_EB22 0x25 /* Extended byte 22 */
#define R_EB23 0x26 /* Extended byte 23 */
#define TDA18271_NUM_REGS 39
/*---------------------------------------------------------------------*/
struct tda18271_rf_tracking_filter_cal {
u32 rfmax;
u8 rfband;
u32 rf1_def;
u32 rf2_def;
u32 rf3_def;
u32 rf1;
u32 rf2;
u32 rf3;
s32 rf_a1;
s32 rf_b1;
s32 rf_a2;
s32 rf_b2;
};
enum tda18271_pll {
TDA18271_MAIN_PLL,
TDA18271_CAL_PLL,
};
struct tda18271_map_layout;
enum tda18271_ver {
TDA18271HDC1,
TDA18271HDC2,
};
struct tda18271_priv {
unsigned char tda18271_regs[TDA18271_NUM_REGS];
struct list_head hybrid_tuner_instance_list;
struct tuner_i2c_props i2c_props;
enum tda18271_mode mode;
enum tda18271_role role;
enum tda18271_i2c_gate gate;
enum tda18271_ver id;
enum tda18271_output_options output_opt;
enum tda18271_small_i2c small_i2c;
unsigned int config; /* interface to saa713x / tda829x */
unsigned int cal_initialized:1;
u8 tm_rfcal;
struct tda18271_map_layout *maps;
struct tda18271_std_map std;
struct tda18271_rf_tracking_filter_cal rf_cal_state[8];
struct mutex lock;
u16 if_freq;
u32 frequency;
u32 bandwidth;
};
/*---------------------------------------------------------------------*/
extern int tda18271_debug;
#define DBG_INFO 1
#define DBG_MAP 2
#define DBG_REG 4
#define DBG_ADV 8
#define DBG_CAL 16
__attribute__((format(printf, 4, 5)))
void _tda_printk(struct tda18271_priv *state, const char *level,
const char *func, const char *fmt, ...);
#define tda_printk(st, lvl, fmt, arg...) \
_tda_printk(st, lvl, __func__, fmt, ##arg)
#define tda_dprintk(st, lvl, fmt, arg...) \
do { \
if (tda18271_debug & lvl) \
tda_printk(st, KERN_DEBUG, fmt, ##arg); \
} while (0)
#define tda_info(fmt, arg...) pr_info(fmt, ##arg)
#define tda_warn(fmt, arg...) tda_printk(priv, KERN_WARNING, fmt, ##arg)
#define tda_err(fmt, arg...) tda_printk(priv, KERN_ERR, fmt, ##arg)
#define tda_dbg(fmt, arg...) tda_dprintk(priv, DBG_INFO, fmt, ##arg)
#define tda_map(fmt, arg...) tda_dprintk(priv, DBG_MAP, fmt, ##arg)
#define tda_reg(fmt, arg...) tda_dprintk(priv, DBG_REG, fmt, ##arg)
#define tda_cal(fmt, arg...) tda_dprintk(priv, DBG_CAL, fmt, ##arg)
#define tda_fail(ret) \
({ \
int __ret; \
__ret = (ret < 0); \
if (__ret) \
tda_printk(priv, KERN_ERR, \
"error %d on line %d\n", ret, __LINE__); \
__ret; \
})
/*---------------------------------------------------------------------*/
enum tda18271_map_type {
/* tda18271_pll_map */
MAIN_PLL,
CAL_PLL,
/* tda18271_map */
RF_CAL,
RF_CAL_KMCO,
RF_CAL_DC_OVER_DT,
BP_FILTER,
RF_BAND,
GAIN_TAPER,
IR_MEASURE,
};
extern int tda18271_lookup_pll_map(struct dvb_frontend *fe,
enum tda18271_map_type map_type,
u32 *freq, u8 *post_div, u8 *div);
extern int tda18271_lookup_map(struct dvb_frontend *fe,
enum tda18271_map_type map_type,
u32 *freq, u8 *val);
extern int tda18271_lookup_thermometer(struct dvb_frontend *fe);
extern int tda18271_lookup_rf_band(struct dvb_frontend *fe,
u32 *freq, u8 *rf_band);
extern int tda18271_lookup_cid_target(struct dvb_frontend *fe,
u32 *freq, u8 *cid_target,
u16 *count_limit);
extern int tda18271_assign_map_layout(struct dvb_frontend *fe);
/*---------------------------------------------------------------------*/
extern int tda18271_read_regs(struct dvb_frontend *fe);
extern int tda18271_read_extended(struct dvb_frontend *fe);
extern int tda18271_write_regs(struct dvb_frontend *fe, int idx, int len);
extern int tda18271_init_regs(struct dvb_frontend *fe);
extern int tda18271_charge_pump_source(struct dvb_frontend *fe,
enum tda18271_pll pll, int force);
extern int tda18271_set_standby_mode(struct dvb_frontend *fe,
int sm, int sm_lt, int sm_xt);
extern int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq);
extern int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq);
extern int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq);
extern int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq);
extern int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq);
extern int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq);
extern int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq);
extern int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq);
#endif /* __TDA18271_PRIV_H__ */
/*
* Overrides for Emacs so that we follow Linus's tabbing style.
* ---------------------------------------------------------------------------
* Local variables:
* c-basic-offset: 8
* End:
*/

139
drivers/media/tuners/tda18271.h Normal file
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/*
tda18271.h - header for the Philips / NXP TDA18271 silicon tuner
Copyright (C) 2007, 2008 Michael Krufky <mkrufky@linuxtv.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __TDA18271_H__
#define __TDA18271_H__
#include <linux/i2c.h>
#include "dvb_frontend.h"
struct tda18271_std_map_item {
u16 if_freq;
/* EP3[4:3] */
unsigned int agc_mode:2;
/* EP3[2:0] */
unsigned int std:3;
/* EP4[7] */
unsigned int fm_rfn:1;
/* EP4[4:2] */
unsigned int if_lvl:3;
/* EB22[6:0] */
unsigned int rfagc_top:7;
};
struct tda18271_std_map {
struct tda18271_std_map_item fm_radio;
struct tda18271_std_map_item atv_b;
struct tda18271_std_map_item atv_dk;
struct tda18271_std_map_item atv_gh;
struct tda18271_std_map_item atv_i;
struct tda18271_std_map_item atv_l;
struct tda18271_std_map_item atv_lc;
struct tda18271_std_map_item atv_mn;
struct tda18271_std_map_item atsc_6;
struct tda18271_std_map_item dvbt_6;
struct tda18271_std_map_item dvbt_7;
struct tda18271_std_map_item dvbt_8;
struct tda18271_std_map_item qam_6;
struct tda18271_std_map_item qam_7;
struct tda18271_std_map_item qam_8;
};
enum tda18271_role {
TDA18271_MASTER = 0,
TDA18271_SLAVE,
};
enum tda18271_i2c_gate {
TDA18271_GATE_AUTO = 0,
TDA18271_GATE_ANALOG,
TDA18271_GATE_DIGITAL,
};
enum tda18271_output_options {
/* slave tuner output & loop thru & xtal oscillator always on */
TDA18271_OUTPUT_LT_XT_ON = 0,
/* slave tuner output loop thru off */
TDA18271_OUTPUT_LT_OFF = 1,
/* xtal oscillator off */
TDA18271_OUTPUT_XT_OFF = 2,
};
enum tda18271_small_i2c {
TDA18271_39_BYTE_CHUNK_INIT = 0,
TDA18271_16_BYTE_CHUNK_INIT = 16,
TDA18271_08_BYTE_CHUNK_INIT = 8,
TDA18271_03_BYTE_CHUNK_INIT = 3,
};
struct tda18271_config {
/* override default if freq / std settings (optional) */
struct tda18271_std_map *std_map;
/* master / slave tuner: master uses main pll, slave uses cal pll */
enum tda18271_role role;
/* use i2c gate provided by analog or digital demod */
enum tda18271_i2c_gate gate;
/* output options that can be disabled */
enum tda18271_output_options output_opt;
/* some i2c providers can't write all 39 registers at once */
enum tda18271_small_i2c small_i2c;
/* force rf tracking filter calibration on startup */
unsigned int rf_cal_on_startup:1;
/* prevent any register access during attach(),
* delaying both IR & RF calibration until init()
* module option 'cal' overrides this delay */
unsigned int delay_cal:1;
/* interface to saa713x / tda829x */
unsigned int config;
};
#define TDA18271_CALLBACK_CMD_AGC_ENABLE 0
enum tda18271_mode {
TDA18271_ANALOG = 0,
TDA18271_DIGITAL,
};
#if IS_ENABLED(CONFIG_MEDIA_TUNER_TDA18271)
extern struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr,
struct i2c_adapter *i2c,
struct tda18271_config *cfg);
#else
static inline struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe,
u8 addr,
struct i2c_adapter *i2c,
struct tda18271_config *cfg)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif /* __TDA18271_H__ */

917
drivers/media/tuners/tda827x.c Normal file
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/*
*
* (c) 2005 Hartmut Hackmann
* (c) 2007 Michael Krufky
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <asm/types.h>
#include <linux/dvb/frontend.h>
#include <linux/videodev2.h>
#include "tda827x.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
#define dprintk(args...) \
do { \
if (debug) printk(KERN_DEBUG "tda827x: " args); \
} while (0)
struct tda827x_priv {
int i2c_addr;
struct i2c_adapter *i2c_adap;
struct tda827x_config *cfg;
unsigned int sgIF;
unsigned char lpsel;
u32 frequency;
u32 bandwidth;
};
static void tda827x_set_std(struct dvb_frontend *fe,
struct analog_parameters *params)
{
struct tda827x_priv *priv = fe->tuner_priv;
char *mode;
priv->lpsel = 0;
if (params->std & V4L2_STD_MN) {
priv->sgIF = 92;
priv->lpsel = 1;
mode = "MN";
} else if (params->std & V4L2_STD_B) {
priv->sgIF = 108;
mode = "B";
} else if (params->std & V4L2_STD_GH) {
priv->sgIF = 124;
mode = "GH";
} else if (params->std & V4L2_STD_PAL_I) {
priv->sgIF = 124;
mode = "I";
} else if (params->std & V4L2_STD_DK) {
priv->sgIF = 124;
mode = "DK";
} else if (params->std & V4L2_STD_SECAM_L) {
priv->sgIF = 124;
mode = "L";
} else if (params->std & V4L2_STD_SECAM_LC) {
priv->sgIF = 20;
mode = "LC";
} else {
priv->sgIF = 124;
mode = "xx";
}
if (params->mode == V4L2_TUNER_RADIO) {
priv->sgIF = 88; /* if frequency is 5.5 MHz */
dprintk("setting tda827x to radio FM\n");
} else
dprintk("setting tda827x to system %s\n", mode);
}
/* ------------------------------------------------------------------ */
struct tda827x_data {
u32 lomax;
u8 spd;
u8 bs;
u8 bp;
u8 cp;
u8 gc3;
u8 div1p5;
};
static const struct tda827x_data tda827x_table[] = {
{ .lomax = 62000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 1},
{ .lomax = 66000000, .spd = 3, .bs = 3, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 1},
{ .lomax = 76000000, .spd = 3, .bs = 1, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 0},
{ .lomax = 84000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 0},
{ .lomax = 93000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 1, .div1p5 = 0},
{ .lomax = 98000000, .spd = 3, .bs = 3, .bp = 0, .cp = 0, .gc3 = 1, .div1p5 = 0},
{ .lomax = 109000000, .spd = 3, .bs = 3, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0},
{ .lomax = 123000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 1},
{ .lomax = 133000000, .spd = 2, .bs = 3, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 1},
{ .lomax = 151000000, .spd = 2, .bs = 1, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0},
{ .lomax = 154000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0},
{ .lomax = 181000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 0, .div1p5 = 0},
{ .lomax = 185000000, .spd = 2, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
{ .lomax = 217000000, .spd = 2, .bs = 3, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
{ .lomax = 244000000, .spd = 1, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 1},
{ .lomax = 265000000, .spd = 1, .bs = 3, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 1},
{ .lomax = 302000000, .spd = 1, .bs = 1, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
{ .lomax = 324000000, .spd = 1, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
{ .lomax = 370000000, .spd = 1, .bs = 2, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0},
{ .lomax = 454000000, .spd = 1, .bs = 3, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0},
{ .lomax = 493000000, .spd = 0, .bs = 2, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 1},
{ .lomax = 530000000, .spd = 0, .bs = 3, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 1},
{ .lomax = 554000000, .spd = 0, .bs = 1, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0},
{ .lomax = 604000000, .spd = 0, .bs = 1, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0},
{ .lomax = 696000000, .spd = 0, .bs = 2, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0},
{ .lomax = 740000000, .spd = 0, .bs = 2, .bp = 4, .cp = 1, .gc3 = 0, .div1p5 = 0},
{ .lomax = 820000000, .spd = 0, .bs = 3, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0},
{ .lomax = 865000000, .spd = 0, .bs = 3, .bp = 4, .cp = 1, .gc3 = 0, .div1p5 = 0},
{ .lomax = 0, .spd = 0, .bs = 0, .bp = 0, .cp = 0, .gc3 = 0, .div1p5 = 0}
};
static int tuner_transfer(struct dvb_frontend *fe,
struct i2c_msg *msg,
const int size)
{
int rc;
struct tda827x_priv *priv = fe->tuner_priv;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
rc = i2c_transfer(priv->i2c_adap, msg, size);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
if (rc >= 0 && rc != size)
return -EIO;
return rc;
}
static int tda827xo_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct tda827x_priv *priv = fe->tuner_priv;
u8 buf[14];
int rc;
struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
.buf = buf, .len = sizeof(buf) };
int i, tuner_freq, if_freq;
u32 N;
dprintk("%s:\n", __func__);
if (c->bandwidth_hz == 0) {
if_freq = 5000000;
} else if (c->bandwidth_hz <= 6000000) {
if_freq = 4000000;
} else if (c->bandwidth_hz <= 7000000) {
if_freq = 4500000;
} else { /* 8 MHz */
if_freq = 5000000;
}
tuner_freq = c->frequency;
i = 0;
while (tda827x_table[i].lomax < tuner_freq) {
if (tda827x_table[i + 1].lomax == 0)
break;
i++;
}
tuner_freq += if_freq;
N = ((tuner_freq + 125000) / 250000) << (tda827x_table[i].spd + 2);
buf[0] = 0;
buf[1] = (N>>8) | 0x40;
buf[2] = N & 0xff;
buf[3] = 0;
buf[4] = 0x52;
buf[5] = (tda827x_table[i].spd << 6) + (tda827x_table[i].div1p5 << 5) +
(tda827x_table[i].bs << 3) +
tda827x_table[i].bp;
buf[6] = (tda827x_table[i].gc3 << 4) + 0x8f;
buf[7] = 0xbf;
buf[8] = 0x2a;
buf[9] = 0x05;
buf[10] = 0xff;
buf[11] = 0x00;
buf[12] = 0x00;
buf[13] = 0x40;
msg.len = 14;
rc = tuner_transfer(fe, &msg, 1);
if (rc < 0)
goto err;
msleep(500);
/* correct CP value */
buf[0] = 0x30;
buf[1] = 0x50 + tda827x_table[i].cp;
msg.len = 2;
rc = tuner_transfer(fe, &msg, 1);
if (rc < 0)
goto err;
priv->frequency = c->frequency;
priv->bandwidth = c->bandwidth_hz;
return 0;
err:
printk(KERN_ERR "%s: could not write to tuner at addr: 0x%02x\n",
__func__, priv->i2c_addr << 1);
return rc;
}
static int tda827xo_sleep(struct dvb_frontend *fe)
{
struct tda827x_priv *priv = fe->tuner_priv;
static u8 buf[] = { 0x30, 0xd0 };
struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
.buf = buf, .len = sizeof(buf) };
dprintk("%s:\n", __func__);
tuner_transfer(fe, &msg, 1);
if (priv->cfg && priv->cfg->sleep)
priv->cfg->sleep(fe);
return 0;
}
/* ------------------------------------------------------------------ */
static int tda827xo_set_analog_params(struct dvb_frontend *fe,
struct analog_parameters *params)
{
unsigned char tuner_reg[8];
unsigned char reg2[2];
u32 N;
int i;
struct tda827x_priv *priv = fe->tuner_priv;
struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0 };
unsigned int freq = params->frequency;
tda827x_set_std(fe, params);
if (params->mode == V4L2_TUNER_RADIO)
freq = freq / 1000;
N = freq + priv->sgIF;
i = 0;
while (tda827x_table[i].lomax < N * 62500) {
if (tda827x_table[i + 1].lomax == 0)
break;
i++;
}
N = N << tda827x_table[i].spd;
tuner_reg[0] = 0;
tuner_reg[1] = (unsigned char)(N>>8);
tuner_reg[2] = (unsigned char) N;
tuner_reg[3] = 0x40;
tuner_reg[4] = 0x52 + (priv->lpsel << 5);
tuner_reg[5] = (tda827x_table[i].spd << 6) +
(tda827x_table[i].div1p5 << 5) +
(tda827x_table[i].bs << 3) + tda827x_table[i].bp;
tuner_reg[6] = 0x8f + (tda827x_table[i].gc3 << 4);
tuner_reg[7] = 0x8f;
msg.buf = tuner_reg;
msg.len = 8;
tuner_transfer(fe, &msg, 1);
msg.buf = reg2;
msg.len = 2;
reg2[0] = 0x80;
reg2[1] = 0;
tuner_transfer(fe, &msg, 1);
reg2[0] = 0x60;
reg2[1] = 0xbf;
tuner_transfer(fe, &msg, 1);
reg2[0] = 0x30;
reg2[1] = tuner_reg[4] + 0x80;
tuner_transfer(fe, &msg, 1);
msleep(1);
reg2[0] = 0x30;
reg2[1] = tuner_reg[4] + 4;
tuner_transfer(fe, &msg, 1);
msleep(1);
reg2[0] = 0x30;
reg2[1] = tuner_reg[4];
tuner_transfer(fe, &msg, 1);
msleep(550);
reg2[0] = 0x30;
reg2[1] = (tuner_reg[4] & 0xfc) + tda827x_table[i].cp;
tuner_transfer(fe, &msg, 1);
reg2[0] = 0x60;
reg2[1] = 0x3f;
tuner_transfer(fe, &msg, 1);
reg2[0] = 0x80;
reg2[1] = 0x08; /* Vsync en */
tuner_transfer(fe, &msg, 1);
priv->frequency = params->frequency;
return 0;
}
static void tda827xo_agcf(struct dvb_frontend *fe)
{
struct tda827x_priv *priv = fe->tuner_priv;
unsigned char data[] = { 0x80, 0x0c };
struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
.buf = data, .len = 2};
tuner_transfer(fe, &msg, 1);
}
/* ------------------------------------------------------------------ */
struct tda827xa_data {
u32 lomax;
u8 svco;
u8 spd;
u8 scr;
u8 sbs;
u8 gc3;
};
static struct tda827xa_data tda827xa_dvbt[] = {
{ .lomax = 56875000, .svco = 3, .spd = 4, .scr = 0, .sbs = 0, .gc3 = 1},
{ .lomax = 67250000, .svco = 0, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
{ .lomax = 81250000, .svco = 1, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
{ .lomax = 97500000, .svco = 2, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
{ .lomax = 113750000, .svco = 3, .spd = 3, .scr = 0, .sbs = 1, .gc3 = 1},
{ .lomax = 134500000, .svco = 0, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
{ .lomax = 154000000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
{ .lomax = 162500000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
{ .lomax = 183000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
{ .lomax = 195000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1},
{ .lomax = 227500000, .svco = 3, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1},
{ .lomax = 269000000, .svco = 0, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1},
{ .lomax = 290000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1},
{ .lomax = 325000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1},
{ .lomax = 390000000, .svco = 2, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1},
{ .lomax = 455000000, .svco = 3, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1},
{ .lomax = 520000000, .svco = 0, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1},
{ .lomax = 538000000, .svco = 0, .spd = 0, .scr = 1, .sbs = 3, .gc3 = 1},
{ .lomax = 550000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1},
{ .lomax = 620000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
{ .lomax = 650000000, .svco = 1, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
{ .lomax = 700000000, .svco = 2, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
{ .lomax = 780000000, .svco = 2, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
{ .lomax = 820000000, .svco = 3, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
{ .lomax = 870000000, .svco = 3, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
{ .lomax = 911000000, .svco = 3, .spd = 0, .scr = 2, .sbs = 4, .gc3 = 0},
{ .lomax = 0, .svco = 0, .spd = 0, .scr = 0, .sbs = 0, .gc3 = 0}
};
static struct tda827xa_data tda827xa_dvbc[] = {
{ .lomax = 50125000, .svco = 2, .spd = 4, .scr = 2, .sbs = 0, .gc3 = 3},
{ .lomax = 58500000, .svco = 3, .spd = 4, .scr = 2, .sbs = 0, .gc3 = 3},
{ .lomax = 69250000, .svco = 0, .spd = 3, .scr = 2, .sbs = 0, .gc3 = 3},
{ .lomax = 83625000, .svco = 1, .spd = 3, .scr = 2, .sbs = 0, .gc3 = 3},
{ .lomax = 97500000, .svco = 2, .spd = 3, .scr = 2, .sbs = 0, .gc3 = 3},
{ .lomax = 100250000, .svco = 2, .spd = 3, .scr = 2, .sbs = 1, .gc3 = 1},
{ .lomax = 117000000, .svco = 3, .spd = 3, .scr = 2, .sbs = 1, .gc3 = 1},
{ .lomax = 138500000, .svco = 0, .spd = 2, .scr = 2, .sbs = 1, .gc3 = 1},
{ .lomax = 167250000, .svco = 1, .spd = 2, .scr = 2, .sbs = 1, .gc3 = 1},
{ .lomax = 187000000, .svco = 2, .spd = 2, .scr = 2, .sbs = 1, .gc3 = 1},
{ .lomax = 200500000, .svco = 2, .spd = 2, .scr = 2, .sbs = 2, .gc3 = 1},
{ .lomax = 234000000, .svco = 3, .spd = 2, .scr = 2, .sbs = 2, .gc3 = 3},
{ .lomax = 277000000, .svco = 0, .spd = 1, .scr = 2, .sbs = 2, .gc3 = 3},
{ .lomax = 325000000, .svco = 1, .spd = 1, .scr = 2, .sbs = 2, .gc3 = 1},
{ .lomax = 334500000, .svco = 1, .spd = 1, .scr = 2, .sbs = 3, .gc3 = 3},
{ .lomax = 401000000, .svco = 2, .spd = 1, .scr = 2, .sbs = 3, .gc3 = 3},
{ .lomax = 468000000, .svco = 3, .spd = 1, .scr = 2, .sbs = 3, .gc3 = 1},
{ .lomax = 535000000, .svco = 0, .spd = 0, .scr = 1, .sbs = 3, .gc3 = 1},
{ .lomax = 554000000, .svco = 0, .spd = 0, .scr = 2, .sbs = 3, .gc3 = 1},
{ .lomax = 638000000, .svco = 1, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 1},
{ .lomax = 669000000, .svco = 1, .spd = 0, .scr = 2, .sbs = 4, .gc3 = 1},
{ .lomax = 720000000, .svco = 2, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 1},
{ .lomax = 802000000, .svco = 2, .spd = 0, .scr = 2, .sbs = 4, .gc3 = 1},
{ .lomax = 835000000, .svco = 3, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 1},
{ .lomax = 885000000, .svco = 3, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 1},
{ .lomax = 911000000, .svco = 3, .spd = 0, .scr = 2, .sbs = 4, .gc3 = 1},
{ .lomax = 0, .svco = 0, .spd = 0, .scr = 0, .sbs = 0, .gc3 = 0}
};
static struct tda827xa_data tda827xa_analog[] = {
{ .lomax = 56875000, .svco = 3, .spd = 4, .scr = 0, .sbs = 0, .gc3 = 3},
{ .lomax = 67250000, .svco = 0, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 3},
{ .lomax = 81250000, .svco = 1, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 3},
{ .lomax = 97500000, .svco = 2, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 3},
{ .lomax = 113750000, .svco = 3, .spd = 3, .scr = 0, .sbs = 1, .gc3 = 1},
{ .lomax = 134500000, .svco = 0, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
{ .lomax = 154000000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
{ .lomax = 162500000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
{ .lomax = 183000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
{ .lomax = 195000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1},
{ .lomax = 227500000, .svco = 3, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 3},
{ .lomax = 269000000, .svco = 0, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 3},
{ .lomax = 325000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1},
{ .lomax = 390000000, .svco = 2, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 3},
{ .lomax = 455000000, .svco = 3, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 3},
{ .lomax = 520000000, .svco = 0, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1},
{ .lomax = 538000000, .svco = 0, .spd = 0, .scr = 1, .sbs = 3, .gc3 = 1},
{ .lomax = 554000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1},
{ .lomax = 620000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
{ .lomax = 650000000, .svco = 1, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
{ .lomax = 700000000, .svco = 2, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
{ .lomax = 780000000, .svco = 2, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
{ .lomax = 820000000, .svco = 3, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
{ .lomax = 870000000, .svco = 3, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
{ .lomax = 911000000, .svco = 3, .spd = 0, .scr = 2, .sbs = 4, .gc3 = 0},
{ .lomax = 0, .svco = 0, .spd = 0, .scr = 0, .sbs = 0, .gc3 = 0}
};
static int tda827xa_sleep(struct dvb_frontend *fe)
{
struct tda827x_priv *priv = fe->tuner_priv;
static u8 buf[] = { 0x30, 0x90 };
struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
.buf = buf, .len = sizeof(buf) };
dprintk("%s:\n", __func__);
tuner_transfer(fe, &msg, 1);
if (priv->cfg && priv->cfg->sleep)
priv->cfg->sleep(fe);
return 0;
}
static void tda827xa_lna_gain(struct dvb_frontend *fe, int high,
struct analog_parameters *params)
{
struct tda827x_priv *priv = fe->tuner_priv;
unsigned char buf[] = {0x22, 0x01};
int arg;
int gp_func;
struct i2c_msg msg = { .flags = 0, .buf = buf, .len = sizeof(buf) };
if (NULL == priv->cfg) {
dprintk("tda827x_config not defined, cannot set LNA gain!\n");
return;
}
msg.addr = priv->cfg->switch_addr;
if (priv->cfg->config) {
if (high)
dprintk("setting LNA to high gain\n");
else
dprintk("setting LNA to low gain\n");
}
switch (priv->cfg->config) {
case TDA8290_LNA_OFF: /* no LNA */
break;
case TDA8290_LNA_GP0_HIGH_ON: /* switch is GPIO 0 of tda8290 */
case TDA8290_LNA_GP0_HIGH_OFF:
if (params == NULL) {
gp_func = 0;
arg = 0;
} else {
/* turn Vsync on */
gp_func = 1;
if (params->std & V4L2_STD_MN)
arg = 1;
else
arg = 0;
}
if (fe->callback)
fe->callback(priv->i2c_adap->algo_data,
DVB_FRONTEND_COMPONENT_TUNER,
gp_func, arg);
buf[1] = high ? 0 : 1;
if (priv->cfg->config == TDA8290_LNA_GP0_HIGH_OFF)
buf[1] = high ? 1 : 0;
tuner_transfer(fe, &msg, 1);
break;
case TDA8290_LNA_ON_BRIDGE: /* switch with GPIO of saa713x */
if (fe->callback)
fe->callback(priv->i2c_adap->algo_data,
DVB_FRONTEND_COMPONENT_TUNER, 0, high);
break;
}
}
static int tda827xa_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct tda827x_priv *priv = fe->tuner_priv;
struct tda827xa_data *frequency_map = tda827xa_dvbt;
u8 buf[11];
struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
.buf = buf, .len = sizeof(buf) };
int i, tuner_freq, if_freq, rc;
u32 N;
dprintk("%s:\n", __func__);
tda827xa_lna_gain(fe, 1, NULL);
msleep(20);
if (c->bandwidth_hz == 0) {
if_freq = 5000000;
} else if (c->bandwidth_hz <= 6000000) {
if_freq = 4000000;
} else if (c->bandwidth_hz <= 7000000) {
if_freq = 4500000;
} else { /* 8 MHz */
if_freq = 5000000;
}
tuner_freq = c->frequency;
switch (c->delivery_system) {
case SYS_DVBC_ANNEX_A:
case SYS_DVBC_ANNEX_C:
dprintk("%s select tda827xa_dvbc\n", __func__);
frequency_map = tda827xa_dvbc;
break;
default:
break;
}
i = 0;
while (frequency_map[i].lomax < tuner_freq) {
if (frequency_map[i + 1].lomax == 0)
break;
i++;
}
tuner_freq += if_freq;
N = ((tuner_freq + 31250) / 62500) << frequency_map[i].spd;
buf[0] = 0; // subaddress
buf[1] = N >> 8;
buf[2] = N & 0xff;
buf[3] = 0;
buf[4] = 0x16;
buf[5] = (frequency_map[i].spd << 5) + (frequency_map[i].svco << 3) +
frequency_map[i].sbs;
buf[6] = 0x4b + (frequency_map[i].gc3 << 4);
buf[7] = 0x1c;
buf[8] = 0x06;
buf[9] = 0x24;
buf[10] = 0x00;
msg.len = 11;
rc = tuner_transfer(fe, &msg, 1);
if (rc < 0)
goto err;
buf[0] = 0x90;
buf[1] = 0xff;
buf[2] = 0x60;
buf[3] = 0x00;
buf[4] = 0x59; // lpsel, for 6MHz + 2
msg.len = 5;
rc = tuner_transfer(fe, &msg, 1);
if (rc < 0)
goto err;
buf[0] = 0xa0;
buf[1] = 0x40;
msg.len = 2;
rc = tuner_transfer(fe, &msg, 1);
if (rc < 0)
goto err;
msleep(11);
msg.flags = I2C_M_RD;
rc = tuner_transfer(fe, &msg, 1);
if (rc < 0)
goto err;
msg.flags = 0;
buf[1] >>= 4;
dprintk("tda8275a AGC2 gain is: %d\n", buf[1]);
if ((buf[1]) < 2) {
tda827xa_lna_gain(fe, 0, NULL);
buf[0] = 0x60;
buf[1] = 0x0c;
rc = tuner_transfer(fe, &msg, 1);
if (rc < 0)
goto err;
}
buf[0] = 0xc0;
buf[1] = 0x99; // lpsel, for 6MHz + 2
rc = tuner_transfer(fe, &msg, 1);
if (rc < 0)
goto err;
buf[0] = 0x60;
buf[1] = 0x3c;
rc = tuner_transfer(fe, &msg, 1);
if (rc < 0)
goto err;
/* correct CP value */
buf[0] = 0x30;
buf[1] = 0x10 + frequency_map[i].scr;
rc = tuner_transfer(fe, &msg, 1);
if (rc < 0)
goto err;
msleep(163);
buf[0] = 0xc0;
buf[1] = 0x39; // lpsel, for 6MHz + 2
rc = tuner_transfer(fe, &msg, 1);
if (rc < 0)
goto err;
msleep(3);
/* freeze AGC1 */
buf[0] = 0x50;
buf[1] = 0x4f + (frequency_map[i].gc3 << 4);
rc = tuner_transfer(fe, &msg, 1);
if (rc < 0)
goto err;
priv->frequency = c->frequency;
priv->bandwidth = c->bandwidth_hz;
return 0;
err:
printk(KERN_ERR "%s: could not write to tuner at addr: 0x%02x\n",
__func__, priv->i2c_addr << 1);
return rc;
}
static int tda827xa_set_analog_params(struct dvb_frontend *fe,
struct analog_parameters *params)
{
unsigned char tuner_reg[11];
u32 N;
int i;
struct tda827x_priv *priv = fe->tuner_priv;
struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
.buf = tuner_reg, .len = sizeof(tuner_reg) };
unsigned int freq = params->frequency;
tda827x_set_std(fe, params);
tda827xa_lna_gain(fe, 1, params);
msleep(10);
if (params->mode == V4L2_TUNER_RADIO)
freq = freq / 1000;
N = freq + priv->sgIF;
i = 0;
while (tda827xa_analog[i].lomax < N * 62500) {
if (tda827xa_analog[i + 1].lomax == 0)
break;
i++;
}
N = N << tda827xa_analog[i].spd;
tuner_reg[0] = 0;
tuner_reg[1] = (unsigned char)(N>>8);
tuner_reg[2] = (unsigned char) N;
tuner_reg[3] = 0;
tuner_reg[4] = 0x16;
tuner_reg[5] = (tda827xa_analog[i].spd << 5) +
(tda827xa_analog[i].svco << 3) +
tda827xa_analog[i].sbs;
tuner_reg[6] = 0x8b + (tda827xa_analog[i].gc3 << 4);
tuner_reg[7] = 0x1c;
tuner_reg[8] = 4;
tuner_reg[9] = 0x20;
tuner_reg[10] = 0x00;
msg.len = 11;
tuner_transfer(fe, &msg, 1);
tuner_reg[0] = 0x90;
tuner_reg[1] = 0xff;
tuner_reg[2] = 0xe0;
tuner_reg[3] = 0;
tuner_reg[4] = 0x99 + (priv->lpsel << 1);
msg.len = 5;
tuner_transfer(fe, &msg, 1);
tuner_reg[0] = 0xa0;
tuner_reg[1] = 0xc0;
msg.len = 2;
tuner_transfer(fe, &msg, 1);
tuner_reg[0] = 0x30;
tuner_reg[1] = 0x10 + tda827xa_analog[i].scr;
tuner_transfer(fe, &msg, 1);
msg.flags = I2C_M_RD;
tuner_transfer(fe, &msg, 1);
msg.flags = 0;
tuner_reg[1] >>= 4;
dprintk("AGC2 gain is: %d\n", tuner_reg[1]);
if (tuner_reg[1] < 1)
tda827xa_lna_gain(fe, 0, params);
msleep(100);
tuner_reg[0] = 0x60;
tuner_reg[1] = 0x3c;
tuner_transfer(fe, &msg, 1);
msleep(163);
tuner_reg[0] = 0x50;
tuner_reg[1] = 0x8f + (tda827xa_analog[i].gc3 << 4);
tuner_transfer(fe, &msg, 1);
tuner_reg[0] = 0x80;
tuner_reg[1] = 0x28;
tuner_transfer(fe, &msg, 1);
tuner_reg[0] = 0xb0;
tuner_reg[1] = 0x01;
tuner_transfer(fe, &msg, 1);
tuner_reg[0] = 0xc0;
tuner_reg[1] = 0x19 + (priv->lpsel << 1);
tuner_transfer(fe, &msg, 1);
priv->frequency = params->frequency;
return 0;
}
static void tda827xa_agcf(struct dvb_frontend *fe)
{
struct tda827x_priv *priv = fe->tuner_priv;
unsigned char data[] = {0x80, 0x2c};
struct i2c_msg msg = {.addr = priv->i2c_addr, .flags = 0,
.buf = data, .len = 2};
tuner_transfer(fe, &msg, 1);
}
/* ------------------------------------------------------------------ */
static int tda827x_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
return 0;
}
static int tda827x_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct tda827x_priv *priv = fe->tuner_priv;
*frequency = priv->frequency;
return 0;
}
static int tda827x_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
{
struct tda827x_priv *priv = fe->tuner_priv;
*bandwidth = priv->bandwidth;
return 0;
}
static int tda827x_init(struct dvb_frontend *fe)
{
struct tda827x_priv *priv = fe->tuner_priv;
dprintk("%s:\n", __func__);
if (priv->cfg && priv->cfg->init)
priv->cfg->init(fe);
return 0;
}
static int tda827x_probe_version(struct dvb_frontend *fe);
static int tda827x_initial_init(struct dvb_frontend *fe)
{
int ret;
ret = tda827x_probe_version(fe);
if (ret)
return ret;
return fe->ops.tuner_ops.init(fe);
}
static int tda827x_initial_sleep(struct dvb_frontend *fe)
{
int ret;
ret = tda827x_probe_version(fe);
if (ret)
return ret;
return fe->ops.tuner_ops.sleep(fe);
}
static struct dvb_tuner_ops tda827xo_tuner_ops = {
.info = {
.name = "Philips TDA827X",
.frequency_min = 55000000,
.frequency_max = 860000000,
.frequency_step = 250000
},
.release = tda827x_release,
.init = tda827x_initial_init,
.sleep = tda827x_initial_sleep,
.set_params = tda827xo_set_params,
.set_analog_params = tda827xo_set_analog_params,
.get_frequency = tda827x_get_frequency,
.get_bandwidth = tda827x_get_bandwidth,
};
static struct dvb_tuner_ops tda827xa_tuner_ops = {
.info = {
.name = "Philips TDA827XA",
.frequency_min = 44000000,
.frequency_max = 906000000,
.frequency_step = 62500
},
.release = tda827x_release,
.init = tda827x_init,
.sleep = tda827xa_sleep,
.set_params = tda827xa_set_params,
.set_analog_params = tda827xa_set_analog_params,
.get_frequency = tda827x_get_frequency,
.get_bandwidth = tda827x_get_bandwidth,
};
static int tda827x_probe_version(struct dvb_frontend *fe)
{
u8 data;
int rc;
struct tda827x_priv *priv = fe->tuner_priv;
struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = I2C_M_RD,
.buf = &data, .len = 1 };
rc = tuner_transfer(fe, &msg, 1);
if (rc < 0) {
printk("%s: could not read from tuner at addr: 0x%02x\n",
__func__, msg.addr << 1);
return rc;
}
if ((data & 0x3c) == 0) {
dprintk("tda827x tuner found\n");
fe->ops.tuner_ops.init = tda827x_init;
fe->ops.tuner_ops.sleep = tda827xo_sleep;
if (priv->cfg)
priv->cfg->agcf = tda827xo_agcf;
} else {
dprintk("tda827xa tuner found\n");
memcpy(&fe->ops.tuner_ops, &tda827xa_tuner_ops, sizeof(struct dvb_tuner_ops));
if (priv->cfg)
priv->cfg->agcf = tda827xa_agcf;
}
return 0;
}
struct dvb_frontend *tda827x_attach(struct dvb_frontend *fe, int addr,
struct i2c_adapter *i2c,
struct tda827x_config *cfg)
{
struct tda827x_priv *priv = NULL;
dprintk("%s:\n", __func__);
priv = kzalloc(sizeof(struct tda827x_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->i2c_addr = addr;
priv->i2c_adap = i2c;
priv->cfg = cfg;
memcpy(&fe->ops.tuner_ops, &tda827xo_tuner_ops, sizeof(struct dvb_tuner_ops));
fe->tuner_priv = priv;
dprintk("type set to %s\n", fe->ops.tuner_ops.info.name);
return fe;
}
EXPORT_SYMBOL_GPL(tda827x_attach);
MODULE_DESCRIPTION("DVB TDA827x driver");
MODULE_AUTHOR("Hartmut Hackmann <hartmut.hackmann@t-online.de>");
MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
MODULE_LICENSE("GPL");
/*
* Overrides for Emacs so that we follow Linus's tabbing style.
* ---------------------------------------------------------------------------
* Local variables:
* c-basic-offset: 8
* End:
*/

69
drivers/media/tuners/tda827x.h Normal file
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@ -0,0 +1,69 @@
/*
DVB Driver for Philips tda827x / tda827xa Silicon tuners
(c) 2005 Hartmut Hackmann
(c) 2007 Michael Krufky
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __DVB_TDA827X_H__
#define __DVB_TDA827X_H__
#include <linux/i2c.h>
#include "dvb_frontend.h"
#include "tda8290.h"
struct tda827x_config
{
/* saa7134 - provided callbacks */
int (*init) (struct dvb_frontend *fe);
int (*sleep) (struct dvb_frontend *fe);
/* interface to tda829x driver */
enum tda8290_lna config;
int switch_addr;
void (*agcf)(struct dvb_frontend *fe);
};
/**
* Attach a tda827x tuner to the supplied frontend structure.
*
* @param fe Frontend to attach to.
* @param addr i2c address of the tuner.
* @param i2c i2c adapter to use.
* @param cfg optional callback function pointers.
* @return FE pointer on success, NULL on failure.
*/
#if IS_ENABLED(CONFIG_MEDIA_TUNER_TDA827X)
extern struct dvb_frontend* tda827x_attach(struct dvb_frontend *fe, int addr,
struct i2c_adapter *i2c,
struct tda827x_config *cfg);
#else
static inline struct dvb_frontend* tda827x_attach(struct dvb_frontend *fe,
int addr,
struct i2c_adapter *i2c,
struct tda827x_config *cfg)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif // CONFIG_MEDIA_TUNER_TDA827X
#endif // __DVB_TDA827X_H__

891
drivers/media/tuners/tda8290.c Normal file
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@ -0,0 +1,891 @@
/*
i2c tv tuner chip device driver
controls the philips tda8290+75 tuner chip combo.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
This "tda8290" module was split apart from the original "tuner" module.
*/
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/videodev2.h>
#include "tuner-i2c.h"
#include "tda8290.h"
#include "tda827x.h"
#include "tda18271.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "enable verbose debug messages");
static int deemphasis_50;
module_param(deemphasis_50, int, 0644);
MODULE_PARM_DESC(deemphasis_50, "0 - 75us deemphasis; 1 - 50us deemphasis");
/* ---------------------------------------------------------------------- */
struct tda8290_priv {
struct tuner_i2c_props i2c_props;
unsigned char tda8290_easy_mode;
unsigned char tda827x_addr;
unsigned char ver;
#define TDA8290 1
#define TDA8295 2
#define TDA8275 4
#define TDA8275A 8
#define TDA18271 16
struct tda827x_config cfg;
struct tda18271_std_map *tda18271_std_map;
};
/*---------------------------------------------------------------------*/
static int tda8290_i2c_bridge(struct dvb_frontend *fe, int close)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
unsigned char enable[2] = { 0x21, 0xC0 };
unsigned char disable[2] = { 0x21, 0x00 };
unsigned char *msg;
if (close) {
msg = enable;
tuner_i2c_xfer_send(&priv->i2c_props, msg, 2);
/* let the bridge stabilize */
msleep(20);
} else {
msg = disable;
tuner_i2c_xfer_send(&priv->i2c_props, msg, 2);
}
return 0;
}
static int tda8295_i2c_bridge(struct dvb_frontend *fe, int close)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
unsigned char enable[2] = { 0x45, 0xc1 };
unsigned char disable[2] = { 0x46, 0x00 };
unsigned char buf[3] = { 0x45, 0x01, 0x00 };
unsigned char *msg;
if (close) {
msg = enable;
tuner_i2c_xfer_send(&priv->i2c_props, msg, 2);
/* let the bridge stabilize */
msleep(20);
} else {
msg = disable;
tuner_i2c_xfer_send_recv(&priv->i2c_props, msg, 1, &msg[1], 1);
buf[2] = msg[1];
buf[2] &= ~0x04;
tuner_i2c_xfer_send(&priv->i2c_props, buf, 3);
msleep(5);
msg[1] |= 0x04;
tuner_i2c_xfer_send(&priv->i2c_props, msg, 2);
}
return 0;
}
/*---------------------------------------------------------------------*/
static void set_audio(struct dvb_frontend *fe,
struct analog_parameters *params)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
char* mode;
if (params->std & V4L2_STD_MN) {
priv->tda8290_easy_mode = 0x01;
mode = "MN";
} else if (params->std & V4L2_STD_B) {
priv->tda8290_easy_mode = 0x02;
mode = "B";
} else if (params->std & V4L2_STD_GH) {
priv->tda8290_easy_mode = 0x04;
mode = "GH";
} else if (params->std & V4L2_STD_PAL_I) {
priv->tda8290_easy_mode = 0x08;
mode = "I";
} else if (params->std & V4L2_STD_DK) {
priv->tda8290_easy_mode = 0x10;
mode = "DK";
} else if (params->std & V4L2_STD_SECAM_L) {
priv->tda8290_easy_mode = 0x20;
mode = "L";
} else if (params->std & V4L2_STD_SECAM_LC) {
priv->tda8290_easy_mode = 0x40;
mode = "LC";
} else {
priv->tda8290_easy_mode = 0x10;
mode = "xx";
}
if (params->mode == V4L2_TUNER_RADIO) {
/* Set TDA8295 to FM radio; Start TDA8290 with MN values */
priv->tda8290_easy_mode = (priv->ver & TDA8295) ? 0x80 : 0x01;
tuner_dbg("setting to radio FM\n");
} else {
tuner_dbg("setting tda829x to system %s\n", mode);
}
}
static struct {
unsigned char seq[2];
} fm_mode[] = {
{ { 0x01, 0x81} }, /* Put device into expert mode */
{ { 0x03, 0x48} }, /* Disable NOTCH and VIDEO filters */
{ { 0x04, 0x04} }, /* Disable color carrier filter (SSIF) */
{ { 0x05, 0x04} }, /* ADC headroom */
{ { 0x06, 0x10} }, /* group delay flat */
{ { 0x07, 0x00} }, /* use the same radio DTO values as a tda8295 */
{ { 0x08, 0x00} },
{ { 0x09, 0x80} },
{ { 0x0a, 0xda} },
{ { 0x0b, 0x4b} },
{ { 0x0c, 0x68} },
{ { 0x0d, 0x00} }, /* PLL off, no video carrier detect */
{ { 0x14, 0x00} }, /* disable auto mute if no video */
};
static void tda8290_set_params(struct dvb_frontend *fe,
struct analog_parameters *params)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
unsigned char soft_reset[] = { 0x00, 0x00 };
unsigned char easy_mode[] = { 0x01, priv->tda8290_easy_mode };
unsigned char expert_mode[] = { 0x01, 0x80 };
unsigned char agc_out_on[] = { 0x02, 0x00 };
unsigned char gainset_off[] = { 0x28, 0x14 };
unsigned char if_agc_spd[] = { 0x0f, 0x88 };
unsigned char adc_head_6[] = { 0x05, 0x04 };
unsigned char adc_head_9[] = { 0x05, 0x02 };
unsigned char adc_head_12[] = { 0x05, 0x01 };
unsigned char pll_bw_nom[] = { 0x0d, 0x47 };
unsigned char pll_bw_low[] = { 0x0d, 0x27 };
unsigned char gainset_2[] = { 0x28, 0x64 };
unsigned char agc_rst_on[] = { 0x0e, 0x0b };
unsigned char agc_rst_off[] = { 0x0e, 0x09 };
unsigned char if_agc_set[] = { 0x0f, 0x81 };
unsigned char addr_adc_sat = 0x1a;
unsigned char addr_agc_stat = 0x1d;
unsigned char addr_pll_stat = 0x1b;
unsigned char adc_sat, agc_stat,
pll_stat;
int i;
set_audio(fe, params);
if (priv->cfg.config)
tuner_dbg("tda827xa config is 0x%02x\n", priv->cfg.config);
tuner_i2c_xfer_send(&priv->i2c_props, easy_mode, 2);
tuner_i2c_xfer_send(&priv->i2c_props, agc_out_on, 2);
tuner_i2c_xfer_send(&priv->i2c_props, soft_reset, 2);
msleep(1);
if (params->mode == V4L2_TUNER_RADIO) {
unsigned char deemphasis[] = { 0x13, 1 };
/* FIXME: allow using a different deemphasis */
if (deemphasis_50)
deemphasis[1] = 2;
for (i = 0; i < ARRAY_SIZE(fm_mode); i++)
tuner_i2c_xfer_send(&priv->i2c_props, fm_mode[i].seq, 2);
tuner_i2c_xfer_send(&priv->i2c_props, deemphasis, 2);
} else {
expert_mode[1] = priv->tda8290_easy_mode + 0x80;
tuner_i2c_xfer_send(&priv->i2c_props, expert_mode, 2);
tuner_i2c_xfer_send(&priv->i2c_props, gainset_off, 2);
tuner_i2c_xfer_send(&priv->i2c_props, if_agc_spd, 2);
if (priv->tda8290_easy_mode & 0x60)
tuner_i2c_xfer_send(&priv->i2c_props, adc_head_9, 2);
else
tuner_i2c_xfer_send(&priv->i2c_props, adc_head_6, 2);
tuner_i2c_xfer_send(&priv->i2c_props, pll_bw_nom, 2);
}
if (fe->ops.analog_ops.i2c_gate_ctrl)
fe->ops.analog_ops.i2c_gate_ctrl(fe, 1);
if (fe->ops.tuner_ops.set_analog_params)
fe->ops.tuner_ops.set_analog_params(fe, params);
for (i = 0; i < 3; i++) {
tuner_i2c_xfer_send_recv(&priv->i2c_props,
&addr_pll_stat, 1, &pll_stat, 1);
if (pll_stat & 0x80) {
tuner_i2c_xfer_send_recv(&priv->i2c_props,
&addr_adc_sat, 1,
&adc_sat, 1);
tuner_i2c_xfer_send_recv(&priv->i2c_props,
&addr_agc_stat, 1,
&agc_stat, 1);
tuner_dbg("tda8290 is locked, AGC: %d\n", agc_stat);
break;
} else {
tuner_dbg("tda8290 not locked, no signal?\n");
msleep(100);
}
}
/* adjust headroom resp. gain */
if ((agc_stat > 115) || (!(pll_stat & 0x80) && (adc_sat < 20))) {
tuner_dbg("adjust gain, step 1. Agc: %d, ADC stat: %d, lock: %d\n",
agc_stat, adc_sat, pll_stat & 0x80);
tuner_i2c_xfer_send(&priv->i2c_props, gainset_2, 2);
msleep(100);
tuner_i2c_xfer_send_recv(&priv->i2c_props,
&addr_agc_stat, 1, &agc_stat, 1);
tuner_i2c_xfer_send_recv(&priv->i2c_props,
&addr_pll_stat, 1, &pll_stat, 1);
if ((agc_stat > 115) || !(pll_stat & 0x80)) {
tuner_dbg("adjust gain, step 2. Agc: %d, lock: %d\n",
agc_stat, pll_stat & 0x80);
if (priv->cfg.agcf)
priv->cfg.agcf(fe);
msleep(100);
tuner_i2c_xfer_send_recv(&priv->i2c_props,
&addr_agc_stat, 1,
&agc_stat, 1);
tuner_i2c_xfer_send_recv(&priv->i2c_props,
&addr_pll_stat, 1,
&pll_stat, 1);
if((agc_stat > 115) || !(pll_stat & 0x80)) {
tuner_dbg("adjust gain, step 3. Agc: %d\n", agc_stat);
tuner_i2c_xfer_send(&priv->i2c_props, adc_head_12, 2);
tuner_i2c_xfer_send(&priv->i2c_props, pll_bw_low, 2);
msleep(100);
}
}
}
/* l/ l' deadlock? */
if(priv->tda8290_easy_mode & 0x60) {
tuner_i2c_xfer_send_recv(&priv->i2c_props,
&addr_adc_sat, 1,
&adc_sat, 1);
tuner_i2c_xfer_send_recv(&priv->i2c_props,
&addr_pll_stat, 1,
&pll_stat, 1);
if ((adc_sat > 20) || !(pll_stat & 0x80)) {
tuner_dbg("trying to resolve SECAM L deadlock\n");
tuner_i2c_xfer_send(&priv->i2c_props, agc_rst_on, 2);
msleep(40);
tuner_i2c_xfer_send(&priv->i2c_props, agc_rst_off, 2);
}
}
if (fe->ops.analog_ops.i2c_gate_ctrl)
fe->ops.analog_ops.i2c_gate_ctrl(fe, 0);
tuner_i2c_xfer_send(&priv->i2c_props, if_agc_set, 2);
}
/*---------------------------------------------------------------------*/
static void tda8295_power(struct dvb_frontend *fe, int enable)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
unsigned char buf[] = { 0x30, 0x00 }; /* clb_stdbt */
tuner_i2c_xfer_send_recv(&priv->i2c_props, &buf[0], 1, &buf[1], 1);
if (enable)
buf[1] = 0x01;
else
buf[1] = 0x03;
tuner_i2c_xfer_send(&priv->i2c_props, buf, 2);
}
static void tda8295_set_easy_mode(struct dvb_frontend *fe, int enable)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
unsigned char buf[] = { 0x01, 0x00 };
tuner_i2c_xfer_send_recv(&priv->i2c_props, &buf[0], 1, &buf[1], 1);
if (enable)
buf[1] = 0x01; /* rising edge sets regs 0x02 - 0x23 */
else
buf[1] = 0x00; /* reset active bit */
tuner_i2c_xfer_send(&priv->i2c_props, buf, 2);
}
static void tda8295_set_video_std(struct dvb_frontend *fe)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
unsigned char buf[] = { 0x00, priv->tda8290_easy_mode };
tuner_i2c_xfer_send(&priv->i2c_props, buf, 2);
tda8295_set_easy_mode(fe, 1);
msleep(20);
tda8295_set_easy_mode(fe, 0);
}
/*---------------------------------------------------------------------*/
static void tda8295_agc1_out(struct dvb_frontend *fe, int enable)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
unsigned char buf[] = { 0x02, 0x00 }; /* DIV_FUNC */
tuner_i2c_xfer_send_recv(&priv->i2c_props, &buf[0], 1, &buf[1], 1);
if (enable)
buf[1] &= ~0x40;
else
buf[1] |= 0x40;
tuner_i2c_xfer_send(&priv->i2c_props, buf, 2);
}
static void tda8295_agc2_out(struct dvb_frontend *fe, int enable)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
unsigned char set_gpio_cf[] = { 0x44, 0x00 };
unsigned char set_gpio_val[] = { 0x46, 0x00 };
tuner_i2c_xfer_send_recv(&priv->i2c_props,
&set_gpio_cf[0], 1, &set_gpio_cf[1], 1);
tuner_i2c_xfer_send_recv(&priv->i2c_props,
&set_gpio_val[0], 1, &set_gpio_val[1], 1);
set_gpio_cf[1] &= 0xf0; /* clear GPIO_0 bits 3-0 */
if (enable) {
set_gpio_cf[1] |= 0x01; /* config GPIO_0 as Open Drain Out */
set_gpio_val[1] &= 0xfe; /* set GPIO_0 pin low */
}
tuner_i2c_xfer_send(&priv->i2c_props, set_gpio_cf, 2);
tuner_i2c_xfer_send(&priv->i2c_props, set_gpio_val, 2);
}
static int tda8295_has_signal(struct dvb_frontend *fe, u16 *signal)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
unsigned char hvpll_stat = 0x26;
unsigned char ret;
tuner_i2c_xfer_send_recv(&priv->i2c_props, &hvpll_stat, 1, &ret, 1);
*signal = (ret & 0x01) ? 65535 : 0;
return 0;
}
/*---------------------------------------------------------------------*/
static void tda8295_set_params(struct dvb_frontend *fe,
struct analog_parameters *params)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
u16 signal = 0;
unsigned char blanking_mode[] = { 0x1d, 0x00 };
set_audio(fe, params);
tuner_dbg("%s: freq = %d\n", __func__, params->frequency);
tda8295_power(fe, 1);
tda8295_agc1_out(fe, 1);
tuner_i2c_xfer_send_recv(&priv->i2c_props,
&blanking_mode[0], 1, &blanking_mode[1], 1);
tda8295_set_video_std(fe);
blanking_mode[1] = 0x03;
tuner_i2c_xfer_send(&priv->i2c_props, blanking_mode, 2);
msleep(20);
if (fe->ops.analog_ops.i2c_gate_ctrl)
fe->ops.analog_ops.i2c_gate_ctrl(fe, 1);
if (fe->ops.tuner_ops.set_analog_params)
fe->ops.tuner_ops.set_analog_params(fe, params);
if (priv->cfg.agcf)
priv->cfg.agcf(fe);
tda8295_has_signal(fe, &signal);
if (signal)
tuner_dbg("tda8295 is locked\n");
else
tuner_dbg("tda8295 not locked, no signal?\n");
if (fe->ops.analog_ops.i2c_gate_ctrl)
fe->ops.analog_ops.i2c_gate_ctrl(fe, 0);
}
/*---------------------------------------------------------------------*/
static int tda8290_has_signal(struct dvb_frontend *fe, u16 *signal)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
unsigned char i2c_get_afc[1] = { 0x1B };
unsigned char afc = 0;
tuner_i2c_xfer_send_recv(&priv->i2c_props,
i2c_get_afc, ARRAY_SIZE(i2c_get_afc), &afc, 1);
*signal = (afc & 0x80) ? 65535 : 0;
return 0;
}
/*---------------------------------------------------------------------*/
static void tda8290_standby(struct dvb_frontend *fe)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
unsigned char cb1[] = { 0x30, 0xD0 };
unsigned char tda8290_standby[] = { 0x00, 0x02 };
unsigned char tda8290_agc_tri[] = { 0x02, 0x20 };
struct i2c_msg msg = {.addr = priv->tda827x_addr, .flags=0, .buf=cb1, .len = 2};
if (fe->ops.analog_ops.i2c_gate_ctrl)
fe->ops.analog_ops.i2c_gate_ctrl(fe, 1);
if (priv->ver & TDA8275A)
cb1[1] = 0x90;
i2c_transfer(priv->i2c_props.adap, &msg, 1);
if (fe->ops.analog_ops.i2c_gate_ctrl)
fe->ops.analog_ops.i2c_gate_ctrl(fe, 0);
tuner_i2c_xfer_send(&priv->i2c_props, tda8290_agc_tri, 2);
tuner_i2c_xfer_send(&priv->i2c_props, tda8290_standby, 2);
}
static void tda8295_standby(struct dvb_frontend *fe)
{
tda8295_agc1_out(fe, 0); /* Put AGC in tri-state */
tda8295_power(fe, 0);
}
static void tda8290_init_if(struct dvb_frontend *fe)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
unsigned char set_VS[] = { 0x30, 0x6F };
unsigned char set_GP00_CF[] = { 0x20, 0x01 };
unsigned char set_GP01_CF[] = { 0x20, 0x0B };
if ((priv->cfg.config == TDA8290_LNA_GP0_HIGH_ON) ||
(priv->cfg.config == TDA8290_LNA_GP0_HIGH_OFF))
tuner_i2c_xfer_send(&priv->i2c_props, set_GP00_CF, 2);
else
tuner_i2c_xfer_send(&priv->i2c_props, set_GP01_CF, 2);
tuner_i2c_xfer_send(&priv->i2c_props, set_VS, 2);
}
static void tda8295_init_if(struct dvb_frontend *fe)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
static unsigned char set_adc_ctl[] = { 0x33, 0x14 };
static unsigned char set_adc_ctl2[] = { 0x34, 0x00 };
static unsigned char set_pll_reg6[] = { 0x3e, 0x63 };
static unsigned char set_pll_reg0[] = { 0x38, 0x23 };
static unsigned char set_pll_reg7[] = { 0x3f, 0x01 };
static unsigned char set_pll_reg10[] = { 0x42, 0x61 };
static unsigned char set_gpio_reg0[] = { 0x44, 0x0b };
tda8295_power(fe, 1);
tda8295_set_easy_mode(fe, 0);
tda8295_set_video_std(fe);
tuner_i2c_xfer_send(&priv->i2c_props, set_adc_ctl, 2);
tuner_i2c_xfer_send(&priv->i2c_props, set_adc_ctl2, 2);
tuner_i2c_xfer_send(&priv->i2c_props, set_pll_reg6, 2);
tuner_i2c_xfer_send(&priv->i2c_props, set_pll_reg0, 2);
tuner_i2c_xfer_send(&priv->i2c_props, set_pll_reg7, 2);
tuner_i2c_xfer_send(&priv->i2c_props, set_pll_reg10, 2);
tuner_i2c_xfer_send(&priv->i2c_props, set_gpio_reg0, 2);
tda8295_agc1_out(fe, 0);
tda8295_agc2_out(fe, 0);
}
static void tda8290_init_tuner(struct dvb_frontend *fe)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
unsigned char tda8275_init[] = { 0x00, 0x00, 0x00, 0x40, 0xdC, 0x04, 0xAf,
0x3F, 0x2A, 0x04, 0xFF, 0x00, 0x00, 0x40 };
unsigned char tda8275a_init[] = { 0x00, 0x00, 0x00, 0x00, 0xdC, 0x05, 0x8b,
0x0c, 0x04, 0x20, 0xFF, 0x00, 0x00, 0x4b };
struct i2c_msg msg = {.addr = priv->tda827x_addr, .flags=0,
.buf=tda8275_init, .len = 14};
if (priv->ver & TDA8275A)
msg.buf = tda8275a_init;
if (fe->ops.analog_ops.i2c_gate_ctrl)
fe->ops.analog_ops.i2c_gate_ctrl(fe, 1);
i2c_transfer(priv->i2c_props.adap, &msg, 1);
if (fe->ops.analog_ops.i2c_gate_ctrl)
fe->ops.analog_ops.i2c_gate_ctrl(fe, 0);
}
/*---------------------------------------------------------------------*/
static void tda829x_release(struct dvb_frontend *fe)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
/* only try to release the tuner if we've
* attached it from within this module */
if (priv->ver & (TDA18271 | TDA8275 | TDA8275A))
if (fe->ops.tuner_ops.release)
fe->ops.tuner_ops.release(fe);
kfree(fe->analog_demod_priv);
fe->analog_demod_priv = NULL;
}
static struct tda18271_config tda829x_tda18271_config = {
.gate = TDA18271_GATE_ANALOG,
};
static int tda829x_find_tuner(struct dvb_frontend *fe)
{
struct tda8290_priv *priv = fe->analog_demod_priv;
int i, ret, tuners_found;
u32 tuner_addrs;
u8 data;
struct i2c_msg msg = { .flags = I2C_M_RD, .buf = &data, .len = 1 };
if (fe->ops.analog_ops.i2c_gate_ctrl)
fe->ops.analog_ops.i2c_gate_ctrl(fe, 1);
/* probe for tuner chip */
tuners_found = 0;
tuner_addrs = 0;
for (i = 0x60; i <= 0x63; i++) {
msg.addr = i;
ret = i2c_transfer(priv->i2c_props.adap, &msg, 1);
if (ret == 1) {
tuners_found++;
tuner_addrs = (tuner_addrs << 8) + i;
}
}
/* if there is more than one tuner, we expect the right one is
behind the bridge and we choose the highest address that doesn't
give a response now
*/
if (fe->ops.analog_ops.i2c_gate_ctrl)
fe->ops.analog_ops.i2c_gate_ctrl(fe, 0);
if (tuners_found > 1)
for (i = 0; i < tuners_found; i++) {
msg.addr = tuner_addrs & 0xff;
ret = i2c_transfer(priv->i2c_props.adap, &msg, 1);
if (ret == 1)
tuner_addrs = tuner_addrs >> 8;
else
break;
}
if (tuner_addrs == 0) {
tuner_addrs = 0x60;
tuner_info("could not clearly identify tuner address, "
"defaulting to %x\n", tuner_addrs);
} else {
tuner_addrs = tuner_addrs & 0xff;
tuner_info("setting tuner address to %x\n", tuner_addrs);
}
priv->tda827x_addr = tuner_addrs;
msg.addr = tuner_addrs;
if (fe->ops.analog_ops.i2c_gate_ctrl)
fe->ops.analog_ops.i2c_gate_ctrl(fe, 1);
ret = i2c_transfer(priv->i2c_props.adap, &msg, 1);
if (ret != 1) {
tuner_warn("tuner access failed!\n");
if (fe->ops.analog_ops.i2c_gate_ctrl)
fe->ops.analog_ops.i2c_gate_ctrl(fe, 0);
return -EREMOTEIO;
}
if ((data == 0x83) || (data == 0x84)) {
priv->ver |= TDA18271;
tda829x_tda18271_config.config = priv->cfg.config;
tda829x_tda18271_config.std_map = priv->tda18271_std_map;
dvb_attach(tda18271_attach, fe, priv->tda827x_addr,
priv->i2c_props.adap, &tda829x_tda18271_config);
} else {
if ((data & 0x3c) == 0)
priv->ver |= TDA8275;
else
priv->ver |= TDA8275A;
dvb_attach(tda827x_attach, fe, priv->tda827x_addr,
priv->i2c_props.adap, &priv->cfg);
priv->cfg.switch_addr = priv->i2c_props.addr;
}
if (fe->ops.tuner_ops.init)
fe->ops.tuner_ops.init(fe);
if (fe->ops.tuner_ops.sleep)
fe->ops.tuner_ops.sleep(fe);
if (fe->ops.analog_ops.i2c_gate_ctrl)
fe->ops.analog_ops.i2c_gate_ctrl(fe, 0);
return 0;
}
static int tda8290_probe(struct tuner_i2c_props *i2c_props)
{
#define TDA8290_ID 0x89
u8 reg = 0x1f, id;
struct i2c_msg msg_read[] = {
{ .addr = i2c_props->addr, .flags = 0, .len = 1, .buf = &reg },
{ .addr = i2c_props->addr, .flags = I2C_M_RD, .len = 1, .buf = &id },
};
/* detect tda8290 */
if (i2c_transfer(i2c_props->adap, msg_read, 2) != 2) {
printk(KERN_WARNING "%s: couldn't read register 0x%02x\n",
__func__, reg);
return -ENODEV;
}
if (id == TDA8290_ID) {
if (debug)
printk(KERN_DEBUG "%s: tda8290 detected @ %d-%04x\n",
__func__, i2c_adapter_id(i2c_props->adap),
i2c_props->addr);
return 0;
}
return -ENODEV;
}
static int tda8295_probe(struct tuner_i2c_props *i2c_props)
{
#define TDA8295_ID 0x8a
#define TDA8295C2_ID 0x8b
u8 reg = 0x2f, id;
struct i2c_msg msg_read[] = {
{ .addr = i2c_props->addr, .flags = 0, .len = 1, .buf = &reg },
{ .addr = i2c_props->addr, .flags = I2C_M_RD, .len = 1, .buf = &id },
};
/* detect tda8295 */
if (i2c_transfer(i2c_props->adap, msg_read, 2) != 2) {
printk(KERN_WARNING "%s: couldn't read register 0x%02x\n",
__func__, reg);
return -ENODEV;
}
if ((id & 0xfe) == TDA8295_ID) {
if (debug)
printk(KERN_DEBUG "%s: %s detected @ %d-%04x\n",
__func__, (id == TDA8295_ID) ?
"tda8295c1" : "tda8295c2",
i2c_adapter_id(i2c_props->adap),
i2c_props->addr);
return 0;
}
return -ENODEV;
}
static struct analog_demod_ops tda8290_ops = {
.set_params = tda8290_set_params,
.has_signal = tda8290_has_signal,
.standby = tda8290_standby,
.release = tda829x_release,
.i2c_gate_ctrl = tda8290_i2c_bridge,
};
static struct analog_demod_ops tda8295_ops = {
.set_params = tda8295_set_params,
.has_signal = tda8295_has_signal,
.standby = tda8295_standby,
.release = tda829x_release,
.i2c_gate_ctrl = tda8295_i2c_bridge,
};
struct dvb_frontend *tda829x_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c_adap, u8 i2c_addr,
struct tda829x_config *cfg)
{
struct tda8290_priv *priv = NULL;
char *name;
priv = kzalloc(sizeof(struct tda8290_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
fe->analog_demod_priv = priv;
priv->i2c_props.addr = i2c_addr;
priv->i2c_props.adap = i2c_adap;
priv->i2c_props.name = "tda829x";
if (cfg) {
priv->cfg.config = cfg->lna_cfg;
priv->tda18271_std_map = cfg->tda18271_std_map;
}
if (tda8290_probe(&priv->i2c_props) == 0) {
priv->ver = TDA8290;
memcpy(&fe->ops.analog_ops, &tda8290_ops,
sizeof(struct analog_demod_ops));
}
if (tda8295_probe(&priv->i2c_props) == 0) {
priv->ver = TDA8295;
memcpy(&fe->ops.analog_ops, &tda8295_ops,
sizeof(struct analog_demod_ops));
}
if (cfg && cfg->no_i2c_gate)
fe->ops.analog_ops.i2c_gate_ctrl = NULL;
if (!(cfg) || (TDA829X_PROBE_TUNER == cfg->probe_tuner)) {
tda8295_power(fe, 1);
if (tda829x_find_tuner(fe) < 0)
goto fail;
}
switch (priv->ver) {
case TDA8290:
name = "tda8290";
break;
case TDA8295:
name = "tda8295";
break;
case TDA8290 | TDA8275:
name = "tda8290+75";
break;
case TDA8295 | TDA8275:
name = "tda8295+75";
break;
case TDA8290 | TDA8275A:
name = "tda8290+75a";
break;
case TDA8295 | TDA8275A:
name = "tda8295+75a";
break;
case TDA8290 | TDA18271:
name = "tda8290+18271";
break;
case TDA8295 | TDA18271:
name = "tda8295+18271";
break;
default:
goto fail;
}
tuner_info("type set to %s\n", name);
fe->ops.analog_ops.info.name = name;
if (priv->ver & TDA8290) {
if (priv->ver & (TDA8275 | TDA8275A))
tda8290_init_tuner(fe);
tda8290_init_if(fe);
} else if (priv->ver & TDA8295)
tda8295_init_if(fe);
return fe;
fail:
memset(&fe->ops.analog_ops, 0, sizeof(struct analog_demod_ops));
tda829x_release(fe);
return NULL;
}
EXPORT_SYMBOL_GPL(tda829x_attach);
int tda829x_probe(struct i2c_adapter *i2c_adap, u8 i2c_addr)
{
struct tuner_i2c_props i2c_props = {
.adap = i2c_adap,
.addr = i2c_addr,
};
unsigned char soft_reset[] = { 0x00, 0x00 };
unsigned char easy_mode_b[] = { 0x01, 0x02 };
unsigned char easy_mode_g[] = { 0x01, 0x04 };
unsigned char restore_9886[] = { 0x00, 0xd6, 0x30 };
unsigned char addr_dto_lsb = 0x07;
unsigned char data;
#define PROBE_BUFFER_SIZE 8
unsigned char buf[PROBE_BUFFER_SIZE];
int i;
/* rule out tda9887, which would return the same byte repeatedly */
tuner_i2c_xfer_send_recv(&i2c_props,
soft_reset, 1, buf, PROBE_BUFFER_SIZE);
for (i = 1; i < PROBE_BUFFER_SIZE; i++) {
if (buf[i] != buf[0])
break;
}
/* all bytes are equal, not a tda829x - probably a tda9887 */
if (i == PROBE_BUFFER_SIZE)
return -ENODEV;
if ((tda8290_probe(&i2c_props) == 0) ||
(tda8295_probe(&i2c_props) == 0))
return 0;
/* fall back to old probing method */
tuner_i2c_xfer_send(&i2c_props, easy_mode_b, 2);
tuner_i2c_xfer_send(&i2c_props, soft_reset, 2);
tuner_i2c_xfer_send_recv(&i2c_props, &addr_dto_lsb, 1, &data, 1);
if (data == 0) {
tuner_i2c_xfer_send(&i2c_props, easy_mode_g, 2);
tuner_i2c_xfer_send(&i2c_props, soft_reset, 2);
tuner_i2c_xfer_send_recv(&i2c_props,
&addr_dto_lsb, 1, &data, 1);
if (data == 0x7b) {
return 0;
}
}
tuner_i2c_xfer_send(&i2c_props, restore_9886, 3);
return -ENODEV;
}
EXPORT_SYMBOL_GPL(tda829x_probe);
MODULE_DESCRIPTION("Philips/NXP TDA8290/TDA8295 analog IF demodulator driver");
MODULE_AUTHOR("Gerd Knorr, Hartmut Hackmann, Michael Krufky");
MODULE_LICENSE("GPL");
/*
* Overrides for Emacs so that we follow Linus's tabbing style.
* ---------------------------------------------------------------------------
* Local variables:
* c-basic-offset: 8
* End:
*/

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/*
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __TDA8290_H__
#define __TDA8290_H__
#include <linux/i2c.h>
#include "dvb_frontend.h"
#include "tda18271.h"
enum tda8290_lna {
TDA8290_LNA_OFF = 0,
TDA8290_LNA_GP0_HIGH_ON = 1,
TDA8290_LNA_GP0_HIGH_OFF = 2,
TDA8290_LNA_ON_BRIDGE = 3,
};
struct tda829x_config {
enum tda8290_lna lna_cfg;
unsigned int probe_tuner:1;
#define TDA829X_PROBE_TUNER 0
#define TDA829X_DONT_PROBE 1
unsigned int no_i2c_gate:1;
struct tda18271_std_map *tda18271_std_map;
};
#if IS_ENABLED(CONFIG_MEDIA_TUNER_TDA8290)
extern int tda829x_probe(struct i2c_adapter *i2c_adap, u8 i2c_addr);
extern struct dvb_frontend *tda829x_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c_adap,
u8 i2c_addr,
struct tda829x_config *cfg);
#else
static inline int tda829x_probe(struct i2c_adapter *i2c_adap, u8 i2c_addr)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return -EINVAL;
}
static inline struct dvb_frontend *tda829x_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c_adap,
u8 i2c_addr,
struct tda829x_config *cfg)
{
printk(KERN_INFO "%s: not probed - driver disabled by Kconfig\n",
__func__);
return NULL;
}
#endif
#endif /* __TDA8290_H__ */

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#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/i2c.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
#include <media/tuner.h>
#include "tuner-i2c.h"
#include "tda9887.h"
/* Chips:
TDA9885 (PAL, NTSC)
TDA9886 (PAL, SECAM, NTSC)
TDA9887 (PAL, SECAM, NTSC, FM Radio)
Used as part of several tuners
*/
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "enable verbose debug messages");
static DEFINE_MUTEX(tda9887_list_mutex);
static LIST_HEAD(hybrid_tuner_instance_list);
struct tda9887_priv {
struct tuner_i2c_props i2c_props;
struct list_head hybrid_tuner_instance_list;
unsigned char data[4];
unsigned int config;
unsigned int mode;
unsigned int audmode;
v4l2_std_id std;
bool standby;
};
/* ---------------------------------------------------------------------- */
#define UNSET (-1U)
struct tvnorm {
v4l2_std_id std;
char *name;
unsigned char b;
unsigned char c;
unsigned char e;
};
/* ---------------------------------------------------------------------- */
//
// TDA defines
//
//// first reg (b)
#define cVideoTrapBypassOFF 0x00 // bit b0
#define cVideoTrapBypassON 0x01 // bit b0
#define cAutoMuteFmInactive 0x00 // bit b1
#define cAutoMuteFmActive 0x02 // bit b1
#define cIntercarrier 0x00 // bit b2
#define cQSS 0x04 // bit b2
#define cPositiveAmTV 0x00 // bit b3:4
#define cFmRadio 0x08 // bit b3:4
#define cNegativeFmTV 0x10 // bit b3:4
#define cForcedMuteAudioON 0x20 // bit b5
#define cForcedMuteAudioOFF 0x00 // bit b5
#define cOutputPort1Active 0x00 // bit b6
#define cOutputPort1Inactive 0x40 // bit b6
#define cOutputPort2Active 0x00 // bit b7
#define cOutputPort2Inactive 0x80 // bit b7
//// second reg (c)
#define cDeemphasisOFF 0x00 // bit c5
#define cDeemphasisON 0x20 // bit c5
#define cDeemphasis75 0x00 // bit c6
#define cDeemphasis50 0x40 // bit c6
#define cAudioGain0 0x00 // bit c7
#define cAudioGain6 0x80 // bit c7
#define cTopMask 0x1f // bit c0:4
#define cTopDefault 0x10 // bit c0:4
//// third reg (e)
#define cAudioIF_4_5 0x00 // bit e0:1
#define cAudioIF_5_5 0x01 // bit e0:1
#define cAudioIF_6_0 0x02 // bit e0:1
#define cAudioIF_6_5 0x03 // bit e0:1
#define cVideoIFMask 0x1c // bit e2:4
/* Video IF selection in TV Mode (bit B3=0) */
#define cVideoIF_58_75 0x00 // bit e2:4
#define cVideoIF_45_75 0x04 // bit e2:4
#define cVideoIF_38_90 0x08 // bit e2:4
#define cVideoIF_38_00 0x0C // bit e2:4
#define cVideoIF_33_90 0x10 // bit e2:4
#define cVideoIF_33_40 0x14 // bit e2:4
#define cRadioIF_45_75 0x18 // bit e2:4
#define cRadioIF_38_90 0x1C // bit e2:4
/* IF1 selection in Radio Mode (bit B3=1) */
#define cRadioIF_33_30 0x00 // bit e2,4 (also 0x10,0x14)
#define cRadioIF_41_30 0x04 // bit e2,4
/* Output of AFC pin in radio mode when bit E7=1 */
#define cRadioAGC_SIF 0x00 // bit e3
#define cRadioAGC_FM 0x08 // bit e3
#define cTunerGainNormal 0x00 // bit e5
#define cTunerGainLow 0x20 // bit e5
#define cGating_18 0x00 // bit e6
#define cGating_36 0x40 // bit e6
#define cAgcOutON 0x80 // bit e7
#define cAgcOutOFF 0x00 // bit e7
/* ---------------------------------------------------------------------- */
static struct tvnorm tvnorms[] = {
{
.std = V4L2_STD_PAL_BG | V4L2_STD_PAL_H | V4L2_STD_PAL_N,
.name = "PAL-BGHN",
.b = ( cNegativeFmTV |
cQSS ),
.c = ( cDeemphasisON |
cDeemphasis50 |
cTopDefault),
.e = ( cGating_36 |
cAudioIF_5_5 |
cVideoIF_38_90 ),
},{
.std = V4L2_STD_PAL_I,
.name = "PAL-I",
.b = ( cNegativeFmTV |
cQSS ),
.c = ( cDeemphasisON |
cDeemphasis50 |
cTopDefault),
.e = ( cGating_36 |
cAudioIF_6_0 |
cVideoIF_38_90 ),
},{
.std = V4L2_STD_PAL_DK,
.name = "PAL-DK",
.b = ( cNegativeFmTV |
cQSS ),
.c = ( cDeemphasisON |
cDeemphasis50 |
cTopDefault),
.e = ( cGating_36 |
cAudioIF_6_5 |
cVideoIF_38_90 ),
},{
.std = V4L2_STD_PAL_M | V4L2_STD_PAL_Nc,
.name = "PAL-M/Nc",
.b = ( cNegativeFmTV |
cQSS ),
.c = ( cDeemphasisON |
cDeemphasis75 |
cTopDefault),
.e = ( cGating_36 |
cAudioIF_4_5 |
cVideoIF_45_75 ),
},{
.std = V4L2_STD_SECAM_B | V4L2_STD_SECAM_G | V4L2_STD_SECAM_H,
.name = "SECAM-BGH",
.b = ( cNegativeFmTV |
cQSS ),
.c = ( cTopDefault),
.e = ( cAudioIF_5_5 |
cVideoIF_38_90 ),
},{
.std = V4L2_STD_SECAM_L,
.name = "SECAM-L",
.b = ( cPositiveAmTV |
cQSS ),
.c = ( cTopDefault),
.e = ( cGating_36 |
cAudioIF_6_5 |
cVideoIF_38_90 ),
},{
.std = V4L2_STD_SECAM_LC,
.name = "SECAM-L'",
.b = ( cOutputPort2Inactive |
cPositiveAmTV |
cQSS ),
.c = ( cTopDefault),
.e = ( cGating_36 |
cAudioIF_6_5 |
cVideoIF_33_90 ),
},{
.std = V4L2_STD_SECAM_DK,
.name = "SECAM-DK",
.b = ( cNegativeFmTV |
cQSS ),
.c = ( cDeemphasisON |
cDeemphasis50 |
cTopDefault),
.e = ( cGating_36 |
cAudioIF_6_5 |
cVideoIF_38_90 ),
},{
.std = V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_KR,
.name = "NTSC-M",
.b = ( cNegativeFmTV |
cQSS ),
.c = ( cDeemphasisON |
cDeemphasis75 |
cTopDefault),
.e = ( cGating_36 |
cAudioIF_4_5 |
cVideoIF_45_75 ),
},{
.std = V4L2_STD_NTSC_M_JP,
.name = "NTSC-M-JP",
.b = ( cNegativeFmTV |
cQSS ),
.c = ( cDeemphasisON |
cDeemphasis50 |
cTopDefault),
.e = ( cGating_36 |
cAudioIF_4_5 |
cVideoIF_58_75 ),
}
};
static struct tvnorm radio_stereo = {
.name = "Radio Stereo",
.b = ( cFmRadio |
cQSS ),
.c = ( cDeemphasisOFF |
cAudioGain6 |
cTopDefault),
.e = ( cTunerGainLow |
cAudioIF_5_5 |
cRadioIF_38_90 ),
};
static struct tvnorm radio_mono = {
.name = "Radio Mono",
.b = ( cFmRadio |
cQSS ),
.c = ( cDeemphasisON |
cDeemphasis75 |
cTopDefault),
.e = ( cTunerGainLow |
cAudioIF_5_5 |
cRadioIF_38_90 ),
};
/* ---------------------------------------------------------------------- */
static void dump_read_message(struct dvb_frontend *fe, unsigned char *buf)
{
struct tda9887_priv *priv = fe->analog_demod_priv;
static char *afc[16] = {
"- 12.5 kHz",
"- 37.5 kHz",
"- 62.5 kHz",
"- 87.5 kHz",
"-112.5 kHz",
"-137.5 kHz",
"-162.5 kHz",
"-187.5 kHz [min]",
"+187.5 kHz [max]",
"+162.5 kHz",
"+137.5 kHz",
"+112.5 kHz",
"+ 87.5 kHz",
"+ 62.5 kHz",
"+ 37.5 kHz",
"+ 12.5 kHz",
};
tuner_info("read: 0x%2x\n", buf[0]);
tuner_info(" after power on : %s\n", (buf[0] & 0x01) ? "yes" : "no");
tuner_info(" afc : %s\n", afc[(buf[0] >> 1) & 0x0f]);
tuner_info(" fmif level : %s\n", (buf[0] & 0x20) ? "high" : "low");
tuner_info(" afc window : %s\n", (buf[0] & 0x40) ? "in" : "out");
tuner_info(" vfi level : %s\n", (buf[0] & 0x80) ? "high" : "low");
}
static void dump_write_message(struct dvb_frontend *fe, unsigned char *buf)
{
struct tda9887_priv *priv = fe->analog_demod_priv;
static char *sound[4] = {
"AM/TV",
"FM/radio",
"FM/TV",
"FM/radio"
};
static char *adjust[32] = {
"-16", "-15", "-14", "-13", "-12", "-11", "-10", "-9",
"-8", "-7", "-6", "-5", "-4", "-3", "-2", "-1",
"0", "+1", "+2", "+3", "+4", "+5", "+6", "+7",
"+8", "+9", "+10", "+11", "+12", "+13", "+14", "+15"
};
static char *deemph[4] = {
"no", "no", "75", "50"
};
static char *carrier[4] = {
"4.5 MHz",
"5.5 MHz",
"6.0 MHz",
"6.5 MHz / AM"
};
static char *vif[8] = {
"58.75 MHz",
"45.75 MHz",
"38.9 MHz",
"38.0 MHz",
"33.9 MHz",
"33.4 MHz",
"45.75 MHz + pin13",
"38.9 MHz + pin13",
};
static char *rif[4] = {
"44 MHz",
"52 MHz",
"52 MHz",
"44 MHz",
};
tuner_info("write: byte B 0x%02x\n", buf[1]);
tuner_info(" B0 video mode : %s\n",
(buf[1] & 0x01) ? "video trap" : "sound trap");
tuner_info(" B1 auto mute fm : %s\n",
(buf[1] & 0x02) ? "yes" : "no");
tuner_info(" B2 carrier mode : %s\n",
(buf[1] & 0x04) ? "QSS" : "Intercarrier");
tuner_info(" B3-4 tv sound/radio : %s\n",
sound[(buf[1] & 0x18) >> 3]);
tuner_info(" B5 force mute audio: %s\n",
(buf[1] & 0x20) ? "yes" : "no");
tuner_info(" B6 output port 1 : %s\n",
(buf[1] & 0x40) ? "high (inactive)" : "low (active)");
tuner_info(" B7 output port 2 : %s\n",
(buf[1] & 0x80) ? "high (inactive)" : "low (active)");
tuner_info("write: byte C 0x%02x\n", buf[2]);
tuner_info(" C0-4 top adjustment : %s dB\n",
adjust[buf[2] & 0x1f]);
tuner_info(" C5-6 de-emphasis : %s\n",
deemph[(buf[2] & 0x60) >> 5]);
tuner_info(" C7 audio gain : %s\n",
(buf[2] & 0x80) ? "-6" : "0");
tuner_info("write: byte E 0x%02x\n", buf[3]);
tuner_info(" E0-1 sound carrier : %s\n",
carrier[(buf[3] & 0x03)]);
tuner_info(" E6 l pll gating : %s\n",
(buf[3] & 0x40) ? "36" : "13");
if (buf[1] & 0x08) {
/* radio */
tuner_info(" E2-4 video if : %s\n",
rif[(buf[3] & 0x0c) >> 2]);
tuner_info(" E7 vif agc output : %s\n",
(buf[3] & 0x80)
? ((buf[3] & 0x10) ? "fm-agc radio" :
"sif-agc radio")
: "fm radio carrier afc");
} else {
/* video */
tuner_info(" E2-4 video if : %s\n",
vif[(buf[3] & 0x1c) >> 2]);
tuner_info(" E5 tuner gain : %s\n",
(buf[3] & 0x80)
? ((buf[3] & 0x20) ? "external" : "normal")
: ((buf[3] & 0x20) ? "minimum" : "normal"));
tuner_info(" E7 vif agc output : %s\n",
(buf[3] & 0x80) ? ((buf[3] & 0x20)
? "pin3 port, pin22 vif agc out"
: "pin22 port, pin3 vif acg ext in")
: "pin3+pin22 port");
}
tuner_info("--\n");
}
/* ---------------------------------------------------------------------- */
static int tda9887_set_tvnorm(struct dvb_frontend *fe)
{
struct tda9887_priv *priv = fe->analog_demod_priv;
struct tvnorm *norm = NULL;
char *buf = priv->data;
int i;
if (priv->mode == V4L2_TUNER_RADIO) {
if (priv->audmode == V4L2_TUNER_MODE_MONO)
norm = &radio_mono;
else
norm = &radio_stereo;
} else {
for (i = 0; i < ARRAY_SIZE(tvnorms); i++) {
if (tvnorms[i].std & priv->std) {
norm = tvnorms+i;
break;
}
}
}
if (NULL == norm) {
tuner_dbg("Unsupported tvnorm entry - audio muted\n");
return -1;
}
tuner_dbg("configure for: %s\n", norm->name);
buf[1] = norm->b;
buf[2] = norm->c;
buf[3] = norm->e;
return 0;
}
static unsigned int port1 = UNSET;
static unsigned int port2 = UNSET;
static unsigned int qss = UNSET;
static unsigned int adjust = UNSET;
module_param(port1, int, 0644);
module_param(port2, int, 0644);
module_param(qss, int, 0644);
module_param(adjust, int, 0644);
static int tda9887_set_insmod(struct dvb_frontend *fe)
{
struct tda9887_priv *priv = fe->analog_demod_priv;
char *buf = priv->data;
if (UNSET != port1) {
if (port1)
buf[1] |= cOutputPort1Inactive;
else
buf[1] &= ~cOutputPort1Inactive;
}
if (UNSET != port2) {
if (port2)
buf[1] |= cOutputPort2Inactive;
else
buf[1] &= ~cOutputPort2Inactive;
}
if (UNSET != qss) {
if (qss)
buf[1] |= cQSS;
else
buf[1] &= ~cQSS;
}
if (adjust < 0x20) {
buf[2] &= ~cTopMask;
buf[2] |= adjust;
}
return 0;
}
static int tda9887_do_config(struct dvb_frontend *fe)
{
struct tda9887_priv *priv = fe->analog_demod_priv;
char *buf = priv->data;
if (priv->config & TDA9887_PORT1_ACTIVE)
buf[1] &= ~cOutputPort1Inactive;
if (priv->config & TDA9887_PORT1_INACTIVE)
buf[1] |= cOutputPort1Inactive;
if (priv->config & TDA9887_PORT2_ACTIVE)
buf[1] &= ~cOutputPort2Inactive;
if (priv->config & TDA9887_PORT2_INACTIVE)
buf[1] |= cOutputPort2Inactive;
if (priv->config & TDA9887_QSS)
buf[1] |= cQSS;
if (priv->config & TDA9887_INTERCARRIER)
buf[1] &= ~cQSS;
if (priv->config & TDA9887_AUTOMUTE)
buf[1] |= cAutoMuteFmActive;
if (priv->config & TDA9887_DEEMPHASIS_MASK) {
buf[2] &= ~0x60;
switch (priv->config & TDA9887_DEEMPHASIS_MASK) {
case TDA9887_DEEMPHASIS_NONE:
buf[2] |= cDeemphasisOFF;
break;
case TDA9887_DEEMPHASIS_50:
buf[2] |= cDeemphasisON | cDeemphasis50;
break;
case TDA9887_DEEMPHASIS_75:
buf[2] |= cDeemphasisON | cDeemphasis75;
break;
}
}
if (priv->config & TDA9887_TOP_SET) {
buf[2] &= ~cTopMask;
buf[2] |= (priv->config >> 8) & cTopMask;
}
if ((priv->config & TDA9887_INTERCARRIER_NTSC) &&
(priv->std & V4L2_STD_NTSC))
buf[1] &= ~cQSS;
if (priv->config & TDA9887_GATING_18)
buf[3] &= ~cGating_36;
if (priv->mode == V4L2_TUNER_RADIO) {
if (priv->config & TDA9887_RIF_41_3) {
buf[3] &= ~cVideoIFMask;
buf[3] |= cRadioIF_41_30;
}
if (priv->config & TDA9887_GAIN_NORMAL)
buf[3] &= ~cTunerGainLow;
}
return 0;
}
/* ---------------------------------------------------------------------- */
static int tda9887_status(struct dvb_frontend *fe)
{
struct tda9887_priv *priv = fe->analog_demod_priv;
unsigned char buf[1];
int rc;
rc = tuner_i2c_xfer_recv(&priv->i2c_props, buf, 1);
if (rc != 1)
tuner_info("i2c i/o error: rc == %d (should be 1)\n", rc);
dump_read_message(fe, buf);
return 0;
}
static void tda9887_configure(struct dvb_frontend *fe)
{
struct tda9887_priv *priv = fe->analog_demod_priv;
int rc;
memset(priv->data,0,sizeof(priv->data));
tda9887_set_tvnorm(fe);
/* A note on the port settings:
These settings tend to depend on the specifics of the board.
By default they are set to inactive (bit value 1) by this driver,
overwriting any changes made by the tvnorm. This means that it
is the responsibility of the module using the tda9887 to set
these values in case of changes in the tvnorm.
In many cases port 2 should be made active (0) when selecting
SECAM-L, and port 2 should remain inactive (1) for SECAM-L'.
For the other standards the tda9887 application note says that
the ports should be set to active (0), but, again, that may
differ depending on the precise hardware configuration.
*/
priv->data[1] |= cOutputPort1Inactive;
priv->data[1] |= cOutputPort2Inactive;
tda9887_do_config(fe);
tda9887_set_insmod(fe);
if (priv->standby)
priv->data[1] |= cForcedMuteAudioON;
tuner_dbg("writing: b=0x%02x c=0x%02x e=0x%02x\n",
priv->data[1], priv->data[2], priv->data[3]);
if (debug > 1)
dump_write_message(fe, priv->data);
if (4 != (rc = tuner_i2c_xfer_send(&priv->i2c_props,priv->data,4)))
tuner_info("i2c i/o error: rc == %d (should be 4)\n", rc);
if (debug > 2) {
msleep_interruptible(1000);
tda9887_status(fe);
}
}
/* ---------------------------------------------------------------------- */
static void tda9887_tuner_status(struct dvb_frontend *fe)
{
struct tda9887_priv *priv = fe->analog_demod_priv;
tuner_info("Data bytes: b=0x%02x c=0x%02x e=0x%02x\n",
priv->data[1], priv->data[2], priv->data[3]);
}
static int tda9887_get_afc(struct dvb_frontend *fe, s32 *afc)
{
struct tda9887_priv *priv = fe->analog_demod_priv;
static const int AFC_BITS_2_kHz[] = {
-12500, -37500, -62500, -97500,
-112500, -137500, -162500, -187500,
187500, 162500, 137500, 112500,
97500 , 62500, 37500 , 12500
};
__u8 reg = 0;
if (priv->mode != V4L2_TUNER_RADIO)
return 0;
if (1 == tuner_i2c_xfer_recv(&priv->i2c_props, &reg, 1))
*afc = AFC_BITS_2_kHz[(reg >> 1) & 0x0f];
return 0;
}
static void tda9887_standby(struct dvb_frontend *fe)
{
struct tda9887_priv *priv = fe->analog_demod_priv;
priv->standby = true;
tda9887_configure(fe);
}
static void tda9887_set_params(struct dvb_frontend *fe,
struct analog_parameters *params)
{
struct tda9887_priv *priv = fe->analog_demod_priv;
priv->standby = false;
priv->mode = params->mode;
priv->audmode = params->audmode;
priv->std = params->std;
tda9887_configure(fe);
}
static int tda9887_set_config(struct dvb_frontend *fe, void *priv_cfg)
{
struct tda9887_priv *priv = fe->analog_demod_priv;
priv->config = *(unsigned int *)priv_cfg;
tda9887_configure(fe);
return 0;
}
static void tda9887_release(struct dvb_frontend *fe)
{
struct tda9887_priv *priv = fe->analog_demod_priv;
mutex_lock(&tda9887_list_mutex);
if (priv)
hybrid_tuner_release_state(priv);
mutex_unlock(&tda9887_list_mutex);
fe->analog_demod_priv = NULL;
}
static struct analog_demod_ops tda9887_ops = {
.info = {
.name = "tda9887",
},
.set_params = tda9887_set_params,
.standby = tda9887_standby,
.tuner_status = tda9887_tuner_status,
.get_afc = tda9887_get_afc,
.release = tda9887_release,
.set_config = tda9887_set_config,
};
struct dvb_frontend *tda9887_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c_adap,
u8 i2c_addr)
{
struct tda9887_priv *priv = NULL;
int instance;
mutex_lock(&tda9887_list_mutex);
instance = hybrid_tuner_request_state(struct tda9887_priv, priv,
hybrid_tuner_instance_list,
i2c_adap, i2c_addr, "tda9887");
switch (instance) {
case 0:
mutex_unlock(&tda9887_list_mutex);
return NULL;
case 1:
fe->analog_demod_priv = priv;
priv->standby = true;
tuner_info("tda988[5/6/7] found\n");
break;
default:
fe->analog_demod_priv = priv;
break;
}
mutex_unlock(&tda9887_list_mutex);
memcpy(&fe->ops.analog_ops, &tda9887_ops,
sizeof(struct analog_demod_ops));
return fe;
}
EXPORT_SYMBOL_GPL(tda9887_attach);
MODULE_LICENSE("GPL");
/*
* Overrides for Emacs so that we follow Linus's tabbing style.
* ---------------------------------------------------------------------------
* Local variables:
* c-basic-offset: 8
* End:
*/

38
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/*
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __TDA9887_H__
#define __TDA9887_H__
#include <linux/i2c.h>
#include "dvb_frontend.h"
/* ------------------------------------------------------------------------ */
#if IS_ENABLED(CONFIG_MEDIA_TUNER_TDA9887)
extern struct dvb_frontend *tda9887_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c_adap,
u8 i2c_addr);
#else
static inline struct dvb_frontend *tda9887_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c_adap,
u8 i2c_addr)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif /* __TDA9887_H__ */

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/*
* For Philips TEA5761 FM Chip
* I2C address is allways 0x20 (0x10 at 7-bit mode).
*
* Copyright (c) 2005-2007 Mauro Carvalho Chehab (mchehab@infradead.org)
* This code is placed under the terms of the GNUv2 General Public License
*
*/
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/videodev2.h>
#include <media/tuner.h>
#include "tuner-i2c.h"
#include "tea5761.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "enable verbose debug messages");
struct tea5761_priv {
struct tuner_i2c_props i2c_props;
u32 frequency;
bool standby;
};
/*****************************************************************************/
/***************************
* TEA5761HN I2C registers *
***************************/
/* INTREG - Read: bytes 0 and 1 / Write: byte 0 */
/* first byte for reading */
#define TEA5761_INTREG_IFFLAG 0x10
#define TEA5761_INTREG_LEVFLAG 0x8
#define TEA5761_INTREG_FRRFLAG 0x2
#define TEA5761_INTREG_BLFLAG 0x1
/* second byte for reading / byte for writing */
#define TEA5761_INTREG_IFMSK 0x10
#define TEA5761_INTREG_LEVMSK 0x8
#define TEA5761_INTREG_FRMSK 0x2
#define TEA5761_INTREG_BLMSK 0x1
/* FRQSET - Read: bytes 2 and 3 / Write: byte 1 and 2 */
/* First byte */
#define TEA5761_FRQSET_SEARCH_UP 0x80 /* 1=Station search from botton to up */
#define TEA5761_FRQSET_SEARCH_MODE 0x40 /* 1=Search mode */
/* Bits 0-5 for divider MSB */
/* Second byte */
/* Bits 0-7 for divider LSB */
/* TNCTRL - Read: bytes 4 and 5 / Write: Bytes 3 and 4 */
/* first byte */
#define TEA5761_TNCTRL_PUPD_0 0x40 /* Power UP/Power Down MSB */
#define TEA5761_TNCTRL_BLIM 0X20 /* 1= Japan Frequencies, 0= European frequencies */
#define TEA5761_TNCTRL_SWPM 0x10 /* 1= software port is FRRFLAG */
#define TEA5761_TNCTRL_IFCTC 0x08 /* 1= IF count time 15.02 ms, 0= IF count time 2.02 ms */
#define TEA5761_TNCTRL_AFM 0x04
#define TEA5761_TNCTRL_SMUTE 0x02 /* 1= Soft mute */
#define TEA5761_TNCTRL_SNC 0x01
/* second byte */
#define TEA5761_TNCTRL_MU 0x80 /* 1=Hard mute */
#define TEA5761_TNCTRL_SSL_1 0x40
#define TEA5761_TNCTRL_SSL_0 0x20
#define TEA5761_TNCTRL_HLSI 0x10
#define TEA5761_TNCTRL_MST 0x08 /* 1 = mono */
#define TEA5761_TNCTRL_SWP 0x04
#define TEA5761_TNCTRL_DTC 0x02 /* 1 = deemphasis 50 us, 0 = deemphasis 75 us */
#define TEA5761_TNCTRL_AHLSI 0x01
/* FRQCHECK - Read: bytes 6 and 7 */
/* First byte */
/* Bits 0-5 for divider MSB */
/* Second byte */
/* Bits 0-7 for divider LSB */
/* TUNCHECK - Read: bytes 8 and 9 */
/* First byte */
#define TEA5761_TUNCHECK_IF_MASK 0x7e /* IF count */
#define TEA5761_TUNCHECK_TUNTO 0x01
/* Second byte */
#define TEA5761_TUNCHECK_LEV_MASK 0xf0 /* Level Count */
#define TEA5761_TUNCHECK_LD 0x08
#define TEA5761_TUNCHECK_STEREO 0x04
/* TESTREG - Read: bytes 10 and 11 / Write: bytes 5 and 6 */
/* All zero = no test mode */
/* MANID - Read: bytes 12 and 13 */
/* First byte - should be 0x10 */
#define TEA5767_MANID_VERSION_MASK 0xf0 /* Version = 1 */
#define TEA5767_MANID_ID_MSB_MASK 0x0f /* Manufacurer ID - should be 0 */
/* Second byte - Should be 0x2b */
#define TEA5767_MANID_ID_LSB_MASK 0xfe /* Manufacturer ID - should be 0x15 */
#define TEA5767_MANID_IDAV 0x01 /* 1 = Chip has ID, 0 = Chip has no ID */
/* Chip ID - Read: bytes 14 and 15 */
/* First byte - should be 0x57 */
/* Second byte - should be 0x61 */
/*****************************************************************************/
#define FREQ_OFFSET 0 /* for TEA5767, it is 700 to give the right freq */
static void tea5761_status_dump(unsigned char *buffer)
{
unsigned int div, frq;
div = ((buffer[2] & 0x3f) << 8) | buffer[3];
frq = 1000 * (div * 32768 / 1000 + FREQ_OFFSET + 225) / 4; /* Freq in KHz */
printk(KERN_INFO "tea5761: Frequency %d.%03d KHz (divider = 0x%04x)\n",
frq / 1000, frq % 1000, div);
}
/* Freq should be specifyed at 62.5 Hz */
static int __set_radio_freq(struct dvb_frontend *fe,
unsigned int freq,
bool mono)
{
struct tea5761_priv *priv = fe->tuner_priv;
unsigned int frq = freq;
unsigned char buffer[7] = {0, 0, 0, 0, 0, 0, 0 };
unsigned div;
int rc;
tuner_dbg("radio freq counter %d\n", frq);
if (priv->standby) {
tuner_dbg("TEA5761 set to standby mode\n");
buffer[5] |= TEA5761_TNCTRL_MU;
} else {
buffer[4] |= TEA5761_TNCTRL_PUPD_0;
}
if (mono) {
tuner_dbg("TEA5761 set to mono\n");
buffer[5] |= TEA5761_TNCTRL_MST;
} else {
tuner_dbg("TEA5761 set to stereo\n");
}
div = (1000 * (frq * 4 / 16 + 700 + 225) ) >> 15;
buffer[1] = (div >> 8) & 0x3f;
buffer[2] = div & 0xff;
if (debug)
tea5761_status_dump(buffer);
if (7 != (rc = tuner_i2c_xfer_send(&priv->i2c_props, buffer, 7)))
tuner_warn("i2c i/o error: rc == %d (should be 5)\n", rc);
priv->frequency = frq * 125 / 2;
return 0;
}
static int set_radio_freq(struct dvb_frontend *fe,
struct analog_parameters *params)
{
struct tea5761_priv *priv = fe->analog_demod_priv;
priv->standby = false;
return __set_radio_freq(fe, params->frequency,
params->audmode == V4L2_TUNER_MODE_MONO);
}
static int set_radio_sleep(struct dvb_frontend *fe)
{
struct tea5761_priv *priv = fe->analog_demod_priv;
priv->standby = true;
return __set_radio_freq(fe, priv->frequency, false);
}
static int tea5761_read_status(struct dvb_frontend *fe, char *buffer)
{
struct tea5761_priv *priv = fe->tuner_priv;
int rc;
memset(buffer, 0, 16);
if (16 != (rc = tuner_i2c_xfer_recv(&priv->i2c_props, buffer, 16))) {
tuner_warn("i2c i/o error: rc == %d (should be 16)\n", rc);
return -EREMOTEIO;
}
return 0;
}
static inline int tea5761_signal(struct dvb_frontend *fe, const char *buffer)
{
struct tea5761_priv *priv = fe->tuner_priv;
int signal = ((buffer[9] & TEA5761_TUNCHECK_LEV_MASK) << (13 - 4));
tuner_dbg("Signal strength: %d\n", signal);
return signal;
}
static inline int tea5761_stereo(struct dvb_frontend *fe, const char *buffer)
{
struct tea5761_priv *priv = fe->tuner_priv;
int stereo = buffer[9] & TEA5761_TUNCHECK_STEREO;
tuner_dbg("Radio ST GET = %02x\n", stereo);
return (stereo ? V4L2_TUNER_SUB_STEREO : 0);
}
static int tea5761_get_status(struct dvb_frontend *fe, u32 *status)
{
unsigned char buffer[16];
*status = 0;
if (0 == tea5761_read_status(fe, buffer)) {
if (tea5761_signal(fe, buffer))
*status = TUNER_STATUS_LOCKED;
if (tea5761_stereo(fe, buffer))
*status |= TUNER_STATUS_STEREO;
}
return 0;
}
static int tea5761_get_rf_strength(struct dvb_frontend *fe, u16 *strength)
{
unsigned char buffer[16];
*strength = 0;
if (0 == tea5761_read_status(fe, buffer))
*strength = tea5761_signal(fe, buffer);
return 0;
}
int tea5761_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr)
{
unsigned char buffer[16];
int rc;
struct tuner_i2c_props i2c = { .adap = i2c_adap, .addr = i2c_addr };
if (16 != (rc = tuner_i2c_xfer_recv(&i2c, buffer, 16))) {
printk(KERN_WARNING "it is not a TEA5761. Received %i chars.\n", rc);
return -EINVAL;
}
if ((buffer[13] != 0x2b) || (buffer[14] != 0x57) || (buffer[15] != 0x061)) {
printk(KERN_WARNING "Manufacturer ID= 0x%02x, Chip ID = %02x%02x."
" It is not a TEA5761\n",
buffer[13], buffer[14], buffer[15]);
return -EINVAL;
}
printk(KERN_WARNING "tea5761: TEA%02x%02x detected. "
"Manufacturer ID= 0x%02x\n",
buffer[14], buffer[15], buffer[13]);
return 0;
}
static int tea5761_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
return 0;
}
static int tea5761_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct tea5761_priv *priv = fe->tuner_priv;
*frequency = priv->frequency;
return 0;
}
static struct dvb_tuner_ops tea5761_tuner_ops = {
.info = {
.name = "tea5761", // Philips TEA5761HN FM Radio
},
.set_analog_params = set_radio_freq,
.sleep = set_radio_sleep,
.release = tea5761_release,
.get_frequency = tea5761_get_frequency,
.get_status = tea5761_get_status,
.get_rf_strength = tea5761_get_rf_strength,
};
struct dvb_frontend *tea5761_attach(struct dvb_frontend *fe,
struct i2c_adapter* i2c_adap,
u8 i2c_addr)
{
struct tea5761_priv *priv = NULL;
if (tea5761_autodetection(i2c_adap, i2c_addr) != 0)
return NULL;
priv = kzalloc(sizeof(struct tea5761_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
fe->tuner_priv = priv;
priv->i2c_props.addr = i2c_addr;
priv->i2c_props.adap = i2c_adap;
priv->i2c_props.name = "tea5761";
memcpy(&fe->ops.tuner_ops, &tea5761_tuner_ops,
sizeof(struct dvb_tuner_ops));
tuner_info("type set to %s\n", "Philips TEA5761HN FM Radio");
return fe;
}
EXPORT_SYMBOL_GPL(tea5761_attach);
EXPORT_SYMBOL_GPL(tea5761_autodetection);
MODULE_DESCRIPTION("Philips TEA5761 FM tuner driver");
MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@infradead.org>");
MODULE_LICENSE("GPL");

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/*
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __TEA5761_H__
#define __TEA5761_H__
#include <linux/i2c.h>
#include "dvb_frontend.h"
#if IS_ENABLED(CONFIG_MEDIA_TUNER_TEA5761)
extern int tea5761_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr);
extern struct dvb_frontend *tea5761_attach(struct dvb_frontend *fe,
struct i2c_adapter* i2c_adap,
u8 i2c_addr);
#else
static inline int tea5761_autodetection(struct i2c_adapter* i2c_adap,
u8 i2c_addr)
{
printk(KERN_INFO "%s: not probed - driver disabled by Kconfig\n",
__func__);
return -EINVAL;
}
static inline struct dvb_frontend *tea5761_attach(struct dvb_frontend *fe,
struct i2c_adapter* i2c_adap,
u8 i2c_addr)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif /* __TEA5761_H__ */

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/*
* For Philips TEA5767 FM Chip used on some TV Cards like Prolink Pixelview
* I2C address is allways 0xC0.
*
*
* Copyright (c) 2005 Mauro Carvalho Chehab (mchehab@infradead.org)
* This code is placed under the terms of the GNU General Public License
*
* tea5767 autodetection thanks to Torsten Seeboth and Atsushi Nakagawa
* from their contributions on DScaler.
*/
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/videodev2.h>
#include "tuner-i2c.h"
#include "tea5767.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "enable verbose debug messages");
/*****************************************************************************/
struct tea5767_priv {
struct tuner_i2c_props i2c_props;
u32 frequency;
struct tea5767_ctrl ctrl;
};
/*****************************************************************************/
/******************************
* Write mode register values *
******************************/
/* First register */
#define TEA5767_MUTE 0x80 /* Mutes output */
#define TEA5767_SEARCH 0x40 /* Activates station search */
/* Bits 0-5 for divider MSB */
/* Second register */
/* Bits 0-7 for divider LSB */
/* Third register */
/* Station search from botton to up */
#define TEA5767_SEARCH_UP 0x80
/* Searches with ADC output = 10 */
#define TEA5767_SRCH_HIGH_LVL 0x60
/* Searches with ADC output = 10 */
#define TEA5767_SRCH_MID_LVL 0x40
/* Searches with ADC output = 5 */
#define TEA5767_SRCH_LOW_LVL 0x20
/* if on, div=4*(Frf+Fif)/Fref otherwise, div=4*(Frf-Fif)/Freq) */
#define TEA5767_HIGH_LO_INJECT 0x10
/* Disable stereo */
#define TEA5767_MONO 0x08
/* Disable right channel and turns to mono */
#define TEA5767_MUTE_RIGHT 0x04
/* Disable left channel and turns to mono */
#define TEA5767_MUTE_LEFT 0x02
#define TEA5767_PORT1_HIGH 0x01
/* Fourth register */
#define TEA5767_PORT2_HIGH 0x80
/* Chips stops working. Only I2C bus remains on */
#define TEA5767_STDBY 0x40
/* Japan freq (76-108 MHz. If disabled, 87.5-108 MHz */
#define TEA5767_JAPAN_BAND 0x20
/* Unselected means 32.768 KHz freq as reference. Otherwise Xtal at 13 MHz */
#define TEA5767_XTAL_32768 0x10
/* Cuts weak signals */
#define TEA5767_SOFT_MUTE 0x08
/* Activates high cut control */
#define TEA5767_HIGH_CUT_CTRL 0x04
/* Activates stereo noise control */
#define TEA5767_ST_NOISE_CTL 0x02
/* If activate PORT 1 indicates SEARCH or else it is used as PORT1 */
#define TEA5767_SRCH_IND 0x01
/* Fifth register */
/* By activating, it will use Xtal at 13 MHz as reference for divider */
#define TEA5767_PLLREF_ENABLE 0x80
/* By activating, deemphasis=50, or else, deemphasis of 50us */
#define TEA5767_DEEMPH_75 0X40
/*****************************
* Read mode register values *
*****************************/
/* First register */
#define TEA5767_READY_FLAG_MASK 0x80
#define TEA5767_BAND_LIMIT_MASK 0X40
/* Bits 0-5 for divider MSB after search or preset */
/* Second register */
/* Bits 0-7 for divider LSB after search or preset */
/* Third register */
#define TEA5767_STEREO_MASK 0x80
#define TEA5767_IF_CNTR_MASK 0x7f
/* Fourth register */
#define TEA5767_ADC_LEVEL_MASK 0xf0
/* should be 0 */
#define TEA5767_CHIP_ID_MASK 0x0f
/* Fifth register */
/* Reserved for future extensions */
#define TEA5767_RESERVED_MASK 0xff
/*****************************************************************************/
static void tea5767_status_dump(struct tea5767_priv *priv,
unsigned char *buffer)
{
unsigned int div, frq;
if (TEA5767_READY_FLAG_MASK & buffer[0])
tuner_info("Ready Flag ON\n");
else
tuner_info("Ready Flag OFF\n");
if (TEA5767_BAND_LIMIT_MASK & buffer[0])
tuner_info("Tuner at band limit\n");
else
tuner_info("Tuner not at band limit\n");
div = ((buffer[0] & 0x3f) << 8) | buffer[1];
switch (priv->ctrl.xtal_freq) {
case TEA5767_HIGH_LO_13MHz:
frq = (div * 50000 - 700000 - 225000) / 4; /* Freq in KHz */
break;
case TEA5767_LOW_LO_13MHz:
frq = (div * 50000 + 700000 + 225000) / 4; /* Freq in KHz */
break;
case TEA5767_LOW_LO_32768:
frq = (div * 32768 + 700000 + 225000) / 4; /* Freq in KHz */
break;
case TEA5767_HIGH_LO_32768:
default:
frq = (div * 32768 - 700000 - 225000) / 4; /* Freq in KHz */
break;
}
buffer[0] = (div >> 8) & 0x3f;
buffer[1] = div & 0xff;
tuner_info("Frequency %d.%03d KHz (divider = 0x%04x)\n",
frq / 1000, frq % 1000, div);
if (TEA5767_STEREO_MASK & buffer[2])
tuner_info("Stereo\n");
else
tuner_info("Mono\n");
tuner_info("IF Counter = %d\n", buffer[2] & TEA5767_IF_CNTR_MASK);
tuner_info("ADC Level = %d\n",
(buffer[3] & TEA5767_ADC_LEVEL_MASK) >> 4);
tuner_info("Chip ID = %d\n", (buffer[3] & TEA5767_CHIP_ID_MASK));
tuner_info("Reserved = 0x%02x\n",
(buffer[4] & TEA5767_RESERVED_MASK));
}
/* Freq should be specifyed at 62.5 Hz */
static int set_radio_freq(struct dvb_frontend *fe,
struct analog_parameters *params)
{
struct tea5767_priv *priv = fe->tuner_priv;
unsigned int frq = params->frequency;
unsigned char buffer[5];
unsigned div;
int rc;
tuner_dbg("radio freq = %d.%03d MHz\n", frq/16000,(frq/16)%1000);
buffer[2] = 0;
if (priv->ctrl.port1)
buffer[2] |= TEA5767_PORT1_HIGH;
if (params->audmode == V4L2_TUNER_MODE_MONO) {
tuner_dbg("TEA5767 set to mono\n");
buffer[2] |= TEA5767_MONO;
} else {
tuner_dbg("TEA5767 set to stereo\n");
}
buffer[3] = 0;
if (priv->ctrl.port2)
buffer[3] |= TEA5767_PORT2_HIGH;
if (priv->ctrl.high_cut)
buffer[3] |= TEA5767_HIGH_CUT_CTRL;
if (priv->ctrl.st_noise)
buffer[3] |= TEA5767_ST_NOISE_CTL;
if (priv->ctrl.soft_mute)
buffer[3] |= TEA5767_SOFT_MUTE;
if (priv->ctrl.japan_band)
buffer[3] |= TEA5767_JAPAN_BAND;
buffer[4] = 0;
if (priv->ctrl.deemph_75)
buffer[4] |= TEA5767_DEEMPH_75;
if (priv->ctrl.pllref)
buffer[4] |= TEA5767_PLLREF_ENABLE;
/* Rounds freq to next decimal value - for 62.5 KHz step */
/* frq = 20*(frq/16)+radio_frq[frq%16]; */
switch (priv->ctrl.xtal_freq) {
case TEA5767_HIGH_LO_13MHz:
tuner_dbg("radio HIGH LO inject xtal @ 13 MHz\n");
buffer[2] |= TEA5767_HIGH_LO_INJECT;
div = (frq * (4000 / 16) + 700000 + 225000 + 25000) / 50000;
break;
case TEA5767_LOW_LO_13MHz:
tuner_dbg("radio LOW LO inject xtal @ 13 MHz\n");
div = (frq * (4000 / 16) - 700000 - 225000 + 25000) / 50000;
break;
case TEA5767_LOW_LO_32768:
tuner_dbg("radio LOW LO inject xtal @ 32,768 MHz\n");
buffer[3] |= TEA5767_XTAL_32768;
/* const 700=4000*175 Khz - to adjust freq to right value */
div = ((frq * (4000 / 16) - 700000 - 225000) + 16384) >> 15;
break;
case TEA5767_HIGH_LO_32768:
default:
tuner_dbg("radio HIGH LO inject xtal @ 32,768 MHz\n");
buffer[2] |= TEA5767_HIGH_LO_INJECT;
buffer[3] |= TEA5767_XTAL_32768;
div = ((frq * (4000 / 16) + 700000 + 225000) + 16384) >> 15;
break;
}
buffer[0] = (div >> 8) & 0x3f;
buffer[1] = div & 0xff;
if (5 != (rc = tuner_i2c_xfer_send(&priv->i2c_props, buffer, 5)))
tuner_warn("i2c i/o error: rc == %d (should be 5)\n", rc);
if (debug) {
if (5 != (rc = tuner_i2c_xfer_recv(&priv->i2c_props, buffer, 5)))
tuner_warn("i2c i/o error: rc == %d (should be 5)\n", rc);
else
tea5767_status_dump(priv, buffer);
}
priv->frequency = frq * 125 / 2;
return 0;
}
static int tea5767_read_status(struct dvb_frontend *fe, char *buffer)
{
struct tea5767_priv *priv = fe->tuner_priv;
int rc;
memset(buffer, 0, 5);
if (5 != (rc = tuner_i2c_xfer_recv(&priv->i2c_props, buffer, 5))) {
tuner_warn("i2c i/o error: rc == %d (should be 5)\n", rc);
return -EREMOTEIO;
}
return 0;
}
static inline int tea5767_signal(struct dvb_frontend *fe, const char *buffer)
{
struct tea5767_priv *priv = fe->tuner_priv;
int signal = ((buffer[3] & TEA5767_ADC_LEVEL_MASK) << 8);
tuner_dbg("Signal strength: %d\n", signal);
return signal;
}
static inline int tea5767_stereo(struct dvb_frontend *fe, const char *buffer)
{
struct tea5767_priv *priv = fe->tuner_priv;
int stereo = buffer[2] & TEA5767_STEREO_MASK;
tuner_dbg("Radio ST GET = %02x\n", stereo);
return (stereo ? V4L2_TUNER_SUB_STEREO : 0);
}
static int tea5767_get_status(struct dvb_frontend *fe, u32 *status)
{
unsigned char buffer[5];
*status = 0;
if (0 == tea5767_read_status(fe, buffer)) {
if (tea5767_signal(fe, buffer))
*status = TUNER_STATUS_LOCKED;
if (tea5767_stereo(fe, buffer))
*status |= TUNER_STATUS_STEREO;
}
return 0;
}
static int tea5767_get_rf_strength(struct dvb_frontend *fe, u16 *strength)
{
unsigned char buffer[5];
*strength = 0;
if (0 == tea5767_read_status(fe, buffer))
*strength = tea5767_signal(fe, buffer);
return 0;
}
static int tea5767_standby(struct dvb_frontend *fe)
{
unsigned char buffer[5];
struct tea5767_priv *priv = fe->tuner_priv;
unsigned div, rc;
div = (87500 * 4 + 700 + 225 + 25) / 50; /* Set frequency to 87.5 MHz */
buffer[0] = (div >> 8) & 0x3f;
buffer[1] = div & 0xff;
buffer[2] = TEA5767_PORT1_HIGH;
buffer[3] = TEA5767_PORT2_HIGH | TEA5767_HIGH_CUT_CTRL |
TEA5767_ST_NOISE_CTL | TEA5767_JAPAN_BAND | TEA5767_STDBY;
buffer[4] = 0;
if (5 != (rc = tuner_i2c_xfer_send(&priv->i2c_props, buffer, 5)))
tuner_warn("i2c i/o error: rc == %d (should be 5)\n", rc);
return 0;
}
int tea5767_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr)
{
struct tuner_i2c_props i2c = { .adap = i2c_adap, .addr = i2c_addr };
unsigned char buffer[7] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
int rc;
if ((rc = tuner_i2c_xfer_recv(&i2c, buffer, 7))< 5) {
printk(KERN_WARNING "It is not a TEA5767. Received %i bytes.\n", rc);
return -EINVAL;
}
/* If all bytes are the same then it's a TV tuner and not a tea5767 */
if (buffer[0] == buffer[1] && buffer[0] == buffer[2] &&
buffer[0] == buffer[3] && buffer[0] == buffer[4]) {
printk(KERN_WARNING "All bytes are equal. It is not a TEA5767\n");
return -EINVAL;
}
/* Status bytes:
* Byte 4: bit 3:1 : CI (Chip Identification) == 0
* bit 0 : internally set to 0
* Byte 5: bit 7:0 : == 0
*/
if (((buffer[3] & 0x0f) != 0x00) || (buffer[4] != 0x00)) {
printk(KERN_WARNING "Chip ID is not zero. It is not a TEA5767\n");
return -EINVAL;
}
return 0;
}
static int tea5767_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
return 0;
}
static int tea5767_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct tea5767_priv *priv = fe->tuner_priv;
*frequency = priv->frequency;
return 0;
}
static int tea5767_set_config (struct dvb_frontend *fe, void *priv_cfg)
{
struct tea5767_priv *priv = fe->tuner_priv;
memcpy(&priv->ctrl, priv_cfg, sizeof(priv->ctrl));
return 0;
}
static struct dvb_tuner_ops tea5767_tuner_ops = {
.info = {
.name = "tea5767", // Philips TEA5767HN FM Radio
},
.set_analog_params = set_radio_freq,
.set_config = tea5767_set_config,
.sleep = tea5767_standby,
.release = tea5767_release,
.get_frequency = tea5767_get_frequency,
.get_status = tea5767_get_status,
.get_rf_strength = tea5767_get_rf_strength,
};
struct dvb_frontend *tea5767_attach(struct dvb_frontend *fe,
struct i2c_adapter* i2c_adap,
u8 i2c_addr)
{
struct tea5767_priv *priv = NULL;
priv = kzalloc(sizeof(struct tea5767_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
fe->tuner_priv = priv;
priv->i2c_props.addr = i2c_addr;
priv->i2c_props.adap = i2c_adap;
priv->i2c_props.name = "tea5767";
priv->ctrl.xtal_freq = TEA5767_HIGH_LO_32768;
priv->ctrl.port1 = 1;
priv->ctrl.port2 = 1;
priv->ctrl.high_cut = 1;
priv->ctrl.st_noise = 1;
priv->ctrl.japan_band = 1;
memcpy(&fe->ops.tuner_ops, &tea5767_tuner_ops,
sizeof(struct dvb_tuner_ops));
tuner_info("type set to %s\n", "Philips TEA5767HN FM Radio");
return fe;
}
EXPORT_SYMBOL_GPL(tea5767_attach);
EXPORT_SYMBOL_GPL(tea5767_autodetection);
MODULE_DESCRIPTION("Philips TEA5767 FM tuner driver");
MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@infradead.org>");
MODULE_LICENSE("GPL");

66
drivers/media/tuners/tea5767.h Normal file
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/*
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __TEA5767_H__
#define __TEA5767_H__
#include <linux/i2c.h>
#include "dvb_frontend.h"
enum tea5767_xtal {
TEA5767_LOW_LO_32768 = 0,
TEA5767_HIGH_LO_32768 = 1,
TEA5767_LOW_LO_13MHz = 2,
TEA5767_HIGH_LO_13MHz = 3,
};
struct tea5767_ctrl {
unsigned int port1:1;
unsigned int port2:1;
unsigned int high_cut:1;
unsigned int st_noise:1;
unsigned int soft_mute:1;
unsigned int japan_band:1;
unsigned int deemph_75:1;
unsigned int pllref:1;
enum tea5767_xtal xtal_freq;
};
#if IS_ENABLED(CONFIG_MEDIA_TUNER_TEA5767)
extern int tea5767_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr);
extern struct dvb_frontend *tea5767_attach(struct dvb_frontend *fe,
struct i2c_adapter* i2c_adap,
u8 i2c_addr);
#else
static inline int tea5767_autodetection(struct i2c_adapter* i2c_adap,
u8 i2c_addr)
{
printk(KERN_INFO "%s: not probed - driver disabled by Kconfig\n",
__func__);
return -EINVAL;
}
static inline struct dvb_frontend *tea5767_attach(struct dvb_frontend *fe,
struct i2c_adapter* i2c_adap,
u8 i2c_addr)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif /* __TEA5767_H__ */

294
drivers/media/tuners/tua9001.c Normal file
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/*
* Infineon TUA 9001 silicon tuner driver
*
* Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include "tua9001.h"
#include "tua9001_priv.h"
/* write register */
static int tua9001_wr_reg(struct tua9001_priv *priv, u8 reg, u16 val)
{
int ret;
u8 buf[3] = { reg, (val >> 8) & 0xff, (val >> 0) & 0xff };
struct i2c_msg msg[1] = {
{
.addr = priv->cfg->i2c_addr,
.flags = 0,
.len = sizeof(buf),
.buf = buf,
}
};
ret = i2c_transfer(priv->i2c, msg, 1);
if (ret == 1) {
ret = 0;
} else {
dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d reg=%02x\n",
KBUILD_MODNAME, ret, reg);
ret = -EREMOTEIO;
}
return ret;
}
static int tua9001_release(struct dvb_frontend *fe)
{
struct tua9001_priv *priv = fe->tuner_priv;
int ret = 0;
dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
if (fe->callback)
ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
TUA9001_CMD_CEN, 0);
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
return ret;
}
static int tua9001_init(struct dvb_frontend *fe)
{
struct tua9001_priv *priv = fe->tuner_priv;
int ret = 0;
u8 i;
struct reg_val data[] = {
{ 0x1e, 0x6512 },
{ 0x25, 0xb888 },
{ 0x39, 0x5460 },
{ 0x3b, 0x00c0 },
{ 0x3a, 0xf000 },
{ 0x08, 0x0000 },
{ 0x32, 0x0030 },
{ 0x41, 0x703a },
{ 0x40, 0x1c78 },
{ 0x2c, 0x1c00 },
{ 0x36, 0xc013 },
{ 0x37, 0x6f18 },
{ 0x27, 0x0008 },
{ 0x2a, 0x0001 },
{ 0x34, 0x0a40 },
};
dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
if (fe->callback) {
ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
TUA9001_CMD_RESETN, 0);
if (ret < 0)
goto err;
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c-gate */
for (i = 0; i < ARRAY_SIZE(data); i++) {
ret = tua9001_wr_reg(priv, data[i].reg, data[i].val);
if (ret < 0)
goto err_i2c_gate_ctrl;
}
err_i2c_gate_ctrl:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c-gate */
err:
if (ret < 0)
dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
return ret;
}
static int tua9001_sleep(struct dvb_frontend *fe)
{
struct tua9001_priv *priv = fe->tuner_priv;
int ret = 0;
dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
if (fe->callback)
ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
TUA9001_CMD_RESETN, 1);
if (ret < 0)
dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
return ret;
}
static int tua9001_set_params(struct dvb_frontend *fe)
{
struct tua9001_priv *priv = fe->tuner_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret = 0, i;
u16 val;
u32 frequency;
struct reg_val data[2];
dev_dbg(&priv->i2c->dev, "%s: delivery_system=%d frequency=%d " \
"bandwidth_hz=%d\n", __func__,
c->delivery_system, c->frequency, c->bandwidth_hz);
switch (c->delivery_system) {
case SYS_DVBT:
switch (c->bandwidth_hz) {
case 8000000:
val = 0x0000;
break;
case 7000000:
val = 0x1000;
break;
case 6000000:
val = 0x2000;
break;
case 5000000:
val = 0x3000;
break;
default:
ret = -EINVAL;
goto err;
}
break;
default:
ret = -EINVAL;
goto err;
}
data[0].reg = 0x04;
data[0].val = val;
frequency = (c->frequency - 150000000);
frequency /= 100;
frequency *= 48;
frequency /= 10000;
data[1].reg = 0x1f;
data[1].val = frequency;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c-gate */
if (fe->callback) {
ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
TUA9001_CMD_RXEN, 0);
if (ret < 0)
goto err_i2c_gate_ctrl;
}
for (i = 0; i < ARRAY_SIZE(data); i++) {
ret = tua9001_wr_reg(priv, data[i].reg, data[i].val);
if (ret < 0)
goto err_i2c_gate_ctrl;
}
if (fe->callback) {
ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
TUA9001_CMD_RXEN, 1);
if (ret < 0)
goto err_i2c_gate_ctrl;
}
err_i2c_gate_ctrl:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c-gate */
err:
if (ret < 0)
dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
return ret;
}
static int tua9001_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct tua9001_priv *priv = fe->tuner_priv;
dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
*frequency = 0; /* Zero-IF */
return 0;
}
static const struct dvb_tuner_ops tua9001_tuner_ops = {
.info = {
.name = "Infineon TUA 9001",
.frequency_min = 170000000,
.frequency_max = 862000000,
.frequency_step = 0,
},
.release = tua9001_release,
.init = tua9001_init,
.sleep = tua9001_sleep,
.set_params = tua9001_set_params,
.get_if_frequency = tua9001_get_if_frequency,
};
struct dvb_frontend *tua9001_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, struct tua9001_config *cfg)
{
struct tua9001_priv *priv = NULL;
int ret;
priv = kzalloc(sizeof(struct tua9001_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->cfg = cfg;
priv->i2c = i2c;
if (fe->callback) {
ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
TUA9001_CMD_CEN, 1);
if (ret < 0)
goto err;
ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
TUA9001_CMD_RXEN, 0);
if (ret < 0)
goto err;
ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
TUA9001_CMD_RESETN, 1);
if (ret < 0)
goto err;
}
dev_info(&priv->i2c->dev,
"%s: Infineon TUA 9001 successfully attached\n",
KBUILD_MODNAME);
memcpy(&fe->ops.tuner_ops, &tua9001_tuner_ops,
sizeof(struct dvb_tuner_ops));
fe->tuner_priv = priv;
return fe;
err:
dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
kfree(priv);
return NULL;
}
EXPORT_SYMBOL(tua9001_attach);
MODULE_DESCRIPTION("Infineon TUA 9001 silicon tuner driver");
MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
MODULE_LICENSE("GPL");

66
drivers/media/tuners/tua9001.h Normal file
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/*
* Infineon TUA 9001 silicon tuner driver
*
* Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef TUA9001_H
#define TUA9001_H
#include <linux/kconfig.h>
#include "dvb_frontend.h"
struct tua9001_config {
/*
* I2C address
*/
u8 i2c_addr;
};
/*
* TUA9001 I/O PINs:
*
* CEN - chip enable
* 0 = chip disabled (chip off)
* 1 = chip enabled (chip on)
*
* RESETN - chip reset
* 0 = reset disabled (chip reset off)
* 1 = reset enabled (chip reset on)
*
* RXEN - RX enable
* 0 = RX disabled (chip idle)
* 1 = RX enabled (chip tuned)
*/
#define TUA9001_CMD_CEN 0
#define TUA9001_CMD_RESETN 1
#define TUA9001_CMD_RXEN 2
#if IS_ENABLED(CONFIG_MEDIA_TUNER_TUA9001)
extern struct dvb_frontend *tua9001_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, struct tua9001_config *cfg);
#else
static inline struct dvb_frontend *tua9001_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, struct tua9001_config *cfg)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif

34
drivers/media/tuners/tua9001_priv.h Normal file
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@ -0,0 +1,34 @@
/*
* Infineon TUA 9001 silicon tuner driver
*
* Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef TUA9001_PRIV_H
#define TUA9001_PRIV_H
struct reg_val {
u8 reg;
u16 val;
};
struct tua9001_priv {
struct tua9001_config *cfg;
struct i2c_adapter *i2c;
};
#endif

182
drivers/media/tuners/tuner-i2c.h Normal file
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/*
tuner-i2c.h - i2c interface for different tuners
Copyright (C) 2007 Michael Krufky (mkrufky@linuxtv.org)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __TUNER_I2C_H__
#define __TUNER_I2C_H__
#include <linux/i2c.h>
#include <linux/slab.h>
struct tuner_i2c_props {
u8 addr;
struct i2c_adapter *adap;
/* used for tuner instance management */
int count;
char *name;
};
static inline int tuner_i2c_xfer_send(struct tuner_i2c_props *props, char *buf, int len)
{
struct i2c_msg msg = { .addr = props->addr, .flags = 0,
.buf = buf, .len = len };
int ret = i2c_transfer(props->adap, &msg, 1);
return (ret == 1) ? len : ret;
}
static inline int tuner_i2c_xfer_recv(struct tuner_i2c_props *props, char *buf, int len)
{
struct i2c_msg msg = { .addr = props->addr, .flags = I2C_M_RD,
.buf = buf, .len = len };
int ret = i2c_transfer(props->adap, &msg, 1);
return (ret == 1) ? len : ret;
}
static inline int tuner_i2c_xfer_send_recv(struct tuner_i2c_props *props,
char *obuf, int olen,
char *ibuf, int ilen)
{
struct i2c_msg msg[2] = { { .addr = props->addr, .flags = 0,
.buf = obuf, .len = olen },
{ .addr = props->addr, .flags = I2C_M_RD,
.buf = ibuf, .len = ilen } };
int ret = i2c_transfer(props->adap, msg, 2);
return (ret == 2) ? ilen : ret;
}
/* Callers must declare as a global for the module:
*
* static LIST_HEAD(hybrid_tuner_instance_list);
*
* hybrid_tuner_instance_list should be the third argument
* passed into hybrid_tuner_request_state().
*
* state structure must contain the following:
*
* struct list_head hybrid_tuner_instance_list;
* struct tuner_i2c_props i2c_props;
*
* hybrid_tuner_instance_list (both within state structure and globally)
* is only required if the driver is using hybrid_tuner_request_state
* and hybrid_tuner_release_state to manage state sharing between
* multiple instances of hybrid tuners.
*/
#define tuner_printk(kernlvl, i2cprops, fmt, arg...) do { \
printk(kernlvl "%s %d-%04x: " fmt, i2cprops.name, \
i2cprops.adap ? \
i2c_adapter_id(i2cprops.adap) : -1, \
i2cprops.addr, ##arg); \
} while (0)
/* TO DO: convert all callers of these macros to pass in
* struct tuner_i2c_props, then remove the macro wrappers */
#define __tuner_warn(i2cprops, fmt, arg...) do { \
tuner_printk(KERN_WARNING, i2cprops, fmt, ##arg); \
} while (0)
#define __tuner_info(i2cprops, fmt, arg...) do { \
tuner_printk(KERN_INFO, i2cprops, fmt, ##arg); \
} while (0)
#define __tuner_err(i2cprops, fmt, arg...) do { \
tuner_printk(KERN_ERR, i2cprops, fmt, ##arg); \
} while (0)
#define __tuner_dbg(i2cprops, fmt, arg...) do { \
if ((debug)) \
tuner_printk(KERN_DEBUG, i2cprops, fmt, ##arg); \
} while (0)
#define tuner_warn(fmt, arg...) __tuner_warn(priv->i2c_props, fmt, ##arg)
#define tuner_info(fmt, arg...) __tuner_info(priv->i2c_props, fmt, ##arg)
#define tuner_err(fmt, arg...) __tuner_err(priv->i2c_props, fmt, ##arg)
#define tuner_dbg(fmt, arg...) __tuner_dbg(priv->i2c_props, fmt, ##arg)
/****************************************************************************/
/* The return value of hybrid_tuner_request_state indicates the number of
* instances using this tuner object.
*
* 0 - no instances, indicates an error - kzalloc must have failed
*
* 1 - one instance, indicates that the tuner object was created successfully
*
* 2 (or more) instances, indicates that an existing tuner object was found
*/
#define hybrid_tuner_request_state(type, state, list, i2cadap, i2caddr, devname)\
({ \
int __ret = 0; \
list_for_each_entry(state, &list, hybrid_tuner_instance_list) { \
if (((i2cadap) && (state->i2c_props.adap)) && \
((i2c_adapter_id(state->i2c_props.adap) == \
i2c_adapter_id(i2cadap)) && \
(i2caddr == state->i2c_props.addr))) { \
__tuner_info(state->i2c_props, \
"attaching existing instance\n"); \
state->i2c_props.count++; \
__ret = state->i2c_props.count; \
break; \
} \
} \
if (0 == __ret) { \
state = kzalloc(sizeof(type), GFP_KERNEL); \
if (NULL == state) \
goto __fail; \
state->i2c_props.addr = i2caddr; \
state->i2c_props.adap = i2cadap; \
state->i2c_props.name = devname; \
__tuner_info(state->i2c_props, \
"creating new instance\n"); \
list_add_tail(&state->hybrid_tuner_instance_list, &list);\
state->i2c_props.count++; \
__ret = state->i2c_props.count; \
} \
__fail: \
__ret; \
})
#define hybrid_tuner_release_state(state) \
({ \
int __ret; \
state->i2c_props.count--; \
__ret = state->i2c_props.count; \
if (!state->i2c_props.count) { \
__tuner_info(state->i2c_props, "destroying instance\n");\
list_del(&state->hybrid_tuner_instance_list); \
kfree(state); \
} \
__ret; \
})
#define hybrid_tuner_report_instance_count(state) \
({ \
int __ret = 0; \
if (state) \
__ret = state->i2c_props.count; \
__ret; \
})
#endif /* __TUNER_I2C_H__ */

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/*
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __TUNER_SIMPLE_H__
#define __TUNER_SIMPLE_H__
#include <linux/i2c.h>
#include "dvb_frontend.h"
#if IS_ENABLED(CONFIG_MEDIA_TUNER_SIMPLE)
extern struct dvb_frontend *simple_tuner_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c_adap,
u8 i2c_addr,
unsigned int type);
#else
static inline struct dvb_frontend *simple_tuner_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c_adap,
u8 i2c_addr,
unsigned int type)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif /* __TUNER_SIMPLE_H__ */

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drivers/media/tuners/tuner-types.c Normal file
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drivers/media/tuners/tuner-xc2028-types.h Normal file
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/* tuner-xc2028_types
*
* This file includes internal tipes to be used inside tuner-xc2028.
* Shouldn't be included outside tuner-xc2028
*
* Copyright (c) 2007-2008 Mauro Carvalho Chehab (mchehab@infradead.org)
* This code is placed under the terms of the GNU General Public License v2
*/
/* xc3028 firmware types */
/* BASE firmware should be loaded before any other firmware */
#define BASE (1<<0)
#define BASE_TYPES (BASE|F8MHZ|MTS|FM|INPUT1|INPUT2|INIT1)
/* F8MHZ marks BASE firmwares for 8 MHz Bandwidth */
#define F8MHZ (1<<1)
/* Multichannel Television Sound (MTS)
Those firmwares are capable of using xc2038 DSP to decode audio and
produce a baseband audio output on some pins of the chip.
There are MTS firmwares for the most used video standards. It should be
required to use MTS firmwares, depending on the way audio is routed into
the bridge chip
*/
#define MTS (1<<2)
/* FIXME: I have no idea what's the difference between
D2620 and D2633 firmwares
*/
#define D2620 (1<<3)
#define D2633 (1<<4)
/* DTV firmwares for 6, 7 and 8 MHz
DTV6 - 6MHz - ATSC/DVB-C/DVB-T/ISDB-T/DOCSIS
DTV8 - 8MHz - DVB-C/DVB-T
*/
#define DTV6 (1 << 5)
#define QAM (1 << 6)
#define DTV7 (1<<7)
#define DTV78 (1<<8)
#define DTV8 (1<<9)
#define DTV_TYPES (D2620|D2633|DTV6|QAM|DTV7|DTV78|DTV8|ATSC)
/* There's a FM | BASE firmware + FM specific firmware (std=0) */
#define FM (1<<10)
#define STD_SPECIFIC_TYPES (MTS|FM|LCD|NOGD)
/* Applies only for FM firmware
Makes it use RF input 1 (pin #2) instead of input 2 (pin #4)
*/
#define INPUT1 (1<<11)
/* LCD firmwares exist only for MTS STD/MN (PAL or NTSC/M)
and for non-MTS STD/MN (PAL, NTSC/M or NTSC/Kr)
There are variants both with and without NOGD
Those firmwares produce better result with LCD displays
*/
#define LCD (1<<12)
/* NOGD firmwares exist only for MTS STD/MN (PAL or NTSC/M)
and for non-MTS STD/MN (PAL, NTSC/M or NTSC/Kr)
The NOGD firmwares don't have group delay compensation filter
*/
#define NOGD (1<<13)
/* Old firmwares were broken into init0 and init1 */
#define INIT1 (1<<14)
/* SCODE firmware selects particular behaviours */
#define MONO (1 << 15)
#define ATSC (1 << 16)
#define IF (1 << 17)
#define LG60 (1 << 18)
#define ATI638 (1 << 19)
#define OREN538 (1 << 20)
#define OREN36 (1 << 21)
#define TOYOTA388 (1 << 22)
#define TOYOTA794 (1 << 23)
#define DIBCOM52 (1 << 24)
#define ZARLINK456 (1 << 25)
#define CHINA (1 << 26)
#define F6MHZ (1 << 27)
#define INPUT2 (1 << 28)
#define SCODE (1 << 29)
/* This flag identifies that the scode table has a new format */
#define HAS_IF (1 << 30)
/* There are different scode tables for MTS and non-MTS.
The MTS firmwares support mono only
*/
#define SCODE_TYPES (SCODE | MTS)
/* Newer types not defined on videodev2.h.
The original idea were to move all those types to videodev2.h, but
it seemed overkill, since, with the exception of SECAM/K3, the other
types seem to be autodetected.
It is not clear where secam/k3 is used, nor we have a feedback of this
working or being autodetected by the standard secam firmware.
*/
#define V4L2_STD_SECAM_K3 (0x04000000)
/* Audio types */
#define V4L2_STD_A2_A (1LL<<32)
#define V4L2_STD_A2_B (1LL<<33)
#define V4L2_STD_NICAM_A (1LL<<34)
#define V4L2_STD_NICAM_B (1LL<<35)
#define V4L2_STD_AM (1LL<<36)
#define V4L2_STD_BTSC (1LL<<37)
#define V4L2_STD_EIAJ (1LL<<38)
#define V4L2_STD_A2 (V4L2_STD_A2_A | V4L2_STD_A2_B)
#define V4L2_STD_NICAM (V4L2_STD_NICAM_A | V4L2_STD_NICAM_B)
/* To preserve backward compatibility,
(std & V4L2_STD_AUDIO) = 0 means that ALL audio stds are supported
*/
#define V4L2_STD_AUDIO (V4L2_STD_A2 | \
V4L2_STD_NICAM | \
V4L2_STD_AM | \
V4L2_STD_BTSC | \
V4L2_STD_EIAJ)
/* Used standards with audio restrictions */
#define V4L2_STD_PAL_BG_A2_A (V4L2_STD_PAL_BG | V4L2_STD_A2_A)
#define V4L2_STD_PAL_BG_A2_B (V4L2_STD_PAL_BG | V4L2_STD_A2_B)
#define V4L2_STD_PAL_BG_NICAM_A (V4L2_STD_PAL_BG | V4L2_STD_NICAM_A)
#define V4L2_STD_PAL_BG_NICAM_B (V4L2_STD_PAL_BG | V4L2_STD_NICAM_B)
#define V4L2_STD_PAL_DK_A2 (V4L2_STD_PAL_DK | V4L2_STD_A2)
#define V4L2_STD_PAL_DK_NICAM (V4L2_STD_PAL_DK | V4L2_STD_NICAM)
#define V4L2_STD_SECAM_L_NICAM (V4L2_STD_SECAM_L | V4L2_STD_NICAM)
#define V4L2_STD_SECAM_L_AM (V4L2_STD_SECAM_L | V4L2_STD_AM)

1531
drivers/media/tuners/tuner-xc2028.c Normal file
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drivers/media/tuners/tuner-xc2028.h Normal file
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/* tuner-xc2028
*
* Copyright (c) 2007-2008 Mauro Carvalho Chehab (mchehab@infradead.org)
* This code is placed under the terms of the GNU General Public License v2
*/
#ifndef __TUNER_XC2028_H__
#define __TUNER_XC2028_H__
#include "dvb_frontend.h"
#define XC2028_DEFAULT_FIRMWARE "xc3028-v27.fw"
#define XC3028L_DEFAULT_FIRMWARE "xc3028L-v36.fw"
/* Dmoduler IF (kHz) */
#define XC3028_FE_DEFAULT 0 /* Don't load SCODE */
#define XC3028_FE_LG60 6000
#define XC3028_FE_ATI638 6380
#define XC3028_FE_OREN538 5380
#define XC3028_FE_OREN36 3600
#define XC3028_FE_TOYOTA388 3880
#define XC3028_FE_TOYOTA794 7940
#define XC3028_FE_DIBCOM52 5200
#define XC3028_FE_ZARLINK456 4560
#define XC3028_FE_CHINA 5200
enum firmware_type {
XC2028_AUTO = 0, /* By default, auto-detects */
XC2028_D2633,
XC2028_D2620,
};
struct xc2028_ctrl {
char *fname;
int max_len;
int msleep;
unsigned int scode_table;
unsigned int mts :1;
unsigned int input1:1;
unsigned int vhfbw7:1;
unsigned int uhfbw8:1;
unsigned int disable_power_mgmt:1;
unsigned int read_not_reliable:1;
unsigned int demod;
enum firmware_type type:2;
};
struct xc2028_config {
struct i2c_adapter *i2c_adap;
u8 i2c_addr;
struct xc2028_ctrl *ctrl;
};
/* xc2028 commands for callback */
#define XC2028_TUNER_RESET 0
#define XC2028_RESET_CLK 1
#define XC2028_I2C_FLUSH 2
#if IS_ENABLED(CONFIG_MEDIA_TUNER_XC2028)
extern struct dvb_frontend *xc2028_attach(struct dvb_frontend *fe,
struct xc2028_config *cfg);
#else
static inline struct dvb_frontend *xc2028_attach(struct dvb_frontend *fe,
struct xc2028_config *cfg)
{
printk(KERN_INFO "%s: not probed - driver disabled by Kconfig\n",
__func__);
return NULL;
}
#endif
#endif /* __TUNER_XC2028_H__ */

1775
drivers/media/tuners/xc4000.c Normal file
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/*
* Driver for Xceive XC4000 "QAM/8VSB single chip tuner"
*
* Copyright (c) 2007 Steven Toth <stoth@linuxtv.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __XC4000_H__
#define __XC4000_H__
#include <linux/firmware.h>
struct dvb_frontend;
struct i2c_adapter;
struct xc4000_config {
u8 i2c_address;
/* if non-zero, power management is enabled by default */
u8 default_pm;
/* value to be written to XREG_AMPLITUDE in DVB-T mode (0: no write) */
u8 dvb_amplitude;
/* if non-zero, register 0x0E is set to filter analog TV video output */
u8 set_smoothedcvbs;
/* IF for DVB-T */
u32 if_khz;
};
/* xc4000 callback command */
#define XC4000_TUNER_RESET 0
/* For each bridge framework, when it attaches either analog or digital,
* it has to store a reference back to its _core equivalent structure,
* so that it can service the hardware by steering gpio's etc.
* Each bridge implementation is different so cast devptr accordingly.
* The xc4000 driver cares not for this value, other than ensuring
* it's passed back to a bridge during tuner_callback().
*/
#if IS_ENABLED(CONFIG_MEDIA_TUNER_XC4000)
extern struct dvb_frontend *xc4000_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
struct xc4000_config *cfg);
#else
static inline struct dvb_frontend *xc4000_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
struct xc4000_config *cfg)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif

1487
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drivers/media/tuners/xc5000.h Normal file
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/*
* Driver for Xceive XC5000 "QAM/8VSB single chip tuner"
*
* Copyright (c) 2007 Steven Toth <stoth@linuxtv.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __XC5000_H__
#define __XC5000_H__
#include <linux/kconfig.h>
#include <linux/firmware.h>
struct dvb_frontend;
struct i2c_adapter;
#define XC5000A 1
#define XC5000C 2
struct xc5000_config {
u8 i2c_address;
u32 if_khz;
u8 radio_input;
u16 xtal_khz;
int chip_id;
};
/* xc5000 callback command */
#define XC5000_TUNER_RESET 0
/* Possible Radio inputs */
#define XC5000_RADIO_NOT_CONFIGURED 0
#define XC5000_RADIO_FM1 1
#define XC5000_RADIO_FM2 2
#define XC5000_RADIO_FM1_MONO 3
/* For each bridge framework, when it attaches either analog or digital,
* it has to store a reference back to its _core equivalent structure,
* so that it can service the hardware by steering gpio's etc.
* Each bridge implementation is different so cast devptr accordingly.
* The xc5000 driver cares not for this value, other than ensuring
* it's passed back to a bridge during tuner_callback().
*/
#if IS_ENABLED(CONFIG_MEDIA_TUNER_XC5000)
extern struct dvb_frontend *xc5000_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
const struct xc5000_config *cfg);
#else
static inline struct dvb_frontend *xc5000_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
const struct xc5000_config *cfg)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif