mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
378
drivers/memory/tegra30-mc.c
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378
drivers/memory/tegra30-mc.c
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/*
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* Tegra30 Memory Controller
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*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/ratelimit.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#define DRV_NAME "tegra30-mc"
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#define MC_INTSTATUS 0x0
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#define MC_INTMASK 0x4
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#define MC_INT_ERR_SHIFT 6
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#define MC_INT_ERR_MASK (0x1f << MC_INT_ERR_SHIFT)
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#define MC_INT_DECERR_EMEM BIT(MC_INT_ERR_SHIFT)
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#define MC_INT_SECURITY_VIOLATION BIT(MC_INT_ERR_SHIFT + 2)
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#define MC_INT_ARBITRATION_EMEM BIT(MC_INT_ERR_SHIFT + 3)
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#define MC_INT_INVALID_SMMU_PAGE BIT(MC_INT_ERR_SHIFT + 4)
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#define MC_ERR_STATUS 0x8
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#define MC_ERR_ADR 0xc
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#define MC_ERR_TYPE_SHIFT 28
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#define MC_ERR_TYPE_MASK (7 << MC_ERR_TYPE_SHIFT)
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#define MC_ERR_TYPE_DECERR_EMEM 2
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#define MC_ERR_TYPE_SECURITY_TRUSTZONE 3
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#define MC_ERR_TYPE_SECURITY_CARVEOUT 4
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#define MC_ERR_TYPE_INVALID_SMMU_PAGE 6
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#define MC_ERR_INVALID_SMMU_PAGE_SHIFT 25
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#define MC_ERR_INVALID_SMMU_PAGE_MASK (7 << MC_ERR_INVALID_SMMU_PAGE_SHIFT)
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#define MC_ERR_RW_SHIFT 16
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#define MC_ERR_RW BIT(MC_ERR_RW_SHIFT)
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#define MC_ERR_SECURITY BIT(MC_ERR_RW_SHIFT + 1)
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#define SECURITY_VIOLATION_TYPE BIT(30) /* 0=TRUSTZONE, 1=CARVEOUT */
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#define MC_EMEM_ARB_CFG 0x90
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#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
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#define MC_EMEM_ARB_TIMING_RCD 0x98
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#define MC_EMEM_ARB_TIMING_RP 0x9c
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#define MC_EMEM_ARB_TIMING_RC 0xa0
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#define MC_EMEM_ARB_TIMING_RAS 0xa4
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#define MC_EMEM_ARB_TIMING_FAW 0xa8
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#define MC_EMEM_ARB_TIMING_RRD 0xac
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#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
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#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
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#define MC_EMEM_ARB_TIMING_R2R 0xb8
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#define MC_EMEM_ARB_TIMING_W2W 0xbc
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#define MC_EMEM_ARB_TIMING_R2W 0xc0
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#define MC_EMEM_ARB_TIMING_W2R 0xc4
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#define MC_EMEM_ARB_DA_TURNS 0xd0
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#define MC_EMEM_ARB_DA_COVERS 0xd4
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#define MC_EMEM_ARB_MISC0 0xd8
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#define MC_EMEM_ARB_MISC1 0xdc
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#define MC_EMEM_ARB_RING3_THROTTLE 0xe4
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#define MC_EMEM_ARB_OVERRIDE 0xe8
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#define MC_TIMING_CONTROL 0xfc
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#define MC_CLIENT_ID_MASK 0x7f
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#define NUM_MC_REG_BANKS 4
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struct tegra30_mc {
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void __iomem *regs[NUM_MC_REG_BANKS];
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struct device *dev;
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u32 ctx[0];
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};
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static inline u32 mc_readl(struct tegra30_mc *mc, u32 offs)
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{
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u32 val = 0;
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if (offs < 0x10)
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val = readl(mc->regs[0] + offs);
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else if (offs < 0x1f0)
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val = readl(mc->regs[1] + offs - 0x3c);
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else if (offs < 0x228)
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val = readl(mc->regs[2] + offs - 0x200);
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else if (offs < 0x400)
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val = readl(mc->regs[3] + offs - 0x284);
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return val;
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}
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static inline void mc_writel(struct tegra30_mc *mc, u32 val, u32 offs)
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{
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if (offs < 0x10)
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writel(val, mc->regs[0] + offs);
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else if (offs < 0x1f0)
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writel(val, mc->regs[1] + offs - 0x3c);
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else if (offs < 0x228)
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writel(val, mc->regs[2] + offs - 0x200);
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else if (offs < 0x400)
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writel(val, mc->regs[3] + offs - 0x284);
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}
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static const char * const tegra30_mc_client[] = {
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"csr_ptcr",
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"cbr_display0a",
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"cbr_display0ab",
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"cbr_display0b",
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"cbr_display0bb",
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"cbr_display0c",
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"cbr_display0cb",
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"cbr_display1b",
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"cbr_display1bb",
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"cbr_eppup",
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"cbr_g2pr",
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"cbr_g2sr",
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"cbr_mpeunifbr",
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"cbr_viruv",
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"csr_afir",
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"csr_avpcarm7r",
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"csr_displayhc",
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"csr_displayhcb",
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"csr_fdcdrd",
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"csr_fdcdrd2",
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"csr_g2dr",
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"csr_hdar",
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"csr_host1xdmar",
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"csr_host1xr",
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"csr_idxsrd",
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"csr_idxsrd2",
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"csr_mpe_ipred",
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"csr_mpeamemrd",
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"csr_mpecsrd",
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"csr_ppcsahbdmar",
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"csr_ppcsahbslvr",
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"csr_satar",
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"csr_texsrd",
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"csr_texsrd2",
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"csr_vdebsevr",
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"csr_vdember",
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"csr_vdemcer",
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"csr_vdetper",
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"csr_mpcorelpr",
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"csr_mpcorer",
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"cbw_eppu",
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"cbw_eppv",
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"cbw_eppy",
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"cbw_mpeunifbw",
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"cbw_viwsb",
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"cbw_viwu",
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"cbw_viwv",
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"cbw_viwy",
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"ccw_g2dw",
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"csw_afiw",
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"csw_avpcarm7w",
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"csw_fdcdwr",
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"csw_fdcdwr2",
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"csw_hdaw",
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"csw_host1xw",
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"csw_ispw",
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"csw_mpcorelpw",
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"csw_mpcorew",
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"csw_mpecswr",
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"csw_ppcsahbdmaw",
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"csw_ppcsahbslvw",
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"csw_sataw",
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"csw_vdebsevw",
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"csw_vdedbgw",
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"csw_vdembew",
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"csw_vdetpmw",
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};
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static void tegra30_mc_decode(struct tegra30_mc *mc, int n)
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{
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u32 err, addr;
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const char * const mc_int_err[] = {
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"MC_DECERR",
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"Unknown",
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"MC_SECURITY_ERR",
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"MC_ARBITRATION_EMEM",
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"MC_SMMU_ERR",
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};
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const char * const err_type[] = {
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"Unknown",
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"Unknown",
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"DECERR_EMEM",
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"SECURITY_TRUSTZONE",
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"SECURITY_CARVEOUT",
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"Unknown",
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"INVALID_SMMU_PAGE",
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"Unknown",
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};
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char attr[6];
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int cid, perm, type, idx;
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const char *client = "Unknown";
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idx = n - MC_INT_ERR_SHIFT;
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if ((idx < 0) || (idx >= ARRAY_SIZE(mc_int_err)) || (idx == 1)) {
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dev_err_ratelimited(mc->dev, "Unknown interrupt status %08lx\n",
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BIT(n));
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return;
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}
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err = mc_readl(mc, MC_ERR_STATUS);
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type = (err & MC_ERR_TYPE_MASK) >> MC_ERR_TYPE_SHIFT;
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perm = (err & MC_ERR_INVALID_SMMU_PAGE_MASK) >>
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MC_ERR_INVALID_SMMU_PAGE_SHIFT;
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if (type == MC_ERR_TYPE_INVALID_SMMU_PAGE)
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sprintf(attr, "%c-%c-%c",
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(perm & BIT(2)) ? 'R' : '-',
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(perm & BIT(1)) ? 'W' : '-',
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(perm & BIT(0)) ? 'S' : '-');
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else
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attr[0] = '\0';
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cid = err & MC_CLIENT_ID_MASK;
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if (cid < ARRAY_SIZE(tegra30_mc_client))
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client = tegra30_mc_client[cid];
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addr = mc_readl(mc, MC_ERR_ADR);
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dev_err_ratelimited(mc->dev, "%s (0x%08x): 0x%08x %s (%s %s %s %s)\n",
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mc_int_err[idx], err, addr, client,
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(err & MC_ERR_SECURITY) ? "secure" : "non-secure",
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(err & MC_ERR_RW) ? "write" : "read",
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err_type[type], attr);
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}
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static const u32 tegra30_mc_ctx[] = {
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MC_EMEM_ARB_CFG,
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MC_EMEM_ARB_OUTSTANDING_REQ,
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MC_EMEM_ARB_TIMING_RCD,
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MC_EMEM_ARB_TIMING_RP,
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MC_EMEM_ARB_TIMING_RC,
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MC_EMEM_ARB_TIMING_RAS,
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MC_EMEM_ARB_TIMING_FAW,
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MC_EMEM_ARB_TIMING_RRD,
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MC_EMEM_ARB_TIMING_RAP2PRE,
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MC_EMEM_ARB_TIMING_WAP2PRE,
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MC_EMEM_ARB_TIMING_R2R,
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MC_EMEM_ARB_TIMING_W2W,
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MC_EMEM_ARB_TIMING_R2W,
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MC_EMEM_ARB_TIMING_W2R,
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MC_EMEM_ARB_DA_TURNS,
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MC_EMEM_ARB_DA_COVERS,
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MC_EMEM_ARB_MISC0,
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MC_EMEM_ARB_MISC1,
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MC_EMEM_ARB_RING3_THROTTLE,
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MC_EMEM_ARB_OVERRIDE,
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MC_INTMASK,
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};
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#ifdef CONFIG_PM
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static int tegra30_mc_suspend(struct device *dev)
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{
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int i;
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struct tegra30_mc *mc = dev_get_drvdata(dev);
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for (i = 0; i < ARRAY_SIZE(tegra30_mc_ctx); i++)
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mc->ctx[i] = mc_readl(mc, tegra30_mc_ctx[i]);
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return 0;
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}
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static int tegra30_mc_resume(struct device *dev)
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{
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int i;
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struct tegra30_mc *mc = dev_get_drvdata(dev);
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for (i = 0; i < ARRAY_SIZE(tegra30_mc_ctx); i++)
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mc_writel(mc, mc->ctx[i], tegra30_mc_ctx[i]);
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mc_writel(mc, 1, MC_TIMING_CONTROL);
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/* Read-back to ensure that write reached */
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mc_readl(mc, MC_TIMING_CONTROL);
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return 0;
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}
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#endif
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static UNIVERSAL_DEV_PM_OPS(tegra30_mc_pm,
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tegra30_mc_suspend,
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tegra30_mc_resume, NULL);
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static const struct of_device_id tegra30_mc_of_match[] = {
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{ .compatible = "nvidia,tegra30-mc", },
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{},
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};
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static irqreturn_t tegra30_mc_isr(int irq, void *data)
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{
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u32 stat, mask, bit;
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struct tegra30_mc *mc = data;
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stat = mc_readl(mc, MC_INTSTATUS);
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mask = mc_readl(mc, MC_INTMASK);
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mask &= stat;
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if (!mask)
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return IRQ_NONE;
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while ((bit = ffs(mask)) != 0) {
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tegra30_mc_decode(mc, bit - 1);
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mask &= ~BIT(bit - 1);
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}
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mc_writel(mc, stat, MC_INTSTATUS);
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return IRQ_HANDLED;
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}
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static int tegra30_mc_probe(struct platform_device *pdev)
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{
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struct resource *irq;
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struct tegra30_mc *mc;
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size_t bytes;
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int err, i;
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u32 intmask;
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bytes = sizeof(*mc) + sizeof(u32) * ARRAY_SIZE(tegra30_mc_ctx);
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mc = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
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if (!mc)
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return -ENOMEM;
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mc->dev = &pdev->dev;
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for (i = 0; i < ARRAY_SIZE(mc->regs); i++) {
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struct resource *res;
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res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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mc->regs[i] = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(mc->regs[i]))
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return PTR_ERR(mc->regs[i]);
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}
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irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (!irq)
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return -ENODEV;
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err = devm_request_irq(&pdev->dev, irq->start, tegra30_mc_isr,
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IRQF_SHARED, dev_name(&pdev->dev), mc);
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if (err)
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return -ENODEV;
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platform_set_drvdata(pdev, mc);
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intmask = MC_INT_INVALID_SMMU_PAGE |
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MC_INT_DECERR_EMEM | MC_INT_SECURITY_VIOLATION;
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mc_writel(mc, intmask, MC_INTMASK);
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return 0;
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}
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static struct platform_driver tegra30_mc_driver = {
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.probe = tegra30_mc_probe,
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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.of_match_table = tegra30_mc_of_match,
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.pm = &tegra30_mc_pm,
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},
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};
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module_platform_driver(tegra30_mc_driver);
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MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
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MODULE_DESCRIPTION("Tegra30 MC driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:" DRV_NAME);
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