mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 01:08:03 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
390
drivers/mfd/max77833-irq.c
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390
drivers/mfd/max77833-irq.c
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@ -0,0 +1,390 @@
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/*
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* max77833-irq.c - Interrupt controller support for MAX77833
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*
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* Copyright (C) 2011 Samsung Electronics Co.Ltd
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* Seoyoung Jeong <seo0.jeong@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* This driver is based on max77833-irq.c
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*/
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#include <linux/err.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/gpio.h>
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#include <linux/mfd/max77833.h>
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#include <linux/mfd/max77833-private.h>
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static const u8 max77833_mask_reg[] = {
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/* TODO: Need to check other INTMASK */
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[TOP_INT] = MAX77833_PMIC_REG_SYSTEM_INT_MASK,
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[CHG_INT] = MAX77833_CHG_REG_INT_MASK,
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[MUIC_INT1] = MAX77833_MUIC_REG_INTMASK1,
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[MUIC_INT2] = MAX77833_MUIC_REG_INTMASK2,
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[MUIC_INT3] = MAX77833_MUIC_REG_INTMASK3,
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// [FUEL_INT] = MAX77833_FG_REG_INT_MASK,
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};
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static struct i2c_client *get_i2c(struct max77833_dev *max77833,
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enum max77833_irq_source src)
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{
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switch (src) {
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case TOP_INT:
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return max77833->i2c;
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// case FUEL_INT:
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// return max77833->fuelgauge;
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case CHG_INT:
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return max77833->i2c;
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case MUIC_INT1 ... MUIC_MAX_INT:
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return max77833->muic;
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default:
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return ERR_PTR(-EINVAL);
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}
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}
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struct max77833_irq_data {
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int mask;
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enum max77833_irq_source group;
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};
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#define DECLARE_IRQ(idx, _group, _mask) \
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[(idx)] = { .group = (_group), .mask = (_mask) }
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static const struct max77833_irq_data max77833_irqs[] = {
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DECLARE_IRQ(MAX77833_SYSTEM_IRQ_T100C_INT, TOP_INT, 1 << 0),
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DECLARE_IRQ(MAX77833_SYSTEM_IRQ_T120C_INT, TOP_INT, 1 << 1),
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DECLARE_IRQ(MAX77833_SYSTEM_IRQ_T140C_INT, TOP_INT, 1 << 2),
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DECLARE_IRQ(MAX77833_SYSTEM_IRQ_I2C_WD_INT, TOP_INT, 1 << 3),
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DECLARE_IRQ(MAX77833_SYSTEM_IRQ_SYSUVLO_INT, TOP_INT, 1 << 4),
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DECLARE_IRQ(MAX77833_SYSTEM_IRQ_MRSTB_INT, TOP_INT, 1 << 5),
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DECLARE_IRQ(MAX77833_SYSTEM_IRQ_TS_INT, TOP_INT, 1 << 7),
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DECLARE_IRQ(MAX77833_CHG_IRQ_BYP_I, CHG_INT, 1 << 0),
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DECLARE_IRQ(MAX77833_CHG_IRQ_BATP_I, CHG_INT, 1 << 2),
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DECLARE_IRQ(MAX77833_CHG_IRQ_BAT_I, CHG_INT, 1 << 3),
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DECLARE_IRQ(MAX77833_CHG_IRQ_CHG_I, CHG_INT, 1 << 4),
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DECLARE_IRQ(MAX77833_CHG_IRQ_WCIN_I, CHG_INT, 1 << 5),
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DECLARE_IRQ(MAX77833_CHG_IRQ_CHGIN_I, CHG_INT, 1 << 6),
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DECLARE_IRQ(MAX77833_CHG_IRQ_AICL_I, CHG_INT, 1 << 7),
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// DECLARE_IRQ(MAX77833_FG_IRQ_ALERT, FUEL_INT, 1 << 4),
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DECLARE_IRQ(MAX77833_MUIC_IRQ_INT1_RESERVED, MUIC_INT1, 0 << 0),
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DECLARE_IRQ(MAX77833_MUIC_IRQ_INT2_RESERVED, MUIC_INT2, 0 << 0),
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DECLARE_IRQ(MAX77833_MUIC_IRQ_INT3_IDRES_INT, MUIC_INT3, 1 << 0),
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DECLARE_IRQ(MAX77833_MUIC_IRQ_INT3_CHGTYP_INT, MUIC_INT3, 1 << 1),
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DECLARE_IRQ(MAX77833_MUIC_IRQ_INT3_CHGTYP_RUN_INT, MUIC_INT3, 1 << 2),
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DECLARE_IRQ(MAX77833_MUIC_IRQ_INT3_SYSMSG_INT, MUIC_INT3, 1 << 6),
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DECLARE_IRQ(MAX77833_MUIC_IRQ_INT3_APCMD_RESP_INT, MUIC_INT3, 1 << 7),
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};
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static void max77833_irq_lock(struct irq_data *data)
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{
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struct max77833_dev *max77833 = irq_get_chip_data(data->irq);
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mutex_lock(&max77833->irqlock);
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}
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static void max77833_irq_sync_unlock(struct irq_data *data)
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{
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struct max77833_dev *max77833 = irq_get_chip_data(data->irq);
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int i;
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for (i = 0; i < MAX77833_IRQ_GROUP_NR; i++) {
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u8 mask_reg = max77833_mask_reg[i];
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struct i2c_client *i2c = get_i2c(max77833, i);
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if (mask_reg == MAX77833_REG_INVALID ||
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IS_ERR_OR_NULL(i2c))
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continue;
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max77833->irq_masks_cache[i] = max77833->irq_masks_cur[i];
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max77833_write_reg(i2c, max77833_mask_reg[i],
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max77833->irq_masks_cur[i]);
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}
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mutex_unlock(&max77833->irqlock);
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}
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static const inline struct max77833_irq_data *
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irq_to_max77833_irq(struct max77833_dev *max77833, int irq)
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{
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return &max77833_irqs[irq - max77833->irq_base];
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}
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static void max77833_irq_mask(struct irq_data *data)
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{
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struct max77833_dev *max77833 = irq_get_chip_data(data->irq);
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const struct max77833_irq_data *irq_data =
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irq_to_max77833_irq(max77833, data->irq);
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if (irq_data->group >= MAX77833_IRQ_GROUP_NR)
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return;
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if (irq_data->group >= MUIC_INT1 && irq_data->group <= MUIC_MAX_INT)
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max77833->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
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else
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max77833->irq_masks_cur[irq_data->group] |= irq_data->mask;
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}
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static void max77833_irq_unmask(struct irq_data *data)
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{
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struct max77833_dev *max77833 = irq_get_chip_data(data->irq);
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const struct max77833_irq_data *irq_data =
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irq_to_max77833_irq(max77833, data->irq);
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if (irq_data->group >= MAX77833_IRQ_GROUP_NR)
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return;
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if (irq_data->group >= MUIC_INT1 && irq_data->group <= MUIC_MAX_INT)
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max77833->irq_masks_cur[irq_data->group] |= irq_data->mask;
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else
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max77833->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
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}
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static struct irq_chip max77833_irq_chip = {
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.name = MFD_DEV_NAME,
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.irq_bus_lock = max77833_irq_lock,
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.irq_bus_sync_unlock = max77833_irq_sync_unlock,
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.irq_mask = max77833_irq_mask,
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.irq_unmask = max77833_irq_unmask,
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};
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static irqreturn_t max77833_irq_thread(int irq, void *data)
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{
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struct max77833_dev *max77833 = data;
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u8 irq_reg[MAX77833_IRQ_GROUP_NR] = {0};
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u8 tmp_irq_reg[MAX77833_IRQ_GROUP_NR] = {};
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#if defined(CONFIG_MUIC_MAX77833_SUPPORT_AFC_CHARGER)
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u8 tmp_irq_mask_reg[MAX77833_IRQ_GROUP_NR] = {};
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#endif /* CONFIG_MUIC_MAX77833_SUPPORT_AFC_CHARGER */
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static int check_num;
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u8 irq_src;
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int i, ret;
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pr_info("%s: irq gpio pre-state(0x%02x)\n", __func__,
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gpio_get_value(max77833->irq_gpio));
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ret = max77833_read_reg(max77833->i2c,
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MAX77833_PMIC_REG_INTSRC, &irq_src);
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if (ret) {
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pr_err("%s:%s Failed to read interrupt source: %d\n",
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MFD_DEV_NAME, __func__, ret);
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return IRQ_NONE;
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}
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pr_info("%s: interrupt source(0x%02x)\n", __func__, irq_src);
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if (irq_src & MAX77833_IRQSRC_CHG) {
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/* CHG_INT */
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ret = max77833_read_reg(max77833->i2c, MAX77833_CHG_REG_INT,
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&irq_reg[CHG_INT]);
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pr_info("%s: charger interrupt(0x%02x)\n",
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__func__, irq_reg[CHG_INT]);
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/* mask chgin to prevent chgin infinite interrupt
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* chgin is unmasked chgin isr
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*/
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if (irq_reg[CHG_INT] &
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max77833_irqs[MAX77833_CHG_IRQ_CHGIN_I].mask) {
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u8 reg_data;
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max77833_read_reg(max77833->i2c,
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MAX77833_CHG_REG_INT_MASK, ®_data);
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reg_data |= (1 << 6);
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max77833_write_reg(max77833->i2c,
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MAX77833_CHG_REG_INT_MASK, reg_data);
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}
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}
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#if 0
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if (irq_src & MAX77833_IRQSRC_FG) {
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pr_info("[%s] fuelgauge interrupt\n", __func__);
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pr_info("[%s]IRQ_BASE(%d), NESTED_IRQ(%d)\n",
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__func__, max77833->irq_base, max77833->irq_base + MAX77833_FG_IRQ_ALERT);
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handle_nested_irq(max77833->irq_base + MAX77833_FG_IRQ_ALERT);
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return IRQ_HANDLED;
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}
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#endif
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if (irq_src & MAX77833_IRQSRC_TOP) {
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/* TOP_INT */
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ret = max77833_read_reg(max77833->i2c, MAX77833_PMIC_REG_SYSTEM_INT,
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&irq_reg[TOP_INT]);
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pr_info("%s: topsys interrupt(0x%02x)\n", __func__, irq_reg[TOP_INT]);
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}
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if (irq_src & MAX77833_IRQSRC_MUIC) {
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/* MUIC INT1 ~ INT3 */
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ret = max77833_bulk_read(max77833->muic, MAX77833_MUIC_REG_INT1,
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MAX77833_NUM_IRQ_MUIC_REGS, &tmp_irq_reg[MUIC_INT1]);
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if (ret) {
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pr_err("%s:%s Failed to read interrupt source: %d\n",
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MFD_DEV_NAME, __func__, ret);
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return IRQ_NONE;
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}
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#if defined(CONFIG_MUIC_MAX77833_SUPPORT_AFC_CHARGER)
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max77833_bulk_read(max77833->muic, MAX77833_MUIC_REG_INTMASK1,
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MAX77833_NUM_IRQ_MUIC_REGS, &tmp_irq_mask_reg[MUIC_INT1]);
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for (i = MUIC_INT1; i < MAX77833_IRQ_GROUP_NR; i++)
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tmp_irq_reg[i] &= tmp_irq_mask_reg[i];
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#endif /* CONFIG_MUIC_MAX77833_SUPPORT_AFC_CHARGER */
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/* Or temp irq register to irq register for if it retries */
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for (i = MUIC_INT1; i <= MUIC_MAX_INT; i++)
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irq_reg[i] |= tmp_irq_reg[i];
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pr_info("%s: muic interrupt(0x%02x, 0x%02x, 0x%02x)\n", __func__,
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irq_reg[MUIC_INT1], irq_reg[MUIC_INT2], irq_reg[MUIC_INT3]);
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/* for debug */
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if ((irq_reg[MUIC_INT1] == 0) && (irq_reg[MUIC_INT2] == 0)
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&& (irq_reg[MUIC_INT3] == 0)) {
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pr_info("%s: irq gpio post-state(0x%02x)\n", __func__,
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gpio_get_value(max77833->irq_gpio));
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if (check_num >= 15) {
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max77833_muic_read_register(max77833->muic);
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panic("max77833 muic interrupt gpio Err!\n");
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}
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check_num++;
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} else
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check_num = 0;
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}
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/* Apply masking */
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for (i = 0; i < MAX77833_IRQ_GROUP_NR; i++) {
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if (i >= MUIC_INT1 && i <= MUIC_MAX_INT)
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irq_reg[i] &= max77833->irq_masks_cur[i];
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else
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irq_reg[i] &= ~max77833->irq_masks_cur[i];
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}
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/* Report */
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for (i = 0; i < MAX77833_IRQ_NR; i++) {
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if (irq_reg[max77833_irqs[i].group] & max77833_irqs[i].mask)
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handle_nested_irq(max77833->irq_base + i);
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}
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return IRQ_HANDLED;
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}
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int max77833_irq_init(struct max77833_dev *max77833)
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{
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int i;
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int ret;
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u8 i2c_data;
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if (!max77833->irq_gpio) {
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dev_warn(max77833->dev, "No interrupt specified.\n");
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max77833->irq_base = 0;
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return 0;
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}
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if (!max77833->irq_base) {
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dev_err(max77833->dev, "No interrupt base specified.\n");
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return 0;
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}
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mutex_init(&max77833->irqlock);
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max77833->irq = gpio_to_irq(max77833->irq_gpio);
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pr_info("%s:%s irq=%d, irq->gpio=%d\n", MFD_DEV_NAME, __func__,
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max77833->irq, max77833->irq_gpio);
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ret = gpio_request(max77833->irq_gpio, "if_pmic_irq");
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if (ret) {
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dev_err(max77833->dev, "%s: failed requesting gpio %d\n",
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__func__, max77833->irq_gpio);
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return ret;
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}
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gpio_direction_input(max77833->irq_gpio);
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gpio_free(max77833->irq_gpio);
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/* Mask individual interrupt sources */
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for (i = 0; i < MAX77833_IRQ_GROUP_NR; i++) {
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struct i2c_client *i2c;
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/* MUIC IRQ 0:MASK 1:NOT MASK */
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/* Other IRQ 1:MASK 0:NOT MASK */
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if (i >= MUIC_INT1 && i <= MUIC_INT3) {
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max77833->irq_masks_cur[i] = 0x00;
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max77833->irq_masks_cache[i] = 0x00;
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} else {
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max77833->irq_masks_cur[i] = 0xff;
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max77833->irq_masks_cache[i] = 0xff;
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}
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i2c = get_i2c(max77833, i);
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if (IS_ERR_OR_NULL(i2c))
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continue;
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if (max77833_mask_reg[i] == MAX77833_REG_INVALID)
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continue;
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if (i >= MUIC_INT1 && i <= MUIC_INT3)
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max77833_write_reg(i2c, max77833_mask_reg[i], 0x00);
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else
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max77833_write_reg(i2c, max77833_mask_reg[i], 0xff);
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}
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/* Register with genirq */
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for (i = 0; i < MAX77833_IRQ_NR; i++) {
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int cur_irq;
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cur_irq = i + max77833->irq_base;
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irq_set_chip_data(cur_irq, max77833);
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irq_set_chip_and_handler(cur_irq, &max77833_irq_chip,
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handle_level_irq);
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irq_set_nested_thread(cur_irq, 1);
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#ifdef CONFIG_ARM
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set_irq_flags(cur_irq, IRQF_VALID);
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#else
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irq_set_noprobe(cur_irq);
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#endif
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}
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/* Unmask max77833 interrupt */
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ret = max77833_read_reg(max77833->i2c, MAX77833_PMIC_REG_INTSRC_MASK,
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&i2c_data);
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if (ret) {
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pr_err("%s:%s fail to read muic reg\n", MFD_DEV_NAME, __func__);
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return ret;
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}
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i2c_data &= ~(MAX77833_IRQSRC_CHG); /* Unmask charger interrupt */
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// i2c_data &= ~(MAX77833_IRQSRC_FG); /* Unmask fg interrupt */
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i2c_data &= ~(MAX77833_IRQSRC_MUIC); /* Unmask muic interrupt */
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max77833_write_reg(max77833->i2c, MAX77833_PMIC_REG_INTSRC_MASK,
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i2c_data);
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pr_info("%s:%s max77833_PMIC_REG_INTSRC_MASK=0x%02x\n",
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MFD_DEV_NAME, __func__, i2c_data);
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ret = request_threaded_irq(max77833->irq, NULL, max77833_irq_thread,
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IRQF_TRIGGER_LOW | IRQF_ONESHOT,
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"max77833-irq", max77833);
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if (ret) {
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dev_err(max77833->dev, "Failed to request IRQ %d: %d\n",
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max77833->irq, ret);
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return ret;
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}
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return 0;
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}
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void max77833_irq_exit(struct max77833_dev *max77833)
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{
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if (max77833->irq)
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free_irq(max77833->irq, max77833);
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}
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