mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
339
drivers/mfd/ssbi.c
Normal file
339
drivers/mfd/ssbi.c
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@ -0,0 +1,339 @@
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/* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
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* Copyright (c) 2010, Google Inc.
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*
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* Original authors: Code Aurora Forum
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*
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* Author: Dima Zavin <dima@android.com>
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* - Largely rewritten from original to not be an i2c driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/ssbi.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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/* SSBI 2.0 controller registers */
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#define SSBI2_CMD 0x0008
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#define SSBI2_RD 0x0010
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#define SSBI2_STATUS 0x0014
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#define SSBI2_MODE2 0x001C
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/* SSBI_CMD fields */
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#define SSBI_CMD_RDWRN (1 << 24)
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/* SSBI_STATUS fields */
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#define SSBI_STATUS_RD_READY (1 << 2)
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#define SSBI_STATUS_READY (1 << 1)
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#define SSBI_STATUS_MCHN_BUSY (1 << 0)
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/* SSBI_MODE2 fields */
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#define SSBI_MODE2_REG_ADDR_15_8_SHFT 0x04
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#define SSBI_MODE2_REG_ADDR_15_8_MASK (0x7f << SSBI_MODE2_REG_ADDR_15_8_SHFT)
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#define SET_SSBI_MODE2_REG_ADDR_15_8(MD, AD) \
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(((MD) & 0x0F) | ((((AD) >> 8) << SSBI_MODE2_REG_ADDR_15_8_SHFT) & \
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SSBI_MODE2_REG_ADDR_15_8_MASK))
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/* SSBI PMIC Arbiter command registers */
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#define SSBI_PA_CMD 0x0000
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#define SSBI_PA_RD_STATUS 0x0004
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/* SSBI_PA_CMD fields */
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#define SSBI_PA_CMD_RDWRN (1 << 24)
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#define SSBI_PA_CMD_ADDR_MASK 0x7fff /* REG_ADDR_7_0, REG_ADDR_8_14*/
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/* SSBI_PA_RD_STATUS fields */
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#define SSBI_PA_RD_STATUS_TRANS_DONE (1 << 27)
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#define SSBI_PA_RD_STATUS_TRANS_DENIED (1 << 26)
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#define SSBI_TIMEOUT_US 100
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enum ssbi_controller_type {
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MSM_SBI_CTRL_SSBI = 0,
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MSM_SBI_CTRL_SSBI2,
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MSM_SBI_CTRL_PMIC_ARBITER,
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};
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struct ssbi {
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struct device *slave;
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void __iomem *base;
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spinlock_t lock;
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enum ssbi_controller_type controller_type;
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int (*read)(struct ssbi *, u16 addr, u8 *buf, int len);
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int (*write)(struct ssbi *, u16 addr, const u8 *buf, int len);
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};
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#define to_ssbi(dev) platform_get_drvdata(to_platform_device(dev))
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static inline u32 ssbi_readl(struct ssbi *ssbi, u32 reg)
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{
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return readl(ssbi->base + reg);
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}
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static inline void ssbi_writel(struct ssbi *ssbi, u32 val, u32 reg)
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{
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writel(val, ssbi->base + reg);
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}
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/*
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* Via private exchange with one of the original authors, the hardware
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* should generally finish a transaction in about 5us. The worst
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* case, is when using the arbiter and both other CPUs have just
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* started trying to use the SSBI bus will result in a time of about
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* 20us. It should never take longer than this.
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*
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* As such, this wait merely spins, with a udelay.
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*/
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static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask)
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{
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u32 timeout = SSBI_TIMEOUT_US;
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u32 val;
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while (timeout--) {
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val = ssbi_readl(ssbi, SSBI2_STATUS);
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if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0))
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return 0;
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static int
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ssbi_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len)
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{
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u32 cmd = SSBI_CMD_RDWRN | ((addr & 0xff) << 16);
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int ret = 0;
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if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
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u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
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mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
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ssbi_writel(ssbi, mode2, SSBI2_MODE2);
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}
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while (len) {
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ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
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if (ret)
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goto err;
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ssbi_writel(ssbi, cmd, SSBI2_CMD);
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ret = ssbi_wait_mask(ssbi, SSBI_STATUS_RD_READY, 0);
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if (ret)
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goto err;
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*buf++ = ssbi_readl(ssbi, SSBI2_RD) & 0xff;
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len--;
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}
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err:
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return ret;
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}
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static int
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ssbi_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len)
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{
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int ret = 0;
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if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
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u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
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mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
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ssbi_writel(ssbi, mode2, SSBI2_MODE2);
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}
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while (len) {
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ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
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if (ret)
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goto err;
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ssbi_writel(ssbi, ((addr & 0xff) << 16) | *buf, SSBI2_CMD);
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ret = ssbi_wait_mask(ssbi, 0, SSBI_STATUS_MCHN_BUSY);
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if (ret)
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goto err;
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buf++;
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len--;
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}
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err:
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return ret;
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}
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/*
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* See ssbi_wait_mask for an explanation of the time and the
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* busywait.
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*/
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static inline int
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ssbi_pa_transfer(struct ssbi *ssbi, u32 cmd, u8 *data)
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{
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u32 timeout = SSBI_TIMEOUT_US;
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u32 rd_status = 0;
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ssbi_writel(ssbi, cmd, SSBI_PA_CMD);
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while (timeout--) {
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rd_status = ssbi_readl(ssbi, SSBI_PA_RD_STATUS);
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if (rd_status & SSBI_PA_RD_STATUS_TRANS_DENIED)
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return -EPERM;
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if (rd_status & SSBI_PA_RD_STATUS_TRANS_DONE) {
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if (data)
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*data = rd_status & 0xff;
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return 0;
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}
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static int
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ssbi_pa_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len)
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{
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u32 cmd;
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int ret = 0;
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cmd = SSBI_PA_CMD_RDWRN | (addr & SSBI_PA_CMD_ADDR_MASK) << 8;
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while (len) {
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ret = ssbi_pa_transfer(ssbi, cmd, buf);
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if (ret)
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goto err;
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buf++;
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len--;
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}
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err:
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return ret;
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}
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static int
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ssbi_pa_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len)
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{
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u32 cmd;
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int ret = 0;
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while (len) {
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cmd = (addr & SSBI_PA_CMD_ADDR_MASK) << 8 | *buf;
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ret = ssbi_pa_transfer(ssbi, cmd, NULL);
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if (ret)
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goto err;
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buf++;
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len--;
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}
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err:
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return ret;
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}
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int ssbi_read(struct device *dev, u16 addr, u8 *buf, int len)
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{
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struct ssbi *ssbi = to_ssbi(dev);
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&ssbi->lock, flags);
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ret = ssbi->read(ssbi, addr, buf, len);
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spin_unlock_irqrestore(&ssbi->lock, flags);
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return ret;
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}
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EXPORT_SYMBOL_GPL(ssbi_read);
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int ssbi_write(struct device *dev, u16 addr, const u8 *buf, int len)
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{
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struct ssbi *ssbi = to_ssbi(dev);
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&ssbi->lock, flags);
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ret = ssbi->write(ssbi, addr, buf, len);
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spin_unlock_irqrestore(&ssbi->lock, flags);
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return ret;
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}
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EXPORT_SYMBOL_GPL(ssbi_write);
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static int ssbi_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct resource *mem_res;
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struct ssbi *ssbi;
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const char *type;
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ssbi = devm_kzalloc(&pdev->dev, sizeof(*ssbi), GFP_KERNEL);
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if (!ssbi)
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return -ENOMEM;
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mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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ssbi->base = devm_ioremap_resource(&pdev->dev, mem_res);
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if (IS_ERR(ssbi->base))
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return PTR_ERR(ssbi->base);
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platform_set_drvdata(pdev, ssbi);
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type = of_get_property(np, "qcom,controller-type", NULL);
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if (type == NULL) {
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dev_err(&pdev->dev, "Missing qcom,controller-type property\n");
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return -EINVAL;
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}
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dev_info(&pdev->dev, "SSBI controller type: '%s'\n", type);
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if (strcmp(type, "ssbi") == 0)
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ssbi->controller_type = MSM_SBI_CTRL_SSBI;
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else if (strcmp(type, "ssbi2") == 0)
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ssbi->controller_type = MSM_SBI_CTRL_SSBI2;
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else if (strcmp(type, "pmic-arbiter") == 0)
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ssbi->controller_type = MSM_SBI_CTRL_PMIC_ARBITER;
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else {
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dev_err(&pdev->dev, "Unknown qcom,controller-type\n");
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return -EINVAL;
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}
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if (ssbi->controller_type == MSM_SBI_CTRL_PMIC_ARBITER) {
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ssbi->read = ssbi_pa_read_bytes;
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ssbi->write = ssbi_pa_write_bytes;
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} else {
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ssbi->read = ssbi_read_bytes;
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ssbi->write = ssbi_write_bytes;
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}
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spin_lock_init(&ssbi->lock);
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return of_platform_populate(np, NULL, NULL, &pdev->dev);
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}
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static const struct of_device_id ssbi_match_table[] = {
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{ .compatible = "qcom,ssbi" },
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{}
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};
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MODULE_DEVICE_TABLE(of, ssbi_match_table);
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static struct platform_driver ssbi_driver = {
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.probe = ssbi_probe,
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.driver = {
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.name = "ssbi",
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.owner = THIS_MODULE,
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.of_match_table = ssbi_match_table,
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},
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};
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module_platform_driver(ssbi_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_VERSION("1.0");
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MODULE_ALIAS("platform:ssbi");
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MODULE_AUTHOR("Dima Zavin <dima@android.com>");
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