mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
286
drivers/mfd/stmpe.h
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286
drivers/mfd/stmpe.h
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/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* License Terms: GNU General Public License, version 2
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* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
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*/
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#ifndef __STMPE_H
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#define __STMPE_H
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#include <linux/device.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/stmpe.h>
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#include <linux/printk.h>
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#include <linux/types.h>
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extern const struct dev_pm_ops stmpe_dev_pm_ops;
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#ifdef STMPE_DUMP_BYTES
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static inline void stmpe_dump_bytes(const char *str, const void *buf,
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size_t len)
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{
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print_hex_dump_bytes(str, DUMP_PREFIX_OFFSET, buf, len);
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}
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#else
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static inline void stmpe_dump_bytes(const char *str, const void *buf,
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size_t len)
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{
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}
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#endif
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/**
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* struct stmpe_variant_block - information about block
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* @cell: base mfd cell
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* @irq: interrupt number to be added to each IORESOURCE_IRQ
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* in the cell
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* @block: block id; used for identification with platform data and for
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* enable and altfunc callbacks
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*/
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struct stmpe_variant_block {
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const struct mfd_cell *cell;
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int irq;
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enum stmpe_block block;
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};
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/**
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* struct stmpe_variant_info - variant-specific information
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* @name: part name
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* @id_val: content of CHIPID register
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* @id_mask: bits valid in CHIPID register for comparison with id_val
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* @num_gpios: number of GPIOS
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* @af_bits: number of bits used to specify the alternate function
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* @regs: variant specific registers.
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* @blocks: list of blocks present on this device
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* @num_blocks: number of blocks present on this device
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* @num_irqs: number of internal IRQs available on this device
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* @enable: callback to enable the specified blocks.
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* Called with the I/O lock held.
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* @get_altfunc: callback to get the alternate function number for the
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* specific block
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* @enable_autosleep: callback to configure autosleep with specified timeout
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*/
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struct stmpe_variant_info {
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const char *name;
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u16 id_val;
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u16 id_mask;
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int num_gpios;
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int af_bits;
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const u8 *regs;
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struct stmpe_variant_block *blocks;
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int num_blocks;
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int num_irqs;
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int (*enable)(struct stmpe *stmpe, unsigned int blocks, bool enable);
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int (*get_altfunc)(struct stmpe *stmpe, enum stmpe_block block);
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int (*enable_autosleep)(struct stmpe *stmpe, int autosleep_timeout);
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};
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/**
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* struct stmpe_client_info - i2c or spi specific routines/info
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* @data: client specific data
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* @read_byte: read single byte
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* @write_byte: write single byte
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* @read_block: read block or multiple bytes
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* @write_block: write block or multiple bytes
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* @init: client init routine, called during probe
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*/
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struct stmpe_client_info {
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void *data;
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int irq;
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void *client;
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struct device *dev;
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int (*read_byte)(struct stmpe *stmpe, u8 reg);
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int (*write_byte)(struct stmpe *stmpe, u8 reg, u8 val);
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int (*read_block)(struct stmpe *stmpe, u8 reg, u8 len, u8 *values);
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int (*write_block)(struct stmpe *stmpe, u8 reg, u8 len,
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const u8 *values);
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void (*init)(struct stmpe *stmpe);
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};
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int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum);
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int stmpe_remove(struct stmpe *stmpe);
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#define STMPE_ICR_LSB_HIGH (1 << 2)
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#define STMPE_ICR_LSB_EDGE (1 << 1)
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#define STMPE_ICR_LSB_GIM (1 << 0)
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/*
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* STMPE801
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*/
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#define STMPE801_ID 0x0108
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#define STMPE801_NR_INTERNAL_IRQS 1
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#define STMPE801_REG_CHIP_ID 0x00
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#define STMPE801_REG_VERSION_ID 0x02
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#define STMPE801_REG_SYS_CTRL 0x04
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#define STMPE801_REG_GPIO_INT_EN 0x08
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#define STMPE801_REG_GPIO_INT_STA 0x09
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#define STMPE801_REG_GPIO_MP_STA 0x10
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#define STMPE801_REG_GPIO_SET_PIN 0x11
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#define STMPE801_REG_GPIO_DIR 0x12
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#define STMPE801_REG_SYS_CTRL_RESET (1 << 7)
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#define STMPE801_REG_SYS_CTRL_INT_EN (1 << 2)
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#define STMPE801_REG_SYS_CTRL_INT_HI (1 << 0)
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/*
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* STMPE811
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*/
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#define STMPE811_IRQ_TOUCH_DET 0
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#define STMPE811_IRQ_FIFO_TH 1
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#define STMPE811_IRQ_FIFO_OFLOW 2
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#define STMPE811_IRQ_FIFO_FULL 3
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#define STMPE811_IRQ_FIFO_EMPTY 4
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#define STMPE811_IRQ_TEMP_SENS 5
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#define STMPE811_IRQ_ADC 6
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#define STMPE811_IRQ_GPIOC 7
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#define STMPE811_NR_INTERNAL_IRQS 8
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#define STMPE811_REG_CHIP_ID 0x00
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#define STMPE811_REG_SYS_CTRL2 0x04
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#define STMPE811_REG_SPI_CFG 0x08
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#define STMPE811_REG_INT_CTRL 0x09
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#define STMPE811_REG_INT_EN 0x0A
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#define STMPE811_REG_INT_STA 0x0B
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#define STMPE811_REG_GPIO_INT_EN 0x0C
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#define STMPE811_REG_GPIO_INT_STA 0x0D
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#define STMPE811_REG_GPIO_SET_PIN 0x10
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#define STMPE811_REG_GPIO_CLR_PIN 0x11
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#define STMPE811_REG_GPIO_MP_STA 0x12
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#define STMPE811_REG_GPIO_DIR 0x13
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#define STMPE811_REG_GPIO_ED 0x14
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#define STMPE811_REG_GPIO_RE 0x15
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#define STMPE811_REG_GPIO_FE 0x16
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#define STMPE811_REG_GPIO_AF 0x17
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#define STMPE811_SYS_CTRL2_ADC_OFF (1 << 0)
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#define STMPE811_SYS_CTRL2_TSC_OFF (1 << 1)
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#define STMPE811_SYS_CTRL2_GPIO_OFF (1 << 2)
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#define STMPE811_SYS_CTRL2_TS_OFF (1 << 3)
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/*
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* STMPE1601
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*/
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#define STMPE1601_IRQ_GPIOC 8
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#define STMPE1601_IRQ_PWM3 7
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#define STMPE1601_IRQ_PWM2 6
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#define STMPE1601_IRQ_PWM1 5
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#define STMPE1601_IRQ_PWM0 4
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#define STMPE1601_IRQ_KEYPAD_OVER 2
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#define STMPE1601_IRQ_KEYPAD 1
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#define STMPE1601_IRQ_WAKEUP 0
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#define STMPE1601_NR_INTERNAL_IRQS 9
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#define STMPE1601_REG_SYS_CTRL 0x02
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#define STMPE1601_REG_SYS_CTRL2 0x03
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#define STMPE1601_REG_ICR_LSB 0x11
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#define STMPE1601_REG_IER_LSB 0x13
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#define STMPE1601_REG_ISR_MSB 0x14
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#define STMPE1601_REG_CHIP_ID 0x80
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#define STMPE1601_REG_INT_EN_GPIO_MASK_LSB 0x17
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#define STMPE1601_REG_INT_STA_GPIO_MSB 0x18
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#define STMPE1601_REG_GPIO_MP_LSB 0x87
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#define STMPE1601_REG_GPIO_SET_LSB 0x83
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#define STMPE1601_REG_GPIO_CLR_LSB 0x85
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#define STMPE1601_REG_GPIO_SET_DIR_LSB 0x89
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#define STMPE1601_REG_GPIO_ED_MSB 0x8A
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#define STMPE1601_REG_GPIO_RE_LSB 0x8D
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#define STMPE1601_REG_GPIO_FE_LSB 0x8F
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#define STMPE1601_REG_GPIO_AF_U_MSB 0x92
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#define STMPE1601_SYS_CTRL_ENABLE_GPIO (1 << 3)
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#define STMPE1601_SYS_CTRL_ENABLE_KPC (1 << 1)
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#define STMPE1601_SYS_CTRL_ENABLE_SPWM (1 << 0)
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/* The 1601/2403 share the same masks */
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#define STMPE1601_AUTOSLEEP_TIMEOUT_MASK (0x7)
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#define STPME1601_AUTOSLEEP_ENABLE (1 << 3)
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/*
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* STMPE1801
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*/
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#define STMPE1801_ID 0xc110
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#define STMPE1801_NR_INTERNAL_IRQS 5
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#define STMPE1801_IRQ_KEYPAD_COMBI 4
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#define STMPE1801_IRQ_GPIOC 3
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#define STMPE1801_IRQ_KEYPAD_OVER 2
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#define STMPE1801_IRQ_KEYPAD 1
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#define STMPE1801_IRQ_WAKEUP 0
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#define STMPE1801_REG_CHIP_ID 0x00
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#define STMPE1801_REG_SYS_CTRL 0x02
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#define STMPE1801_REG_INT_CTRL_LOW 0x04
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#define STMPE1801_REG_INT_EN_MASK_LOW 0x06
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#define STMPE1801_REG_INT_STA_LOW 0x08
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#define STMPE1801_REG_INT_EN_GPIO_MASK_LOW 0x0A
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#define STMPE1801_REG_INT_EN_GPIO_MASK_MID 0x0B
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#define STMPE1801_REG_INT_EN_GPIO_MASK_HIGH 0x0C
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#define STMPE1801_REG_INT_STA_GPIO_LOW 0x0D
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#define STMPE1801_REG_INT_STA_GPIO_MID 0x0E
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#define STMPE1801_REG_INT_STA_GPIO_HIGH 0x0F
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#define STMPE1801_REG_GPIO_SET_LOW 0x10
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#define STMPE1801_REG_GPIO_SET_MID 0x11
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#define STMPE1801_REG_GPIO_SET_HIGH 0x12
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#define STMPE1801_REG_GPIO_CLR_LOW 0x13
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#define STMPE1801_REG_GPIO_CLR_MID 0x14
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#define STMPE1801_REG_GPIO_CLR_HIGH 0x15
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#define STMPE1801_REG_GPIO_MP_LOW 0x16
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#define STMPE1801_REG_GPIO_MP_MID 0x17
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#define STMPE1801_REG_GPIO_MP_HIGH 0x18
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#define STMPE1801_REG_GPIO_SET_DIR_LOW 0x19
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#define STMPE1801_REG_GPIO_SET_DIR_MID 0x1A
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#define STMPE1801_REG_GPIO_SET_DIR_HIGH 0x1B
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#define STMPE1801_REG_GPIO_RE_LOW 0x1C
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#define STMPE1801_REG_GPIO_RE_MID 0x1D
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#define STMPE1801_REG_GPIO_RE_HIGH 0x1E
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#define STMPE1801_REG_GPIO_FE_LOW 0x1F
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#define STMPE1801_REG_GPIO_FE_MID 0x20
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#define STMPE1801_REG_GPIO_FE_HIGH 0x21
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#define STMPE1801_REG_GPIO_PULL_UP_LOW 0x22
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#define STMPE1801_REG_GPIO_PULL_UP_MID 0x23
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#define STMPE1801_REG_GPIO_PULL_UP_HIGH 0x24
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#define STMPE1801_MSK_SYS_CTRL_RESET (1 << 7)
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#define STMPE1801_MSK_INT_EN_KPC (1 << 1)
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#define STMPE1801_MSK_INT_EN_GPIO (1 << 3)
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/*
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* STMPE24xx
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*/
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#define STMPE24XX_IRQ_GPIOC 8
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#define STMPE24XX_IRQ_PWM2 7
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#define STMPE24XX_IRQ_PWM1 6
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#define STMPE24XX_IRQ_PWM0 5
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#define STMPE24XX_IRQ_ROT_OVER 4
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#define STMPE24XX_IRQ_ROT 3
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#define STMPE24XX_IRQ_KEYPAD_OVER 2
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#define STMPE24XX_IRQ_KEYPAD 1
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#define STMPE24XX_IRQ_WAKEUP 0
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#define STMPE24XX_NR_INTERNAL_IRQS 9
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#define STMPE24XX_REG_SYS_CTRL 0x02
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#define STMPE24XX_REG_ICR_LSB 0x11
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#define STMPE24XX_REG_IER_LSB 0x13
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#define STMPE24XX_REG_ISR_MSB 0x14
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#define STMPE24XX_REG_CHIP_ID 0x80
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#define STMPE24XX_REG_IEGPIOR_LSB 0x18
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#define STMPE24XX_REG_ISGPIOR_MSB 0x19
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#define STMPE24XX_REG_GPMR_LSB 0xA4
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#define STMPE24XX_REG_GPSR_LSB 0x85
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#define STMPE24XX_REG_GPCR_LSB 0x88
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#define STMPE24XX_REG_GPDR_LSB 0x8B
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#define STMPE24XX_REG_GPEDR_MSB 0x8C
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#define STMPE24XX_REG_GPRER_LSB 0x91
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#define STMPE24XX_REG_GPFER_LSB 0x94
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#define STMPE24XX_REG_GPAFR_U_MSB 0x9B
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#define STMPE24XX_SYS_CTRL_ENABLE_GPIO (1 << 3)
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#define STMPE24XX_SYSCON_ENABLE_PWM (1 << 2)
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#define STMPE24XX_SYS_CTRL_ENABLE_KPC (1 << 1)
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#define STMPE24XX_SYSCON_ENABLE_ROT (1 << 0)
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#endif
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