mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-30 23:58:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
244
drivers/misc/samsung/scsc/mifintrbit.c
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244
drivers/misc/samsung/scsc/mifintrbit.c
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/****************************************************************************
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*
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* Copyright (c) 2014 - 2016 Samsung Electronics Co., Ltd. All rights reserved
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*
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****************************************************************************/
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/* Uses */
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#include <linux/bitmap.h>
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#include <linux/errno.h>
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#include <linux/spinlock.h>
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#include <scsc/scsc_logring.h>
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#include "scsc_mif_abs.h"
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/* Implements */
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#include "mifintrbit.h"
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/* default handler just logs a warning and clears the bit */
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static void mifintrbit_default_handler(int irq, void *data)
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{
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struct mifintrbit *intr = (struct mifintrbit *)data;
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unsigned long flags;
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spin_lock_irqsave(&intr->spinlock, flags);
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intr->mif->irq_bit_clear(intr->mif, irq);
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spin_unlock_irqrestore(&intr->spinlock, flags);
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}
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static void print_bitmaps(struct mifintrbit *intr)
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{
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unsigned long dst1, dst2, dst3;
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bitmap_copy_le(&dst1, intr->bitmap_tohost, MIFINTRBIT_NUM_INT);
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bitmap_copy_le(&dst2, intr->bitmap_fromhost_r4, MIFINTRBIT_NUM_INT);
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bitmap_copy_le(&dst3, intr->bitmap_fromhost_m4, MIFINTRBIT_NUM_INT);
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}
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static void mifiintrman_isr(int irq, void *data)
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{
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struct mifintrbit *intr = (struct mifintrbit *)data;
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unsigned long flags;
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int irq_reg = 0;
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int bit;
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/* Avoid unused parameter error */
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(void)irq;
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spin_lock_irqsave(&intr->spinlock, flags);
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irq_reg = intr->mif->irq_get(intr->mif);
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print_bitmaps(intr);
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for_each_set_bit(bit, (unsigned long int *)&irq_reg, MIFINTRBIT_NUM_INT) {
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if (intr->mifintrbit_irq_handler[bit] != mifintrbit_default_handler)
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intr->mifintrbit_irq_handler[bit](bit, intr->irq_data[bit]);
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}
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spin_unlock_irqrestore(&intr->spinlock, flags);
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}
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/* Public functions */
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int mifintrbit_alloc_tohost(struct mifintrbit *intr, mifintrbit_handler handler, void *data)
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{
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struct scsc_mif_abs *mif;
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unsigned long flags;
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int which_bit = 0;
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spin_lock_irqsave(&intr->spinlock, flags);
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/* Search for free slots */
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which_bit = find_first_zero_bit(intr->bitmap_tohost, MIFINTRBIT_NUM_INT);
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if (which_bit >= MIFINTRBIT_NUM_INT)
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goto error;
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if (intr->mifintrbit_irq_handler[which_bit] != mifintrbit_default_handler) {
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spin_unlock_irqrestore(&intr->spinlock, flags);
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goto error;
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}
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/* Get abs implementation */
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mif = intr->mif;
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/* Mask to prevent spurious incoming interrupts */
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mif->irq_bit_mask(mif, which_bit);
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/* Clear the interrupt */
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mif->irq_bit_clear(mif, which_bit);
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/* Register the handler */
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intr->mifintrbit_irq_handler[which_bit] = handler;
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intr->irq_data[which_bit] = data;
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/* Once registration is set, and IRQ has been cleared, unmask the interrupt */
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mif->irq_bit_unmask(mif, which_bit);
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/* Update bit mask */
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set_bit(which_bit, intr->bitmap_tohost);
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spin_unlock_irqrestore(&intr->spinlock, flags);
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return which_bit;
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error:
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spin_unlock_irqrestore(&intr->spinlock, flags);
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SCSC_TAG_ERR(MIF, "Error registering irq\n");
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return -EIO;
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}
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int mifintrbit_free_tohost(struct mifintrbit *intr, int which_bit)
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{
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struct scsc_mif_abs *mif;
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unsigned long flags;
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if (which_bit >= MIFINTRBIT_NUM_INT)
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goto error;
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spin_lock_irqsave(&intr->spinlock, flags);
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/* Get abs implementation */
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mif = intr->mif;
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/* Mask to prevent spurious incoming interrupts */
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mif->irq_bit_mask(mif, which_bit);
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/* Set the handler with default */
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intr->mifintrbit_irq_handler[which_bit] = mifintrbit_default_handler;
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intr->irq_data[which_bit] = NULL;
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/* Clear the interrupt for hygiene */
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mif->irq_bit_clear(mif, which_bit);
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/* Update bit mask */
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clear_bit(which_bit, intr->bitmap_tohost);
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spin_unlock_irqrestore(&intr->spinlock, flags);
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return 0;
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error:
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SCSC_TAG_ERR(MIF, "Error unregistering irq\n");
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return -EIO;
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}
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int mifintrbit_alloc_fromhost(struct mifintrbit *intr, enum scsc_mif_abs_target target)
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{
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unsigned long flags;
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int which_bit = 0;
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unsigned long *p;
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spin_lock_irqsave(&intr->spinlock, flags);
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if (target == SCSC_MIF_ABS_TARGET_R4)
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p = intr->bitmap_fromhost_r4;
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else if (target == SCSC_MIF_ABS_TARGET_M4)
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p = intr->bitmap_fromhost_m4;
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else
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goto error;
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/* Search for free slots */
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which_bit = find_first_zero_bit(p, MIFINTRBIT_NUM_INT);
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if (which_bit == MIFINTRBIT_NUM_INT)
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goto error;
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/* Update bit mask */
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set_bit(which_bit, p);
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spin_unlock_irqrestore(&intr->spinlock, flags);
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return which_bit;
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error:
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spin_unlock_irqrestore(&intr->spinlock, flags);
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SCSC_TAG_ERR(MIF, "Error allocating bit %d on %s\n",
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which_bit, target ? "M4" : "R4");
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return -EIO;
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}
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int mifintrbit_free_fromhost(struct mifintrbit *intr, int which_bit, enum scsc_mif_abs_target target)
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{
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unsigned long flags;
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unsigned long *p;
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spin_lock_irqsave(&intr->spinlock, flags);
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if (which_bit >= MIFINTRBIT_NUM_INT)
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goto error;
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if (target == SCSC_MIF_ABS_TARGET_R4)
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p = intr->bitmap_fromhost_r4;
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else if (target == SCSC_MIF_ABS_TARGET_M4)
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p = intr->bitmap_fromhost_m4;
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else
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goto error;
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/* Clear bit mask */
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clear_bit(which_bit, p);
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spin_unlock_irqrestore(&intr->spinlock, flags);
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return 0;
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error:
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spin_unlock_irqrestore(&intr->spinlock, flags);
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SCSC_TAG_ERR(MIF, "Error freeing bit %d on %s\n",
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which_bit, target ? "M4" : "R4");
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return -EIO;
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}
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/* core API */
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void mifintrbit_deinit(struct mifintrbit *intr)
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{
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unsigned long flags;
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int i;
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spin_lock_irqsave(&intr->spinlock, flags);
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/* Set all handlers to default before unregistering the handler */
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for (i = 0; i < MIFINTRBIT_NUM_INT; i++)
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intr->mifintrbit_irq_handler[i] = mifintrbit_default_handler;
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intr->mif->irq_unreg_handler(intr->mif);
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spin_unlock_irqrestore(&intr->spinlock, flags);
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}
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void mifintrbit_init(struct mifintrbit *intr, struct scsc_mif_abs *mif)
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{
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int i;
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spin_lock_init(&intr->spinlock);
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/* Set all handlersd to default before hooking the hardware interrupt */
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for (i = 0; i < MIFINTRBIT_NUM_INT; i++)
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intr->mifintrbit_irq_handler[i] = mifintrbit_default_handler;
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/* reset bitmaps */
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bitmap_zero(intr->bitmap_tohost, MIFINTRBIT_NUM_INT);
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bitmap_zero(intr->bitmap_fromhost_r4, MIFINTRBIT_NUM_INT);
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bitmap_zero(intr->bitmap_fromhost_m4, MIFINTRBIT_NUM_INT);
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/**
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* Pre-allocate/reserve MIF interrupt bits 0 in both
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* .._fromhost_r4 and .._fromhost_m4 interrupt bits.
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*
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* These bits are used for purpose of forcing Panics from
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* either MX manager or GDB monitor channels.
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*/
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set_bit(MIFINTRBIT_RESERVED_PANIC_R4, intr->bitmap_fromhost_r4);
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set_bit(MIFINTRBIT_RESERVED_PANIC_M4, intr->bitmap_fromhost_m4);
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/* register isr with mif abstraction */
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mif->irq_reg_handler(mif, mifiintrman_isr, (void *)intr);
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/* cache mif */
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intr->mif = mif;
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}
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