mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
397
drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c
Normal file
397
drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c
Normal file
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/* $Date: 2005/10/24 23:18:13 $ $RCSfile: mv88e1xxx.c,v $ $Revision: 1.49 $ */
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#include "common.h"
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#include "mv88e1xxx.h"
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#include "cphy.h"
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#include "elmer0.h"
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/* MV88E1XXX MDI crossover register values */
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#define CROSSOVER_MDI 0
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#define CROSSOVER_MDIX 1
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#define CROSSOVER_AUTO 3
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#define INTR_ENABLE_MASK 0x6CA0
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/*
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* Set the bits given by 'bitval' in PHY register 'reg'.
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*/
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static void mdio_set_bit(struct cphy *cphy, int reg, u32 bitval)
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{
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u32 val;
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(void) simple_mdio_read(cphy, reg, &val);
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(void) simple_mdio_write(cphy, reg, val | bitval);
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}
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/*
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* Clear the bits given by 'bitval' in PHY register 'reg'.
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*/
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static void mdio_clear_bit(struct cphy *cphy, int reg, u32 bitval)
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{
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u32 val;
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(void) simple_mdio_read(cphy, reg, &val);
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(void) simple_mdio_write(cphy, reg, val & ~bitval);
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}
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/*
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* NAME: phy_reset
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*
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* DESC: Reset the given PHY's port. NOTE: This is not a global
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* chip reset.
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*
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* PARAMS: cphy - Pointer to PHY instance data.
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*
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* RETURN: 0 - Successful reset.
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* -1 - Timeout.
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*/
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static int mv88e1xxx_reset(struct cphy *cphy, int wait)
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{
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u32 ctl;
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int time_out = 1000;
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mdio_set_bit(cphy, MII_BMCR, BMCR_RESET);
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do {
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(void) simple_mdio_read(cphy, MII_BMCR, &ctl);
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ctl &= BMCR_RESET;
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if (ctl)
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udelay(1);
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} while (ctl && --time_out);
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return ctl ? -1 : 0;
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}
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static int mv88e1xxx_interrupt_enable(struct cphy *cphy)
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{
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/* Enable PHY interrupts. */
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(void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER,
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INTR_ENABLE_MASK);
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/* Enable Marvell interrupts through Elmer0. */
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if (t1_is_asic(cphy->adapter)) {
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u32 elmer;
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t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
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elmer |= ELMER0_GP_BIT1;
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if (is_T2(cphy->adapter))
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elmer |= ELMER0_GP_BIT2 | ELMER0_GP_BIT3 | ELMER0_GP_BIT4;
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t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
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}
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return 0;
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}
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static int mv88e1xxx_interrupt_disable(struct cphy *cphy)
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{
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/* Disable all phy interrupts. */
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(void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, 0);
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/* Disable Marvell interrupts through Elmer0. */
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if (t1_is_asic(cphy->adapter)) {
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u32 elmer;
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t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
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elmer &= ~ELMER0_GP_BIT1;
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if (is_T2(cphy->adapter))
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elmer &= ~(ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4);
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t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
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}
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return 0;
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}
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static int mv88e1xxx_interrupt_clear(struct cphy *cphy)
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{
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u32 elmer;
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/* Clear PHY interrupts by reading the register. */
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(void) simple_mdio_read(cphy,
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MV88E1XXX_INTERRUPT_STATUS_REGISTER, &elmer);
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/* Clear Marvell interrupts through Elmer0. */
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if (t1_is_asic(cphy->adapter)) {
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t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);
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elmer |= ELMER0_GP_BIT1;
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if (is_T2(cphy->adapter))
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elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4;
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t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
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}
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return 0;
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}
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/*
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* Set the PHY speed and duplex. This also disables auto-negotiation, except
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* for 1Gb/s, where auto-negotiation is mandatory.
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*/
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static int mv88e1xxx_set_speed_duplex(struct cphy *phy, int speed, int duplex)
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{
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u32 ctl;
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(void) simple_mdio_read(phy, MII_BMCR, &ctl);
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if (speed >= 0) {
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ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
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if (speed == SPEED_100)
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ctl |= BMCR_SPEED100;
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else if (speed == SPEED_1000)
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ctl |= BMCR_SPEED1000;
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}
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if (duplex >= 0) {
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ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE);
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if (duplex == DUPLEX_FULL)
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ctl |= BMCR_FULLDPLX;
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}
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if (ctl & BMCR_SPEED1000) /* auto-negotiation required for 1Gb/s */
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ctl |= BMCR_ANENABLE;
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(void) simple_mdio_write(phy, MII_BMCR, ctl);
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return 0;
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}
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static int mv88e1xxx_crossover_set(struct cphy *cphy, int crossover)
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{
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u32 data32;
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(void) simple_mdio_read(cphy,
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MV88E1XXX_SPECIFIC_CNTRL_REGISTER, &data32);
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data32 &= ~V_PSCR_MDI_XOVER_MODE(M_PSCR_MDI_XOVER_MODE);
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data32 |= V_PSCR_MDI_XOVER_MODE(crossover);
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(void) simple_mdio_write(cphy,
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MV88E1XXX_SPECIFIC_CNTRL_REGISTER, data32);
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return 0;
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}
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static int mv88e1xxx_autoneg_enable(struct cphy *cphy)
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{
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u32 ctl;
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(void) mv88e1xxx_crossover_set(cphy, CROSSOVER_AUTO);
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(void) simple_mdio_read(cphy, MII_BMCR, &ctl);
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/* restart autoneg for change to take effect */
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ctl |= BMCR_ANENABLE | BMCR_ANRESTART;
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(void) simple_mdio_write(cphy, MII_BMCR, ctl);
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return 0;
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}
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static int mv88e1xxx_autoneg_disable(struct cphy *cphy)
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{
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u32 ctl;
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/*
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* Crossover *must* be set to manual in order to disable auto-neg.
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* The Alaska FAQs document highlights this point.
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*/
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(void) mv88e1xxx_crossover_set(cphy, CROSSOVER_MDI);
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/*
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* Must include autoneg reset when disabling auto-neg. This
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* is described in the Alaska FAQ document.
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*/
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(void) simple_mdio_read(cphy, MII_BMCR, &ctl);
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ctl &= ~BMCR_ANENABLE;
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(void) simple_mdio_write(cphy, MII_BMCR, ctl | BMCR_ANRESTART);
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return 0;
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}
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static int mv88e1xxx_autoneg_restart(struct cphy *cphy)
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{
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mdio_set_bit(cphy, MII_BMCR, BMCR_ANRESTART);
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return 0;
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}
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static int mv88e1xxx_advertise(struct cphy *phy, unsigned int advertise_map)
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{
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u32 val = 0;
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if (advertise_map &
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(ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
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(void) simple_mdio_read(phy, MII_GBCR, &val);
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val &= ~(GBCR_ADV_1000HALF | GBCR_ADV_1000FULL);
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if (advertise_map & ADVERTISED_1000baseT_Half)
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val |= GBCR_ADV_1000HALF;
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if (advertise_map & ADVERTISED_1000baseT_Full)
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val |= GBCR_ADV_1000FULL;
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}
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(void) simple_mdio_write(phy, MII_GBCR, val);
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val = 1;
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if (advertise_map & ADVERTISED_10baseT_Half)
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val |= ADVERTISE_10HALF;
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if (advertise_map & ADVERTISED_10baseT_Full)
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val |= ADVERTISE_10FULL;
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if (advertise_map & ADVERTISED_100baseT_Half)
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val |= ADVERTISE_100HALF;
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if (advertise_map & ADVERTISED_100baseT_Full)
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val |= ADVERTISE_100FULL;
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if (advertise_map & ADVERTISED_PAUSE)
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val |= ADVERTISE_PAUSE;
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if (advertise_map & ADVERTISED_ASYM_PAUSE)
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val |= ADVERTISE_PAUSE_ASYM;
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(void) simple_mdio_write(phy, MII_ADVERTISE, val);
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return 0;
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}
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static int mv88e1xxx_set_loopback(struct cphy *cphy, int on)
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{
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if (on)
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mdio_set_bit(cphy, MII_BMCR, BMCR_LOOPBACK);
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else
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mdio_clear_bit(cphy, MII_BMCR, BMCR_LOOPBACK);
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return 0;
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}
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static int mv88e1xxx_get_link_status(struct cphy *cphy, int *link_ok,
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int *speed, int *duplex, int *fc)
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{
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u32 status;
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int sp = -1, dplx = -1, pause = 0;
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(void) simple_mdio_read(cphy,
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MV88E1XXX_SPECIFIC_STATUS_REGISTER, &status);
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if ((status & V_PSSR_STATUS_RESOLVED) != 0) {
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if (status & V_PSSR_RX_PAUSE)
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pause |= PAUSE_RX;
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if (status & V_PSSR_TX_PAUSE)
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pause |= PAUSE_TX;
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dplx = (status & V_PSSR_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
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sp = G_PSSR_SPEED(status);
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if (sp == 0)
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sp = SPEED_10;
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else if (sp == 1)
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sp = SPEED_100;
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else
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sp = SPEED_1000;
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}
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if (link_ok)
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*link_ok = (status & V_PSSR_LINK) != 0;
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if (speed)
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*speed = sp;
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if (duplex)
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*duplex = dplx;
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if (fc)
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*fc = pause;
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return 0;
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}
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static int mv88e1xxx_downshift_set(struct cphy *cphy, int downshift_enable)
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{
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u32 val;
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(void) simple_mdio_read(cphy,
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MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, &val);
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/*
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* Set the downshift counter to 2 so we try to establish Gb link
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* twice before downshifting.
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*/
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val &= ~(V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(M_DOWNSHIFT_CNT));
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if (downshift_enable)
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val |= V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(2);
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(void) simple_mdio_write(cphy,
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MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, val);
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return 0;
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}
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static int mv88e1xxx_interrupt_handler(struct cphy *cphy)
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{
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int cphy_cause = 0;
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u32 status;
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/*
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* Loop until cause reads zero. Need to handle bouncing interrupts.
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*/
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while (1) {
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u32 cause;
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(void) simple_mdio_read(cphy,
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MV88E1XXX_INTERRUPT_STATUS_REGISTER,
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&cause);
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cause &= INTR_ENABLE_MASK;
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if (!cause)
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break;
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if (cause & MV88E1XXX_INTR_LINK_CHNG) {
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(void) simple_mdio_read(cphy,
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MV88E1XXX_SPECIFIC_STATUS_REGISTER, &status);
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if (status & MV88E1XXX_INTR_LINK_CHNG)
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cphy->state |= PHY_LINK_UP;
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else {
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cphy->state &= ~PHY_LINK_UP;
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if (cphy->state & PHY_AUTONEG_EN)
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cphy->state &= ~PHY_AUTONEG_RDY;
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cphy_cause |= cphy_cause_link_change;
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}
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}
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if (cause & MV88E1XXX_INTR_AUTONEG_DONE)
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cphy->state |= PHY_AUTONEG_RDY;
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if ((cphy->state & (PHY_LINK_UP | PHY_AUTONEG_RDY)) ==
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(PHY_LINK_UP | PHY_AUTONEG_RDY))
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cphy_cause |= cphy_cause_link_change;
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}
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return cphy_cause;
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}
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static void mv88e1xxx_destroy(struct cphy *cphy)
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{
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kfree(cphy);
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}
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static struct cphy_ops mv88e1xxx_ops = {
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.destroy = mv88e1xxx_destroy,
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.reset = mv88e1xxx_reset,
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.interrupt_enable = mv88e1xxx_interrupt_enable,
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.interrupt_disable = mv88e1xxx_interrupt_disable,
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.interrupt_clear = mv88e1xxx_interrupt_clear,
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.interrupt_handler = mv88e1xxx_interrupt_handler,
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.autoneg_enable = mv88e1xxx_autoneg_enable,
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.autoneg_disable = mv88e1xxx_autoneg_disable,
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.autoneg_restart = mv88e1xxx_autoneg_restart,
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.advertise = mv88e1xxx_advertise,
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.set_loopback = mv88e1xxx_set_loopback,
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.set_speed_duplex = mv88e1xxx_set_speed_duplex,
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.get_link_status = mv88e1xxx_get_link_status,
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};
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static struct cphy *mv88e1xxx_phy_create(struct net_device *dev, int phy_addr,
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const struct mdio_ops *mdio_ops)
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{
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struct adapter *adapter = netdev_priv(dev);
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struct cphy *cphy = kzalloc(sizeof(*cphy), GFP_KERNEL);
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if (!cphy)
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return NULL;
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cphy_init(cphy, dev, phy_addr, &mv88e1xxx_ops, mdio_ops);
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/* Configure particular PHY's to run in a different mode. */
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if ((board_info(adapter)->caps & SUPPORTED_TP) &&
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board_info(adapter)->chip_phy == CHBT_PHY_88E1111) {
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/*
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* Configure the PHY transmitter as class A to reduce EMI.
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*/
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(void) simple_mdio_write(cphy,
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MV88E1XXX_EXTENDED_ADDR_REGISTER, 0xB);
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(void) simple_mdio_write(cphy,
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MV88E1XXX_EXTENDED_REGISTER, 0x8004);
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}
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(void) mv88e1xxx_downshift_set(cphy, 1); /* Enable downshift */
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/* LED */
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if (is_T2(adapter)) {
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(void) simple_mdio_write(cphy,
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MV88E1XXX_LED_CONTROL_REGISTER, 0x1);
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}
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return cphy;
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}
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static int mv88e1xxx_phy_reset(adapter_t* adapter)
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{
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return 0;
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}
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const struct gphy t1_mv88e1xxx_ops = {
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.create = mv88e1xxx_phy_create,
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.reset = mv88e1xxx_phy_reset
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};
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