mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 08:08:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
39
drivers/net/ethernet/faraday/Kconfig
Normal file
39
drivers/net/ethernet/faraday/Kconfig
Normal file
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@ -0,0 +1,39 @@
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#
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# Faraday device configuration
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#
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config NET_VENDOR_FARADAY
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bool "Faraday devices"
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default y
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depends on ARM
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---help---
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If you have a network (Ethernet) card belonging to this class, say Y
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and read the Ethernet-HOWTO, available from
|
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<http://www.tldp.org/docs.html#howto>.
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Note that the answer to this question doesn't directly affect the
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kernel: saying N will just cause the configurator to skip all
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the questions about Faraday cards. If you say Y, you will be asked for
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your specific card in the following questions.
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if NET_VENDOR_FARADAY
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config FTMAC100
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tristate "Faraday FTMAC100 10/100 Ethernet support"
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depends on ARM
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select MII
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---help---
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This driver supports the FTMAC100 10/100 Ethernet controller
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from Faraday. It is used on Faraday A320, Andes AG101 and some
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other ARM/NDS32 SoC's.
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config FTGMAC100
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tristate "Faraday FTGMAC100 Gigabit Ethernet support"
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depends on ARM
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select PHYLIB
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---help---
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This driver supports the FTGMAC100 Gigabit Ethernet controller
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from Faraday. It is used on Faraday A369, Andes AG102 and some
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other ARM/NDS32 SoC's.
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endif # NET_VENDOR_FARADAY
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6
drivers/net/ethernet/faraday/Makefile
Normal file
6
drivers/net/ethernet/faraday/Makefile
Normal file
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@ -0,0 +1,6 @@
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#
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# Makefile for the Faraday device drivers.
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#
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obj-$(CONFIG_FTGMAC100) += ftgmac100.o
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obj-$(CONFIG_FTMAC100) += ftmac100.o
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1346
drivers/net/ethernet/faraday/ftgmac100.c
Normal file
1346
drivers/net/ethernet/faraday/ftgmac100.c
Normal file
File diff suppressed because it is too large
Load diff
246
drivers/net/ethernet/faraday/ftgmac100.h
Normal file
246
drivers/net/ethernet/faraday/ftgmac100.h
Normal file
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@ -0,0 +1,246 @@
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/*
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* Faraday FTGMAC100 Gigabit Ethernet
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*
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* (C) Copyright 2009-2011 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __FTGMAC100_H
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#define __FTGMAC100_H
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#define FTGMAC100_OFFSET_ISR 0x00
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#define FTGMAC100_OFFSET_IER 0x04
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#define FTGMAC100_OFFSET_MAC_MADR 0x08
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#define FTGMAC100_OFFSET_MAC_LADR 0x0c
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#define FTGMAC100_OFFSET_MAHT0 0x10
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#define FTGMAC100_OFFSET_MAHT1 0x14
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#define FTGMAC100_OFFSET_NPTXPD 0x18
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#define FTGMAC100_OFFSET_RXPD 0x1c
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#define FTGMAC100_OFFSET_NPTXR_BADR 0x20
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#define FTGMAC100_OFFSET_RXR_BADR 0x24
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#define FTGMAC100_OFFSET_HPTXPD 0x28
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#define FTGMAC100_OFFSET_HPTXR_BADR 0x2c
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#define FTGMAC100_OFFSET_ITC 0x30
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#define FTGMAC100_OFFSET_APTC 0x34
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#define FTGMAC100_OFFSET_DBLAC 0x38
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#define FTGMAC100_OFFSET_DMAFIFOS 0x3c
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#define FTGMAC100_OFFSET_REVR 0x40
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#define FTGMAC100_OFFSET_FEAR 0x44
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#define FTGMAC100_OFFSET_TPAFCR 0x48
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#define FTGMAC100_OFFSET_RBSR 0x4c
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#define FTGMAC100_OFFSET_MACCR 0x50
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#define FTGMAC100_OFFSET_MACSR 0x54
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#define FTGMAC100_OFFSET_TM 0x58
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#define FTGMAC100_OFFSET_PHYCR 0x60
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#define FTGMAC100_OFFSET_PHYDATA 0x64
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#define FTGMAC100_OFFSET_FCR 0x68
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#define FTGMAC100_OFFSET_BPR 0x6c
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#define FTGMAC100_OFFSET_WOLCR 0x70
|
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#define FTGMAC100_OFFSET_WOLSR 0x74
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#define FTGMAC100_OFFSET_WFCRC 0x78
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#define FTGMAC100_OFFSET_WFBM1 0x80
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#define FTGMAC100_OFFSET_WFBM2 0x84
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#define FTGMAC100_OFFSET_WFBM3 0x88
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#define FTGMAC100_OFFSET_WFBM4 0x8c
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#define FTGMAC100_OFFSET_NPTXR_PTR 0x90
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#define FTGMAC100_OFFSET_HPTXR_PTR 0x94
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#define FTGMAC100_OFFSET_RXR_PTR 0x98
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#define FTGMAC100_OFFSET_TX 0xa0
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#define FTGMAC100_OFFSET_TX_MCOL_SCOL 0xa4
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#define FTGMAC100_OFFSET_TX_ECOL_FAIL 0xa8
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#define FTGMAC100_OFFSET_TX_LCOL_UND 0xac
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#define FTGMAC100_OFFSET_RX 0xb0
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#define FTGMAC100_OFFSET_RX_BC 0xb4
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#define FTGMAC100_OFFSET_RX_MC 0xb8
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#define FTGMAC100_OFFSET_RX_PF_AEP 0xbc
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#define FTGMAC100_OFFSET_RX_RUNT 0xc0
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#define FTGMAC100_OFFSET_RX_CRCER_FTL 0xc4
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#define FTGMAC100_OFFSET_RX_COL_LOST 0xc8
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/*
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* Interrupt status register & interrupt enable register
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*/
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#define FTGMAC100_INT_RPKT_BUF (1 << 0)
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#define FTGMAC100_INT_RPKT_FIFO (1 << 1)
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#define FTGMAC100_INT_NO_RXBUF (1 << 2)
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#define FTGMAC100_INT_RPKT_LOST (1 << 3)
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#define FTGMAC100_INT_XPKT_ETH (1 << 4)
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#define FTGMAC100_INT_XPKT_FIFO (1 << 5)
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#define FTGMAC100_INT_NO_NPTXBUF (1 << 6)
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#define FTGMAC100_INT_XPKT_LOST (1 << 7)
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#define FTGMAC100_INT_AHB_ERR (1 << 8)
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#define FTGMAC100_INT_PHYSTS_CHG (1 << 9)
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#define FTGMAC100_INT_NO_HPTXBUF (1 << 10)
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/*
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* Interrupt timer control register
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*/
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#define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0)
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#define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4)
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#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7)
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#define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8)
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#define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12)
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#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15)
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/*
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* Automatic polling timer control register
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*/
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#define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
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#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
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#define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
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#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
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/*
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* DMA burst length and arbitration control register
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*/
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#define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0)
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#define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3)
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#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6)
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#define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8)
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#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10)
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#define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12)
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#define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16)
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#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20)
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#define FTGMAC100_DBLAC_IFG_INC (1 << 23)
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/*
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* DMA FIFO status register
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*/
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#define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf)
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#define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf)
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#define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7)
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#define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf)
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#define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3)
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#define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf)
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#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26)
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#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27)
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#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28)
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#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29)
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#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30)
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#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31)
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/*
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* Receive buffer size register
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*/
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#define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff)
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/*
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* MAC control register
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*/
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#define FTGMAC100_MACCR_TXDMA_EN (1 << 0)
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#define FTGMAC100_MACCR_RXDMA_EN (1 << 1)
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#define FTGMAC100_MACCR_TXMAC_EN (1 << 2)
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#define FTGMAC100_MACCR_RXMAC_EN (1 << 3)
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#define FTGMAC100_MACCR_RM_VLAN (1 << 4)
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#define FTGMAC100_MACCR_HPTXR_EN (1 << 5)
|
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#define FTGMAC100_MACCR_LOOP_EN (1 << 6)
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#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7)
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#define FTGMAC100_MACCR_FULLDUP (1 << 8)
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#define FTGMAC100_MACCR_GIGA_MODE (1 << 9)
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#define FTGMAC100_MACCR_CRC_APD (1 << 10)
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#define FTGMAC100_MACCR_RX_RUNT (1 << 12)
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#define FTGMAC100_MACCR_JUMBO_LF (1 << 13)
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#define FTGMAC100_MACCR_RX_ALL (1 << 14)
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#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15)
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#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16)
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#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17)
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#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18)
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#define FTGMAC100_MACCR_FAST_MODE (1 << 19)
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#define FTGMAC100_MACCR_SW_RST (1 << 31)
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/*
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* PHY control register
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*/
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#define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f
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#define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f)
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#define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16)
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#define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21)
|
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#define FTGMAC100_PHYCR_MIIRD (1 << 26)
|
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#define FTGMAC100_PHYCR_MIIWR (1 << 27)
|
||||
|
||||
/*
|
||||
* PHY data register
|
||||
*/
|
||||
#define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff)
|
||||
#define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff)
|
||||
|
||||
/*
|
||||
* Transmit descriptor, aligned to 16 bytes
|
||||
*/
|
||||
struct ftgmac100_txdes {
|
||||
unsigned int txdes0;
|
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unsigned int txdes1;
|
||||
unsigned int txdes2; /* not used by HW */
|
||||
unsigned int txdes3; /* TXBUF_BADR */
|
||||
} __attribute__ ((aligned(16)));
|
||||
|
||||
#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
|
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#define FTGMAC100_TXDES0_EDOTR (1 << 15)
|
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#define FTGMAC100_TXDES0_CRC_ERR (1 << 19)
|
||||
#define FTGMAC100_TXDES0_LTS (1 << 28)
|
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#define FTGMAC100_TXDES0_FTS (1 << 29)
|
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#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31)
|
||||
|
||||
#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
|
||||
#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16)
|
||||
#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17)
|
||||
#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18)
|
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#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19)
|
||||
#define FTGMAC100_TXDES1_LLC (1 << 22)
|
||||
#define FTGMAC100_TXDES1_TX2FIC (1 << 30)
|
||||
#define FTGMAC100_TXDES1_TXIC (1 << 31)
|
||||
|
||||
/*
|
||||
* Receive descriptor, aligned to 16 bytes
|
||||
*/
|
||||
struct ftgmac100_rxdes {
|
||||
unsigned int rxdes0;
|
||||
unsigned int rxdes1;
|
||||
unsigned int rxdes2; /* not used by HW */
|
||||
unsigned int rxdes3; /* RXBUF_BADR */
|
||||
} __attribute__ ((aligned(16)));
|
||||
|
||||
#define FTGMAC100_RXDES0_VDBC 0x3fff
|
||||
#define FTGMAC100_RXDES0_EDORR (1 << 15)
|
||||
#define FTGMAC100_RXDES0_MULTICAST (1 << 16)
|
||||
#define FTGMAC100_RXDES0_BROADCAST (1 << 17)
|
||||
#define FTGMAC100_RXDES0_RX_ERR (1 << 18)
|
||||
#define FTGMAC100_RXDES0_CRC_ERR (1 << 19)
|
||||
#define FTGMAC100_RXDES0_FTL (1 << 20)
|
||||
#define FTGMAC100_RXDES0_RUNT (1 << 21)
|
||||
#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22)
|
||||
#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23)
|
||||
#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24)
|
||||
#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25)
|
||||
#define FTGMAC100_RXDES0_LRS (1 << 28)
|
||||
#define FTGMAC100_RXDES0_FRS (1 << 29)
|
||||
#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31)
|
||||
|
||||
#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
|
||||
#define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20)
|
||||
#define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20)
|
||||
#define FTGMAC100_RXDES1_PROT_IP (0x1 << 20)
|
||||
#define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
|
||||
#define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
|
||||
#define FTGMAC100_RXDES1_LLC (1 << 22)
|
||||
#define FTGMAC100_RXDES1_DF (1 << 23)
|
||||
#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24)
|
||||
#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25)
|
||||
#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
|
||||
#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27)
|
||||
|
||||
#endif /* __FTGMAC100_H */
|
||||
1203
drivers/net/ethernet/faraday/ftmac100.c
Normal file
1203
drivers/net/ethernet/faraday/ftmac100.c
Normal file
File diff suppressed because it is too large
Load diff
180
drivers/net/ethernet/faraday/ftmac100.h
Normal file
180
drivers/net/ethernet/faraday/ftmac100.h
Normal file
|
|
@ -0,0 +1,180 @@
|
|||
/*
|
||||
* Faraday FTMAC100 10/100 Ethernet
|
||||
*
|
||||
* (C) Copyright 2009-2011 Faraday Technology
|
||||
* Po-Yu Chuang <ratbert@faraday-tech.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __FTMAC100_H
|
||||
#define __FTMAC100_H
|
||||
|
||||
#define FTMAC100_OFFSET_ISR 0x00
|
||||
#define FTMAC100_OFFSET_IMR 0x04
|
||||
#define FTMAC100_OFFSET_MAC_MADR 0x08
|
||||
#define FTMAC100_OFFSET_MAC_LADR 0x0c
|
||||
#define FTMAC100_OFFSET_MAHT0 0x10
|
||||
#define FTMAC100_OFFSET_MAHT1 0x14
|
||||
#define FTMAC100_OFFSET_TXPD 0x18
|
||||
#define FTMAC100_OFFSET_RXPD 0x1c
|
||||
#define FTMAC100_OFFSET_TXR_BADR 0x20
|
||||
#define FTMAC100_OFFSET_RXR_BADR 0x24
|
||||
#define FTMAC100_OFFSET_ITC 0x28
|
||||
#define FTMAC100_OFFSET_APTC 0x2c
|
||||
#define FTMAC100_OFFSET_DBLAC 0x30
|
||||
#define FTMAC100_OFFSET_MACCR 0x88
|
||||
#define FTMAC100_OFFSET_MACSR 0x8c
|
||||
#define FTMAC100_OFFSET_PHYCR 0x90
|
||||
#define FTMAC100_OFFSET_PHYWDATA 0x94
|
||||
#define FTMAC100_OFFSET_FCR 0x98
|
||||
#define FTMAC100_OFFSET_BPR 0x9c
|
||||
#define FTMAC100_OFFSET_TS 0xc4
|
||||
#define FTMAC100_OFFSET_DMAFIFOS 0xc8
|
||||
#define FTMAC100_OFFSET_TM 0xcc
|
||||
#define FTMAC100_OFFSET_TX_MCOL_SCOL 0xd4
|
||||
#define FTMAC100_OFFSET_RPF_AEP 0xd8
|
||||
#define FTMAC100_OFFSET_XM_PG 0xdc
|
||||
#define FTMAC100_OFFSET_RUNT_TLCC 0xe0
|
||||
#define FTMAC100_OFFSET_CRCER_FTL 0xe4
|
||||
#define FTMAC100_OFFSET_RLC_RCC 0xe8
|
||||
#define FTMAC100_OFFSET_BROC 0xec
|
||||
#define FTMAC100_OFFSET_MULCA 0xf0
|
||||
#define FTMAC100_OFFSET_RP 0xf4
|
||||
#define FTMAC100_OFFSET_XP 0xf8
|
||||
|
||||
/*
|
||||
* Interrupt status register & interrupt mask register
|
||||
*/
|
||||
#define FTMAC100_INT_RPKT_FINISH (1 << 0)
|
||||
#define FTMAC100_INT_NORXBUF (1 << 1)
|
||||
#define FTMAC100_INT_XPKT_FINISH (1 << 2)
|
||||
#define FTMAC100_INT_NOTXBUF (1 << 3)
|
||||
#define FTMAC100_INT_XPKT_OK (1 << 4)
|
||||
#define FTMAC100_INT_XPKT_LOST (1 << 5)
|
||||
#define FTMAC100_INT_RPKT_SAV (1 << 6)
|
||||
#define FTMAC100_INT_RPKT_LOST (1 << 7)
|
||||
#define FTMAC100_INT_AHB_ERR (1 << 8)
|
||||
#define FTMAC100_INT_PHYSTS_CHG (1 << 9)
|
||||
|
||||
/*
|
||||
* Interrupt timer control register
|
||||
*/
|
||||
#define FTMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0)
|
||||
#define FTMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4)
|
||||
#define FTMAC100_ITC_RXINT_TIME_SEL (1 << 7)
|
||||
#define FTMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8)
|
||||
#define FTMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12)
|
||||
#define FTMAC100_ITC_TXINT_TIME_SEL (1 << 15)
|
||||
|
||||
/*
|
||||
* Automatic polling timer control register
|
||||
*/
|
||||
#define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
|
||||
#define FTMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
|
||||
#define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
|
||||
#define FTMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
|
||||
|
||||
/*
|
||||
* DMA burst length and arbitration control register
|
||||
*/
|
||||
#define FTMAC100_DBLAC_INCR4_EN (1 << 0)
|
||||
#define FTMAC100_DBLAC_INCR8_EN (1 << 1)
|
||||
#define FTMAC100_DBLAC_INCR16_EN (1 << 2)
|
||||
#define FTMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 3)
|
||||
#define FTMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 6)
|
||||
#define FTMAC100_DBLAC_RX_THR_EN (1 << 9)
|
||||
|
||||
/*
|
||||
* MAC control register
|
||||
*/
|
||||
#define FTMAC100_MACCR_XDMA_EN (1 << 0)
|
||||
#define FTMAC100_MACCR_RDMA_EN (1 << 1)
|
||||
#define FTMAC100_MACCR_SW_RST (1 << 2)
|
||||
#define FTMAC100_MACCR_LOOP_EN (1 << 3)
|
||||
#define FTMAC100_MACCR_CRC_DIS (1 << 4)
|
||||
#define FTMAC100_MACCR_XMT_EN (1 << 5)
|
||||
#define FTMAC100_MACCR_ENRX_IN_HALFTX (1 << 6)
|
||||
#define FTMAC100_MACCR_RCV_EN (1 << 8)
|
||||
#define FTMAC100_MACCR_HT_MULTI_EN (1 << 9)
|
||||
#define FTMAC100_MACCR_RX_RUNT (1 << 10)
|
||||
#define FTMAC100_MACCR_RX_FTL (1 << 11)
|
||||
#define FTMAC100_MACCR_RCV_ALL (1 << 12)
|
||||
#define FTMAC100_MACCR_CRC_APD (1 << 14)
|
||||
#define FTMAC100_MACCR_FULLDUP (1 << 15)
|
||||
#define FTMAC100_MACCR_RX_MULTIPKT (1 << 16)
|
||||
#define FTMAC100_MACCR_RX_BROADPKT (1 << 17)
|
||||
|
||||
/*
|
||||
* PHY control register
|
||||
*/
|
||||
#define FTMAC100_PHYCR_MIIRDATA 0xffff
|
||||
#define FTMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16)
|
||||
#define FTMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21)
|
||||
#define FTMAC100_PHYCR_MIIRD (1 << 26)
|
||||
#define FTMAC100_PHYCR_MIIWR (1 << 27)
|
||||
|
||||
/*
|
||||
* PHY write data register
|
||||
*/
|
||||
#define FTMAC100_PHYWDATA_MIIWDATA(x) ((x) & 0xffff)
|
||||
|
||||
/*
|
||||
* Transmit descriptor, aligned to 16 bytes
|
||||
*/
|
||||
struct ftmac100_txdes {
|
||||
unsigned int txdes0;
|
||||
unsigned int txdes1;
|
||||
unsigned int txdes2; /* TXBUF_BADR */
|
||||
unsigned int txdes3; /* not used by HW */
|
||||
} __attribute__ ((aligned(16)));
|
||||
|
||||
#define FTMAC100_TXDES0_TXPKT_LATECOL (1 << 0)
|
||||
#define FTMAC100_TXDES0_TXPKT_EXSCOL (1 << 1)
|
||||
#define FTMAC100_TXDES0_TXDMA_OWN (1 << 31)
|
||||
|
||||
#define FTMAC100_TXDES1_TXBUF_SIZE(x) ((x) & 0x7ff)
|
||||
#define FTMAC100_TXDES1_LTS (1 << 27)
|
||||
#define FTMAC100_TXDES1_FTS (1 << 28)
|
||||
#define FTMAC100_TXDES1_TX2FIC (1 << 29)
|
||||
#define FTMAC100_TXDES1_TXIC (1 << 30)
|
||||
#define FTMAC100_TXDES1_EDOTR (1 << 31)
|
||||
|
||||
/*
|
||||
* Receive descriptor, aligned to 16 bytes
|
||||
*/
|
||||
struct ftmac100_rxdes {
|
||||
unsigned int rxdes0;
|
||||
unsigned int rxdes1;
|
||||
unsigned int rxdes2; /* RXBUF_BADR */
|
||||
unsigned int rxdes3; /* not used by HW */
|
||||
} __attribute__ ((aligned(16)));
|
||||
|
||||
#define FTMAC100_RXDES0_RFL 0x7ff
|
||||
#define FTMAC100_RXDES0_MULTICAST (1 << 16)
|
||||
#define FTMAC100_RXDES0_BROADCAST (1 << 17)
|
||||
#define FTMAC100_RXDES0_RX_ERR (1 << 18)
|
||||
#define FTMAC100_RXDES0_CRC_ERR (1 << 19)
|
||||
#define FTMAC100_RXDES0_FTL (1 << 20)
|
||||
#define FTMAC100_RXDES0_RUNT (1 << 21)
|
||||
#define FTMAC100_RXDES0_RX_ODD_NB (1 << 22)
|
||||
#define FTMAC100_RXDES0_LRS (1 << 28)
|
||||
#define FTMAC100_RXDES0_FRS (1 << 29)
|
||||
#define FTMAC100_RXDES0_RXDMA_OWN (1 << 31)
|
||||
|
||||
#define FTMAC100_RXDES1_RXBUF_SIZE(x) ((x) & 0x7ff)
|
||||
#define FTMAC100_RXDES1_EDORR (1 << 31)
|
||||
|
||||
#endif /* __FTMAC100_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue