mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
298
drivers/net/ethernet/intel/ixgbevf/defines.h
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298
drivers/net/ethernet/intel/ixgbevf/defines.h
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/*******************************************************************************
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Intel 82599 Virtual Function driver
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Copyright(c) 1999 - 2012 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _IXGBEVF_DEFINES_H_
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#define _IXGBEVF_DEFINES_H_
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/* Device IDs */
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#define IXGBE_DEV_ID_82599_VF 0x10ED
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#define IXGBE_DEV_ID_X540_VF 0x1515
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#define IXGBE_VF_IRQ_CLEAR_MASK 7
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#define IXGBE_VF_MAX_TX_QUEUES 8
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#define IXGBE_VF_MAX_RX_QUEUES 8
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/* DCB define */
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#define IXGBE_VF_MAX_TRAFFIC_CLASS 8
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/* Link speed */
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typedef u32 ixgbe_link_speed;
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#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
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#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
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#define IXGBE_LINK_SPEED_100_FULL 0x0008
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#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
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#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
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#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
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#define IXGBE_LINKS_UP 0x40000000
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#define IXGBE_LINKS_SPEED_82599 0x30000000
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#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
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#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
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#define IXGBE_LINKS_SPEED_100_82599 0x10000000
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/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
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#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
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#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
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#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
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/* Interrupt Vector Allocation Registers */
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#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
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#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
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/* Receive Config masks */
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#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
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#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
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#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
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#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
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#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */
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#define IXGBE_RXDCTL_RLPML_EN 0x00008000
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/* DCA Control */
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#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
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/* PSRTYPE bit definitions */
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#define IXGBE_PSRTYPE_TCPHDR 0x00000010
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#define IXGBE_PSRTYPE_UDPHDR 0x00000020
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#define IXGBE_PSRTYPE_IPV4HDR 0x00000100
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#define IXGBE_PSRTYPE_IPV6HDR 0x00000200
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#define IXGBE_PSRTYPE_L2HDR 0x00001000
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/* SRRCTL bit definitions */
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#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
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#define IXGBE_SRRCTL_RDMTS_SHIFT 22
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#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
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#define IXGBE_SRRCTL_DROP_EN 0x10000000
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#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
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#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
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#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
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#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
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#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
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#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
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#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
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#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
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/* Receive Descriptor bit definitions */
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#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
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#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
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#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */
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#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
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#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
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#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
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#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
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#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
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#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
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#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
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#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
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#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
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#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
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#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
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#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
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#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
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#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
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#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
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#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
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#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
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#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
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#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
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#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
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#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
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#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
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#define IXGBE_RXDADV_ERR_MASK 0xFFF00000 /* RDESC.ERRORS mask */
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#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
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#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
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#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
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#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
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#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
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#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
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#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
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#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
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#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
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#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
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#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
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#define IXGBE_RXD_PRI_SHIFT 13
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#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
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#define IXGBE_RXD_CFI_SHIFT 12
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#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
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#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
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#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */
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#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */
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#define IXGBE_RXDADV_STAT_MASK 0x000FFFFF /* Stat/NEXTP: bit 0-19 */
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#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */
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#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */
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#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
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#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */
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#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
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#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */
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#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
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#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
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#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
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#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
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#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
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#define IXGBE_RXDADV_RSCCNT_SHIFT 17
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#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
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#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
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#define IXGBE_RXDADV_SPH 0x8000
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#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
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IXGBE_RXD_ERR_CE | \
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IXGBE_RXD_ERR_LE | \
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IXGBE_RXD_ERR_PE | \
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IXGBE_RXD_ERR_OSE | \
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IXGBE_RXD_ERR_USE)
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#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
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IXGBE_RXDADV_ERR_CE | \
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IXGBE_RXDADV_ERR_LE | \
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IXGBE_RXDADV_ERR_PE | \
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IXGBE_RXDADV_ERR_OSE | \
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IXGBE_RXDADV_ERR_USE)
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#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
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#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
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#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
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#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
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#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
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#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
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#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
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#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
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#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
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#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS)
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/* Transmit Descriptor - Advanced */
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union ixgbe_adv_tx_desc {
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struct {
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__le64 buffer_addr; /* Address of descriptor's data buf */
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__le32 cmd_type_len;
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__le32 olinfo_status;
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} read;
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struct {
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__le64 rsvd; /* Reserved */
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__le32 nxtseq_seed;
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__le32 status;
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} wb;
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};
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/* Receive Descriptor - Advanced */
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union ixgbe_adv_rx_desc {
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struct {
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__le64 pkt_addr; /* Packet buffer address */
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__le64 hdr_addr; /* Header buffer address */
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} read;
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struct {
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struct {
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union {
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__le32 data;
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struct {
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__le16 pkt_info; /* RSS, Pkt type */
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__le16 hdr_info; /* Splithdr, hdrlen */
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} hs_rss;
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} lo_dword;
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union {
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__le32 rss; /* RSS Hash */
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struct {
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__le16 ip_id; /* IP id */
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__le16 csum; /* Packet Checksum */
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} csum_ip;
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} hi_dword;
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} lower;
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struct {
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__le32 status_error; /* ext status/error */
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__le16 length; /* Packet length */
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__le16 vlan; /* VLAN tag */
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} upper;
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} wb; /* writeback */
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};
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/* Context descriptors */
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struct ixgbe_adv_tx_context_desc {
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__le32 vlan_macip_lens;
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__le32 seqnum_seed;
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__le32 type_tucmd_mlhl;
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__le32 mss_l4len_idx;
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};
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/* Adv Transmit Descriptor Config Masks */
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#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
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#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
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#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
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#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
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#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
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#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
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#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
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#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
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#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
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#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
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#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
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#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
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#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
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#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
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#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
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#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
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#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */
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#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
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#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
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IXGBE_ADVTXD_POPTS_SHIFT)
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#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
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IXGBE_ADVTXD_POPTS_SHIFT)
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#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
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#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
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#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
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#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
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#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
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/* Interrupt register bitmasks */
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#define IXGBE_EITR_CNT_WDIS 0x80000000
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#define IXGBE_MAX_EITR 0x00000FF8
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#define IXGBE_MIN_EITR 8
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/* Error Codes */
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#define IXGBE_ERR_INVALID_MAC_ADDR -1
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#define IXGBE_ERR_RESET_FAILED -2
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#define IXGBE_ERR_INVALID_ARGUMENT -3
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/* Transmit Config masks */
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#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue */
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#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */
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#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
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#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* Rx Desc enable */
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#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* Rx Desc header ena */
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#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* Rx Desc payload ena */
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#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* Rx rd Desc Relax Order */
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#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */
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#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */
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#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
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#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
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#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */
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#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
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#endif /* _IXGBEVF_DEFINES_H_ */
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