mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 09:22:44 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
15
drivers/net/ethernet/qlogic/qlcnic/Makefile
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15
drivers/net/ethernet/qlogic/qlcnic/Makefile
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@ -0,0 +1,15 @@
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#
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# Makefile for Qlogic 1G/10G Ethernet Driver for CNA devices
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#
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obj-$(CONFIG_QLCNIC) := qlcnic.o
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qlcnic-y := qlcnic_hw.o qlcnic_main.o qlcnic_init.o \
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qlcnic_ethtool.o qlcnic_ctx.o qlcnic_io.o \
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qlcnic_sysfs.o qlcnic_minidump.o qlcnic_83xx_hw.o \
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qlcnic_83xx_init.o qlcnic_83xx_vnic.o \
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qlcnic_sriov_common.o
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qlcnic-$(CONFIG_QLCNIC_SRIOV) += qlcnic_sriov_pf.o
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qlcnic-$(CONFIG_QLCNIC_DCB) += qlcnic_dcb.o
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2395
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
Normal file
2395
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
Normal file
File diff suppressed because it is too large
Load diff
4165
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
Normal file
4165
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
Normal file
File diff suppressed because it is too large
Load diff
661
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h
Normal file
661
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h
Normal file
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@ -0,0 +1,661 @@
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/*
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* QLogic qlcnic NIC Driver
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* Copyright (c) 2009-2013 QLogic Corporation
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*
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* See LICENSE.qlcnic for copyright and licensing details.
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*/
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#ifndef __QLCNIC_83XX_HW_H
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#define __QLCNIC_83XX_HW_H
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#include <linux/types.h>
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#include <linux/etherdevice.h>
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#include "qlcnic_hw.h"
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#define QLCNIC_83XX_BAR0_LENGTH 0x4000
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/* Directly mapped registers */
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#define QLC_83XX_CRB_WIN_BASE 0x3800
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#define QLC_83XX_CRB_WIN_FUNC(f) (QLC_83XX_CRB_WIN_BASE+((f)*4))
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#define QLC_83XX_SEM_LOCK_BASE 0x3840
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#define QLC_83XX_SEM_UNLOCK_BASE 0x3844
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#define QLC_83XX_SEM_LOCK_FUNC(f) (QLC_83XX_SEM_LOCK_BASE+((f)*8))
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#define QLC_83XX_SEM_UNLOCK_FUNC(f) (QLC_83XX_SEM_UNLOCK_BASE+((f)*8))
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#define QLC_83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
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#define QLC_83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
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#define QLC_83XX_LINK_SPEED_FACTOR 10
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#define QLC_83xx_FUNC_VAL(v, f) ((v) & (1 << (f * 4)))
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#define QLC_83XX_INTX_PTR 0x38C0
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#define QLC_83XX_INTX_TRGR 0x38C4
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#define QLC_83XX_INTX_MASK 0x38C8
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#define QLC_83XX_DRV_LOCK_WAIT_COUNTER 100
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#define QLC_83XX_DRV_LOCK_WAIT_DELAY 20
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#define QLC_83XX_NEED_DRV_LOCK_RECOVERY 1
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#define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS 2
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#define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT 3
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#define QLC_83XX_DRV_LOCK_RECOVERY_DELAY 200
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#define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK 0x3
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#define QLC_83XX_LB_WAIT_COUNT 250
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#define QLC_83XX_LB_MSLEEP_COUNT 20
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#define QLC_83XX_NO_NIC_RESOURCE 0x5
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#define QLC_83XX_MAC_PRESENT 0xC
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#define QLC_83XX_MAC_ABSENT 0xD
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#define QLC_83XX_FLASH_SECTOR_SIZE (64 * 1024)
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/* PEG status definitions */
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#define QLC_83XX_CMDPEG_COMPLETE 0xff01
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#define QLC_83XX_VALID_INTX_BIT30(val) ((val) & BIT_30)
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#define QLC_83XX_VALID_INTX_BIT31(val) ((val) & BIT_31)
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#define QLC_83XX_INTX_FUNC(val) ((val) & 0xFF)
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#define QLC_83XX_LEGACY_INTX_MAX_RETRY 100
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#define QLC_83XX_LEGACY_INTX_DELAY 4
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#define QLC_83XX_REG_DESC 1
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#define QLC_83XX_LRO_DESC 2
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#define QLC_83XX_CTRL_DESC 3
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#define QLC_83XX_FW_CAPABILITY_TSO BIT_6
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#define QLC_83XX_FW_CAP_LRO_MSS BIT_17
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#define QLC_83XX_HOST_RDS_MODE_UNIQUE 0
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#define QLC_83XX_HOST_SDS_MBX_IDX 8
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#define QLCNIC_HOST_RDS_MBX_IDX 88
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/* Pause control registers */
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#define QLC_83XX_SRE_SHIM_REG 0x0D200284
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#define QLC_83XX_PORT0_THRESHOLD 0x0B2003A4
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#define QLC_83XX_PORT1_THRESHOLD 0x0B2013A4
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#define QLC_83XX_PORT0_TC_MC_REG 0x0B200388
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#define QLC_83XX_PORT1_TC_MC_REG 0x0B201388
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#define QLC_83XX_PORT0_TC_STATS 0x0B20039C
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#define QLC_83XX_PORT1_TC_STATS 0x0B20139C
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#define QLC_83XX_PORT2_IFB_THRESHOLD 0x0B200704
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#define QLC_83XX_PORT3_IFB_THRESHOLD 0x0B201704
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/* Peg PC status registers */
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#define QLC_83XX_CRB_PEG_NET_0 0x3400003c
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#define QLC_83XX_CRB_PEG_NET_1 0x3410003c
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#define QLC_83XX_CRB_PEG_NET_2 0x3420003c
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#define QLC_83XX_CRB_PEG_NET_3 0x3430003c
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#define QLC_83XX_CRB_PEG_NET_4 0x34b0003c
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/* Firmware image definitions */
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#define QLC_83XX_BOOTLOADER_FLASH_ADDR 0x10000
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#define QLC_83XX_FW_FILE_NAME "83xx_fw.bin"
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#define QLC_83XX_POST_FW_FILE_NAME "83xx_post_fw.bin"
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#define QLC_84XX_FW_FILE_NAME "84xx_fw.bin"
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#define QLC_83XX_BOOT_FROM_FLASH 0
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#define QLC_83XX_BOOT_FROM_FILE 0x12345678
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#define QLC_FW_FILE_NAME_LEN 20
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#define QLC_83XX_MAX_RESET_SEQ_ENTRIES 16
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#define QLC_83XX_MBX_POST_BC_OP 0x1
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#define QLC_83XX_MBX_COMPLETION 0x0
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#define QLC_83XX_MBX_REQUEST 0x1
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#define QLC_83XX_MBX_TIMEOUT (5 * HZ)
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#define QLC_83XX_MBX_CMD_LOOP 5000000
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/* status descriptor mailbox data
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* @phy_addr_{low|high}: physical address of buffer
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* @sds_ring_size: buffer size
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* @intrpt_id: interrupt id
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* @intrpt_val: source of interrupt
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*/
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struct qlcnic_sds_mbx {
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u32 phy_addr_low;
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u32 phy_addr_high;
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u32 rsvd1[4];
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#if defined(__LITTLE_ENDIAN)
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u16 sds_ring_size;
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u16 rsvd2;
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u16 rsvd3[2];
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u16 intrpt_id;
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u8 intrpt_val;
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u8 rsvd4;
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#elif defined(__BIG_ENDIAN)
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u16 rsvd2;
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u16 sds_ring_size;
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u16 rsvd3[2];
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u8 rsvd4;
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u8 intrpt_val;
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u16 intrpt_id;
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#endif
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u32 rsvd5;
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} __packed;
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/* receive descriptor buffer data
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* phy_addr_reg_{low|high}: physical address of regular buffer
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* phy_addr_jmb_{low|high}: physical address of jumbo buffer
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* reg_ring_sz: size of regular buffer
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* reg_ring_len: no. of entries in regular buffer
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* jmb_ring_len: no. of entries in jumbo buffer
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* jmb_ring_sz: size of jumbo buffer
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*/
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struct qlcnic_rds_mbx {
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u32 phy_addr_reg_low;
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u32 phy_addr_reg_high;
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u32 phy_addr_jmb_low;
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u32 phy_addr_jmb_high;
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#if defined(__LITTLE_ENDIAN)
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u16 reg_ring_sz;
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u16 reg_ring_len;
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u16 jmb_ring_sz;
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u16 jmb_ring_len;
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#elif defined(__BIG_ENDIAN)
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u16 reg_ring_len;
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u16 reg_ring_sz;
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u16 jmb_ring_len;
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u16 jmb_ring_sz;
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#endif
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} __packed;
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/* host producers for regular and jumbo rings */
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struct __host_producer_mbx {
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u32 reg_buf;
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u32 jmb_buf;
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} __packed;
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/* Receive context mailbox data outbox registers
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* @state: state of the context
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* @vport_id: virtual port id
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* @context_id: receive context id
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* @num_pci_func: number of pci functions of the port
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* @phy_port: physical port id
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*/
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struct qlcnic_rcv_mbx_out {
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#if defined(__LITTLE_ENDIAN)
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u8 rcv_num;
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u8 sts_num;
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u16 ctx_id;
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u8 state;
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u8 num_pci_func;
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u8 phy_port;
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u8 vport_id;
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#elif defined(__BIG_ENDIAN)
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u16 ctx_id;
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u8 sts_num;
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u8 rcv_num;
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u8 vport_id;
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u8 phy_port;
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u8 num_pci_func;
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u8 state;
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#endif
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u32 host_csmr[QLCNIC_MAX_SDS_RINGS];
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struct __host_producer_mbx host_prod[QLCNIC_MAX_SDS_RINGS];
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} __packed;
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struct qlcnic_add_rings_mbx_out {
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#if defined(__LITTLE_ENDIAN)
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u8 rcv_num;
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u8 sts_num;
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u16 ctx_id;
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#elif defined(__BIG_ENDIAN)
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u16 ctx_id;
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u8 sts_num;
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u8 rcv_num;
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#endif
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u32 host_csmr[QLCNIC_MAX_SDS_RINGS];
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struct __host_producer_mbx host_prod[QLCNIC_MAX_SDS_RINGS];
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} __packed;
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/* Transmit context mailbox inbox registers
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* @phys_addr_{low|high}: DMA address of the transmit buffer
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* @cnsmr_index_{low|high}: host consumer index
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* @size: legth of transmit buffer ring
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* @intr_id: interrput id
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* @src: src of interrupt
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*/
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struct qlcnic_tx_mbx {
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u32 phys_addr_low;
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u32 phys_addr_high;
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u32 cnsmr_index_low;
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u32 cnsmr_index_high;
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#if defined(__LITTLE_ENDIAN)
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u16 size;
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||||
u16 intr_id;
|
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u8 src;
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u8 rsvd[3];
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#elif defined(__BIG_ENDIAN)
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u16 intr_id;
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||||
u16 size;
|
||||
u8 rsvd[3];
|
||||
u8 src;
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#endif
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} __packed;
|
||||
|
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/* Transmit context mailbox outbox registers
|
||||
* @host_prod: host producer index
|
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* @ctx_id: transmit context id
|
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* @state: state of the transmit context
|
||||
*/
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||||
|
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struct qlcnic_tx_mbx_out {
|
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u32 host_prod;
|
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#if defined(__LITTLE_ENDIAN)
|
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u16 ctx_id;
|
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u8 state;
|
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u8 rsvd;
|
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#elif defined(__BIG_ENDIAN)
|
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u8 rsvd;
|
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u8 state;
|
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u16 ctx_id;
|
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#endif
|
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} __packed;
|
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|
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struct qlcnic_intrpt_config {
|
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u8 type;
|
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u8 enabled;
|
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u16 id;
|
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u32 src;
|
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};
|
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|
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struct qlcnic_macvlan_mbx {
|
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#if defined(__LITTLE_ENDIAN)
|
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u8 mac_addr0;
|
||||
u8 mac_addr1;
|
||||
u8 mac_addr2;
|
||||
u8 mac_addr3;
|
||||
u8 mac_addr4;
|
||||
u8 mac_addr5;
|
||||
u16 vlan;
|
||||
#elif defined(__BIG_ENDIAN)
|
||||
u8 mac_addr3;
|
||||
u8 mac_addr2;
|
||||
u8 mac_addr1;
|
||||
u8 mac_addr0;
|
||||
u16 vlan;
|
||||
u8 mac_addr5;
|
||||
u8 mac_addr4;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct qlc_83xx_fw_info {
|
||||
const struct firmware *fw;
|
||||
char fw_file_name[QLC_FW_FILE_NAME_LEN];
|
||||
};
|
||||
|
||||
struct qlc_83xx_reset {
|
||||
struct qlc_83xx_reset_hdr *hdr;
|
||||
int seq_index;
|
||||
int seq_error;
|
||||
int array_index;
|
||||
u32 array[QLC_83XX_MAX_RESET_SEQ_ENTRIES];
|
||||
u8 *buff;
|
||||
u8 *stop_offset;
|
||||
u8 *start_offset;
|
||||
u8 *init_offset;
|
||||
u8 seq_end;
|
||||
u8 template_end;
|
||||
};
|
||||
|
||||
#define QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY 0x1
|
||||
#define QLC_83XX_IDC_GRACEFULL_RESET 0x2
|
||||
#define QLC_83XX_IDC_DISABLE_FW_DUMP 0x4
|
||||
#define QLC_83XX_IDC_TIMESTAMP 0
|
||||
#define QLC_83XX_IDC_DURATION 1
|
||||
#define QLC_83XX_IDC_INIT_TIMEOUT_SECS 30
|
||||
#define QLC_83XX_IDC_RESET_ACK_TIMEOUT_SECS 10
|
||||
#define QLC_83XX_IDC_RESET_TIMEOUT_SECS 10
|
||||
#define QLC_83XX_IDC_QUIESCE_ACK_TIMEOUT_SECS 20
|
||||
#define QLC_83XX_IDC_FW_POLL_DELAY (1 * HZ)
|
||||
#define QLC_83XX_IDC_FW_FAIL_THRESH 2
|
||||
#define QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO 8
|
||||
#define QLC_83XX_IDC_MAX_CNA_FUNCTIONS 16
|
||||
#define QLC_83XX_IDC_MAJOR_VERSION 1
|
||||
#define QLC_83XX_IDC_MINOR_VERSION 0
|
||||
#define QLC_83XX_IDC_FLASH_PARAM_ADDR 0x3e8020
|
||||
|
||||
struct qlcnic_adapter;
|
||||
struct qlcnic_fw_dump;
|
||||
|
||||
struct qlc_83xx_idc {
|
||||
int (*state_entry) (struct qlcnic_adapter *);
|
||||
u64 sec_counter;
|
||||
u64 delay;
|
||||
unsigned long status;
|
||||
int err_code;
|
||||
int collect_dump;
|
||||
u8 curr_state;
|
||||
u8 prev_state;
|
||||
u8 vnic_state;
|
||||
u8 vnic_wait_limit;
|
||||
u8 quiesce_req;
|
||||
u8 delay_reset;
|
||||
char **name;
|
||||
};
|
||||
|
||||
enum qlcnic_vlan_operations {
|
||||
QLC_VLAN_ADD = 0,
|
||||
QLC_VLAN_DELETE
|
||||
};
|
||||
|
||||
/* Device States */
|
||||
enum qlcnic_83xx_states {
|
||||
QLC_83XX_IDC_DEV_UNKNOWN,
|
||||
QLC_83XX_IDC_DEV_COLD,
|
||||
QLC_83XX_IDC_DEV_INIT,
|
||||
QLC_83XX_IDC_DEV_READY,
|
||||
QLC_83XX_IDC_DEV_NEED_RESET,
|
||||
QLC_83XX_IDC_DEV_NEED_QUISCENT,
|
||||
QLC_83XX_IDC_DEV_FAILED,
|
||||
QLC_83XX_IDC_DEV_QUISCENT
|
||||
};
|
||||
|
||||
#define QLCNIC_MBX_RSP(reg) LSW(reg)
|
||||
#define QLCNIC_MBX_NUM_REGS(reg) (MSW(reg) & 0x1FF)
|
||||
#define QLCNIC_MBX_STATUS(reg) (((reg) >> 25) & 0x7F)
|
||||
#define QLCNIC_MBX_HOST(ahw, i) ((ahw)->pci_base0 + ((i) * 4))
|
||||
#define QLCNIC_MBX_FW(ahw, i) ((ahw)->pci_base0 + 0x800 + ((i) * 4))
|
||||
|
||||
/* Mailbox process AEN count */
|
||||
#define QLC_83XX_IDC_COMP_AEN 3
|
||||
#define QLC_83XX_MBX_AEN_CNT 5
|
||||
#define QLC_83XX_MODULE_LOADED 1
|
||||
#define QLC_83XX_MBX_READY 2
|
||||
#define QLC_83XX_MBX_AEN_ACK 3
|
||||
#define QLC_83XX_SFP_PRESENT(data) ((data) & 3)
|
||||
#define QLC_83XX_SFP_ERR(data) (((data) >> 2) & 3)
|
||||
#define QLC_83XX_SFP_MODULE_TYPE(data) (((data) >> 4) & 0x1F)
|
||||
#define QLC_83XX_SFP_CU_LENGTH(data) (LSB((data) >> 16))
|
||||
#define QLC_83XX_SFP_TX_FAULT(data) ((data) & BIT_10)
|
||||
#define QLC_83XX_LINK_STATS(data) ((data) & BIT_0)
|
||||
#define QLC_83XX_CURRENT_LINK_SPEED(data) (((data) >> 3) & 7)
|
||||
#define QLC_83XX_LINK_PAUSE(data) (((data) >> 6) & 3)
|
||||
#define QLC_83XX_LINK_LB(data) (((data) >> 8) & 7)
|
||||
#define QLC_83XX_LINK_FEC(data) ((data) & BIT_12)
|
||||
#define QLC_83XX_LINK_EEE(data) ((data) & BIT_13)
|
||||
#define QLC_83XX_DCBX(data) (((data) >> 28) & 7)
|
||||
#define QLC_83XX_AUTONEG(data) ((data) & BIT_15)
|
||||
#define QLC_83XX_TX_PAUSE 0x10
|
||||
#define QLC_83XX_RX_PAUSE 0x20
|
||||
#define QLC_83XX_TX_RX_PAUSE 0x30
|
||||
#define QLC_83XX_CFG_STD_PAUSE (1 << 5)
|
||||
#define QLC_83XX_CFG_STD_TX_PAUSE (1 << 20)
|
||||
#define QLC_83XX_CFG_STD_RX_PAUSE (2 << 20)
|
||||
#define QLC_83XX_CFG_STD_TX_RX_PAUSE (3 << 20)
|
||||
#define QLC_83XX_ENABLE_AUTONEG (1 << 15)
|
||||
#define QLC_83XX_CFG_LOOPBACK_HSS (2 << 1)
|
||||
#define QLC_83XX_CFG_LOOPBACK_PHY (3 << 1)
|
||||
#define QLC_83XX_CFG_LOOPBACK_EXT (4 << 1)
|
||||
|
||||
/* LED configuration settings */
|
||||
#define QLC_83XX_ENABLE_BEACON 0xe
|
||||
#define QLC_83XX_BEACON_ON 1
|
||||
#define QLC_83XX_BEACON_OFF 0
|
||||
#define QLC_83XX_LED_RATE 0xff
|
||||
#define QLC_83XX_LED_ACT (1 << 10)
|
||||
#define QLC_83XX_LED_MOD (0 << 13)
|
||||
#define QLC_83XX_LED_CONFIG (QLC_83XX_LED_RATE | QLC_83XX_LED_ACT | \
|
||||
QLC_83XX_LED_MOD)
|
||||
|
||||
#define QLC_83XX_10M_LINK 1
|
||||
#define QLC_83XX_100M_LINK 2
|
||||
#define QLC_83XX_1G_LINK 3
|
||||
#define QLC_83XX_10G_LINK 4
|
||||
#define QLC_83XX_STAT_TX 3
|
||||
#define QLC_83XX_STAT_RX 2
|
||||
#define QLC_83XX_STAT_MAC 1
|
||||
#define QLC_83XX_TX_STAT_REGS 14
|
||||
#define QLC_83XX_RX_STAT_REGS 40
|
||||
#define QLC_83XX_MAC_STAT_REGS 94
|
||||
|
||||
#define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2)))
|
||||
#define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2))
|
||||
#define QLC_83XX_DEFAULT_OPMODE 0x55555555
|
||||
#define QLC_83XX_PRIVLEGED_FUNC 0x1
|
||||
#define QLC_83XX_VIRTUAL_FUNC 0x2
|
||||
|
||||
#define QLC_83XX_LB_MAX_FILTERS 2048
|
||||
#define QLC_83XX_LB_BUCKET_SIZE 256
|
||||
#define QLC_83XX_MINIMUM_VECTOR 3
|
||||
#define QLC_83XX_MAX_MC_COUNT 38
|
||||
#define QLC_83XX_MAX_UC_COUNT 4096
|
||||
|
||||
#define QLC_83XX_PVID_STRIP_CAPABILITY BIT_22
|
||||
#define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val) (val & 0x80000000)
|
||||
#define QLC_83XX_GET_LRO_CAPABILITY(val) (val & 0x20)
|
||||
#define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40)
|
||||
#define QLC_83XX_GET_HW_LRO_CAPABILITY(val) (val & 0x400)
|
||||
#define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val) (val & 0x4000)
|
||||
#define QLC_83XX_GET_FW_LRO_MSS_CAPABILITY(val) (val & 0x20000)
|
||||
#define QLC_83XX_ESWITCH_CAPABILITY BIT_23
|
||||
#define QLC_83XX_SRIOV_MODE 0x1
|
||||
#define QLCNIC_BRDTYPE_83XX_10G 0x0083
|
||||
|
||||
#define QLC_83XX_FLASH_SPI_STATUS 0x2808E010
|
||||
#define QLC_83XX_FLASH_SPI_CONTROL 0x2808E014
|
||||
#define QLC_83XX_FLASH_STATUS 0x42100004
|
||||
#define QLC_83XX_FLASH_CONTROL 0x42110004
|
||||
#define QLC_83XX_FLASH_ADDR 0x42110008
|
||||
#define QLC_83XX_FLASH_WRDATA 0x4211000C
|
||||
#define QLC_83XX_FLASH_RDDATA 0x42110018
|
||||
#define QLC_83XX_FLASH_DIRECT_WINDOW 0x42110030
|
||||
#define QLC_83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
|
||||
#define QLC_83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
|
||||
#define QLC_83XX_FLASH_WRITE_CMD 0xdacdacda
|
||||
#define QLC_83XX_FLASH_BULK_WRITE_CMD 0xcadcadca
|
||||
#define QLC_83XX_FLASH_READ_RETRY_COUNT 5000
|
||||
#define QLC_83XX_FLASH_STATUS_READY 0x6
|
||||
#define QLC_83XX_FLASH_WRITE_MIN 2
|
||||
#define QLC_83XX_FLASH_WRITE_MAX 64
|
||||
#define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY 1
|
||||
#define QLC_83XX_ERASE_MODE 1
|
||||
#define QLC_83XX_WRITE_MODE 2
|
||||
#define QLC_83XX_BULK_WRITE_MODE 3
|
||||
#define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG 0xFD0100
|
||||
#define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG 0xFD0300
|
||||
#define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL 0xFD009F
|
||||
#define QLC_83XX_FLASH_OEM_ERASE_SIG 0xFD03D8
|
||||
#define QLC_83XX_FLASH_OEM_WRITE_SIG 0xFD0101
|
||||
#define QLC_83XX_FLASH_OEM_READ_SIG 0xFD0005
|
||||
#define QLC_83XX_FLASH_ADDR_TEMP_VAL 0x00800000
|
||||
#define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL 0x00800001
|
||||
#define QLC_83XX_FLASH_WRDATA_DEF 0x0
|
||||
#define QLC_83XX_FLASH_READ_CTRL 0x3F
|
||||
#define QLC_83XX_FLASH_SPI_CTRL 0x4
|
||||
#define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL 0x2
|
||||
#define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL 0x5
|
||||
#define QLC_83XX_FLASH_LAST_ERASE_MS_VAL 0x3D
|
||||
#define QLC_83XX_FLASH_FIRST_MS_PATTERN 0x43
|
||||
#define QLC_83XX_FLASH_SECOND_MS_PATTERN 0x7F
|
||||
#define QLC_83XX_FLASH_LAST_MS_PATTERN 0x7D
|
||||
#define QLC_83xx_FLASH_MAX_WAIT_USEC 100
|
||||
#define QLC_83XX_FLASH_LOCK_TIMEOUT 10000
|
||||
|
||||
enum qlc_83xx_mbx_cmd_type {
|
||||
QLC_83XX_MBX_CMD_WAIT = 0,
|
||||
QLC_83XX_MBX_CMD_NO_WAIT,
|
||||
QLC_83XX_MBX_CMD_BUSY_WAIT,
|
||||
};
|
||||
|
||||
enum qlc_83xx_mbx_response_states {
|
||||
QLC_83XX_MBX_RESPONSE_WAIT = 0,
|
||||
QLC_83XX_MBX_RESPONSE_ARRIVED,
|
||||
};
|
||||
|
||||
#define QLC_83XX_MBX_RESPONSE_FAILED 0x2
|
||||
#define QLC_83XX_MBX_RESPONSE_UNKNOWN 0x3
|
||||
|
||||
/* Additional registers in 83xx */
|
||||
enum qlc_83xx_ext_regs {
|
||||
QLCNIC_GLOBAL_RESET = 0,
|
||||
QLCNIC_WILDCARD,
|
||||
QLCNIC_INFORMANT,
|
||||
QLCNIC_HOST_MBX_CTRL,
|
||||
QLCNIC_FW_MBX_CTRL,
|
||||
QLCNIC_BOOTLOADER_ADDR,
|
||||
QLCNIC_BOOTLOADER_SIZE,
|
||||
QLCNIC_FW_IMAGE_ADDR,
|
||||
QLCNIC_MBX_INTR_ENBL,
|
||||
QLCNIC_DEF_INT_MASK,
|
||||
QLCNIC_DEF_INT_ID,
|
||||
QLC_83XX_IDC_MAJ_VERSION,
|
||||
QLC_83XX_IDC_DEV_STATE,
|
||||
QLC_83XX_IDC_DRV_PRESENCE,
|
||||
QLC_83XX_IDC_DRV_ACK,
|
||||
QLC_83XX_IDC_CTRL,
|
||||
QLC_83XX_IDC_DRV_AUDIT,
|
||||
QLC_83XX_IDC_MIN_VERSION,
|
||||
QLC_83XX_RECOVER_DRV_LOCK,
|
||||
QLC_83XX_IDC_PF_0,
|
||||
QLC_83XX_IDC_PF_1,
|
||||
QLC_83XX_IDC_PF_2,
|
||||
QLC_83XX_IDC_PF_3,
|
||||
QLC_83XX_IDC_PF_4,
|
||||
QLC_83XX_IDC_PF_5,
|
||||
QLC_83XX_IDC_PF_6,
|
||||
QLC_83XX_IDC_PF_7,
|
||||
QLC_83XX_IDC_PF_8,
|
||||
QLC_83XX_IDC_PF_9,
|
||||
QLC_83XX_IDC_PF_10,
|
||||
QLC_83XX_IDC_PF_11,
|
||||
QLC_83XX_IDC_PF_12,
|
||||
QLC_83XX_IDC_PF_13,
|
||||
QLC_83XX_IDC_PF_14,
|
||||
QLC_83XX_IDC_PF_15,
|
||||
QLC_83XX_IDC_DEV_PARTITION_INFO_1,
|
||||
QLC_83XX_IDC_DEV_PARTITION_INFO_2,
|
||||
QLC_83XX_DRV_OP_MODE,
|
||||
QLC_83XX_VNIC_STATE,
|
||||
QLC_83XX_DRV_LOCK,
|
||||
QLC_83XX_DRV_UNLOCK,
|
||||
QLC_83XX_DRV_LOCK_ID,
|
||||
QLC_83XX_ASIC_TEMP,
|
||||
};
|
||||
|
||||
/* Initialize/Stop NIC command bit definitions */
|
||||
#define QLC_REGISTER_LB_IDC BIT_0
|
||||
#define QLC_REGISTER_DCB_AEN BIT_1
|
||||
#define QLC_83XX_MULTI_TENANCY_INFO BIT_29
|
||||
#define QLC_INIT_FW_RESOURCES BIT_31
|
||||
|
||||
/* 83xx funcitons */
|
||||
int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *, struct qlcnic_cmd_args *);
|
||||
int qlcnic_83xx_setup_intr(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_get_func_no(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_cam_lock(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *);
|
||||
int qlcnic_send_ctrl_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *, u32);
|
||||
void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
|
||||
void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
|
||||
int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong, int *);
|
||||
int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32);
|
||||
int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32);
|
||||
int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int);
|
||||
int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int);
|
||||
void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *, u64 *, u16);
|
||||
int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *);
|
||||
int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
|
||||
void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *, int);
|
||||
|
||||
int qlcnic_83xx_napi_add(struct qlcnic_adapter *, struct net_device *);
|
||||
void qlcnic_83xx_napi_del(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_napi_enable(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_napi_disable(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_config_led(struct qlcnic_adapter *, u32, u32);
|
||||
int qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32);
|
||||
int qlcnic_ind_rd(struct qlcnic_adapter *, u32);
|
||||
int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *,
|
||||
struct qlcnic_host_tx_ring *, int);
|
||||
void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *,
|
||||
struct qlcnic_host_tx_ring *);
|
||||
int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
|
||||
int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int);
|
||||
void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *);
|
||||
int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool);
|
||||
int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, u16, u8);
|
||||
int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *, u8);
|
||||
int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *,
|
||||
struct qlcnic_adapter *, u32);
|
||||
void qlcnic_free_mbx_args(struct qlcnic_cmd_args *);
|
||||
void qlcnic_set_npar_data(struct qlcnic_adapter *, const struct qlcnic_info *,
|
||||
struct qlcnic_info *);
|
||||
int qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *,
|
||||
struct ethtool_coalesce *);
|
||||
int qlcnic_83xx_set_rx_tx_intr_coal(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_get_port_info(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *);
|
||||
irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *);
|
||||
irqreturn_t qlcnic_83xx_intr(int, void *);
|
||||
irqreturn_t qlcnic_83xx_tmp_intr(int, void *);
|
||||
void qlcnic_83xx_check_vf(struct qlcnic_adapter *,
|
||||
const struct pci_device_id *);
|
||||
int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_register_map(struct qlcnic_hardware_context *);
|
||||
void qlcnic_83xx_idc_aen_work(struct work_struct *);
|
||||
void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int);
|
||||
|
||||
int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32);
|
||||
int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int);
|
||||
int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *);
|
||||
int qlcnic_83xx_lock_flash(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_save_flash_status(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_restore_flash_status(struct qlcnic_adapter *, int);
|
||||
int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_flash_read32(struct qlcnic_adapter *, u32, u8 *, int);
|
||||
int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *,
|
||||
u32, u8 *, int);
|
||||
int qlcnic_83xx_init(struct qlcnic_adapter *, int);
|
||||
int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_idc_poll_dev_state(struct work_struct *);
|
||||
void qlcnic_83xx_idc_exit(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *, u32);
|
||||
int qlcnic_83xx_lock_driver(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_set_default_offload_settings(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_disable_vnic_mode(struct qlcnic_adapter *, int);
|
||||
int qlcnic_83xx_config_vnic_opmode(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_get_vnic_vport_info(struct qlcnic_adapter *,
|
||||
struct qlcnic_info *, u8);
|
||||
int qlcnic_83xx_get_vnic_pf_info(struct qlcnic_adapter *, struct qlcnic_info *);
|
||||
int qlcnic_83xx_set_port_eswitch_status(struct qlcnic_adapter *, int, int *);
|
||||
|
||||
void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data);
|
||||
int qlcnic_83xx_get_settings(struct qlcnic_adapter *, struct ethtool_cmd *);
|
||||
int qlcnic_83xx_set_settings(struct qlcnic_adapter *, struct ethtool_cmd *);
|
||||
void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *,
|
||||
struct ethtool_pauseparam *);
|
||||
int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *,
|
||||
struct ethtool_pauseparam *);
|
||||
int qlcnic_83xx_test_link(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_reg_test(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_get_registers(struct qlcnic_adapter *, u32 *);
|
||||
int qlcnic_83xx_loopback_test(struct net_device *, u8);
|
||||
int qlcnic_83xx_interrupt_test(struct net_device *);
|
||||
int qlcnic_83xx_set_led(struct net_device *, enum ethtool_phys_id_state);
|
||||
int qlcnic_83xx_flash_test(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_idc_init(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_set_vnic_opmode(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_check_vnic_state(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_aer_reset(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *);
|
||||
u32 qlcnic_83xx_get_saved_state(void *, u32);
|
||||
void qlcnic_83xx_set_saved_state(void *, u32, u32);
|
||||
void qlcnic_83xx_cache_tmpl_hdr_values(struct qlcnic_fw_dump *);
|
||||
u32 qlcnic_83xx_get_cap_size(void *, int);
|
||||
void qlcnic_83xx_set_sys_info(void *, int, u32);
|
||||
void qlcnic_83xx_store_cap_mask(void *, u32);
|
||||
int qlcnic_ms_mem_write128(struct qlcnic_adapter *, u64, u32 *, u32);
|
||||
#endif
|
||||
2616
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c
Normal file
2616
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c
Normal file
File diff suppressed because it is too large
Load diff
284
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_vnic.c
Normal file
284
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_vnic.c
Normal file
|
|
@ -0,0 +1,284 @@
|
|||
/*
|
||||
* QLogic qlcnic NIC Driver
|
||||
* Copyright (c) 2009-2013 QLogic Corporation
|
||||
*
|
||||
* See LICENSE.qlcnic for copyright and licensing details.
|
||||
*/
|
||||
|
||||
#include "qlcnic.h"
|
||||
#include "qlcnic_hw.h"
|
||||
|
||||
static int qlcnic_83xx_enable_vnic_mode(struct qlcnic_adapter *adapter, int lock)
|
||||
{
|
||||
if (lock) {
|
||||
if (qlcnic_83xx_lock_driver(adapter))
|
||||
return -EBUSY;
|
||||
}
|
||||
QLCWRX(adapter->ahw, QLC_83XX_VNIC_STATE, QLCNIC_DEV_NPAR_OPER);
|
||||
if (lock)
|
||||
qlcnic_83xx_unlock_driver(adapter);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int qlcnic_83xx_disable_vnic_mode(struct qlcnic_adapter *adapter, int lock)
|
||||
{
|
||||
struct qlcnic_hardware_context *ahw = adapter->ahw;
|
||||
|
||||
if (lock) {
|
||||
if (qlcnic_83xx_lock_driver(adapter))
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
QLCWRX(adapter->ahw, QLC_83XX_VNIC_STATE, QLCNIC_DEV_NPAR_NON_OPER);
|
||||
ahw->idc.vnic_state = QLCNIC_DEV_NPAR_NON_OPER;
|
||||
|
||||
if (lock)
|
||||
qlcnic_83xx_unlock_driver(adapter);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int qlcnic_83xx_set_vnic_opmode(struct qlcnic_adapter *adapter)
|
||||
{
|
||||
u8 id;
|
||||
int ret = -EBUSY;
|
||||
u32 data = QLCNIC_MGMT_FUNC;
|
||||
struct qlcnic_hardware_context *ahw = adapter->ahw;
|
||||
|
||||
if (qlcnic_83xx_lock_driver(adapter))
|
||||
return ret;
|
||||
|
||||
id = ahw->pci_func;
|
||||
data = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
|
||||
data = (data & ~QLC_83XX_SET_FUNC_OPMODE(0x3, id)) |
|
||||
QLC_83XX_SET_FUNC_OPMODE(QLCNIC_MGMT_FUNC, id);
|
||||
|
||||
QLCWRX(adapter->ahw, QLC_83XX_DRV_OP_MODE, data);
|
||||
|
||||
qlcnic_83xx_unlock_driver(adapter);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
qlcnic_83xx_config_vnic_buff_descriptors(struct qlcnic_adapter *adapter)
|
||||
{
|
||||
struct qlcnic_hardware_context *ahw = adapter->ahw;
|
||||
|
||||
if (ahw->port_type == QLCNIC_XGBE) {
|
||||
adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_VF;
|
||||
adapter->max_rxd = MAX_RCV_DESCRIPTORS_VF;
|
||||
adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
|
||||
adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
|
||||
|
||||
} else if (ahw->port_type == QLCNIC_GBE) {
|
||||
adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
|
||||
adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
|
||||
adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
|
||||
adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
|
||||
}
|
||||
adapter->num_txd = MAX_CMD_DESCRIPTORS;
|
||||
adapter->max_rds_rings = MAX_RDS_RINGS;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* qlcnic_83xx_init_mgmt_vnic
|
||||
*
|
||||
* @adapter: adapter structure
|
||||
* Management virtual NIC sets the operational mode of other vNIC's and
|
||||
* configures embedded switch (ESWITCH).
|
||||
* Returns: Success(0) or error code.
|
||||
*
|
||||
**/
|
||||
static int qlcnic_83xx_init_mgmt_vnic(struct qlcnic_adapter *adapter)
|
||||
{
|
||||
struct qlcnic_hardware_context *ahw = adapter->ahw;
|
||||
struct device *dev = &adapter->pdev->dev;
|
||||
struct qlcnic_npar_info *npar;
|
||||
int i, err = -EIO;
|
||||
|
||||
qlcnic_83xx_get_minidump_template(adapter);
|
||||
|
||||
if (!(adapter->flags & QLCNIC_ADAPTER_INITIALIZED)) {
|
||||
if (qlcnic_init_pci_info(adapter))
|
||||
return err;
|
||||
|
||||
npar = adapter->npars;
|
||||
|
||||
for (i = 0; i < ahw->total_nic_func; i++, npar++) {
|
||||
dev_info(dev, "id:%d active:%d type:%d port:%d min_bw:%d max_bw:%d mac_addr:%pM\n",
|
||||
npar->pci_func, npar->active, npar->type,
|
||||
npar->phy_port, npar->min_bw, npar->max_bw,
|
||||
npar->mac);
|
||||
}
|
||||
|
||||
dev_info(dev, "Max functions = %d, active functions = %d\n",
|
||||
ahw->max_pci_func, ahw->total_nic_func);
|
||||
|
||||
if (qlcnic_83xx_set_vnic_opmode(adapter))
|
||||
return err;
|
||||
|
||||
if (qlcnic_set_default_offload_settings(adapter))
|
||||
return err;
|
||||
} else {
|
||||
if (qlcnic_reset_npar_config(adapter))
|
||||
return err;
|
||||
}
|
||||
|
||||
if (qlcnic_83xx_get_port_info(adapter))
|
||||
return err;
|
||||
|
||||
qlcnic_83xx_config_vnic_buff_descriptors(adapter);
|
||||
ahw->msix_supported = qlcnic_use_msi_x ? 1 : 0;
|
||||
adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
|
||||
qlcnic_83xx_enable_vnic_mode(adapter, 1);
|
||||
|
||||
dev_info(dev, "HAL Version: %d, Management function\n",
|
||||
ahw->fw_hal_version);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qlcnic_83xx_init_privileged_vnic(struct qlcnic_adapter *adapter)
|
||||
{
|
||||
int err = -EIO;
|
||||
|
||||
qlcnic_83xx_get_minidump_template(adapter);
|
||||
if (qlcnic_83xx_get_port_info(adapter))
|
||||
return err;
|
||||
|
||||
qlcnic_83xx_config_vnic_buff_descriptors(adapter);
|
||||
adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
|
||||
adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
|
||||
|
||||
dev_info(&adapter->pdev->dev,
|
||||
"HAL Version: %d, Privileged function\n",
|
||||
adapter->ahw->fw_hal_version);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qlcnic_83xx_init_non_privileged_vnic(struct qlcnic_adapter *adapter)
|
||||
{
|
||||
int err = -EIO;
|
||||
|
||||
qlcnic_83xx_get_fw_version(adapter);
|
||||
if (qlcnic_set_eswitch_port_config(adapter))
|
||||
return err;
|
||||
|
||||
if (qlcnic_83xx_get_port_info(adapter))
|
||||
return err;
|
||||
|
||||
qlcnic_83xx_config_vnic_buff_descriptors(adapter);
|
||||
adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
|
||||
adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
|
||||
|
||||
dev_info(&adapter->pdev->dev, "HAL Version: %d, Virtual function\n",
|
||||
adapter->ahw->fw_hal_version);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* qlcnic_83xx_vnic_opmode
|
||||
*
|
||||
* @adapter: adapter structure
|
||||
* Identify virtual NIC operational modes.
|
||||
*
|
||||
* Returns: Success(0) or error code.
|
||||
*
|
||||
**/
|
||||
int qlcnic_83xx_config_vnic_opmode(struct qlcnic_adapter *adapter)
|
||||
{
|
||||
u32 op_mode, priv_level;
|
||||
struct qlcnic_hardware_context *ahw = adapter->ahw;
|
||||
struct qlcnic_nic_template *nic_ops = adapter->nic_ops;
|
||||
|
||||
qlcnic_get_func_no(adapter);
|
||||
op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
|
||||
|
||||
if (op_mode == QLC_83XX_DEFAULT_OPMODE)
|
||||
priv_level = QLCNIC_MGMT_FUNC;
|
||||
else
|
||||
priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
|
||||
ahw->pci_func);
|
||||
switch (priv_level) {
|
||||
case QLCNIC_NON_PRIV_FUNC:
|
||||
ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
|
||||
ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
|
||||
nic_ops->init_driver = qlcnic_83xx_init_non_privileged_vnic;
|
||||
break;
|
||||
case QLCNIC_PRIV_FUNC:
|
||||
ahw->op_mode = QLCNIC_PRIV_FUNC;
|
||||
ahw->idc.state_entry = qlcnic_83xx_idc_vnic_pf_entry;
|
||||
nic_ops->init_driver = qlcnic_83xx_init_privileged_vnic;
|
||||
break;
|
||||
case QLCNIC_MGMT_FUNC:
|
||||
ahw->op_mode = QLCNIC_MGMT_FUNC;
|
||||
ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
|
||||
nic_ops->init_driver = qlcnic_83xx_init_mgmt_vnic;
|
||||
break;
|
||||
default:
|
||||
dev_err(&adapter->pdev->dev, "Invalid Virtual NIC opmode\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if (ahw->capabilities & QLC_83XX_ESWITCH_CAPABILITY) {
|
||||
adapter->flags |= QLCNIC_ESWITCH_ENABLED;
|
||||
if (adapter->drv_mac_learn)
|
||||
adapter->rx_mac_learn = true;
|
||||
} else {
|
||||
adapter->flags &= ~QLCNIC_ESWITCH_ENABLED;
|
||||
adapter->rx_mac_learn = false;
|
||||
}
|
||||
|
||||
ahw->idc.vnic_state = QLCNIC_DEV_NPAR_NON_OPER;
|
||||
ahw->idc.vnic_wait_limit = QLCNIC_DEV_NPAR_OPER_TIMEO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int qlcnic_83xx_check_vnic_state(struct qlcnic_adapter *adapter)
|
||||
{
|
||||
struct qlcnic_hardware_context *ahw = adapter->ahw;
|
||||
struct qlc_83xx_idc *idc = &ahw->idc;
|
||||
u32 state;
|
||||
|
||||
state = QLCRDX(ahw, QLC_83XX_VNIC_STATE);
|
||||
while (state != QLCNIC_DEV_NPAR_OPER && idc->vnic_wait_limit--) {
|
||||
msleep(1000);
|
||||
state = QLCRDX(ahw, QLC_83XX_VNIC_STATE);
|
||||
}
|
||||
|
||||
if (!idc->vnic_wait_limit) {
|
||||
dev_err(&adapter->pdev->dev,
|
||||
"vNIC mode not operational, state check timed out.\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int qlcnic_83xx_set_port_eswitch_status(struct qlcnic_adapter *adapter,
|
||||
int func, int *port_id)
|
||||
{
|
||||
struct qlcnic_info nic_info;
|
||||
int err = 0;
|
||||
|
||||
memset(&nic_info, 0, sizeof(struct qlcnic_info));
|
||||
|
||||
err = qlcnic_get_nic_info(adapter, &nic_info, func);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (nic_info.capabilities & QLC_83XX_ESWITCH_CAPABILITY)
|
||||
*port_id = nic_info.phys_port;
|
||||
else
|
||||
err = -EIO;
|
||||
|
||||
if (!err)
|
||||
adapter->eswitch[*port_id].flags |= QLCNIC_SWITCH_ENABLE;
|
||||
|
||||
return err;
|
||||
}
|
||||
1428
drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c
Normal file
1428
drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c
Normal file
File diff suppressed because it is too large
Load diff
1147
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
Normal file
1147
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
Normal file
File diff suppressed because it is too large
Load diff
122
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.h
Normal file
122
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.h
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* QLogic qlcnic NIC Driver
|
||||
* Copyright (c) 2009-2013 QLogic Corporation
|
||||
*
|
||||
* See LICENSE.qlcnic for copyright and licensing details.
|
||||
*/
|
||||
|
||||
#ifndef __QLCNIC_DCBX_H
|
||||
#define __QLCNIC_DCBX_H
|
||||
|
||||
#define QLCNIC_DCB_STATE 0
|
||||
#define QLCNIC_DCB_AEN_MODE 1
|
||||
|
||||
#ifdef CONFIG_QLCNIC_DCB
|
||||
int qlcnic_register_dcb(struct qlcnic_adapter *);
|
||||
#else
|
||||
static inline int qlcnic_register_dcb(struct qlcnic_adapter *adapter)
|
||||
{ return 0; }
|
||||
#endif
|
||||
|
||||
struct qlcnic_dcb;
|
||||
|
||||
struct qlcnic_dcb_ops {
|
||||
int (*query_hw_capability) (struct qlcnic_dcb *, char *);
|
||||
int (*get_hw_capability) (struct qlcnic_dcb *);
|
||||
int (*query_cee_param) (struct qlcnic_dcb *, char *, u8);
|
||||
void (*init_dcbnl_ops) (struct qlcnic_dcb *);
|
||||
void (*aen_handler) (struct qlcnic_dcb *, void *);
|
||||
int (*get_cee_cfg) (struct qlcnic_dcb *);
|
||||
void (*get_info) (struct qlcnic_dcb *);
|
||||
int (*attach) (struct qlcnic_dcb *);
|
||||
void (*free) (struct qlcnic_dcb *);
|
||||
};
|
||||
|
||||
struct qlcnic_dcb {
|
||||
struct qlcnic_dcb_mbx_params *param;
|
||||
struct qlcnic_adapter *adapter;
|
||||
struct delayed_work aen_work;
|
||||
struct workqueue_struct *wq;
|
||||
struct qlcnic_dcb_ops *ops;
|
||||
struct qlcnic_dcb_cfg *cfg;
|
||||
unsigned long state;
|
||||
};
|
||||
|
||||
static inline void qlcnic_clear_dcb_ops(struct qlcnic_dcb *dcb)
|
||||
{
|
||||
kfree(dcb);
|
||||
dcb = NULL;
|
||||
}
|
||||
|
||||
static inline int qlcnic_dcb_get_hw_capability(struct qlcnic_dcb *dcb)
|
||||
{
|
||||
if (dcb && dcb->ops->get_hw_capability)
|
||||
return dcb->ops->get_hw_capability(dcb);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void qlcnic_dcb_free(struct qlcnic_dcb *dcb)
|
||||
{
|
||||
if (dcb && dcb->ops->free)
|
||||
dcb->ops->free(dcb);
|
||||
}
|
||||
|
||||
static inline int qlcnic_dcb_attach(struct qlcnic_dcb *dcb)
|
||||
{
|
||||
if (dcb && dcb->ops->attach)
|
||||
return dcb->ops->attach(dcb);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
qlcnic_dcb_query_hw_capability(struct qlcnic_dcb *dcb, char *buf)
|
||||
{
|
||||
if (dcb && dcb->ops->query_hw_capability)
|
||||
return dcb->ops->query_hw_capability(dcb, buf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void qlcnic_dcb_get_info(struct qlcnic_dcb *dcb)
|
||||
{
|
||||
if (dcb && dcb->ops->get_info)
|
||||
dcb->ops->get_info(dcb);
|
||||
}
|
||||
|
||||
static inline int
|
||||
qlcnic_dcb_query_cee_param(struct qlcnic_dcb *dcb, char *buf, u8 type)
|
||||
{
|
||||
if (dcb && dcb->ops->query_cee_param)
|
||||
return dcb->ops->query_cee_param(dcb, buf, type);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int qlcnic_dcb_get_cee_cfg(struct qlcnic_dcb *dcb)
|
||||
{
|
||||
if (dcb && dcb->ops->get_cee_cfg)
|
||||
return dcb->ops->get_cee_cfg(dcb);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void qlcnic_dcb_aen_handler(struct qlcnic_dcb *dcb, void *msg)
|
||||
{
|
||||
if (dcb && dcb->ops->aen_handler)
|
||||
dcb->ops->aen_handler(dcb, msg);
|
||||
}
|
||||
|
||||
static inline void qlcnic_dcb_init_dcbnl_ops(struct qlcnic_dcb *dcb)
|
||||
{
|
||||
if (dcb && dcb->ops->init_dcbnl_ops)
|
||||
dcb->ops->init_dcbnl_ops(dcb);
|
||||
}
|
||||
|
||||
static inline void qlcnic_dcb_enable(struct qlcnic_dcb *dcb)
|
||||
{
|
||||
if (dcb && qlcnic_dcb_attach(dcb))
|
||||
qlcnic_clear_dcb_ops(dcb);
|
||||
}
|
||||
#endif
|
||||
1882
drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c
Normal file
1882
drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c
Normal file
File diff suppressed because it is too large
Load diff
948
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h
Normal file
948
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h
Normal file
|
|
@ -0,0 +1,948 @@
|
|||
/*
|
||||
* QLogic qlcnic NIC Driver
|
||||
* Copyright (c) 2009-2013 QLogic Corporation
|
||||
*
|
||||
* See LICENSE.qlcnic for copyright and licensing details.
|
||||
*/
|
||||
|
||||
#ifndef __QLCNIC_HDR_H_
|
||||
#define __QLCNIC_HDR_H_
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "qlcnic_hw.h"
|
||||
|
||||
/*
|
||||
* The basic unit of access when reading/writing control registers.
|
||||
*/
|
||||
|
||||
enum {
|
||||
QLCNIC_HW_H0_CH_HUB_ADR = 0x05,
|
||||
QLCNIC_HW_H1_CH_HUB_ADR = 0x0E,
|
||||
QLCNIC_HW_H2_CH_HUB_ADR = 0x03,
|
||||
QLCNIC_HW_H3_CH_HUB_ADR = 0x01,
|
||||
QLCNIC_HW_H4_CH_HUB_ADR = 0x06,
|
||||
QLCNIC_HW_H5_CH_HUB_ADR = 0x07,
|
||||
QLCNIC_HW_H6_CH_HUB_ADR = 0x08
|
||||
};
|
||||
|
||||
/* Hub 0 */
|
||||
enum {
|
||||
QLCNIC_HW_MN_CRB_AGT_ADR = 0x15,
|
||||
QLCNIC_HW_MS_CRB_AGT_ADR = 0x25
|
||||
};
|
||||
|
||||
/* Hub 1 */
|
||||
enum {
|
||||
QLCNIC_HW_PS_CRB_AGT_ADR = 0x73,
|
||||
QLCNIC_HW_SS_CRB_AGT_ADR = 0x20,
|
||||
QLCNIC_HW_RPMX3_CRB_AGT_ADR = 0x0b,
|
||||
QLCNIC_HW_QMS_CRB_AGT_ADR = 0x00,
|
||||
QLCNIC_HW_SQGS0_CRB_AGT_ADR = 0x01,
|
||||
QLCNIC_HW_SQGS1_CRB_AGT_ADR = 0x02,
|
||||
QLCNIC_HW_SQGS2_CRB_AGT_ADR = 0x03,
|
||||
QLCNIC_HW_SQGS3_CRB_AGT_ADR = 0x04,
|
||||
QLCNIC_HW_C2C0_CRB_AGT_ADR = 0x58,
|
||||
QLCNIC_HW_C2C1_CRB_AGT_ADR = 0x59,
|
||||
QLCNIC_HW_C2C2_CRB_AGT_ADR = 0x5a,
|
||||
QLCNIC_HW_RPMX2_CRB_AGT_ADR = 0x0a,
|
||||
QLCNIC_HW_RPMX4_CRB_AGT_ADR = 0x0c,
|
||||
QLCNIC_HW_RPMX7_CRB_AGT_ADR = 0x0f,
|
||||
QLCNIC_HW_RPMX9_CRB_AGT_ADR = 0x12,
|
||||
QLCNIC_HW_SMB_CRB_AGT_ADR = 0x18
|
||||
};
|
||||
|
||||
/* Hub 2 */
|
||||
enum {
|
||||
QLCNIC_HW_NIU_CRB_AGT_ADR = 0x31,
|
||||
QLCNIC_HW_I2C0_CRB_AGT_ADR = 0x19,
|
||||
QLCNIC_HW_I2C1_CRB_AGT_ADR = 0x29,
|
||||
|
||||
QLCNIC_HW_SN_CRB_AGT_ADR = 0x10,
|
||||
QLCNIC_HW_I2Q_CRB_AGT_ADR = 0x20,
|
||||
QLCNIC_HW_LPC_CRB_AGT_ADR = 0x22,
|
||||
QLCNIC_HW_ROMUSB_CRB_AGT_ADR = 0x21,
|
||||
QLCNIC_HW_QM_CRB_AGT_ADR = 0x66,
|
||||
QLCNIC_HW_SQG0_CRB_AGT_ADR = 0x60,
|
||||
QLCNIC_HW_SQG1_CRB_AGT_ADR = 0x61,
|
||||
QLCNIC_HW_SQG2_CRB_AGT_ADR = 0x62,
|
||||
QLCNIC_HW_SQG3_CRB_AGT_ADR = 0x63,
|
||||
QLCNIC_HW_RPMX1_CRB_AGT_ADR = 0x09,
|
||||
QLCNIC_HW_RPMX5_CRB_AGT_ADR = 0x0d,
|
||||
QLCNIC_HW_RPMX6_CRB_AGT_ADR = 0x0e,
|
||||
QLCNIC_HW_RPMX8_CRB_AGT_ADR = 0x11
|
||||
};
|
||||
|
||||
/* Hub 3 */
|
||||
enum {
|
||||
QLCNIC_HW_PH_CRB_AGT_ADR = 0x1A,
|
||||
QLCNIC_HW_SRE_CRB_AGT_ADR = 0x50,
|
||||
QLCNIC_HW_EG_CRB_AGT_ADR = 0x51,
|
||||
QLCNIC_HW_RPMX0_CRB_AGT_ADR = 0x08
|
||||
};
|
||||
|
||||
/* Hub 4 */
|
||||
enum {
|
||||
QLCNIC_HW_PEGN0_CRB_AGT_ADR = 0x40,
|
||||
QLCNIC_HW_PEGN1_CRB_AGT_ADR,
|
||||
QLCNIC_HW_PEGN2_CRB_AGT_ADR,
|
||||
QLCNIC_HW_PEGN3_CRB_AGT_ADR,
|
||||
QLCNIC_HW_PEGNI_CRB_AGT_ADR,
|
||||
QLCNIC_HW_PEGND_CRB_AGT_ADR,
|
||||
QLCNIC_HW_PEGNC_CRB_AGT_ADR,
|
||||
QLCNIC_HW_PEGR0_CRB_AGT_ADR,
|
||||
QLCNIC_HW_PEGR1_CRB_AGT_ADR,
|
||||
QLCNIC_HW_PEGR2_CRB_AGT_ADR,
|
||||
QLCNIC_HW_PEGR3_CRB_AGT_ADR,
|
||||
QLCNIC_HW_PEGN4_CRB_AGT_ADR
|
||||
};
|
||||
|
||||
/* Hub 5 */
|
||||
enum {
|
||||
QLCNIC_HW_PEGS0_CRB_AGT_ADR = 0x40,
|
||||
QLCNIC_HW_PEGS1_CRB_AGT_ADR,
|
||||
QLCNIC_HW_PEGS2_CRB_AGT_ADR,
|
||||
QLCNIC_HW_PEGS3_CRB_AGT_ADR,
|
||||
QLCNIC_HW_PEGSI_CRB_AGT_ADR,
|
||||
QLCNIC_HW_PEGSD_CRB_AGT_ADR,
|
||||
QLCNIC_HW_PEGSC_CRB_AGT_ADR
|
||||
};
|
||||
|
||||
/* Hub 6 */
|
||||
enum {
|
||||
QLCNIC_HW_CAS0_CRB_AGT_ADR = 0x46,
|
||||
QLCNIC_HW_CAS1_CRB_AGT_ADR = 0x47,
|
||||
QLCNIC_HW_CAS2_CRB_AGT_ADR = 0x48,
|
||||
QLCNIC_HW_CAS3_CRB_AGT_ADR = 0x49,
|
||||
QLCNIC_HW_NCM_CRB_AGT_ADR = 0x16,
|
||||
QLCNIC_HW_TMR_CRB_AGT_ADR = 0x17,
|
||||
QLCNIC_HW_XDMA_CRB_AGT_ADR = 0x05,
|
||||
QLCNIC_HW_OCM0_CRB_AGT_ADR = 0x06,
|
||||
QLCNIC_HW_OCM1_CRB_AGT_ADR = 0x07
|
||||
};
|
||||
|
||||
/* Floaters - non existent modules */
|
||||
#define QLCNIC_HW_EFC_RPMX0_CRB_AGT_ADR 0x67
|
||||
|
||||
/* This field defines PCI/X adr [25:20] of agents on the CRB */
|
||||
enum {
|
||||
QLCNIC_HW_PX_MAP_CRB_PH = 0,
|
||||
QLCNIC_HW_PX_MAP_CRB_PS,
|
||||
QLCNIC_HW_PX_MAP_CRB_MN,
|
||||
QLCNIC_HW_PX_MAP_CRB_MS,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGR1,
|
||||
QLCNIC_HW_PX_MAP_CRB_SRE,
|
||||
QLCNIC_HW_PX_MAP_CRB_NIU,
|
||||
QLCNIC_HW_PX_MAP_CRB_QMN,
|
||||
QLCNIC_HW_PX_MAP_CRB_SQN0,
|
||||
QLCNIC_HW_PX_MAP_CRB_SQN1,
|
||||
QLCNIC_HW_PX_MAP_CRB_SQN2,
|
||||
QLCNIC_HW_PX_MAP_CRB_SQN3,
|
||||
QLCNIC_HW_PX_MAP_CRB_QMS,
|
||||
QLCNIC_HW_PX_MAP_CRB_SQS0,
|
||||
QLCNIC_HW_PX_MAP_CRB_SQS1,
|
||||
QLCNIC_HW_PX_MAP_CRB_SQS2,
|
||||
QLCNIC_HW_PX_MAP_CRB_SQS3,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGN0,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGN1,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGN2,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGN3,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGND,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGNI,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGS0,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGS1,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGS2,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGS3,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGSD,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGSI,
|
||||
QLCNIC_HW_PX_MAP_CRB_SN,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGR2,
|
||||
QLCNIC_HW_PX_MAP_CRB_EG,
|
||||
QLCNIC_HW_PX_MAP_CRB_PH2,
|
||||
QLCNIC_HW_PX_MAP_CRB_PS2,
|
||||
QLCNIC_HW_PX_MAP_CRB_CAM,
|
||||
QLCNIC_HW_PX_MAP_CRB_CAS0,
|
||||
QLCNIC_HW_PX_MAP_CRB_CAS1,
|
||||
QLCNIC_HW_PX_MAP_CRB_CAS2,
|
||||
QLCNIC_HW_PX_MAP_CRB_C2C0,
|
||||
QLCNIC_HW_PX_MAP_CRB_C2C1,
|
||||
QLCNIC_HW_PX_MAP_CRB_TIMR,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGR3,
|
||||
QLCNIC_HW_PX_MAP_CRB_RPMX1,
|
||||
QLCNIC_HW_PX_MAP_CRB_RPMX2,
|
||||
QLCNIC_HW_PX_MAP_CRB_RPMX3,
|
||||
QLCNIC_HW_PX_MAP_CRB_RPMX4,
|
||||
QLCNIC_HW_PX_MAP_CRB_RPMX5,
|
||||
QLCNIC_HW_PX_MAP_CRB_RPMX6,
|
||||
QLCNIC_HW_PX_MAP_CRB_RPMX7,
|
||||
QLCNIC_HW_PX_MAP_CRB_XDMA,
|
||||
QLCNIC_HW_PX_MAP_CRB_I2Q,
|
||||
QLCNIC_HW_PX_MAP_CRB_ROMUSB,
|
||||
QLCNIC_HW_PX_MAP_CRB_CAS3,
|
||||
QLCNIC_HW_PX_MAP_CRB_RPMX0,
|
||||
QLCNIC_HW_PX_MAP_CRB_RPMX8,
|
||||
QLCNIC_HW_PX_MAP_CRB_RPMX9,
|
||||
QLCNIC_HW_PX_MAP_CRB_OCM0,
|
||||
QLCNIC_HW_PX_MAP_CRB_OCM1,
|
||||
QLCNIC_HW_PX_MAP_CRB_SMB,
|
||||
QLCNIC_HW_PX_MAP_CRB_I2C0,
|
||||
QLCNIC_HW_PX_MAP_CRB_I2C1,
|
||||
QLCNIC_HW_PX_MAP_CRB_LPC,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGNC,
|
||||
QLCNIC_HW_PX_MAP_CRB_PGR0
|
||||
};
|
||||
|
||||
#define BIT_0 0x1
|
||||
#define BIT_1 0x2
|
||||
#define BIT_2 0x4
|
||||
#define BIT_3 0x8
|
||||
#define BIT_4 0x10
|
||||
#define BIT_5 0x20
|
||||
#define BIT_6 0x40
|
||||
#define BIT_7 0x80
|
||||
#define BIT_8 0x100
|
||||
#define BIT_9 0x200
|
||||
#define BIT_10 0x400
|
||||
#define BIT_11 0x800
|
||||
#define BIT_12 0x1000
|
||||
#define BIT_13 0x2000
|
||||
#define BIT_14 0x4000
|
||||
#define BIT_15 0x8000
|
||||
#define BIT_16 0x10000
|
||||
#define BIT_17 0x20000
|
||||
#define BIT_18 0x40000
|
||||
#define BIT_19 0x80000
|
||||
#define BIT_20 0x100000
|
||||
#define BIT_21 0x200000
|
||||
#define BIT_22 0x400000
|
||||
#define BIT_23 0x800000
|
||||
#define BIT_24 0x1000000
|
||||
#define BIT_25 0x2000000
|
||||
#define BIT_26 0x4000000
|
||||
#define BIT_27 0x8000000
|
||||
#define BIT_28 0x10000000
|
||||
#define BIT_29 0x20000000
|
||||
#define BIT_30 0x40000000
|
||||
#define BIT_31 0x80000000
|
||||
|
||||
/* This field defines CRB adr [31:20] of the agents */
|
||||
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_MN \
|
||||
((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MN_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PH \
|
||||
((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_PH_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_MS \
|
||||
((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MS_CRB_AGT_ADR)
|
||||
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PS \
|
||||
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_PS_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SS \
|
||||
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SS_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3 \
|
||||
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX3_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_QMS \
|
||||
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_QMS_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS0 \
|
||||
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS0_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS1 \
|
||||
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS1_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS2 \
|
||||
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS2_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS3 \
|
||||
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS3_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C0 \
|
||||
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C0_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C1 \
|
||||
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C1_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2 \
|
||||
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX2_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4 \
|
||||
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX4_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7 \
|
||||
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX7_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9 \
|
||||
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX9_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SMB \
|
||||
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SMB_CRB_AGT_ADR)
|
||||
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_NIU \
|
||||
((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_NIU_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0 \
|
||||
((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C0_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1 \
|
||||
((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C1_CRB_AGT_ADR)
|
||||
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SRE \
|
||||
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SRE_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_EG \
|
||||
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_EG_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0 \
|
||||
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX0_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_QMN \
|
||||
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_QM_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0 \
|
||||
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG0_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1 \
|
||||
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG1_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2 \
|
||||
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG2_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3 \
|
||||
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG3_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1 \
|
||||
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX1_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5 \
|
||||
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX5_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6 \
|
||||
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX6_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8 \
|
||||
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX8_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS0 \
|
||||
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS0_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS1 \
|
||||
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS1_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS2 \
|
||||
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS2_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS3 \
|
||||
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS3_CRB_AGT_ADR)
|
||||
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI \
|
||||
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNI_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGND \
|
||||
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGND_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0 \
|
||||
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN0_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1 \
|
||||
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN1_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2 \
|
||||
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN2_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3 \
|
||||
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN3_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4 \
|
||||
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN4_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC \
|
||||
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNC_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR0 \
|
||||
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR0_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR1 \
|
||||
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR1_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR2 \
|
||||
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR2_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR3 \
|
||||
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR3_CRB_AGT_ADR)
|
||||
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI \
|
||||
((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSI_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSD \
|
||||
((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSD_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0 \
|
||||
((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS0_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1 \
|
||||
((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS1_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2 \
|
||||
((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS2_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3 \
|
||||
((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS3_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSC \
|
||||
((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSC_CRB_AGT_ADR)
|
||||
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAM \
|
||||
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_NCM_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR \
|
||||
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_TMR_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA \
|
||||
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_XDMA_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SN \
|
||||
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_SN_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q \
|
||||
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_I2Q_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB \
|
||||
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_ROMUSB_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0 \
|
||||
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM0_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM1 \
|
||||
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM1_CRB_AGT_ADR)
|
||||
#define QLCNIC_HW_CRB_HUB_AGT_ADR_LPC \
|
||||
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_LPC_CRB_AGT_ADR)
|
||||
|
||||
#define QLCNIC_SRE_MISC (QLCNIC_CRB_SRE + 0x0002c)
|
||||
|
||||
#define QLCNIC_I2Q_CLR_PCI_HI (QLCNIC_CRB_I2Q + 0x00034)
|
||||
|
||||
#define ROMUSB_GLB (QLCNIC_CRB_ROMUSB + 0x00000)
|
||||
#define ROMUSB_ROM (QLCNIC_CRB_ROMUSB + 0x10000)
|
||||
|
||||
#define QLCNIC_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
|
||||
#define QLCNIC_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
|
||||
#define QLCNIC_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c)
|
||||
#define QLCNIC_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
|
||||
#define QLCNIC_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044)
|
||||
#define QLCNIC_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
|
||||
#define QLCNIC_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00A8)
|
||||
|
||||
#define QLCNIC_ROMUSB_GPIO(n) (ROMUSB_GLB + 0x60 + (4 * (n)))
|
||||
|
||||
#define QLCNIC_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
|
||||
#define QLCNIC_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
|
||||
#define QLCNIC_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
|
||||
#define QLCNIC_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
|
||||
#define QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
|
||||
#define QLCNIC_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Definitions specific to M25P flash
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* all are 1MB windows */
|
||||
|
||||
#define QLCNIC_PCI_CRB_WINDOWSIZE 0x00100000
|
||||
#define QLCNIC_PCI_CRB_WINDOW(A) \
|
||||
(QLCNIC_PCI_CRBSPACE + (A)*QLCNIC_PCI_CRB_WINDOWSIZE)
|
||||
|
||||
#define QLCNIC_CRB_NIU QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_NIU)
|
||||
#define QLCNIC_CRB_SRE QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SRE)
|
||||
#define QLCNIC_CRB_ROMUSB \
|
||||
QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_ROMUSB)
|
||||
#define QLCNIC_CRB_EPG QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_EG)
|
||||
#define QLCNIC_CRB_I2Q QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2Q)
|
||||
#define QLCNIC_CRB_TIMER QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_TIMR)
|
||||
#define QLCNIC_CRB_I2C0 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2C0)
|
||||
#define QLCNIC_CRB_SMB QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SMB)
|
||||
#define QLCNIC_CRB_MAX QLCNIC_PCI_CRB_WINDOW(64)
|
||||
|
||||
#define QLCNIC_CRB_PCIX_HOST QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH)
|
||||
#define QLCNIC_CRB_PCIX_HOST2 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH2)
|
||||
#define QLCNIC_CRB_PEG_NET_0 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN0)
|
||||
#define QLCNIC_CRB_PEG_NET_1 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN1)
|
||||
#define QLCNIC_CRB_PEG_NET_2 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN2)
|
||||
#define QLCNIC_CRB_PEG_NET_3 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN3)
|
||||
#define QLCNIC_CRB_PEG_NET_4 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SQS2)
|
||||
#define QLCNIC_CRB_PEG_NET_D QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGND)
|
||||
#define QLCNIC_CRB_PEG_NET_I QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGNI)
|
||||
#define QLCNIC_CRB_DDR_NET QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_MN)
|
||||
#define QLCNIC_CRB_QDR_NET QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SN)
|
||||
|
||||
#define QLCNIC_CRB_PCIX_MD QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PS)
|
||||
#define QLCNIC_CRB_PCIE QLCNIC_CRB_PCIX_MD
|
||||
|
||||
#define ISR_INT_VECTOR (QLCNIC_PCIX_PS_REG(PCIX_INT_VECTOR))
|
||||
#define ISR_INT_MASK (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK))
|
||||
#define ISR_INT_MASK_SLOW (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK))
|
||||
#define ISR_INT_TARGET_STATUS (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS))
|
||||
#define ISR_INT_TARGET_MASK (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK))
|
||||
#define ISR_INT_TARGET_STATUS_F1 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
|
||||
#define ISR_INT_TARGET_MASK_F1 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
|
||||
#define ISR_INT_TARGET_STATUS_F2 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
|
||||
#define ISR_INT_TARGET_MASK_F2 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
|
||||
#define ISR_INT_TARGET_STATUS_F3 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
|
||||
#define ISR_INT_TARGET_MASK_F3 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
|
||||
#define ISR_INT_TARGET_STATUS_F4 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
|
||||
#define ISR_INT_TARGET_MASK_F4 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
|
||||
#define ISR_INT_TARGET_STATUS_F5 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
|
||||
#define ISR_INT_TARGET_MASK_F5 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
|
||||
#define ISR_INT_TARGET_STATUS_F6 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
|
||||
#define ISR_INT_TARGET_MASK_F6 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
|
||||
#define ISR_INT_TARGET_STATUS_F7 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
|
||||
#define ISR_INT_TARGET_MASK_F7 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
|
||||
|
||||
#define QLCNIC_PCI_OCM0_2M (0x000c0000UL)
|
||||
#define QLCNIC_PCI_CRBSPACE (0x06000000UL)
|
||||
#define QLCNIC_PCI_CAMQM (0x04800000UL)
|
||||
#define QLCNIC_PCI_CAMQM_END (0x04800800UL)
|
||||
#define QLCNIC_PCI_CAMQM_2M_BASE (0x000ff800UL)
|
||||
|
||||
#define QLCNIC_CRB_CAM QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_CAM)
|
||||
|
||||
#define QLCNIC_ADDR_DDR_NET (0x0000000000000000ULL)
|
||||
#define QLCNIC_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
|
||||
#define QLCNIC_ADDR_OCM0 (0x0000000200000000ULL)
|
||||
#define QLCNIC_ADDR_OCM0_MAX (0x00000002000fffffULL)
|
||||
#define QLCNIC_ADDR_OCM1 (0x0000000200400000ULL)
|
||||
#define QLCNIC_ADDR_OCM1_MAX (0x00000002004fffffULL)
|
||||
#define QLCNIC_ADDR_QDR_NET (0x0000000300000000ULL)
|
||||
#define QLCNIC_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
|
||||
|
||||
/*
|
||||
* Register offsets for MN
|
||||
*/
|
||||
#define QLCNIC_MIU_CONTROL (0x000)
|
||||
#define QLCNIC_MIU_MN_CONTROL (QLCNIC_CRB_DDR_NET+QLCNIC_MIU_CONTROL)
|
||||
|
||||
/* 200ms delay in each loop */
|
||||
#define QLCNIC_NIU_PHY_WAITLEN 200000
|
||||
/* 10 seconds before we give up */
|
||||
#define QLCNIC_NIU_PHY_WAITMAX 50
|
||||
#define QLCNIC_NIU_MAX_GBE_PORTS 4
|
||||
#define QLCNIC_NIU_MAX_XG_PORTS 2
|
||||
|
||||
#define QLCNIC_NIU_MODE (QLCNIC_CRB_NIU + 0x00000)
|
||||
#define QLCNIC_NIU_GB_PAUSE_CTL (QLCNIC_CRB_NIU + 0x0030c)
|
||||
#define QLCNIC_NIU_XG_PAUSE_CTL (QLCNIC_CRB_NIU + 0x00098)
|
||||
|
||||
#define QLCNIC_NIU_GB_MAC_CONFIG_0(I) \
|
||||
(QLCNIC_CRB_NIU + 0x30000 + (I)*0x10000)
|
||||
#define QLCNIC_NIU_GB_MAC_CONFIG_1(I) \
|
||||
(QLCNIC_CRB_NIU + 0x30004 + (I)*0x10000)
|
||||
|
||||
#define MAX_CTL_CHECK 1000
|
||||
#define TEST_AGT_CTRL (0x00)
|
||||
|
||||
#define TA_CTL_START BIT_0
|
||||
#define TA_CTL_ENABLE BIT_1
|
||||
#define TA_CTL_WRITE BIT_2
|
||||
#define TA_CTL_BUSY BIT_3
|
||||
|
||||
/* XG Link status */
|
||||
#define XG_LINK_UP 0x10
|
||||
#define XG_LINK_DOWN 0x20
|
||||
|
||||
#define XG_LINK_UP_P3P 0x01
|
||||
#define XG_LINK_DOWN_P3P 0x02
|
||||
#define XG_LINK_STATE_P3P_MASK 0xf
|
||||
#define XG_LINK_STATE_P3P(pcifn, val) \
|
||||
(((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3P_MASK)
|
||||
|
||||
#define P3P_LINK_SPEED_MHZ 100
|
||||
#define P3P_LINK_SPEED_MASK 0xff
|
||||
#define P3P_LINK_SPEED_REG(pcifn) \
|
||||
(CRB_PF_LINK_SPEED_1 + (((pcifn) / 4) * 4))
|
||||
#define P3P_LINK_SPEED_VAL(pcifn, reg) \
|
||||
(((reg) >> (8 * ((pcifn) & 0x3))) & P3P_LINK_SPEED_MASK)
|
||||
|
||||
#define QLCNIC_CAM_RAM_BASE (QLCNIC_CRB_CAM + 0x02000)
|
||||
#define QLCNIC_CAM_RAM(reg) (QLCNIC_CAM_RAM_BASE + (reg))
|
||||
#define QLCNIC_ROM_LOCK_ID (QLCNIC_CAM_RAM(0x100))
|
||||
#define QLCNIC_PHY_LOCK_ID (QLCNIC_CAM_RAM(0x120))
|
||||
#define QLCNIC_CRB_WIN_LOCK_ID (QLCNIC_CAM_RAM(0x124))
|
||||
|
||||
#define NIC_CRB_BASE (QLCNIC_CAM_RAM(0x200))
|
||||
#define NIC_CRB_BASE_2 (QLCNIC_CAM_RAM(0x700))
|
||||
#define QLCNIC_REG(X) (NIC_CRB_BASE+(X))
|
||||
#define QLCNIC_REG_2(X) (NIC_CRB_BASE_2+(X))
|
||||
|
||||
#define QLCNIC_CDRP_MAX_ARGS 4
|
||||
#define QLCNIC_CDRP_ARG(i) (QLCNIC_REG(0x18 + ((i) * 4)))
|
||||
|
||||
#define QLCNIC_CDRP_CRB_OFFSET (QLCNIC_REG(0x18))
|
||||
#define QLCNIC_SIGN_CRB_OFFSET (QLCNIC_REG(0x28))
|
||||
|
||||
#define CRB_XG_STATE_P3P (QLCNIC_REG(0x98))
|
||||
#define CRB_PF_LINK_SPEED_1 (QLCNIC_REG(0xe8))
|
||||
#define CRB_DRIVER_VERSION (QLCNIC_REG(0x2a0))
|
||||
|
||||
#define CRB_FW_CAPABILITIES_2 (QLCNIC_CAM_RAM(0x12c))
|
||||
|
||||
/*
|
||||
* CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address
|
||||
* which can be read by the Phantom host to get producer/consumer indexes from
|
||||
* Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following
|
||||
* registers will be used for the addresses of the ring's shared memory
|
||||
* on the Phantom.
|
||||
*/
|
||||
|
||||
#define qlcnic_get_temp_val(x) ((x) >> 16)
|
||||
#define qlcnic_get_temp_state(x) ((x) & 0xffff)
|
||||
#define qlcnic_encode_temp(val, state) (((val) << 16) | (state))
|
||||
|
||||
/*
|
||||
* Temperature control.
|
||||
*/
|
||||
enum {
|
||||
QLCNIC_TEMP_NORMAL = 0x1, /* Normal operating range */
|
||||
QLCNIC_TEMP_WARN, /* Sound alert, temperature getting high */
|
||||
QLCNIC_TEMP_PANIC /* Fatal error, hardware has shut down. */
|
||||
};
|
||||
|
||||
|
||||
/* Lock IDs for PHY lock */
|
||||
#define PHY_LOCK_DRIVER 0x44524956
|
||||
|
||||
#define PCIX_INT_VECTOR (0x10100)
|
||||
#define PCIX_INT_MASK (0x10104)
|
||||
|
||||
#define PCIX_OCM_WINDOW (0x10800)
|
||||
#define PCIX_OCM_WINDOW_REG(func) (PCIX_OCM_WINDOW + 0x4 * (func))
|
||||
|
||||
#define PCIX_TARGET_STATUS (0x10118)
|
||||
#define PCIX_TARGET_STATUS_F1 (0x10160)
|
||||
#define PCIX_TARGET_STATUS_F2 (0x10164)
|
||||
#define PCIX_TARGET_STATUS_F3 (0x10168)
|
||||
#define PCIX_TARGET_STATUS_F4 (0x10360)
|
||||
#define PCIX_TARGET_STATUS_F5 (0x10364)
|
||||
#define PCIX_TARGET_STATUS_F6 (0x10368)
|
||||
#define PCIX_TARGET_STATUS_F7 (0x1036c)
|
||||
|
||||
#define PCIX_TARGET_MASK (0x10128)
|
||||
#define PCIX_TARGET_MASK_F1 (0x10170)
|
||||
#define PCIX_TARGET_MASK_F2 (0x10174)
|
||||
#define PCIX_TARGET_MASK_F3 (0x10178)
|
||||
#define PCIX_TARGET_MASK_F4 (0x10370)
|
||||
#define PCIX_TARGET_MASK_F5 (0x10374)
|
||||
#define PCIX_TARGET_MASK_F6 (0x10378)
|
||||
#define PCIX_TARGET_MASK_F7 (0x1037c)
|
||||
|
||||
#define PCIX_MSI_F(i) (0x13000+((i)*4))
|
||||
|
||||
#define QLCNIC_PCIX_PH_REG(reg) (QLCNIC_CRB_PCIE + (reg))
|
||||
#define QLCNIC_PCIX_PS_REG(reg) (QLCNIC_CRB_PCIX_MD + (reg))
|
||||
#define QLCNIC_PCIE_REG(reg) (QLCNIC_CRB_PCIE + (reg))
|
||||
|
||||
#define PCIE_SEM0_LOCK (0x1c000)
|
||||
#define PCIE_SEM0_UNLOCK (0x1c004)
|
||||
#define PCIE_SEM_LOCK(N) (PCIE_SEM0_LOCK + 8*(N))
|
||||
#define PCIE_SEM_UNLOCK(N) (PCIE_SEM0_UNLOCK + 8*(N))
|
||||
|
||||
#define PCIE_SETUP_FUNCTION (0x12040)
|
||||
#define PCIE_SETUP_FUNCTION2 (0x12048)
|
||||
#define PCIE_MISCCFG_RC (0x1206c)
|
||||
#define PCIE_TGT_SPLIT_CHICKEN (0x12080)
|
||||
#define PCIE_CHICKEN3 (0x120c8)
|
||||
|
||||
#define ISR_INT_STATE_REG (QLCNIC_PCIX_PS_REG(PCIE_MISCCFG_RC))
|
||||
#define PCIE_MAX_MASTER_SPLIT (0x14048)
|
||||
|
||||
#define QLCNIC_PORT_MODE_NONE 0
|
||||
#define QLCNIC_PORT_MODE_XG 1
|
||||
#define QLCNIC_PORT_MODE_GB 2
|
||||
#define QLCNIC_PORT_MODE_802_3_AP 3
|
||||
#define QLCNIC_PORT_MODE_AUTO_NEG 4
|
||||
#define QLCNIC_PORT_MODE_AUTO_NEG_1G 5
|
||||
#define QLCNIC_PORT_MODE_AUTO_NEG_XG 6
|
||||
#define QLCNIC_PORT_MODE_ADDR (QLCNIC_CAM_RAM(0x24))
|
||||
#define QLCNIC_WOL_PORT_MODE (QLCNIC_CAM_RAM(0x198))
|
||||
|
||||
#define QLCNIC_WOL_CONFIG_NV (QLCNIC_CAM_RAM(0x184))
|
||||
#define QLCNIC_WOL_CONFIG (QLCNIC_CAM_RAM(0x188))
|
||||
|
||||
#define QLCNIC_PEG_TUNE_MN_PRESENT 0x1
|
||||
#define QLCNIC_PEG_TUNE_CAPABILITY (QLCNIC_CAM_RAM(0x02c))
|
||||
|
||||
#define QLCNIC_DMA_WATCHDOG_CTRL (QLCNIC_CAM_RAM(0x14))
|
||||
#define QLCNIC_ROM_DEV_INIT_TIMEOUT (0x3e885c)
|
||||
#define QLCNIC_ROM_DRV_RESET_TIMEOUT (0x3e8860)
|
||||
|
||||
/* Device State */
|
||||
#define QLCNIC_DEV_COLD 0x1
|
||||
#define QLCNIC_DEV_INITIALIZING 0x2
|
||||
#define QLCNIC_DEV_READY 0x3
|
||||
#define QLCNIC_DEV_NEED_RESET 0x4
|
||||
#define QLCNIC_DEV_NEED_QUISCENT 0x5
|
||||
#define QLCNIC_DEV_FAILED 0x6
|
||||
#define QLCNIC_DEV_QUISCENT 0x7
|
||||
|
||||
#define QLCNIC_DEV_BADBAD 0xbad0bad0
|
||||
|
||||
#define QLCNIC_DEV_NPAR_NON_OPER 0 /* NON Operational */
|
||||
#define QLCNIC_DEV_NPAR_OPER 1 /* NPAR Operational */
|
||||
#define QLCNIC_DEV_NPAR_OPER_TIMEO 30 /* Operational time out */
|
||||
|
||||
#define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4)))
|
||||
#define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4)))
|
||||
#define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4)))
|
||||
#define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4)))
|
||||
#define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL) &= ~(3 << (FN * 4)))
|
||||
|
||||
#define QLC_DEV_GET_DRV(VAL, FN) (0xf & ((VAL) >> (FN * 4)))
|
||||
#define QLC_DEV_SET_DRV(VAL, FN) ((VAL) << (FN * 4))
|
||||
|
||||
#define QLCNIC_TYPE_NIC 1
|
||||
#define QLCNIC_TYPE_FCOE 2
|
||||
#define QLCNIC_TYPE_ISCSI 3
|
||||
|
||||
#define QLCNIC_RCODE_DRIVER_INFO 0x20000000
|
||||
#define QLCNIC_RCODE_DRIVER_CAN_RELOAD BIT_30
|
||||
#define QLCNIC_RCODE_FATAL_ERROR BIT_31
|
||||
#define QLCNIC_FWERROR_PEGNUM(code) ((code) & 0xff)
|
||||
#define QLCNIC_FWERROR_CODE(code) ((code >> 8) & 0x1fffff)
|
||||
#define QLCNIC_FWERROR_FAN_FAILURE 0x16
|
||||
|
||||
#define FW_POLL_DELAY (1 * HZ)
|
||||
#define FW_FAIL_THRESH 2
|
||||
|
||||
#define QLCNIC_RESET_TIMEOUT_SECS 10
|
||||
#define QLCNIC_INIT_TIMEOUT_SECS 30
|
||||
#define QLCNIC_RCVPEG_CHECK_RETRY_COUNT 2000
|
||||
#define QLCNIC_RCVPEG_CHECK_DELAY 10
|
||||
#define QLCNIC_CMDPEG_CHECK_RETRY_COUNT 60
|
||||
#define QLCNIC_CMDPEG_CHECK_DELAY 500
|
||||
#define QLCNIC_HEARTBEAT_PERIOD_MSECS 200
|
||||
#define QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT 10
|
||||
|
||||
#define QLCNIC_MAX_MC_COUNT 38
|
||||
#define QLCNIC_MAX_UC_COUNT 512
|
||||
#define QLCNIC_WATCHDOG_TIMEOUTVALUE 5
|
||||
|
||||
#define ISR_MSI_INT_TRIGGER(FUNC) (QLCNIC_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
|
||||
#define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
|
||||
|
||||
/*
|
||||
* PCI Interrupt Vector Values.
|
||||
*/
|
||||
#define PCIX_INT_VECTOR_BIT_F0 0x0080
|
||||
#define PCIX_INT_VECTOR_BIT_F1 0x0100
|
||||
#define PCIX_INT_VECTOR_BIT_F2 0x0200
|
||||
#define PCIX_INT_VECTOR_BIT_F3 0x0400
|
||||
#define PCIX_INT_VECTOR_BIT_F4 0x0800
|
||||
#define PCIX_INT_VECTOR_BIT_F5 0x1000
|
||||
#define PCIX_INT_VECTOR_BIT_F6 0x2000
|
||||
#define PCIX_INT_VECTOR_BIT_F7 0x4000
|
||||
|
||||
struct qlcnic_legacy_intr_set {
|
||||
u32 int_vec_bit;
|
||||
u32 tgt_status_reg;
|
||||
u32 tgt_mask_reg;
|
||||
u32 pci_int_reg;
|
||||
};
|
||||
|
||||
#define QLCNIC_MSIX_BASE 0x132110
|
||||
#define QLCNIC_MAX_VLAN_FILTERS 64
|
||||
|
||||
#define FLASH_ROM_WINDOW 0x42110030
|
||||
#define FLASH_ROM_DATA 0x42150000
|
||||
|
||||
#define QLCNIC_FW_DUMP_REG1 0x00130060
|
||||
#define QLCNIC_FW_DUMP_REG2 0x001e0000
|
||||
#define QLCNIC_FLASH_SEM2_LK 0x0013C010
|
||||
#define QLCNIC_FLASH_SEM2_ULK 0x0013C014
|
||||
#define QLCNIC_FLASH_LOCK_ID 0x001B2100
|
||||
|
||||
/* PCI function operational mode */
|
||||
enum {
|
||||
QLCNIC_MGMT_FUNC = 0,
|
||||
QLCNIC_PRIV_FUNC = 1,
|
||||
QLCNIC_NON_PRIV_FUNC = 2,
|
||||
QLCNIC_SRIOV_PF_FUNC = 3,
|
||||
QLCNIC_SRIOV_VF_FUNC = 4,
|
||||
QLCNIC_UNKNOWN_FUNC_MODE = 5
|
||||
};
|
||||
|
||||
enum {
|
||||
QLCNIC_PORT_DEFAULTS = 0,
|
||||
QLCNIC_ADD_VLAN = 1,
|
||||
QLCNIC_DEL_VLAN = 2
|
||||
};
|
||||
|
||||
#define QLC_DEV_DRV_DEFAULT 0x11111111
|
||||
|
||||
#define LSB(x) ((uint8_t)(x))
|
||||
#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
|
||||
|
||||
#define LSW(x) ((uint16_t)((uint32_t)(x)))
|
||||
#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
|
||||
|
||||
#define LSD(x) ((uint32_t)((uint64_t)(x)))
|
||||
#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
|
||||
|
||||
#define QLCNIC_MS_CTRL 0x41000090
|
||||
#define QLCNIC_MS_ADDR_LO 0x41000094
|
||||
#define QLCNIC_MS_ADDR_HI 0x41000098
|
||||
#define QLCNIC_MS_WRTDATA_LO 0x410000A0
|
||||
#define QLCNIC_MS_WRTDATA_HI 0x410000A4
|
||||
#define QLCNIC_MS_WRTDATA_ULO 0x410000B0
|
||||
#define QLCNIC_MS_WRTDATA_UHI 0x410000B4
|
||||
#define QLCNIC_MS_RDDATA_LO 0x410000A8
|
||||
#define QLCNIC_MS_RDDATA_HI 0x410000AC
|
||||
#define QLCNIC_MS_RDDATA_ULO 0x410000B8
|
||||
#define QLCNIC_MS_RDDATA_UHI 0x410000BC
|
||||
|
||||
#define QLCNIC_TA_WRITE_ENABLE (TA_CTL_ENABLE | TA_CTL_WRITE)
|
||||
#define QLCNIC_TA_WRITE_START (TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE)
|
||||
#define QLCNIC_TA_START_ENABLE (TA_CTL_START | TA_CTL_ENABLE)
|
||||
|
||||
#define QLCNIC_LEGACY_INTR_CONFIG \
|
||||
{ \
|
||||
{ \
|
||||
.int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
|
||||
.tgt_status_reg = ISR_INT_TARGET_STATUS, \
|
||||
.tgt_mask_reg = ISR_INT_TARGET_MASK, }, \
|
||||
\
|
||||
{ \
|
||||
.int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
|
||||
.tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
|
||||
.tgt_mask_reg = ISR_INT_TARGET_MASK_F1, }, \
|
||||
\
|
||||
{ \
|
||||
.int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
|
||||
.tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
|
||||
.tgt_mask_reg = ISR_INT_TARGET_MASK_F2, }, \
|
||||
\
|
||||
{ \
|
||||
.int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
|
||||
.tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
|
||||
.tgt_mask_reg = ISR_INT_TARGET_MASK_F3, }, \
|
||||
\
|
||||
{ \
|
||||
.int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
|
||||
.tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
|
||||
.tgt_mask_reg = ISR_INT_TARGET_MASK_F4, }, \
|
||||
\
|
||||
{ \
|
||||
.int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
|
||||
.tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
|
||||
.tgt_mask_reg = ISR_INT_TARGET_MASK_F5, }, \
|
||||
\
|
||||
{ \
|
||||
.int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
|
||||
.tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
|
||||
.tgt_mask_reg = ISR_INT_TARGET_MASK_F6, }, \
|
||||
\
|
||||
{ \
|
||||
.int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
|
||||
.tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
|
||||
.tgt_mask_reg = ISR_INT_TARGET_MASK_F7, }, \
|
||||
}
|
||||
|
||||
/* NIU REGS */
|
||||
|
||||
#define _qlcnic_crb_get_bit(var, bit) ((var >> bit) & 0x1)
|
||||
|
||||
/*
|
||||
* NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
|
||||
*
|
||||
* Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
|
||||
* Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream
|
||||
* Bit 2 : enable_rx => 1:enable frame recv, 0:disable
|
||||
* Bit 3 : rx_synced => R/O: recv enable synched to recv stream
|
||||
* Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
|
||||
* Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
|
||||
* Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
|
||||
* Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
|
||||
* Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
|
||||
* Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
|
||||
* Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
|
||||
* Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
|
||||
*/
|
||||
#define qlcnic_gb_rx_flowctl(config_word) \
|
||||
((config_word) |= 1 << 5)
|
||||
#define qlcnic_gb_get_rx_flowctl(config_word) \
|
||||
_qlcnic_crb_get_bit((config_word), 5)
|
||||
#define qlcnic_gb_unset_rx_flowctl(config_word) \
|
||||
((config_word) &= ~(1 << 5))
|
||||
|
||||
/*
|
||||
* NIU GB Pause Ctl Register
|
||||
*/
|
||||
|
||||
#define qlcnic_gb_set_gb0_mask(config_word) \
|
||||
((config_word) |= 1 << 0)
|
||||
#define qlcnic_gb_set_gb1_mask(config_word) \
|
||||
((config_word) |= 1 << 2)
|
||||
#define qlcnic_gb_set_gb2_mask(config_word) \
|
||||
((config_word) |= 1 << 4)
|
||||
#define qlcnic_gb_set_gb3_mask(config_word) \
|
||||
((config_word) |= 1 << 6)
|
||||
|
||||
#define qlcnic_gb_get_gb0_mask(config_word) \
|
||||
_qlcnic_crb_get_bit((config_word), 0)
|
||||
#define qlcnic_gb_get_gb1_mask(config_word) \
|
||||
_qlcnic_crb_get_bit((config_word), 2)
|
||||
#define qlcnic_gb_get_gb2_mask(config_word) \
|
||||
_qlcnic_crb_get_bit((config_word), 4)
|
||||
#define qlcnic_gb_get_gb3_mask(config_word) \
|
||||
_qlcnic_crb_get_bit((config_word), 6)
|
||||
|
||||
#define qlcnic_gb_unset_gb0_mask(config_word) \
|
||||
((config_word) &= ~(1 << 0))
|
||||
#define qlcnic_gb_unset_gb1_mask(config_word) \
|
||||
((config_word) &= ~(1 << 2))
|
||||
#define qlcnic_gb_unset_gb2_mask(config_word) \
|
||||
((config_word) &= ~(1 << 4))
|
||||
#define qlcnic_gb_unset_gb3_mask(config_word) \
|
||||
((config_word) &= ~(1 << 6))
|
||||
|
||||
/*
|
||||
* NIU XG Pause Ctl Register
|
||||
*
|
||||
* Bit 0 : xg0_mask => 1:disable tx pause frames
|
||||
* Bit 1 : xg0_request => 1:request single pause frame
|
||||
* Bit 2 : xg0_on_off => 1:request is pause on, 0:off
|
||||
* Bit 3 : xg1_mask => 1:disable tx pause frames
|
||||
* Bit 4 : xg1_request => 1:request single pause frame
|
||||
* Bit 5 : xg1_on_off => 1:request is pause on, 0:off
|
||||
*/
|
||||
|
||||
#define qlcnic_xg_set_xg0_mask(config_word) \
|
||||
((config_word) |= 1 << 0)
|
||||
#define qlcnic_xg_set_xg1_mask(config_word) \
|
||||
((config_word) |= 1 << 3)
|
||||
|
||||
#define qlcnic_xg_get_xg0_mask(config_word) \
|
||||
_qlcnic_crb_get_bit((config_word), 0)
|
||||
#define qlcnic_xg_get_xg1_mask(config_word) \
|
||||
_qlcnic_crb_get_bit((config_word), 3)
|
||||
|
||||
#define qlcnic_xg_unset_xg0_mask(config_word) \
|
||||
((config_word) &= ~(1 << 0))
|
||||
#define qlcnic_xg_unset_xg1_mask(config_word) \
|
||||
((config_word) &= ~(1 << 3))
|
||||
|
||||
/*
|
||||
* NIU XG Pause Ctl Register
|
||||
*
|
||||
* Bit 0 : xg0_mask => 1:disable tx pause frames
|
||||
* Bit 1 : xg0_request => 1:request single pause frame
|
||||
* Bit 2 : xg0_on_off => 1:request is pause on, 0:off
|
||||
* Bit 3 : xg1_mask => 1:disable tx pause frames
|
||||
* Bit 4 : xg1_request => 1:request single pause frame
|
||||
* Bit 5 : xg1_on_off => 1:request is pause on, 0:off
|
||||
*/
|
||||
|
||||
/*
|
||||
* PHY-Specific MII control/status registers.
|
||||
*/
|
||||
#define QLCNIC_NIU_GB_MII_MGMT_ADDR_AUTONEG 4
|
||||
#define QLCNIC_NIU_GB_MII_MGMT_ADDR_PHY_STATUS 17
|
||||
|
||||
/*
|
||||
* PHY-Specific Status Register (reg 17).
|
||||
*
|
||||
* Bit 0 : jabber => 1:jabber detected, 0:not
|
||||
* Bit 1 : polarity => 1:polarity reversed, 0:normal
|
||||
* Bit 2 : recvpause => 1:receive pause enabled, 0:disabled
|
||||
* Bit 3 : xmitpause => 1:transmit pause enabled, 0:disabled
|
||||
* Bit 4 : energydetect => 1:sleep, 0:active
|
||||
* Bit 5 : downshift => 1:downshift, 0:no downshift
|
||||
* Bit 6 : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
|
||||
* Bits 7-9 : cablelen => not valid in 10Mb/s mode
|
||||
* 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
|
||||
* Bit 10 : link => 1:link up, 0:link down
|
||||
* Bit 11 : resolved => 1:speed and duplex resolved, 0:not yet
|
||||
* Bit 12 : pagercvd => 1:page received, 0:page not received
|
||||
* Bit 13 : duplex => 1:full duplex, 0:half duplex
|
||||
* Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
|
||||
*/
|
||||
|
||||
#define qlcnic_get_phy_speed(config_word) (((config_word) >> 14) & 0x03)
|
||||
|
||||
#define qlcnic_set_phy_speed(config_word, val) \
|
||||
((config_word) |= ((val & 0x03) << 14))
|
||||
#define qlcnic_set_phy_duplex(config_word) \
|
||||
((config_word) |= 1 << 13)
|
||||
#define qlcnic_clear_phy_duplex(config_word) \
|
||||
((config_word) &= ~(1 << 13))
|
||||
|
||||
#define qlcnic_get_phy_link(config_word) \
|
||||
_qlcnic_crb_get_bit(config_word, 10)
|
||||
#define qlcnic_get_phy_duplex(config_word) \
|
||||
_qlcnic_crb_get_bit(config_word, 13)
|
||||
|
||||
#define QLCNIC_NIU_NON_PROMISC_MODE 0
|
||||
#define QLCNIC_NIU_PROMISC_MODE 1
|
||||
#define QLCNIC_NIU_ALLMULTI_MODE 2
|
||||
|
||||
#define QLCNIC_PCIE_SEM_TIMEOUT 10000
|
||||
|
||||
struct crb_128M_2M_sub_block_map {
|
||||
unsigned valid;
|
||||
unsigned start_128M;
|
||||
unsigned end_128M;
|
||||
unsigned start_2M;
|
||||
};
|
||||
|
||||
struct crb_128M_2M_block_map{
|
||||
struct crb_128M_2M_sub_block_map sub_block[16];
|
||||
};
|
||||
#endif /* __QLCNIC_HDR_H_ */
|
||||
1686
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
Normal file
1686
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
Normal file
File diff suppressed because it is too large
Load diff
225
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.h
Normal file
225
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.h
Normal file
|
|
@ -0,0 +1,225 @@
|
|||
/*
|
||||
* QLogic qlcnic NIC Driver
|
||||
* Copyright (c) 2009-2013 QLogic Corporation
|
||||
*
|
||||
* See LICENSE.qlcnic for copyright and licensing details.
|
||||
*/
|
||||
|
||||
#ifndef __QLCNIC_HW_H
|
||||
#define __QLCNIC_HW_H
|
||||
|
||||
/* Common registers in 83xx and 82xx */
|
||||
enum qlcnic_regs {
|
||||
QLCNIC_PEG_HALT_STATUS1 = 0,
|
||||
QLCNIC_PEG_HALT_STATUS2,
|
||||
QLCNIC_PEG_ALIVE_COUNTER,
|
||||
QLCNIC_FLASH_LOCK_OWNER,
|
||||
QLCNIC_FW_CAPABILITIES,
|
||||
QLCNIC_CRB_DRV_ACTIVE,
|
||||
QLCNIC_CRB_DEV_STATE,
|
||||
QLCNIC_CRB_DRV_STATE,
|
||||
QLCNIC_CRB_DRV_SCRATCH,
|
||||
QLCNIC_CRB_DEV_PARTITION_INFO,
|
||||
QLCNIC_CRB_DRV_IDC_VER,
|
||||
QLCNIC_FW_VERSION_MAJOR,
|
||||
QLCNIC_FW_VERSION_MINOR,
|
||||
QLCNIC_FW_VERSION_SUB,
|
||||
QLCNIC_CRB_DEV_NPAR_STATE,
|
||||
QLCNIC_FW_IMG_VALID,
|
||||
QLCNIC_CMDPEG_STATE,
|
||||
QLCNIC_RCVPEG_STATE,
|
||||
QLCNIC_ASIC_TEMP,
|
||||
QLCNIC_FW_API,
|
||||
QLCNIC_DRV_OP_MODE,
|
||||
QLCNIC_FLASH_LOCK,
|
||||
QLCNIC_FLASH_UNLOCK,
|
||||
};
|
||||
|
||||
/* Read from an address offset from BAR0, existing registers */
|
||||
#define QLC_SHARED_REG_RD32(a, addr) \
|
||||
readl(((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
|
||||
|
||||
/* Write to an address offset from BAR0, existing registers */
|
||||
#define QLC_SHARED_REG_WR32(a, addr, value) \
|
||||
writel(value, ((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
|
||||
|
||||
/* Read from a direct address offset from BAR0, additional registers */
|
||||
#define QLCRDX(ahw, addr) \
|
||||
readl(((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr]))
|
||||
|
||||
/* Write to a direct address offset from BAR0, additional registers */
|
||||
#define QLCWRX(ahw, addr, value) \
|
||||
writel(value, (((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr])))
|
||||
|
||||
#define QLCNIC_CMD_CONFIGURE_IP_ADDR 0x1
|
||||
#define QLCNIC_CMD_CONFIG_INTRPT 0x2
|
||||
#define QLCNIC_CMD_CREATE_RX_CTX 0x7
|
||||
#define QLCNIC_CMD_DESTROY_RX_CTX 0x8
|
||||
#define QLCNIC_CMD_CREATE_TX_CTX 0x9
|
||||
#define QLCNIC_CMD_DESTROY_TX_CTX 0xa
|
||||
#define QLCNIC_CMD_CONFIGURE_LRO 0xC
|
||||
#define QLCNIC_CMD_CONFIGURE_MAC_LEARNING 0xD
|
||||
#define QLCNIC_CMD_GET_STATISTICS 0xF
|
||||
#define QLCNIC_CMD_INTRPT_TEST 0x11
|
||||
#define QLCNIC_CMD_SET_MTU 0x12
|
||||
#define QLCNIC_CMD_READ_PHY 0x13
|
||||
#define QLCNIC_CMD_WRITE_PHY 0x14
|
||||
#define QLCNIC_CMD_READ_HW_REG 0x15
|
||||
#define QLCNIC_CMD_GET_FLOW_CTL 0x16
|
||||
#define QLCNIC_CMD_SET_FLOW_CTL 0x17
|
||||
#define QLCNIC_CMD_READ_MAX_MTU 0x18
|
||||
#define QLCNIC_CMD_READ_MAX_LRO 0x19
|
||||
#define QLCNIC_CMD_MAC_ADDRESS 0x1f
|
||||
#define QLCNIC_CMD_GET_PCI_INFO 0x20
|
||||
#define QLCNIC_CMD_GET_NIC_INFO 0x21
|
||||
#define QLCNIC_CMD_SET_NIC_INFO 0x22
|
||||
#define QLCNIC_CMD_GET_ESWITCH_CAPABILITY 0x24
|
||||
#define QLCNIC_CMD_TOGGLE_ESWITCH 0x25
|
||||
#define QLCNIC_CMD_GET_ESWITCH_STATUS 0x26
|
||||
#define QLCNIC_CMD_SET_PORTMIRRORING 0x27
|
||||
#define QLCNIC_CMD_CONFIGURE_ESWITCH 0x28
|
||||
#define QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG 0x29
|
||||
#define QLCNIC_CMD_GET_ESWITCH_STATS 0x2a
|
||||
#define QLCNIC_CMD_CONFIG_PORT 0x2e
|
||||
#define QLCNIC_CMD_TEMP_SIZE 0x2f
|
||||
#define QLCNIC_CMD_GET_TEMP_HDR 0x30
|
||||
#define QLCNIC_CMD_BC_EVENT_SETUP 0x31
|
||||
#define QLCNIC_CMD_CONFIG_VPORT 0x32
|
||||
#define QLCNIC_CMD_DCB_QUERY_CAP 0x34
|
||||
#define QLCNIC_CMD_DCB_QUERY_PARAM 0x35
|
||||
#define QLCNIC_CMD_GET_MAC_STATS 0x37
|
||||
#define QLCNIC_CMD_82XX_SET_DRV_VER 0x38
|
||||
#define QLCNIC_CMD_MQ_TX_CONFIG_INTR 0x39
|
||||
#define QLCNIC_CMD_GET_LED_STATUS 0x3C
|
||||
#define QLCNIC_CMD_CONFIGURE_RSS 0x41
|
||||
#define QLCNIC_CMD_CONFIG_INTR_COAL 0x43
|
||||
#define QLCNIC_CMD_CONFIGURE_LED 0x44
|
||||
#define QLCNIC_CMD_CONFIG_MAC_VLAN 0x45
|
||||
#define QLCNIC_CMD_GET_LINK_EVENT 0x48
|
||||
#define QLCNIC_CMD_CONFIGURE_MAC_RX_MODE 0x49
|
||||
#define QLCNIC_CMD_CONFIGURE_HW_LRO 0x4A
|
||||
#define QLCNIC_CMD_SET_INGRESS_ENCAP 0x4E
|
||||
#define QLCNIC_CMD_INIT_NIC_FUNC 0x60
|
||||
#define QLCNIC_CMD_STOP_NIC_FUNC 0x61
|
||||
#define QLCNIC_CMD_IDC_ACK 0x63
|
||||
#define QLCNIC_CMD_SET_PORT_CONFIG 0x66
|
||||
#define QLCNIC_CMD_GET_PORT_CONFIG 0x67
|
||||
#define QLCNIC_CMD_GET_LINK_STATUS 0x68
|
||||
#define QLCNIC_CMD_SET_LED_CONFIG 0x69
|
||||
#define QLCNIC_CMD_GET_LED_CONFIG 0x6A
|
||||
#define QLCNIC_CMD_83XX_SET_DRV_VER 0x6F
|
||||
#define QLCNIC_CMD_ADD_RCV_RINGS 0x0B
|
||||
|
||||
#define QLCNIC_INTRPT_INTX 1
|
||||
#define QLCNIC_INTRPT_MSIX 3
|
||||
#define QLCNIC_INTRPT_ADD 1
|
||||
#define QLCNIC_INTRPT_DEL 2
|
||||
|
||||
#define QLCNIC_GET_CURRENT_MAC 1
|
||||
#define QLCNIC_SET_STATION_MAC 2
|
||||
#define QLCNIC_GET_DEFAULT_MAC 3
|
||||
#define QLCNIC_GET_FAC_DEF_MAC 4
|
||||
#define QLCNIC_SET_FAC_DEF_MAC 5
|
||||
|
||||
#define QLCNIC_MBX_LINK_EVENT 0x8001
|
||||
#define QLCNIC_MBX_BC_EVENT 0x8002
|
||||
#define QLCNIC_MBX_COMP_EVENT 0x8100
|
||||
#define QLCNIC_MBX_REQUEST_EVENT 0x8101
|
||||
#define QLCNIC_MBX_TIME_EXTEND_EVENT 0x8102
|
||||
#define QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT 0x8110
|
||||
#define QLCNIC_MBX_SFP_INSERT_EVENT 0x8130
|
||||
#define QLCNIC_MBX_SFP_REMOVE_EVENT 0x8131
|
||||
|
||||
struct qlcnic_mailbox_metadata {
|
||||
u32 cmd;
|
||||
u32 in_args;
|
||||
u32 out_args;
|
||||
};
|
||||
|
||||
/* Mailbox ownership */
|
||||
#define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
|
||||
|
||||
#define QLCNIC_SET_OWNER 1
|
||||
#define QLCNIC_CLR_OWNER 0
|
||||
#define QLCNIC_MBX_TIMEOUT 5000
|
||||
|
||||
#define QLCNIC_MBX_RSP_OK 1
|
||||
#define QLCNIC_MBX_PORT_RSP_OK 0x1a
|
||||
#define QLCNIC_MBX_ASYNC_EVENT BIT_15
|
||||
|
||||
/* Set HW Tx ring limit for 82xx adapter. */
|
||||
#define QLCNIC_MAX_HW_TX_RINGS 8
|
||||
#define QLCNIC_MAX_HW_VNIC_TX_RINGS 4
|
||||
#define QLCNIC_MAX_TX_RINGS 8
|
||||
#define QLCNIC_MAX_SDS_RINGS 8
|
||||
|
||||
struct qlcnic_pci_info;
|
||||
struct qlcnic_info;
|
||||
struct qlcnic_cmd_args;
|
||||
struct ethtool_stats;
|
||||
struct pci_device_id;
|
||||
struct qlcnic_host_sds_ring;
|
||||
struct qlcnic_host_tx_ring;
|
||||
struct qlcnic_hardware_context;
|
||||
struct qlcnic_adapter;
|
||||
struct qlcnic_fw_dump;
|
||||
|
||||
int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong, int *);
|
||||
int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *, ulong, u32);
|
||||
int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int);
|
||||
int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
|
||||
int qlcnic_82xx_napi_add(struct qlcnic_adapter *adapter,
|
||||
struct net_device *netdev);
|
||||
void qlcnic_82xx_get_beacon_state(struct qlcnic_adapter *);
|
||||
void qlcnic_82xx_change_filter(struct qlcnic_adapter *adapter,
|
||||
u64 *uaddr, u16 vlan_id);
|
||||
int qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *,
|
||||
struct ethtool_coalesce *);
|
||||
int qlcnic_82xx_set_rx_coalesce(struct qlcnic_adapter *);
|
||||
int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int);
|
||||
void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
|
||||
__be32, int);
|
||||
int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int);
|
||||
void qlcnic_82xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
|
||||
int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8);
|
||||
int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *, u8);
|
||||
void qlcnic_82xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
|
||||
void qlcnic_82xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
|
||||
int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
|
||||
struct qlcnic_cmd_args *);
|
||||
int qlcnic_82xx_mq_intrpt(struct qlcnic_adapter *, int);
|
||||
int qlcnic_82xx_config_intrpt(struct qlcnic_adapter *, u8);
|
||||
int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *);
|
||||
int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *,
|
||||
struct qlcnic_host_tx_ring *tx_ring, int);
|
||||
void qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter *);
|
||||
void qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter *,
|
||||
struct qlcnic_host_tx_ring *);
|
||||
int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, u16, u8);
|
||||
int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *, u8*, u8);
|
||||
int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
|
||||
int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
|
||||
int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
|
||||
int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *,
|
||||
struct qlcnic_adapter *, u32);
|
||||
int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *, ulong, u32);
|
||||
int qlcnic_82xx_get_board_info(struct qlcnic_adapter *);
|
||||
int qlcnic_82xx_config_led(struct qlcnic_adapter *, u32, u32);
|
||||
void qlcnic_82xx_get_func_no(struct qlcnic_adapter *);
|
||||
int qlcnic_82xx_api_lock(struct qlcnic_adapter *);
|
||||
void qlcnic_82xx_api_unlock(struct qlcnic_adapter *);
|
||||
void qlcnic_82xx_napi_enable(struct qlcnic_adapter *);
|
||||
void qlcnic_82xx_napi_disable(struct qlcnic_adapter *);
|
||||
void qlcnic_82xx_napi_del(struct qlcnic_adapter *);
|
||||
int qlcnic_82xx_shutdown(struct pci_dev *);
|
||||
int qlcnic_82xx_resume(struct qlcnic_adapter *);
|
||||
void qlcnic_clr_all_drv_state(struct qlcnic_adapter *adapter, u8 failed);
|
||||
void qlcnic_fw_poll_work(struct work_struct *work);
|
||||
|
||||
u32 qlcnic_82xx_get_saved_state(void *, u32);
|
||||
void qlcnic_82xx_set_saved_state(void *, u32, u32);
|
||||
void qlcnic_82xx_cache_tmpl_hdr_values(struct qlcnic_fw_dump *);
|
||||
u32 qlcnic_82xx_get_cap_size(void *, int);
|
||||
void qlcnic_82xx_set_sys_info(void *, int, u32);
|
||||
void qlcnic_82xx_store_cap_mask(void *, u32);
|
||||
#endif /* __QLCNIC_HW_H_ */
|
||||
1310
drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c
Normal file
1310
drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c
Normal file
File diff suppressed because it is too large
Load diff
2208
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
Normal file
2208
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
Normal file
File diff suppressed because it is too large
Load diff
4346
drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c
Normal file
4346
drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c
Normal file
File diff suppressed because it is too large
Load diff
1415
drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c
Normal file
1415
drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c
Normal file
File diff suppressed because it is too large
Load diff
276
drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov.h
Normal file
276
drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov.h
Normal file
|
|
@ -0,0 +1,276 @@
|
|||
/*
|
||||
* QLogic qlcnic NIC Driver
|
||||
* Copyright (c) 2009-2013 QLogic Corporation
|
||||
*
|
||||
* See LICENSE.qlcnic for copyright and licensing details.
|
||||
*/
|
||||
|
||||
#ifndef _QLCNIC_83XX_SRIOV_H_
|
||||
#define _QLCNIC_83XX_SRIOV_H_
|
||||
|
||||
#include "qlcnic.h"
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
extern const u32 qlcnic_83xx_reg_tbl[];
|
||||
extern const u32 qlcnic_83xx_ext_reg_tbl[];
|
||||
|
||||
struct qlcnic_bc_payload {
|
||||
u64 payload[126];
|
||||
};
|
||||
|
||||
struct qlcnic_bc_hdr {
|
||||
#if defined(__LITTLE_ENDIAN)
|
||||
u8 version;
|
||||
u8 msg_type:4;
|
||||
u8 rsvd1:3;
|
||||
u8 op_type:1;
|
||||
u8 num_cmds;
|
||||
u8 num_frags;
|
||||
u8 frag_num;
|
||||
u8 cmd_op;
|
||||
u16 seq_id;
|
||||
u64 rsvd3;
|
||||
#elif defined(__BIG_ENDIAN)
|
||||
u8 num_frags;
|
||||
u8 num_cmds;
|
||||
u8 op_type:1;
|
||||
u8 rsvd1:3;
|
||||
u8 msg_type:4;
|
||||
u8 version;
|
||||
u16 seq_id;
|
||||
u8 cmd_op;
|
||||
u8 frag_num;
|
||||
u64 rsvd3;
|
||||
#endif
|
||||
};
|
||||
|
||||
enum qlcnic_bc_commands {
|
||||
QLCNIC_BC_CMD_CHANNEL_INIT = 0x0,
|
||||
QLCNIC_BC_CMD_CHANNEL_TERM = 0x1,
|
||||
QLCNIC_BC_CMD_GET_ACL = 0x2,
|
||||
QLCNIC_BC_CMD_CFG_GUEST_VLAN = 0x3,
|
||||
};
|
||||
|
||||
#define QLCNIC_83XX_SRIOV_VF_MAX_MAC 2
|
||||
#define QLC_BC_CMD 1
|
||||
|
||||
struct qlcnic_trans_list {
|
||||
/* Lock for manipulating list */
|
||||
spinlock_t lock;
|
||||
struct list_head wait_list;
|
||||
int count;
|
||||
};
|
||||
|
||||
enum qlcnic_trans_state {
|
||||
QLC_INIT = 0,
|
||||
QLC_WAIT_FOR_CHANNEL_FREE,
|
||||
QLC_WAIT_FOR_RESP,
|
||||
QLC_ABORT,
|
||||
QLC_END,
|
||||
};
|
||||
|
||||
struct qlcnic_bc_trans {
|
||||
u8 func_id;
|
||||
u8 active;
|
||||
u8 curr_rsp_frag;
|
||||
u8 curr_req_frag;
|
||||
u16 cmd_id;
|
||||
u16 req_pay_size;
|
||||
u16 rsp_pay_size;
|
||||
u32 trans_id;
|
||||
enum qlcnic_trans_state trans_state;
|
||||
struct list_head list;
|
||||
struct qlcnic_bc_hdr *req_hdr;
|
||||
struct qlcnic_bc_hdr *rsp_hdr;
|
||||
struct qlcnic_bc_payload *req_pay;
|
||||
struct qlcnic_bc_payload *rsp_pay;
|
||||
struct completion resp_cmpl;
|
||||
struct qlcnic_vf_info *vf;
|
||||
};
|
||||
|
||||
enum qlcnic_vf_state {
|
||||
QLC_BC_VF_SEND = 0,
|
||||
QLC_BC_VF_RECV,
|
||||
QLC_BC_VF_CHANNEL,
|
||||
QLC_BC_VF_STATE,
|
||||
QLC_BC_VF_FLR,
|
||||
QLC_BC_VF_SOFT_FLR,
|
||||
};
|
||||
|
||||
enum qlcnic_vlan_mode {
|
||||
QLC_NO_VLAN_MODE = 0,
|
||||
QLC_PVID_MODE,
|
||||
QLC_GUEST_VLAN_MODE,
|
||||
};
|
||||
|
||||
struct qlcnic_resources {
|
||||
u16 num_tx_mac_filters;
|
||||
u16 num_rx_ucast_mac_filters;
|
||||
u16 num_rx_mcast_mac_filters;
|
||||
|
||||
u16 num_txvlan_keys;
|
||||
|
||||
u16 num_rx_queues;
|
||||
u16 num_tx_queues;
|
||||
|
||||
u16 num_rx_buf_rings;
|
||||
u16 num_rx_status_rings;
|
||||
|
||||
u16 num_destip;
|
||||
u32 num_lro_flows_supported;
|
||||
u16 max_local_ipv6_addrs;
|
||||
u16 max_remote_ipv6_addrs;
|
||||
};
|
||||
|
||||
struct qlcnic_vport {
|
||||
u16 handle;
|
||||
u16 max_tx_bw;
|
||||
u16 min_tx_bw;
|
||||
u16 pvid;
|
||||
u8 vlan_mode;
|
||||
u8 qos;
|
||||
bool spoofchk;
|
||||
u8 mac[6];
|
||||
};
|
||||
|
||||
struct qlcnic_vf_info {
|
||||
u8 pci_func;
|
||||
u16 rx_ctx_id;
|
||||
u16 tx_ctx_id;
|
||||
u16 *sriov_vlans;
|
||||
int num_vlan;
|
||||
unsigned long state;
|
||||
struct completion ch_free_cmpl;
|
||||
struct work_struct trans_work;
|
||||
struct work_struct flr_work;
|
||||
/* It synchronizes commands sent from VF */
|
||||
struct mutex send_cmd_lock;
|
||||
struct qlcnic_bc_trans *send_cmd;
|
||||
struct qlcnic_bc_trans *flr_trans;
|
||||
struct qlcnic_trans_list rcv_act;
|
||||
struct qlcnic_trans_list rcv_pend;
|
||||
struct qlcnic_adapter *adapter;
|
||||
struct qlcnic_vport *vp;
|
||||
spinlock_t vlan_list_lock; /* Lock for VLAN list */
|
||||
};
|
||||
|
||||
struct qlcnic_async_work_list {
|
||||
struct list_head list;
|
||||
struct work_struct work;
|
||||
void *ptr;
|
||||
struct qlcnic_cmd_args *cmd;
|
||||
};
|
||||
|
||||
struct qlcnic_back_channel {
|
||||
u16 trans_counter;
|
||||
struct workqueue_struct *bc_trans_wq;
|
||||
struct workqueue_struct *bc_async_wq;
|
||||
struct workqueue_struct *bc_flr_wq;
|
||||
struct list_head async_list;
|
||||
};
|
||||
|
||||
struct qlcnic_sriov {
|
||||
u16 vp_handle;
|
||||
u8 num_vfs;
|
||||
u8 any_vlan;
|
||||
u8 vlan_mode;
|
||||
u16 num_allowed_vlans;
|
||||
u16 *allowed_vlans;
|
||||
u16 vlan;
|
||||
struct qlcnic_resources ff_max;
|
||||
struct qlcnic_back_channel bc;
|
||||
struct qlcnic_vf_info *vf_info;
|
||||
};
|
||||
|
||||
int qlcnic_sriov_init(struct qlcnic_adapter *, int);
|
||||
void qlcnic_sriov_cleanup(struct qlcnic_adapter *);
|
||||
void __qlcnic_sriov_cleanup(struct qlcnic_adapter *);
|
||||
void qlcnic_sriov_vf_register_map(struct qlcnic_hardware_context *);
|
||||
int qlcnic_sriov_vf_init(struct qlcnic_adapter *, int);
|
||||
void qlcnic_sriov_vf_set_ops(struct qlcnic_adapter *);
|
||||
int qlcnic_sriov_func_to_index(struct qlcnic_adapter *, u8);
|
||||
void qlcnic_sriov_handle_bc_event(struct qlcnic_adapter *, u32);
|
||||
int qlcnic_sriov_cfg_bc_intr(struct qlcnic_adapter *, u8);
|
||||
void qlcnic_sriov_cleanup_async_list(struct qlcnic_back_channel *);
|
||||
void qlcnic_sriov_cleanup_list(struct qlcnic_trans_list *);
|
||||
int __qlcnic_sriov_add_act_list(struct qlcnic_sriov *, struct qlcnic_vf_info *,
|
||||
struct qlcnic_bc_trans *);
|
||||
int qlcnic_sriov_get_vf_vport_info(struct qlcnic_adapter *,
|
||||
struct qlcnic_info *, u16);
|
||||
int qlcnic_sriov_cfg_vf_guest_vlan(struct qlcnic_adapter *, u16, u8);
|
||||
void qlcnic_sriov_free_vlans(struct qlcnic_adapter *);
|
||||
void qlcnic_sriov_alloc_vlans(struct qlcnic_adapter *);
|
||||
bool qlcnic_sriov_check_any_vlan(struct qlcnic_vf_info *);
|
||||
void qlcnic_sriov_del_vlan_id(struct qlcnic_sriov *,
|
||||
struct qlcnic_vf_info *, u16);
|
||||
void qlcnic_sriov_add_vlan_id(struct qlcnic_sriov *,
|
||||
struct qlcnic_vf_info *, u16);
|
||||
|
||||
static inline bool qlcnic_sriov_enable_check(struct qlcnic_adapter *adapter)
|
||||
{
|
||||
return test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state) ? true : false;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_QLCNIC_SRIOV
|
||||
void qlcnic_sriov_pf_process_bc_cmd(struct qlcnic_adapter *,
|
||||
struct qlcnic_bc_trans *,
|
||||
struct qlcnic_cmd_args *);
|
||||
void qlcnic_sriov_pf_disable(struct qlcnic_adapter *);
|
||||
void qlcnic_sriov_pf_cleanup(struct qlcnic_adapter *);
|
||||
int qlcnic_pci_sriov_configure(struct pci_dev *, int);
|
||||
void qlcnic_pf_set_interface_id_create_rx_ctx(struct qlcnic_adapter *, u32 *);
|
||||
void qlcnic_pf_set_interface_id_create_tx_ctx(struct qlcnic_adapter *, u32 *);
|
||||
void qlcnic_pf_set_interface_id_del_rx_ctx(struct qlcnic_adapter *, u32 *);
|
||||
void qlcnic_pf_set_interface_id_del_tx_ctx(struct qlcnic_adapter *, u32 *);
|
||||
void qlcnic_pf_set_interface_id_promisc(struct qlcnic_adapter *, u32 *);
|
||||
void qlcnic_pf_set_interface_id_ipaddr(struct qlcnic_adapter *, u32 *);
|
||||
void qlcnic_pf_set_interface_id_macaddr(struct qlcnic_adapter *, u32 *);
|
||||
void qlcnic_sriov_pf_handle_flr(struct qlcnic_sriov *, struct qlcnic_vf_info *);
|
||||
bool qlcnic_sriov_soft_flr_check(struct qlcnic_adapter *,
|
||||
struct qlcnic_bc_trans *,
|
||||
struct qlcnic_vf_info *);
|
||||
void qlcnic_sriov_pf_reset(struct qlcnic_adapter *);
|
||||
int qlcnic_sriov_pf_reinit(struct qlcnic_adapter *);
|
||||
int qlcnic_sriov_set_vf_mac(struct net_device *, int, u8 *);
|
||||
int qlcnic_sriov_set_vf_tx_rate(struct net_device *, int, int, int);
|
||||
int qlcnic_sriov_get_vf_config(struct net_device *, int ,
|
||||
struct ifla_vf_info *);
|
||||
int qlcnic_sriov_set_vf_vlan(struct net_device *, int, u16, u8);
|
||||
int qlcnic_sriov_set_vf_spoofchk(struct net_device *, int, bool);
|
||||
#else
|
||||
static inline void qlcnic_sriov_pf_disable(struct qlcnic_adapter *adapter) {}
|
||||
static inline void qlcnic_sriov_pf_cleanup(struct qlcnic_adapter *adapter) {}
|
||||
static inline void
|
||||
qlcnic_pf_set_interface_id_create_rx_ctx(struct qlcnic_adapter *adapter,
|
||||
u32 *int_id) {}
|
||||
static inline void
|
||||
qlcnic_pf_set_interface_id_create_tx_ctx(struct qlcnic_adapter *adapter,
|
||||
u32 *int_id) {}
|
||||
static inline void
|
||||
qlcnic_pf_set_interface_id_del_rx_ctx(struct qlcnic_adapter *adapter,
|
||||
u32 *int_id) {}
|
||||
static inline void
|
||||
qlcnic_pf_set_interface_id_del_tx_ctx(struct qlcnic_adapter *adapter,
|
||||
u32 *int_id) {}
|
||||
static inline void
|
||||
qlcnic_pf_set_interface_id_ipaddr(struct qlcnic_adapter *adapter, u32 *int_id)
|
||||
{}
|
||||
static inline void
|
||||
qlcnic_pf_set_interface_id_macaddr(struct qlcnic_adapter *adapter, u32 *int_id)
|
||||
{}
|
||||
static inline void
|
||||
qlcnic_pf_set_interface_id_promisc(struct qlcnic_adapter *adapter, u32 *int_id)
|
||||
{}
|
||||
static inline void qlcnic_sriov_pf_handle_flr(struct qlcnic_sriov *sriov,
|
||||
struct qlcnic_vf_info *vf) {}
|
||||
static inline bool qlcnic_sriov_soft_flr_check(struct qlcnic_adapter *adapter,
|
||||
struct qlcnic_bc_trans *trans,
|
||||
struct qlcnic_vf_info *vf)
|
||||
{ return false; }
|
||||
static inline void qlcnic_sriov_pf_reset(struct qlcnic_adapter *adapter) {}
|
||||
static inline int qlcnic_sriov_pf_reinit(struct qlcnic_adapter *adapter)
|
||||
{ return 0; }
|
||||
#endif
|
||||
|
||||
#endif
|
||||
2209
drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov_common.c
Normal file
2209
drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov_common.c
Normal file
File diff suppressed because it is too large
Load diff
2047
drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov_pf.c
Normal file
2047
drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov_pf.c
Normal file
File diff suppressed because it is too large
Load diff
1438
drivers/net/ethernet/qlogic/qlcnic/qlcnic_sysfs.c
Normal file
1438
drivers/net/ethernet/qlogic/qlcnic/qlcnic_sysfs.c
Normal file
File diff suppressed because it is too large
Load diff
Loading…
Add table
Add a link
Reference in a new issue