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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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88
drivers/net/wireless/rtl818x/Kconfig Normal file
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#
# RTL818X Wireless LAN device configuration
#
config RTL8180
tristate "Realtek 8180/8185/8187SE PCI support"
depends on MAC80211 && PCI
select EEPROM_93CX6
---help---
This is a driver for RTL8180, RTL8185 and RTL8187SE based cards.
These are PCI based chips found in cards such as:
(RTL8185 802.11g)
A-Link WL54PC
(RTL8180 802.11b)
Belkin F5D6020 v3
Belkin F5D6020 v3
Dlink DWL-610
Dlink DWL-510
Netgear MA521
Level-One WPC-0101
Acer Aspire 1357 LMi
VCTnet PC-11B1
Ovislink AirLive WL-1120PCM
Mentor WL-PCI
Linksys WPC11 v4
TrendNET TEW-288PI
D-Link DWL-520 Rev D
Repotec RP-WP7126
TP-Link TL-WN250/251
Zonet ZEW1000
Longshine LCS-8031-R
HomeLine HLW-PCC200
GigaFast WF721-AEX
Planet WL-3553
Encore ENLWI-PCI1-NT
TrendNET TEW-266PC
Gigabyte GN-WLMR101
Siemens-fujitsu Amilo D1840W
Edimax EW-7126
PheeNet WL-11PCIR
Tonze PC-2100T
Planet WL-8303
Dlink DWL-650 v M1
Edimax EW-7106
Q-Tec 770WC
Topcom Skyr@cer 4011b
Roper FreeLan 802.11b (edition 2004)
Wistron Neweb Corp CB-200B
Pentagram HorNET
QTec 775WC
TwinMOS Booming B Series
Micronet SP906BB
Sweex LC700010
Surecom EP-9428
Safecom SWLCR-1100
Thanks to Realtek for their support!
config RTL8187
tristate "Realtek 8187 and 8187B USB support"
depends on MAC80211 && USB
select EEPROM_93CX6
---help---
This is a driver for RTL8187 and RTL8187B based cards.
These are USB based chips found in devices such as:
Netgear WG111v2
Level 1 WNC-0301USB
Micronet SP907GK V5
Encore ENUWI-G2
Trendnet TEW-424UB
ASUS P5B Deluxe/P5K Premium motherboards
Toshiba Satellite Pro series of laptops
Asus Wireless Link
Linksys WUSB54GC-EU v2
(v1 = rt73usb; v3 is rt2070-based,
use staging/rt3070 or try rt2800usb)
Thanks to Realtek for their support!
# If possible, automatically enable LEDs for RTL8187.
config RTL8187_LEDS
bool
depends on RTL8187 && MAC80211_LEDS && (LEDS_CLASS = y || LEDS_CLASS = RTL8187)
default y

2
drivers/net/wireless/rtl818x/Makefile Normal file
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obj-$(CONFIG_RTL8180) += rtl8180/
obj-$(CONFIG_RTL8187) += rtl8187/

5
drivers/net/wireless/rtl818x/rtl8180/Makefile Normal file
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rtl818x_pci-objs := dev.o rtl8225.o sa2400.o max2820.o grf5101.o rtl8225se.o
obj-$(CONFIG_RTL8180) += rtl818x_pci.o
ccflags-y += -Idrivers/net/wireless/rtl818x

1990
drivers/net/wireless/rtl818x/rtl8180/dev.c Normal file
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190
drivers/net/wireless/rtl818x/rtl8180/grf5101.c Normal file
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/*
* Radio tuning for GCT GRF5101 on RTL8180
*
* Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
*
* Code from the BSD driver and the rtl8181 project have been
* very useful to understand certain things
*
* I want to thanks the Authors of such projects and the Ndiswrapper
* project Authors.
*
* A special Big Thanks also is for all people who donated me cards,
* making possible the creation of the original rtl8180 driver
* from which this code is derived!
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/pci.h>
#include <linux/delay.h>
#include <net/mac80211.h>
#include "rtl8180.h"
#include "grf5101.h"
static const int grf5101_encode[] = {
0x0, 0x8, 0x4, 0xC,
0x2, 0xA, 0x6, 0xE,
0x1, 0x9, 0x5, 0xD,
0x3, 0xB, 0x7, 0xF
};
static void write_grf5101(struct ieee80211_hw *dev, u8 addr, u32 data)
{
struct rtl8180_priv *priv = dev->priv;
u32 phy_config;
phy_config = grf5101_encode[(data >> 8) & 0xF];
phy_config |= grf5101_encode[(data >> 4) & 0xF] << 4;
phy_config |= grf5101_encode[data & 0xF] << 8;
phy_config |= grf5101_encode[(addr >> 1) & 0xF] << 12;
phy_config |= (addr & 1) << 16;
phy_config |= grf5101_encode[(data & 0xf000) >> 12] << 24;
/* MAC will bang bits to the chip */
phy_config |= 0x90000000;
rtl818x_iowrite32(priv,
(__le32 __iomem *) &priv->map->RFPinsOutput, phy_config);
msleep(3);
}
static void grf5101_write_phy_antenna(struct ieee80211_hw *dev, short chan)
{
struct rtl8180_priv *priv = dev->priv;
u8 ant = GRF5101_ANTENNA;
if (priv->rfparam & RF_PARAM_ANTBDEFAULT)
ant |= BB_ANTENNA_B;
if (chan == 14)
ant |= BB_ANTATTEN_CHAN14;
rtl8180_write_phy(dev, 0x10, ant);
}
static u8 grf5101_rf_calc_rssi(u8 agc, u8 sq)
{
if (agc > 60)
return 65;
/* TODO(?): just return agc (or agc + 5) to avoid mult / div */
return 65 * agc / 60;
}
static void grf5101_rf_set_channel(struct ieee80211_hw *dev,
struct ieee80211_conf *conf)
{
struct rtl8180_priv *priv = dev->priv;
int channel =
ieee80211_frequency_to_channel(conf->chandef.chan->center_freq);
u32 txpw = priv->channels[channel - 1].hw_value & 0xFF;
u32 chan = channel - 1;
/* set TX power */
write_grf5101(dev, 0x15, 0x0);
write_grf5101(dev, 0x06, txpw);
write_grf5101(dev, 0x15, 0x10);
write_grf5101(dev, 0x15, 0x0);
/* set frequency */
write_grf5101(dev, 0x07, 0x0);
write_grf5101(dev, 0x0B, chan);
write_grf5101(dev, 0x07, 0x1000);
grf5101_write_phy_antenna(dev, channel);
}
static void grf5101_rf_stop(struct ieee80211_hw *dev)
{
struct rtl8180_priv *priv = dev->priv;
u32 anaparam;
anaparam = priv->anaparam;
anaparam &= 0x000fffff;
anaparam |= 0x3f900000;
rtl8180_set_anaparam(priv, anaparam);
write_grf5101(dev, 0x07, 0x0);
write_grf5101(dev, 0x1f, 0x45);
write_grf5101(dev, 0x1f, 0x5);
write_grf5101(dev, 0x00, 0x8e4);
}
static void grf5101_rf_init(struct ieee80211_hw *dev)
{
struct rtl8180_priv *priv = dev->priv;
rtl8180_set_anaparam(priv, priv->anaparam);
write_grf5101(dev, 0x1f, 0x0);
write_grf5101(dev, 0x1f, 0x0);
write_grf5101(dev, 0x1f, 0x40);
write_grf5101(dev, 0x1f, 0x60);
write_grf5101(dev, 0x1f, 0x61);
write_grf5101(dev, 0x1f, 0x61);
write_grf5101(dev, 0x00, 0xae4);
write_grf5101(dev, 0x1f, 0x1);
write_grf5101(dev, 0x1f, 0x41);
write_grf5101(dev, 0x1f, 0x61);
write_grf5101(dev, 0x01, 0x1a23);
write_grf5101(dev, 0x02, 0x4971);
write_grf5101(dev, 0x03, 0x41de);
write_grf5101(dev, 0x04, 0x2d80);
write_grf5101(dev, 0x05, 0x68ff); /* 0x61ff original value */
write_grf5101(dev, 0x06, 0x0);
write_grf5101(dev, 0x07, 0x0);
write_grf5101(dev, 0x08, 0x7533);
write_grf5101(dev, 0x09, 0xc401);
write_grf5101(dev, 0x0a, 0x0);
write_grf5101(dev, 0x0c, 0x1c7);
write_grf5101(dev, 0x0d, 0x29d3);
write_grf5101(dev, 0x0e, 0x2e8);
write_grf5101(dev, 0x10, 0x192);
write_grf5101(dev, 0x11, 0x248);
write_grf5101(dev, 0x12, 0x0);
write_grf5101(dev, 0x13, 0x20c4);
write_grf5101(dev, 0x14, 0xf4fc);
write_grf5101(dev, 0x15, 0x0);
write_grf5101(dev, 0x16, 0x1500);
write_grf5101(dev, 0x07, 0x1000);
/* baseband configuration */
rtl8180_write_phy(dev, 0, 0xa8);
rtl8180_write_phy(dev, 3, 0x0);
rtl8180_write_phy(dev, 4, 0xc0);
rtl8180_write_phy(dev, 5, 0x90);
rtl8180_write_phy(dev, 6, 0x1e);
rtl8180_write_phy(dev, 7, 0x64);
grf5101_write_phy_antenna(dev, 1);
rtl8180_write_phy(dev, 0x11, 0x88);
if (rtl818x_ioread8(priv, &priv->map->CONFIG2) &
RTL818X_CONFIG2_ANTENNA_DIV)
rtl8180_write_phy(dev, 0x12, 0xc0); /* enable ant diversity */
else
rtl8180_write_phy(dev, 0x12, 0x40); /* disable ant diversity */
rtl8180_write_phy(dev, 0x13, 0x90 | priv->csthreshold);
rtl8180_write_phy(dev, 0x19, 0x0);
rtl8180_write_phy(dev, 0x1a, 0xa0);
rtl8180_write_phy(dev, 0x1b, 0x44);
}
const struct rtl818x_rf_ops grf5101_rf_ops = {
.name = "GCT",
.init = grf5101_rf_init,
.stop = grf5101_rf_stop,
.set_chan = grf5101_rf_set_channel,
.calc_rssi = grf5101_rf_calc_rssi,
};

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drivers/net/wireless/rtl818x/rtl8180/grf5101.h Normal file
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#ifndef RTL8180_GRF5101_H
#define RTL8180_GRF5101_H
/*
* Radio tuning for GCT GRF5101 on RTL8180
*
* Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
*
* Code from the BSD driver and the rtl8181 project have been
* very useful to understand certain things
*
* I want to thanks the Authors of such projects and the Ndiswrapper
* project Authors.
*
* A special Big Thanks also is for all people who donated me cards,
* making possible the creation of the original rtl8180 driver
* from which this code is derived!
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define GRF5101_ANTENNA 0xA3
extern const struct rtl818x_rf_ops grf5101_rf_ops;
#endif /* RTL8180_GRF5101_H */

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drivers/net/wireless/rtl818x/rtl8180/max2820.c Normal file
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/*
* Radio tuning for Maxim max2820 on RTL8180
*
* Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
*
* Code from the BSD driver and the rtl8181 project have been
* very useful to understand certain things
*
* I want to thanks the Authors of such projects and the Ndiswrapper
* project Authors.
*
* A special Big Thanks also is for all people who donated me cards,
* making possible the creation of the original rtl8180 driver
* from which this code is derived!
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/pci.h>
#include <linux/delay.h>
#include <net/mac80211.h>
#include "rtl8180.h"
#include "max2820.h"
static const u32 max2820_chan[] = {
12, /* CH 1 */
17,
22,
27,
32,
37,
42,
47,
52,
57,
62,
67,
72,
84, /* CH 14 */
};
static void write_max2820(struct ieee80211_hw *dev, u8 addr, u32 data)
{
struct rtl8180_priv *priv = dev->priv;
u32 phy_config;
phy_config = 0x90 + (data & 0xf);
phy_config <<= 16;
phy_config += addr;
phy_config <<= 8;
phy_config += (data >> 4) & 0xff;
rtl818x_iowrite32(priv,
(__le32 __iomem *) &priv->map->RFPinsOutput, phy_config);
msleep(1);
}
static void max2820_write_phy_antenna(struct ieee80211_hw *dev, short chan)
{
struct rtl8180_priv *priv = dev->priv;
u8 ant;
ant = MAXIM_ANTENNA;
if (priv->rfparam & RF_PARAM_ANTBDEFAULT)
ant |= BB_ANTENNA_B;
if (chan == 14)
ant |= BB_ANTATTEN_CHAN14;
rtl8180_write_phy(dev, 0x10, ant);
}
static u8 max2820_rf_calc_rssi(u8 agc, u8 sq)
{
bool odd;
odd = !!(agc & 1);
agc >>= 1;
if (odd)
agc += 76;
else
agc += 66;
/* TODO: change addends above to avoid mult / div below */
return 65 * agc / 100;
}
static void max2820_rf_set_channel(struct ieee80211_hw *dev,
struct ieee80211_conf *conf)
{
struct rtl8180_priv *priv = dev->priv;
int channel = conf ?
ieee80211_frequency_to_channel(conf->chandef.chan->center_freq) : 1;
unsigned int chan_idx = channel - 1;
u32 txpw = priv->channels[chan_idx].hw_value & 0xFF;
u32 chan = max2820_chan[chan_idx];
/* While philips SA2400 drive the PA bias from
* sa2400, for MAXIM we do this directly from BB */
rtl8180_write_phy(dev, 3, txpw);
max2820_write_phy_antenna(dev, channel);
write_max2820(dev, 3, chan);
}
static void max2820_rf_stop(struct ieee80211_hw *dev)
{
rtl8180_write_phy(dev, 3, 0x8);
write_max2820(dev, 1, 0);
}
static void max2820_rf_init(struct ieee80211_hw *dev)
{
struct rtl8180_priv *priv = dev->priv;
/* MAXIM from netbsd driver */
write_max2820(dev, 0, 0x007); /* test mode as indicated in datasheet */
write_max2820(dev, 1, 0x01e); /* enable register */
write_max2820(dev, 2, 0x001); /* synt register */
max2820_rf_set_channel(dev, NULL);
write_max2820(dev, 4, 0x313); /* rx register */
/* PA is driven directly by the BB, we keep the MAXIM bias
* at the highest value in case that setting it to lower
* values may introduce some further attenuation somewhere..
*/
write_max2820(dev, 5, 0x00f);
/* baseband configuration */
rtl8180_write_phy(dev, 0, 0x88); /* sys1 */
rtl8180_write_phy(dev, 3, 0x08); /* txagc */
rtl8180_write_phy(dev, 4, 0xf8); /* lnadet */
rtl8180_write_phy(dev, 5, 0x90); /* ifagcinit */
rtl8180_write_phy(dev, 6, 0x1a); /* ifagclimit */
rtl8180_write_phy(dev, 7, 0x64); /* ifagcdet */
max2820_write_phy_antenna(dev, 1);
rtl8180_write_phy(dev, 0x11, 0x88); /* trl */
if (rtl818x_ioread8(priv, &priv->map->CONFIG2) &
RTL818X_CONFIG2_ANTENNA_DIV)
rtl8180_write_phy(dev, 0x12, 0xc7);
else
rtl8180_write_phy(dev, 0x12, 0x47);
rtl8180_write_phy(dev, 0x13, 0x9b);
rtl8180_write_phy(dev, 0x19, 0x0); /* CHESTLIM */
rtl8180_write_phy(dev, 0x1a, 0x9f); /* CHSQLIM */
max2820_rf_set_channel(dev, NULL);
}
const struct rtl818x_rf_ops max2820_rf_ops = {
.name = "Maxim",
.init = max2820_rf_init,
.stop = max2820_rf_stop,
.set_chan = max2820_rf_set_channel,
.calc_rssi = max2820_rf_calc_rssi,
};

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drivers/net/wireless/rtl818x/rtl8180/max2820.h Normal file
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#ifndef RTL8180_MAX2820_H
#define RTL8180_MAX2820_H
/*
* Radio tuning for Maxim max2820 on RTL8180
*
* Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
*
* Code from the BSD driver and the rtl8181 project have been
* very useful to understand certain things
*
* I want to thanks the Authors of such projects and the Ndiswrapper
* project Authors.
*
* A special Big Thanks also is for all people who donated me cards,
* making possible the creation of the original rtl8180 driver
* from which this code is derived!
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define MAXIM_ANTENNA 0xb3
extern const struct rtl818x_rf_ops max2820_rf_ops;
#endif /* RTL8180_MAX2820_H */

185
drivers/net/wireless/rtl818x/rtl8180/rtl8180.h Normal file
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#ifndef RTL8180_H
#define RTL8180_H
#include "rtl818x.h"
#define MAX_RX_SIZE IEEE80211_MAX_RTS_THRESHOLD
#define RF_PARAM_ANALOGPHY (1 << 0)
#define RF_PARAM_ANTBDEFAULT (1 << 1)
#define RF_PARAM_CARRIERSENSE1 (1 << 2)
#define RF_PARAM_CARRIERSENSE2 (1 << 3)
#define BB_ANTATTEN_CHAN14 0x0C
#define BB_ANTENNA_B 0x40
#define BB_HOST_BANG (1 << 30)
#define BB_HOST_BANG_EN (1 << 2)
#define BB_HOST_BANG_CLK (1 << 1)
#define BB_HOST_BANG_DATA 1
#define ANAPARAM_TXDACOFF_SHIFT 27
#define ANAPARAM_PWR0_SHIFT 28
#define ANAPARAM_PWR0_MASK (0x07 << ANAPARAM_PWR0_SHIFT)
#define ANAPARAM_PWR1_SHIFT 20
#define ANAPARAM_PWR1_MASK (0x7F << ANAPARAM_PWR1_SHIFT)
/* rtl8180/rtl8185 have 3 queue + beacon queue.
* mac80211 can use just one, + beacon = 2 tot.
*/
#define RTL8180_NR_TX_QUEUES 2
/* rtl8187SE have 6 queues + beacon queues
* mac80211 can use 4 QoS data queue, + beacon = 5 tot
*/
#define RTL8187SE_NR_TX_QUEUES 5
/* for array static allocation, it is the max of above */
#define RTL818X_NR_TX_QUEUES 5
struct rtl8180_tx_desc {
__le32 flags;
__le16 rts_duration;
__le16 plcp_len;
__le32 tx_buf;
union{
__le32 frame_len;
struct {
__le16 frame_len_se;
__le16 frame_duration;
} __packed;
} __packed;
__le32 next_tx_desc;
u8 cw;
u8 retry_limit;
u8 agc;
u8 flags2;
/* rsvd for 8180/8185.
* valid for 8187se but we dont use it
*/
u32 reserved;
/* all rsvd for 8180/8185 */
__le16 flags3;
__le16 frag_qsize;
} __packed;
struct rtl818x_rx_cmd_desc {
__le32 flags;
u32 reserved;
__le32 rx_buf;
} __packed;
struct rtl8180_rx_desc {
__le32 flags;
__le32 flags2;
__le64 tsft;
} __packed;
struct rtl8187se_rx_desc {
__le32 flags;
__le64 tsft;
__le32 flags2;
__le32 flags3;
u32 reserved[3];
} __packed;
struct rtl8180_tx_ring {
struct rtl8180_tx_desc *desc;
dma_addr_t dma;
unsigned int idx;
unsigned int entries;
struct sk_buff_head queue;
};
struct rtl8180_vif {
struct ieee80211_hw *dev;
/* beaconing */
struct delayed_work beacon_work;
bool enable_beacon;
};
struct rtl8180_priv {
/* common between rtl818x drivers */
struct rtl818x_csr __iomem *map;
const struct rtl818x_rf_ops *rf;
struct ieee80211_vif *vif;
/* rtl8180 driver specific */
bool map_pio;
spinlock_t lock;
void *rx_ring;
u8 rx_ring_sz;
dma_addr_t rx_ring_dma;
unsigned int rx_idx;
struct sk_buff *rx_buf[32];
struct rtl8180_tx_ring tx_ring[RTL818X_NR_TX_QUEUES];
struct ieee80211_channel channels[14];
struct ieee80211_rate rates[12];
struct ieee80211_supported_band band;
struct ieee80211_tx_queue_params queue_param[4];
struct pci_dev *pdev;
u32 rx_conf;
u8 slot_time;
u16 ack_time;
enum {
RTL818X_CHIP_FAMILY_RTL8180,
RTL818X_CHIP_FAMILY_RTL8185,
RTL818X_CHIP_FAMILY_RTL8187SE,
} chip_family;
u32 anaparam;
u16 rfparam;
u8 csthreshold;
u8 mac_addr[ETH_ALEN];
u8 rf_type;
u8 xtal_out;
u8 xtal_in;
u8 xtal_cal;
u8 thermal_meter_val;
u8 thermal_meter_en;
u8 antenna_diversity_en;
u8 antenna_diversity_default;
/* sequence # */
u16 seqno;
};
void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data);
void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam);
void rtl8180_set_anaparam2(struct rtl8180_priv *priv, u32 anaparam2);
static inline u8 rtl818x_ioread8(struct rtl8180_priv *priv, u8 __iomem *addr)
{
return ioread8(addr);
}
static inline u16 rtl818x_ioread16(struct rtl8180_priv *priv, __le16 __iomem *addr)
{
return ioread16(addr);
}
static inline u32 rtl818x_ioread32(struct rtl8180_priv *priv, __le32 __iomem *addr)
{
return ioread32(addr);
}
static inline void rtl818x_iowrite8(struct rtl8180_priv *priv,
u8 __iomem *addr, u8 val)
{
iowrite8(val, addr);
}
static inline void rtl818x_iowrite16(struct rtl8180_priv *priv,
__le16 __iomem *addr, u16 val)
{
iowrite16(val, addr);
}
static inline void rtl818x_iowrite32(struct rtl8180_priv *priv,
__le32 __iomem *addr, u32 val)
{
iowrite32(val, addr);
}
#endif /* RTL8180_H */

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drivers/net/wireless/rtl818x/rtl8180/rtl8225.c Normal file
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/*
* Radio tuning for RTL8225 on RTL8180
*
* Copyright 2007 Michael Wu <flamingice@sourmilk.net>
* Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
*
* Based on the r8180 driver, which is:
* Copyright 2005 Andrea Merello <andrea.merello@gmail.com>, et al.
*
* Thanks to Realtek for their support!
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/pci.h>
#include <linux/delay.h>
#include <net/mac80211.h>
#include "rtl8180.h"
#include "rtl8225.h"
static void rtl8225_write(struct ieee80211_hw *dev, u8 addr, u16 data)
{
struct rtl8180_priv *priv = dev->priv;
u16 reg80, reg84, reg82;
u32 bangdata;
int i;
bangdata = (data << 4) | (addr & 0xf);
reg80 = rtl818x_ioread16(priv, &priv->map->RFPinsOutput) & 0xfff3;
reg82 = rtl818x_ioread16(priv, &priv->map->RFPinsEnable);
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82 | 0x7);
reg84 = rtl818x_ioread16(priv, &priv->map->RFPinsSelect);
rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x7 | 0x400);
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(10);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 2));
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(2);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80);
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(10);
for (i = 15; i >= 0; i--) {
u16 reg = reg80;
if (bangdata & (1 << i))
reg |= 1;
if (i & 1)
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg | (1 << 1));
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg | (1 << 1));
if (!(i & 1))
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg);
}
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 2));
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(10);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 2));
rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x400);
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
}
static u16 rtl8225_read(struct ieee80211_hw *dev, u8 addr)
{
struct rtl8180_priv *priv = dev->priv;
u16 reg80, reg82, reg84, out;
int i;
reg80 = rtl818x_ioread16(priv, &priv->map->RFPinsOutput);
reg82 = rtl818x_ioread16(priv, &priv->map->RFPinsEnable);
reg84 = rtl818x_ioread16(priv, &priv->map->RFPinsSelect) | 0x400;
reg80 &= ~0xF;
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82 | 0x000F);
rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x000F);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 2));
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(4);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80);
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(5);
for (i = 4; i >= 0; i--) {
u16 reg = reg80 | ((addr >> i) & 1);
if (!(i & 1)) {
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg);
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(1);
}
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg | (1 << 1));
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(2);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg | (1 << 1));
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(2);
if (i & 1) {
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg);
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(1);
}
}
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x000E);
rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x040E);
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3) | (1 << 1));
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(2);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3));
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(2);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3));
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(2);
out = 0;
for (i = 11; i >= 0; i--) {
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3));
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(1);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3) | (1 << 1));
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(2);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3) | (1 << 1));
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(2);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3) | (1 << 1));
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(2);
if (rtl818x_ioread16(priv, &priv->map->RFPinsInput) & (1 << 1))
out |= 1 << i;
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3));
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(2);
}
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3) | (1 << 2));
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(2);
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82);
rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x03A0);
return out;
}
static const u16 rtl8225bcd_rxgain[] = {
0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
};
static const u8 rtl8225_agc[] = {
0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e,
0x9d, 0x9c, 0x9b, 0x9a, 0x99, 0x98, 0x97, 0x96,
0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 0x8f, 0x8e,
0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86,
0x85, 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e,
0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38, 0x37, 0x36,
0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 0x2e,
0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26,
0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e,
0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16,
0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06,
0x05, 0x04, 0x03, 0x02, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
};
static const u8 rtl8225_gain[] = {
0x23, 0x88, 0x7c, 0xa5, /* -82dbm */
0x23, 0x88, 0x7c, 0xb5, /* -82dbm */
0x23, 0x88, 0x7c, 0xc5, /* -82dbm */
0x33, 0x80, 0x79, 0xc5, /* -78dbm */
0x43, 0x78, 0x76, 0xc5, /* -74dbm */
0x53, 0x60, 0x73, 0xc5, /* -70dbm */
0x63, 0x58, 0x70, 0xc5, /* -66dbm */
};
static const u8 rtl8225_threshold[] = {
0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd
};
static const u8 rtl8225_tx_gain_cck_ofdm[] = {
0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
};
static const u8 rtl8225_tx_power_cck[] = {
0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
};
static const u8 rtl8225_tx_power_cck_ch14[] = {
0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
};
static const u8 rtl8225_tx_power_ofdm[] = {
0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
};
static const u32 rtl8225_chan[] = {
0x085c, 0x08dc, 0x095c, 0x09dc, 0x0a5c, 0x0adc, 0x0b5c,
0x0bdc, 0x0c5c, 0x0cdc, 0x0d5c, 0x0ddc, 0x0e5c, 0x0f72
};
static void rtl8225_rf_set_tx_power(struct ieee80211_hw *dev, int channel)
{
struct rtl8180_priv *priv = dev->priv;
u8 cck_power, ofdm_power;
const u8 *tmp;
u32 reg;
int i;
cck_power = priv->channels[channel - 1].hw_value & 0xFF;
ofdm_power = priv->channels[channel - 1].hw_value >> 8;
cck_power = min(cck_power, (u8)35);
ofdm_power = min(ofdm_power, (u8)35);
rtl818x_iowrite8(priv, &priv->map->TX_GAIN_CCK,
rtl8225_tx_gain_cck_ofdm[cck_power / 6] >> 1);
if (channel == 14)
tmp = &rtl8225_tx_power_cck_ch14[(cck_power % 6) * 8];
else
tmp = &rtl8225_tx_power_cck[(cck_power % 6) * 8];
for (i = 0; i < 8; i++)
rtl8225_write_phy_cck(dev, 0x44 + i, *tmp++);
msleep(1); /* FIXME: optional? */
/* TODO: use set_anaparam2 dev.c_func*/
/* anaparam2 on */
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_ON);
rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
rtl818x_iowrite8(priv, &priv->map->TX_GAIN_OFDM,
rtl8225_tx_gain_cck_ofdm[ofdm_power/6] >> 1);
tmp = &rtl8225_tx_power_ofdm[ofdm_power % 6];
rtl8225_write_phy_ofdm(dev, 5, *tmp);
rtl8225_write_phy_ofdm(dev, 7, *tmp);
msleep(1);
}
static void rtl8225_rf_init(struct ieee80211_hw *dev)
{
struct rtl8180_priv *priv = dev->priv;
int i;
rtl8180_set_anaparam(priv, RTL8225_ANAPARAM_ON);
/* host_pci_init */
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x0488);
rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
msleep(200); /* FIXME: ehh?? */
rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0xFF & ~(1 << 6));
rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
/* TODO: check if we need really to change BRSR to do RF config */
rtl818x_ioread16(priv, &priv->map->BRSR);
rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
rtl8225_write(dev, 0x0, 0x067);
rtl8225_write(dev, 0x1, 0xFE0);
rtl8225_write(dev, 0x2, 0x44D);
rtl8225_write(dev, 0x3, 0x441);
rtl8225_write(dev, 0x4, 0x8BE);
rtl8225_write(dev, 0x5, 0xBF0); /* TODO: minipci */
rtl8225_write(dev, 0x6, 0xAE6);
rtl8225_write(dev, 0x7, rtl8225_chan[0]);
rtl8225_write(dev, 0x8, 0x01F);
rtl8225_write(dev, 0x9, 0x334);
rtl8225_write(dev, 0xA, 0xFD4);
rtl8225_write(dev, 0xB, 0x391);
rtl8225_write(dev, 0xC, 0x050);
rtl8225_write(dev, 0xD, 0x6DB);
rtl8225_write(dev, 0xE, 0x029);
rtl8225_write(dev, 0xF, 0x914); msleep(1);
rtl8225_write(dev, 0x2, 0xC4D); msleep(100);
rtl8225_write(dev, 0x0, 0x127);
for (i = 0; i < ARRAY_SIZE(rtl8225bcd_rxgain); i++) {
rtl8225_write(dev, 0x1, i + 1);
rtl8225_write(dev, 0x2, rtl8225bcd_rxgain[i]);
}
rtl8225_write(dev, 0x0, 0x027);
rtl8225_write(dev, 0x0, 0x22F);
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
for (i = 0; i < ARRAY_SIZE(rtl8225_agc); i++) {
rtl8225_write_phy_ofdm(dev, 0xB, rtl8225_agc[i]);
msleep(1);
rtl8225_write_phy_ofdm(dev, 0xA, 0x80 + i);
msleep(1);
}
msleep(1);
rtl8225_write_phy_ofdm(dev, 0x00, 0x01); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x01, 0x02); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x02, 0x62); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x03, 0x00); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x04, 0x00); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x05, 0x00); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x06, 0x00); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x07, 0x00); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x08, 0x00); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x09, 0xfe); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x0a, 0x09); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x0b, 0x80); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x0c, 0x01); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x0e, 0xd3); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x0f, 0x38); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x10, 0x84); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x11, 0x03); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x12, 0x20); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x13, 0x20); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x14, 0x00); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x15, 0x40); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x16, 0x00); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x17, 0x40); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x18, 0xef); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x19, 0x19); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x1a, 0x20); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x1b, 0x76); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x1c, 0x04); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x1e, 0x95); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x1f, 0x75); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x20, 0x1f); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x21, 0x27); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x22, 0x16); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x24, 0x46); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x25, 0x20); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x26, 0x90); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x27, 0x88); msleep(1);
rtl8225_write_phy_cck(dev, 0x00, 0x98); msleep(1);
rtl8225_write_phy_cck(dev, 0x03, 0x20); msleep(1);
rtl8225_write_phy_cck(dev, 0x04, 0x7e); msleep(1);
rtl8225_write_phy_cck(dev, 0x05, 0x12); msleep(1);
rtl8225_write_phy_cck(dev, 0x06, 0xfc); msleep(1);
rtl8225_write_phy_cck(dev, 0x07, 0x78); msleep(1);
rtl8225_write_phy_cck(dev, 0x08, 0x2e); msleep(1);
rtl8225_write_phy_cck(dev, 0x10, 0x93); msleep(1);
rtl8225_write_phy_cck(dev, 0x11, 0x88); msleep(1);
rtl8225_write_phy_cck(dev, 0x12, 0x47); msleep(1);
rtl8225_write_phy_cck(dev, 0x13, 0xd0);
rtl8225_write_phy_cck(dev, 0x19, 0x00);
rtl8225_write_phy_cck(dev, 0x1a, 0xa0);
rtl8225_write_phy_cck(dev, 0x1b, 0x08);
rtl8225_write_phy_cck(dev, 0x40, 0x86);
rtl8225_write_phy_cck(dev, 0x41, 0x8d); msleep(1);
rtl8225_write_phy_cck(dev, 0x42, 0x15); msleep(1);
rtl8225_write_phy_cck(dev, 0x43, 0x18); msleep(1);
rtl8225_write_phy_cck(dev, 0x44, 0x1f); msleep(1);
rtl8225_write_phy_cck(dev, 0x45, 0x1e); msleep(1);
rtl8225_write_phy_cck(dev, 0x46, 0x1a); msleep(1);
rtl8225_write_phy_cck(dev, 0x47, 0x15); msleep(1);
rtl8225_write_phy_cck(dev, 0x48, 0x10); msleep(1);
rtl8225_write_phy_cck(dev, 0x49, 0x0a); msleep(1);
rtl8225_write_phy_cck(dev, 0x4a, 0x05); msleep(1);
rtl8225_write_phy_cck(dev, 0x4b, 0x02); msleep(1);
rtl8225_write_phy_cck(dev, 0x4c, 0x05); msleep(1);
rtl818x_iowrite8(priv, &priv->map->TESTR, 0x0D); msleep(1);
rtl8225_rf_set_tx_power(dev, 1);
/* RX antenna default to A */
rtl8225_write_phy_cck(dev, 0x10, 0x9b); msleep(1); /* B: 0xDB */
rtl8225_write_phy_ofdm(dev, 0x26, 0x90); msleep(1); /* B: 0x10 */
rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03); /* B: 0x00 */
msleep(1);
rtl818x_iowrite32(priv, (__le32 __iomem *)((void __iomem *)priv->map + 0x94), 0x15c00002);
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
rtl8225_write(dev, 0x0c, 0x50);
/* set OFDM initial gain */
rtl8225_write_phy_ofdm(dev, 0x0d, rtl8225_gain[4 * 4]);
rtl8225_write_phy_ofdm(dev, 0x23, rtl8225_gain[4 * 4 + 1]);
rtl8225_write_phy_ofdm(dev, 0x1b, rtl8225_gain[4 * 4 + 2]);
rtl8225_write_phy_ofdm(dev, 0x1d, rtl8225_gain[4 * 4 + 3]);
/* set CCK threshold */
rtl8225_write_phy_cck(dev, 0x41, rtl8225_threshold[0]);
}
static const u8 rtl8225z2_tx_power_cck_ch14[] = {
0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
};
static const u8 rtl8225z2_tx_power_cck_B[] = {
0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x04
};
static const u8 rtl8225z2_tx_power_cck_A[] = {
0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04
};
static const u8 rtl8225z2_tx_power_cck[] = {
0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
};
static void rtl8225z2_rf_set_tx_power(struct ieee80211_hw *dev, int channel)
{
struct rtl8180_priv *priv = dev->priv;
u8 cck_power, ofdm_power;
const u8 *tmp;
int i;
cck_power = priv->channels[channel - 1].hw_value & 0xFF;
ofdm_power = priv->channels[channel - 1].hw_value >> 8;
if (channel == 14)
tmp = rtl8225z2_tx_power_cck_ch14;
else if (cck_power == 12)
tmp = rtl8225z2_tx_power_cck_B;
else if (cck_power == 13)
tmp = rtl8225z2_tx_power_cck_A;
else
tmp = rtl8225z2_tx_power_cck;
for (i = 0; i < 8; i++)
rtl8225_write_phy_cck(dev, 0x44 + i, *tmp++);
cck_power = min(cck_power, (u8)35);
if (cck_power == 13 || cck_power == 14)
cck_power = 12;
if (cck_power >= 15)
cck_power -= 2;
rtl818x_iowrite8(priv, &priv->map->TX_GAIN_CCK, cck_power);
rtl818x_ioread8(priv, &priv->map->TX_GAIN_CCK);
msleep(1);
ofdm_power = min(ofdm_power, (u8)35);
rtl818x_iowrite8(priv, &priv->map->TX_GAIN_OFDM, ofdm_power);
rtl8225_write_phy_ofdm(dev, 2, 0x62);
rtl8225_write_phy_ofdm(dev, 5, 0x00);
rtl8225_write_phy_ofdm(dev, 6, 0x40);
rtl8225_write_phy_ofdm(dev, 7, 0x00);
rtl8225_write_phy_ofdm(dev, 8, 0x40);
msleep(1);
}
static const u16 rtl8225z2_rxgain[] = {
0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009,
0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141,
0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183,
0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244,
0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288,
0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345,
0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389,
0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393,
0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d,
0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9,
0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
};
static void rtl8225z2_rf_init(struct ieee80211_hw *dev)
{
struct rtl8180_priv *priv = dev->priv;
int i;
rtl8180_set_anaparam(priv, RTL8225_ANAPARAM_ON);
/* host_pci_init */
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x0488);
rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
msleep(200); /* FIXME: ehh?? */
rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0xFF & ~(1 << 6));
rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00088008);
/* TODO: check if we need really to change BRSR to do RF config */
rtl818x_ioread16(priv, &priv->map->BRSR);
rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
rtl8225_write(dev, 0x0, 0x0B7); msleep(1);
rtl8225_write(dev, 0x1, 0xEE0); msleep(1);
rtl8225_write(dev, 0x2, 0x44D); msleep(1);
rtl8225_write(dev, 0x3, 0x441); msleep(1);
rtl8225_write(dev, 0x4, 0x8C3); msleep(1);
rtl8225_write(dev, 0x5, 0xC72); msleep(1);
rtl8225_write(dev, 0x6, 0x0E6); msleep(1);
rtl8225_write(dev, 0x7, 0x82A); msleep(1);
rtl8225_write(dev, 0x8, 0x03F); msleep(1);
rtl8225_write(dev, 0x9, 0x335); msleep(1);
rtl8225_write(dev, 0xa, 0x9D4); msleep(1);
rtl8225_write(dev, 0xb, 0x7BB); msleep(1);
rtl8225_write(dev, 0xc, 0x850); msleep(1);
rtl8225_write(dev, 0xd, 0xCDF); msleep(1);
rtl8225_write(dev, 0xe, 0x02B); msleep(1);
rtl8225_write(dev, 0xf, 0x114); msleep(100);
if (!(rtl8225_read(dev, 6) & (1 << 7))) {
rtl8225_write(dev, 0x02, 0x0C4D);
msleep(200);
rtl8225_write(dev, 0x02, 0x044D);
msleep(100);
/* TODO: readd calibration failure message when the calibration
check works */
}
rtl8225_write(dev, 0x0, 0x1B7);
rtl8225_write(dev, 0x3, 0x002);
rtl8225_write(dev, 0x5, 0x004);
for (i = 0; i < ARRAY_SIZE(rtl8225z2_rxgain); i++) {
rtl8225_write(dev, 0x1, i + 1);
rtl8225_write(dev, 0x2, rtl8225z2_rxgain[i]);
}
rtl8225_write(dev, 0x0, 0x0B7); msleep(100);
rtl8225_write(dev, 0x2, 0xC4D);
msleep(200);
rtl8225_write(dev, 0x2, 0x44D);
msleep(100);
rtl8225_write(dev, 0x00, 0x2BF);
rtl8225_write(dev, 0xFF, 0xFFFF);
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
for (i = 0; i < ARRAY_SIZE(rtl8225_agc); i++) {
rtl8225_write_phy_ofdm(dev, 0xB, rtl8225_agc[i]);
msleep(1);
rtl8225_write_phy_ofdm(dev, 0xA, 0x80 + i);
msleep(1);
}
msleep(1);
rtl8225_write_phy_ofdm(dev, 0x00, 0x01); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x01, 0x02); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x02, 0x62); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x03, 0x00); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x04, 0x00); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x05, 0x00); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x06, 0x40); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x07, 0x00); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x08, 0x40); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x09, 0xfe); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x0a, 0x09); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x18, 0xef); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x0b, 0x80); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x0c, 0x01); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x0d, 0x43);
rtl8225_write_phy_ofdm(dev, 0x0e, 0xd3); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x0f, 0x38); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x10, 0x84); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x11, 0x06); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x12, 0x20); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x13, 0x20); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x14, 0x00); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x15, 0x40); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x16, 0x00); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x17, 0x40); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x18, 0xef); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x19, 0x19); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x1a, 0x20); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x1b, 0x11); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x1c, 0x04); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x1d, 0xc5); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x1e, 0xb3); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x1f, 0x75); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x20, 0x1f); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x21, 0x27); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x22, 0x16); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x23, 0x80); msleep(1); /* FIXME: not needed? */
rtl8225_write_phy_ofdm(dev, 0x24, 0x46); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x25, 0x20); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x26, 0x90); msleep(1);
rtl8225_write_phy_ofdm(dev, 0x27, 0x88); msleep(1);
rtl8225_write_phy_cck(dev, 0x00, 0x98); msleep(1);
rtl8225_write_phy_cck(dev, 0x03, 0x20); msleep(1);
rtl8225_write_phy_cck(dev, 0x04, 0x7e); msleep(1);
rtl8225_write_phy_cck(dev, 0x05, 0x12); msleep(1);
rtl8225_write_phy_cck(dev, 0x06, 0xfc); msleep(1);
rtl8225_write_phy_cck(dev, 0x07, 0x78); msleep(1);
rtl8225_write_phy_cck(dev, 0x08, 0x2e); msleep(1);
rtl8225_write_phy_cck(dev, 0x10, 0x93); msleep(1);
rtl8225_write_phy_cck(dev, 0x11, 0x88); msleep(1);
rtl8225_write_phy_cck(dev, 0x12, 0x47); msleep(1);
rtl8225_write_phy_cck(dev, 0x13, 0xd0);
rtl8225_write_phy_cck(dev, 0x19, 0x00);
rtl8225_write_phy_cck(dev, 0x1a, 0xa0);
rtl8225_write_phy_cck(dev, 0x1b, 0x08);
rtl8225_write_phy_cck(dev, 0x40, 0x86);
rtl8225_write_phy_cck(dev, 0x41, 0x8a); msleep(1);
rtl8225_write_phy_cck(dev, 0x42, 0x15); msleep(1);
rtl8225_write_phy_cck(dev, 0x43, 0x18); msleep(1);
rtl8225_write_phy_cck(dev, 0x44, 0x36); msleep(1);
rtl8225_write_phy_cck(dev, 0x45, 0x35); msleep(1);
rtl8225_write_phy_cck(dev, 0x46, 0x2e); msleep(1);
rtl8225_write_phy_cck(dev, 0x47, 0x25); msleep(1);
rtl8225_write_phy_cck(dev, 0x48, 0x1c); msleep(1);
rtl8225_write_phy_cck(dev, 0x49, 0x12); msleep(1);
rtl8225_write_phy_cck(dev, 0x4a, 0x09); msleep(1);
rtl8225_write_phy_cck(dev, 0x4b, 0x04); msleep(1);
rtl8225_write_phy_cck(dev, 0x4c, 0x05); msleep(1);
rtl818x_iowrite8(priv, (u8 __iomem *)((void __iomem *)priv->map + 0x5B), 0x0D); msleep(1);
rtl8225z2_rf_set_tx_power(dev, 1);
/* RX antenna default to A */
rtl8225_write_phy_cck(dev, 0x10, 0x9b); msleep(1); /* B: 0xDB */
rtl8225_write_phy_ofdm(dev, 0x26, 0x90); msleep(1); /* B: 0x10 */
rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03); /* B: 0x00 */
msleep(1);
rtl818x_iowrite32(priv, (__le32 __iomem *)((void __iomem *)priv->map + 0x94), 0x15c00002);
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
}
static void rtl8225_rf_stop(struct ieee80211_hw *dev)
{
struct rtl8180_priv *priv = dev->priv;
u8 reg;
rtl8225_write(dev, 0x4, 0x1f); msleep(1);
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_OFF);
rtl818x_iowrite32(priv, &priv->map->ANAPARAM, RTL8225_ANAPARAM_OFF);
rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
}
static void rtl8225_rf_set_channel(struct ieee80211_hw *dev,
struct ieee80211_conf *conf)
{
struct rtl8180_priv *priv = dev->priv;
int chan =
ieee80211_frequency_to_channel(conf->chandef.chan->center_freq);
if (priv->rf->init == rtl8225_rf_init)
rtl8225_rf_set_tx_power(dev, chan);
else
rtl8225z2_rf_set_tx_power(dev, chan);
rtl8225_write(dev, 0x7, rtl8225_chan[chan - 1]);
msleep(10);
}
static const struct rtl818x_rf_ops rtl8225_ops = {
.name = "rtl8225",
.init = rtl8225_rf_init,
.stop = rtl8225_rf_stop,
.set_chan = rtl8225_rf_set_channel,
};
static const struct rtl818x_rf_ops rtl8225z2_ops = {
.name = "rtl8225z2",
.init = rtl8225z2_rf_init,
.stop = rtl8225_rf_stop,
.set_chan = rtl8225_rf_set_channel,
};
const struct rtl818x_rf_ops * rtl8180_detect_rf(struct ieee80211_hw *dev)
{
struct rtl8180_priv *priv = dev->priv;
u16 reg8, reg9;
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x0488);
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
msleep(100);
rtl8225_write(dev, 0, 0x1B7);
reg8 = rtl8225_read(dev, 8);
reg9 = rtl8225_read(dev, 9);
rtl8225_write(dev, 0, 0x0B7);
if (reg8 != 0x588 || reg9 != 0x700)
return &rtl8225_ops;
return &rtl8225z2_ops;
}

23
drivers/net/wireless/rtl818x/rtl8180/rtl8225.h Normal file
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@ -0,0 +1,23 @@
#ifndef RTL8180_RTL8225_H
#define RTL8180_RTL8225_H
#define RTL8225_ANAPARAM_ON 0xa0000b59
#define RTL8225_ANAPARAM2_ON 0x860dec11
#define RTL8225_ANAPARAM_OFF 0xa00beb59
#define RTL8225_ANAPARAM2_OFF 0x840dec11
const struct rtl818x_rf_ops * rtl8180_detect_rf(struct ieee80211_hw *);
static inline void rtl8225_write_phy_ofdm(struct ieee80211_hw *dev,
u8 addr, u8 data)
{
rtl8180_write_phy(dev, addr, data);
}
static inline void rtl8225_write_phy_cck(struct ieee80211_hw *dev,
u8 addr, u8 data)
{
rtl8180_write_phy(dev, addr, data | 0x10000);
}
#endif /* RTL8180_RTL8225_H */

475
drivers/net/wireless/rtl818x/rtl8180/rtl8225se.c Normal file
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/* Radio tuning for RTL8225 on RTL8187SE
*
* Copyright 2009 Larry Finger <Larry.Finger@lwfinger.net>
* Copyright 2014 Andrea Merello <andrea.merello@gmail.com>
*
* Based on the r8180 and Realtek r8187se drivers, which are:
* Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
*
* Also based on the rtl8187 driver, which is:
* Copyright 2007 Michael Wu <flamingice@sourmilk.net>
* Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <net/mac80211.h>
#include "rtl8180.h"
#include "rtl8225se.h"
#define PFX "rtl8225 (se) "
static const u32 RF_GAIN_TABLE[] = {
0x0096, 0x0076, 0x0056, 0x0036, 0x0016, 0x01f6, 0x01d6, 0x01b6,
0x0196, 0x0176, 0x00F7, 0x00D7, 0x00B7, 0x0097, 0x0077, 0x0057,
0x0037, 0x00FB, 0x00DB, 0x00BB, 0x00FF, 0x00E3, 0x00C3, 0x00A3,
0x0083, 0x0063, 0x0043, 0x0023, 0x0003, 0x01E3, 0x01C3, 0x01A3,
0x0183, 0x0163, 0x0143, 0x0123, 0x0103
};
static const u8 cck_ofdm_gain_settings[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
};
static const u8 rtl8225se_tx_gain_cck_ofdm[] = {
0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
};
static const u8 rtl8225se_tx_power_cck[] = {
0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
};
static const u8 rtl8225se_tx_power_cck_ch14[] = {
0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
};
static const u8 rtl8225se_tx_power_ofdm[] = {
0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
};
static const u32 rtl8225se_chan[] = {
0x0080, 0x0100, 0x0180, 0x0200, 0x0280, 0x0300, 0x0380,
0x0400, 0x0480, 0x0500, 0x0580, 0x0600, 0x0680, 0x074A,
};
static const u8 rtl8225sez2_tx_power_cck_ch14[] = {
0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
};
static const u8 rtl8225sez2_tx_power_cck_B[] = {
0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x04
};
static const u8 rtl8225sez2_tx_power_cck_A[] = {
0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04
};
static const u8 rtl8225sez2_tx_power_cck[] = {
0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
};
static const u8 ZEBRA_AGC[] = {
0x7E, 0x7E, 0x7E, 0x7E, 0x7D, 0x7C, 0x7B, 0x7A,
0x79, 0x78, 0x77, 0x76, 0x75, 0x74, 0x73, 0x72,
0x71, 0x70, 0x6F, 0x6E, 0x6D, 0x6C, 0x6B, 0x6A,
0x69, 0x68, 0x67, 0x66, 0x65, 0x64, 0x63, 0x62,
0x48, 0x47, 0x46, 0x45, 0x44, 0x29, 0x28, 0x27,
0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x08, 0x07,
0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
0x0f, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x15, 0x16,
0x17, 0x17, 0x18, 0x18, 0x19, 0x1a, 0x1a, 0x1b,
0x1b, 0x1c, 0x1c, 0x1d, 0x1d, 0x1d, 0x1e, 0x1e,
0x1f, 0x1f, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x21,
0x21, 0x21, 0x22, 0x22, 0x22, 0x23, 0x23, 0x24,
0x24, 0x25, 0x25, 0x25, 0x26, 0x26, 0x27, 0x27,
0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F
};
static const u8 OFDM_CONFIG[] = {
0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
0xD8, 0x3C, 0x7B, 0x10, 0x10
};
static void rtl8187se_three_wire_io(struct ieee80211_hw *dev, u8 *data,
u8 len, bool write)
{
struct rtl8180_priv *priv = dev->priv;
int i;
u8 tmp;
do {
for (i = 0; i < 5; i++) {
tmp = rtl818x_ioread8(priv, SW_3W_CMD1);
if (!(tmp & 0x3))
break;
udelay(10);
}
if (i == 5)
wiphy_err(dev->wiphy, PFX
"CmdReg: 0x%x RE/WE bits aren't clear\n", tmp);
tmp = rtl818x_ioread8(priv, &priv->map->rf_sw_config) | 0x02;
rtl818x_iowrite8(priv, &priv->map->rf_sw_config, tmp);
tmp = rtl818x_ioread8(priv, REG_ADDR1(0x84)) & 0xF7;
rtl818x_iowrite8(priv, REG_ADDR1(0x84), tmp);
if (write) {
if (len == 16) {
rtl818x_iowrite16(priv, SW_3W_DB0,
*(u16 *)data);
} else if (len == 64) {
rtl818x_iowrite32(priv, SW_3W_DB0_4,
*((u32 *)data));
rtl818x_iowrite32(priv, SW_3W_DB1_4,
*((u32 *)(data + 4)));
} else
wiphy_err(dev->wiphy, PFX
"Unimplemented length\n");
} else {
rtl818x_iowrite16(priv, SW_3W_DB0, *(u16 *)data);
}
if (write)
tmp = 2;
else
tmp = 1;
rtl818x_iowrite8(priv, SW_3W_CMD1, tmp);
for (i = 0; i < 5; i++) {
tmp = rtl818x_ioread8(priv, SW_3W_CMD1);
if (!(tmp & 0x3))
break;
udelay(10);
}
rtl818x_iowrite8(priv, SW_3W_CMD1, 0);
if (!write) {
*((u16 *)data) = rtl818x_ioread16(priv, SI_DATA_REG);
*((u16 *)data) &= 0x0FFF;
}
} while (0);
}
static u32 rtl8187se_rf_readreg(struct ieee80211_hw *dev, u8 addr)
{
u32 dataread = addr & 0x0F;
rtl8187se_three_wire_io(dev, (u8 *)&dataread, 16, 0);
return dataread;
}
static void rtl8187se_rf_writereg(struct ieee80211_hw *dev, u8 addr, u32 data)
{
u32 outdata = (data << 4) | (u32)(addr & 0x0F);
rtl8187se_three_wire_io(dev, (u8 *)&outdata, 16, 1);
}
static void rtl8225se_write_zebra_agc(struct ieee80211_hw *dev)
{
int i;
for (i = 0; i < 128; i++) {
rtl8225se_write_phy_ofdm(dev, 0xF, ZEBRA_AGC[i]);
rtl8225se_write_phy_ofdm(dev, 0xE, i+0x80);
rtl8225se_write_phy_ofdm(dev, 0xE, 0);
}
}
static void rtl8187se_write_ofdm_config(struct ieee80211_hw *dev)
{
/* write OFDM_CONFIG table */
int i;
for (i = 0; i < 60; i++)
rtl8225se_write_phy_ofdm(dev, i, OFDM_CONFIG[i]);
}
static void rtl8225sez2_rf_set_tx_power(struct ieee80211_hw *dev, int channel)
{
struct rtl8180_priv *priv = dev->priv;
u8 cck_power, ofdm_power;
cck_power = priv->channels[channel - 1].hw_value & 0xFF;
if (cck_power > 35)
cck_power = 35;
rtl818x_iowrite8(priv, &priv->map->TX_GAIN_CCK,
cck_ofdm_gain_settings[cck_power]);
usleep_range(1000, 5000);
ofdm_power = priv->channels[channel - 1].hw_value >> 8;
if (ofdm_power > 35)
ofdm_power = 35;
rtl818x_iowrite8(priv, &priv->map->TX_GAIN_OFDM,
cck_ofdm_gain_settings[ofdm_power]);
if (ofdm_power < 12) {
rtl8225se_write_phy_ofdm(dev, 7, 0x5C);
rtl8225se_write_phy_ofdm(dev, 9, 0x5C);
}
if (ofdm_power < 18) {
rtl8225se_write_phy_ofdm(dev, 7, 0x54);
rtl8225se_write_phy_ofdm(dev, 9, 0x54);
} else {
rtl8225se_write_phy_ofdm(dev, 7, 0x50);
rtl8225se_write_phy_ofdm(dev, 9, 0x50);
}
usleep_range(1000, 5000);
}
static void rtl8187se_write_rf_gain(struct ieee80211_hw *dev)
{
int i;
for (i = 0; i <= 36; i++) {
rtl8187se_rf_writereg(dev, 0x01, i); mdelay(1);
rtl8187se_rf_writereg(dev, 0x02, RF_GAIN_TABLE[i]); mdelay(1);
}
}
static void rtl8187se_write_initial_gain(struct ieee80211_hw *dev,
int init_gain)
{
switch (init_gain) {
default:
rtl8225se_write_phy_ofdm(dev, 0x17, 0x26); mdelay(1);
rtl8225se_write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
rtl8225se_write_phy_ofdm(dev, 0x05, 0xFA); mdelay(1);
break;
case 2:
rtl8225se_write_phy_ofdm(dev, 0x17, 0x36); mdelay(1);
rtl8225se_write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
rtl8225se_write_phy_ofdm(dev, 0x05, 0xFA); mdelay(1);
break;
case 3:
rtl8225se_write_phy_ofdm(dev, 0x17, 0x36); mdelay(1);
rtl8225se_write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
rtl8225se_write_phy_ofdm(dev, 0x05, 0xFB); mdelay(1);
break;
case 4:
rtl8225se_write_phy_ofdm(dev, 0x17, 0x46); mdelay(1);
rtl8225se_write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
rtl8225se_write_phy_ofdm(dev, 0x05, 0xFB); mdelay(1);
break;
case 5:
rtl8225se_write_phy_ofdm(dev, 0x17, 0x46); mdelay(1);
rtl8225se_write_phy_ofdm(dev, 0x24, 0x96); mdelay(1);
rtl8225se_write_phy_ofdm(dev, 0x05, 0xFB); mdelay(1);
break;
case 6:
rtl8225se_write_phy_ofdm(dev, 0x17, 0x56); mdelay(1);
rtl8225se_write_phy_ofdm(dev, 0x24, 0x96); mdelay(1);
rtl8225se_write_phy_ofdm(dev, 0x05, 0xFC); mdelay(1);
break;
case 7:
rtl8225se_write_phy_ofdm(dev, 0x17, 0x56); mdelay(1);
rtl8225se_write_phy_ofdm(dev, 0x24, 0xA6); mdelay(1);
rtl8225se_write_phy_ofdm(dev, 0x05, 0xFC); mdelay(1);
break;
case 8:
rtl8225se_write_phy_ofdm(dev, 0x17, 0x66); mdelay(1);
rtl8225se_write_phy_ofdm(dev, 0x24, 0xB6); mdelay(1);
rtl8225se_write_phy_ofdm(dev, 0x05, 0xFC); mdelay(1);
break;
}
}
void rtl8225se_rf_init(struct ieee80211_hw *dev)
{
struct rtl8180_priv *priv = dev->priv;
u32 rf23, rf24;
u8 d_cut = 0;
u8 tmp;
/* Page 1 */
rtl8187se_rf_writereg(dev, 0x00, 0x013F); mdelay(1);
rf23 = rtl8187se_rf_readreg(dev, 0x08); mdelay(1);
rf24 = rtl8187se_rf_readreg(dev, 0x09); mdelay(1);
if (rf23 == 0x0818 && rf24 == 0x070C)
d_cut = 1;
wiphy_info(dev->wiphy, "RTL8225-SE version %s\n",
d_cut ? "D" : "not-D");
/* Page 0: reg 0 - 15 */
rtl8187se_rf_writereg(dev, 0x00, 0x009F); mdelay(1);
rtl8187se_rf_writereg(dev, 0x01, 0x06E0); mdelay(1);
rtl8187se_rf_writereg(dev, 0x02, 0x004D); mdelay(1);
rtl8187se_rf_writereg(dev, 0x03, 0x07F1); mdelay(1);
rtl8187se_rf_writereg(dev, 0x04, 0x0975); mdelay(1);
rtl8187se_rf_writereg(dev, 0x05, 0x0C72); mdelay(1);
rtl8187se_rf_writereg(dev, 0x06, 0x0AE6); mdelay(1);
rtl8187se_rf_writereg(dev, 0x07, 0x00CA); mdelay(1);
rtl8187se_rf_writereg(dev, 0x08, 0x0E1C); mdelay(1);
rtl8187se_rf_writereg(dev, 0x09, 0x02F0); mdelay(1);
rtl8187se_rf_writereg(dev, 0x0A, 0x09D0); mdelay(1);
rtl8187se_rf_writereg(dev, 0x0B, 0x01BA); mdelay(1);
rtl8187se_rf_writereg(dev, 0x0C, 0x0640); mdelay(1);
rtl8187se_rf_writereg(dev, 0x0D, 0x08DF); mdelay(1);
rtl8187se_rf_writereg(dev, 0x0E, 0x0020); mdelay(1);
rtl8187se_rf_writereg(dev, 0x0F, 0x0990); mdelay(1);
/* page 1: reg 16-30 */
rtl8187se_rf_writereg(dev, 0x00, 0x013F); mdelay(1);
rtl8187se_rf_writereg(dev, 0x03, 0x0806); mdelay(1);
rtl8187se_rf_writereg(dev, 0x04, 0x03A7); mdelay(1);
rtl8187se_rf_writereg(dev, 0x05, 0x059B); mdelay(1);
rtl8187se_rf_writereg(dev, 0x06, 0x0081); mdelay(1);
rtl8187se_rf_writereg(dev, 0x07, 0x01A0); mdelay(1);
rtl8187se_rf_writereg(dev, 0x0A, 0x0001); mdelay(1);
rtl8187se_rf_writereg(dev, 0x0B, 0x0418); mdelay(1);
rtl8187se_rf_writereg(dev, 0x0C, 0x0FBE); mdelay(1);
rtl8187se_rf_writereg(dev, 0x0D, 0x0008); mdelay(1);
if (d_cut)
rtl8187se_rf_writereg(dev, 0x0E, 0x0807);
else
rtl8187se_rf_writereg(dev, 0x0E, 0x0806);
mdelay(1);
rtl8187se_rf_writereg(dev, 0x0F, 0x0ACC); mdelay(1);
rtl8187se_rf_writereg(dev, 0x00, 0x01D7); mdelay(1);
rtl8187se_rf_writereg(dev, 0x03, 0x0E00); mdelay(1);
rtl8187se_rf_writereg(dev, 0x04, 0x0E50); mdelay(1);
rtl8187se_write_rf_gain(dev);
rtl8187se_rf_writereg(dev, 0x05, 0x0203); mdelay(1);
rtl8187se_rf_writereg(dev, 0x06, 0x0200); mdelay(1);
rtl8187se_rf_writereg(dev, 0x00, 0x0137); mdelay(11);
rtl8187se_rf_writereg(dev, 0x0D, 0x0008); mdelay(11);
rtl8187se_rf_writereg(dev, 0x00, 0x0037); mdelay(11);
rtl8187se_rf_writereg(dev, 0x04, 0x0160); mdelay(11);
rtl8187se_rf_writereg(dev, 0x07, 0x0080); mdelay(11);
rtl8187se_rf_writereg(dev, 0x02, 0x088D); mdelay(221);
rtl8187se_rf_writereg(dev, 0x00, 0x0137); mdelay(11);
rtl8187se_rf_writereg(dev, 0x07, 0x0000); mdelay(1);
rtl8187se_rf_writereg(dev, 0x07, 0x0180); mdelay(1);
rtl8187se_rf_writereg(dev, 0x07, 0x0220); mdelay(1);
rtl8187se_rf_writereg(dev, 0x07, 0x03E0); mdelay(1);
rtl8187se_rf_writereg(dev, 0x06, 0x00C1); mdelay(1);
rtl8187se_rf_writereg(dev, 0x0A, 0x0001); mdelay(1);
if (priv->xtal_cal) {
tmp = (priv->xtal_in << 4) | (priv->xtal_out << 1) |
(1 << 11) | (1 << 9);
rtl8187se_rf_writereg(dev, 0x0F, tmp);
wiphy_info(dev->wiphy, "Xtal cal\n");
mdelay(1);
} else {
wiphy_info(dev->wiphy, "NO Xtal cal\n");
rtl8187se_rf_writereg(dev, 0x0F, 0x0ACC);
mdelay(1);
}
/* page 0 */
rtl8187se_rf_writereg(dev, 0x00, 0x00BF); mdelay(1);
rtl8187se_rf_writereg(dev, 0x0D, 0x08DF); mdelay(1);
rtl8187se_rf_writereg(dev, 0x02, 0x004D); mdelay(1);
rtl8187se_rf_writereg(dev, 0x04, 0x0975); mdelay(31);
rtl8187se_rf_writereg(dev, 0x00, 0x0197); mdelay(1);
rtl8187se_rf_writereg(dev, 0x05, 0x05AB); mdelay(1);
rtl8187se_rf_writereg(dev, 0x00, 0x009F); mdelay(1);
rtl8187se_rf_writereg(dev, 0x01, 0x0000); mdelay(1);
rtl8187se_rf_writereg(dev, 0x02, 0x0000); mdelay(1);
/* power save parameters */
/* TODO: move to dev.c */
rtl818x_iowrite8(priv, REG_ADDR1(0x024E),
rtl818x_ioread8(priv, REG_ADDR1(0x24E)) & 0x9F);
rtl8225se_write_phy_cck(dev, 0x00, 0xC8);
rtl8225se_write_phy_cck(dev, 0x06, 0x1C);
rtl8225se_write_phy_cck(dev, 0x10, 0x78);
rtl8225se_write_phy_cck(dev, 0x2E, 0xD0);
rtl8225se_write_phy_cck(dev, 0x2F, 0x06);
rtl8225se_write_phy_cck(dev, 0x01, 0x46);
/* power control */
rtl818x_iowrite8(priv, &priv->map->TX_GAIN_CCK, 0x10);
rtl818x_iowrite8(priv, &priv->map->TX_GAIN_OFDM, 0x1B);
rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03);
rtl8225se_write_phy_ofdm(dev, 0x00, 0x12);
rtl8225se_write_zebra_agc(dev);
rtl8225se_write_phy_ofdm(dev, 0x10, 0x00);
rtl8187se_write_ofdm_config(dev);
/* turn on RF */
rtl8187se_rf_writereg(dev, 0x00, 0x009F); udelay(500);
rtl8187se_rf_writereg(dev, 0x04, 0x0972); udelay(500);
/* turn on RF again */
rtl8187se_rf_writereg(dev, 0x00, 0x009F); udelay(500);
rtl8187se_rf_writereg(dev, 0x04, 0x0972); udelay(500);
/* turn on BB */
rtl8225se_write_phy_ofdm(dev, 0x10, 0x40);
rtl8225se_write_phy_ofdm(dev, 0x12, 0x40);
rtl8187se_write_initial_gain(dev, 4);
}
void rtl8225se_rf_stop(struct ieee80211_hw *dev)
{
/* checked for 8187se */
struct rtl8180_priv *priv = dev->priv;
/* turn off BB RXIQ matrix to cut off rx signal */
rtl8225se_write_phy_ofdm(dev, 0x10, 0x00);
rtl8225se_write_phy_ofdm(dev, 0x12, 0x00);
/* turn off RF */
rtl8187se_rf_writereg(dev, 0x04, 0x0000);
rtl8187se_rf_writereg(dev, 0x00, 0x0000);
usleep_range(1000, 5000);
/* turn off A/D and D/A */
rtl8180_set_anaparam(priv, RTL8225SE_ANAPARAM_OFF);
rtl8180_set_anaparam2(priv, RTL8225SE_ANAPARAM2_OFF);
}
void rtl8225se_rf_set_channel(struct ieee80211_hw *dev,
struct ieee80211_conf *conf)
{
int chan =
ieee80211_frequency_to_channel(conf->chandef.chan->center_freq);
rtl8225sez2_rf_set_tx_power(dev, chan);
rtl8187se_rf_writereg(dev, 0x7, rtl8225se_chan[chan - 1]);
if ((rtl8187se_rf_readreg(dev, 0x7) & 0x0F80) !=
rtl8225se_chan[chan - 1])
rtl8187se_rf_writereg(dev, 0x7, rtl8225se_chan[chan - 1]);
usleep_range(10000, 20000);
}
static const struct rtl818x_rf_ops rtl8225se_ops = {
.name = "rtl8225-se",
.init = rtl8225se_rf_init,
.stop = rtl8225se_rf_stop,
.set_chan = rtl8225se_rf_set_channel,
};
const struct rtl818x_rf_ops *rtl8187se_detect_rf(struct ieee80211_hw *dev)
{
return &rtl8225se_ops;
}

61
drivers/net/wireless/rtl818x/rtl8180/rtl8225se.h Normal file
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@ -0,0 +1,61 @@
/* Definitions for RTL8187SE hardware
*
* Copyright 2009 Larry Finger <Larry.Finger@lwfinger.net>
* Copyright 2014 Andrea Merello <andrea.merello@gmail.com>
*
* Based on the r8180 and Realtek r8187se drivers, which are:
* Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
*
* Also based on the rtl8187 driver, which is:
* Copyright 2007 Michael Wu <flamingice@sourmilk.net>
* Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef RTL8187SE_RTL8225_H
#define RTL8187SE_RTL8225_H
#define RTL8225SE_ANAPARAM_ON 0xb0054d00
#define RTL8225SE_ANAPARAM2_ON 0x000004c6
/* all off except PLL */
#define RTL8225SE_ANAPARAM_OFF 0xb0054dec
/* all on including PLL */
#define RTL8225SE_ANAPARAM_OFF2 0xb0054dfc
#define RTL8225SE_ANAPARAM2_OFF 0x00ff04c6
#define RTL8225SE_ANAPARAM3 0x10
enum rtl8187se_power_state {
RTL8187SE_POWER_ON,
RTL8187SE_POWER_OFF,
RTL8187SE_POWER_SLEEP
};
static inline void rtl8225se_write_phy_ofdm(struct ieee80211_hw *dev,
u8 addr, u8 data)
{
rtl8180_write_phy(dev, addr, data);
}
static inline void rtl8225se_write_phy_cck(struct ieee80211_hw *dev,
u8 addr, u8 data)
{
rtl8180_write_phy(dev, addr, data | 0x10000);
}
const struct rtl818x_rf_ops *rtl8187se_detect_rf(struct ieee80211_hw *);
void rtl8225se_rf_stop(struct ieee80211_hw *dev);
void rtl8225se_rf_set_channel(struct ieee80211_hw *dev,
struct ieee80211_conf *conf);
void rtl8225se_rf_conf_erp(struct ieee80211_hw *dev,
struct ieee80211_bss_conf *info);
void rtl8225se_rf_init(struct ieee80211_hw *dev);
#endif /* RTL8187SE_RTL8225_H */

228
drivers/net/wireless/rtl818x/rtl8180/sa2400.c Normal file
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@ -0,0 +1,228 @@
/*
* Radio tuning for Philips SA2400 on RTL8180
*
* Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
*
* Code from the BSD driver and the rtl8181 project have been
* very useful to understand certain things
*
* I want to thanks the Authors of such projects and the Ndiswrapper
* project Authors.
*
* A special Big Thanks also is for all people who donated me cards,
* making possible the creation of the original rtl8180 driver
* from which this code is derived!
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/pci.h>
#include <linux/delay.h>
#include <net/mac80211.h>
#include "rtl8180.h"
#include "sa2400.h"
static const u32 sa2400_chan[] = {
0x00096c, /* ch1 */
0x080970,
0x100974,
0x180978,
0x000980,
0x080984,
0x100988,
0x18098c,
0x000994,
0x080998,
0x10099c,
0x1809a0,
0x0009a8,
0x0009b4, /* ch 14 */
};
static void write_sa2400(struct ieee80211_hw *dev, u8 addr, u32 data)
{
struct rtl8180_priv *priv = dev->priv;
u32 phy_config;
/* MAC will bang bits to the sa2400. sw 3-wire is NOT used */
phy_config = 0xb0000000;
phy_config |= ((u32)(addr & 0xf)) << 24;
phy_config |= data & 0xffffff;
rtl818x_iowrite32(priv,
(__le32 __iomem *) &priv->map->RFPinsOutput, phy_config);
msleep(3);
}
static void sa2400_write_phy_antenna(struct ieee80211_hw *dev, short chan)
{
struct rtl8180_priv *priv = dev->priv;
u8 ant = SA2400_ANTENNA;
if (priv->rfparam & RF_PARAM_ANTBDEFAULT)
ant |= BB_ANTENNA_B;
if (chan == 14)
ant |= BB_ANTATTEN_CHAN14;
rtl8180_write_phy(dev, 0x10, ant);
}
static u8 sa2400_rf_rssi_map[] = {
0x64, 0x64, 0x63, 0x62, 0x61, 0x60, 0x5f, 0x5e,
0x5d, 0x5c, 0x5b, 0x5a, 0x57, 0x54, 0x52, 0x50,
0x4e, 0x4c, 0x4a, 0x48, 0x46, 0x44, 0x41, 0x3f,
0x3c, 0x3a, 0x37, 0x36, 0x36, 0x1c, 0x1c, 0x1b,
0x1b, 0x1a, 0x1a, 0x19, 0x19, 0x18, 0x18, 0x17,
0x17, 0x16, 0x16, 0x15, 0x15, 0x14, 0x14, 0x13,
0x13, 0x12, 0x12, 0x11, 0x11, 0x10, 0x10, 0x0f,
0x0f, 0x0e, 0x0e, 0x0d, 0x0d, 0x0c, 0x0c, 0x0b,
0x0b, 0x0a, 0x0a, 0x09, 0x09, 0x08, 0x08, 0x07,
0x07, 0x06, 0x06, 0x05, 0x04, 0x03, 0x02,
};
static u8 sa2400_rf_calc_rssi(u8 agc, u8 sq)
{
if (sq == 0x80)
return 1;
if (sq > 78)
return 32;
/* TODO: recalc sa2400_rf_rssi_map to avoid mult / div */
return 65 * sa2400_rf_rssi_map[sq] / 100;
}
static void sa2400_rf_set_channel(struct ieee80211_hw *dev,
struct ieee80211_conf *conf)
{
struct rtl8180_priv *priv = dev->priv;
int channel =
ieee80211_frequency_to_channel(conf->chandef.chan->center_freq);
u32 txpw = priv->channels[channel - 1].hw_value & 0xFF;
u32 chan = sa2400_chan[channel - 1];
write_sa2400(dev, 7, txpw);
sa2400_write_phy_antenna(dev, channel);
write_sa2400(dev, 0, chan);
write_sa2400(dev, 1, 0xbb50);
write_sa2400(dev, 2, 0x80);
write_sa2400(dev, 3, 0);
}
static void sa2400_rf_stop(struct ieee80211_hw *dev)
{
write_sa2400(dev, 4, 0);
}
static void sa2400_rf_init(struct ieee80211_hw *dev)
{
struct rtl8180_priv *priv = dev->priv;
u32 anaparam, txconf;
u8 firdac;
int analogphy = priv->rfparam & RF_PARAM_ANALOGPHY;
anaparam = priv->anaparam;
anaparam &= ~(1 << ANAPARAM_TXDACOFF_SHIFT);
anaparam &= ~ANAPARAM_PWR1_MASK;
anaparam &= ~ANAPARAM_PWR0_MASK;
if (analogphy) {
anaparam |= SA2400_ANA_ANAPARAM_PWR1_ON << ANAPARAM_PWR1_SHIFT;
firdac = 0;
} else {
anaparam |= (SA2400_DIG_ANAPARAM_PWR1_ON << ANAPARAM_PWR1_SHIFT);
anaparam |= (SA2400_ANAPARAM_PWR0_ON << ANAPARAM_PWR0_SHIFT);
firdac = 1 << SA2400_REG4_FIRDAC_SHIFT;
}
rtl8180_set_anaparam(priv, anaparam);
write_sa2400(dev, 0, sa2400_chan[0]);
write_sa2400(dev, 1, 0xbb50);
write_sa2400(dev, 2, 0x80);
write_sa2400(dev, 3, 0);
write_sa2400(dev, 4, 0x19340 | firdac);
write_sa2400(dev, 5, 0x1dfb | (SA2400_MAX_SENS - 54) << 15);
write_sa2400(dev, 4, 0x19348 | firdac); /* calibrate VCO */
if (!analogphy)
write_sa2400(dev, 4, 0x1938c); /*???*/
write_sa2400(dev, 4, 0x19340 | firdac);
write_sa2400(dev, 0, sa2400_chan[0]);
write_sa2400(dev, 1, 0xbb50);
write_sa2400(dev, 2, 0x80);
write_sa2400(dev, 3, 0);
write_sa2400(dev, 4, 0x19344 | firdac); /* calibrate filter */
/* new from rtl8180 embedded driver (rtl8181 project) */
write_sa2400(dev, 6, 0x13ff | (1 << 23)); /* MANRX */
write_sa2400(dev, 8, 0); /* VCO */
if (analogphy) {
rtl8180_set_anaparam(priv, anaparam |
(1 << ANAPARAM_TXDACOFF_SHIFT));
txconf = rtl818x_ioread32(priv, &priv->map->TX_CONF);
rtl818x_iowrite32(priv, &priv->map->TX_CONF,
txconf | RTL818X_TX_CONF_LOOPBACK_CONT);
write_sa2400(dev, 4, 0x19341); /* calibrates DC */
/* a 5us sleep is required here,
* we rely on the 3ms delay introduced in write_sa2400 */
write_sa2400(dev, 4, 0x19345);
/* a 20us sleep is required here,
* we rely on the 3ms delay introduced in write_sa2400 */
rtl818x_iowrite32(priv, &priv->map->TX_CONF, txconf);
rtl8180_set_anaparam(priv, anaparam);
}
/* end new code */
write_sa2400(dev, 4, 0x19341 | firdac); /* RTX MODE */
/* baseband configuration */
rtl8180_write_phy(dev, 0, 0x98);
rtl8180_write_phy(dev, 3, 0x38);
rtl8180_write_phy(dev, 4, 0xe0);
rtl8180_write_phy(dev, 5, 0x90);
rtl8180_write_phy(dev, 6, 0x1a);
rtl8180_write_phy(dev, 7, 0x64);
sa2400_write_phy_antenna(dev, 1);
rtl8180_write_phy(dev, 0x11, 0x80);
if (rtl818x_ioread8(priv, &priv->map->CONFIG2) &
RTL818X_CONFIG2_ANTENNA_DIV)
rtl8180_write_phy(dev, 0x12, 0xc7); /* enable ant diversity */
else
rtl8180_write_phy(dev, 0x12, 0x47); /* disable ant diversity */
rtl8180_write_phy(dev, 0x13, 0x90 | priv->csthreshold);
rtl8180_write_phy(dev, 0x19, 0x0);
rtl8180_write_phy(dev, 0x1a, 0xa0);
}
const struct rtl818x_rf_ops sa2400_rf_ops = {
.name = "Philips",
.init = sa2400_rf_init,
.stop = sa2400_rf_stop,
.set_chan = sa2400_rf_set_channel,
.calc_rssi = sa2400_rf_calc_rssi,
};

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#ifndef RTL8180_SA2400_H
#define RTL8180_SA2400_H
/*
* Radio tuning for Philips SA2400 on RTL8180
*
* Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
*
* Code from the BSD driver and the rtl8181 project have been
* very useful to understand certain things
*
* I want to thanks the Authors of such projects and the Ndiswrapper
* project Authors.
*
* A special Big Thanks also is for all people who donated me cards,
* making possible the creation of the original rtl8180 driver
* from which this code is derived!
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define SA2400_ANTENNA 0x91
#define SA2400_DIG_ANAPARAM_PWR1_ON 0x8
#define SA2400_ANA_ANAPARAM_PWR1_ON 0x28
#define SA2400_ANAPARAM_PWR0_ON 0x3
/* RX sensitivity in dbm */
#define SA2400_MAX_SENS 85
#define SA2400_REG4_FIRDAC_SHIFT 7
extern const struct rtl818x_rf_ops sa2400_rf_ops;
#endif /* RTL8180_SA2400_H */

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rtl8187-objs := dev.o rtl8225.o leds.o rfkill.o
obj-$(CONFIG_RTL8187) += rtl8187.o
ccflags-y += -Idrivers/net/wireless/rtl818x

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drivers/net/wireless/rtl818x/rtl8187/dev.c Normal file
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245
drivers/net/wireless/rtl818x/rtl8187/leds.c Normal file
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/*
* Linux LED driver for RTL8187
*
* Copyright 2009 Larry Finger <Larry.Finger@lwfinger.net>
*
* Based on the LED handling in the r8187 driver, which is:
* Copyright (c) Realtek Semiconductor Corp. All rights reserved.
*
* Thanks to Realtek for their support!
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifdef CONFIG_RTL8187_LEDS
#include <net/mac80211.h>
#include <linux/usb.h>
#include <linux/eeprom_93cx6.h>
#include "rtl8187.h"
#include "leds.h"
static void led_turn_on(struct work_struct *work)
{
/* As this routine does read/write operations on the hardware, it must
* be run from a work queue.
*/
u8 reg;
struct rtl8187_priv *priv = container_of(work, struct rtl8187_priv,
led_on.work);
struct rtl8187_led *led = &priv->led_tx;
/* Don't change the LED, when the device is down. */
if (!priv->vif || priv->vif->type == NL80211_IFTYPE_UNSPECIFIED)
return ;
/* Skip if the LED is not registered. */
if (!led->dev)
return;
mutex_lock(&priv->conf_mutex);
switch (led->ledpin) {
case LED_PIN_GPIO0:
rtl818x_iowrite8(priv, &priv->map->GPIO0, 0x01);
rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0x00);
break;
case LED_PIN_LED0:
reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~(1 << 4);
rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
break;
case LED_PIN_LED1:
reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~(1 << 5);
rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
break;
case LED_PIN_HW:
default:
break;
}
mutex_unlock(&priv->conf_mutex);
}
static void led_turn_off(struct work_struct *work)
{
/* As this routine does read/write operations on the hardware, it must
* be run from a work queue.
*/
u8 reg;
struct rtl8187_priv *priv = container_of(work, struct rtl8187_priv,
led_off.work);
struct rtl8187_led *led = &priv->led_tx;
/* Don't change the LED, when the device is down. */
if (!priv->vif || priv->vif->type == NL80211_IFTYPE_UNSPECIFIED)
return ;
/* Skip if the LED is not registered. */
if (!led->dev)
return;
mutex_lock(&priv->conf_mutex);
switch (led->ledpin) {
case LED_PIN_GPIO0:
rtl818x_iowrite8(priv, &priv->map->GPIO0, 0x01);
rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0x01);
break;
case LED_PIN_LED0:
reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) | (1 << 4);
rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
break;
case LED_PIN_LED1:
reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) | (1 << 5);
rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
break;
case LED_PIN_HW:
default:
break;
}
mutex_unlock(&priv->conf_mutex);
}
/* Callback from the LED subsystem. */
static void rtl8187_led_brightness_set(struct led_classdev *led_dev,
enum led_brightness brightness)
{
struct rtl8187_led *led = container_of(led_dev, struct rtl8187_led,
led_dev);
struct ieee80211_hw *hw = led->dev;
struct rtl8187_priv *priv;
static bool radio_on;
if (!hw)
return;
priv = hw->priv;
if (led->is_radio) {
if (brightness == LED_FULL) {
ieee80211_queue_delayed_work(hw, &priv->led_on, 0);
radio_on = true;
} else if (radio_on) {
radio_on = false;
cancel_delayed_work(&priv->led_on);
ieee80211_queue_delayed_work(hw, &priv->led_off, 0);
}
} else if (radio_on) {
if (brightness == LED_OFF) {
ieee80211_queue_delayed_work(hw, &priv->led_off, 0);
/* The LED is off for 1/20 sec - it just blinks. */
ieee80211_queue_delayed_work(hw, &priv->led_on,
HZ / 20);
} else
ieee80211_queue_delayed_work(hw, &priv->led_on, 0);
}
}
static int rtl8187_register_led(struct ieee80211_hw *dev,
struct rtl8187_led *led, const char *name,
const char *default_trigger, u8 ledpin,
bool is_radio)
{
int err;
struct rtl8187_priv *priv = dev->priv;
if (led->dev)
return -EEXIST;
if (!default_trigger)
return -EINVAL;
led->dev = dev;
led->ledpin = ledpin;
led->is_radio = is_radio;
strncpy(led->name, name, sizeof(led->name));
led->led_dev.name = led->name;
led->led_dev.default_trigger = default_trigger;
led->led_dev.brightness_set = rtl8187_led_brightness_set;
err = led_classdev_register(&priv->udev->dev, &led->led_dev);
if (err) {
printk(KERN_INFO "LEDs: Failed to register %s\n", name);
led->dev = NULL;
return err;
}
return 0;
}
static void rtl8187_unregister_led(struct rtl8187_led *led)
{
struct ieee80211_hw *hw = led->dev;
struct rtl8187_priv *priv = hw->priv;
led_classdev_unregister(&led->led_dev);
flush_delayed_work(&priv->led_off);
led->dev = NULL;
}
void rtl8187_leds_init(struct ieee80211_hw *dev, u16 custid)
{
struct rtl8187_priv *priv = dev->priv;
char name[RTL8187_LED_MAX_NAME_LEN + 1];
u8 ledpin;
int err;
/* According to the vendor driver, the LED operation depends on the
* customer ID encoded in the EEPROM
*/
printk(KERN_INFO "rtl8187: Customer ID is 0x%02X\n", custid);
switch (custid) {
case EEPROM_CID_RSVD0:
case EEPROM_CID_RSVD1:
case EEPROM_CID_SERCOMM_PS:
case EEPROM_CID_QMI:
case EEPROM_CID_DELL:
case EEPROM_CID_TOSHIBA:
ledpin = LED_PIN_GPIO0;
break;
case EEPROM_CID_ALPHA0:
ledpin = LED_PIN_LED0;
break;
case EEPROM_CID_HW:
ledpin = LED_PIN_HW;
break;
default:
ledpin = LED_PIN_GPIO0;
}
INIT_DELAYED_WORK(&priv->led_on, led_turn_on);
INIT_DELAYED_WORK(&priv->led_off, led_turn_off);
snprintf(name, sizeof(name),
"rtl8187-%s::radio", wiphy_name(dev->wiphy));
err = rtl8187_register_led(dev, &priv->led_radio, name,
ieee80211_get_radio_led_name(dev), ledpin, true);
if (err)
return;
snprintf(name, sizeof(name),
"rtl8187-%s::tx", wiphy_name(dev->wiphy));
err = rtl8187_register_led(dev, &priv->led_tx, name,
ieee80211_get_tx_led_name(dev), ledpin, false);
if (err)
goto err_tx;
snprintf(name, sizeof(name),
"rtl8187-%s::rx", wiphy_name(dev->wiphy));
err = rtl8187_register_led(dev, &priv->led_rx, name,
ieee80211_get_rx_led_name(dev), ledpin, false);
if (!err)
return;
/* registration of RX LED failed - unregister */
rtl8187_unregister_led(&priv->led_tx);
err_tx:
rtl8187_unregister_led(&priv->led_radio);
}
void rtl8187_leds_exit(struct ieee80211_hw *dev)
{
struct rtl8187_priv *priv = dev->priv;
rtl8187_unregister_led(&priv->led_radio);
rtl8187_unregister_led(&priv->led_rx);
rtl8187_unregister_led(&priv->led_tx);
cancel_delayed_work_sync(&priv->led_off);
cancel_delayed_work_sync(&priv->led_on);
}
#endif /* def CONFIG_RTL8187_LEDS */

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drivers/net/wireless/rtl818x/rtl8187/leds.h Normal file
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/*
* Definitions for RTL8187 leds
*
* Copyright 2009 Larry Finger <Larry.Finger@lwfinger.net>
*
* Based on the LED handling in the r8187 driver, which is:
* Copyright (c) Realtek Semiconductor Corp. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef RTL8187_LED_H
#define RTL8187_LED_H
#ifdef CONFIG_RTL8187_LEDS
#define RTL8187_LED_MAX_NAME_LEN 21
#include <linux/leds.h>
#include <linux/types.h>
enum {
LED_PIN_LED0,
LED_PIN_LED1,
LED_PIN_GPIO0,
LED_PIN_HW
};
enum {
EEPROM_CID_RSVD0 = 0x00,
EEPROM_CID_RSVD1 = 0xFF,
EEPROM_CID_ALPHA0 = 0x01,
EEPROM_CID_SERCOMM_PS = 0x02,
EEPROM_CID_HW = 0x03,
EEPROM_CID_TOSHIBA = 0x04,
EEPROM_CID_QMI = 0x07,
EEPROM_CID_DELL = 0x08
};
struct rtl8187_led {
struct ieee80211_hw *dev;
/* The LED class device */
struct led_classdev led_dev;
/* The pin/method used to control the led */
u8 ledpin;
/* The unique name string for this LED device. */
char name[RTL8187_LED_MAX_NAME_LEN + 1];
/* If the LED is radio or tx/rx */
bool is_radio;
};
void rtl8187_leds_init(struct ieee80211_hw *dev, u16 code);
void rtl8187_leds_exit(struct ieee80211_hw *dev);
#endif /* def CONFIG_RTL8187_LEDS */
#endif /* RTL8187_LED_H */

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drivers/net/wireless/rtl818x/rtl8187/rfkill.c Normal file
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/*
* Linux RFKILL support for RTL8187
*
* Copyright (c) 2009 Herton Ronaldo Krzesinski <herton@mandriva.com.br>
*
* Based on the RFKILL handling in the r8187 driver, which is:
* Copyright (c) Realtek Semiconductor Corp. All rights reserved.
*
* Thanks to Realtek for their support!
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/types.h>
#include <linux/usb.h>
#include <net/mac80211.h>
#include "rtl8187.h"
#include "rfkill.h"
static bool rtl8187_is_radio_enabled(struct rtl8187_priv *priv)
{
u8 gpio;
gpio = rtl818x_ioread8(priv, &priv->map->GPIO0);
rtl818x_iowrite8(priv, &priv->map->GPIO0, gpio & ~priv->rfkill_mask);
gpio = rtl818x_ioread8(priv, &priv->map->GPIO1);
return gpio & priv->rfkill_mask;
}
void rtl8187_rfkill_init(struct ieee80211_hw *hw)
{
struct rtl8187_priv *priv = hw->priv;
priv->rfkill_off = rtl8187_is_radio_enabled(priv);
printk(KERN_INFO "rtl8187: wireless switch is %s\n",
priv->rfkill_off ? "on" : "off");
wiphy_rfkill_set_hw_state(hw->wiphy, !priv->rfkill_off);
wiphy_rfkill_start_polling(hw->wiphy);
}
void rtl8187_rfkill_poll(struct ieee80211_hw *hw)
{
bool enabled;
struct rtl8187_priv *priv = hw->priv;
mutex_lock(&priv->conf_mutex);
enabled = rtl8187_is_radio_enabled(priv);
if (unlikely(enabled != priv->rfkill_off)) {
priv->rfkill_off = enabled;
printk(KERN_INFO "rtl8187: wireless radio switch turned %s\n",
enabled ? "on" : "off");
wiphy_rfkill_set_hw_state(hw->wiphy, !enabled);
}
mutex_unlock(&priv->conf_mutex);
}
void rtl8187_rfkill_exit(struct ieee80211_hw *hw)
{
wiphy_rfkill_stop_polling(hw->wiphy);
}

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drivers/net/wireless/rtl818x/rtl8187/rfkill.h Normal file
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#ifndef RTL8187_RFKILL_H
#define RTL8187_RFKILL_H
void rtl8187_rfkill_init(struct ieee80211_hw *hw);
void rtl8187_rfkill_poll(struct ieee80211_hw *hw);
void rtl8187_rfkill_exit(struct ieee80211_hw *hw);
#endif /* RTL8187_RFKILL_H */

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drivers/net/wireless/rtl818x/rtl8187/rtl8187.h Normal file
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/*
* Definitions for RTL8187 hardware
*
* Copyright 2007 Michael Wu <flamingice@sourmilk.net>
* Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
*
* Based on the r8187 driver, which is:
* Copyright 2005 Andrea Merello <andrea.merello@gmail.com>, et al.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef RTL8187_H
#define RTL8187_H
#include <linux/cache.h>
#include "rtl818x.h"
#include "leds.h"
#define RTL8187_EEPROM_TXPWR_BASE 0x05
#define RTL8187_EEPROM_MAC_ADDR 0x07
#define RTL8187_EEPROM_TXPWR_CHAN_1 0x16 /* 3 channels */
#define RTL8187_EEPROM_TXPWR_CHAN_6 0x1B /* 2 channels */
#define RTL8187_EEPROM_TXPWR_CHAN_4 0x3D /* 2 channels */
#define RTL8187_EEPROM_SELECT_GPIO 0x3B
#define RTL8187_REQT_READ 0xC0
#define RTL8187_REQT_WRITE 0x40
#define RTL8187_REQ_GET_REG 0x05
#define RTL8187_REQ_SET_REG 0x05
#define RTL8187_MAX_RX 0x9C4
#define RFKILL_MASK_8187_89_97 0x2
#define RFKILL_MASK_8198 0x4
#define RETRY_COUNT 7
struct rtl8187_rx_info {
struct urb *urb;
struct ieee80211_hw *dev;
};
struct rtl8187_rx_hdr {
__le32 flags;
u8 noise;
u8 signal;
u8 agc;
u8 reserved;
__le64 mac_time;
} __packed;
struct rtl8187b_rx_hdr {
__le32 flags;
__le64 mac_time;
u8 sq;
u8 rssi;
u8 agc;
u8 flags2;
__le16 snr_long2end;
s8 pwdb_g12;
u8 fot;
} __packed;
/* {rtl8187,rtl8187b}_tx_info is in skb */
struct rtl8187_tx_hdr {
__le32 flags;
__le16 rts_duration;
__le16 len;
__le32 retry;
} __packed;
struct rtl8187b_tx_hdr {
__le32 flags;
__le16 rts_duration;
__le16 len;
__le32 unused_1;
__le16 unused_2;
__le16 tx_duration;
__le32 unused_3;
__le32 retry;
__le32 unused_4[2];
} __packed;
enum {
DEVICE_RTL8187,
DEVICE_RTL8187B
};
struct rtl8187_vif {
struct ieee80211_hw *dev;
/* beaconing */
struct delayed_work beacon_work;
bool enable_beacon;
};
struct rtl8187_priv {
/* common between rtl818x drivers */
struct rtl818x_csr *map;
const struct rtl818x_rf_ops *rf;
struct ieee80211_vif *vif;
/* The mutex protects the TX loopback state.
* Any attempt to set channels concurrently locks the device.
*/
struct mutex conf_mutex;
/* rtl8187 specific */
struct ieee80211_channel channels[14];
struct ieee80211_rate rates[12];
struct ieee80211_supported_band band;
struct usb_device *udev;
u32 rx_conf;
struct usb_anchor anchored;
struct delayed_work work;
struct ieee80211_hw *dev;
#ifdef CONFIG_RTL8187_LEDS
struct rtl8187_led led_radio;
struct rtl8187_led led_tx;
struct rtl8187_led led_rx;
struct delayed_work led_on;
struct delayed_work led_off;
#endif
u16 txpwr_base;
u8 asic_rev;
u8 is_rtl8187b;
enum {
RTL8187BvB,
RTL8187BvD,
RTL8187BvE
} hw_rev;
struct sk_buff_head rx_queue;
u8 signal;
u8 noise;
u8 slot_time;
u8 aifsn[4];
u8 rfkill_mask;
struct {
union {
__le64 buf;
u8 dummy1[L1_CACHE_BYTES];
} ____cacheline_aligned;
struct sk_buff_head queue;
} b_tx_status; /* This queue is used by both -b and non-b devices */
struct mutex io_mutex;
union {
u8 bits8;
__le16 bits16;
__le32 bits32;
u8 dummy2[L1_CACHE_BYTES];
} *io_dmabuf ____cacheline_aligned;
bool rfkill_off;
u16 seqno;
};
void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data);
static inline u8 rtl818x_ioread8_idx(struct rtl8187_priv *priv,
u8 *addr, u8 idx)
{
u8 val;
mutex_lock(&priv->io_mutex);
usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0),
RTL8187_REQ_GET_REG, RTL8187_REQT_READ,
(unsigned long)addr, idx & 0x03,
&priv->io_dmabuf->bits8, sizeof(val), HZ / 2);
val = priv->io_dmabuf->bits8;
mutex_unlock(&priv->io_mutex);
return val;
}
static inline u8 rtl818x_ioread8(struct rtl8187_priv *priv, u8 *addr)
{
return rtl818x_ioread8_idx(priv, addr, 0);
}
static inline u16 rtl818x_ioread16_idx(struct rtl8187_priv *priv,
__le16 *addr, u8 idx)
{
__le16 val;
mutex_lock(&priv->io_mutex);
usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0),
RTL8187_REQ_GET_REG, RTL8187_REQT_READ,
(unsigned long)addr, idx & 0x03,
&priv->io_dmabuf->bits16, sizeof(val), HZ / 2);
val = priv->io_dmabuf->bits16;
mutex_unlock(&priv->io_mutex);
return le16_to_cpu(val);
}
static inline u16 rtl818x_ioread16(struct rtl8187_priv *priv, __le16 *addr)
{
return rtl818x_ioread16_idx(priv, addr, 0);
}
static inline u32 rtl818x_ioread32_idx(struct rtl8187_priv *priv,
__le32 *addr, u8 idx)
{
__le32 val;
mutex_lock(&priv->io_mutex);
usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0),
RTL8187_REQ_GET_REG, RTL8187_REQT_READ,
(unsigned long)addr, idx & 0x03,
&priv->io_dmabuf->bits32, sizeof(val), HZ / 2);
val = priv->io_dmabuf->bits32;
mutex_unlock(&priv->io_mutex);
return le32_to_cpu(val);
}
static inline u32 rtl818x_ioread32(struct rtl8187_priv *priv, __le32 *addr)
{
return rtl818x_ioread32_idx(priv, addr, 0);
}
static inline void rtl818x_iowrite8_idx(struct rtl8187_priv *priv,
u8 *addr, u8 val, u8 idx)
{
mutex_lock(&priv->io_mutex);
priv->io_dmabuf->bits8 = val;
usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
RTL8187_REQ_SET_REG, RTL8187_REQT_WRITE,
(unsigned long)addr, idx & 0x03,
&priv->io_dmabuf->bits8, sizeof(val), HZ / 2);
mutex_unlock(&priv->io_mutex);
}
static inline void rtl818x_iowrite8(struct rtl8187_priv *priv, u8 *addr, u8 val)
{
rtl818x_iowrite8_idx(priv, addr, val, 0);
}
static inline void rtl818x_iowrite16_idx(struct rtl8187_priv *priv,
__le16 *addr, u16 val, u8 idx)
{
mutex_lock(&priv->io_mutex);
priv->io_dmabuf->bits16 = cpu_to_le16(val);
usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
RTL8187_REQ_SET_REG, RTL8187_REQT_WRITE,
(unsigned long)addr, idx & 0x03,
&priv->io_dmabuf->bits16, sizeof(val), HZ / 2);
mutex_unlock(&priv->io_mutex);
}
static inline void rtl818x_iowrite16(struct rtl8187_priv *priv, __le16 *addr,
u16 val)
{
rtl818x_iowrite16_idx(priv, addr, val, 0);
}
static inline void rtl818x_iowrite32_idx(struct rtl8187_priv *priv,
__le32 *addr, u32 val, u8 idx)
{
mutex_lock(&priv->io_mutex);
priv->io_dmabuf->bits32 = cpu_to_le32(val);
usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
RTL8187_REQ_SET_REG, RTL8187_REQT_WRITE,
(unsigned long)addr, idx & 0x03,
&priv->io_dmabuf->bits32, sizeof(val), HZ / 2);
mutex_unlock(&priv->io_mutex);
}
static inline void rtl818x_iowrite32(struct rtl8187_priv *priv, __le32 *addr,
u32 val)
{
rtl818x_iowrite32_idx(priv, addr, val, 0);
}
#endif /* RTL8187_H */

961
drivers/net/wireless/rtl818x/rtl8187/rtl8225.c Normal file
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@ -0,0 +1,961 @@
/*
* Radio tuning for RTL8225 on RTL8187
*
* Copyright 2007 Michael Wu <flamingice@sourmilk.net>
* Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
*
* Based on the r8187 driver, which is:
* Copyright 2005 Andrea Merello <andrea.merello@gmail.com>, et al.
*
* Magic delays, register offsets, and phy value tables below are
* taken from the original r8187 driver sources. Thanks to Realtek
* for their support!
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/usb.h>
#include <net/mac80211.h>
#include "rtl8187.h"
#include "rtl8225.h"
static void rtl8225_write_bitbang(struct ieee80211_hw *dev, u8 addr, u16 data)
{
struct rtl8187_priv *priv = dev->priv;
u16 reg80, reg84, reg82;
u32 bangdata;
int i;
bangdata = (data << 4) | (addr & 0xf);
reg80 = rtl818x_ioread16(priv, &priv->map->RFPinsOutput) & 0xfff3;
reg82 = rtl818x_ioread16(priv, &priv->map->RFPinsEnable);
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82 | 0x7);
reg84 = rtl818x_ioread16(priv, &priv->map->RFPinsSelect);
rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x7);
udelay(10);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 2));
udelay(2);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80);
udelay(10);
for (i = 15; i >= 0; i--) {
u16 reg = reg80 | (bangdata & (1 << i)) >> i;
if (i & 1)
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg | (1 << 1));
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg | (1 << 1));
if (!(i & 1))
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg);
}
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 2));
udelay(10);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 2));
rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84);
}
static void rtl8225_write_8051(struct ieee80211_hw *dev, u8 addr, __le16 data)
{
struct rtl8187_priv *priv = dev->priv;
u16 reg80, reg82, reg84;
reg80 = rtl818x_ioread16(priv, &priv->map->RFPinsOutput);
reg82 = rtl818x_ioread16(priv, &priv->map->RFPinsEnable);
reg84 = rtl818x_ioread16(priv, &priv->map->RFPinsSelect);
reg80 &= ~(0x3 << 2);
reg84 &= ~0xF;
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82 | 0x0007);
rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x0007);
udelay(10);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 2));
udelay(2);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80);
udelay(10);
mutex_lock(&priv->io_mutex);
priv->io_dmabuf->bits16 = data;
usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
RTL8187_REQ_SET_REG, RTL8187_REQT_WRITE,
addr, 0x8225, &priv->io_dmabuf->bits16, sizeof(data),
HZ / 2);
mutex_unlock(&priv->io_mutex);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 2));
udelay(10);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 2));
rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84);
}
static void rtl8225_write(struct ieee80211_hw *dev, u8 addr, u16 data)
{
struct rtl8187_priv *priv = dev->priv;
if (priv->asic_rev)
rtl8225_write_8051(dev, addr, cpu_to_le16(data));
else
rtl8225_write_bitbang(dev, addr, data);
}
static u16 rtl8225_read(struct ieee80211_hw *dev, u8 addr)
{
struct rtl8187_priv *priv = dev->priv;
u16 reg80, reg82, reg84, out;
int i;
reg80 = rtl818x_ioread16(priv, &priv->map->RFPinsOutput);
reg82 = rtl818x_ioread16(priv, &priv->map->RFPinsEnable);
reg84 = rtl818x_ioread16(priv, &priv->map->RFPinsSelect);
reg80 &= ~0xF;
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82 | 0x000F);
rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x000F);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 2));
udelay(4);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80);
udelay(5);
for (i = 4; i >= 0; i--) {
u16 reg = reg80 | ((addr >> i) & 1);
if (!(i & 1)) {
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg);
udelay(1);
}
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg | (1 << 1));
udelay(2);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg | (1 << 1));
udelay(2);
if (i & 1) {
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg);
udelay(1);
}
}
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3) | (1 << 1));
udelay(2);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3));
udelay(2);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3));
udelay(2);
out = 0;
for (i = 11; i >= 0; i--) {
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3));
udelay(1);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3) | (1 << 1));
udelay(2);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3) | (1 << 1));
udelay(2);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3) | (1 << 1));
udelay(2);
if (rtl818x_ioread16(priv, &priv->map->RFPinsInput) & (1 << 1))
out |= 1 << i;
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3));
udelay(2);
}
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput,
reg80 | (1 << 3) | (1 << 2));
udelay(2);
rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82);
rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84);
rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x03A0);
return out;
}
static const u16 rtl8225bcd_rxgain[] = {
0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
};
static const u8 rtl8225_agc[] = {
0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e,
0x9d, 0x9c, 0x9b, 0x9a, 0x99, 0x98, 0x97, 0x96,
0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 0x8f, 0x8e,
0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86,
0x85, 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e,
0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38, 0x37, 0x36,
0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 0x2e,
0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26,
0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e,
0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16,
0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06,
0x05, 0x04, 0x03, 0x02, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
};
static const u8 rtl8225_gain[] = {
0x23, 0x88, 0x7c, 0xa5, /* -82dBm */
0x23, 0x88, 0x7c, 0xb5, /* -82dBm */
0x23, 0x88, 0x7c, 0xc5, /* -82dBm */
0x33, 0x80, 0x79, 0xc5, /* -78dBm */
0x43, 0x78, 0x76, 0xc5, /* -74dBm */
0x53, 0x60, 0x73, 0xc5, /* -70dBm */
0x63, 0x58, 0x70, 0xc5, /* -66dBm */
};
static const u8 rtl8225_threshold[] = {
0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd
};
static const u8 rtl8225_tx_gain_cck_ofdm[] = {
0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
};
static const u8 rtl8225_tx_power_cck[] = {
0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
};
static const u8 rtl8225_tx_power_cck_ch14[] = {
0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
};
static const u8 rtl8225_tx_power_ofdm[] = {
0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
};
static const u32 rtl8225_chan[] = {
0x085c, 0x08dc, 0x095c, 0x09dc, 0x0a5c, 0x0adc, 0x0b5c,
0x0bdc, 0x0c5c, 0x0cdc, 0x0d5c, 0x0ddc, 0x0e5c, 0x0f72
};
static void rtl8225_rf_set_tx_power(struct ieee80211_hw *dev, int channel)
{
struct rtl8187_priv *priv = dev->priv;
u8 cck_power, ofdm_power;
const u8 *tmp;
u32 reg;
int i;
cck_power = priv->channels[channel - 1].hw_value & 0xF;
ofdm_power = priv->channels[channel - 1].hw_value >> 4;
cck_power = min(cck_power, (u8)11);
if (ofdm_power > (u8)15)
ofdm_power = 25;
else
ofdm_power += 10;
rtl818x_iowrite8(priv, &priv->map->TX_GAIN_CCK,
rtl8225_tx_gain_cck_ofdm[cck_power / 6] >> 1);
if (channel == 14)
tmp = &rtl8225_tx_power_cck_ch14[(cck_power % 6) * 8];
else
tmp = &rtl8225_tx_power_cck[(cck_power % 6) * 8];
for (i = 0; i < 8; i++)
rtl8225_write_phy_cck(dev, 0x44 + i, *tmp++);
msleep(1); // FIXME: optional?
/* anaparam2 on */
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
rtl818x_iowrite8(priv, &priv->map->CONFIG3,
reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
RTL8187_RTL8225_ANAPARAM2_ON);
rtl818x_iowrite8(priv, &priv->map->CONFIG3,
reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
rtl8225_write_phy_ofdm(dev, 2, 0x42);
rtl8225_write_phy_ofdm(dev, 6, 0x00);
rtl8225_write_phy_ofdm(dev, 8, 0x00);
rtl818x_iowrite8(priv, &priv->map->TX_GAIN_OFDM,
rtl8225_tx_gain_cck_ofdm[ofdm_power / 6] >> 1);
tmp = &rtl8225_tx_power_ofdm[ofdm_power % 6];
rtl8225_write_phy_ofdm(dev, 5, *tmp);
rtl8225_write_phy_ofdm(dev, 7, *tmp);
msleep(1);
}
static void rtl8225_rf_init(struct ieee80211_hw *dev)
{
struct rtl8187_priv *priv = dev->priv;
int i;
rtl8225_write(dev, 0x0, 0x067);
rtl8225_write(dev, 0x1, 0xFE0);
rtl8225_write(dev, 0x2, 0x44D);
rtl8225_write(dev, 0x3, 0x441);
rtl8225_write(dev, 0x4, 0x486);
rtl8225_write(dev, 0x5, 0xBC0);
rtl8225_write(dev, 0x6, 0xAE6);
rtl8225_write(dev, 0x7, 0x82A);
rtl8225_write(dev, 0x8, 0x01F);
rtl8225_write(dev, 0x9, 0x334);
rtl8225_write(dev, 0xA, 0xFD4);
rtl8225_write(dev, 0xB, 0x391);
rtl8225_write(dev, 0xC, 0x050);
rtl8225_write(dev, 0xD, 0x6DB);
rtl8225_write(dev, 0xE, 0x029);
rtl8225_write(dev, 0xF, 0x914); msleep(100);
rtl8225_write(dev, 0x2, 0xC4D); msleep(200);
rtl8225_write(dev, 0x2, 0x44D); msleep(200);
if (!(rtl8225_read(dev, 6) & (1 << 7))) {
rtl8225_write(dev, 0x02, 0x0c4d);
msleep(200);
rtl8225_write(dev, 0x02, 0x044d);
msleep(100);
if (!(rtl8225_read(dev, 6) & (1 << 7)))
wiphy_warn(dev->wiphy, "RF Calibration Failed! %x\n",
rtl8225_read(dev, 6));
}
rtl8225_write(dev, 0x0, 0x127);
for (i = 0; i < ARRAY_SIZE(rtl8225bcd_rxgain); i++) {
rtl8225_write(dev, 0x1, i + 1);
rtl8225_write(dev, 0x2, rtl8225bcd_rxgain[i]);
}
rtl8225_write(dev, 0x0, 0x027);
rtl8225_write(dev, 0x0, 0x22F);
for (i = 0; i < ARRAY_SIZE(rtl8225_agc); i++) {
rtl8225_write_phy_ofdm(dev, 0xB, rtl8225_agc[i]);
rtl8225_write_phy_ofdm(dev, 0xA, 0x80 + i);
}
msleep(1);
rtl8225_write_phy_ofdm(dev, 0x00, 0x01);
rtl8225_write_phy_ofdm(dev, 0x01, 0x02);
rtl8225_write_phy_ofdm(dev, 0x02, 0x42);
rtl8225_write_phy_ofdm(dev, 0x03, 0x00);
rtl8225_write_phy_ofdm(dev, 0x04, 0x00);
rtl8225_write_phy_ofdm(dev, 0x05, 0x00);
rtl8225_write_phy_ofdm(dev, 0x06, 0x40);
rtl8225_write_phy_ofdm(dev, 0x07, 0x00);
rtl8225_write_phy_ofdm(dev, 0x08, 0x40);
rtl8225_write_phy_ofdm(dev, 0x09, 0xfe);
rtl8225_write_phy_ofdm(dev, 0x0a, 0x09);
rtl8225_write_phy_ofdm(dev, 0x0b, 0x80);
rtl8225_write_phy_ofdm(dev, 0x0c, 0x01);
rtl8225_write_phy_ofdm(dev, 0x0e, 0xd3);
rtl8225_write_phy_ofdm(dev, 0x0f, 0x38);
rtl8225_write_phy_ofdm(dev, 0x10, 0x84);
rtl8225_write_phy_ofdm(dev, 0x11, 0x06);
rtl8225_write_phy_ofdm(dev, 0x12, 0x20);
rtl8225_write_phy_ofdm(dev, 0x13, 0x20);
rtl8225_write_phy_ofdm(dev, 0x14, 0x00);
rtl8225_write_phy_ofdm(dev, 0x15, 0x40);
rtl8225_write_phy_ofdm(dev, 0x16, 0x00);
rtl8225_write_phy_ofdm(dev, 0x17, 0x40);
rtl8225_write_phy_ofdm(dev, 0x18, 0xef);
rtl8225_write_phy_ofdm(dev, 0x19, 0x19);
rtl8225_write_phy_ofdm(dev, 0x1a, 0x20);
rtl8225_write_phy_ofdm(dev, 0x1b, 0x76);
rtl8225_write_phy_ofdm(dev, 0x1c, 0x04);
rtl8225_write_phy_ofdm(dev, 0x1e, 0x95);
rtl8225_write_phy_ofdm(dev, 0x1f, 0x75);
rtl8225_write_phy_ofdm(dev, 0x20, 0x1f);
rtl8225_write_phy_ofdm(dev, 0x21, 0x27);
rtl8225_write_phy_ofdm(dev, 0x22, 0x16);
rtl8225_write_phy_ofdm(dev, 0x24, 0x46);
rtl8225_write_phy_ofdm(dev, 0x25, 0x20);
rtl8225_write_phy_ofdm(dev, 0x26, 0x90);
rtl8225_write_phy_ofdm(dev, 0x27, 0x88);
rtl8225_write_phy_ofdm(dev, 0x0d, rtl8225_gain[2 * 4]);
rtl8225_write_phy_ofdm(dev, 0x1b, rtl8225_gain[2 * 4 + 2]);
rtl8225_write_phy_ofdm(dev, 0x1d, rtl8225_gain[2 * 4 + 3]);
rtl8225_write_phy_ofdm(dev, 0x23, rtl8225_gain[2 * 4 + 1]);
rtl8225_write_phy_cck(dev, 0x00, 0x98);
rtl8225_write_phy_cck(dev, 0x03, 0x20);
rtl8225_write_phy_cck(dev, 0x04, 0x7e);
rtl8225_write_phy_cck(dev, 0x05, 0x12);
rtl8225_write_phy_cck(dev, 0x06, 0xfc);
rtl8225_write_phy_cck(dev, 0x07, 0x78);
rtl8225_write_phy_cck(dev, 0x08, 0x2e);
rtl8225_write_phy_cck(dev, 0x10, 0x9b);
rtl8225_write_phy_cck(dev, 0x11, 0x88);
rtl8225_write_phy_cck(dev, 0x12, 0x47);
rtl8225_write_phy_cck(dev, 0x13, 0xd0);
rtl8225_write_phy_cck(dev, 0x19, 0x00);
rtl8225_write_phy_cck(dev, 0x1a, 0xa0);
rtl8225_write_phy_cck(dev, 0x1b, 0x08);
rtl8225_write_phy_cck(dev, 0x40, 0x86);
rtl8225_write_phy_cck(dev, 0x41, 0x8d);
rtl8225_write_phy_cck(dev, 0x42, 0x15);
rtl8225_write_phy_cck(dev, 0x43, 0x18);
rtl8225_write_phy_cck(dev, 0x44, 0x1f);
rtl8225_write_phy_cck(dev, 0x45, 0x1e);
rtl8225_write_phy_cck(dev, 0x46, 0x1a);
rtl8225_write_phy_cck(dev, 0x47, 0x15);
rtl8225_write_phy_cck(dev, 0x48, 0x10);
rtl8225_write_phy_cck(dev, 0x49, 0x0a);
rtl8225_write_phy_cck(dev, 0x4a, 0x05);
rtl8225_write_phy_cck(dev, 0x4b, 0x02);
rtl8225_write_phy_cck(dev, 0x4c, 0x05);
rtl818x_iowrite8(priv, &priv->map->TESTR, 0x0D);
rtl8225_rf_set_tx_power(dev, 1);
/* RX antenna default to A */
rtl8225_write_phy_cck(dev, 0x10, 0x9b); /* B: 0xDB */
rtl8225_write_phy_ofdm(dev, 0x26, 0x90); /* B: 0x10 */
rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03); /* B: 0x00 */
msleep(1);
rtl818x_iowrite32(priv, (__le32 *)0xFF94, 0x3dc00002);
/* set sensitivity */
rtl8225_write(dev, 0x0c, 0x50);
rtl8225_write_phy_ofdm(dev, 0x0d, rtl8225_gain[2 * 4]);
rtl8225_write_phy_ofdm(dev, 0x1b, rtl8225_gain[2 * 4 + 2]);
rtl8225_write_phy_ofdm(dev, 0x1d, rtl8225_gain[2 * 4 + 3]);
rtl8225_write_phy_ofdm(dev, 0x23, rtl8225_gain[2 * 4 + 1]);
rtl8225_write_phy_cck(dev, 0x41, rtl8225_threshold[2]);
}
static const u8 rtl8225z2_agc[] = {
0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51, 0x4f,
0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x39, 0x37,
0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25, 0x23, 0x21, 0x1f,
0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09, 0x07,
0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19,
0x19, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28,
0x28, 0x29, 0x2a, 0x2a, 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d,
0x2d, 0x2d, 0x2d, 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30,
0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31,
0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31
};
static const u8 rtl8225z2_ofdm[] = {
0x10, 0x0d, 0x01, 0x00, 0x14, 0xfb, 0xfb, 0x60,
0x00, 0x60, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00,
0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xa8, 0x26,
0x32, 0x33, 0x07, 0xa5, 0x6f, 0x55, 0xc8, 0xb3,
0x0a, 0xe1, 0x2C, 0x8a, 0x86, 0x83, 0x34, 0x0f,
0x4f, 0x24, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00,
0xc0, 0xc1, 0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e,
0x6d, 0x3c, 0xfb, 0x07
};
static const u8 rtl8225z2_tx_power_cck_ch14[] = {
0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00,
0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00
};
static const u8 rtl8225z2_tx_power_cck[] = {
0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04,
0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03,
0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03,
0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03
};
static const u8 rtl8225z2_tx_power_ofdm[] = {
0x42, 0x00, 0x40, 0x00, 0x40
};
static const u8 rtl8225z2_tx_gain_cck_ofdm[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23
};
static void rtl8225z2_rf_set_tx_power(struct ieee80211_hw *dev, int channel)
{
struct rtl8187_priv *priv = dev->priv;
u8 cck_power, ofdm_power;
const u8 *tmp;
u32 reg;
int i;
cck_power = priv->channels[channel - 1].hw_value & 0xF;
ofdm_power = priv->channels[channel - 1].hw_value >> 4;
cck_power = min(cck_power, (u8)15);
cck_power += priv->txpwr_base & 0xF;
cck_power = min(cck_power, (u8)35);
if (ofdm_power > (u8)15)
ofdm_power = 25;
else
ofdm_power += 10;
ofdm_power += priv->txpwr_base >> 4;
ofdm_power = min(ofdm_power, (u8)35);
if (channel == 14)
tmp = rtl8225z2_tx_power_cck_ch14;
else
tmp = rtl8225z2_tx_power_cck;
for (i = 0; i < 8; i++)
rtl8225_write_phy_cck(dev, 0x44 + i, *tmp++);
rtl818x_iowrite8(priv, &priv->map->TX_GAIN_CCK,
rtl8225z2_tx_gain_cck_ofdm[cck_power]);
msleep(1);
/* anaparam2 on */
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
rtl818x_iowrite8(priv, &priv->map->CONFIG3,
reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
RTL8187_RTL8225_ANAPARAM2_ON);
rtl818x_iowrite8(priv, &priv->map->CONFIG3,
reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
rtl8225_write_phy_ofdm(dev, 2, 0x42);
rtl8225_write_phy_ofdm(dev, 5, 0x00);
rtl8225_write_phy_ofdm(dev, 6, 0x40);
rtl8225_write_phy_ofdm(dev, 7, 0x00);
rtl8225_write_phy_ofdm(dev, 8, 0x40);
rtl818x_iowrite8(priv, &priv->map->TX_GAIN_OFDM,
rtl8225z2_tx_gain_cck_ofdm[ofdm_power]);
msleep(1);
}
static void rtl8225z2_b_rf_set_tx_power(struct ieee80211_hw *dev, int channel)
{
struct rtl8187_priv *priv = dev->priv;
u8 cck_power, ofdm_power;
const u8 *tmp;
int i;
cck_power = priv->channels[channel - 1].hw_value & 0xF;
ofdm_power = priv->channels[channel - 1].hw_value >> 4;
if (cck_power > 15)
cck_power = (priv->hw_rev == RTL8187BvB) ? 15 : 22;
else
cck_power += (priv->hw_rev == RTL8187BvB) ? 0 : 7;
cck_power += priv->txpwr_base & 0xF;
cck_power = min(cck_power, (u8)35);
if (ofdm_power > 15)
ofdm_power = (priv->hw_rev == RTL8187BvB) ? 17 : 25;
else
ofdm_power += (priv->hw_rev == RTL8187BvB) ? 2 : 10;
ofdm_power += (priv->txpwr_base >> 4) & 0xF;
ofdm_power = min(ofdm_power, (u8)35);
if (channel == 14)
tmp = rtl8225z2_tx_power_cck_ch14;
else
tmp = rtl8225z2_tx_power_cck;
if (priv->hw_rev == RTL8187BvB) {
if (cck_power <= 6)
; /* do nothing */
else if (cck_power <= 11)
tmp += 8;
else
tmp += 16;
} else {
if (cck_power <= 5)
; /* do nothing */
else if (cck_power <= 11)
tmp += 8;
else if (cck_power <= 17)
tmp += 16;
else
tmp += 24;
}
for (i = 0; i < 8; i++)
rtl8225_write_phy_cck(dev, 0x44 + i, *tmp++);
rtl818x_iowrite8(priv, &priv->map->TX_GAIN_CCK,
rtl8225z2_tx_gain_cck_ofdm[cck_power] << 1);
msleep(1);
rtl818x_iowrite8(priv, &priv->map->TX_GAIN_OFDM,
rtl8225z2_tx_gain_cck_ofdm[ofdm_power] << 1);
if (priv->hw_rev == RTL8187BvB) {
if (ofdm_power <= 11) {
rtl8225_write_phy_ofdm(dev, 0x87, 0x60);
rtl8225_write_phy_ofdm(dev, 0x89, 0x60);
} else {
rtl8225_write_phy_ofdm(dev, 0x87, 0x5c);
rtl8225_write_phy_ofdm(dev, 0x89, 0x5c);
}
} else {
if (ofdm_power <= 11) {
rtl8225_write_phy_ofdm(dev, 0x87, 0x5c);
rtl8225_write_phy_ofdm(dev, 0x89, 0x5c);
} else if (ofdm_power <= 17) {
rtl8225_write_phy_ofdm(dev, 0x87, 0x54);
rtl8225_write_phy_ofdm(dev, 0x89, 0x54);
} else {
rtl8225_write_phy_ofdm(dev, 0x87, 0x50);
rtl8225_write_phy_ofdm(dev, 0x89, 0x50);
}
}
msleep(1);
}
static const u16 rtl8225z2_rxgain[] = {
0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
};
static const u8 rtl8225z2_gain_bg[] = {
0x23, 0x15, 0xa5, /* -82-1dBm */
0x23, 0x15, 0xb5, /* -82-2dBm */
0x23, 0x15, 0xc5, /* -82-3dBm */
0x33, 0x15, 0xc5, /* -78dBm */
0x43, 0x15, 0xc5, /* -74dBm */
0x53, 0x15, 0xc5, /* -70dBm */
0x63, 0x15, 0xc5 /* -66dBm */
};
static void rtl8225z2_rf_init(struct ieee80211_hw *dev)
{
struct rtl8187_priv *priv = dev->priv;
int i;
rtl8225_write(dev, 0x0, 0x2BF);
rtl8225_write(dev, 0x1, 0xEE0);
rtl8225_write(dev, 0x2, 0x44D);
rtl8225_write(dev, 0x3, 0x441);
rtl8225_write(dev, 0x4, 0x8C3);
rtl8225_write(dev, 0x5, 0xC72);
rtl8225_write(dev, 0x6, 0x0E6);
rtl8225_write(dev, 0x7, 0x82A);
rtl8225_write(dev, 0x8, 0x03F);
rtl8225_write(dev, 0x9, 0x335);
rtl8225_write(dev, 0xa, 0x9D4);
rtl8225_write(dev, 0xb, 0x7BB);
rtl8225_write(dev, 0xc, 0x850);
rtl8225_write(dev, 0xd, 0xCDF);
rtl8225_write(dev, 0xe, 0x02B);
rtl8225_write(dev, 0xf, 0x114);
msleep(100);
rtl8225_write(dev, 0x0, 0x1B7);
for (i = 0; i < ARRAY_SIZE(rtl8225z2_rxgain); i++) {
rtl8225_write(dev, 0x1, i + 1);
rtl8225_write(dev, 0x2, rtl8225z2_rxgain[i]);
}
rtl8225_write(dev, 0x3, 0x080);
rtl8225_write(dev, 0x5, 0x004);
rtl8225_write(dev, 0x0, 0x0B7);
rtl8225_write(dev, 0x2, 0xc4D);
msleep(200);
rtl8225_write(dev, 0x2, 0x44D);
msleep(100);
if (!(rtl8225_read(dev, 6) & (1 << 7))) {
rtl8225_write(dev, 0x02, 0x0C4D);
msleep(200);
rtl8225_write(dev, 0x02, 0x044D);
msleep(100);
if (!(rtl8225_read(dev, 6) & (1 << 7)))
wiphy_warn(dev->wiphy, "RF Calibration Failed! %x\n",
rtl8225_read(dev, 6));
}
msleep(200);
rtl8225_write(dev, 0x0, 0x2BF);
for (i = 0; i < ARRAY_SIZE(rtl8225_agc); i++) {
rtl8225_write_phy_ofdm(dev, 0xB, rtl8225_agc[i]);
rtl8225_write_phy_ofdm(dev, 0xA, 0x80 + i);
}
msleep(1);
rtl8225_write_phy_ofdm(dev, 0x00, 0x01);
rtl8225_write_phy_ofdm(dev, 0x01, 0x02);
rtl8225_write_phy_ofdm(dev, 0x02, 0x42);
rtl8225_write_phy_ofdm(dev, 0x03, 0x00);
rtl8225_write_phy_ofdm(dev, 0x04, 0x00);
rtl8225_write_phy_ofdm(dev, 0x05, 0x00);
rtl8225_write_phy_ofdm(dev, 0x06, 0x40);
rtl8225_write_phy_ofdm(dev, 0x07, 0x00);
rtl8225_write_phy_ofdm(dev, 0x08, 0x40);
rtl8225_write_phy_ofdm(dev, 0x09, 0xfe);
rtl8225_write_phy_ofdm(dev, 0x0a, 0x08);
rtl8225_write_phy_ofdm(dev, 0x0b, 0x80);
rtl8225_write_phy_ofdm(dev, 0x0c, 0x01);
rtl8225_write_phy_ofdm(dev, 0x0d, 0x43);
rtl8225_write_phy_ofdm(dev, 0x0e, 0xd3);
rtl8225_write_phy_ofdm(dev, 0x0f, 0x38);
rtl8225_write_phy_ofdm(dev, 0x10, 0x84);
rtl8225_write_phy_ofdm(dev, 0x11, 0x07);
rtl8225_write_phy_ofdm(dev, 0x12, 0x20);
rtl8225_write_phy_ofdm(dev, 0x13, 0x20);
rtl8225_write_phy_ofdm(dev, 0x14, 0x00);
rtl8225_write_phy_ofdm(dev, 0x15, 0x40);
rtl8225_write_phy_ofdm(dev, 0x16, 0x00);
rtl8225_write_phy_ofdm(dev, 0x17, 0x40);
rtl8225_write_phy_ofdm(dev, 0x18, 0xef);
rtl8225_write_phy_ofdm(dev, 0x19, 0x19);
rtl8225_write_phy_ofdm(dev, 0x1a, 0x20);
rtl8225_write_phy_ofdm(dev, 0x1b, 0x15);
rtl8225_write_phy_ofdm(dev, 0x1c, 0x04);
rtl8225_write_phy_ofdm(dev, 0x1d, 0xc5);
rtl8225_write_phy_ofdm(dev, 0x1e, 0x95);
rtl8225_write_phy_ofdm(dev, 0x1f, 0x75);
rtl8225_write_phy_ofdm(dev, 0x20, 0x1f);
rtl8225_write_phy_ofdm(dev, 0x21, 0x17);
rtl8225_write_phy_ofdm(dev, 0x22, 0x16);
rtl8225_write_phy_ofdm(dev, 0x23, 0x80);
rtl8225_write_phy_ofdm(dev, 0x24, 0x46);
rtl8225_write_phy_ofdm(dev, 0x25, 0x00);
rtl8225_write_phy_ofdm(dev, 0x26, 0x90);
rtl8225_write_phy_ofdm(dev, 0x27, 0x88);
rtl8225_write_phy_ofdm(dev, 0x0b, rtl8225z2_gain_bg[4 * 3]);
rtl8225_write_phy_ofdm(dev, 0x1b, rtl8225z2_gain_bg[4 * 3 + 1]);
rtl8225_write_phy_ofdm(dev, 0x1d, rtl8225z2_gain_bg[4 * 3 + 2]);
rtl8225_write_phy_ofdm(dev, 0x21, 0x37);
rtl8225_write_phy_cck(dev, 0x00, 0x98);
rtl8225_write_phy_cck(dev, 0x03, 0x20);
rtl8225_write_phy_cck(dev, 0x04, 0x7e);
rtl8225_write_phy_cck(dev, 0x05, 0x12);
rtl8225_write_phy_cck(dev, 0x06, 0xfc);
rtl8225_write_phy_cck(dev, 0x07, 0x78);
rtl8225_write_phy_cck(dev, 0x08, 0x2e);
rtl8225_write_phy_cck(dev, 0x10, 0x9b);
rtl8225_write_phy_cck(dev, 0x11, 0x88);
rtl8225_write_phy_cck(dev, 0x12, 0x47);
rtl8225_write_phy_cck(dev, 0x13, 0xd0);
rtl8225_write_phy_cck(dev, 0x19, 0x00);
rtl8225_write_phy_cck(dev, 0x1a, 0xa0);
rtl8225_write_phy_cck(dev, 0x1b, 0x08);
rtl8225_write_phy_cck(dev, 0x40, 0x86);
rtl8225_write_phy_cck(dev, 0x41, 0x8d);
rtl8225_write_phy_cck(dev, 0x42, 0x15);
rtl8225_write_phy_cck(dev, 0x43, 0x18);
rtl8225_write_phy_cck(dev, 0x44, 0x36);
rtl8225_write_phy_cck(dev, 0x45, 0x35);
rtl8225_write_phy_cck(dev, 0x46, 0x2e);
rtl8225_write_phy_cck(dev, 0x47, 0x25);
rtl8225_write_phy_cck(dev, 0x48, 0x1c);
rtl8225_write_phy_cck(dev, 0x49, 0x12);
rtl8225_write_phy_cck(dev, 0x4a, 0x09);
rtl8225_write_phy_cck(dev, 0x4b, 0x04);
rtl8225_write_phy_cck(dev, 0x4c, 0x05);
rtl818x_iowrite8(priv, (u8 *)0xFF5B, 0x0D); msleep(1);
rtl8225z2_rf_set_tx_power(dev, 1);
/* RX antenna default to A */
rtl8225_write_phy_cck(dev, 0x10, 0x9b); /* B: 0xDB */
rtl8225_write_phy_ofdm(dev, 0x26, 0x90); /* B: 0x10 */
rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03); /* B: 0x00 */
msleep(1);
rtl818x_iowrite32(priv, (__le32 *)0xFF94, 0x3dc00002);
}
static void rtl8225z2_b_rf_init(struct ieee80211_hw *dev)
{
struct rtl8187_priv *priv = dev->priv;
int i;
rtl8225_write(dev, 0x0, 0x0B7);
rtl8225_write(dev, 0x1, 0xEE0);
rtl8225_write(dev, 0x2, 0x44D);
rtl8225_write(dev, 0x3, 0x441);
rtl8225_write(dev, 0x4, 0x8C3);
rtl8225_write(dev, 0x5, 0xC72);
rtl8225_write(dev, 0x6, 0x0E6);
rtl8225_write(dev, 0x7, 0x82A);
rtl8225_write(dev, 0x8, 0x03F);
rtl8225_write(dev, 0x9, 0x335);
rtl8225_write(dev, 0xa, 0x9D4);
rtl8225_write(dev, 0xb, 0x7BB);
rtl8225_write(dev, 0xc, 0x850);
rtl8225_write(dev, 0xd, 0xCDF);
rtl8225_write(dev, 0xe, 0x02B);
rtl8225_write(dev, 0xf, 0x114);
rtl8225_write(dev, 0x0, 0x1B7);
for (i = 0; i < ARRAY_SIZE(rtl8225z2_rxgain); i++) {
rtl8225_write(dev, 0x1, i + 1);
rtl8225_write(dev, 0x2, rtl8225z2_rxgain[i]);
}
rtl8225_write(dev, 0x3, 0x080);
rtl8225_write(dev, 0x5, 0x004);
rtl8225_write(dev, 0x0, 0x0B7);
rtl8225_write(dev, 0x2, 0xC4D);
rtl8225_write(dev, 0x2, 0x44D);
rtl8225_write(dev, 0x0, 0x2BF);
rtl818x_iowrite8(priv, &priv->map->TX_GAIN_CCK, 0x03);
rtl818x_iowrite8(priv, &priv->map->TX_GAIN_OFDM, 0x07);
rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03);
rtl8225_write_phy_ofdm(dev, 0x80, 0x12);
for (i = 0; i < ARRAY_SIZE(rtl8225z2_agc); i++) {
rtl8225_write_phy_ofdm(dev, 0xF, rtl8225z2_agc[i]);
rtl8225_write_phy_ofdm(dev, 0xE, 0x80 + i);
rtl8225_write_phy_ofdm(dev, 0xE, 0);
}
rtl8225_write_phy_ofdm(dev, 0x80, 0x10);
for (i = 0; i < ARRAY_SIZE(rtl8225z2_ofdm); i++)
rtl8225_write_phy_ofdm(dev, i, rtl8225z2_ofdm[i]);
rtl8225_write_phy_ofdm(dev, 0x97, 0x46);
rtl8225_write_phy_ofdm(dev, 0xa4, 0xb6);
rtl8225_write_phy_ofdm(dev, 0x85, 0xfc);
rtl8225_write_phy_cck(dev, 0xc1, 0x88);
}
static void rtl8225_rf_stop(struct ieee80211_hw *dev)
{
rtl8225_write(dev, 0x4, 0x1f);
}
static void rtl8225_rf_set_channel(struct ieee80211_hw *dev,
struct ieee80211_conf *conf)
{
struct rtl8187_priv *priv = dev->priv;
int chan =
ieee80211_frequency_to_channel(conf->chandef.chan->center_freq);
if (priv->rf->init == rtl8225_rf_init)
rtl8225_rf_set_tx_power(dev, chan);
else if (priv->rf->init == rtl8225z2_rf_init)
rtl8225z2_rf_set_tx_power(dev, chan);
else
rtl8225z2_b_rf_set_tx_power(dev, chan);
rtl8225_write(dev, 0x7, rtl8225_chan[chan - 1]);
msleep(10);
}
static const struct rtl818x_rf_ops rtl8225_ops = {
.name = "rtl8225",
.init = rtl8225_rf_init,
.stop = rtl8225_rf_stop,
.set_chan = rtl8225_rf_set_channel
};
static const struct rtl818x_rf_ops rtl8225z2_ops = {
.name = "rtl8225z2",
.init = rtl8225z2_rf_init,
.stop = rtl8225_rf_stop,
.set_chan = rtl8225_rf_set_channel
};
static const struct rtl818x_rf_ops rtl8225z2_b_ops = {
.name = "rtl8225z2",
.init = rtl8225z2_b_rf_init,
.stop = rtl8225_rf_stop,
.set_chan = rtl8225_rf_set_channel
};
const struct rtl818x_rf_ops * rtl8187_detect_rf(struct ieee80211_hw *dev)
{
u16 reg8, reg9;
struct rtl8187_priv *priv = dev->priv;
if (!priv->is_rtl8187b) {
rtl8225_write(dev, 0, 0x1B7);
reg8 = rtl8225_read(dev, 8);
reg9 = rtl8225_read(dev, 9);
rtl8225_write(dev, 0, 0x0B7);
if (reg8 != 0x588 || reg9 != 0x700)
return &rtl8225_ops;
return &rtl8225z2_ops;
} else
return &rtl8225z2_b_ops;
}

44
drivers/net/wireless/rtl818x/rtl8187/rtl8225.h Normal file
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/*
* Radio tuning definitions for RTL8225 on RTL8187
*
* Copyright 2007 Michael Wu <flamingice@sourmilk.net>
* Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
*
* Based on the r8187 driver, which is:
* Copyright 2005 Andrea Merello <andrea.merello@gmail.com>, et al.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef RTL8187_RTL8225_H
#define RTL8187_RTL8225_H
#define RTL8187_RTL8225_ANAPARAM_ON 0xa0000a59
#define RTL8187_RTL8225_ANAPARAM2_ON 0x860c7312
#define RTL8187_RTL8225_ANAPARAM_OFF 0xa00beb59
#define RTL8187_RTL8225_ANAPARAM2_OFF 0x840dec11
#define RTL8187B_RTL8225_ANAPARAM_ON 0x45090658
#define RTL8187B_RTL8225_ANAPARAM2_ON 0x727f3f52
#define RTL8187B_RTL8225_ANAPARAM3_ON 0x00
#define RTL8187B_RTL8225_ANAPARAM_OFF 0x55480658
#define RTL8187B_RTL8225_ANAPARAM2_OFF 0x72003f50
#define RTL8187B_RTL8225_ANAPARAM3_OFF 0x00
const struct rtl818x_rf_ops * rtl8187_detect_rf(struct ieee80211_hw *);
static inline void rtl8225_write_phy_ofdm(struct ieee80211_hw *dev,
u8 addr, u32 data)
{
rtl8187_write_phy(dev, addr, data);
}
static inline void rtl8225_write_phy_cck(struct ieee80211_hw *dev,
u8 addr, u32 data)
{
rtl8187_write_phy(dev, addr, data | 0x10000);
}
#endif /* RTL8187_RTL8225_H */

405
drivers/net/wireless/rtl818x/rtl818x.h Normal file
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/*
* Definitions for RTL818x hardware
*
* Copyright 2007 Michael Wu <flamingice@sourmilk.net>
* Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
*
* Based on the r8187 driver, which is:
* Copyright 2005 Andrea Merello <andrea.merello@gmail.com>, et al.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef RTL818X_H
#define RTL818X_H
struct rtl818x_csr {
u8 MAC[6];
u8 reserved_0[2];
union {
__le32 MAR[2]; /* 0x8 */
struct{ /* rtl8187se */
u8 rf_sw_config; /* 0x8 */
u8 reserved_01[3];
__le32 TMGDA; /* 0xc */
} __packed;
} __packed;
union { /* 0x10 */
struct {
u8 RX_FIFO_COUNT;
u8 reserved_1;
u8 TX_FIFO_COUNT;
u8 BQREQ;
} __packed;
__le32 TBKDA; /* for 8187se */
} __packed;
__le32 TBEDA; /* 0x14 - for rtl8187se */
__le32 TSFT[2];
union { /* 0x20 */
__le32 TLPDA;
__le32 TVIDA; /* for 8187se */
} __packed;
union { /* 0x24 */
__le32 TNPDA;
__le32 TVODA; /* for 8187se */
} __packed;
/* hi pri ring for all cards */
__le32 THPDA; /* 0x28 */
union { /* 0x2c */
struct {
u8 reserved_2a;
u8 EIFS_8187SE;
} __packed;
__le16 BRSR;
} __packed;
u8 BSSID[6]; /* 0x2e */
union { /* 0x34 */
struct {
u8 RESP_RATE;
u8 EIFS;
} __packed;
__le16 BRSR_8187SE;
} __packed;
u8 reserved_3[1]; /* 0x36 */
u8 CMD; /* 0x37 */
#define RTL818X_CMD_TX_ENABLE (1 << 2)
#define RTL818X_CMD_RX_ENABLE (1 << 3)
#define RTL818X_CMD_RESET (1 << 4)
u8 reserved_4[4]; /* 0x38 */
union {
struct {
__le16 INT_MASK;
__le16 INT_STATUS;
} __packed;
__le32 INT_STATUS_SE; /* 0x3c */
} __packed;
/* status bits for rtl8187 and rtl8180/8185 */
#define RTL818X_INT_RX_OK (1 << 0)
#define RTL818X_INT_RX_ERR (1 << 1)
#define RTL818X_INT_TXL_OK (1 << 2)
#define RTL818X_INT_TXL_ERR (1 << 3)
#define RTL818X_INT_RX_DU (1 << 4)
#define RTL818X_INT_RX_FO (1 << 5)
#define RTL818X_INT_TXN_OK (1 << 6)
#define RTL818X_INT_TXN_ERR (1 << 7)
#define RTL818X_INT_TXH_OK (1 << 8)
#define RTL818X_INT_TXH_ERR (1 << 9)
#define RTL818X_INT_TXB_OK (1 << 10)
#define RTL818X_INT_TXB_ERR (1 << 11)
#define RTL818X_INT_ATIM (1 << 12)
#define RTL818X_INT_BEACON (1 << 13)
#define RTL818X_INT_TIME_OUT (1 << 14)
#define RTL818X_INT_TX_FO (1 << 15)
/* status bits for rtl8187se */
#define RTL818X_INT_SE_TIMER3 (1 << 0)
#define RTL818X_INT_SE_TIMER2 (1 << 1)
#define RTL818X_INT_SE_RQ0SOR (1 << 2)
#define RTL818X_INT_SE_TXBED_OK (1 << 3)
#define RTL818X_INT_SE_TXBED_ERR (1 << 4)
#define RTL818X_INT_SE_TXBE_OK (1 << 5)
#define RTL818X_INT_SE_TXBE_ERR (1 << 6)
#define RTL818X_INT_SE_RX_OK (1 << 7)
#define RTL818X_INT_SE_RX_ERR (1 << 8)
#define RTL818X_INT_SE_TXL_OK (1 << 9)
#define RTL818X_INT_SE_TXL_ERR (1 << 10)
#define RTL818X_INT_SE_RX_DU (1 << 11)
#define RTL818X_INT_SE_RX_FIFO (1 << 12)
#define RTL818X_INT_SE_TXN_OK (1 << 13)
#define RTL818X_INT_SE_TXN_ERR (1 << 14)
#define RTL818X_INT_SE_TXH_OK (1 << 15)
#define RTL818X_INT_SE_TXH_ERR (1 << 16)
#define RTL818X_INT_SE_TXB_OK (1 << 17)
#define RTL818X_INT_SE_TXB_ERR (1 << 18)
#define RTL818X_INT_SE_ATIM_TO (1 << 19)
#define RTL818X_INT_SE_BK_TO (1 << 20)
#define RTL818X_INT_SE_TIMER1 (1 << 21)
#define RTL818X_INT_SE_TX_FIFO (1 << 22)
#define RTL818X_INT_SE_WAKEUP (1 << 23)
#define RTL818X_INT_SE_BK_DMA (1 << 24)
#define RTL818X_INT_SE_TMGD_OK (1 << 30)
__le32 TX_CONF; /* 0x40 */
#define RTL818X_TX_CONF_LOOPBACK_MAC (1 << 17)
#define RTL818X_TX_CONF_LOOPBACK_CONT (3 << 17)
#define RTL818X_TX_CONF_NO_ICV (1 << 19)
#define RTL818X_TX_CONF_DISCW (1 << 20)
#define RTL818X_TX_CONF_SAT_HWPLCP (1 << 24)
#define RTL818X_TX_CONF_R8180_ABCD (2 << 25)
#define RTL818X_TX_CONF_R8180_F (3 << 25)
#define RTL818X_TX_CONF_R8185_ABC (4 << 25)
#define RTL818X_TX_CONF_R8185_D (5 << 25)
#define RTL818X_TX_CONF_R8187vD (5 << 25)
#define RTL818X_TX_CONF_R8187vD_B (6 << 25)
#define RTL818X_TX_CONF_RTL8187SE (6 << 25)
#define RTL818X_TX_CONF_HWVER_MASK (7 << 25)
#define RTL818X_TX_CONF_DISREQQSIZE (1 << 28)
#define RTL818X_TX_CONF_PROBE_DTS (1 << 29)
#define RTL818X_TX_CONF_HW_SEQNUM (1 << 30)
#define RTL818X_TX_CONF_CW_MIN (1 << 31)
__le32 RX_CONF;
#define RTL818X_RX_CONF_MONITOR (1 << 0)
#define RTL818X_RX_CONF_NICMAC (1 << 1)
#define RTL818X_RX_CONF_MULTICAST (1 << 2)
#define RTL818X_RX_CONF_BROADCAST (1 << 3)
#define RTL818X_RX_CONF_FCS (1 << 5)
#define RTL818X_RX_CONF_DATA (1 << 18)
#define RTL818X_RX_CONF_CTRL (1 << 19)
#define RTL818X_RX_CONF_MGMT (1 << 20)
#define RTL818X_RX_CONF_ADDR3 (1 << 21)
#define RTL818X_RX_CONF_PM (1 << 22)
#define RTL818X_RX_CONF_BSSID (1 << 23)
#define RTL818X_RX_CONF_RX_AUTORESETPHY (1 << 28)
#define RTL818X_RX_CONF_CSDM1 (1 << 29)
#define RTL818X_RX_CONF_CSDM2 (1 << 30)
#define RTL818X_RX_CONF_ONLYERLPKT (1 << 31)
__le32 INT_TIMEOUT;
__le32 TBDA;
u8 EEPROM_CMD;
#define RTL818X_EEPROM_CMD_READ (1 << 0)
#define RTL818X_EEPROM_CMD_WRITE (1 << 1)
#define RTL818X_EEPROM_CMD_CK (1 << 2)
#define RTL818X_EEPROM_CMD_CS (1 << 3)
#define RTL818X_EEPROM_CMD_NORMAL (0 << 6)
#define RTL818X_EEPROM_CMD_LOAD (1 << 6)
#define RTL818X_EEPROM_CMD_PROGRAM (2 << 6)
#define RTL818X_EEPROM_CMD_CONFIG (3 << 6)
u8 CONFIG0;
u8 CONFIG1;
u8 CONFIG2;
#define RTL818X_CONFIG2_ANTENNA_DIV (1 << 6)
__le32 ANAPARAM;
u8 MSR;
#define RTL818X_MSR_NO_LINK (0 << 2)
#define RTL818X_MSR_ADHOC (1 << 2)
#define RTL818X_MSR_INFRA (2 << 2)
#define RTL818X_MSR_MASTER (3 << 2)
#define RTL818X_MSR_ENEDCA (4 << 2)
u8 CONFIG3;
#define RTL818X_CONFIG3_ANAPARAM_WRITE (1 << 6)
#define RTL818X_CONFIG3_GNT_SELECT (1 << 7)
u8 CONFIG4;
#define RTL818X_CONFIG4_POWEROFF (1 << 6)
#define RTL818X_CONFIG4_VCOOFF (1 << 7)
u8 TESTR;
u8 reserved_9[2];
u8 PGSELECT;
u8 SECURITY;
__le32 ANAPARAM2;
u8 reserved_10[8];
__le32 IMR; /* 0x6c - Interrupt mask reg for 8187se */
#define IMR_TMGDOK ((1 << 30))
#define IMR_DOT11HINT ((1 << 25)) /* 802.11h Measurement Interrupt */
#define IMR_BCNDMAINT ((1 << 24)) /* Beacon DMA Interrupt */
#define IMR_WAKEINT ((1 << 23)) /* Wake Up Interrupt */
#define IMR_TXFOVW ((1 << 22)) /* Tx FIFO Overflow */
#define IMR_TIMEOUT1 ((1 << 21)) /* Time Out Interrupt 1 */
#define IMR_BCNINT ((1 << 20)) /* Beacon Time out */
#define IMR_ATIMINT ((1 << 19)) /* ATIM Time Out */
#define IMR_TBDER ((1 << 18)) /* Tx Beacon Descriptor Error */
#define IMR_TBDOK ((1 << 17)) /* Tx Beacon Descriptor OK */
#define IMR_THPDER ((1 << 16)) /* Tx High Priority Descriptor Error */
#define IMR_THPDOK ((1 << 15)) /* Tx High Priority Descriptor OK */
#define IMR_TVODER ((1 << 14)) /* Tx AC_VO Descriptor Error Int */
#define IMR_TVODOK ((1 << 13)) /* Tx AC_VO Descriptor OK Interrupt */
#define IMR_FOVW ((1 << 12)) /* Rx FIFO Overflow Interrupt */
#define IMR_RDU ((1 << 11)) /* Rx Descriptor Unavailable */
#define IMR_TVIDER ((1 << 10)) /* Tx AC_VI Descriptor Error */
#define IMR_TVIDOK ((1 << 9)) /* Tx AC_VI Descriptor OK Interrupt */
#define IMR_RER ((1 << 8)) /* Rx Error Interrupt */
#define IMR_ROK ((1 << 7)) /* Receive OK Interrupt */
#define IMR_TBEDER ((1 << 6)) /* Tx AC_BE Descriptor Error */
#define IMR_TBEDOK ((1 << 5)) /* Tx AC_BE Descriptor OK */
#define IMR_TBKDER ((1 << 4)) /* Tx AC_BK Descriptor Error */
#define IMR_TBKDOK ((1 << 3)) /* Tx AC_BK Descriptor OK */
#define IMR_RQOSOK ((1 << 2)) /* Rx QoS OK Interrupt */
#define IMR_TIMEOUT2 ((1 << 1)) /* Time Out Interrupt 2 */
#define IMR_TIMEOUT3 ((1 << 0)) /* Time Out Interrupt 3 */
__le16 BEACON_INTERVAL; /* 0x70 */
__le16 ATIM_WND; /* 0x72 */
__le16 BEACON_INTERVAL_TIME; /* 0x74 */
__le16 ATIMTR_INTERVAL; /* 0x76 */
u8 PHY_DELAY; /* 0x78 */
u8 CARRIER_SENSE_COUNTER; /* 0x79 */
u8 reserved_11[2]; /* 0x7a */
u8 PHY[4]; /* 0x7c */
__le16 RFPinsOutput; /* 0x80 */
__le16 RFPinsEnable; /* 0x82 */
__le16 RFPinsSelect; /* 0x84 */
__le16 RFPinsInput; /* 0x86 */
__le32 RF_PARA; /* 0x88 */
__le32 RF_TIMING; /* 0x8c */
u8 GP_ENABLE; /* 0x90 */
u8 GPIO0; /* 0x91 */
u8 GPIO1; /* 0x92 */
u8 TPPOLL_STOP; /* 0x93 - rtl8187se only */
#define RTL818x_TPPOLL_STOP_BQ (1 << 7)
#define RTL818x_TPPOLL_STOP_VI (1 << 4)
#define RTL818x_TPPOLL_STOP_VO (1 << 5)
#define RTL818x_TPPOLL_STOP_BE (1 << 3)
#define RTL818x_TPPOLL_STOP_BK (1 << 2)
#define RTL818x_TPPOLL_STOP_MG (1 << 1)
#define RTL818x_TPPOLL_STOP_HI (1 << 6)
__le32 HSSI_PARA; /* 0x94 */
u8 reserved_13[4]; /* 0x98 */
u8 TX_AGC_CTL; /* 0x9c */
#define RTL818X_TX_AGC_CTL_PERPACKET_GAIN (1 << 0)
#define RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL (1 << 1)
#define RTL818X_TX_AGC_CTL_FEEDBACK_ANT (1 << 2)
u8 TX_GAIN_CCK;
u8 TX_GAIN_OFDM;
u8 TX_ANTENNA;
u8 reserved_14[16];
u8 WPA_CONF;
u8 reserved_15[3];
u8 SIFS;
u8 DIFS;
u8 SLOT;
u8 reserved_16[5];
u8 CW_CONF;
#define RTL818X_CW_CONF_PERPACKET_CW (1 << 0)
#define RTL818X_CW_CONF_PERPACKET_RETRY (1 << 1)
u8 CW_VAL;
u8 RATE_FALLBACK;
#define RTL818X_RATE_FALLBACK_ENABLE (1 << 7)
u8 ACM_CONTROL;
u8 reserved_17[24];
u8 CONFIG5;
u8 TX_DMA_POLLING;
u8 PHY_PR;
u8 reserved_18;
__le16 CWR;
u8 RETRY_CTR;
u8 reserved_19[3];
__le16 INT_MIG;
/* RTL818X_R8187B_*: magic numbers from ioregisters */
#define RTL818X_R8187B_B 0
#define RTL818X_R8187B_D 1
#define RTL818X_R8187B_E 2
__le32 RDSAR;
__le16 TID_AC_MAP;
u8 reserved_20[4];
union {
__le16 ANAPARAM3; /* 0xee */
u8 ANAPARAM3A; /* for rtl8187 */
};
#define AC_PARAM_TXOP_LIMIT_SHIFT 16
#define AC_PARAM_ECW_MAX_SHIFT 12
#define AC_PARAM_ECW_MIN_SHIFT 8
#define AC_PARAM_AIFS_SHIFT 0
__le32 AC_VO_PARAM; /* 0xf0 */
union { /* 0xf4 */
__le32 AC_VI_PARAM;
__le16 FEMR;
} __packed;
union{ /* 0xf8 */
__le32 AC_BE_PARAM; /* rtl8187se */
struct{
u8 reserved_21[2];
__le16 TALLY_CNT; /* 0xfa */
} __packed;
} __packed;
union {
u8 TALLY_SEL; /* 0xfc */
__le32 AC_BK_PARAM;
} __packed;
} __packed;
/* These are addresses with NON-standard usage.
* They have offsets very far from this struct.
* I don't like to introduce a ton of "reserved"..
* They are for RTL8187SE
*/
#define REG_ADDR1(addr) ((u8 __iomem *)priv->map + (addr))
#define REG_ADDR2(addr) ((__le16 __iomem *)priv->map + ((addr) >> 1))
#define REG_ADDR4(addr) ((__le32 __iomem *)priv->map + ((addr) >> 2))
#define FEMR_SE REG_ADDR2(0x1D4)
#define ARFR REG_ADDR2(0x1E0)
#define RFSW_CTRL REG_ADDR2(0x272)
#define SW_3W_DB0 REG_ADDR2(0x274)
#define SW_3W_DB0_4 REG_ADDR4(0x274)
#define SW_3W_DB1 REG_ADDR2(0x278)
#define SW_3W_DB1_4 REG_ADDR4(0x278)
#define SW_3W_CMD1 REG_ADDR1(0x27D)
#define PI_DATA_REG REG_ADDR2(0x360)
#define SI_DATA_REG REG_ADDR2(0x362)
struct rtl818x_rf_ops {
char *name;
void (*init)(struct ieee80211_hw *);
void (*stop)(struct ieee80211_hw *);
void (*set_chan)(struct ieee80211_hw *, struct ieee80211_conf *);
u8 (*calc_rssi)(u8 agc, u8 sq);
};
/**
* enum rtl818x_tx_desc_flags - Tx/Rx flags are common between RTL818X chips
*
* @RTL818X_TX_DESC_FLAG_NO_ENC: Disable hardware based encryption.
* @RTL818X_TX_DESC_FLAG_TX_OK: TX frame was ACKed.
* @RTL818X_TX_DESC_FLAG_SPLCP: Use short preamble.
* @RTL818X_TX_DESC_FLAG_MOREFRAG: More fragments follow.
* @RTL818X_TX_DESC_FLAG_CTS: Use CTS-to-self protection.
* @RTL818X_TX_DESC_FLAG_RTS: Use RTS/CTS protection.
* @RTL818X_TX_DESC_FLAG_LS: Last segment of the frame.
* @RTL818X_TX_DESC_FLAG_FS: First segment of the frame.
*/
enum rtl818x_tx_desc_flags {
RTL818X_TX_DESC_FLAG_NO_ENC = (1 << 15),
RTL818X_TX_DESC_FLAG_TX_OK = (1 << 15),
RTL818X_TX_DESC_FLAG_SPLCP = (1 << 16),
RTL818X_TX_DESC_FLAG_RX_UNDER = (1 << 16),
RTL818X_TX_DESC_FLAG_MOREFRAG = (1 << 17),
RTL818X_TX_DESC_FLAG_CTS = (1 << 18),
RTL818X_TX_DESC_FLAG_RTS = (1 << 23),
RTL818X_TX_DESC_FLAG_LS = (1 << 28),
RTL818X_TX_DESC_FLAG_FS = (1 << 29),
RTL818X_TX_DESC_FLAG_DMA = (1 << 30),
RTL818X_TX_DESC_FLAG_OWN = (1 << 31)
};
enum rtl818x_rx_desc_flags {
RTL818X_RX_DESC_FLAG_ICV_ERR = (1 << 12),
RTL818X_RX_DESC_FLAG_CRC32_ERR = (1 << 13),
RTL818X_RX_DESC_FLAG_PM = (1 << 14),
RTL818X_RX_DESC_FLAG_RX_ERR = (1 << 15),
RTL818X_RX_DESC_FLAG_BCAST = (1 << 16),
RTL818X_RX_DESC_FLAG_PAM = (1 << 17),
RTL818X_RX_DESC_FLAG_MCAST = (1 << 18),
RTL818X_RX_DESC_FLAG_QOS = (1 << 19), /* RTL8187(B) only */
RTL818X_RX_DESC_FLAG_TRSW = (1 << 24), /* RTL8187(B) only */
RTL818X_RX_DESC_FLAG_SPLCP = (1 << 25),
RTL818X_RX_DESC_FLAG_FOF = (1 << 26),
RTL818X_RX_DESC_FLAG_DMA_FAIL = (1 << 27),
RTL818X_RX_DESC_FLAG_LS = (1 << 28),
RTL818X_RX_DESC_FLAG_FS = (1 << 29),
RTL818X_RX_DESC_FLAG_EOR = (1 << 30),
RTL818X_RX_DESC_FLAG_OWN = (1 << 31)
};
#endif /* RTL818X_H */