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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 17:32:46 -04:00
Fixed MTP to work with TWRP
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commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
58
drivers/net/wireless/rtlwifi/rtl8192ce/table.h
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58
drivers/net/wireless/rtlwifi/rtl8192ce/table.h
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/******************************************************************************
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*
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* Copyright(c) 2009-2012 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Created on 2010/ 5/18, 1:41
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __RTL92CE_TABLE__H_
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#define __RTL92CE_TABLE__H_
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#include <linux/types.h>
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#define PHY_REG_2TARRAY_LENGTH 374
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extern u32 RTL8192CEPHY_REG_2TARRAY[PHY_REG_2TARRAY_LENGTH];
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#define PHY_REG_1TARRAY_LENGTH 374
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extern u32 RTL8192CEPHY_REG_1TARRAY[PHY_REG_1TARRAY_LENGTH];
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#define PHY_REG_ARRAY_PGLENGTH 192
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extern u32 RTL8192CEPHY_REG_ARRAY_PG[PHY_REG_ARRAY_PGLENGTH];
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#define RADIOA_2TARRAYLENGTH 282
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extern u32 RTL8192CERADIOA_2TARRAY[RADIOA_2TARRAYLENGTH];
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#define RADIOB_2TARRAYLENGTH 78
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extern u32 RTL8192CE_RADIOB_2TARRAY[RADIOB_2TARRAYLENGTH];
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#define RADIOA_1TARRAYLENGTH 282
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extern u32 RTL8192CE_RADIOA_1TARRAY[RADIOA_1TARRAYLENGTH];
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#define RADIOB_1TARRAYLENGTH 1
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extern u32 RTL8192CE_RADIOB_1TARRAY[RADIOB_1TARRAYLENGTH];
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#define MAC_2T_ARRAYLENGTH 162
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extern u32 RTL8192CEMAC_2T_ARRAY[MAC_2T_ARRAYLENGTH];
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#define AGCTAB_2TARRAYLENGTH 320
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extern u32 RTL8192CEAGCTAB_2TARRAY[AGCTAB_2TARRAYLENGTH];
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#define AGCTAB_1TARRAYLENGTH 320
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extern u32 RTL8192CEAGCTAB_1TARRAY[AGCTAB_1TARRAYLENGTH];
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#endif
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