mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 08:08:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
419
drivers/net/wireless/rtlwifi/rtl8192de/sw.c
Normal file
419
drivers/net/wireless/rtlwifi/rtl8192de/sw.c
Normal file
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@ -0,0 +1,419 @@
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/******************************************************************************
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*
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* Copyright(c) 2009-2012 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
|
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* published by the Free Software Foundation.
|
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
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* more details.
|
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*
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||||
* You should have received a copy of the GNU General Public License along with
|
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* this program; if not, write to the Free Software Foundation, Inc.,
|
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#include "../wifi.h"
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#include "../core.h"
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#include "../pci.h"
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#include "../base.h"
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#include "reg.h"
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#include "def.h"
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#include "phy.h"
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#include "dm.h"
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#include "hw.h"
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#include "sw.h"
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#include "trx.h"
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#include "led.h"
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#include <linux/module.h>
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static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw)
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{
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struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
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/*close ASPM for AMD defaultly */
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rtlpci->const_amdpci_aspm = 0;
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/*
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* ASPM PS mode.
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* 0 - Disable ASPM,
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* 1 - Enable ASPM without Clock Req,
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* 2 - Enable ASPM with Clock Req,
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* 3 - Alwyas Enable ASPM with Clock Req,
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* 4 - Always Enable ASPM without Clock Req.
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* set defult to RTL8192CE:3 RTL8192E:2
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* */
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rtlpci->const_pci_aspm = 3;
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/*Setting for PCI-E device */
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rtlpci->const_devicepci_aspm_setting = 0x03;
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/*Setting for PCI-E bridge */
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rtlpci->const_hostpci_aspm_setting = 0x02;
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/*
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* In Hw/Sw Radio Off situation.
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* 0 - Default,
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* 1 - From ASPM setting without low Mac Pwr,
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* 2 - From ASPM setting with low Mac Pwr,
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* 3 - Bus D3
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* set default to RTL8192CE:0 RTL8192SE:2
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*/
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rtlpci->const_hwsw_rfoff_d3 = 0;
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/*
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* This setting works for those device with
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* backdoor ASPM setting such as EPHY setting.
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* 0 - Not support ASPM,
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* 1 - Support ASPM,
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* 2 - According to chipset.
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*/
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rtlpci->const_support_pciaspm = 1;
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}
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static int rtl92d_init_sw_vars(struct ieee80211_hw *hw)
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{
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int err;
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u8 tid;
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
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rtlpriv->dm.dm_initialgain_enable = true;
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rtlpriv->dm.dm_flag = 0;
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rtlpriv->dm.disable_framebursting = false;
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rtlpriv->dm.thermalvalue = 0;
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rtlpriv->dm.useramask = true;
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/* dual mac */
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if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
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rtlpriv->phy.current_channel = 36;
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else
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rtlpriv->phy.current_channel = 1;
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if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
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rtlpriv->rtlhal.disable_amsdu_8k = true;
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/* No long RX - reduce fragmentation */
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rtlpci->rxbuffersize = 4096;
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}
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rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
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rtlpci->receive_config = (
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RCR_APPFCS
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| RCR_AMF
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| RCR_ADF
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| RCR_APP_MIC
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| RCR_APP_ICV
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| RCR_AICV
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| RCR_ACRC32
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| RCR_AB
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| RCR_AM
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| RCR_APM
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| RCR_APP_PHYST_RXFF
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| RCR_HTC_LOC_CTRL
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);
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rtlpci->irq_mask[0] = (u32) (
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IMR_ROK
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| IMR_VODOK
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| IMR_VIDOK
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| IMR_BEDOK
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| IMR_BKDOK
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| IMR_MGNTDOK
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| IMR_HIGHDOK
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| IMR_BDOK
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| IMR_RDU
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| IMR_RXFOVW
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);
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rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD);
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/* for debug level */
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rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
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/* for LPS & IPS */
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rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
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rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
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rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
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if (!rtlpriv->psc.inactiveps)
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pr_info("Power Save off (module option)\n");
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if (!rtlpriv->psc.fwctrl_lps)
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pr_info("FW Power Save off (module option)\n");
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rtlpriv->psc.reg_fwctrl_lps = 3;
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rtlpriv->psc.reg_max_lps_awakeintvl = 5;
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/* for ASPM, you can close aspm through
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* set const_support_pciaspm = 0 */
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rtl92d_init_aspm_vars(hw);
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if (rtlpriv->psc.reg_fwctrl_lps == 1)
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rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
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else if (rtlpriv->psc.reg_fwctrl_lps == 2)
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rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
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else if (rtlpriv->psc.reg_fwctrl_lps == 3)
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rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
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/* for early mode */
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rtlpriv->rtlhal.earlymode_enable = false;
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for (tid = 0; tid < 8; tid++)
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skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
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/* for firmware buf */
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rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
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if (!rtlpriv->rtlhal.pfirmware) {
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RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
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"Can't alloc buffer for fw\n");
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return 1;
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}
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rtlpriv->max_fw_size = 0x8000;
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pr_info("Driver for Realtek RTL8192DE WLAN interface\n");
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pr_info("Loading firmware file %s\n", rtlpriv->cfg->fw_name);
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/* request fw */
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err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
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rtlpriv->io.dev, GFP_KERNEL, hw,
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rtl_fw_cb);
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if (err) {
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RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
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"Failed to request firmware!\n");
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return 1;
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}
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return 0;
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}
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static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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u8 tid;
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if (rtlpriv->rtlhal.pfirmware) {
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vfree(rtlpriv->rtlhal.pfirmware);
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rtlpriv->rtlhal.pfirmware = NULL;
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}
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for (tid = 0; tid < 8; tid++)
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skb_queue_purge(&rtlpriv->mac80211.skb_waitq[tid]);
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}
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static struct rtl_hal_ops rtl8192de_hal_ops = {
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.init_sw_vars = rtl92d_init_sw_vars,
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.deinit_sw_vars = rtl92d_deinit_sw_vars,
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.read_eeprom_info = rtl92de_read_eeprom_info,
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.interrupt_recognized = rtl92de_interrupt_recognized,
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.hw_init = rtl92de_hw_init,
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.hw_disable = rtl92de_card_disable,
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.hw_suspend = rtl92de_suspend,
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.hw_resume = rtl92de_resume,
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.enable_interrupt = rtl92de_enable_interrupt,
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.disable_interrupt = rtl92de_disable_interrupt,
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.set_network_type = rtl92de_set_network_type,
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.set_chk_bssid = rtl92de_set_check_bssid,
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.set_qos = rtl92de_set_qos,
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.set_bcn_reg = rtl92de_set_beacon_related_registers,
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.set_bcn_intv = rtl92de_set_beacon_interval,
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.update_interrupt_mask = rtl92de_update_interrupt_mask,
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.get_hw_reg = rtl92de_get_hw_reg,
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.set_hw_reg = rtl92de_set_hw_reg,
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.update_rate_tbl = rtl92de_update_hal_rate_tbl,
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.fill_tx_desc = rtl92de_tx_fill_desc,
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.fill_tx_cmddesc = rtl92de_tx_fill_cmddesc,
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.query_rx_desc = rtl92de_rx_query_desc,
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.set_channel_access = rtl92de_update_channel_access_setting,
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.radio_onoff_checking = rtl92de_gpio_radio_on_off_checking,
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.set_bw_mode = rtl92d_phy_set_bw_mode,
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.switch_channel = rtl92d_phy_sw_chnl,
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.dm_watchdog = rtl92d_dm_watchdog,
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.scan_operation_backup = rtl_phy_scan_operation_backup,
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.set_rf_power_state = rtl92d_phy_set_rf_power_state,
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.led_control = rtl92de_led_control,
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.set_desc = rtl92de_set_desc,
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.get_desc = rtl92de_get_desc,
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.tx_polling = rtl92de_tx_polling,
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.enable_hw_sec = rtl92de_enable_hw_security_config,
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.set_key = rtl92de_set_key,
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.init_sw_leds = rtl92de_init_sw_leds,
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.get_bbreg = rtl92d_phy_query_bb_reg,
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.set_bbreg = rtl92d_phy_set_bb_reg,
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.get_rfreg = rtl92d_phy_query_rf_reg,
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.set_rfreg = rtl92d_phy_set_rf_reg,
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.linked_set_reg = rtl92d_linked_set_reg,
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.get_btc_status = rtl_btc_status_false,
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};
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static struct rtl_mod_params rtl92de_mod_params = {
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.sw_crypto = false,
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.inactiveps = true,
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.swctrl_lps = true,
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.fwctrl_lps = false,
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.debug = DBG_EMERG,
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};
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static struct rtl_hal_cfg rtl92de_hal_cfg = {
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.bar_id = 2,
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.write_readback = true,
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.name = "rtl8192de",
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.fw_name = "rtlwifi/rtl8192defw.bin",
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.ops = &rtl8192de_hal_ops,
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.mod_params = &rtl92de_mod_params,
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.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
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.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
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.maps[SYS_CLK] = REG_SYS_CLKR,
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.maps[MAC_RCR_AM] = RCR_AM,
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.maps[MAC_RCR_AB] = RCR_AB,
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.maps[MAC_RCR_ACRC32] = RCR_ACRC32,
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.maps[MAC_RCR_ACF] = RCR_ACF,
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.maps[MAC_RCR_AAP] = RCR_AAP,
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.maps[EFUSE_TEST] = REG_EFUSE_TEST,
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.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
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.maps[EFUSE_CLK] = 0, /* just for 92se */
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.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
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.maps[EFUSE_PWC_EV12V] = PWC_EV12V,
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.maps[EFUSE_FEN_ELDR] = FEN_ELDR,
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.maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
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.maps[EFUSE_ANA8M] = 0, /* just for 92se */
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.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
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.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
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.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
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.maps[RWCAM] = REG_CAMCMD,
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.maps[WCAMI] = REG_CAMWRITE,
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.maps[RCAMO] = REG_CAMREAD,
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.maps[CAMDBG] = REG_CAMDBG,
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.maps[SECR] = REG_SECCFG,
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.maps[SEC_CAM_NONE] = CAM_NONE,
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.maps[SEC_CAM_WEP40] = CAM_WEP40,
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.maps[SEC_CAM_TKIP] = CAM_TKIP,
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.maps[SEC_CAM_AES] = CAM_AES,
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.maps[SEC_CAM_WEP104] = CAM_WEP104,
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.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
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.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
|
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.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
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.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
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.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
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.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
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.maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
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.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
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.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
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.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
|
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.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
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.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
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.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
|
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.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
|
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.maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
|
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.maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
|
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|
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.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
|
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.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
|
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.maps[RTL_IMR_BCNINT] = IMR_BCNINT,
|
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.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
|
||||
.maps[RTL_IMR_RDU] = IMR_RDU,
|
||||
.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
|
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.maps[RTL_IMR_BDOK] = IMR_BDOK,
|
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.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
|
||||
.maps[RTL_IMR_TBDER] = IMR_TBDER,
|
||||
.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
|
||||
.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
|
||||
.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
|
||||
.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
|
||||
.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
|
||||
.maps[RTL_IMR_VODOK] = IMR_VODOK,
|
||||
.maps[RTL_IMR_ROK] = IMR_ROK,
|
||||
.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
|
||||
|
||||
.maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M,
|
||||
.maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M,
|
||||
.maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M,
|
||||
.maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M,
|
||||
.maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M,
|
||||
.maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M,
|
||||
.maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M,
|
||||
.maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M,
|
||||
.maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M,
|
||||
.maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M,
|
||||
.maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M,
|
||||
.maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M,
|
||||
|
||||
.maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7,
|
||||
.maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15,
|
||||
};
|
||||
|
||||
static struct pci_device_id rtl92de_pci_ids[] = {
|
||||
{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8193, rtl92de_hal_cfg)},
|
||||
{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x002B, rtl92de_hal_cfg)},
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(pci, rtl92de_pci_ids);
|
||||
|
||||
MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
|
||||
MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
|
||||
MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("Realtek 8192DE 802.11n Dual Mac PCI wireless");
|
||||
MODULE_FIRMWARE("rtlwifi/rtl8192defw.bin");
|
||||
|
||||
module_param_named(swenc, rtl92de_mod_params.sw_crypto, bool, 0444);
|
||||
module_param_named(debug, rtl92de_mod_params.debug, int, 0444);
|
||||
module_param_named(ips, rtl92de_mod_params.inactiveps, bool, 0444);
|
||||
module_param_named(swlps, rtl92de_mod_params.swctrl_lps, bool, 0444);
|
||||
module_param_named(fwlps, rtl92de_mod_params.fwctrl_lps, bool, 0444);
|
||||
MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
|
||||
MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
|
||||
MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
|
||||
MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
|
||||
MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
|
||||
|
||||
static struct pci_driver rtl92de_driver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.id_table = rtl92de_pci_ids,
|
||||
.probe = rtl_pci_probe,
|
||||
.remove = rtl_pci_disconnect,
|
||||
.driver.pm = &rtlwifi_pm_ops,
|
||||
};
|
||||
|
||||
/* add global spin lock to solve the problem that
|
||||
* Dul mac register operation on the same time */
|
||||
spinlock_t globalmutex_power;
|
||||
spinlock_t globalmutex_for_fwdownload;
|
||||
spinlock_t globalmutex_for_power_and_efuse;
|
||||
|
||||
static int __init rtl92de_module_init(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
spin_lock_init(&globalmutex_power);
|
||||
spin_lock_init(&globalmutex_for_fwdownload);
|
||||
spin_lock_init(&globalmutex_for_power_and_efuse);
|
||||
|
||||
ret = pci_register_driver(&rtl92de_driver);
|
||||
if (ret)
|
||||
RT_ASSERT(false, "No device found\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit rtl92de_module_exit(void)
|
||||
{
|
||||
pci_unregister_driver(&rtl92de_driver);
|
||||
}
|
||||
|
||||
module_init(rtl92de_module_init);
|
||||
module_exit(rtl92de_module_exit);
|
||||
Loading…
Add table
Add a link
Reference in a new issue