mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 09:22:44 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
19
drivers/net/wireless/rtlwifi/rtl8821ae/Makefile
Normal file
19
drivers/net/wireless/rtlwifi/rtl8821ae/Makefile
Normal file
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@ -0,0 +1,19 @@
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obj-m := rtl8821ae.o
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rtl8821ae-objs := \
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dm.o \
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fw.o \
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hw.o \
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led.o \
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phy.o \
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pwrseq.o \
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rf.o \
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sw.o \
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table.o \
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trx.o \
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obj-$(CONFIG_RTL8821AE) += rtl8821ae.o
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ccflags-y += -D__CHECK_ENDIAN__
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450
drivers/net/wireless/rtlwifi/rtl8821ae/def.h
Normal file
450
drivers/net/wireless/rtlwifi/rtl8821ae/def.h
Normal file
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@ -0,0 +1,450 @@
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/******************************************************************************
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*
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* Copyright(c) 2009-2010 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
|
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
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* more details.
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||||
*
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* The full GNU General Public License is included in this distribution in the
|
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __RTL8821AE_DEF_H__
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#define __RTL8821AE_DEF_H__
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/*--------------------------Define -------------------------------------------*/
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#define USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN 1
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/* BIT 7 HT Rate*/
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/*TxHT = 0*/
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#define MGN_1M 0x02
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#define MGN_2M 0x04
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#define MGN_5_5M 0x0b
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#define MGN_11M 0x16
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#define MGN_6M 0x0c
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#define MGN_9M 0x12
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#define MGN_12M 0x18
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#define MGN_18M 0x24
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#define MGN_24M 0x30
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#define MGN_36M 0x48
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#define MGN_48M 0x60
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#define MGN_54M 0x6c
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/* TxHT = 1 */
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#define MGN_MCS0 0x80
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#define MGN_MCS1 0x81
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#define MGN_MCS2 0x82
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#define MGN_MCS3 0x83
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#define MGN_MCS4 0x84
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#define MGN_MCS5 0x85
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#define MGN_MCS6 0x86
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#define MGN_MCS7 0x87
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#define MGN_MCS8 0x88
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#define MGN_MCS9 0x89
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#define MGN_MCS10 0x8a
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#define MGN_MCS11 0x8b
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#define MGN_MCS12 0x8c
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#define MGN_MCS13 0x8d
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#define MGN_MCS14 0x8e
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#define MGN_MCS15 0x8f
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/* VHT rate */
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#define MGN_VHT1SS_MCS0 0x90
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#define MGN_VHT1SS_MCS1 0x91
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#define MGN_VHT1SS_MCS2 0x92
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#define MGN_VHT1SS_MCS3 0x93
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#define MGN_VHT1SS_MCS4 0x94
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#define MGN_VHT1SS_MCS5 0x95
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#define MGN_VHT1SS_MCS6 0x96
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#define MGN_VHT1SS_MCS7 0x97
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#define MGN_VHT1SS_MCS8 0x98
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#define MGN_VHT1SS_MCS9 0x99
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#define MGN_VHT2SS_MCS0 0x9a
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#define MGN_VHT2SS_MCS1 0x9b
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#define MGN_VHT2SS_MCS2 0x9c
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#define MGN_VHT2SS_MCS3 0x9d
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#define MGN_VHT2SS_MCS4 0x9e
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#define MGN_VHT2SS_MCS5 0x9f
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#define MGN_VHT2SS_MCS6 0xa0
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#define MGN_VHT2SS_MCS7 0xa1
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#define MGN_VHT2SS_MCS8 0xa2
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#define MGN_VHT2SS_MCS9 0xa3
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#define MGN_VHT3SS_MCS0 0xa4
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#define MGN_VHT3SS_MCS1 0xa5
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#define MGN_VHT3SS_MCS2 0xa6
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#define MGN_VHT3SS_MCS3 0xa7
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#define MGN_VHT3SS_MCS4 0xa8
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#define MGN_VHT3SS_MCS5 0xa9
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#define MGN_VHT3SS_MCS6 0xaa
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#define MGN_VHT3SS_MCS7 0xab
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#define MGN_VHT3SS_MCS8 0xac
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#define MGN_VHT3SS_MCS9 0xad
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#define MGN_MCS0_SG 0xc0
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#define MGN_MCS1_SG 0xc1
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#define MGN_MCS2_SG 0xc2
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#define MGN_MCS3_SG 0xc3
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#define MGN_MCS4_SG 0xc4
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#define MGN_MCS5_SG 0xc5
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#define MGN_MCS6_SG 0xc6
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#define MGN_MCS7_SG 0xc7
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#define MGN_MCS8_SG 0xc8
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#define MGN_MCS9_SG 0xc9
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#define MGN_MCS10_SG 0xca
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#define MGN_MCS11_SG 0xcb
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#define MGN_MCS12_SG 0xcc
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#define MGN_MCS13_SG 0xcd
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#define MGN_MCS14_SG 0xce
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#define MGN_MCS15_SG 0xcf
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#define MGN_UNKNOWN 0xff
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/* 30 ms */
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#define WIFI_NAV_UPPER_US 30000
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#define HAL_92C_NAV_UPPER_UNIT 128
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#define HAL_RETRY_LIMIT_INFRA 48
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#define HAL_RETRY_LIMIT_AP_ADHOC 7
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#define RESET_DELAY_8185 20
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#define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
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#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
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#define NUM_OF_FIRMWARE_QUEUE 10
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#define NUM_OF_PAGES_IN_FW 0x100
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#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
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#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
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#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
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#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
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#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
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#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
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#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
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#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
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#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
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#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
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#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
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#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
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#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
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#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
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#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
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#define MAX_RX_DMA_BUFFER_SIZE 0x3E80
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#define MAX_LINES_HWCONFIG_TXT 1000
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#define MAX_BYTES_LINE_HWCONFIG_TXT 256
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#define SW_THREE_WIRE 0
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#define HW_THREE_WIRE 2
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#define BT_DEMO_BOARD 0
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#define BT_QA_BOARD 1
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#define BT_FPGA 2
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#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
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#define HAL_PRIME_CHNL_OFFSET_LOWER 1
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#define HAL_PRIME_CHNL_OFFSET_UPPER 2
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#define MAX_H2C_QUEUE_NUM 10
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#define RX_MPDU_QUEUE 0
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#define RX_CMD_QUEUE 1
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#define RX_MAX_QUEUE 2
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#define AC2QUEUEID(_AC) (_AC)
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#define MAX_RX_DMA_BUFFER_SIZE_8812 0x3E80
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#define C2H_RX_CMD_HDR_LEN 8
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#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
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LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
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#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
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LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
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#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
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LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
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#define GET_C2H_CMD_CONTINUE(__prxhdr) \
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LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
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#define GET_C2H_CMD_CONTENT(__prxhdr) \
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((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
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#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
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#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
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#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
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#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
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#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
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#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
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#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
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#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
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#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
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#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
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#define CHIP_8812 BIT(2)
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#define CHIP_8821 (BIT(0)|BIT(2))
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#define CHIP_8821A (BIT(0)|BIT(2))
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#define NORMAL_CHIP BIT(3)
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#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
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#define RF_TYPE_1T2R BIT(4)
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#define RF_TYPE_2T2R BIT(5)
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#define CHIP_VENDOR_UMC BIT(7)
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#define B_CUT_VERSION BIT(12)
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#define C_CUT_VERSION BIT(13)
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#define D_CUT_VERSION ((BIT(12)|BIT(13)))
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#define E_CUT_VERSION BIT(14)
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#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28))
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enum version_8821ae {
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VERSION_TEST_CHIP_1T1R_8812 = 0x0004,
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VERSION_TEST_CHIP_2T2R_8812 = 0x0024,
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VERSION_NORMAL_TSMC_CHIP_1T1R_8812 = 0x100c,
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VERSION_NORMAL_TSMC_CHIP_2T2R_8812 = 0x102c,
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VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT = 0x200c,
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VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT = 0x202c,
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VERSION_TEST_CHIP_8821 = 0x0005,
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VERSION_NORMAL_TSMC_CHIP_8821 = 0x000d,
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VERSION_NORMAL_TSMC_CHIP_8821_B_CUT = 0x100d,
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VERSION_UNKNOWN = 0xFF,
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};
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enum vht_data_sc {
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VHT_DATA_SC_DONOT_CARE = 0,
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VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
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VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
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VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
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VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
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VHT_DATA_SC_20_RECV1 = 5,
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VHT_DATA_SC_20_RECV2 = 6,
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VHT_DATA_SC_20_RECV3 = 7,
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VHT_DATA_SC_20_RECV4 = 8,
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VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
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VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
|
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};
|
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|
||||
/* MASK */
|
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#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
|
||||
#define CHIP_TYPE_MASK BIT(3)
|
||||
#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
|
||||
#define MANUFACTUER_MASK BIT(7)
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||||
#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
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||||
#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
|
||||
|
||||
/* Get element */
|
||||
#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
|
||||
#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
|
||||
#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
|
||||
#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
|
||||
#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
|
||||
#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
|
||||
|
||||
#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version)) ? false : true)
|
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#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
|
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? true : false)
|
||||
#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
|
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? true : false)
|
||||
|
||||
#define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812) ? \
|
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true : false)
|
||||
#define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821) ? \
|
||||
true : false)
|
||||
|
||||
#define IS_VENDOR_8812A_TEST_CHIP(version) ((IS_8812_SERIES(version)) ? \
|
||||
((IS_NORMAL_CHIP(version)) ? \
|
||||
false : true) : false)
|
||||
#define IS_VENDOR_8812A_MP_CHIP(version) ((IS_8812_SERIES(version)) ? \
|
||||
((IS_NORMAL_CHIP(version)) ? \
|
||||
true : false) : false)
|
||||
#define IS_VENDOR_8812A_C_CUT(version) ((IS_8812_SERIES(version)) ? \
|
||||
((GET_CVID_CUT_VERSION(version) == \
|
||||
C_CUT_VERSION) ? \
|
||||
true : false) : false)
|
||||
|
||||
#define IS_VENDOR_8821A_TEST_CHIP(version) ((IS_8821_SERIES(version)) ? \
|
||||
((IS_NORMAL_CHIP(version)) ? \
|
||||
false : true) : false)
|
||||
#define IS_VENDOR_8821A_MP_CHIP(version) ((IS_8821_SERIES(version)) ? \
|
||||
((IS_NORMAL_CHIP(version)) ? \
|
||||
true : false) : false)
|
||||
#define IS_VENDOR_8821A_B_CUT(version) ((IS_8821_SERIES(version)) ? \
|
||||
((GET_CVID_CUT_VERSION(version) == \
|
||||
B_CUT_VERSION) ? \
|
||||
true : false) : false)
|
||||
enum board_type {
|
||||
ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */
|
||||
ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1 = mini card. */
|
||||
ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */
|
||||
ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */
|
||||
ODM_BOARD_EXT_PA = BIT(3), /* 1 = existing 2G ext-PA */
|
||||
ODM_BOARD_EXT_LNA = BIT(4), /* 1 = existing 2G ext-LNA */
|
||||
ODM_BOARD_EXT_TRSW = BIT(5), /* 1 = existing ext-TRSW */
|
||||
ODM_BOARD_EXT_PA_5G = BIT(6), /* 1 = existing 5G ext-PA */
|
||||
ODM_BOARD_EXT_LNA_5G = BIT(7), /* 1 = existing 5G ext-LNA */
|
||||
};
|
||||
|
||||
enum rf_optype {
|
||||
RF_OP_BY_SW_3WIRE = 0,
|
||||
RF_OP_BY_FW,
|
||||
RF_OP_MAX
|
||||
};
|
||||
|
||||
enum rf_power_state {
|
||||
RF_ON,
|
||||
RF_OFF,
|
||||
RF_SLEEP,
|
||||
RF_SHUT_DOWN,
|
||||
};
|
||||
|
||||
enum power_save_mode {
|
||||
POWER_SAVE_MODE_ACTIVE,
|
||||
POWER_SAVE_MODE_SAVE,
|
||||
};
|
||||
|
||||
enum power_polocy_config {
|
||||
POWERCFG_MAX_POWER_SAVINGS,
|
||||
POWERCFG_GLOBAL_POWER_SAVINGS,
|
||||
POWERCFG_LOCAL_POWER_SAVINGS,
|
||||
POWERCFG_LENOVO,
|
||||
};
|
||||
|
||||
enum interface_select_pci {
|
||||
INTF_SEL1_MINICARD = 0,
|
||||
INTF_SEL0_PCIE = 1,
|
||||
INTF_SEL2_RSV = 2,
|
||||
INTF_SEL3_RSV = 3,
|
||||
};
|
||||
|
||||
enum hal_fw_c2h_cmd_id {
|
||||
HAL_FW_C2H_CMD_READ_MACREG = 0,
|
||||
HAL_FW_C2H_CMD_READ_BBREG = 1,
|
||||
HAL_FW_C2H_CMD_READ_RFREG = 2,
|
||||
HAL_FW_C2H_CMD_READ_EEPROM = 3,
|
||||
HAL_FW_C2H_CMD_READ_EFUSE = 4,
|
||||
HAL_FW_C2H_CMD_READ_CAM = 5,
|
||||
HAL_FW_C2H_CMD_GET_BASICRATE = 6,
|
||||
HAL_FW_C2H_CMD_GET_DATARATE = 7,
|
||||
HAL_FW_C2H_CMD_SURVEY = 8,
|
||||
HAL_FW_C2H_CMD_SURVEYDONE = 9,
|
||||
HAL_FW_C2H_CMD_JOINBSS = 10,
|
||||
HAL_FW_C2H_CMD_ADDSTA = 11,
|
||||
HAL_FW_C2H_CMD_DELSTA = 12,
|
||||
HAL_FW_C2H_CMD_ATIMDONE = 13,
|
||||
HAL_FW_C2H_CMD_TX_REPORT = 14,
|
||||
HAL_FW_C2H_CMD_CCX_REPORT = 15,
|
||||
HAL_FW_C2H_CMD_DTM_REPORT = 16,
|
||||
HAL_FW_C2H_CMD_TX_RATE_STATISTICS = 17,
|
||||
HAL_FW_C2H_CMD_C2HLBK = 18,
|
||||
HAL_FW_C2H_CMD_C2HDBG = 19,
|
||||
HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
|
||||
HAL_FW_C2H_CMD_MAX
|
||||
};
|
||||
|
||||
enum rtl_desc_qsel {
|
||||
QSLT_BK = 0x2,
|
||||
QSLT_BE = 0x0,
|
||||
QSLT_VI = 0x5,
|
||||
QSLT_VO = 0x7,
|
||||
QSLT_BEACON = 0x10,
|
||||
QSLT_HIGH = 0x11,
|
||||
QSLT_MGNT = 0x12,
|
||||
QSLT_CMD = 0x13,
|
||||
};
|
||||
|
||||
enum rtl_desc8821ae_rate {
|
||||
DESC_RATE1M = 0x00,
|
||||
DESC_RATE2M = 0x01,
|
||||
DESC_RATE5_5M = 0x02,
|
||||
DESC_RATE11M = 0x03,
|
||||
|
||||
DESC_RATE6M = 0x04,
|
||||
DESC_RATE9M = 0x05,
|
||||
DESC_RATE12M = 0x06,
|
||||
DESC_RATE18M = 0x07,
|
||||
DESC_RATE24M = 0x08,
|
||||
DESC_RATE36M = 0x09,
|
||||
DESC_RATE48M = 0x0a,
|
||||
DESC_RATE54M = 0x0b,
|
||||
|
||||
DESC_RATEMCS0 = 0x0c,
|
||||
DESC_RATEMCS1 = 0x0d,
|
||||
DESC_RATEMCS2 = 0x0e,
|
||||
DESC_RATEMCS3 = 0x0f,
|
||||
DESC_RATEMCS4 = 0x10,
|
||||
DESC_RATEMCS5 = 0x11,
|
||||
DESC_RATEMCS6 = 0x12,
|
||||
DESC_RATEMCS7 = 0x13,
|
||||
DESC_RATEMCS8 = 0x14,
|
||||
DESC_RATEMCS9 = 0x15,
|
||||
DESC_RATEMCS10 = 0x16,
|
||||
DESC_RATEMCS11 = 0x17,
|
||||
DESC_RATEMCS12 = 0x18,
|
||||
DESC_RATEMCS13 = 0x19,
|
||||
DESC_RATEMCS14 = 0x1a,
|
||||
DESC_RATEMCS15 = 0x1b,
|
||||
|
||||
DESC_RATEVHT1SS_MCS0 = 0x2c,
|
||||
DESC_RATEVHT1SS_MCS1 = 0x2d,
|
||||
DESC_RATEVHT1SS_MCS2 = 0x2e,
|
||||
DESC_RATEVHT1SS_MCS3 = 0x2f,
|
||||
DESC_RATEVHT1SS_MCS4 = 0x30,
|
||||
DESC_RATEVHT1SS_MCS5 = 0x31,
|
||||
DESC_RATEVHT1SS_MCS6 = 0x32,
|
||||
DESC_RATEVHT1SS_MCS7 = 0x33,
|
||||
DESC_RATEVHT1SS_MCS8 = 0x34,
|
||||
DESC_RATEVHT1SS_MCS9 = 0x35,
|
||||
DESC_RATEVHT2SS_MCS0 = 0x36,
|
||||
DESC_RATEVHT2SS_MCS1 = 0x37,
|
||||
DESC_RATEVHT2SS_MCS2 = 0x38,
|
||||
DESC_RATEVHT2SS_MCS3 = 0x39,
|
||||
DESC_RATEVHT2SS_MCS4 = 0x3a,
|
||||
DESC_RATEVHT2SS_MCS5 = 0x3b,
|
||||
DESC_RATEVHT2SS_MCS6 = 0x3c,
|
||||
DESC_RATEVHT2SS_MCS7 = 0x3d,
|
||||
DESC_RATEVHT2SS_MCS8 = 0x3e,
|
||||
DESC_RATEVHT2SS_MCS9 = 0x3f,
|
||||
};
|
||||
|
||||
enum rx_packet_type {
|
||||
NORMAL_RX,
|
||||
TX_REPORT1,
|
||||
TX_REPORT2,
|
||||
HIS_REPORT,
|
||||
C2H_PACKET,
|
||||
};
|
||||
|
||||
struct phy_sts_cck_8821ae_t {
|
||||
u8 adc_pwdb_X[4];
|
||||
u8 sq_rpt;
|
||||
u8 cck_agc_rpt;
|
||||
};
|
||||
|
||||
struct h2c_cmd_8821ae {
|
||||
u8 element_id;
|
||||
u32 cmd_len;
|
||||
u8 *p_cmdbuffer;
|
||||
};
|
||||
|
||||
#endif
|
||||
3019
drivers/net/wireless/rtlwifi/rtl8821ae/dm.c
Normal file
3019
drivers/net/wireless/rtlwifi/rtl8821ae/dm.c
Normal file
File diff suppressed because it is too large
Load diff
356
drivers/net/wireless/rtlwifi/rtl8821ae/dm.h
Normal file
356
drivers/net/wireless/rtlwifi/rtl8821ae/dm.h
Normal file
|
|
@ -0,0 +1,356 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2010 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL8821AE_DM_H__
|
||||
#define __RTL8821AE_DM_H__
|
||||
|
||||
#define MAIN_ANT 0
|
||||
#define AUX_ANT 1
|
||||
#define MAIN_ANT_CG_TRX 1
|
||||
#define AUX_ANT_CG_TRX 0
|
||||
#define MAIN_ANT_CGCS_RX 0
|
||||
#define AUX_ANT_CGCS_RX 1
|
||||
|
||||
#define TXSCALE_TABLE_SIZE 37
|
||||
|
||||
/*RF REG LIST*/
|
||||
#define DM_REG_RF_MODE_11N 0x00
|
||||
#define DM_REG_RF_0B_11N 0x0B
|
||||
#define DM_REG_CHNBW_11N 0x18
|
||||
#define DM_REG_T_METER_11N 0x24
|
||||
#define DM_REG_RF_25_11N 0x25
|
||||
#define DM_REG_RF_26_11N 0x26
|
||||
#define DM_REG_RF_27_11N 0x27
|
||||
#define DM_REG_RF_2B_11N 0x2B
|
||||
#define DM_REG_RF_2C_11N 0x2C
|
||||
#define DM_REG_RXRF_A3_11N 0x3C
|
||||
#define DM_REG_T_METER_92D_11N 0x42
|
||||
#define DM_REG_T_METER_88E_11N 0x42
|
||||
|
||||
/*BB REG LIST*/
|
||||
/*PAGE 8 */
|
||||
#define DM_REG_BB_CTRL_11N 0x800
|
||||
#define DM_REG_RF_PIN_11N 0x804
|
||||
#define DM_REG_PSD_CTRL_11N 0x808
|
||||
#define DM_REG_TX_ANT_CTRL_11N 0x80C
|
||||
#define DM_REG_BB_PWR_SAV5_11N 0x818
|
||||
#define DM_REG_CCK_RPT_FORMAT_11N 0x824
|
||||
#define DM_REG_RX_DEFUALT_A_11N 0x858
|
||||
#define DM_REG_RX_DEFUALT_B_11N 0x85A
|
||||
#define DM_REG_BB_PWR_SAV3_11N 0x85C
|
||||
#define DM_REG_ANTSEL_CTRL_11N 0x860
|
||||
#define DM_REG_RX_ANT_CTRL_11N 0x864
|
||||
#define DM_REG_PIN_CTRL_11N 0x870
|
||||
#define DM_REG_BB_PWR_SAV1_11N 0x874
|
||||
#define DM_REG_ANTSEL_PATH_11N 0x878
|
||||
#define DM_REG_BB_3WIRE_11N 0x88C
|
||||
#define DM_REG_SC_CNT_11N 0x8C4
|
||||
#define DM_REG_PSD_DATA_11N 0x8B4
|
||||
/*PAGE 9*/
|
||||
#define DM_REG_ANT_MAPPING1_11N 0x914
|
||||
#define DM_REG_ANT_MAPPING2_11N 0x918
|
||||
/*PAGE A*/
|
||||
#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00
|
||||
#define DM_REG_CCK_CCA_11N 0xA0A
|
||||
#define DM_REG_CCK_CCA_11AC 0xA0A
|
||||
#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
|
||||
#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10
|
||||
#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14
|
||||
#define DM_REG_CCK_FILTER_PARA1_11N 0xA22
|
||||
#define DM_REG_CCK_FILTER_PARA2_11N 0xA23
|
||||
#define DM_REG_CCK_FILTER_PARA3_11N 0xA24
|
||||
#define DM_REG_CCK_FILTER_PARA4_11N 0xA25
|
||||
#define DM_REG_CCK_FILTER_PARA5_11N 0xA26
|
||||
#define DM_REG_CCK_FILTER_PARA6_11N 0xA27
|
||||
#define DM_REG_CCK_FILTER_PARA7_11N 0xA28
|
||||
#define DM_REG_CCK_FILTER_PARA8_11N 0xA29
|
||||
#define DM_REG_CCK_FA_RST_11N 0xA2C
|
||||
#define DM_REG_CCK_FA_MSB_11N 0xA58
|
||||
#define DM_REG_CCK_FA_LSB_11N 0xA5C
|
||||
#define DM_REG_CCK_CCA_CNT_11N 0xA60
|
||||
#define DM_REG_BB_PWR_SAV4_11N 0xA74
|
||||
/*PAGE B */
|
||||
#define DM_REG_LNA_SWITCH_11N 0xB2C
|
||||
#define DM_REG_PATH_SWITCH_11N 0xB30
|
||||
#define DM_REG_RSSI_CTRL_11N 0xB38
|
||||
#define DM_REG_CONFIG_ANTA_11N 0xB68
|
||||
#define DM_REG_RSSI_BT_11N 0xB9C
|
||||
/*PAGE C */
|
||||
#define DM_REG_OFDM_FA_HOLDC_11N 0xC00
|
||||
#define DM_REG_RX_PATH_11N 0xC04
|
||||
#define DM_REG_TRMUX_11N 0xC08
|
||||
#define DM_REG_OFDM_FA_RSTC_11N 0xC0C
|
||||
#define DM_REG_RXIQI_MATRIX_11N 0xC14
|
||||
#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
|
||||
#define DM_REG_IGI_A_11N 0xC50
|
||||
#define DM_REG_IGI_A_11AC 0xC50
|
||||
#define DM_REG_ANTDIV_PARA2_11N 0xC54
|
||||
#define DM_REG_IGI_B_11N 0xC58
|
||||
#define DM_REG_IGI_B_11AC 0xE50
|
||||
#define DM_REG_ANTDIV_PARA3_11N 0xC5C
|
||||
#define DM_REG_BB_PWR_SAV2_11N 0xC70
|
||||
#define DM_REG_RX_OFF_11N 0xC7C
|
||||
#define DM_REG_TXIQK_MATRIXA_11N 0xC80
|
||||
#define DM_REG_TXIQK_MATRIXB_11N 0xC88
|
||||
#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
|
||||
#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
|
||||
#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
|
||||
#define DM_REG_ANTDIV_PARA1_11N 0xCA4
|
||||
#define DM_REG_OFDM_FA_TYPE1_11N 0xCF0
|
||||
/*PAGE D */
|
||||
#define DM_REG_OFDM_FA_RSTD_11N 0xD00
|
||||
#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0
|
||||
#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4
|
||||
#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8
|
||||
/*PAGE E */
|
||||
#define DM_REG_TXAGC_A_6_18_11N 0xE00
|
||||
#define DM_REG_TXAGC_A_24_54_11N 0xE04
|
||||
#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08
|
||||
#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10
|
||||
#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14
|
||||
#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18
|
||||
#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C
|
||||
#define DM_REG_FPGA0_IQK_11N 0xE28
|
||||
#define DM_REG_TXIQK_TONE_A_11N 0xE30
|
||||
#define DM_REG_RXIQK_TONE_A_11N 0xE34
|
||||
#define DM_REG_TXIQK_PI_A_11N 0xE38
|
||||
#define DM_REG_RXIQK_PI_A_11N 0xE3C
|
||||
#define DM_REG_TXIQK_11N 0xE40
|
||||
#define DM_REG_RXIQK_11N 0xE44
|
||||
#define DM_REG_IQK_AGC_PTS_11N 0xE48
|
||||
#define DM_REG_IQK_AGC_RSP_11N 0xE4C
|
||||
#define DM_REG_BLUETOOTH_11N 0xE6C
|
||||
#define DM_REG_RX_WAIT_CCA_11N 0xE70
|
||||
#define DM_REG_TX_CCK_RFON_11N 0xE74
|
||||
#define DM_REG_TX_CCK_BBON_11N 0xE78
|
||||
#define DM_REG_OFDM_RFON_11N 0xE7C
|
||||
#define DM_REG_OFDM_BBON_11N 0xE80
|
||||
#define DM_REG_TX2RX_11N 0xE84
|
||||
#define DM_REG_TX2TX_11N 0xE88
|
||||
#define DM_REG_RX_CCK_11N 0xE8C
|
||||
#define DM_REG_RX_OFDM_11N 0xED0
|
||||
#define DM_REG_RX_WAIT_RIFS_11N 0xED4
|
||||
#define DM_REG_RX2RX_11N 0xED8
|
||||
#define DM_REG_STANDBY_11N 0xEDC
|
||||
#define DM_REG_SLEEP_11N 0xEE0
|
||||
#define DM_REG_PMPD_ANAEN_11N 0xEEC
|
||||
|
||||
/*MAC REG LIST*/
|
||||
#define DM_REG_BB_RST_11N 0x02
|
||||
#define DM_REG_ANTSEL_PIN_11N 0x4C
|
||||
#define DM_REG_EARLY_MODE_11N 0x4D0
|
||||
#define DM_REG_RSSI_MONITOR_11N 0x4FE
|
||||
#define DM_REG_EDCA_VO_11N 0x500
|
||||
#define DM_REG_EDCA_VI_11N 0x504
|
||||
#define DM_REG_EDCA_BE_11N 0x508
|
||||
#define DM_REG_EDCA_BK_11N 0x50C
|
||||
#define DM_REG_TXPAUSE_11N 0x522
|
||||
#define DM_REG_RESP_TX_11N 0x6D8
|
||||
#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0
|
||||
#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4
|
||||
|
||||
/*DIG Related*/
|
||||
#define DM_BIT_IGI_11N 0x0000007F
|
||||
#define DM_BIT_IGI_11AC 0xFFFFFFFF
|
||||
|
||||
#define HAL_DM_DIG_DISABLE BIT(0)
|
||||
#define HAL_DM_HIPWR_DISABLE BIT(1)
|
||||
|
||||
#define OFDM_TABLE_LENGTH 43
|
||||
#define CCK_TABLE_LENGTH 33
|
||||
|
||||
#define OFDM_TABLE_SIZE 37
|
||||
#define CCK_TABLE_SIZE 33
|
||||
|
||||
#define BW_AUTO_SWITCH_HIGH_LOW 25
|
||||
#define BW_AUTO_SWITCH_LOW_HIGH 30
|
||||
|
||||
#define DM_DIG_THRESH_HIGH 40
|
||||
#define DM_DIG_THRESH_LOW 35
|
||||
|
||||
#define DM_FALSEALARM_THRESH_LOW 400
|
||||
#define DM_FALSEALARM_THRESH_HIGH 1000
|
||||
|
||||
#define DM_DIG_MAX 0x3e
|
||||
#define DM_DIG_MIN 0x1e
|
||||
|
||||
#define DM_DIG_MAX_AP 0x32
|
||||
#define DM_DIG_MIN_AP 0x20
|
||||
|
||||
#define DM_DIG_FA_UPPER 0x3e
|
||||
#define DM_DIG_FA_LOWER 0x1e
|
||||
#define DM_DIG_FA_TH0 200
|
||||
#define DM_DIG_FA_TH1 0x300
|
||||
#define DM_DIG_FA_TH2 0x400
|
||||
|
||||
#define DM_DIG_BACKOFF_MAX 12
|
||||
#define DM_DIG_BACKOFF_MIN -4
|
||||
#define DM_DIG_BACKOFF_DEFAULT 10
|
||||
|
||||
#define RXPATHSELECTION_SS_TH_LOW 30
|
||||
#define RXPATHSELECTION_DIFF_TH 18
|
||||
|
||||
#define DM_RATR_STA_INIT 0
|
||||
#define DM_RATR_STA_HIGH 1
|
||||
#define DM_RATR_STA_MIDDLE 2
|
||||
#define DM_RATR_STA_LOW 3
|
||||
|
||||
#define CTS2SELF_THVAL 30
|
||||
#define REGC38_TH 20
|
||||
|
||||
#define WAIOTTHVAL 25
|
||||
|
||||
#define TXHIGHPWRLEVEL_NORMAL 0
|
||||
#define TXHIGHPWRLEVEL_LEVEL1 1
|
||||
#define TXHIGHPWRLEVEL_LEVEL2 2
|
||||
#define TXHIGHPWRLEVEL_BT1 3
|
||||
#define TXHIGHPWRLEVEL_BT2 4
|
||||
|
||||
#define DM_TYPE_BYFW 0
|
||||
#define DM_TYPE_BYDRIVER 1
|
||||
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
|
||||
#define TXPWRTRACK_MAX_IDX 6
|
||||
|
||||
/* Dynamic ATC switch */
|
||||
#define ATC_STATUS_OFF 0x0 /* enable */
|
||||
#define ATC_STATUS_ON 0x1 /* disable */
|
||||
#define CFO_THRESHOLD_XTAL 10 /* kHz */
|
||||
#define CFO_THRESHOLD_ATC 80 /* kHz */
|
||||
|
||||
#define AVG_THERMAL_NUM_8812A 4
|
||||
#define TXPWR_TRACK_TABLE_SIZE 30
|
||||
#define MAX_PATH_NUM_8812A 2
|
||||
#define MAX_PATH_NUM_8821A 1
|
||||
|
||||
enum FAT_STATE {
|
||||
FAT_NORMAL_STATE = 0,
|
||||
FAT_TRAINING_STATE = 1,
|
||||
};
|
||||
|
||||
enum tag_dynamic_init_gain_operation_type_definition {
|
||||
DIG_TYPE_THRESH_HIGH = 0,
|
||||
DIG_TYPE_THRESH_LOW = 1,
|
||||
DIG_TYPE_BACKOFF = 2,
|
||||
DIG_TYPE_RX_GAIN_MIN = 3,
|
||||
DIG_TYPE_RX_GAIN_MAX = 4,
|
||||
DIG_TYPE_ENABLE = 5,
|
||||
DIG_TYPE_DISABLE = 6,
|
||||
DIG_OP_TYPE_MAX
|
||||
};
|
||||
|
||||
enum tag_cck_packet_detection_threshold_type_definition {
|
||||
CCK_PD_STAGE_LOWRSSI = 0,
|
||||
CCK_PD_STAGE_HIGHRSSI = 1,
|
||||
CCK_FA_STAGE_LOW = 2,
|
||||
CCK_FA_STAGE_HIGH = 3,
|
||||
CCK_PD_STAGE_MAX = 4,
|
||||
};
|
||||
|
||||
enum dm_1r_cca_e {
|
||||
CCA_1R = 0,
|
||||
CCA_2R = 1,
|
||||
CCA_MAX = 2,
|
||||
};
|
||||
|
||||
enum dm_rf_e {
|
||||
RF_SAVE = 0,
|
||||
RF_NORMAL = 1,
|
||||
RF_MAX = 2,
|
||||
};
|
||||
|
||||
enum dm_sw_ant_switch_e {
|
||||
ANS_ANTENNA_B = 1,
|
||||
ANS_ANTENNA_A = 2,
|
||||
ANS_ANTENNA_MAX = 3,
|
||||
};
|
||||
|
||||
enum dm_dig_ext_port_alg_e {
|
||||
DIG_EXT_PORT_STAGE_0 = 0,
|
||||
DIG_EXT_PORT_STAGE_1 = 1,
|
||||
DIG_EXT_PORT_STAGE_2 = 2,
|
||||
DIG_EXT_PORT_STAGE_3 = 3,
|
||||
DIG_EXT_PORT_STAGE_MAX = 4,
|
||||
};
|
||||
|
||||
enum dm_dig_connect_e {
|
||||
DIG_STA_DISCONNECT = 0,
|
||||
DIG_STA_CONNECT = 1,
|
||||
DIG_STA_BEFORE_CONNECT = 2,
|
||||
DIG_MULTISTA_DISCONNECT = 3,
|
||||
DIG_MULTISTA_CONNECT = 4,
|
||||
DIG_CONNECT_MAX
|
||||
};
|
||||
|
||||
enum pwr_track_control_method {
|
||||
BBSWING,
|
||||
TXAGC,
|
||||
MIX_MODE
|
||||
};
|
||||
|
||||
#define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
|
||||
#define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
|
||||
#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
|
||||
#define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
|
||||
#define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
|
||||
#define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
|
||||
((((struct rtl_priv *)(_priv))->mac80211.opmode == \
|
||||
NL80211_IFTYPE_ADHOC) ? \
|
||||
(((struct rtl_priv *)(_priv))->dm.entry_min_undec_sm_pwdb) : \
|
||||
(((struct rtl_priv *)(_priv))->dm.undec_sm_pwdb))
|
||||
|
||||
void rtl8821ae_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
|
||||
u8 *pdesc, u32 mac_id);
|
||||
void rtl8821ae_dm_ant_sel_statistics(struct ieee80211_hw *hw,
|
||||
u8 antsel_tr_mux, u32 mac_id,
|
||||
u32 rx_pwdb_all);
|
||||
void rtl8821ae_dm_fast_antenna_training_callback(unsigned long data);
|
||||
void rtl8821ae_dm_init(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_dm_watchdog(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);
|
||||
void rtl8821ae_dm_init_edca_turbo(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_dm_check_txpower_tracking_thermalmeter(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_dm_txpower_track_adjust(struct ieee80211_hw *hw,
|
||||
u8 type, u8 *pdirection,
|
||||
u32 *poutwrite_val);
|
||||
void rtl8821ae_dm_clear_txpower_tracking_state(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_dm_write_cck_cca_thres(struct ieee80211_hw *hw, u8 current_cca);
|
||||
void rtl8821ae_dm_initialize_txpower_tracking_thermalmeter(struct ieee80211_hw *hw);
|
||||
void rtl8812ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
|
||||
enum pwr_track_control_method method,
|
||||
u8 rf_path,
|
||||
u8 channel_mapped_index);
|
||||
void rtl8821ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
|
||||
enum pwr_track_control_method method,
|
||||
u8 rf_path, u8 channel_mapped_index);
|
||||
|
||||
void rtl8821ae_dm_update_init_rate(struct ieee80211_hw *hw, u8 rate);
|
||||
u8 rtl8821ae_hw_rate_to_mrate(struct ieee80211_hw *hw, u8 rate);
|
||||
void rtl8812ae_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw);
|
||||
|
||||
#endif
|
||||
1857
drivers/net/wireless/rtlwifi/rtl8821ae/fw.c
Normal file
1857
drivers/net/wireless/rtlwifi/rtl8821ae/fw.c
Normal file
File diff suppressed because it is too large
Load diff
351
drivers/net/wireless/rtlwifi/rtl8821ae/fw.h
Normal file
351
drivers/net/wireless/rtlwifi/rtl8821ae/fw.h
Normal file
|
|
@ -0,0 +1,351 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2010 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL8821AE__FW__H__
|
||||
#define __RTL8821AE__FW__H__
|
||||
#include "def.h"
|
||||
|
||||
#define FW_8821AE_SIZE 0x8000
|
||||
#define FW_8821AE_START_ADDRESS 0x1000
|
||||
#define FW_8821AE_END_ADDRESS 0x5FFF
|
||||
#define FW_8821AE_PAGE_SIZE 4096
|
||||
#define FW_8821AE_POLLING_DELAY 5
|
||||
#define FW_8821AE_POLLING_TIMEOUT_COUNT 6000
|
||||
|
||||
#define IS_FW_HEADER_EXIST_8812(_pfwhdr) \
|
||||
((_pfwhdr->signature&0xFFF0) == 0x9500)
|
||||
|
||||
#define IS_FW_HEADER_EXIST_8821(_pfwhdr) \
|
||||
((_pfwhdr->signature&0xFFF0) == 0x2100)
|
||||
|
||||
#define USE_OLD_WOWLAN_DEBUG_FW 0
|
||||
|
||||
#define H2C_8821AE_RSVDPAGE_LOC_LEN 5
|
||||
#define H2C_8821AE_PWEMODE_LENGTH 5
|
||||
#define H2C_8821AE_JOINBSSRPT_LENGTH 1
|
||||
#define H2C_8821AE_AP_OFFLOAD_LENGTH 3
|
||||
#define H2C_8821AE_WOWLAN_LENGTH 3
|
||||
#define H2C_8821AE_KEEP_ALIVE_CTRL_LENGTH 3
|
||||
#if (USE_OLD_WOWLAN_DEBUG_FW == 0)
|
||||
#define H2C_8821AE_REMOTE_WAKE_CTRL_LEN 1
|
||||
#else
|
||||
#define H2C_8821AE_REMOTE_WAKE_CTRL_LEN 3
|
||||
#endif
|
||||
#define H2C_8821AE_AOAC_GLOBAL_INFO_LEN 2
|
||||
#define H2C_8821AE_AOAC_RSVDPAGE_LOC_LEN 7
|
||||
#define H2C_8821AE_DISCONNECT_DECISION_CTRL_LEN 3
|
||||
|
||||
/* Fw PS state for RPWM.
|
||||
*BIT[2:0] = HW state
|
||||
|
||||
*BIT[3] = Protocol PS state,
|
||||
1: register active state ,
|
||||
0: register sleep state
|
||||
|
||||
*BIT[4] = sub-state
|
||||
*/
|
||||
#define FW_PS_GO_ON BIT(0)
|
||||
#define FW_PS_TX_NULL BIT(1)
|
||||
#define FW_PS_RF_ON BIT(2)
|
||||
#define FW_PS_REGISTER_ACTIVE BIT(3)
|
||||
|
||||
#define FW_PS_DPS BIT(0)
|
||||
#define FW_PS_LCLK (FW_PS_DPS)
|
||||
#define FW_PS_RF_OFF BIT(1)
|
||||
#define FW_PS_ALL_ON BIT(2)
|
||||
#define FW_PS_ST_ACTIVE BIT(3)
|
||||
#define FW_PS_ISR_ENABLE BIT(4)
|
||||
#define FW_PS_IMR_ENABLE BIT(5)
|
||||
|
||||
#define FW_PS_ACK BIT(6)
|
||||
#define FW_PS_TOGGLE BIT(7)
|
||||
|
||||
/* 8821AE RPWM value*/
|
||||
/* BIT[0] = 1: 32k, 0: 40M*/
|
||||
/* 32k*/
|
||||
#define FW_PS_CLOCK_OFF BIT(0)
|
||||
/*40M*/
|
||||
#define FW_PS_CLOCK_ON 0
|
||||
|
||||
#define FW_PS_STATE_MASK (0x0F)
|
||||
#define FW_PS_STATE_HW_MASK (0x07)
|
||||
/*ISR_ENABLE, IMR_ENABLE, and PS mode should be inherited.*/
|
||||
#define FW_PS_STATE_INT_MASK (0x3F)
|
||||
|
||||
#define FW_PS_STATE(x) (FW_PS_STATE_MASK & (x))
|
||||
#define FW_PS_STATE_HW(x) (FW_PS_STATE_HW_MASK & (x))
|
||||
#define FW_PS_STATE_INT(x) (FW_PS_STATE_INT_MASK & (x))
|
||||
#define FW_PS_ISR_VAL(x) ((x) & 0x70)
|
||||
#define FW_PS_IMR_MASK(x) ((x) & 0xDF)
|
||||
#define FW_PS_KEEP_IMR(x) ((x) & 0x20)
|
||||
|
||||
#define FW_PS_STATE_S0 (FW_PS_DPS)
|
||||
#define FW_PS_STATE_S1 (FW_PS_LCLK)
|
||||
#define FW_PS_STATE_S2 (FW_PS_RF_OFF)
|
||||
#define FW_PS_STATE_S3 (FW_PS_ALL_ON)
|
||||
#define FW_PS_STATE_S4 ((FW_PS_ST_ACTIVE) | (FW_PS_ALL_ON))
|
||||
/* ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))*/
|
||||
#define FW_PS_STATE_ALL_ON_8821AE (FW_PS_CLOCK_ON)
|
||||
/* (FW_PS_RF_ON)*/
|
||||
#define FW_PS_STATE_RF_ON_8821AE (FW_PS_CLOCK_ON)
|
||||
/* 0x0*/
|
||||
#define FW_PS_STATE_RF_OFF_8821AE (FW_PS_CLOCK_ON)
|
||||
/* (FW_PS_STATE_RF_OFF)*/
|
||||
#define FW_PS_STATE_RF_OFF_LOW_PWR_8821AE (FW_PS_CLOCK_OFF)
|
||||
|
||||
#define FW_PS_STATE_ALL_ON_92C (FW_PS_STATE_S4)
|
||||
#define FW_PS_STATE_RF_ON_92C (FW_PS_STATE_S3)
|
||||
#define FW_PS_STATE_RF_OFF_92C (FW_PS_STATE_S2)
|
||||
#define FW_PS_STATE_RF_OFF_LOW_PWR_92C (FW_PS_STATE_S1)
|
||||
|
||||
/* For 8821AE H2C PwrMode Cmd ID 5.*/
|
||||
#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
|
||||
#define FW_PWR_STATE_RF_OFF 0
|
||||
|
||||
#define FW_PS_IS_ACK(x) ((x) & FW_PS_ACK)
|
||||
#define FW_PS_IS_CLK_ON(x) ((x) & (FW_PS_RF_OFF | FW_PS_ALL_ON))
|
||||
#define FW_PS_IS_RF_ON(x) ((x) & (FW_PS_ALL_ON))
|
||||
#define FW_PS_IS_ACTIVE(x) ((x) & (FW_PS_ST_ACTIVE))
|
||||
#define FW_PS_IS_CPWM_INT(x) ((x) & 0x40)
|
||||
|
||||
#define FW_CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
|
||||
|
||||
#define IS_IN_LOW_POWER_STATE_8821AE(__state) \
|
||||
(FW_PS_STATE(__state) == FW_PS_CLOCK_OFF)
|
||||
|
||||
#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
|
||||
#define FW_PWR_STATE_RF_OFF 0
|
||||
|
||||
struct rtl8821a_firmware_header {
|
||||
u16 signature;
|
||||
u8 category;
|
||||
u8 function;
|
||||
u16 version;
|
||||
u8 subversion;
|
||||
u8 rsvd1;
|
||||
u8 month;
|
||||
u8 date;
|
||||
u8 hour;
|
||||
u8 minute;
|
||||
u16 ramcodeSize;
|
||||
u16 rsvd2;
|
||||
u32 svnindex;
|
||||
u32 rsvd3;
|
||||
u32 rsvd4;
|
||||
u32 rsvd5;
|
||||
};
|
||||
|
||||
enum rtl8812_c2h_evt {
|
||||
C2H_8812_DBG = 0,
|
||||
C2H_8812_LB = 1,
|
||||
C2H_8812_TXBF = 2,
|
||||
C2H_8812_TX_REPORT = 3,
|
||||
C2H_8812_BT_INFO = 9,
|
||||
C2H_8812_BT_MP = 11,
|
||||
C2H_8812_RA_RPT = 12,
|
||||
|
||||
C2H_8812_FW_SWCHNL = 0x10,
|
||||
C2H_8812_IQK_FINISH = 0x11,
|
||||
MAX_8812_C2HEVENT
|
||||
};
|
||||
|
||||
enum rtl8821a_h2c_cmd {
|
||||
H2C_8821AE_RSVDPAGE = 0,
|
||||
H2C_8821AE_MSRRPT = 1,
|
||||
H2C_8821AE_SCAN = 2,
|
||||
H2C_8821AE_KEEP_ALIVE_CTRL = 3,
|
||||
H2C_8821AE_DISCONNECT_DECISION = 4,
|
||||
H2C_8821AE_INIT_OFFLOAD = 6,
|
||||
H2C_8821AE_AP_OFFLOAD = 8,
|
||||
H2C_8821AE_BCN_RSVDPAGE = 9,
|
||||
H2C_8821AE_PROBERSP_RSVDPAGE = 10,
|
||||
|
||||
H2C_8821AE_SETPWRMODE = 0x20,
|
||||
H2C_8821AE_PS_TUNING_PARA = 0x21,
|
||||
H2C_8821AE_PS_TUNING_PARA2 = 0x22,
|
||||
H2C_8821AE_PS_LPS_PARA = 0x23,
|
||||
H2C_8821AE_P2P_PS_OFFLOAD = 024,
|
||||
|
||||
H2C_8821AE_WO_WLAN = 0x80,
|
||||
H2C_8821AE_REMOTE_WAKE_CTRL = 0x81,
|
||||
H2C_8821AE_AOAC_GLOBAL_INFO = 0x82,
|
||||
H2C_8821AE_AOAC_RSVDPAGE = 0x83,
|
||||
|
||||
H2C_RSSI_21AE_REPORT = 0x42,
|
||||
H2C_8821AE_RA_MASK = 0x40,
|
||||
H2C_8821AE_SELECTIVE_SUSPEND_ROF_CMD,
|
||||
H2C_8821AE_P2P_PS_MODE,
|
||||
H2C_8821AE_PSD_RESULT,
|
||||
/*Not defined CTW CMD for P2P yet*/
|
||||
H2C_8821AE_P2P_PS_CTW_CMD,
|
||||
MAX_8821AE_H2CCMD
|
||||
};
|
||||
|
||||
#define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1 : 0))
|
||||
|
||||
#define SET_8812_H2CCMD_WOWLAN_FUNC_ENABLE(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 0, 1, __value)
|
||||
#define SET_8812_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 1, 1, __value)
|
||||
#define SET_8812_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 2, 1, __value)
|
||||
#define SET_8812_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 3, 1, __value)
|
||||
#define SET_8812_H2CCMD_WOWLAN_ALL_PKT_DROP(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 4, 1, __value)
|
||||
#define SET_8812_H2CCMD_WOWLAN_GPIO_ACTIVE(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 5, 1, __value)
|
||||
#define SET_8812_H2CCMD_WOWLAN_REKEY_WAKE_UP(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 6, 1, __value)
|
||||
#define SET_8812_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 7, 1, __value)
|
||||
#define SET_8812_H2CCMD_WOWLAN_GPIONUM(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd) + 1, 0, 8, __value)
|
||||
#define SET_8812_H2CCMD_WOWLAN_GPIO_DURATION(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd) + 2, 0, 8, __value)
|
||||
|
||||
#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_RLBM(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 4, __value)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+1, 4, 4, __value)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+2, 0, 8, __value)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+3, 0, 8, __value)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_PWR_STATE(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+4, 0, 8, __value)
|
||||
#define GET_8821AE_H2CCMD_PWRMODE_PARM_MODE(__cmd) \
|
||||
LE_BITS_TO_1BYTE(__cmd, 0, 8)
|
||||
|
||||
#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__ph2ccmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__ph2ccmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE((__ph2ccmd)+3, 0, 8, __val)
|
||||
|
||||
/* _MEDIA_STATUS_RPT_PARM_CMD1 */
|
||||
#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 0, 1, __value)
|
||||
#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 1, 1, __value)
|
||||
#define SET_H2CCMD_MSRRPT_PARM_MACID(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd+1, 0, 8, __value)
|
||||
#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd+2, 0, 8, __value)
|
||||
|
||||
/* AP_OFFLOAD */
|
||||
#define SET_H2CCMD_AP_OFFLOAD_ON(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 0, 8, __value)
|
||||
#define SET_H2CCMD_AP_OFFLOAD_HIDDEN(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 8, __value)
|
||||
#define SET_H2CCMD_AP_OFFLOAD_DENYANY(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+2, 0, 8, __value)
|
||||
#define SET_H2CCMD_AP_OFFLOAD_WAKEUP_EVT_RPT(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+3, 0, 8, __value)
|
||||
|
||||
/* Keep Alive Control*/
|
||||
#define SET_8812_H2CCMD_KEEP_ALIVE_ENABLE(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 0, 1, __value)
|
||||
#define SET_8812_H2CCMD_KEEP_ALIVE_ACCPEPT_USER_DEFINED(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 1, 1, __value)
|
||||
#define SET_8812_H2CCMD_KEEP_ALIVE_PERIOD(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 8, __value)
|
||||
|
||||
/*REMOTE_WAKE_CTRL */
|
||||
#define SET_8812_H2CCMD_REMOTE_WAKECTRL_ENABLE(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 0, 1, __value)
|
||||
#define SET_8812_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__cmd, __value)\
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 1, 1, __value)
|
||||
#define SET_8812_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__cmd, __value)\
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 2, 1, __value)
|
||||
#define SET_8812_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__cmd, __value)\
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 3, 1, __value)
|
||||
#define SET_8812_H2CCMD_REMOTE_WAKE_CTRL_REALWOWV2_EN(__cmd, __value)\
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 6, 1, __value)
|
||||
|
||||
/* GTK_OFFLOAD */
|
||||
#define SET_8812_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__cmd, __value)\
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 0, 8, __value)
|
||||
#define SET_8812_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 8, __value)
|
||||
|
||||
/* AOAC_RSVDPAGE_LOC */
|
||||
#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd), 0, 8, __value)
|
||||
#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 8, __value)
|
||||
#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__cmd, __value)\
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+2, 0, 8, __value)
|
||||
#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+3, 0, 8, __value)
|
||||
#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+4, 0, 8, __value)
|
||||
#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+5, 0, 8, __value)
|
||||
|
||||
/* Disconnect_Decision_Control */
|
||||
#define SET_8812_H2CCMD_DISCONNECT_DECISION_CTRL_ENABLE(__cmd, __value) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 0, 1, __value)
|
||||
#define SET_8812_H2CCMD_DISCONNECT_DECISION_CTRL_USER_SETTING(__cmd, __value)\
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 1, 1, __value)
|
||||
#define SET_8812_H2CCMD_DISCONNECT_DECISION_CTRL_CHECK_PERIOD(__cmd, __value)\
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 8, __value) /* unit: beacon period */
|
||||
#define SET_8812_H2CCMD_DISCONNECT_DECISION_CTRL_TRYPKT_NUM(__cmd, __value)\
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+2, 0, 8, __value)
|
||||
|
||||
int rtl8821ae_download_fw(struct ieee80211_hw *hw, bool buse_wake_on_wlan_fw);
|
||||
#if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
|
||||
void rtl8821ae_set_fw_related_for_wowlan(struct ieee80211_hw *hw,
|
||||
bool used_wowlan_fw);
|
||||
|
||||
#endif
|
||||
void rtl8821ae_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
|
||||
u32 cmd_len, u8 *cmdbuffer);
|
||||
void rtl8821ae_firmware_selfreset(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
|
||||
void rtl8821ae_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw,
|
||||
u8 mstatus);
|
||||
void rtl8821ae_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw,
|
||||
u8 ap_offload_enable);
|
||||
void rtl8821ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw,
|
||||
bool b_dl_finished, bool dl_whole_packet);
|
||||
void rtl8812ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw,
|
||||
bool b_dl_finished, bool dl_whole_packet);
|
||||
void rtl8821ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw,
|
||||
u8 p2p_ps_state);
|
||||
void rtl8821ae_set_fw_wowlan_mode(struct ieee80211_hw *hw, bool func_en);
|
||||
void rtl8821ae_set_fw_remote_wake_ctrl_cmd(struct ieee80211_hw *hw,
|
||||
u8 enable);
|
||||
void rtl8821ae_set_fw_keep_alive_cmd(struct ieee80211_hw *hw, bool func_en);
|
||||
void rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(struct ieee80211_hw *hw,
|
||||
bool enabled);
|
||||
void rtl8821ae_set_fw_global_info_cmd(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_c2h_packet_handler(struct ieee80211_hw *hw,
|
||||
u8 *buffer, u8 length);
|
||||
#endif
|
||||
4219
drivers/net/wireless/rtlwifi/rtl8821ae/hw.c
Normal file
4219
drivers/net/wireless/rtlwifi/rtl8821ae/hw.c
Normal file
File diff suppressed because it is too large
Load diff
70
drivers/net/wireless/rtlwifi/rtl8821ae/hw.h
Normal file
70
drivers/net/wireless/rtlwifi/rtl8821ae/hw.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2010 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL8821AE_HW_H__
|
||||
#define __RTL8821AE_HW_H__
|
||||
|
||||
void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
|
||||
void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw);
|
||||
|
||||
void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
|
||||
u32 *p_inta, u32 *p_intb);
|
||||
int rtl8821ae_hw_init(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_card_disable(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw);
|
||||
int rtl8821ae_set_network_type(struct ieee80211_hw *hw,
|
||||
enum nl80211_iftype type);
|
||||
void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
|
||||
void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci);
|
||||
void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
|
||||
u32 add_msr, u32 rm_msr);
|
||||
void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
|
||||
void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
|
||||
struct ieee80211_sta *sta,
|
||||
u8 rssi_level);
|
||||
void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw);
|
||||
bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
|
||||
void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
|
||||
u8 *p_macaddr, bool is_group, u8 enc_algo,
|
||||
bool is_wepkey, bool clear_all);
|
||||
|
||||
void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_suspend(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_resume(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
|
||||
bool allow_all_da,
|
||||
bool write_into_reg);
|
||||
void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw);
|
||||
void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
|
||||
struct rtl_wow_pattern *rtl_pattern,
|
||||
u8 index);
|
||||
|
||||
#endif
|
||||
237
drivers/net/wireless/rtlwifi/rtl8821ae/led.c
Normal file
237
drivers/net/wireless/rtlwifi/rtl8821ae/led.c
Normal file
|
|
@ -0,0 +1,237 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2010 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "../wifi.h"
|
||||
#include "../pci.h"
|
||||
#include "reg.h"
|
||||
#include "led.h"
|
||||
|
||||
static void _rtl8821ae_init_led(struct ieee80211_hw *hw,
|
||||
struct rtl_led *pled,
|
||||
enum rtl_led_pin ledpin)
|
||||
{
|
||||
pled->hw = hw;
|
||||
pled->ledpin = ledpin;
|
||||
pled->ledon = false;
|
||||
}
|
||||
|
||||
void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
|
||||
{
|
||||
u8 ledcfg;
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
|
||||
"LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
|
||||
|
||||
switch (pled->ledpin) {
|
||||
case LED_PIN_GPIO0:
|
||||
break;
|
||||
case LED_PIN_LED0:
|
||||
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
|
||||
ledcfg &= ~BIT(6);
|
||||
rtl_write_byte(rtlpriv,
|
||||
REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5));
|
||||
break;
|
||||
case LED_PIN_LED1:
|
||||
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
|
||||
rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg & 0x10);
|
||||
break;
|
||||
default:
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
|
||||
"switch case not process\n");
|
||||
break;
|
||||
}
|
||||
pled->ledon = true;
|
||||
}
|
||||
|
||||
void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
|
||||
{
|
||||
u16 ledreg = REG_LEDCFG1;
|
||||
u8 ledcfg = 0;
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
|
||||
switch (pled->ledpin) {
|
||||
case LED_PIN_LED0:
|
||||
ledreg = REG_LEDCFG1;
|
||||
break;
|
||||
|
||||
case LED_PIN_LED1:
|
||||
ledreg = REG_LEDCFG2;
|
||||
break;
|
||||
|
||||
case LED_PIN_GPIO0:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
|
||||
"In SwLedOn, LedAddr:%X LEDPIN=%d\n",
|
||||
ledreg, pled->ledpin);
|
||||
|
||||
ledcfg = rtl_read_byte(rtlpriv, ledreg);
|
||||
ledcfg |= BIT(5); /*Set 0x4c[21]*/
|
||||
ledcfg &= ~(BIT(7) | BIT(6) | BIT(3) | BIT(2) | BIT(1) | BIT(0));
|
||||
/*Clear 0x4c[23:22] and 0x4c[19:16]*/
|
||||
rtl_write_byte(rtlpriv, ledreg, ledcfg); /*SW control led0 on.*/
|
||||
pled->ledon = true;
|
||||
}
|
||||
|
||||
void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
|
||||
u8 ledcfg;
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
|
||||
"LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
|
||||
|
||||
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
|
||||
|
||||
switch (pled->ledpin) {
|
||||
case LED_PIN_GPIO0:
|
||||
break;
|
||||
case LED_PIN_LED0:
|
||||
ledcfg &= 0xf0;
|
||||
if (pcipriv->ledctl.led_opendrain) {
|
||||
ledcfg &= 0x90; /* Set to software control. */
|
||||
rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg|BIT(3)));
|
||||
ledcfg = rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG);
|
||||
ledcfg &= 0xFE;
|
||||
rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, ledcfg);
|
||||
} else {
|
||||
ledcfg &= ~BIT(6);
|
||||
rtl_write_byte(rtlpriv, REG_LEDCFG2,
|
||||
(ledcfg | BIT(3) | BIT(5)));
|
||||
}
|
||||
break;
|
||||
case LED_PIN_LED1:
|
||||
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
|
||||
ledcfg &= 0x10; /* Set to software control. */
|
||||
rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg|BIT(3));
|
||||
break;
|
||||
default:
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
|
||||
"switch case not process\n");
|
||||
break;
|
||||
}
|
||||
pled->ledon = false;
|
||||
}
|
||||
|
||||
void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
|
||||
{
|
||||
u16 ledreg = REG_LEDCFG1;
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
|
||||
|
||||
switch (pled->ledpin) {
|
||||
case LED_PIN_LED0:
|
||||
ledreg = REG_LEDCFG1;
|
||||
break;
|
||||
|
||||
case LED_PIN_LED1:
|
||||
ledreg = REG_LEDCFG2;
|
||||
break;
|
||||
|
||||
case LED_PIN_GPIO0:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
|
||||
"In SwLedOff,LedAddr:%X LEDPIN=%d\n",
|
||||
ledreg, pled->ledpin);
|
||||
/*Open-drain arrangement for controlling the LED*/
|
||||
if (pcipriv->ledctl.led_opendrain) {
|
||||
u8 ledcfg = rtl_read_byte(rtlpriv, ledreg);
|
||||
|
||||
ledreg &= 0xd0; /* Set to software control.*/
|
||||
rtl_write_byte(rtlpriv, ledreg, (ledcfg | BIT(3)));
|
||||
|
||||
/*Open-drain arrangement*/
|
||||
ledcfg = rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG);
|
||||
ledcfg &= 0xFE;/*Set GPIO[8] to input mode*/
|
||||
rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, ledcfg);
|
||||
} else {
|
||||
rtl_write_byte(rtlpriv, ledreg, 0x28);
|
||||
}
|
||||
|
||||
pled->ledon = false;
|
||||
}
|
||||
|
||||
void rtl8821ae_init_sw_leds(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
|
||||
|
||||
_rtl8821ae_init_led(hw, &pcipriv->ledctl.sw_led0, LED_PIN_LED0);
|
||||
_rtl8821ae_init_led(hw, &pcipriv->ledctl.sw_led1, LED_PIN_LED1);
|
||||
}
|
||||
|
||||
static void _rtl8821ae_sw_led_control(struct ieee80211_hw *hw,
|
||||
enum led_ctl_mode ledaction)
|
||||
{
|
||||
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
|
||||
struct rtl_led *pLed0 = &pcipriv->ledctl.sw_led0;
|
||||
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
|
||||
|
||||
switch (ledaction) {
|
||||
case LED_CTL_POWER_ON:
|
||||
case LED_CTL_LINK:
|
||||
case LED_CTL_NO_LINK:
|
||||
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
|
||||
rtl8812ae_sw_led_on(hw, pLed0);
|
||||
else
|
||||
rtl8821ae_sw_led_on(hw, pLed0);
|
||||
break;
|
||||
case LED_CTL_POWER_OFF:
|
||||
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
|
||||
rtl8812ae_sw_led_off(hw, pLed0);
|
||||
else
|
||||
rtl8821ae_sw_led_off(hw, pLed0);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rtl8821ae_led_control(struct ieee80211_hw *hw,
|
||||
enum led_ctl_mode ledaction)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
|
||||
|
||||
if ((ppsc->rfoff_reason > RF_CHANGE_BY_PS) &&
|
||||
(ledaction == LED_CTL_TX ||
|
||||
ledaction == LED_CTL_RX ||
|
||||
ledaction == LED_CTL_SITE_SURVEY ||
|
||||
ledaction == LED_CTL_LINK ||
|
||||
ledaction == LED_CTL_NO_LINK ||
|
||||
ledaction == LED_CTL_START_TO_LINK ||
|
||||
ledaction == LED_CTL_POWER_ON)) {
|
||||
return;
|
||||
}
|
||||
RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, "ledaction %d,\n",
|
||||
ledaction);
|
||||
_rtl8821ae_sw_led_control(hw, ledaction);
|
||||
}
|
||||
37
drivers/net/wireless/rtlwifi/rtl8821ae/led.h
Normal file
37
drivers/net/wireless/rtlwifi/rtl8821ae/led.h
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2010 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL8821AE_LED_H__
|
||||
#define __RTL8821AE_LED_H__
|
||||
|
||||
void rtl8821ae_init_sw_leds(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
|
||||
void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
|
||||
void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
|
||||
void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
|
||||
void rtl8821ae_led_control(struct ieee80211_hw *hw,
|
||||
enum led_ctl_mode ledaction);
|
||||
|
||||
#endif
|
||||
4858
drivers/net/wireless/rtlwifi/rtl8821ae/phy.c
Normal file
4858
drivers/net/wireless/rtlwifi/rtl8821ae/phy.c
Normal file
File diff suppressed because it is too large
Load diff
259
drivers/net/wireless/rtlwifi/rtl8821ae/phy.h
Normal file
259
drivers/net/wireless/rtlwifi/rtl8821ae/phy.h
Normal file
|
|
@ -0,0 +1,259 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2010 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL8821AE_PHY_H__
|
||||
#define __RTL8821AE_PHY_H__
|
||||
|
||||
/* MAX_TX_COUNT must always be set to 4, otherwise read
|
||||
* efuse table sequence will be wrong.
|
||||
*/
|
||||
#define MAX_TX_COUNT 4
|
||||
#define TX_1S 0
|
||||
#define TX_2S 1
|
||||
#define TX_3S 2
|
||||
#define TX_4S 3
|
||||
|
||||
#define MAX_POWER_INDEX 0x3F
|
||||
|
||||
#define MAX_PRECMD_CNT 16
|
||||
#define MAX_RFDEPENDCMD_CNT 16
|
||||
#define MAX_POSTCMD_CNT 16
|
||||
|
||||
#define MAX_DOZE_WAITING_TIMES_9x 64
|
||||
|
||||
#define RT_CANNOT_IO(hw) false
|
||||
#define HIGHPOWER_RADIOA_ARRAYLEN 22
|
||||
|
||||
#define IQK_ADDA_REG_NUM 16
|
||||
#define IQK_BB_REG_NUM 9
|
||||
#define MAX_TOLERANCE 5
|
||||
#define IQK_DELAY_TIME 10
|
||||
#define index_mapping_NUM 15
|
||||
|
||||
#define APK_BB_REG_NUM 5
|
||||
#define APK_AFE_REG_NUM 16
|
||||
#define APK_CURVE_REG_NUM 4
|
||||
#define PATH_NUM 2
|
||||
|
||||
#define LOOP_LIMIT 5
|
||||
#define MAX_STALL_TIME 50
|
||||
#define AntennaDiversityValue 0x80
|
||||
#define MAX_TXPWR_IDX_NMODE_92S 63
|
||||
#define Reset_Cnt_Limit 3
|
||||
|
||||
#define IQK_ADDA_REG_NUM 16
|
||||
#define IQK_MAC_REG_NUM 4
|
||||
|
||||
#define RF6052_MAX_PATH 2
|
||||
|
||||
#define CT_OFFSET_MAC_ADDR 0X16
|
||||
|
||||
#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
|
||||
#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
|
||||
#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
|
||||
#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
|
||||
#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
|
||||
|
||||
#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
|
||||
#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
|
||||
|
||||
#define CT_OFFSET_CHANNEL_PLAH 0x75
|
||||
#define CT_OFFSET_THERMAL_METER 0x78
|
||||
#define CT_OFFSET_RF_OPTION 0x79
|
||||
#define CT_OFFSET_VERSION 0x7E
|
||||
#define CT_OFFSET_CUSTOMER_ID 0x7F
|
||||
|
||||
#define RTL8821AE_MAX_PATH_NUM 2
|
||||
|
||||
#define TARGET_CHNL_NUM_2G_5G_8812 59
|
||||
|
||||
enum swchnlcmd_id {
|
||||
CMDID_END,
|
||||
CMDID_SET_TXPOWEROWER_LEVEL,
|
||||
CMDID_BBREGWRITE10,
|
||||
CMDID_WRITEPORT_ULONG,
|
||||
CMDID_WRITEPORT_USHORT,
|
||||
CMDID_WRITEPORT_UCHAR,
|
||||
CMDID_RF_WRITEREG,
|
||||
};
|
||||
|
||||
struct swchnlcmd {
|
||||
enum swchnlcmd_id cmdid;
|
||||
u32 para1;
|
||||
u32 para2;
|
||||
u32 msdelay;
|
||||
};
|
||||
|
||||
enum hw90_block_e {
|
||||
HW90_BLOCK_MAC = 0,
|
||||
HW90_BLOCK_PHY0 = 1,
|
||||
HW90_BLOCK_PHY1 = 2,
|
||||
HW90_BLOCK_RF = 3,
|
||||
HW90_BLOCK_MAXIMUM = 4,
|
||||
};
|
||||
|
||||
enum baseband_config_type {
|
||||
BASEBAND_CONFIG_PHY_REG = 0,
|
||||
BASEBAND_CONFIG_AGC_TAB = 1,
|
||||
};
|
||||
|
||||
enum ra_offset_area {
|
||||
RA_OFFSET_LEGACY_OFDM1,
|
||||
RA_OFFSET_LEGACY_OFDM2,
|
||||
RA_OFFSET_HT_OFDM1,
|
||||
RA_OFFSET_HT_OFDM2,
|
||||
RA_OFFSET_HT_OFDM3,
|
||||
RA_OFFSET_HT_OFDM4,
|
||||
RA_OFFSET_HT_CCK,
|
||||
};
|
||||
|
||||
enum antenna_path {
|
||||
ANTENNA_NONE,
|
||||
ANTENNA_D,
|
||||
ANTENNA_C,
|
||||
ANTENNA_CD,
|
||||
ANTENNA_B,
|
||||
ANTENNA_BD,
|
||||
ANTENNA_BC,
|
||||
ANTENNA_BCD,
|
||||
ANTENNA_A,
|
||||
ANTENNA_AD,
|
||||
ANTENNA_AC,
|
||||
ANTENNA_ACD,
|
||||
ANTENNA_AB,
|
||||
ANTENNA_ABD,
|
||||
ANTENNA_ABC,
|
||||
ANTENNA_ABCD
|
||||
};
|
||||
|
||||
struct r_antenna_select_ofdm {
|
||||
u32 r_tx_antenna:4;
|
||||
u32 r_ant_l:4;
|
||||
u32 r_ant_non_ht:4;
|
||||
u32 r_ant_ht1:4;
|
||||
u32 r_ant_ht2:4;
|
||||
u32 r_ant_ht_s1:4;
|
||||
u32 r_ant_non_ht_s1:4;
|
||||
u32 ofdm_txsc:2;
|
||||
u32 reserved:2;
|
||||
};
|
||||
|
||||
struct r_antenna_select_cck {
|
||||
u8 r_cckrx_enable_2:2;
|
||||
u8 r_cckrx_enable:2;
|
||||
u8 r_ccktx_enable:4;
|
||||
};
|
||||
|
||||
struct efuse_contents {
|
||||
u8 mac_addr[ETH_ALEN];
|
||||
u8 cck_tx_power_idx[6];
|
||||
u8 ht40_1s_tx_power_idx[6];
|
||||
u8 ht40_2s_tx_power_idx_diff[3];
|
||||
u8 ht20_tx_power_idx_diff[3];
|
||||
u8 ofdm_tx_power_idx_diff[3];
|
||||
u8 ht40_max_power_offset[3];
|
||||
u8 ht20_max_power_offset[3];
|
||||
u8 channel_plan;
|
||||
u8 thermal_meter;
|
||||
u8 rf_option[5];
|
||||
u8 version;
|
||||
u8 oem_id;
|
||||
u8 regulatory;
|
||||
};
|
||||
|
||||
struct tx_power_struct {
|
||||
u8 cck[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
|
||||
u8 ht40_1s[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
|
||||
u8 ht40_2s[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
|
||||
u8 ht20_diff[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
|
||||
u8 legacy_ht_diff[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
|
||||
u8 legacy_ht_txpowerdiff;
|
||||
u8 groupht20[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
|
||||
u8 groupht40[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
|
||||
u8 pwrgroup_cnt;
|
||||
u32 mcs_original_offset[4][16];
|
||||
};
|
||||
enum _ANT_DIV_TYPE {
|
||||
NO_ANTDIV = 0xFF,
|
||||
CG_TRX_HW_ANTDIV = 0x01,
|
||||
CGCS_RX_HW_ANTDIV = 0x02,
|
||||
FIXED_HW_ANTDIV = 0x03,
|
||||
CG_TRX_SMART_ANTDIV = 0x04,
|
||||
CGCS_RX_SW_ANTDIV = 0x05,
|
||||
|
||||
};
|
||||
|
||||
u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw,
|
||||
u32 regaddr, u32 bitmask);
|
||||
void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw,
|
||||
u32 regaddr, u32 bitmask, u32 data);
|
||||
u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw,
|
||||
enum radio_path rfpath, u32 regaddr,
|
||||
u32 bitmask);
|
||||
void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw,
|
||||
enum radio_path rfpath, u32 regaddr,
|
||||
u32 bitmask, u32 data);
|
||||
bool rtl8821ae_phy_mac_config(struct ieee80211_hw *hw);
|
||||
bool rtl8821ae_phy_bb_config(struct ieee80211_hw *hw);
|
||||
bool rtl8821ae_phy_rf_config(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw *hw,
|
||||
u8 band);
|
||||
void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw *hw,
|
||||
long *powerlevel);
|
||||
void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw *hw,
|
||||
u8 channel);
|
||||
void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw *hw,
|
||||
u8 operation);
|
||||
void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw *hw,
|
||||
enum nl80211_channel_type ch_type);
|
||||
void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw *hw);
|
||||
u8 rtl8821ae_phy_sw_chnl(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw,
|
||||
bool b_recovery);
|
||||
void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw *hw,
|
||||
bool b_recovery);
|
||||
void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
|
||||
void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
|
||||
bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
|
||||
enum radio_path rfpath);
|
||||
bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
|
||||
enum radio_path rfpath);
|
||||
bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
|
||||
bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
|
||||
enum rf_pwrstate rfpwr_state);
|
||||
u8 _rtl8812ae_get_right_chnl_place_for_iqk(u8 chnl);
|
||||
void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
|
||||
u8 channel, u8 path);
|
||||
void rtl8812ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
|
||||
u8 thermal_value, u8 threshold);
|
||||
void rtl8821ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
|
||||
u8 thermal_value, u8 threshold);
|
||||
void rtl8821ae_reset_iqk_result(struct ieee80211_hw *hw);
|
||||
u32 phy_get_tx_swing_8812A(struct ieee80211_hw *hw, u8 band, u8 rf_path);
|
||||
|
||||
#endif
|
||||
182
drivers/net/wireless/rtlwifi/rtl8821ae/pwrseq.c
Normal file
182
drivers/net/wireless/rtlwifi/rtl8821ae/pwrseq.c
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2010 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "../pwrseqcmd.h"
|
||||
#include "pwrseq.h"
|
||||
|
||||
/* drivers should parse below arrays and do the corresponding actions */
|
||||
/* 3 Power on Array */
|
||||
struct wlan_pwr_cfg rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS +
|
||||
RTL8812_TRANS_END_STEPS] = {
|
||||
RTL8812_TRANS_CARDEMU_TO_ACT
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
/* 3Radio off GPIO Array */
|
||||
struct wlan_pwr_cfg rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8812_TRANS_END_STEPS] = {
|
||||
RTL8812_TRANS_ACT_TO_CARDEMU
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
/* 3Card Disable Array */
|
||||
struct wlan_pwr_cfg rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS
|
||||
+ RTL8812_TRANS_CARDEMU_TO_PDN_STEPS
|
||||
+ RTL8812_TRANS_END_STEPS] = {
|
||||
RTL8812_TRANS_ACT_TO_CARDEMU
|
||||
RTL8812_TRANS_CARDEMU_TO_CARDDIS
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Card Enable Array */
|
||||
struct wlan_pwr_cfg rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS
|
||||
+ RTL8812_TRANS_CARDEMU_TO_PDN_STEPS
|
||||
+ RTL8812_TRANS_END_STEPS] = {
|
||||
RTL8812_TRANS_CARDDIS_TO_CARDEMU
|
||||
RTL8812_TRANS_CARDEMU_TO_ACT
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
/* 3Suspend Array */
|
||||
struct wlan_pwr_cfg rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8812_TRANS_CARDEMU_TO_SUS_STEPS +
|
||||
RTL8812_TRANS_END_STEPS] = {
|
||||
RTL8812_TRANS_ACT_TO_CARDEMU
|
||||
RTL8812_TRANS_CARDEMU_TO_SUS
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Resume Array */
|
||||
struct wlan_pwr_cfg rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8812_TRANS_CARDEMU_TO_SUS_STEPS +
|
||||
RTL8812_TRANS_END_STEPS] = {
|
||||
RTL8812_TRANS_SUS_TO_CARDEMU
|
||||
RTL8812_TRANS_CARDEMU_TO_ACT
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
/* 3HWPDN Array */
|
||||
struct wlan_pwr_cfg rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
|
||||
RTL8812_TRANS_END_STEPS] = {
|
||||
RTL8812_TRANS_ACT_TO_CARDEMU
|
||||
RTL8812_TRANS_CARDEMU_TO_PDN
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Enter LPS */
|
||||
struct wlan_pwr_cfg rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS +
|
||||
RTL8812_TRANS_END_STEPS] = {
|
||||
/* FW behavior */
|
||||
RTL8812_TRANS_ACT_TO_LPS
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Leave LPS */
|
||||
struct wlan_pwr_cfg rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS +
|
||||
RTL8812_TRANS_END_STEPS] = {
|
||||
/* FW behavior */
|
||||
RTL8812_TRANS_LPS_TO_ACT
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
/* drivers should parse below arrays and do the corresponding actions */
|
||||
/*3 Power on Array*/
|
||||
struct wlan_pwr_cfg rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS
|
||||
+ RTL8821A_TRANS_END_STEPS] = {
|
||||
RTL8821A_TRANS_CARDEMU_TO_ACT
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
|
||||
/*3Radio off GPIO Array */
|
||||
struct wlan_pwr_cfg rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
|
||||
+ RTL8821A_TRANS_END_STEPS] = {
|
||||
RTL8821A_TRANS_ACT_TO_CARDEMU
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
|
||||
/*3Card Disable Array*/
|
||||
struct wlan_pwr_cfg rtl8821A_card_disable_flow
|
||||
[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
|
||||
+ RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS
|
||||
+ RTL8821A_TRANS_END_STEPS] = {
|
||||
RTL8821A_TRANS_ACT_TO_CARDEMU
|
||||
RTL8821A_TRANS_CARDEMU_TO_CARDDIS
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
|
||||
/*3 Card Enable Array*/
|
||||
/*RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS*/
|
||||
struct wlan_pwr_cfg rtl8821A_card_enable_flow
|
||||
[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
|
||||
+ RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS
|
||||
+ RTL8821A_TRANS_END_STEPS] = {
|
||||
RTL8821A_TRANS_CARDDIS_TO_CARDEMU
|
||||
RTL8821A_TRANS_CARDEMU_TO_ACT
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
|
||||
/*3Suspend Array*/
|
||||
struct wlan_pwr_cfg rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
|
||||
+ RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS
|
||||
+ RTL8821A_TRANS_END_STEPS] = {
|
||||
RTL8821A_TRANS_ACT_TO_CARDEMU
|
||||
RTL8821A_TRANS_CARDEMU_TO_SUS
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
|
||||
/*3 Resume Array*/
|
||||
struct wlan_pwr_cfg rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
|
||||
+ RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS
|
||||
+ RTL8821A_TRANS_END_STEPS] = {
|
||||
RTL8821A_TRANS_SUS_TO_CARDEMU
|
||||
RTL8821A_TRANS_CARDEMU_TO_ACT
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
|
||||
/*3HWPDN Array*/
|
||||
struct wlan_pwr_cfg rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
|
||||
+ RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS
|
||||
+ RTL8821A_TRANS_END_STEPS] = {
|
||||
RTL8821A_TRANS_ACT_TO_CARDEMU
|
||||
RTL8821A_TRANS_CARDEMU_TO_PDN
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
|
||||
/*3 Enter LPS */
|
||||
struct wlan_pwr_cfg rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS
|
||||
+ RTL8821A_TRANS_END_STEPS] = {
|
||||
/*FW behavior*/
|
||||
RTL8821A_TRANS_ACT_TO_LPS
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
|
||||
/*3 Leave LPS */
|
||||
struct wlan_pwr_cfg rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS
|
||||
+ RTL8821A_TRANS_END_STEPS] = {
|
||||
/*FW behavior*/
|
||||
RTL8821A_TRANS_LPS_TO_ACT
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
738
drivers/net/wireless/rtlwifi/rtl8821ae/pwrseq.h
Normal file
738
drivers/net/wireless/rtlwifi/rtl8821ae/pwrseq.h
Normal file
|
|
@ -0,0 +1,738 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2010 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL8821AE_PWRSEQ_H__
|
||||
#define __RTL8821AE_PWRSEQ_H__
|
||||
|
||||
#include "../pwrseqcmd.h"
|
||||
#include "../btcoexist/halbt_precomp.h"
|
||||
|
||||
#define RTL8812_TRANS_CARDEMU_TO_ACT_STEPS 15
|
||||
#define RTL8812_TRANS_ACT_TO_CARDEMU_STEPS 15
|
||||
#define RTL8812_TRANS_CARDEMU_TO_SUS_STEPS 15
|
||||
#define RTL8812_TRANS_SUS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8812_TRANS_CARDEMU_TO_PDN_STEPS 25
|
||||
#define RTL8812_TRANS_PDN_TO_CARDEMU_STEPS 15
|
||||
#define RTL8812_TRANS_ACT_TO_LPS_STEPS 15
|
||||
#define RTL8812_TRANS_LPS_TO_ACT_STEPS 15
|
||||
#define RTL8812_TRANS_END_STEPS 1
|
||||
|
||||
/* The following macros have the following format:
|
||||
* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value
|
||||
* comments },
|
||||
*/
|
||||
#define RTL8812_TRANS_CARDEMU_TO_ACT \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
|
||||
/* disable SW LPS 0x04[10]=0*/}, \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
|
||||
/* wait till 0x04[17] = 1 power ready*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
|
||||
/* disable HWPDN 0x04[15]=0*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
|
||||
/* disable WL suspend*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
|
||||
/* polling until return 0*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
|
||||
|
||||
#define RTL8812_TRANS_ACT_TO_CARDEMU \
|
||||
{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
|
||||
/* 0xc00[7:0] = 4 turn off 3-wire */}, \
|
||||
{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
|
||||
/* 0xe00[7:0] = 4 turn off 3-wire */}, \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
|
||||
/* 0x2[0] = 0 RESET BB, CLOSE RF */}, \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
|
||||
/*Delay 1us*/}, \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
|
||||
/* Whole BB is reset*/}, \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A \
|
||||
/* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/}, \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
|
||||
/*0x8[1] = 0 ANA clk =500k */}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
|
||||
/*0x04[9] = 1 turn off MAC by HW state machine*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
|
||||
/*wait till 0x04[9] = 0 polling until return 0 to disable*/},
|
||||
|
||||
#define RTL8812_TRANS_CARDEMU_TO_SUS \
|
||||
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc}, \
|
||||
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC}, \
|
||||
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07 \
|
||||
/* gpio11 input mode, gpio10~8 output mode */}, \
|
||||
{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
|
||||
/* gpio 0~7 output same value as input ?? */}, \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff \
|
||||
/* gpio0~7 output mode */}, \
|
||||
{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
|
||||
/* 0x47[7:0] = 00 gpio mode */}, \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
|
||||
/* suspend option all off */}, \
|
||||
{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
|
||||
/*0x14[7] = 1 turn on ZCD */}, \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
|
||||
/* 0x15[0] =1 trun on ZCD */}, \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
|
||||
/*0x23[4] = 1 hpon LDO sleep mode */}, \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
|
||||
/*0x8[1] = 0 ANA clk =500k */}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
|
||||
/*0x04[11] = 2b'11 enable WL suspend for PCIe*/},
|
||||
|
||||
#define RTL8812_TRANS_SUS_TO_CARDEMU \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
|
||||
/*0x04[11] = 2b'01enable WL suspend*/}, \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0 \
|
||||
/*0x23[4] = 0 hpon LDO sleep mode leave */}, \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
|
||||
/* 0x15[0] =0 trun off ZCD */}, \
|
||||
{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0 \
|
||||
/*0x14[7] = 0 turn off ZCD */}, \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
|
||||
/* gpio0~7 input mode */}, \
|
||||
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
|
||||
/* gpio11 input mode, gpio10~8 input mode */},
|
||||
|
||||
#define RTL8812_TRANS_CARDEMU_TO_CARDDIS \
|
||||
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
|
||||
/*0x03[2] = 0, reset 8051*/}, \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05 \
|
||||
/*0x80=05h if reload fw, fill the default value of host_CPU handshake field*/}, \
|
||||
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc}, \
|
||||
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC}, \
|
||||
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07 \
|
||||
/* gpio11 input mode, gpio10~8 output mode */}, \
|
||||
{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
|
||||
/* gpio 0~7 output same value as input ?? */}, \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff \
|
||||
/* gpio0~7 output mode */}, \
|
||||
{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
|
||||
/* 0x47[7:0] = 00 gpio mode */}, \
|
||||
{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
|
||||
/*0x14[7] = 1 turn on ZCD */}, \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
|
||||
/* 0x15[0] =1 trun on ZCD */}, \
|
||||
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
|
||||
/*0x12[0] = 0 force PFM mode */}, \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
|
||||
/*0x23[4] = 1 hpon LDO sleep mode */}, \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
|
||||
/*0x8[1] = 0 ANA clk =500k */}, \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
|
||||
/*0x07=0x20 , SOP option to disable BG/MB*/}, \
|
||||
{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
|
||||
/*0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8812 */}, \
|
||||
{0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
|
||||
/*0x076[1]=0 , disable RFC_1 control REG_OPT_CTRL_8812 +2 */}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
|
||||
/*0x04[11] = 2b'01 enable WL suspend*/},
|
||||
|
||||
#define RTL8812_TRANS_CARDDIS_TO_CARDEMU \
|
||||
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
|
||||
/*0x12[0] = 1 force PWM mode */}, \
|
||||
{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0 \
|
||||
/*0x14[7] = 0 turn off ZCD */}, \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
|
||||
/* 0x15[0] =0 trun off ZCD */}, \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0 \
|
||||
/*0x23[4] = 0 hpon LDO leave sleep mode */}, \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
|
||||
/* gpio0~7 input mode */}, \
|
||||
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
|
||||
/* gpio11 input mode, gpio10~8 input mode */}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
|
||||
/*0x04[10] = 0, enable SW LPS PCIE only*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
|
||||
/*0x04[11] = 2b'01enable WL suspend*/}, \
|
||||
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
|
||||
/*0x03[2] = 1, enable 8051*/}, \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
|
||||
/*PCIe DMA start*/},
|
||||
|
||||
#define RTL8812_TRANS_CARDEMU_TO_PDN \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
|
||||
/* 0x04[15] = 1*/},
|
||||
|
||||
#define RTL8812_TRANS_PDN_TO_CARDEMU \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
|
||||
/* 0x04[15] = 0*/},
|
||||
|
||||
#define RTL8812_TRANS_ACT_TO_LPS \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
|
||||
/*PCIe DMA stop*/}, \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F \
|
||||
/*Tx Pause*/}, \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
|
||||
/*Should be zero if no packet is transmitting*/}, \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
|
||||
/*Should be zero if no packet is transmitting*/}, \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
|
||||
/*Should be zero if no packet is transmitting*/}, \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
|
||||
/*Should be zero if no packet is transmitting*/}, \
|
||||
{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
|
||||
/* 0xc00[7:0] = 4 turn off 3-wire */}, \
|
||||
{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
|
||||
/* 0xe00[7:0] = 4 turn off 3-wire */}, \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
|
||||
/*CCK and OFDM are disabled,and clock are gated,and RF closed*/}, \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
|
||||
/*Delay 1us*/}, \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
|
||||
/* Whole BB is reset*/}, \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03 \
|
||||
/*Reset MAC TRX*/}, \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
|
||||
/*check if removed later*/}, \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
|
||||
/*Respond TxOK to scheduler*/},
|
||||
|
||||
#define RTL8812_TRANS_LPS_TO_ACT \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
|
||||
/*SDIO RPWM*/}, \
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
|
||||
/*USB RPWM*/}, \
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
|
||||
/*PCIe RPWM*/}, \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \
|
||||
/*Delay*/}, \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
|
||||
/*. 0x08[4] = 0 switch TSF to 40M*/}, \
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
|
||||
/*Polling 0x109[7]=0 TSF in 40M*/}, \
|
||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
|
||||
/*. 0x29[7:6] = 2b'00 enable BB clock*/}, \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
|
||||
/*. 0x101[1] = 1*/}, \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
|
||||
/*. 0x100[7:0] = 0xFF enable WMAC TRX*/}, \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
|
||||
/*. 0x02[1:0] = 2b'11 enable BB macro*/}, \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
|
||||
/*. 0x522 = 0*/},
|
||||
|
||||
#define RTL8812_TRANS_END \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
0, PWR_CMD_END, 0, 0},
|
||||
|
||||
extern struct wlan_pwr_cfg rtl8812_power_on_flow
|
||||
[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS +
|
||||
RTL8812_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8812_radio_off_flow
|
||||
[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8812_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8812_card_disable_flow
|
||||
[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
|
||||
RTL8812_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8812_card_enable_flow
|
||||
[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
|
||||
RTL8812_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8812_suspend_flow
|
||||
[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8812_TRANS_CARDEMU_TO_SUS_STEPS +
|
||||
RTL8812_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8812_resume_flow
|
||||
[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8812_TRANS_CARDEMU_TO_SUS_STEPS +
|
||||
RTL8812_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8812_hwpdn_flow
|
||||
[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
|
||||
RTL8812_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8812_enter_lps_flow
|
||||
[RTL8812_TRANS_ACT_TO_LPS_STEPS +
|
||||
RTL8812_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8812_leave_lps_flow
|
||||
[RTL8812_TRANS_LPS_TO_ACT_STEPS +
|
||||
RTL8812_TRANS_END_STEPS];
|
||||
|
||||
/* Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd
|
||||
* There are 6 HW Power States:
|
||||
* 0: POFF--Power Off
|
||||
* 1: PDN--Power Down
|
||||
* 2: CARDEMU--Card Emulation
|
||||
* 3: ACT--Active Mode
|
||||
* 4: LPS--Low Power State
|
||||
* 5: SUS--Suspend
|
||||
*
|
||||
* The transision from different states are defined below
|
||||
* TRANS_CARDEMU_TO_ACT
|
||||
* TRANS_ACT_TO_CARDEMU
|
||||
* TRANS_CARDEMU_TO_SUS
|
||||
* TRANS_SUS_TO_CARDEMU
|
||||
* TRANS_CARDEMU_TO_PDN
|
||||
* TRANS_ACT_TO_LPS
|
||||
* TRANS_LPS_TO_ACT
|
||||
*
|
||||
* TRANS_END
|
||||
*/
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS 25
|
||||
#define RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS 15
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS 15
|
||||
#define RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS 15
|
||||
#define RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS 15
|
||||
#define RTL8821A_TRANS_ACT_TO_LPS_STEPS 15
|
||||
#define RTL8821A_TRANS_LPS_TO_ACT_STEPS 15
|
||||
#define RTL8821A_TRANS_END_STEPS 1
|
||||
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_ACT \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
|
||||
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
|
||||
/*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/}, \
|
||||
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
|
||||
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
|
||||
/*0x67[0] = 0 to disable BT_GPS_SEL pins*/}, \
|
||||
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
|
||||
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS \
|
||||
/*Delay 1ms*/}, \
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
|
||||
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \
|
||||
/*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
|
||||
/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/}, \
|
||||
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \
|
||||
/* Disable USB suspend */}, \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
|
||||
/* wait till 0x04[17] = 1 power ready*/}, \
|
||||
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0 \
|
||||
/* Enable USB suspend */}, \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
|
||||
/* release WLON reset 0x04[16]=1*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
|
||||
/* disable HWPDN 0x04[15]=0*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \
|
||||
/* disable WL suspend*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
|
||||
/* polling until return 0*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0 \
|
||||
/**/}, \
|
||||
{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
|
||||
/*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */},\
|
||||
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
|
||||
/*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A \
|
||||
from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */},\
|
||||
{0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \
|
||||
/*anapar_mac<118> , 0x25[6]=0 by wlan single function*/},\
|
||||
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
|
||||
/*Enable falling edge triggering interrupt*/},\
|
||||
{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
|
||||
/*Enable GPIO9 interrupt mode*/},\
|
||||
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
|
||||
/*Enable GPIO9 input mode*/},\
|
||||
{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
|
||||
/*Enable HSISR GPIO[C:0] interrupt*/},\
|
||||
{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
|
||||
/*Enable HSISR GPIO9 interrupt*/},\
|
||||
{0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A \
|
||||
/*0x7A = 0x3A start BT*/},\
|
||||
{0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82 \
|
||||
/* 0x2C[23:12]=0x820 ; XTAL trim */}, \
|
||||
{0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 \
|
||||
/* 0x10[6]=1 */},
|
||||
|
||||
#define RTL8821A_TRANS_ACT_TO_CARDEMU \
|
||||
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
|
||||
/*0x1F[7:0] = 0 turn off RF*/}, \
|
||||
{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
|
||||
/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from \
|
||||
register 0x65[2] */},\
|
||||
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
|
||||
/*Enable rising edge triggering interrupt*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
|
||||
/*0x04[9] = 1 turn off MAC by HW state machine*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
|
||||
/*wait till 0x04[9] = 0 polling until return 0 to disable*/}, \
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
|
||||
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
|
||||
/*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/}, \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
|
||||
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
|
||||
/*0x20[0] = 1b'0 disable LDOA12 MACRO block*/},
|
||||
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_SUS \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
|
||||
/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
|
||||
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
|
||||
/*0x04[12:11] = 2b'01 enable WL suspend*/}, \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
|
||||
/*0x23[4] = 1b'1 12H LDO enter sleep mode*/}, \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
|
||||
/*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
|
||||
/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/}, \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
|
||||
/*Set SDIO suspend local register*/}, \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
|
||||
/*wait power state to suspend*/},
|
||||
|
||||
#define RTL8821A_TRANS_SUS_TO_CARDEMU \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
|
||||
/*clear suspend enable and power down enable*/}, \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
|
||||
/*Set SDIO suspend local register*/}, \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
|
||||
/*wait power state to suspend*/},\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
|
||||
/*0x23[4] = 1b'0 12H LDO enter normal mode*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
|
||||
/*0x04[12:11] = 2b'01enable WL suspend*/},
|
||||
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
|
||||
/*0x07=0x20 , SOP option to disable BG/MB*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
|
||||
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
|
||||
/*0x04[12:11] = 2b'01 enable WL suspend*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
|
||||
/*0x04[10] = 1, enable SW LPS*/}, \
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1 \
|
||||
/*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/}, \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
|
||||
/*0x23[4] = 1b'1 12H LDO enter sleep mode*/}, \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
|
||||
/*Set SDIO suspend local register*/}, \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
|
||||
/*wait power state to suspend*/},
|
||||
|
||||
#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
|
||||
/*clear suspend enable and power down enable*/}, \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
|
||||
/*Set SDIO suspend local register*/}, \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
|
||||
/*wait power state to suspend*/},\
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
|
||||
/*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
|
||||
/*0x04[12:11] = 2b'01enable WL suspend*/},\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
|
||||
/*0x23[4] = 1b'0 12H LDO enter normal mode*/}, \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
|
||||
/*PCIe DMA start*/},
|
||||
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_PDN \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
|
||||
/*0x23[4] = 1b'1 12H LDO enter sleep mode*/}, \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
|
||||
PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
|
||||
/*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/}, \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
|
||||
/* 0x04[16] = 0*/},\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
|
||||
/* 0x04[15] = 1*/},
|
||||
|
||||
#define RTL8821A_TRANS_PDN_TO_CARDEMU \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
|
||||
/* 0x04[15] = 0*/},
|
||||
|
||||
#define RTL8821A_TRANS_ACT_TO_LPS \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
|
||||
/*PCIe DMA stop*/}, \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
|
||||
/*Tx Pause*/}, \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
|
||||
/*Should be zero if no packet is transmitting*/}, \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
|
||||
/*Should be zero if no packet is transmitting*/}, \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
|
||||
/*Should be zero if no packet is transmitting*/}, \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
|
||||
/*Should be zero if no packet is transmitting*/}, \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
|
||||
/*CCK and OFDM are disabled,and clock are gated*/}, \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
|
||||
/*Delay 1us*/}, \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
|
||||
/*Whole BB is reset*/}, \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03 \
|
||||
/*Reset MAC TRX*/}, \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
|
||||
/*check if removed later*/}, \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
|
||||
/*When driver enter Sus/ Disable, enable LOP for BT*/}, \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
|
||||
/*Respond TxOK to scheduler*/},
|
||||
|
||||
#define RTL8821A_TRANS_LPS_TO_ACT \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
|
||||
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
|
||||
/*SDIO RPWM*/},\
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
|
||||
/*USB RPWM*/},\
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
|
||||
/*PCIe RPWM*/},\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \
|
||||
/*Delay*/},\
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
|
||||
/*. 0x08[4] = 0 switch TSF to 40M*/},\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
|
||||
/*Polling 0x109[7]=0 TSF in 40M*/},\
|
||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
|
||||
/*. 0x29[7:6] = 2b'00 enable BB clock*/},\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
|
||||
/*. 0x101[1] = 1*/},\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
|
||||
/*. 0x100[7:0] = 0xFF enable WMAC TRX*/},\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
|
||||
/*. 0x02[1:0] = 2b'11 enable BB macro*/},\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
|
||||
/*. 0x522 = 0*/},
|
||||
|
||||
#define RTL8821A_TRANS_END \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
||||
0, PWR_CMD_END, 0, 0},
|
||||
|
||||
extern struct wlan_pwr_cfg rtl8821A_power_on_flow
|
||||
[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS +
|
||||
RTL8821A_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8821A_radio_off_flow
|
||||
[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8821A_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8821A_card_disable_flow
|
||||
[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS +
|
||||
RTL8821A_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8821A_card_enable_flow
|
||||
[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS +
|
||||
RTL8821A_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8821A_suspend_flow
|
||||
[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS +
|
||||
RTL8821A_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8821A_resume_flow
|
||||
[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS +
|
||||
RTL8821A_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8821A_hwpdn_flow
|
||||
[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS +
|
||||
RTL8821A_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8821A_enter_lps_flow
|
||||
[RTL8821A_TRANS_ACT_TO_LPS_STEPS +
|
||||
RTL8821A_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8821A_leave_lps_flow
|
||||
[RTL8821A_TRANS_LPS_TO_ACT_STEPS +
|
||||
RTL8821A_TRANS_END_STEPS];
|
||||
|
||||
/*RTL8812 Power Configuration CMDs for PCIe interface*/
|
||||
#define RTL8812_NIC_PWR_ON_FLOW rtl8812_power_on_flow
|
||||
#define RTL8812_NIC_RF_OFF_FLOW rtl8812_radio_off_flow
|
||||
#define RTL8812_NIC_DISABLE_FLOW rtl8812_card_disable_flow
|
||||
#define RTL8812_NIC_ENABLE_FLOW rtl8812_card_enable_flow
|
||||
#define RTL8812_NIC_SUSPEND_FLOW rtl8812_suspend_flow
|
||||
#define RTL8812_NIC_RESUME_FLOW rtl8812_resume_flow
|
||||
#define RTL8812_NIC_PDN_FLOW rtl8812_hwpdn_flow
|
||||
#define RTL8812_NIC_LPS_ENTER_FLOW rtl8812_enter_lps_flow
|
||||
#define RTL8812_NIC_LPS_LEAVE_FLOW rtl8812_leave_lps_flow
|
||||
|
||||
/* RTL8821 Power Configuration CMDs for PCIe interface */
|
||||
#define RTL8821A_NIC_PWR_ON_FLOW rtl8821A_power_on_flow
|
||||
#define RTL8821A_NIC_RF_OFF_FLOW rtl8821A_radio_off_flow
|
||||
#define RTL8821A_NIC_DISABLE_FLOW rtl8821A_card_disable_flow
|
||||
#define RTL8821A_NIC_ENABLE_FLOW rtl8821A_card_enable_flow
|
||||
#define RTL8821A_NIC_SUSPEND_FLOW rtl8821A_suspend_flow
|
||||
#define RTL8821A_NIC_RESUME_FLOW rtl8821A_resume_flow
|
||||
#define RTL8821A_NIC_PDN_FLOW rtl8821A_hwpdn_flow
|
||||
#define RTL8821A_NIC_LPS_ENTER_FLOW rtl8821A_enter_lps_flow
|
||||
#define RTL8821A_NIC_LPS_LEAVE_FLOW rtl8821A_leave_lps_flow
|
||||
|
||||
#endif
|
||||
2464
drivers/net/wireless/rtlwifi/rtl8821ae/reg.h
Normal file
2464
drivers/net/wireless/rtlwifi/rtl8821ae/reg.h
Normal file
File diff suppressed because it is too large
Load diff
465
drivers/net/wireless/rtlwifi/rtl8821ae/rf.c
Normal file
465
drivers/net/wireless/rtlwifi/rtl8821ae/rf.c
Normal file
|
|
@ -0,0 +1,465 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2010 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "../wifi.h"
|
||||
#include "reg.h"
|
||||
#include "def.h"
|
||||
#include "phy.h"
|
||||
#include "rf.h"
|
||||
#include "dm.h"
|
||||
|
||||
static bool _rtl8821ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
|
||||
|
||||
void rtl8821ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
|
||||
switch (bandwidth) {
|
||||
case HT_CHANNEL_WIDTH_20:
|
||||
rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 3);
|
||||
rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 3);
|
||||
break;
|
||||
case HT_CHANNEL_WIDTH_20_40:
|
||||
rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 1);
|
||||
rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 1);
|
||||
break;
|
||||
case HT_CHANNEL_WIDTH_80:
|
||||
rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 0);
|
||||
rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 0);
|
||||
break;
|
||||
default:
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
|
||||
"unknown bandwidth: %#X\n", bandwidth);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rtl8821ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
|
||||
u8 *ppowerlevel)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_phy *rtlphy = &rtlpriv->phy;
|
||||
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
|
||||
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
|
||||
u32 tx_agc[2] = {0, 0}, tmpval;
|
||||
bool turbo_scanoff = false;
|
||||
u8 idx1, idx2;
|
||||
u8 *ptr;
|
||||
u8 direction;
|
||||
u32 pwrtrac_value;
|
||||
|
||||
if (rtlefuse->eeprom_regulatory != 0)
|
||||
turbo_scanoff = true;
|
||||
|
||||
if (mac->act_scanning) {
|
||||
tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
|
||||
tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
|
||||
|
||||
if (turbo_scanoff) {
|
||||
for (idx1 = RF90_PATH_A;
|
||||
idx1 <= RF90_PATH_B;
|
||||
idx1++) {
|
||||
tx_agc[idx1] = ppowerlevel[idx1] |
|
||||
(ppowerlevel[idx1] << 8) |
|
||||
(ppowerlevel[idx1] << 16) |
|
||||
(ppowerlevel[idx1] << 24);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
|
||||
tx_agc[idx1] = ppowerlevel[idx1] |
|
||||
(ppowerlevel[idx1] << 8) |
|
||||
(ppowerlevel[idx1] << 16) |
|
||||
(ppowerlevel[idx1] << 24);
|
||||
}
|
||||
|
||||
if (rtlefuse->eeprom_regulatory == 0) {
|
||||
tmpval =
|
||||
(rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
|
||||
(rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
|
||||
8);
|
||||
tx_agc[RF90_PATH_A] += tmpval;
|
||||
|
||||
tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
|
||||
(rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
|
||||
24);
|
||||
tx_agc[RF90_PATH_B] += tmpval;
|
||||
}
|
||||
}
|
||||
|
||||
for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
|
||||
ptr = (u8 *)(&tx_agc[idx1]);
|
||||
for (idx2 = 0; idx2 < 4; idx2++) {
|
||||
if (*ptr > RF6052_MAX_TX_PWR)
|
||||
*ptr = RF6052_MAX_TX_PWR;
|
||||
ptr++;
|
||||
}
|
||||
}
|
||||
rtl8821ae_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
|
||||
if (direction == 1) {
|
||||
tx_agc[0] += pwrtrac_value;
|
||||
tx_agc[1] += pwrtrac_value;
|
||||
} else if (direction == 2) {
|
||||
tx_agc[0] -= pwrtrac_value;
|
||||
tx_agc[1] -= pwrtrac_value;
|
||||
}
|
||||
tmpval = tx_agc[RF90_PATH_A];
|
||||
rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, MASKDWORD, tmpval);
|
||||
|
||||
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
|
||||
"CCK PWR 1~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
|
||||
RTXAGC_A_CCK11_CCK1);
|
||||
|
||||
tmpval = tx_agc[RF90_PATH_B];
|
||||
rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, MASKDWORD, tmpval);
|
||||
|
||||
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
|
||||
"CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
|
||||
RTXAGC_B_CCK11_CCK1);
|
||||
}
|
||||
|
||||
static void rtl8821ae_phy_get_power_base(struct ieee80211_hw *hw,
|
||||
u8 *ppowerlevel_ofdm,
|
||||
u8 *ppowerlevel_bw20,
|
||||
u8 *ppowerlevel_bw40, u8 channel,
|
||||
u32 *ofdmbase, u32 *mcsbase)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_phy *rtlphy = &rtlpriv->phy;
|
||||
u32 powerbase0, powerbase1;
|
||||
u8 i, powerlevel[2];
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
powerbase0 = ppowerlevel_ofdm[i];
|
||||
|
||||
powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
|
||||
(powerbase0 << 8) | powerbase0;
|
||||
*(ofdmbase + i) = powerbase0;
|
||||
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
|
||||
" [OFDM power base index rf(%c) = 0x%x]\n",
|
||||
((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
|
||||
}
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
|
||||
powerlevel[i] = ppowerlevel_bw20[i];
|
||||
else
|
||||
powerlevel[i] = ppowerlevel_bw40[i];
|
||||
|
||||
powerbase1 = powerlevel[i];
|
||||
powerbase1 = (powerbase1 << 24) |
|
||||
(powerbase1 << 16) | (powerbase1 << 8) | powerbase1;
|
||||
|
||||
*(mcsbase + i) = powerbase1;
|
||||
|
||||
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
|
||||
" [MCS power base index rf(%c) = 0x%x]\n",
|
||||
((i == 0) ? 'A' : 'B'), *(mcsbase + i));
|
||||
}
|
||||
}
|
||||
|
||||
static void get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
|
||||
u8 channel, u8 index,
|
||||
u32 *powerbase0,
|
||||
u32 *powerbase1,
|
||||
u32 *p_outwriteval)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_phy *rtlphy = &rtlpriv->phy;
|
||||
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
|
||||
u8 i, chnlgroup = 0, pwr_diff_limit[4], pwr_diff = 0, customer_pwr_diff;
|
||||
u32 writeval, customer_limit, rf;
|
||||
|
||||
for (rf = 0; rf < 2; rf++) {
|
||||
switch (rtlefuse->eeprom_regulatory) {
|
||||
case 0:
|
||||
chnlgroup = 0;
|
||||
|
||||
writeval =
|
||||
rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
|
||||
(rf ? 8 : 0)]
|
||||
+ ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
|
||||
|
||||
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
|
||||
"RTK better performance, writeval(%c) = 0x%x\n",
|
||||
((rf == 0) ? 'A' : 'B'), writeval);
|
||||
break;
|
||||
case 1:
|
||||
if (rtlphy->pwrgroup_cnt == 1) {
|
||||
chnlgroup = 0;
|
||||
} else {
|
||||
if (channel < 3)
|
||||
chnlgroup = 0;
|
||||
else if (channel < 6)
|
||||
chnlgroup = 1;
|
||||
else if (channel < 9)
|
||||
chnlgroup = 2;
|
||||
else if (channel < 12)
|
||||
chnlgroup = 3;
|
||||
else if (channel < 14)
|
||||
chnlgroup = 4;
|
||||
else if (channel == 14)
|
||||
chnlgroup = 5;
|
||||
}
|
||||
|
||||
writeval =
|
||||
rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
|
||||
[index + (rf ? 8 : 0)] + ((index < 2) ?
|
||||
powerbase0[rf] :
|
||||
powerbase1[rf]);
|
||||
|
||||
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
|
||||
"Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
|
||||
((rf == 0) ? 'A' : 'B'), writeval);
|
||||
|
||||
break;
|
||||
case 2:
|
||||
writeval =
|
||||
((index < 2) ? powerbase0[rf] : powerbase1[rf]);
|
||||
|
||||
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
|
||||
"Better regulatory, writeval(%c) = 0x%x\n",
|
||||
((rf == 0) ? 'A' : 'B'), writeval);
|
||||
break;
|
||||
case 3:
|
||||
chnlgroup = 0;
|
||||
|
||||
if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
|
||||
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
|
||||
"customer's limit, 40MHz rf(%c) = 0x%x\n",
|
||||
((rf == 0) ? 'A' : 'B'),
|
||||
rtlefuse->pwrgroup_ht40[rf][channel -
|
||||
1]);
|
||||
} else {
|
||||
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
|
||||
"customer's limit, 20MHz rf(%c) = 0x%x\n",
|
||||
((rf == 0) ? 'A' : 'B'),
|
||||
rtlefuse->pwrgroup_ht20[rf][channel -
|
||||
1]);
|
||||
}
|
||||
|
||||
if (index < 2)
|
||||
pwr_diff = rtlefuse->txpwr_legacyhtdiff[rf][channel-1];
|
||||
else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
|
||||
pwr_diff =
|
||||
rtlefuse->txpwr_ht20diff[rf][channel-1];
|
||||
|
||||
if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40)
|
||||
customer_pwr_diff =
|
||||
rtlefuse->pwrgroup_ht40[rf][channel-1];
|
||||
else
|
||||
customer_pwr_diff =
|
||||
rtlefuse->pwrgroup_ht20[rf][channel-1];
|
||||
|
||||
if (pwr_diff > customer_pwr_diff)
|
||||
pwr_diff = 0;
|
||||
else
|
||||
pwr_diff = customer_pwr_diff - pwr_diff;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
pwr_diff_limit[i] =
|
||||
(u8)((rtlphy->mcs_txpwrlevel_origoffset
|
||||
[chnlgroup][index + (rf ? 8 : 0)] &
|
||||
(0x7f << (i * 8))) >> (i * 8));
|
||||
|
||||
if (pwr_diff_limit[i] > pwr_diff)
|
||||
pwr_diff_limit[i] = pwr_diff;
|
||||
}
|
||||
|
||||
customer_limit = (pwr_diff_limit[3] << 24) |
|
||||
(pwr_diff_limit[2] << 16) |
|
||||
(pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
|
||||
|
||||
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
|
||||
"Customer's limit rf(%c) = 0x%x\n",
|
||||
((rf == 0) ? 'A' : 'B'), customer_limit);
|
||||
|
||||
writeval = customer_limit +
|
||||
((index < 2) ? powerbase0[rf] : powerbase1[rf]);
|
||||
|
||||
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
|
||||
"Customer, writeval rf(%c)= 0x%x\n",
|
||||
((rf == 0) ? 'A' : 'B'), writeval);
|
||||
break;
|
||||
default:
|
||||
chnlgroup = 0;
|
||||
writeval =
|
||||
rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
|
||||
[index + (rf ? 8 : 0)]
|
||||
+ ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
|
||||
|
||||
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
|
||||
"RTK better performance, writeval rf(%c) = 0x%x\n",
|
||||
((rf == 0) ? 'A' : 'B'), writeval);
|
||||
break;
|
||||
}
|
||||
|
||||
if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
|
||||
writeval = writeval - 0x06060606;
|
||||
else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
|
||||
TXHIGHPWRLEVEL_BT2)
|
||||
writeval = writeval - 0x0c0c0c0c;
|
||||
*(p_outwriteval + rf) = writeval;
|
||||
}
|
||||
}
|
||||
|
||||
static void _rtl8821ae_write_ofdm_power_reg(struct ieee80211_hw *hw,
|
||||
u8 index, u32 *pvalue)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
u16 regoffset_a[6] = {
|
||||
RTXAGC_A_OFDM18_OFDM6, RTXAGC_A_OFDM54_OFDM24,
|
||||
RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
|
||||
RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
|
||||
};
|
||||
u16 regoffset_b[6] = {
|
||||
RTXAGC_B_OFDM18_OFDM6, RTXAGC_B_OFDM54_OFDM24,
|
||||
RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
|
||||
RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
|
||||
};
|
||||
u8 i, rf, pwr_val[4];
|
||||
u32 writeval;
|
||||
u16 regoffset;
|
||||
|
||||
for (rf = 0; rf < 2; rf++) {
|
||||
writeval = pvalue[rf];
|
||||
for (i = 0; i < 4; i++) {
|
||||
pwr_val[i] = (u8)((writeval & (0x7f <<
|
||||
(i * 8))) >> (i * 8));
|
||||
|
||||
if (pwr_val[i] > RF6052_MAX_TX_PWR)
|
||||
pwr_val[i] = RF6052_MAX_TX_PWR;
|
||||
}
|
||||
writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
|
||||
(pwr_val[1] << 8) | pwr_val[0];
|
||||
|
||||
if (rf == 0)
|
||||
regoffset = regoffset_a[index];
|
||||
else
|
||||
regoffset = regoffset_b[index];
|
||||
rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
|
||||
|
||||
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
|
||||
"Set 0x%x = %08x\n", regoffset, writeval);
|
||||
}
|
||||
}
|
||||
|
||||
void rtl8821ae_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
|
||||
u8 *ppowerlevel_ofdm,
|
||||
u8 *ppowerlevel_bw20,
|
||||
u8 *ppowerlevel_bw40,
|
||||
u8 channel)
|
||||
{
|
||||
u32 writeval[2], powerbase0[2], powerbase1[2];
|
||||
u8 index;
|
||||
u8 direction;
|
||||
u32 pwrtrac_value;
|
||||
|
||||
rtl8821ae_phy_get_power_base(hw, ppowerlevel_ofdm,
|
||||
ppowerlevel_bw20,
|
||||
ppowerlevel_bw40,
|
||||
channel,
|
||||
&powerbase0[0],
|
||||
&powerbase1[0]);
|
||||
|
||||
rtl8821ae_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
|
||||
|
||||
for (index = 0; index < 6; index++) {
|
||||
get_txpower_writeval_by_regulatory(hw, channel, index,
|
||||
&powerbase0[0],
|
||||
&powerbase1[0],
|
||||
&writeval[0]);
|
||||
if (direction == 1) {
|
||||
writeval[0] += pwrtrac_value;
|
||||
writeval[1] += pwrtrac_value;
|
||||
} else if (direction == 2) {
|
||||
writeval[0] -= pwrtrac_value;
|
||||
writeval[1] -= pwrtrac_value;
|
||||
}
|
||||
_rtl8821ae_write_ofdm_power_reg(hw, index, &writeval[0]);
|
||||
}
|
||||
}
|
||||
|
||||
bool rtl8821ae_phy_rf6052_config(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_phy *rtlphy = &rtlpriv->phy;
|
||||
|
||||
if (rtlphy->rf_type == RF_1T1R)
|
||||
rtlphy->num_total_rfpath = 1;
|
||||
else
|
||||
rtlphy->num_total_rfpath = 2;
|
||||
|
||||
return _rtl8821ae_phy_rf6052_config_parafile(hw);
|
||||
}
|
||||
|
||||
static bool _rtl8821ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_phy *rtlphy = &rtlpriv->phy;
|
||||
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
|
||||
u8 rfpath;
|
||||
bool rtstatus = true;
|
||||
|
||||
for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
|
||||
switch (rfpath) {
|
||||
case RF90_PATH_A: {
|
||||
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
|
||||
rtstatus =
|
||||
rtl8812ae_phy_config_rf_with_headerfile(hw,
|
||||
(enum radio_path)rfpath);
|
||||
else
|
||||
rtstatus =
|
||||
rtl8821ae_phy_config_rf_with_headerfile(hw,
|
||||
(enum radio_path)rfpath);
|
||||
break;
|
||||
}
|
||||
case RF90_PATH_B:
|
||||
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
|
||||
rtstatus =
|
||||
rtl8812ae_phy_config_rf_with_headerfile(hw,
|
||||
(enum radio_path)rfpath);
|
||||
else
|
||||
rtstatus =
|
||||
rtl8821ae_phy_config_rf_with_headerfile(hw,
|
||||
(enum radio_path)rfpath);
|
||||
break;
|
||||
case RF90_PATH_C:
|
||||
break;
|
||||
case RF90_PATH_D:
|
||||
break;
|
||||
}
|
||||
|
||||
if (!rtstatus) {
|
||||
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
|
||||
"Radio[%d] Fail!!", rfpath);
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
/*put arrays in dm.c*/
|
||||
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
|
||||
return rtstatus;
|
||||
}
|
||||
43
drivers/net/wireless/rtlwifi/rtl8821ae/rf.h
Normal file
43
drivers/net/wireless/rtlwifi/rtl8821ae/rf.h
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2010 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL8821AE_RF_H__
|
||||
#define __RTL8821AE_RF_H__
|
||||
|
||||
#define RF6052_MAX_TX_PWR 0x3F
|
||||
#define RF6052_MAX_REG 0x3F
|
||||
|
||||
void rtl8821ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
|
||||
u8 bandwidth);
|
||||
void rtl8821ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
|
||||
u8 *ppowerlevel);
|
||||
void rtl8821ae_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
|
||||
u8 *ppowerlevel_ofdm,
|
||||
u8 *ppowerlevel_bw20,
|
||||
u8 *ppowerlevel_bw40,
|
||||
u8 channel);
|
||||
bool rtl8821ae_phy_rf6052_config(struct ieee80211_hw *hw);
|
||||
|
||||
#endif
|
||||
484
drivers/net/wireless/rtlwifi/rtl8821ae/sw.c
Normal file
484
drivers/net/wireless/rtlwifi/rtl8821ae/sw.c
Normal file
|
|
@ -0,0 +1,484 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2010 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "../wifi.h"
|
||||
#include "../core.h"
|
||||
#include "../pci.h"
|
||||
#include "reg.h"
|
||||
#include "def.h"
|
||||
#include "phy.h"
|
||||
#include "dm.h"
|
||||
#include "hw.h"
|
||||
#include "fw.h"
|
||||
#include "sw.h"
|
||||
#include "trx.h"
|
||||
#include "led.h"
|
||||
#include "table.h"
|
||||
#include "../btcoexist/rtl_btc.h"
|
||||
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
static void rtl8821ae_init_aspm_vars(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
|
||||
|
||||
/*close ASPM for AMD defaultly */
|
||||
rtlpci->const_amdpci_aspm = 0;
|
||||
|
||||
/**
|
||||
* ASPM PS mode.
|
||||
* 0 - Disable ASPM,
|
||||
* 1 - Enable ASPM without Clock Req,
|
||||
* 2 - Enable ASPM with Clock Req,
|
||||
* 3 - Alwyas Enable ASPM with Clock Req,
|
||||
* 4 - Always Enable ASPM without Clock Req.
|
||||
* set defult to RTL8192CE:3 RTL8192E:2
|
||||
*/
|
||||
rtlpci->const_pci_aspm = 3;
|
||||
|
||||
/*Setting for PCI-E device */
|
||||
rtlpci->const_devicepci_aspm_setting = 0x03;
|
||||
|
||||
/*Setting for PCI-E bridge */
|
||||
rtlpci->const_hostpci_aspm_setting = 0x02;
|
||||
|
||||
/**
|
||||
* In Hw/Sw Radio Off situation.
|
||||
* 0 - Default,
|
||||
* 1 - From ASPM setting without low Mac Pwr,
|
||||
* 2 - From ASPM setting with low Mac Pwr,
|
||||
* 3 - Bus D3
|
||||
* set default to RTL8192CE:0 RTL8192SE:2
|
||||
*/
|
||||
rtlpci->const_hwsw_rfoff_d3 = 0;
|
||||
|
||||
/**
|
||||
* This setting works for those device with
|
||||
* backdoor ASPM setting such as EPHY setting.
|
||||
* 0 - Not support ASPM,
|
||||
* 1 - Support ASPM,
|
||||
* 2 - According to chipset.
|
||||
*/
|
||||
rtlpci->const_support_pciaspm = 1;
|
||||
}
|
||||
|
||||
static void load_wowlan_fw(struct rtl_priv *rtlpriv)
|
||||
{
|
||||
/* callback routine to load wowlan firmware after main fw has
|
||||
* been loaded
|
||||
*/
|
||||
const struct firmware *wowlan_firmware;
|
||||
char *fw_name = NULL;
|
||||
int err;
|
||||
|
||||
/* for wowlan firmware buf */
|
||||
rtlpriv->rtlhal.wowlan_firmware = vzalloc(0x8000);
|
||||
if (!rtlpriv->rtlhal.wowlan_firmware) {
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
|
||||
"Can't alloc buffer for wowlan fw.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8821AE)
|
||||
fw_name = "rtlwifi/rtl8821aefw_wowlan.bin";
|
||||
else
|
||||
fw_name = "rtlwifi/rtl8812aefw_wowlan.bin";
|
||||
err = request_firmware(&wowlan_firmware, fw_name, rtlpriv->io.dev);
|
||||
if (err) {
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
|
||||
"Failed to request wowlan firmware!\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
if (wowlan_firmware->size > 0x8000) {
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
|
||||
"Wowlan Firmware is too big!\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
memcpy(rtlpriv->rtlhal.wowlan_firmware, wowlan_firmware->data,
|
||||
wowlan_firmware->size);
|
||||
rtlpriv->rtlhal.wowlan_fwsize = wowlan_firmware->size;
|
||||
release_firmware(wowlan_firmware);
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "WOWLAN FirmwareDownload OK\n");
|
||||
return;
|
||||
error:
|
||||
release_firmware(wowlan_firmware);
|
||||
vfree(rtlpriv->rtlhal.wowlan_firmware);
|
||||
}
|
||||
|
||||
/*InitializeVariables8812E*/
|
||||
int rtl8821ae_init_sw_vars(struct ieee80211_hw *hw)
|
||||
{
|
||||
int err = 0;
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
|
||||
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
|
||||
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
|
||||
|
||||
rtl8821ae_bt_reg_init(hw);
|
||||
rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
|
||||
rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
|
||||
|
||||
rtlpriv->dm.dm_initialgain_enable = 1;
|
||||
rtlpriv->dm.dm_flag = 0;
|
||||
rtlpriv->dm.disable_framebursting = 0;
|
||||
rtlpriv->dm.thermalvalue = 0;
|
||||
rtlpci->transmit_config = CFENDFORM | BIT(15) | BIT(24) | BIT(25);
|
||||
|
||||
mac->ht_enable = true;
|
||||
mac->ht_cur_stbc = 0;
|
||||
mac->ht_stbc_cap = 0;
|
||||
mac->vht_cur_ldpc = 0;
|
||||
mac->vht_ldpc_cap = 0;
|
||||
mac->vht_cur_stbc = 0;
|
||||
mac->vht_stbc_cap = 0;
|
||||
|
||||
rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
|
||||
/*following 2 is for register 5G band, refer to _rtl_init_mac80211()*/
|
||||
rtlpriv->rtlhal.bandset = BAND_ON_BOTH;
|
||||
rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
|
||||
|
||||
rtlpci->receive_config = (RCR_APPFCS |
|
||||
RCR_APP_MIC |
|
||||
RCR_APP_ICV |
|
||||
RCR_APP_PHYST_RXFF |
|
||||
RCR_NONQOS_VHT |
|
||||
RCR_HTC_LOC_CTRL |
|
||||
RCR_AMF |
|
||||
RCR_ACF |
|
||||
/*This bit controls the PS-Poll packet filter.*/
|
||||
RCR_ADF |
|
||||
RCR_AICV |
|
||||
RCR_ACRC32 |
|
||||
RCR_AB |
|
||||
RCR_AM |
|
||||
RCR_APM |
|
||||
0);
|
||||
|
||||
rtlpci->irq_mask[0] =
|
||||
(u32)(IMR_PSTIMEOUT |
|
||||
IMR_GTINT3 |
|
||||
IMR_HSISR_IND_ON_INT |
|
||||
IMR_C2HCMD |
|
||||
IMR_HIGHDOK |
|
||||
IMR_MGNTDOK |
|
||||
IMR_BKDOK |
|
||||
IMR_BEDOK |
|
||||
IMR_VIDOK |
|
||||
IMR_VODOK |
|
||||
IMR_RDU |
|
||||
IMR_ROK |
|
||||
0);
|
||||
|
||||
rtlpci->irq_mask[1] =
|
||||
(u32)(IMR_RXFOVW |
|
||||
IMR_TXFOVW |
|
||||
0);
|
||||
rtlpci->sys_irq_mask = (u32)(HSIMR_PDN_INT_EN |
|
||||
HSIMR_RON_INT_EN |
|
||||
0);
|
||||
/* for WOWLAN */
|
||||
rtlpriv->psc.wo_wlan_mode = WAKE_ON_MAGIC_PACKET |
|
||||
WAKE_ON_PATTERN_MATCH;
|
||||
|
||||
/* for debug level */
|
||||
rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
|
||||
/* for LPS & IPS */
|
||||
rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
|
||||
rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
|
||||
rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
|
||||
rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
|
||||
if (rtlpriv->cfg->mod_params->disable_watchdog)
|
||||
pr_info("watchdog disabled\n");
|
||||
rtlpriv->psc.reg_fwctrl_lps = 3;
|
||||
rtlpriv->psc.reg_max_lps_awakeintvl = 5;
|
||||
rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
|
||||
|
||||
/* for ASPM, you can close aspm through
|
||||
* set const_support_pciaspm = 0
|
||||
*/
|
||||
rtl8821ae_init_aspm_vars(hw);
|
||||
|
||||
if (rtlpriv->psc.reg_fwctrl_lps == 1)
|
||||
rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
|
||||
else if (rtlpriv->psc.reg_fwctrl_lps == 2)
|
||||
rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
|
||||
else if (rtlpriv->psc.reg_fwctrl_lps == 3)
|
||||
rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
|
||||
|
||||
rtlpriv->rtl_fw_second_cb = load_wowlan_fw;
|
||||
/* for firmware buf */
|
||||
rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
|
||||
if (!rtlpriv->rtlhal.pfirmware) {
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
|
||||
"Can't alloc buffer for fw.\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
|
||||
rtlpriv->cfg->fw_name = "rtlwifi/rtl8812aefw.bin";
|
||||
else
|
||||
rtlpriv->cfg->fw_name = "rtlwifi/rtl8821aefw.bin";
|
||||
|
||||
rtlpriv->max_fw_size = 0x8000;
|
||||
pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
|
||||
err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
|
||||
rtlpriv->io.dev, GFP_KERNEL, hw,
|
||||
rtl_fw_cb);
|
||||
if (err) {
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
|
||||
"Failed to request firmware!\n");
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void rtl8821ae_deinit_sw_vars(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
|
||||
if (rtlpriv->rtlhal.pfirmware) {
|
||||
vfree(rtlpriv->rtlhal.pfirmware);
|
||||
rtlpriv->rtlhal.pfirmware = NULL;
|
||||
}
|
||||
#if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
|
||||
if (rtlpriv->rtlhal.wowlan_firmware) {
|
||||
vfree(rtlpriv->rtlhal.wowlan_firmware);
|
||||
rtlpriv->rtlhal.wowlan_firmware = NULL;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/* get bt coexist status */
|
||||
bool rtl8821ae_get_btc_status(void)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static struct rtl_hal_ops rtl8821ae_hal_ops = {
|
||||
.init_sw_vars = rtl8821ae_init_sw_vars,
|
||||
.deinit_sw_vars = rtl8821ae_deinit_sw_vars,
|
||||
.read_eeprom_info = rtl8821ae_read_eeprom_info,
|
||||
.interrupt_recognized = rtl8821ae_interrupt_recognized,
|
||||
.hw_init = rtl8821ae_hw_init,
|
||||
.hw_disable = rtl8821ae_card_disable,
|
||||
.hw_suspend = rtl8821ae_suspend,
|
||||
.hw_resume = rtl8821ae_resume,
|
||||
.enable_interrupt = rtl8821ae_enable_interrupt,
|
||||
.disable_interrupt = rtl8821ae_disable_interrupt,
|
||||
.set_network_type = rtl8821ae_set_network_type,
|
||||
.set_chk_bssid = rtl8821ae_set_check_bssid,
|
||||
.set_qos = rtl8821ae_set_qos,
|
||||
.set_bcn_reg = rtl8821ae_set_beacon_related_registers,
|
||||
.set_bcn_intv = rtl8821ae_set_beacon_interval,
|
||||
.update_interrupt_mask = rtl8821ae_update_interrupt_mask,
|
||||
.get_hw_reg = rtl8821ae_get_hw_reg,
|
||||
.set_hw_reg = rtl8821ae_set_hw_reg,
|
||||
.update_rate_tbl = rtl8821ae_update_hal_rate_tbl,
|
||||
.fill_tx_desc = rtl8821ae_tx_fill_desc,
|
||||
.fill_tx_cmddesc = rtl8821ae_tx_fill_cmddesc,
|
||||
.query_rx_desc = rtl8821ae_rx_query_desc,
|
||||
.set_channel_access = rtl8821ae_update_channel_access_setting,
|
||||
.radio_onoff_checking = rtl8821ae_gpio_radio_on_off_checking,
|
||||
.set_bw_mode = rtl8821ae_phy_set_bw_mode,
|
||||
.switch_channel = rtl8821ae_phy_sw_chnl,
|
||||
.dm_watchdog = rtl8821ae_dm_watchdog,
|
||||
.scan_operation_backup = rtl8821ae_phy_scan_operation_backup,
|
||||
.set_rf_power_state = rtl8821ae_phy_set_rf_power_state,
|
||||
.led_control = rtl8821ae_led_control,
|
||||
.set_desc = rtl8821ae_set_desc,
|
||||
.get_desc = rtl8821ae_get_desc,
|
||||
.is_tx_desc_closed = rtl8821ae_is_tx_desc_closed,
|
||||
.tx_polling = rtl8821ae_tx_polling,
|
||||
.enable_hw_sec = rtl8821ae_enable_hw_security_config,
|
||||
.set_key = rtl8821ae_set_key,
|
||||
.init_sw_leds = rtl8821ae_init_sw_leds,
|
||||
.get_bbreg = rtl8821ae_phy_query_bb_reg,
|
||||
.set_bbreg = rtl8821ae_phy_set_bb_reg,
|
||||
.get_rfreg = rtl8821ae_phy_query_rf_reg,
|
||||
.set_rfreg = rtl8821ae_phy_set_rf_reg,
|
||||
.fill_h2c_cmd = rtl8821ae_fill_h2c_cmd,
|
||||
.get_btc_status = rtl8821ae_get_btc_status,
|
||||
.rx_command_packet = rtl8821ae_rx_command_packet,
|
||||
.add_wowlan_pattern = rtl8821ae_add_wowlan_pattern,
|
||||
};
|
||||
|
||||
static struct rtl_mod_params rtl8821ae_mod_params = {
|
||||
.sw_crypto = false,
|
||||
.inactiveps = true,
|
||||
.swctrl_lps = false,
|
||||
.fwctrl_lps = true,
|
||||
.msi_support = true,
|
||||
.debug = DBG_EMERG,
|
||||
.disable_watchdog = 0,
|
||||
};
|
||||
|
||||
static struct rtl_hal_cfg rtl8821ae_hal_cfg = {
|
||||
.bar_id = 2,
|
||||
.write_readback = true,
|
||||
.name = "rtl8821ae_pci",
|
||||
.fw_name = "rtlwifi/rtl8821aefw.bin",
|
||||
.ops = &rtl8821ae_hal_ops,
|
||||
.mod_params = &rtl8821ae_mod_params,
|
||||
.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
|
||||
.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
|
||||
.maps[SYS_CLK] = REG_SYS_CLKR,
|
||||
.maps[MAC_RCR_AM] = AM,
|
||||
.maps[MAC_RCR_AB] = AB,
|
||||
.maps[MAC_RCR_ACRC32] = ACRC32,
|
||||
.maps[MAC_RCR_ACF] = ACF,
|
||||
.maps[MAC_RCR_AAP] = AAP,
|
||||
.maps[MAC_HIMR] = REG_HIMR,
|
||||
.maps[MAC_HIMRE] = REG_HIMRE,
|
||||
|
||||
.maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
|
||||
|
||||
.maps[EFUSE_TEST] = REG_EFUSE_TEST,
|
||||
.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
|
||||
.maps[EFUSE_CLK] = 0,
|
||||
.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
|
||||
.maps[EFUSE_PWC_EV12V] = PWC_EV12V,
|
||||
.maps[EFUSE_FEN_ELDR] = FEN_ELDR,
|
||||
.maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
|
||||
.maps[EFUSE_ANA8M] = ANA8M,
|
||||
.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
|
||||
.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
|
||||
.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
|
||||
.maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
|
||||
|
||||
.maps[RWCAM] = REG_CAMCMD,
|
||||
.maps[WCAMI] = REG_CAMWRITE,
|
||||
.maps[RCAMO] = REG_CAMREAD,
|
||||
.maps[CAMDBG] = REG_CAMDBG,
|
||||
.maps[SECR] = REG_SECCFG,
|
||||
.maps[SEC_CAM_NONE] = CAM_NONE,
|
||||
.maps[SEC_CAM_WEP40] = CAM_WEP40,
|
||||
.maps[SEC_CAM_TKIP] = CAM_TKIP,
|
||||
.maps[SEC_CAM_AES] = CAM_AES,
|
||||
.maps[SEC_CAM_WEP104] = CAM_WEP104,
|
||||
|
||||
.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
|
||||
.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
|
||||
.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
|
||||
.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
|
||||
.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
|
||||
.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
|
||||
/* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/
|
||||
.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
|
||||
.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
|
||||
.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
|
||||
.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
|
||||
.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
|
||||
.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
|
||||
.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
|
||||
/* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
|
||||
/* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
|
||||
|
||||
.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
|
||||
.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
|
||||
.maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
|
||||
.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
|
||||
.maps[RTL_IMR_RDU] = IMR_RDU,
|
||||
.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
|
||||
.maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
|
||||
.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
|
||||
.maps[RTL_IMR_TBDER] = IMR_TBDER,
|
||||
.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
|
||||
.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
|
||||
.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
|
||||
.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
|
||||
.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
|
||||
.maps[RTL_IMR_VODOK] = IMR_VODOK,
|
||||
.maps[RTL_IMR_ROK] = IMR_ROK,
|
||||
.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
|
||||
|
||||
.maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
|
||||
.maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
|
||||
.maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
|
||||
.maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
|
||||
.maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
|
||||
.maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
|
||||
.maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
|
||||
.maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
|
||||
.maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
|
||||
.maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
|
||||
.maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
|
||||
.maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
|
||||
|
||||
.maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
|
||||
.maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
|
||||
|
||||
/*VHT hightest rate*/
|
||||
.maps[RTL_RC_VHT_RATE_1SS_MCS7] = DESC_RATEVHT1SS_MCS7,
|
||||
.maps[RTL_RC_VHT_RATE_1SS_MCS8] = DESC_RATEVHT1SS_MCS8,
|
||||
.maps[RTL_RC_VHT_RATE_1SS_MCS9] = DESC_RATEVHT1SS_MCS9,
|
||||
.maps[RTL_RC_VHT_RATE_2SS_MCS7] = DESC_RATEVHT2SS_MCS7,
|
||||
.maps[RTL_RC_VHT_RATE_2SS_MCS8] = DESC_RATEVHT2SS_MCS8,
|
||||
.maps[RTL_RC_VHT_RATE_2SS_MCS9] = DESC_RATEVHT2SS_MCS9,
|
||||
};
|
||||
|
||||
static struct pci_device_id rtl8821ae_pci_ids[] = {
|
||||
{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8812, rtl8821ae_hal_cfg)},
|
||||
{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8821, rtl8821ae_hal_cfg)},
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(pci, rtl8821ae_pci_ids);
|
||||
|
||||
MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("Realtek 8821ae 802.11ac PCI wireless");
|
||||
MODULE_FIRMWARE("rtlwifi/rtl8821aefw.bin");
|
||||
|
||||
module_param_named(swenc, rtl8821ae_mod_params.sw_crypto, bool, 0444);
|
||||
module_param_named(debug, rtl8821ae_mod_params.debug, int, 0444);
|
||||
module_param_named(ips, rtl8821ae_mod_params.inactiveps, bool, 0444);
|
||||
module_param_named(swlps, rtl8821ae_mod_params.swctrl_lps, bool, 0444);
|
||||
module_param_named(fwlps, rtl8821ae_mod_params.fwctrl_lps, bool, 0444);
|
||||
module_param_named(msi, rtl8821ae_mod_params.msi_support, bool, 0444);
|
||||
module_param_named(disable_watchdog, rtl8821ae_mod_params.disable_watchdog,
|
||||
bool, 0444);
|
||||
MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
|
||||
MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
|
||||
MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
|
||||
MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
|
||||
MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
|
||||
MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
|
||||
MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
|
||||
|
||||
static struct pci_driver rtl8821ae_driver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.id_table = rtl8821ae_pci_ids,
|
||||
.probe = rtl_pci_probe,
|
||||
.remove = rtl_pci_disconnect,
|
||||
.driver.pm = &rtlwifi_pm_ops,
|
||||
};
|
||||
|
||||
module_pci_driver(rtl8821ae_driver);
|
||||
34
drivers/net/wireless/rtlwifi/rtl8821ae/sw.h
Normal file
34
drivers/net/wireless/rtlwifi/rtl8821ae/sw.h
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2010 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL8821AE_SW_H__
|
||||
#define __RTL8821AE_SW_H__
|
||||
|
||||
int rtl8821ae_init_sw_vars(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_deinit_sw_vars(struct ieee80211_hw *hw);
|
||||
void rtl8821ae_init_var_map(struct ieee80211_hw *hw);
|
||||
bool rtl8821ae_get_btc_status(void);
|
||||
|
||||
#endif
|
||||
4572
drivers/net/wireless/rtlwifi/rtl8821ae/table.c
Normal file
4572
drivers/net/wireless/rtlwifi/rtl8821ae/table.c
Normal file
File diff suppressed because it is too large
Load diff
60
drivers/net/wireless/rtlwifi/rtl8821ae/table.h
Normal file
60
drivers/net/wireless/rtlwifi/rtl8821ae/table.h
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2010 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Created on 2010/ 5/18, 1:41
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL8821AE_TABLE__H_
|
||||
#define __RTL8821AE_TABLE__H_
|
||||
|
||||
#include <linux/types.h>
|
||||
#define RTL8821AEPHY_REG_1TARRAYLEN 344
|
||||
extern u32 RTL8821AE_PHY_REG_ARRAY[];
|
||||
#define RTL8812AEPHY_REG_1TARRAYLEN 490
|
||||
extern u32 RTL8812AE_PHY_REG_ARRAY[];
|
||||
#define RTL8821AEPHY_REG_ARRAY_PGLEN 90
|
||||
extern u32 RTL8821AE_PHY_REG_ARRAY_PG[];
|
||||
#define RTL8812AEPHY_REG_ARRAY_PGLEN 276
|
||||
extern u32 RTL8812AE_PHY_REG_ARRAY_PG[];
|
||||
/* #define RTL8723BE_RADIOA_1TARRAYLEN 206 */
|
||||
/* extern u8 *RTL8821AE_TXPWR_LMT_ARRAY[]; */
|
||||
#define RTL8812AE_RADIOA_1TARRAYLEN 1264
|
||||
extern u32 RTL8812AE_RADIOA_ARRAY[];
|
||||
#define RTL8812AE_RADIOB_1TARRAYLEN 1240
|
||||
extern u32 RTL8812AE_RADIOB_ARRAY[];
|
||||
#define RTL8821AE_RADIOA_1TARRAYLEN 1176
|
||||
extern u32 RTL8821AE_RADIOA_ARRAY[];
|
||||
#define RTL8821AEMAC_1T_ARRAYLEN 194
|
||||
extern u32 RTL8821AE_MAC_REG_ARRAY[];
|
||||
#define RTL8812AEMAC_1T_ARRAYLEN 214
|
||||
extern u32 RTL8812AE_MAC_REG_ARRAY[];
|
||||
#define RTL8821AEAGCTAB_1TARRAYLEN 382
|
||||
extern u32 RTL8821AE_AGC_TAB_ARRAY[];
|
||||
#define RTL8812AEAGCTAB_1TARRAYLEN 1312
|
||||
extern u32 RTL8812AE_AGC_TAB_ARRAY[];
|
||||
#define RTL8812AE_TXPWR_LMT_ARRAY_LEN 3948
|
||||
extern u8 *RTL8812AE_TXPWR_LMT[];
|
||||
#define RTL8821AE_TXPWR_LMT_ARRAY_LEN 3948
|
||||
extern u8 *RTL8821AE_TXPWR_LMT[];
|
||||
#endif
|
||||
1236
drivers/net/wireless/rtlwifi/rtl8821ae/trx.c
Normal file
1236
drivers/net/wireless/rtlwifi/rtl8821ae/trx.c
Normal file
File diff suppressed because it is too large
Load diff
620
drivers/net/wireless/rtlwifi/rtl8821ae/trx.h
Normal file
620
drivers/net/wireless/rtlwifi/rtl8821ae/trx.h
Normal file
|
|
@ -0,0 +1,620 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2010 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL8821AE_TRX_H__
|
||||
#define __RTL8821AE_TRX_H__
|
||||
|
||||
#define TX_DESC_SIZE 40
|
||||
#define TX_DESC_AGGR_SUBFRAME_SIZE 32
|
||||
|
||||
#define RX_DESC_SIZE 32
|
||||
#define RX_DRV_INFO_SIZE_UNIT 8
|
||||
|
||||
#define TX_DESC_NEXT_DESC_OFFSET 40
|
||||
#define USB_HWDESC_HEADER_LEN 40
|
||||
#define CRCLENGTH 4
|
||||
|
||||
#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 0, 16, __val)
|
||||
#define SET_TX_DESC_OFFSET(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 16, 8, __val)
|
||||
#define SET_TX_DESC_BMC(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 24, 1, __val)
|
||||
#define SET_TX_DESC_HTC(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 25, 1, __val)
|
||||
#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 26, 1, __val)
|
||||
#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 27, 1, __val)
|
||||
#define SET_TX_DESC_LINIP(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 28, 1, __val)
|
||||
#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 29, 1, __val)
|
||||
#define SET_TX_DESC_GF(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
|
||||
#define SET_TX_DESC_OWN(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
|
||||
|
||||
#define GET_TX_DESC_PKT_SIZE(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 0, 16)
|
||||
#define GET_TX_DESC_OFFSET(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 16, 8)
|
||||
#define GET_TX_DESC_BMC(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 24, 1)
|
||||
#define GET_TX_DESC_HTC(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 25, 1)
|
||||
#define GET_TX_DESC_LAST_SEG(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 26, 1)
|
||||
#define GET_TX_DESC_FIRST_SEG(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 27, 1)
|
||||
#define GET_TX_DESC_LINIP(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 28, 1)
|
||||
#define GET_TX_DESC_NO_ACM(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 29, 1)
|
||||
#define GET_TX_DESC_GF(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 30, 1)
|
||||
#define GET_TX_DESC_OWN(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 31, 1)
|
||||
|
||||
#define SET_TX_DESC_MACID(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 7, __val)
|
||||
#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 8, 5, __val)
|
||||
#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 13, 1, __val)
|
||||
#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 14, 1, __val)
|
||||
#define SET_TX_DESC_PIFS(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 15, 1, __val)
|
||||
#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 16, 5, __val)
|
||||
#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 21, 1, __val)
|
||||
#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 22, 2, __val)
|
||||
#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 24, 5, __val)
|
||||
|
||||
#define SET_TX_DESC_PAID(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 9, __val)
|
||||
#define SET_TX_DESC_CCA_RTS(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 10, 2, __val)
|
||||
#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 12, 1, __val)
|
||||
#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 13, 1, __val)
|
||||
#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 14, 2, __val)
|
||||
#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 16, 1, __val)
|
||||
#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 17, 1, __val)
|
||||
#define SET_TX_DESC_RAW(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 18, 1, __val)
|
||||
#define SET_TX_DESC_SPE_RPT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 19, 1, __val)
|
||||
#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 20, 3, __val)
|
||||
#define SET_TX_DESC_BT_INT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 23, 1, __val)
|
||||
#define SET_TX_DESC_GID(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 24, 6, __val)
|
||||
|
||||
#define SET_TX_DESC_WHEADER_LEN(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 4, __val)
|
||||
#define SET_TX_DESC_CHK_EN(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 4, 1, __val)
|
||||
#define SET_TX_DESC_EARLY_MODE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 5, 1, __val)
|
||||
#define SET_TX_DESC_HWSEQ_SEL(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 6, 2, __val)
|
||||
#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 8, 1, __val)
|
||||
#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 9, 1, __val)
|
||||
#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 10, 1, __val)
|
||||
#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 11, 1, __val)
|
||||
#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 12, 1, __val)
|
||||
#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 13, 1, __val)
|
||||
#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 15, 1, __val)
|
||||
#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 16, 1, __val)
|
||||
#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 17, 5, __val)
|
||||
#define SET_TX_DESC_NDPA(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 22, 2, __val)
|
||||
#define SET_TX_DESC_AMPDU_MAX_TIME(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 24, 8, __val)
|
||||
#define SET_TX_DESC_TX_ANT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 24, 4, __val)
|
||||
|
||||
#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 7, __val)
|
||||
#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 8, 5, __val)
|
||||
#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 13, 4, __val)
|
||||
#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 17, 1, __val)
|
||||
#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 18, 6, __val)
|
||||
#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 24, 5, __val)
|
||||
|
||||
#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 4, __val)
|
||||
#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_1BYTE(__pdesc+20, 4, 1, __val)
|
||||
#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 5, 2, __val)
|
||||
#define SET_TX_DESC_DATA_LDPC(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 7, 1, __val)
|
||||
#define SET_TX_DESC_DATA_STBC(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 8, 2, __val)
|
||||
#define SET_TX_DESC_CTROL_STBC(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 10, 2, __val)
|
||||
#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 12, 1, __val)
|
||||
#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 13, 4, __val)
|
||||
|
||||
#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 16, __val)
|
||||
|
||||
#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+28, 0, 16)
|
||||
|
||||
#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+32, 15, 1, __val)
|
||||
|
||||
#define SET_TX_DESC_SEQ(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+36, 12, 12, __val)
|
||||
|
||||
#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+40, 0, 32, __val)
|
||||
|
||||
#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+40, 0, 32)
|
||||
|
||||
#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+48, 0, 32, __val)
|
||||
|
||||
#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+48, 0, 32)
|
||||
|
||||
#define GET_RX_DESC_PKT_LEN(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 0, 14)
|
||||
#define GET_RX_DESC_CRC32(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 14, 1)
|
||||
#define GET_RX_DESC_ICV(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 15, 1)
|
||||
#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 16, 4)
|
||||
#define GET_RX_DESC_SECURITY(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 20, 3)
|
||||
#define GET_RX_DESC_QOS(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 23, 1)
|
||||
#define GET_RX_DESC_SHIFT(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 24, 2)
|
||||
#define GET_RX_DESC_PHYST(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 26, 1)
|
||||
#define GET_RX_DESC_SWDEC(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 27, 1)
|
||||
#define GET_RX_DESC_LS(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 28, 1)
|
||||
#define GET_RX_DESC_FS(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 29, 1)
|
||||
#define GET_RX_DESC_EOR(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 30, 1)
|
||||
#define GET_RX_DESC_OWN(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 31, 1)
|
||||
|
||||
#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
|
||||
#define SET_RX_DESC_EOR(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
|
||||
#define SET_RX_DESC_OWN(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
|
||||
|
||||
#define GET_RX_DESC_MACID(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 0, 7)
|
||||
#define GET_RX_DESC_TID(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 8, 4)
|
||||
#define GET_RX_DESC_AMSDU(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 13, 1)
|
||||
#define GET_RX_STATUS_DESC_RXID_MATCH(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
|
||||
#define GET_RX_DESC_PAGGR(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
|
||||
#define GET_RX_DESC_A1_FIT(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
|
||||
#define GET_RX_DESC_CHKERR(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 20, 1)
|
||||
#define GET_RX_DESC_IPVER(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 21, 1)
|
||||
#define GET_RX_STATUS_DESC_IS_TCPUDP(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 22, 1)
|
||||
#define GET_RX_STATUS_DESC_CHK_VLD(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 23, 1)
|
||||
#define GET_RX_DESC_PAM(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 24, 1)
|
||||
#define GET_RX_DESC_PWR(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 25, 1)
|
||||
#define GET_RX_DESC_MD(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 26, 1)
|
||||
#define GET_RX_DESC_MF(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 27, 1)
|
||||
#define GET_RX_DESC_TYPE(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 28, 2)
|
||||
#define GET_RX_DESC_MC(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 30, 1)
|
||||
#define GET_RX_DESC_BC(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 31, 1)
|
||||
|
||||
#define GET_RX_DESC_SEQ(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+8, 0, 12)
|
||||
#define GET_RX_DESC_FRAG(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+8, 12, 4)
|
||||
#define GET_RX_STATUS_DESC_RX_IS_QOS(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+8, 16, 1)
|
||||
#define GET_RX_STATUS_DESC_WLANHD_IV_LEN(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+8, 18, 6)
|
||||
#define GET_RX_STATUS_DESC_RPT_SEL(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+8, 28, 1)
|
||||
|
||||
#define GET_RX_DESC_RXMCS(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+12, 0, 7)
|
||||
#define GET_RX_DESC_HTC(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+12, 10, 1)
|
||||
#define GET_RX_STATUS_DESC_EOSP(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+12, 11, 1)
|
||||
#define GET_RX_STATUS_DESC_BSSID_FIT(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+12, 12, 2)
|
||||
|
||||
#define GET_RX_STATUS_DESC_PATTERN_MATCH(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+12, 29, 1)
|
||||
#define GET_RX_STATUS_DESC_UNICAST_MATCH(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+12, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_MAGIC_MATCH(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+12, 31, 1)
|
||||
|
||||
#define GET_RX_DESC_SPLCP(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+16, 0, 1)
|
||||
#define GET_RX_STATUS_DESC_LDPC(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+16, 1, 1)
|
||||
#define GET_RX_STATUS_DESC_STBC(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+16, 2, 1)
|
||||
#define GET_RX_DESC_BW(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+16, 4, 2)
|
||||
|
||||
#define GET_RX_DESC_TSFL(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+20, 0, 32)
|
||||
|
||||
#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+24, 0, 32)
|
||||
#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+28, 0, 32)
|
||||
|
||||
#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
|
||||
#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
|
||||
|
||||
/* TX report 2 format in Rx desc*/
|
||||
|
||||
#define GET_RX_RPT2_DESC_PKT_LEN(__status) \
|
||||
LE_BITS_TO_4BYTE(__status, 0, 9)
|
||||
#define GET_RX_RPT2_DESC_MACID_VALID_1(__status) \
|
||||
LE_BITS_TO_4BYTE(__status+16, 0, 32)
|
||||
#define GET_RX_RPT2_DESC_MACID_VALID_2(__status) \
|
||||
LE_BITS_TO_4BYTE(__status+20, 0, 32)
|
||||
|
||||
#define SET_EARLYMODE_PKTNUM(__paddr, __value) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr, 0, 4, __value)
|
||||
#define SET_EARLYMODE_LEN0(__paddr, __value) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr, 4, 12, __value)
|
||||
#define SET_EARLYMODE_LEN1(__paddr, __value) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr, 16, 12, __value)
|
||||
#define SET_EARLYMODE_LEN2_1(__paddr, __value) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr, 28, 4, __value)
|
||||
#define SET_EARLYMODE_LEN2_2(__paddr, __value) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr+4, 0, 8, __value)
|
||||
#define SET_EARLYMODE_LEN3(__paddr, __value) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr+4, 8, 12, __value)
|
||||
#define SET_EARLYMODE_LEN4(__paddr, __value) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr+4, 20, 12, __value)
|
||||
|
||||
#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
|
||||
do { \
|
||||
if (_size > TX_DESC_NEXT_DESC_OFFSET) \
|
||||
memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
|
||||
else \
|
||||
memset(__pdesc, 0, _size); \
|
||||
} while (0)
|
||||
|
||||
#define RTL8821AE_RX_HAL_IS_CCK_RATE(rxmcs)\
|
||||
(rxmcs == DESC_RATE1M ||\
|
||||
rxmcs == DESC_RATE2M ||\
|
||||
rxmcs == DESC_RATE5_5M ||\
|
||||
rxmcs == DESC_RATE11M)
|
||||
|
||||
struct phy_rx_agc_info_t {
|
||||
#ifdef __LITTLE_ENDIAN
|
||||
u8 gain:7, trsw:1;
|
||||
#else
|
||||
u8 trsw:1, gain:7;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct phy_status_rpt {
|
||||
/* DWORD 0 */
|
||||
u8 gain_trsw[2];
|
||||
#ifdef __LITTLE_ENDIAN
|
||||
u16 chl_num:10;
|
||||
u16 sub_chnl:4;
|
||||
u16 r_rfmod:2;
|
||||
#else /* _BIG_ENDIAN_ */
|
||||
u16 r_rfmod:2;
|
||||
u16 sub_chnl:4;
|
||||
u16 chl_num:10;
|
||||
#endif
|
||||
/* DWORD 1 */
|
||||
u8 pwdb_all;
|
||||
u8 cfosho[4]; /* DW 1 byte 1 DW 2 byte 0 */
|
||||
|
||||
/* DWORD 2 */
|
||||
char cfotail[4]; /* DW 2 byte 1 DW 3 byte 0 */
|
||||
|
||||
/* DWORD 3 */
|
||||
char rxevm[2]; /* DW 3 byte 1 DW 3 byte 2 */
|
||||
char rxsnr[2]; /* DW 3 byte 3 DW 4 byte 0 */
|
||||
|
||||
/* DWORD 4 */
|
||||
u8 pcts_msk_rpt[2];
|
||||
u8 pdsnr[2]; /* DW 4 byte 3 DW 5 Byte 0 */
|
||||
|
||||
/* DWORD 5 */
|
||||
u8 csi_current[2];
|
||||
u8 rx_gain_c;
|
||||
|
||||
/* DWORD 6 */
|
||||
u8 rx_gain_d;
|
||||
u8 sigevm;
|
||||
u8 resvd_0;
|
||||
u8 antidx_anta:3;
|
||||
u8 antidx_antb:3;
|
||||
u8 resvd_1:2;
|
||||
} __packed;
|
||||
|
||||
struct rx_fwinfo_8821ae {
|
||||
u8 gain_trsw[4];
|
||||
u8 pwdb_all;
|
||||
u8 cfosho[4];
|
||||
u8 cfotail[4];
|
||||
char rxevm[2];
|
||||
char rxsnr[4];
|
||||
u8 pdsnr[2];
|
||||
u8 csi_current[2];
|
||||
u8 csi_target[2];
|
||||
u8 sigevm;
|
||||
u8 max_ex_pwr;
|
||||
u8 ex_intf_flag:1;
|
||||
u8 sgi_en:1;
|
||||
u8 rxsc:2;
|
||||
u8 reserve:4;
|
||||
} __packed;
|
||||
|
||||
struct tx_desc_8821ae {
|
||||
u32 pktsize:16;
|
||||
u32 offset:8;
|
||||
u32 bmc:1;
|
||||
u32 htc:1;
|
||||
u32 lastseg:1;
|
||||
u32 firstseg:1;
|
||||
u32 linip:1;
|
||||
u32 noacm:1;
|
||||
u32 gf:1;
|
||||
u32 own:1;
|
||||
|
||||
u32 macid:6;
|
||||
u32 rsvd0:2;
|
||||
u32 queuesel:5;
|
||||
u32 rd_nav_ext:1;
|
||||
u32 lsig_txop_en:1;
|
||||
u32 pifs:1;
|
||||
u32 rateid:4;
|
||||
u32 nav_usehdr:1;
|
||||
u32 en_descid:1;
|
||||
u32 sectype:2;
|
||||
u32 pktoffset:8;
|
||||
|
||||
u32 rts_rc:6;
|
||||
u32 data_rc:6;
|
||||
u32 agg_en:1;
|
||||
u32 rdg_en:1;
|
||||
u32 bar_retryht:2;
|
||||
u32 agg_break:1;
|
||||
u32 morefrag:1;
|
||||
u32 raw:1;
|
||||
u32 ccx:1;
|
||||
u32 ampdudensity:3;
|
||||
u32 bt_int:1;
|
||||
u32 ant_sela:1;
|
||||
u32 ant_selb:1;
|
||||
u32 txant_cck:2;
|
||||
u32 txant_l:2;
|
||||
u32 txant_ht:2;
|
||||
|
||||
u32 nextheadpage:8;
|
||||
u32 tailpage:8;
|
||||
u32 seq:12;
|
||||
u32 cpu_handle:1;
|
||||
u32 tag1:1;
|
||||
u32 trigger_int:1;
|
||||
u32 hwseq_en:1;
|
||||
|
||||
u32 rtsrate:5;
|
||||
u32 apdcfe:1;
|
||||
u32 qos:1;
|
||||
u32 hwseq_ssn:1;
|
||||
u32 userrate:1;
|
||||
u32 dis_rtsfb:1;
|
||||
u32 dis_datafb:1;
|
||||
u32 cts2self:1;
|
||||
u32 rts_en:1;
|
||||
u32 hwrts_en:1;
|
||||
u32 portid:1;
|
||||
u32 pwr_status:3;
|
||||
u32 waitdcts:1;
|
||||
u32 cts2ap_en:1;
|
||||
u32 txsc:2;
|
||||
u32 stbc:2;
|
||||
u32 txshort:1;
|
||||
u32 txbw:1;
|
||||
u32 rtsshort:1;
|
||||
u32 rtsbw:1;
|
||||
u32 rtssc:2;
|
||||
u32 rtsstbc:2;
|
||||
|
||||
u32 txrate:6;
|
||||
u32 shortgi:1;
|
||||
u32 ccxt:1;
|
||||
u32 txrate_fb_lmt:5;
|
||||
u32 rtsrate_fb_lmt:4;
|
||||
u32 retrylmt_en:1;
|
||||
u32 txretrylmt:6;
|
||||
u32 usb_txaggnum:8;
|
||||
|
||||
u32 txagca:5;
|
||||
u32 txagcb:5;
|
||||
u32 usemaxlen:1;
|
||||
u32 maxaggnum:5;
|
||||
u32 mcsg1maxlen:4;
|
||||
u32 mcsg2maxlen:4;
|
||||
u32 mcsg3maxlen:4;
|
||||
u32 mcs7sgimaxlen:4;
|
||||
|
||||
u32 txbuffersize:16;
|
||||
u32 sw_offset30:8;
|
||||
u32 sw_offset31:4;
|
||||
u32 rsvd1:1;
|
||||
u32 antsel_c:1;
|
||||
u32 null_0:1;
|
||||
u32 null_1:1;
|
||||
|
||||
u32 txbuffaddr;
|
||||
u32 txbufferaddr64;
|
||||
u32 nextdescaddress;
|
||||
u32 nextdescaddress64;
|
||||
|
||||
u32 reserve_pass_pcie_mm_limit[4];
|
||||
} __packed;
|
||||
|
||||
struct rx_desc_8821ae {
|
||||
u32 length:14;
|
||||
u32 crc32:1;
|
||||
u32 icverror:1;
|
||||
u32 drv_infosize:4;
|
||||
u32 security:3;
|
||||
u32 qos:1;
|
||||
u32 shift:2;
|
||||
u32 phystatus:1;
|
||||
u32 swdec:1;
|
||||
u32 lastseg:1;
|
||||
u32 firstseg:1;
|
||||
u32 eor:1;
|
||||
u32 own:1;
|
||||
|
||||
u32 macid:6;
|
||||
u32 tid:4;
|
||||
u32 hwrsvd:5;
|
||||
u32 paggr:1;
|
||||
u32 faggr:1;
|
||||
u32 a1_fit:4;
|
||||
u32 a2_fit:4;
|
||||
u32 pam:1;
|
||||
u32 pwr:1;
|
||||
u32 moredata:1;
|
||||
u32 morefrag:1;
|
||||
u32 type:2;
|
||||
u32 mc:1;
|
||||
u32 bc:1;
|
||||
|
||||
u32 seq:12;
|
||||
u32 frag:4;
|
||||
u32 nextpktlen:14;
|
||||
u32 nextind:1;
|
||||
u32 rsvd:1;
|
||||
|
||||
u32 rxmcs:6;
|
||||
u32 rxht:1;
|
||||
u32 amsdu:1;
|
||||
u32 splcp:1;
|
||||
u32 bandwidth:1;
|
||||
u32 htc:1;
|
||||
u32 tcpchk_rpt:1;
|
||||
u32 ipcchk_rpt:1;
|
||||
u32 tcpchk_valid:1;
|
||||
u32 hwpcerr:1;
|
||||
u32 hwpcind:1;
|
||||
u32 iv0:16;
|
||||
|
||||
u32 iv1;
|
||||
|
||||
u32 tsfl;
|
||||
|
||||
u32 bufferaddress;
|
||||
u32 bufferaddress64;
|
||||
|
||||
} __packed;
|
||||
|
||||
void rtl8821ae_tx_fill_desc(struct ieee80211_hw *hw,
|
||||
struct ieee80211_hdr *hdr, u8 *pdesc_tx, u8 *txbd,
|
||||
struct ieee80211_tx_info *info,
|
||||
struct ieee80211_sta *sta,
|
||||
struct sk_buff *skb,
|
||||
u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
|
||||
bool rtl8821ae_rx_query_desc(struct ieee80211_hw *hw,
|
||||
struct rtl_stats *status,
|
||||
struct ieee80211_rx_status *rx_status,
|
||||
u8 *pdesc, struct sk_buff *skb);
|
||||
void rtl8821ae_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
|
||||
bool istx, u8 desc_name, u8 *val);
|
||||
u32 rtl8821ae_get_desc(u8 *pdesc, bool istx, u8 desc_name);
|
||||
bool rtl8821ae_is_tx_desc_closed(struct ieee80211_hw *hw,
|
||||
u8 hw_queue, u16 index);
|
||||
void rtl8821ae_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
|
||||
void rtl8821ae_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
|
||||
bool firstseg, bool lastseg,
|
||||
struct sk_buff *skb);
|
||||
u32 rtl8821ae_rx_command_packet(struct ieee80211_hw *hw,
|
||||
struct rtl_stats status,
|
||||
struct sk_buff *skb);
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue