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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
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108
drivers/pinctrl/freescale/Kconfig Normal file
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config PINCTRL_IMX
bool
select PINMUX
select PINCONF
config PINCTRL_IMX1_CORE
bool
select PINMUX
select PINCONF
config PINCTRL_IMX1
bool "IMX1 pinctrl driver"
depends on SOC_IMX1
select PINCTRL_IMX1_CORE
help
Say Y here to enable the imx1 pinctrl driver
config PINCTRL_IMX21
bool "i.MX21 pinctrl driver"
depends on SOC_IMX21
select PINCTRL_IMX1_CORE
help
Say Y here to enable the i.MX21 pinctrl driver
config PINCTRL_IMX27
bool "IMX27 pinctrl driver"
depends on SOC_IMX27
select PINCTRL_IMX1_CORE
help
Say Y here to enable the imx27 pinctrl driver
config PINCTRL_IMX25
bool "IMX25 pinctrl driver"
depends on OF
depends on SOC_IMX25
select PINCTRL_IMX
help
Say Y here to enable the imx25 pinctrl driver
config PINCTRL_IMX35
bool "IMX35 pinctrl driver"
depends on SOC_IMX35
select PINCTRL_IMX
help
Say Y here to enable the imx35 pinctrl driver
config PINCTRL_IMX50
bool "IMX50 pinctrl driver"
depends on SOC_IMX50
select PINCTRL_IMX
help
Say Y here to enable the imx50 pinctrl driver
config PINCTRL_IMX51
bool "IMX51 pinctrl driver"
depends on SOC_IMX51
select PINCTRL_IMX
help
Say Y here to enable the imx51 pinctrl driver
config PINCTRL_IMX53
bool "IMX53 pinctrl driver"
depends on SOC_IMX53
select PINCTRL_IMX
help
Say Y here to enable the imx53 pinctrl driver
config PINCTRL_IMX6Q
bool "IMX6Q/DL pinctrl driver"
depends on SOC_IMX6Q
select PINCTRL_IMX
help
Say Y here to enable the imx6q/dl pinctrl driver
config PINCTRL_IMX6SL
bool "IMX6SL pinctrl driver"
depends on SOC_IMX6SL
select PINCTRL_IMX
help
Say Y here to enable the imx6sl pinctrl driver
config PINCTRL_IMX6SX
bool "IMX6SX pinctrl driver"
depends on SOC_IMX6SX
select PINCTRL_IMX
help
Say Y here to enable the imx6sx pinctrl driver
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610
select PINCTRL_IMX
help
Say Y here to enable the Freescale Vybrid VF610 pinctrl driver
config PINCTRL_MXS
bool
select PINMUX
select PINCONF
config PINCTRL_IMX23
bool
select PINCTRL_MXS
config PINCTRL_IMX28
bool
select PINCTRL_MXS

19
drivers/pinctrl/freescale/Makefile Normal file
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# Freescale pin control drivers
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o
obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o
obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o

631
drivers/pinctrl/freescale/pinctrl-imx.c Normal file
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/*
* Core driver for the imx pin controller
*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* Author: Dong Aisheng <dong.aisheng@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include "../core.h"
#include "pinctrl-imx.h"
/* The bits in CONFIG cell defined in binding doc*/
#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
#define IMX_PAD_SION 0x40000000 /* set SION */
/**
* @dev: a pointer back to containing device
* @base: the offset to the controller in virtual memory
*/
struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
const struct imx_pinctrl_soc_info *info;
};
static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
const struct imx_pinctrl_soc_info *info,
const char *name)
{
const struct imx_pin_group *grp = NULL;
int i;
for (i = 0; i < info->ngroups; i++) {
if (!strcmp(info->groups[i].name, name)) {
grp = &info->groups[i];
break;
}
}
return grp;
}
static int imx_get_groups_count(struct pinctrl_dev *pctldev)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
return info->ngroups;
}
static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
return info->groups[selector].name;
}
static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
const unsigned **pins,
unsigned *npins)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
if (selector >= info->ngroups)
return -EINVAL;
*pins = info->groups[selector].pin_ids;
*npins = info->groups[selector].npins;
return 0;
}
static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned offset)
{
seq_printf(s, "%s", dev_name(pctldev->dev));
}
static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map, unsigned *num_maps)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_group *grp;
struct pinctrl_map *new_map;
struct device_node *parent;
int map_num = 1;
int i, j;
/*
* first find the group of this node and check if we need create
* config maps for pins
*/
grp = imx_pinctrl_find_group_by_name(info, np->name);
if (!grp) {
dev_err(info->dev, "unable to find group for node %s\n",
np->name);
return -EINVAL;
}
for (i = 0; i < grp->npins; i++) {
if (!(grp->pins[i].config & IMX_NO_PAD_CTL))
map_num++;
}
new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
if (!new_map)
return -ENOMEM;
*map = new_map;
*num_maps = map_num;
/* create mux map */
parent = of_get_parent(np);
if (!parent) {
kfree(new_map);
return -EINVAL;
}
new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
new_map[0].data.mux.function = parent->name;
new_map[0].data.mux.group = np->name;
of_node_put(parent);
/* create config map */
new_map++;
for (i = j = 0; i < grp->npins; i++) {
if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) {
new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
new_map[j].data.configs.group_or_pin =
pin_get_name(pctldev, grp->pins[i].pin);
new_map[j].data.configs.configs = &grp->pins[i].config;
new_map[j].data.configs.num_configs = 1;
j++;
}
}
dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
(*map)->data.mux.function, (*map)->data.mux.group, map_num);
return 0;
}
static void imx_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
kfree(map);
}
static const struct pinctrl_ops imx_pctrl_ops = {
.get_groups_count = imx_get_groups_count,
.get_group_name = imx_get_group_name,
.get_group_pins = imx_get_group_pins,
.pin_dbg_show = imx_pin_dbg_show,
.dt_node_to_map = imx_dt_node_to_map,
.dt_free_map = imx_dt_free_map,
};
static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
unsigned int npins, pin_id;
int i;
struct imx_pin_group *grp;
/*
* Configure the mux mode for each pin in the group for a specific
* function.
*/
grp = &info->groups[group];
npins = grp->npins;
dev_dbg(ipctl->dev, "enable function %s group %s\n",
info->functions[selector].name, grp->name);
for (i = 0; i < npins; i++) {
struct imx_pin *pin = &grp->pins[i];
pin_id = pin->pin;
pin_reg = &info->pin_regs[pin_id];
if (pin_reg->mux_reg == -1) {
dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
info->pins[pin_id].name);
return -EINVAL;
}
if (info->flags & SHARE_MUX_CONF_REG) {
u32 reg;
reg = readl(ipctl->base + pin_reg->mux_reg);
reg &= ~(0x7 << 20);
reg |= (pin->mux_mode << 20);
writel(reg, ipctl->base + pin_reg->mux_reg);
} else {
writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
}
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
pin_reg->mux_reg, pin->mux_mode);
/*
* If the select input value begins with 0xff, it's a quirky
* select input and the value should be interpreted as below.
* 31 23 15 7 0
* | 0xff | shift | width | select |
* It's used to work around the problem that the select
* input for some pin is not implemented in the select
* input register but in some general purpose register.
* We encode the select input value, width and shift of
* the bit field into input_val cell of pin function ID
* in device tree, and then decode them here for setting
* up the select input bits in general purpose register.
*/
if (pin->input_val >> 24 == 0xff) {
u32 val = pin->input_val;
u8 select = val & 0xff;
u8 width = (val >> 8) & 0xff;
u8 shift = (val >> 16) & 0xff;
u32 mask = ((1 << width) - 1) << shift;
/*
* The input_reg[i] here is actually some IOMUXC general
* purpose register, not regular select input register.
*/
val = readl(ipctl->base + pin->input_reg);
val &= ~mask;
val |= select << shift;
writel(val, ipctl->base + pin->input_reg);
} else if (pin->input_reg) {
/*
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
writel(pin->input_val, ipctl->base + pin->input_reg);
dev_dbg(ipctl->dev,
"==>select_input: offset 0x%x val 0x%x\n",
pin->input_reg, pin->input_val);
}
}
return 0;
}
static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
return info->nfunctions;
}
static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
return info->functions[selector].name;
}
static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
*groups = info->functions[selector].groups;
*num_groups = info->functions[selector].num_groups;
return 0;
}
static const struct pinmux_ops imx_pmx_ops = {
.get_functions_count = imx_pmx_get_funcs_count,
.get_function_name = imx_pmx_get_func_name,
.get_function_groups = imx_pmx_get_groups,
.set_mux = imx_pmx_set,
};
static int imx_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *config)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
if (pin_reg->conf_reg == -1) {
dev_err(info->dev, "Pin(%s) does not support config function\n",
info->pins[pin_id].name);
return -EINVAL;
}
*config = readl(ipctl->base + pin_reg->conf_reg);
if (info->flags & SHARE_MUX_CONF_REG)
*config &= 0xffff;
return 0;
}
static int imx_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *configs,
unsigned num_configs)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
int i;
if (pin_reg->conf_reg == -1) {
dev_err(info->dev, "Pin(%s) does not support config function\n",
info->pins[pin_id].name);
return -EINVAL;
}
dev_dbg(ipctl->dev, "pinconf set pin %s\n",
info->pins[pin_id].name);
for (i = 0; i < num_configs; i++) {
if (info->flags & SHARE_MUX_CONF_REG) {
u32 reg;
reg = readl(ipctl->base + pin_reg->conf_reg);
reg &= ~0xffff;
reg |= configs[i];
writel(reg, ipctl->base + pin_reg->conf_reg);
} else {
writel(configs[i], ipctl->base + pin_reg->conf_reg);
}
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
pin_reg->conf_reg, configs[i]);
} /* for each config */
return 0;
}
static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin_id)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
unsigned long config;
if (!pin_reg || pin_reg->conf_reg == -1) {
seq_printf(s, "N/A");
return;
}
config = readl(ipctl->base + pin_reg->conf_reg);
seq_printf(s, "0x%lx", config);
}
static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned group)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
struct imx_pin_group *grp;
unsigned long config;
const char *name;
int i, ret;
if (group > info->ngroups)
return;
seq_printf(s, "\n");
grp = &info->groups[group];
for (i = 0; i < grp->npins; i++) {
struct imx_pin *pin = &grp->pins[i];
name = pin_get_name(pctldev, pin->pin);
ret = imx_pinconf_get(pctldev, pin->pin, &config);
if (ret)
return;
seq_printf(s, "%s: 0x%lx", name, config);
}
}
static const struct pinconf_ops imx_pinconf_ops = {
.pin_config_get = imx_pinconf_get,
.pin_config_set = imx_pinconf_set,
.pin_config_dbg_show = imx_pinconf_dbg_show,
.pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
};
static struct pinctrl_desc imx_pinctrl_desc = {
.pctlops = &imx_pctrl_ops,
.pmxops = &imx_pmx_ops,
.confops = &imx_pinconf_ops,
.owner = THIS_MODULE,
};
/*
* Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
* 1 u32 CONFIG, so 24 types in total for each pin.
*/
#define FSL_PIN_SIZE 24
#define SHARE_FSL_PIN_SIZE 20
static int imx_pinctrl_parse_groups(struct device_node *np,
struct imx_pin_group *grp,
struct imx_pinctrl_soc_info *info,
u32 index)
{
int size, pin_size;
const __be32 *list;
int i;
u32 config;
dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
if (info->flags & SHARE_MUX_CONF_REG)
pin_size = SHARE_FSL_PIN_SIZE;
else
pin_size = FSL_PIN_SIZE;
/* Initialise group */
grp->name = np->name;
/*
* the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
* do sanity check and calculate pins number
*/
list = of_get_property(np, "fsl,pins", &size);
if (!list) {
dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name);
return -EINVAL;
}
/* we do not check return since it's safe node passed down */
if (!size || size % pin_size) {
dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name);
return -EINVAL;
}
grp->npins = size / pin_size;
grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(struct imx_pin),
GFP_KERNEL);
grp->pin_ids = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
GFP_KERNEL);
if (!grp->pins || ! grp->pin_ids)
return -ENOMEM;
for (i = 0; i < grp->npins; i++) {
u32 mux_reg = be32_to_cpu(*list++);
u32 conf_reg;
unsigned int pin_id;
struct imx_pin_reg *pin_reg;
struct imx_pin *pin = &grp->pins[i];
if (info->flags & SHARE_MUX_CONF_REG)
conf_reg = mux_reg;
else
conf_reg = be32_to_cpu(*list++);
pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
pin_reg = &info->pin_regs[pin_id];
pin->pin = pin_id;
grp->pin_ids[i] = pin_id;
pin_reg->mux_reg = mux_reg;
pin_reg->conf_reg = conf_reg;
pin->input_reg = be32_to_cpu(*list++);
pin->mux_mode = be32_to_cpu(*list++);
pin->input_val = be32_to_cpu(*list++);
/* SION bit is in mux register */
config = be32_to_cpu(*list++);
if (config & IMX_PAD_SION)
pin->mux_mode |= IOMUXC_CONFIG_SION;
pin->config = config & ~IMX_PAD_SION;
dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
pin->mux_mode, pin->config);
}
return 0;
}
static int imx_pinctrl_parse_functions(struct device_node *np,
struct imx_pinctrl_soc_info *info,
u32 index)
{
struct device_node *child;
struct imx_pmx_func *func;
struct imx_pin_group *grp;
static u32 grp_index;
u32 i = 0;
dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
func = &info->functions[index];
/* Initialise function */
func->name = np->name;
func->num_groups = of_get_child_count(np);
if (func->num_groups == 0) {
dev_err(info->dev, "no groups defined in %s\n", np->full_name);
return -EINVAL;
}
func->groups = devm_kzalloc(info->dev,
func->num_groups * sizeof(char *), GFP_KERNEL);
for_each_child_of_node(np, child) {
func->groups[i] = child->name;
grp = &info->groups[grp_index++];
imx_pinctrl_parse_groups(child, grp, info, i++);
}
return 0;
}
static int imx_pinctrl_probe_dt(struct platform_device *pdev,
struct imx_pinctrl_soc_info *info)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *child;
u32 nfuncs = 0;
u32 i = 0;
if (!np)
return -ENODEV;
nfuncs = of_get_child_count(np);
if (nfuncs <= 0) {
dev_err(&pdev->dev, "no functions defined\n");
return -EINVAL;
}
info->nfunctions = nfuncs;
info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
GFP_KERNEL);
if (!info->functions)
return -ENOMEM;
info->ngroups = 0;
for_each_child_of_node(np, child)
info->ngroups += of_get_child_count(child);
info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
GFP_KERNEL);
if (!info->groups)
return -ENOMEM;
for_each_child_of_node(np, child)
imx_pinctrl_parse_functions(child, info, i++);
return 0;
}
int imx_pinctrl_probe(struct platform_device *pdev,
struct imx_pinctrl_soc_info *info)
{
struct imx_pinctrl *ipctl;
struct resource *res;
int ret;
if (!info || !info->pins || !info->npins) {
dev_err(&pdev->dev, "wrong pinctrl info\n");
return -EINVAL;
}
info->dev = &pdev->dev;
/* Create state holders etc for this driver */
ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
if (!ipctl)
return -ENOMEM;
info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) *
info->npins, GFP_KERNEL);
if (!info->pin_regs)
return -ENOMEM;
memset(info->pin_regs, 0xff, sizeof(*info->pin_regs) * info->npins);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ipctl->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(ipctl->base))
return PTR_ERR(ipctl->base);
imx_pinctrl_desc.name = dev_name(&pdev->dev);
imx_pinctrl_desc.pins = info->pins;
imx_pinctrl_desc.npins = info->npins;
ret = imx_pinctrl_probe_dt(pdev, info);
if (ret) {
dev_err(&pdev->dev, "fail to probe dt properties\n");
return ret;
}
ipctl->info = info;
ipctl->dev = info->dev;
platform_set_drvdata(pdev, ipctl);
ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
if (!ipctl->pctl) {
dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
return -EINVAL;
}
dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
return 0;
}
int imx_pinctrl_remove(struct platform_device *pdev)
{
struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
pinctrl_unregister(ipctl->pctl);
return 0;
}

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drivers/pinctrl/freescale/pinctrl-imx.h Normal file
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/*
* IMX pinmux core definitions
*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* Author: Dong Aisheng <dong.aisheng@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DRIVERS_PINCTRL_IMX_H
#define __DRIVERS_PINCTRL_IMX_H
struct platform_device;
/**
* struct imx_pin_group - describes a single i.MX pin
* @pin: the pin_id of this pin
* @mux_mode: the mux mode for this pin.
* @input_reg: the select input register offset for this pin if any
* 0 if no select input setting needed.
* @input_val: the select input value for this pin.
* @configs: the config for this pin.
*/
struct imx_pin {
unsigned int pin;
unsigned int mux_mode;
u16 input_reg;
unsigned int input_val;
unsigned long config;
};
/**
* struct imx_pin_group - describes an IMX pin group
* @name: the name of this specific pin group
* @npins: the number of pins in this group array, i.e. the number of
* elements in .pins so we can iterate over that array
* @pin_ids: array of pin_ids. pinctrl forces us to maintain such an array
* @pins: array of pins
*/
struct imx_pin_group {
const char *name;
unsigned npins;
unsigned int *pin_ids;
struct imx_pin *pins;
};
/**
* struct imx_pmx_func - describes IMX pinmux functions
* @name: the name of this specific function
* @groups: corresponding pin groups
* @num_groups: the number of groups
*/
struct imx_pmx_func {
const char *name;
const char **groups;
unsigned num_groups;
};
/**
* struct imx_pin_reg - describe a pin reg map
* @mux_reg: mux register offset
* @conf_reg: config register offset
*/
struct imx_pin_reg {
s16 mux_reg;
s16 conf_reg;
};
struct imx_pinctrl_soc_info {
struct device *dev;
const struct pinctrl_pin_desc *pins;
unsigned int npins;
struct imx_pin_reg *pin_regs;
struct imx_pin_group *groups;
unsigned int ngroups;
struct imx_pmx_func *functions;
unsigned int nfunctions;
unsigned int flags;
};
#define SHARE_MUX_CONF_REG 0x1
#define NO_MUX 0x0
#define NO_PAD 0x0
#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
#define PAD_CTL_MASK(len) ((1 << len) - 1)
#define IMX_MUX_MASK 0x7
#define IOMUXC_CONFIG_SION (0x1 << 4)
int imx_pinctrl_probe(struct platform_device *pdev,
struct imx_pinctrl_soc_info *info);
int imx_pinctrl_remove(struct platform_device *pdev);
#endif /* __DRIVERS_PINCTRL_IMX_H */

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drivers/pinctrl/freescale/pinctrl-imx1-core.c Normal file
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/*
* Core driver for the imx pin controller in imx1/21/27
*
* Copyright (C) 2013 Pengutronix
* Author: Markus Pargmann <mpa@pengutronix.de>
*
* Based on pinctrl-imx.c:
* Author: Dong Aisheng <dong.aisheng@linaro.org>
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include "../core.h"
#include "pinctrl-imx1.h"
struct imx1_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
const struct imx1_pinctrl_soc_info *info;
};
/*
* MX1 register offsets
*/
#define MX1_DDIR 0x00
#define MX1_OCR 0x04
#define MX1_ICONFA 0x0c
#define MX1_ICONFB 0x14
#define MX1_GIUS 0x20
#define MX1_GPR 0x38
#define MX1_PUEN 0x40
#define MX1_PORT_STRIDE 0x100
/*
* MUX_ID format defines
*/
#define MX1_MUX_FUNCTION(val) (BIT(0) & val)
#define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
#define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
#define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
#define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
#define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
/*
* IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
* control register are seperated into function, output configuration, input
* configuration A, input configuration B, GPIO in use and data direction.
*
* Those controls that are represented by 1 bit have a direct mapping between
* bit position and pin id. If they are represented by 2 bit, the lower 16 pins
* are in the first register and the upper 16 pins in the second (next)
* register. pin_id is stored in bit (pin_id%16)*2 and the bit above.
*/
/*
* Calculates the register offset from a pin_id
*/
static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id)
{
unsigned int port = pin_id / 32;
return ipctl->base + port * MX1_PORT_STRIDE;
}
/*
* Write to a register with 2 bits per pin. The function will automatically
* use the next register if the pin is managed in the second register.
*/
static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
u32 value, u32 reg_offset)
{
void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
int offset = (pin_id % 16) * 2; /* offset, regardless of register used */
int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */
u32 old_val;
u32 new_val;
/* Use the next register if the pin's port pin number is >=16 */
if (pin_id % 32 >= 16)
reg += 0x04;
dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
reg, offset, value);
/* Get current state of pins */
old_val = readl(reg);
old_val &= mask;
new_val = value & 0x3; /* Make sure value is really 2 bit */
new_val <<= offset;
new_val |= old_val;/* Set new state for pin_id */
writel(new_val, reg);
}
static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
u32 value, u32 reg_offset)
{
void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
int offset = pin_id % 32;
int mask = ~BIT_MASK(offset);
u32 old_val;
u32 new_val;
/* Get current state of pins */
old_val = readl(reg);
old_val &= mask;
new_val = value & 0x1; /* Make sure value is really 1 bit */
new_val <<= offset;
new_val |= old_val;/* Set new state for pin_id */
writel(new_val, reg);
}
static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
u32 reg_offset)
{
void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
int offset = (pin_id % 16) * 2;
/* Use the next register if the pin's port pin number is >=16 */
if (pin_id % 32 >= 16)
reg += 0x04;
return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset;
}
static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
u32 reg_offset)
{
void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
int offset = pin_id % 32;
return !!(readl(reg) & BIT(offset));
}
static const inline struct imx1_pin_group *imx1_pinctrl_find_group_by_name(
const struct imx1_pinctrl_soc_info *info,
const char *name)
{
const struct imx1_pin_group *grp = NULL;
int i;
for (i = 0; i < info->ngroups; i++) {
if (!strcmp(info->groups[i].name, name)) {
grp = &info->groups[i];
break;
}
}
return grp;
}
static int imx1_get_groups_count(struct pinctrl_dev *pctldev)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
return info->ngroups;
}
static const char *imx1_get_group_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
return info->groups[selector].name;
}
static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
const unsigned int **pins,
unsigned *npins)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
if (selector >= info->ngroups)
return -EINVAL;
*pins = info->groups[selector].pin_ids;
*npins = info->groups[selector].npins;
return 0;
}
static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned offset)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d",
imx1_read_bit(ipctl, offset, MX1_GIUS),
imx1_read_bit(ipctl, offset, MX1_GPR),
imx1_read_bit(ipctl, offset, MX1_DDIR),
imx1_read_2bit(ipctl, offset, MX1_OCR),
imx1_read_2bit(ipctl, offset, MX1_ICONFA),
imx1_read_2bit(ipctl, offset, MX1_ICONFB));
}
static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map, unsigned *num_maps)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
const struct imx1_pin_group *grp;
struct pinctrl_map *new_map;
struct device_node *parent;
int map_num = 1;
int i, j;
/*
* first find the group of this node and check if we need create
* config maps for pins
*/
grp = imx1_pinctrl_find_group_by_name(info, np->name);
if (!grp) {
dev_err(info->dev, "unable to find group for node %s\n",
np->name);
return -EINVAL;
}
for (i = 0; i < grp->npins; i++)
map_num++;
new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
if (!new_map)
return -ENOMEM;
*map = new_map;
*num_maps = map_num;
/* create mux map */
parent = of_get_parent(np);
if (!parent) {
kfree(new_map);
return -EINVAL;
}
new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
new_map[0].data.mux.function = parent->name;
new_map[0].data.mux.group = np->name;
of_node_put(parent);
/* create config map */
new_map++;
for (i = j = 0; i < grp->npins; i++) {
new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
new_map[j].data.configs.group_or_pin =
pin_get_name(pctldev, grp->pins[i].pin_id);
new_map[j].data.configs.configs = &grp->pins[i].config;
new_map[j].data.configs.num_configs = 1;
j++;
}
dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
(*map)->data.mux.function, (*map)->data.mux.group, map_num);
return 0;
}
static void imx1_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
kfree(map);
}
static const struct pinctrl_ops imx1_pctrl_ops = {
.get_groups_count = imx1_get_groups_count,
.get_group_name = imx1_get_group_name,
.get_group_pins = imx1_get_group_pins,
.pin_dbg_show = imx1_pin_dbg_show,
.dt_node_to_map = imx1_dt_node_to_map,
.dt_free_map = imx1_dt_free_map,
};
static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
const struct imx1_pin *pins;
unsigned int npins;
int i;
/*
* Configure the mux mode for each pin in the group for a specific
* function.
*/
pins = info->groups[group].pins;
npins = info->groups[group].npins;
WARN_ON(!pins || !npins);
dev_dbg(ipctl->dev, "enable function %s group %s\n",
info->functions[selector].name, info->groups[group].name);
for (i = 0; i < npins; i++) {
unsigned int mux = pins[i].mux_id;
unsigned int pin_id = pins[i].pin_id;
unsigned int afunction = MX1_MUX_FUNCTION(mux);
unsigned int gpio_in_use = MX1_MUX_GPIO(mux);
unsigned int direction = MX1_MUX_DIR(mux);
unsigned int gpio_oconf = MX1_MUX_OCONF(mux);
unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux);
unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux);
dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n",
__func__, pin_id, afunction, gpio_in_use,
direction, gpio_oconf, gpio_iconfa,
gpio_iconfb);
imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
if (gpio_in_use) {
imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR);
imx1_write_2bit(ipctl, pin_id, gpio_iconfa,
MX1_ICONFA);
imx1_write_2bit(ipctl, pin_id, gpio_iconfb,
MX1_ICONFB);
} else {
imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR);
}
}
return 0;
}
static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
return info->nfunctions;
}
static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
return info->functions[selector].name;
}
static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
*groups = info->functions[selector].groups;
*num_groups = info->functions[selector].num_groups;
return 0;
}
static const struct pinmux_ops imx1_pmx_ops = {
.get_functions_count = imx1_pmx_get_funcs_count,
.get_function_name = imx1_pmx_get_func_name,
.get_function_groups = imx1_pmx_get_groups,
.set_mux = imx1_pmx_set,
};
static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *config)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
*config = imx1_read_bit(ipctl, pin_id, MX1_PUEN);
return 0;
}
static int imx1_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *configs,
unsigned num_configs)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
int i;
for (i = 0; i != num_configs; ++i) {
imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
info->pins[pin_id].name);
}
return 0;
}
static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin_id)
{
unsigned long config;
imx1_pinconf_get(pctldev, pin_id, &config);
seq_printf(s, "0x%lx", config);
}
static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned group)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
struct imx1_pin_group *grp;
unsigned long config;
const char *name;
int i, ret;
if (group > info->ngroups)
return;
seq_puts(s, "\n");
grp = &info->groups[group];
for (i = 0; i < grp->npins; i++) {
name = pin_get_name(pctldev, grp->pins[i].pin_id);
ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config);
if (ret)
return;
seq_printf(s, "%s: 0x%lx", name, config);
}
}
static const struct pinconf_ops imx1_pinconf_ops = {
.pin_config_get = imx1_pinconf_get,
.pin_config_set = imx1_pinconf_set,
.pin_config_dbg_show = imx1_pinconf_dbg_show,
.pin_config_group_dbg_show = imx1_pinconf_group_dbg_show,
};
static struct pinctrl_desc imx1_pinctrl_desc = {
.pctlops = &imx1_pctrl_ops,
.pmxops = &imx1_pmx_ops,
.confops = &imx1_pinconf_ops,
.owner = THIS_MODULE,
};
static int imx1_pinctrl_parse_groups(struct device_node *np,
struct imx1_pin_group *grp,
struct imx1_pinctrl_soc_info *info,
u32 index)
{
int size;
const __be32 *list;
int i;
dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
/* Initialise group */
grp->name = np->name;
/*
* the binding format is fsl,pins = <PIN MUX_ID CONFIG>
*/
list = of_get_property(np, "fsl,pins", &size);
/* we do not check return since it's safe node passed down */
if (!size || size % 12) {
dev_notice(info->dev, "Not a valid fsl,pins property (%s)\n",
np->name);
return -EINVAL;
}
grp->npins = size / 12;
grp->pins = devm_kzalloc(info->dev,
grp->npins * sizeof(struct imx1_pin), GFP_KERNEL);
grp->pin_ids = devm_kzalloc(info->dev,
grp->npins * sizeof(unsigned int), GFP_KERNEL);
if (!grp->pins || !grp->pin_ids)
return -ENOMEM;
for (i = 0; i < grp->npins; i++) {
grp->pins[i].pin_id = be32_to_cpu(*list++);
grp->pins[i].mux_id = be32_to_cpu(*list++);
grp->pins[i].config = be32_to_cpu(*list++);
grp->pin_ids[i] = grp->pins[i].pin_id;
}
return 0;
}
static int imx1_pinctrl_parse_functions(struct device_node *np,
struct imx1_pinctrl_soc_info *info,
u32 index)
{
struct device_node *child;
struct imx1_pmx_func *func;
struct imx1_pin_group *grp;
int ret;
static u32 grp_index;
u32 i = 0;
dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
func = &info->functions[index];
/* Initialise function */
func->name = np->name;
func->num_groups = of_get_child_count(np);
if (func->num_groups == 0)
return -EINVAL;
func->groups = devm_kzalloc(info->dev,
func->num_groups * sizeof(char *), GFP_KERNEL);
if (!func->groups)
return -ENOMEM;
for_each_child_of_node(np, child) {
func->groups[i] = child->name;
grp = &info->groups[grp_index++];
ret = imx1_pinctrl_parse_groups(child, grp, info, i++);
if (ret == -ENOMEM)
return ret;
}
return 0;
}
static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *child;
int ret;
u32 nfuncs = 0;
u32 ngroups = 0;
u32 ifunc = 0;
if (!np)
return -ENODEV;
for_each_child_of_node(np, child) {
++nfuncs;
ngroups += of_get_child_count(child);
}
if (!nfuncs) {
dev_err(&pdev->dev, "No pin functions defined\n");
return -EINVAL;
}
info->nfunctions = nfuncs;
info->functions = devm_kzalloc(&pdev->dev,
nfuncs * sizeof(struct imx1_pmx_func), GFP_KERNEL);
info->ngroups = ngroups;
info->groups = devm_kzalloc(&pdev->dev,
ngroups * sizeof(struct imx1_pin_group), GFP_KERNEL);
if (!info->functions || !info->groups)
return -ENOMEM;
for_each_child_of_node(np, child) {
ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
if (ret == -ENOMEM)
return -ENOMEM;
}
return 0;
}
int imx1_pinctrl_core_probe(struct platform_device *pdev,
struct imx1_pinctrl_soc_info *info)
{
struct imx1_pinctrl *ipctl;
struct resource *res;
struct pinctrl_desc *pctl_desc;
int ret;
if (!info || !info->pins || !info->npins) {
dev_err(&pdev->dev, "wrong pinctrl info\n");
return -EINVAL;
}
info->dev = &pdev->dev;
/* Create state holders etc for this driver */
ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
if (!ipctl)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENOENT;
ipctl->base = devm_ioremap_nocache(&pdev->dev, res->start,
resource_size(res));
if (!ipctl->base)
return -ENOMEM;
pctl_desc = &imx1_pinctrl_desc;
pctl_desc->name = dev_name(&pdev->dev);
pctl_desc->pins = info->pins;
pctl_desc->npins = info->npins;
ret = imx1_pinctrl_parse_dt(pdev, ipctl, info);
if (ret) {
dev_err(&pdev->dev, "fail to probe dt properties\n");
return ret;
}
ipctl->info = info;
ipctl->dev = info->dev;
platform_set_drvdata(pdev, ipctl);
ipctl->pctl = pinctrl_register(pctl_desc, &pdev->dev, ipctl);
if (!ipctl->pctl) {
dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
return -EINVAL;
}
ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
if (ret) {
pinctrl_unregister(ipctl->pctl);
dev_err(&pdev->dev, "Failed to populate subdevices\n");
return ret;
}
dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
return 0;
}
int imx1_pinctrl_core_remove(struct platform_device *pdev)
{
struct imx1_pinctrl *ipctl = platform_get_drvdata(pdev);
pinctrl_unregister(ipctl->pctl);
return 0;
}

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/*
* i.MX1 pinctrl driver based on imx pinmux core
*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx1.h"
#define PAD_ID(port, pin) ((port) * 32 + (pin))
#define PA 0
#define PB 1
#define PC 2
#define PD 3
enum imx1_pads {
MX1_PAD_A24 = PAD_ID(PA, 0),
MX1_PAD_TIN = PAD_ID(PA, 1),
MX1_PAD_PWMO = PAD_ID(PA, 2),
MX1_PAD_CSI_MCLK = PAD_ID(PA, 3),
MX1_PAD_CSI_D0 = PAD_ID(PA, 4),
MX1_PAD_CSI_D1 = PAD_ID(PA, 5),
MX1_PAD_CSI_D2 = PAD_ID(PA, 6),
MX1_PAD_CSI_D3 = PAD_ID(PA, 7),
MX1_PAD_CSI_D4 = PAD_ID(PA, 8),
MX1_PAD_CSI_D5 = PAD_ID(PA, 9),
MX1_PAD_CSI_D6 = PAD_ID(PA, 10),
MX1_PAD_CSI_D7 = PAD_ID(PA, 11),
MX1_PAD_CSI_VSYNC = PAD_ID(PA, 12),
MX1_PAD_CSI_HSYNC = PAD_ID(PA, 13),
MX1_PAD_CSI_PIXCLK = PAD_ID(PA, 14),
MX1_PAD_I2C_SDA = PAD_ID(PA, 15),
MX1_PAD_I2C_SCL = PAD_ID(PA, 16),
MX1_PAD_DTACK = PAD_ID(PA, 17),
MX1_PAD_BCLK = PAD_ID(PA, 18),
MX1_PAD_LBA = PAD_ID(PA, 19),
MX1_PAD_ECB = PAD_ID(PA, 20),
MX1_PAD_A0 = PAD_ID(PA, 21),
MX1_PAD_CS4 = PAD_ID(PA, 22),
MX1_PAD_CS5 = PAD_ID(PA, 23),
MX1_PAD_A16 = PAD_ID(PA, 24),
MX1_PAD_A17 = PAD_ID(PA, 25),
MX1_PAD_A18 = PAD_ID(PA, 26),
MX1_PAD_A19 = PAD_ID(PA, 27),
MX1_PAD_A20 = PAD_ID(PA, 28),
MX1_PAD_A21 = PAD_ID(PA, 29),
MX1_PAD_A22 = PAD_ID(PA, 30),
MX1_PAD_A23 = PAD_ID(PA, 31),
MX1_PAD_SD_DAT0 = PAD_ID(PB, 8),
MX1_PAD_SD_DAT1 = PAD_ID(PB, 9),
MX1_PAD_SD_DAT2 = PAD_ID(PB, 10),
MX1_PAD_SD_DAT3 = PAD_ID(PB, 11),
MX1_PAD_SD_SCLK = PAD_ID(PB, 12),
MX1_PAD_SD_CMD = PAD_ID(PB, 13),
MX1_PAD_SIM_SVEN = PAD_ID(PB, 14),
MX1_PAD_SIM_PD = PAD_ID(PB, 15),
MX1_PAD_SIM_TX = PAD_ID(PB, 16),
MX1_PAD_SIM_RX = PAD_ID(PB, 17),
MX1_PAD_SIM_RST = PAD_ID(PB, 18),
MX1_PAD_SIM_CLK = PAD_ID(PB, 19),
MX1_PAD_USBD_AFE = PAD_ID(PB, 20),
MX1_PAD_USBD_OE = PAD_ID(PB, 21),
MX1_PAD_USBD_RCV = PAD_ID(PB, 22),
MX1_PAD_USBD_SUSPND = PAD_ID(PB, 23),
MX1_PAD_USBD_VP = PAD_ID(PB, 24),
MX1_PAD_USBD_VM = PAD_ID(PB, 25),
MX1_PAD_USBD_VPO = PAD_ID(PB, 26),
MX1_PAD_USBD_VMO = PAD_ID(PB, 27),
MX1_PAD_UART2_CTS = PAD_ID(PB, 28),
MX1_PAD_UART2_RTS = PAD_ID(PB, 29),
MX1_PAD_UART2_TXD = PAD_ID(PB, 30),
MX1_PAD_UART2_RXD = PAD_ID(PB, 31),
MX1_PAD_SSI_RXFS = PAD_ID(PC, 3),
MX1_PAD_SSI_RXCLK = PAD_ID(PC, 4),
MX1_PAD_SSI_RXDAT = PAD_ID(PC, 5),
MX1_PAD_SSI_TXDAT = PAD_ID(PC, 6),
MX1_PAD_SSI_TXFS = PAD_ID(PC, 7),
MX1_PAD_SSI_TXCLK = PAD_ID(PC, 8),
MX1_PAD_UART1_CTS = PAD_ID(PC, 9),
MX1_PAD_UART1_RTS = PAD_ID(PC, 10),
MX1_PAD_UART1_TXD = PAD_ID(PC, 11),
MX1_PAD_UART1_RXD = PAD_ID(PC, 12),
MX1_PAD_SPI1_RDY = PAD_ID(PC, 13),
MX1_PAD_SPI1_SCLK = PAD_ID(PC, 14),
MX1_PAD_SPI1_SS = PAD_ID(PC, 15),
MX1_PAD_SPI1_MISO = PAD_ID(PC, 16),
MX1_PAD_SPI1_MOSI = PAD_ID(PC, 17),
MX1_PAD_BT13 = PAD_ID(PC, 19),
MX1_PAD_BT12 = PAD_ID(PC, 20),
MX1_PAD_BT11 = PAD_ID(PC, 21),
MX1_PAD_BT10 = PAD_ID(PC, 22),
MX1_PAD_BT9 = PAD_ID(PC, 23),
MX1_PAD_BT8 = PAD_ID(PC, 24),
MX1_PAD_BT7 = PAD_ID(PC, 25),
MX1_PAD_BT6 = PAD_ID(PC, 26),
MX1_PAD_BT5 = PAD_ID(PC, 27),
MX1_PAD_BT4 = PAD_ID(PC, 28),
MX1_PAD_BT3 = PAD_ID(PC, 29),
MX1_PAD_BT2 = PAD_ID(PC, 30),
MX1_PAD_BT1 = PAD_ID(PC, 31),
MX1_PAD_LSCLK = PAD_ID(PD, 6),
MX1_PAD_REV = PAD_ID(PD, 7),
MX1_PAD_CLS = PAD_ID(PD, 8),
MX1_PAD_PS = PAD_ID(PD, 9),
MX1_PAD_SPL_SPR = PAD_ID(PD, 10),
MX1_PAD_CONTRAST = PAD_ID(PD, 11),
MX1_PAD_ACD_OE = PAD_ID(PD, 12),
MX1_PAD_LP_HSYNC = PAD_ID(PD, 13),
MX1_PAD_FLM_VSYNC = PAD_ID(PD, 14),
MX1_PAD_LD0 = PAD_ID(PD, 15),
MX1_PAD_LD1 = PAD_ID(PD, 16),
MX1_PAD_LD2 = PAD_ID(PD, 17),
MX1_PAD_LD3 = PAD_ID(PD, 18),
MX1_PAD_LD4 = PAD_ID(PD, 19),
MX1_PAD_LD5 = PAD_ID(PD, 20),
MX1_PAD_LD6 = PAD_ID(PD, 21),
MX1_PAD_LD7 = PAD_ID(PD, 22),
MX1_PAD_LD8 = PAD_ID(PD, 23),
MX1_PAD_LD9 = PAD_ID(PD, 24),
MX1_PAD_LD10 = PAD_ID(PD, 25),
MX1_PAD_LD11 = PAD_ID(PD, 26),
MX1_PAD_LD12 = PAD_ID(PD, 27),
MX1_PAD_LD13 = PAD_ID(PD, 28),
MX1_PAD_LD14 = PAD_ID(PD, 29),
MX1_PAD_LD15 = PAD_ID(PD, 30),
MX1_PAD_TMR2OUT = PAD_ID(PD, 31),
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx1_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX1_PAD_A24),
IMX_PINCTRL_PIN(MX1_PAD_TIN),
IMX_PINCTRL_PIN(MX1_PAD_PWMO),
IMX_PINCTRL_PIN(MX1_PAD_CSI_MCLK),
IMX_PINCTRL_PIN(MX1_PAD_CSI_D0),
IMX_PINCTRL_PIN(MX1_PAD_CSI_D1),
IMX_PINCTRL_PIN(MX1_PAD_CSI_D2),
IMX_PINCTRL_PIN(MX1_PAD_CSI_D3),
IMX_PINCTRL_PIN(MX1_PAD_CSI_D4),
IMX_PINCTRL_PIN(MX1_PAD_CSI_D5),
IMX_PINCTRL_PIN(MX1_PAD_CSI_D6),
IMX_PINCTRL_PIN(MX1_PAD_CSI_D7),
IMX_PINCTRL_PIN(MX1_PAD_CSI_VSYNC),
IMX_PINCTRL_PIN(MX1_PAD_CSI_HSYNC),
IMX_PINCTRL_PIN(MX1_PAD_CSI_PIXCLK),
IMX_PINCTRL_PIN(MX1_PAD_I2C_SDA),
IMX_PINCTRL_PIN(MX1_PAD_I2C_SCL),
IMX_PINCTRL_PIN(MX1_PAD_DTACK),
IMX_PINCTRL_PIN(MX1_PAD_BCLK),
IMX_PINCTRL_PIN(MX1_PAD_LBA),
IMX_PINCTRL_PIN(MX1_PAD_ECB),
IMX_PINCTRL_PIN(MX1_PAD_A0),
IMX_PINCTRL_PIN(MX1_PAD_CS4),
IMX_PINCTRL_PIN(MX1_PAD_CS5),
IMX_PINCTRL_PIN(MX1_PAD_A16),
IMX_PINCTRL_PIN(MX1_PAD_A17),
IMX_PINCTRL_PIN(MX1_PAD_A18),
IMX_PINCTRL_PIN(MX1_PAD_A19),
IMX_PINCTRL_PIN(MX1_PAD_A20),
IMX_PINCTRL_PIN(MX1_PAD_A21),
IMX_PINCTRL_PIN(MX1_PAD_A22),
IMX_PINCTRL_PIN(MX1_PAD_A23),
IMX_PINCTRL_PIN(MX1_PAD_SD_DAT0),
IMX_PINCTRL_PIN(MX1_PAD_SD_DAT1),
IMX_PINCTRL_PIN(MX1_PAD_SD_DAT2),
IMX_PINCTRL_PIN(MX1_PAD_SD_DAT3),
IMX_PINCTRL_PIN(MX1_PAD_SD_SCLK),
IMX_PINCTRL_PIN(MX1_PAD_SD_CMD),
IMX_PINCTRL_PIN(MX1_PAD_SIM_SVEN),
IMX_PINCTRL_PIN(MX1_PAD_SIM_PD),
IMX_PINCTRL_PIN(MX1_PAD_SIM_TX),
IMX_PINCTRL_PIN(MX1_PAD_SIM_RX),
IMX_PINCTRL_PIN(MX1_PAD_SIM_CLK),
IMX_PINCTRL_PIN(MX1_PAD_USBD_AFE),
IMX_PINCTRL_PIN(MX1_PAD_USBD_OE),
IMX_PINCTRL_PIN(MX1_PAD_USBD_RCV),
IMX_PINCTRL_PIN(MX1_PAD_USBD_SUSPND),
IMX_PINCTRL_PIN(MX1_PAD_USBD_VP),
IMX_PINCTRL_PIN(MX1_PAD_USBD_VM),
IMX_PINCTRL_PIN(MX1_PAD_USBD_VPO),
IMX_PINCTRL_PIN(MX1_PAD_USBD_VMO),
IMX_PINCTRL_PIN(MX1_PAD_UART2_CTS),
IMX_PINCTRL_PIN(MX1_PAD_UART2_RTS),
IMX_PINCTRL_PIN(MX1_PAD_UART2_TXD),
IMX_PINCTRL_PIN(MX1_PAD_UART2_RXD),
IMX_PINCTRL_PIN(MX1_PAD_SSI_RXFS),
IMX_PINCTRL_PIN(MX1_PAD_SSI_RXCLK),
IMX_PINCTRL_PIN(MX1_PAD_SSI_RXDAT),
IMX_PINCTRL_PIN(MX1_PAD_SSI_TXDAT),
IMX_PINCTRL_PIN(MX1_PAD_SSI_TXFS),
IMX_PINCTRL_PIN(MX1_PAD_SSI_TXCLK),
IMX_PINCTRL_PIN(MX1_PAD_UART1_CTS),
IMX_PINCTRL_PIN(MX1_PAD_UART1_RTS),
IMX_PINCTRL_PIN(MX1_PAD_UART1_TXD),
IMX_PINCTRL_PIN(MX1_PAD_UART1_RXD),
IMX_PINCTRL_PIN(MX1_PAD_SPI1_RDY),
IMX_PINCTRL_PIN(MX1_PAD_SPI1_SCLK),
IMX_PINCTRL_PIN(MX1_PAD_SPI1_SS),
IMX_PINCTRL_PIN(MX1_PAD_SPI1_MISO),
IMX_PINCTRL_PIN(MX1_PAD_SPI1_MOSI),
IMX_PINCTRL_PIN(MX1_PAD_BT13),
IMX_PINCTRL_PIN(MX1_PAD_BT12),
IMX_PINCTRL_PIN(MX1_PAD_BT11),
IMX_PINCTRL_PIN(MX1_PAD_BT10),
IMX_PINCTRL_PIN(MX1_PAD_BT9),
IMX_PINCTRL_PIN(MX1_PAD_BT8),
IMX_PINCTRL_PIN(MX1_PAD_BT7),
IMX_PINCTRL_PIN(MX1_PAD_BT6),
IMX_PINCTRL_PIN(MX1_PAD_BT5),
IMX_PINCTRL_PIN(MX1_PAD_BT4),
IMX_PINCTRL_PIN(MX1_PAD_BT3),
IMX_PINCTRL_PIN(MX1_PAD_BT2),
IMX_PINCTRL_PIN(MX1_PAD_BT1),
IMX_PINCTRL_PIN(MX1_PAD_LSCLK),
IMX_PINCTRL_PIN(MX1_PAD_REV),
IMX_PINCTRL_PIN(MX1_PAD_CLS),
IMX_PINCTRL_PIN(MX1_PAD_PS),
IMX_PINCTRL_PIN(MX1_PAD_SPL_SPR),
IMX_PINCTRL_PIN(MX1_PAD_CONTRAST),
IMX_PINCTRL_PIN(MX1_PAD_ACD_OE),
IMX_PINCTRL_PIN(MX1_PAD_LP_HSYNC),
IMX_PINCTRL_PIN(MX1_PAD_FLM_VSYNC),
IMX_PINCTRL_PIN(MX1_PAD_LD0),
IMX_PINCTRL_PIN(MX1_PAD_LD1),
IMX_PINCTRL_PIN(MX1_PAD_LD2),
IMX_PINCTRL_PIN(MX1_PAD_LD3),
IMX_PINCTRL_PIN(MX1_PAD_LD4),
IMX_PINCTRL_PIN(MX1_PAD_LD5),
IMX_PINCTRL_PIN(MX1_PAD_LD6),
IMX_PINCTRL_PIN(MX1_PAD_LD7),
IMX_PINCTRL_PIN(MX1_PAD_LD8),
IMX_PINCTRL_PIN(MX1_PAD_LD9),
IMX_PINCTRL_PIN(MX1_PAD_LD10),
IMX_PINCTRL_PIN(MX1_PAD_LD11),
IMX_PINCTRL_PIN(MX1_PAD_LD12),
IMX_PINCTRL_PIN(MX1_PAD_LD13),
IMX_PINCTRL_PIN(MX1_PAD_LD14),
IMX_PINCTRL_PIN(MX1_PAD_LD15),
IMX_PINCTRL_PIN(MX1_PAD_TMR2OUT),
};
static struct imx1_pinctrl_soc_info imx1_pinctrl_info = {
.pins = imx1_pinctrl_pads,
.npins = ARRAY_SIZE(imx1_pinctrl_pads),
};
static int __init imx1_pinctrl_probe(struct platform_device *pdev)
{
return imx1_pinctrl_core_probe(pdev, &imx1_pinctrl_info);
}
static const struct of_device_id imx1_pinctrl_of_match[] = {
{ .compatible = "fsl,imx1-iomuxc", },
{ }
};
MODULE_DEVICE_TABLE(of, imx1_pinctrl_of_match);
static struct platform_driver imx1_pinctrl_driver = {
.driver = {
.name = "imx1-pinctrl",
.owner = THIS_MODULE,
.of_match_table = imx1_pinctrl_of_match,
},
.remove = imx1_pinctrl_core_remove,
};
module_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe);
MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
MODULE_DESCRIPTION("Freescale i.MX1 pinctrl driver");
MODULE_LICENSE("GPL");

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drivers/pinctrl/freescale/pinctrl-imx1.h Normal file
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/*
* IMX pinmux core definitions
*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* Author: Dong Aisheng <dong.aisheng@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DRIVERS_PINCTRL_IMX1_H
#define __DRIVERS_PINCTRL_IMX1_H
struct platform_device;
/**
* struct imx1_pin - describes an IMX1/21/27 pin.
* @pin_id: ID of the described pin.
* @mux_id: ID of the mux setup.
* @config: Configuration of the pin (currently only pullup-enable).
*/
struct imx1_pin {
unsigned int pin_id;
unsigned int mux_id;
unsigned long config;
};
/**
* struct imx1_pin_group - describes an IMX pin group
* @name: the name of this specific pin group
* @pins: an array of imx1_pin structs used in this group
* @npins: the number of pins in this group array, i.e. the number of
* elements in .pins so we can iterate over that array
*/
struct imx1_pin_group {
const char *name;
unsigned int *pin_ids;
struct imx1_pin *pins;
unsigned npins;
};
/**
* struct imx1_pmx_func - describes IMX pinmux functions
* @name: the name of this specific function
* @groups: corresponding pin groups
* @num_groups: the number of groups
*/
struct imx1_pmx_func {
const char *name;
const char **groups;
unsigned num_groups;
};
struct imx1_pinctrl_soc_info {
struct device *dev;
const struct pinctrl_pin_desc *pins;
unsigned int npins;
struct imx1_pin_group *groups;
unsigned int ngroups;
struct imx1_pmx_func *functions;
unsigned int nfunctions;
};
#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
int imx1_pinctrl_core_probe(struct platform_device *pdev,
struct imx1_pinctrl_soc_info *info);
int imx1_pinctrl_core_remove(struct platform_device *pdev);
#endif /* __DRIVERS_PINCTRL_IMX1_H */

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/*
* i.MX21 pinctrl driver based on imx pinmux core
*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx1.h"
#define PAD_ID(port, pin) ((port) * 32 + (pin))
#define PA 0
#define PB 1
#define PC 2
#define PD 3
#define PE 4
#define PF 5
enum imx21_pads {
MX21_PAD_LSCLK = PAD_ID(PA, 5),
MX21_PAD_LD0 = PAD_ID(PA, 6),
MX21_PAD_LD1 = PAD_ID(PA, 7),
MX21_PAD_LD2 = PAD_ID(PA, 8),
MX21_PAD_LD3 = PAD_ID(PA, 9),
MX21_PAD_LD4 = PAD_ID(PA, 10),
MX21_PAD_LD5 = PAD_ID(PA, 11),
MX21_PAD_LD6 = PAD_ID(PA, 12),
MX21_PAD_LD7 = PAD_ID(PA, 13),
MX21_PAD_LD8 = PAD_ID(PA, 14),
MX21_PAD_LD9 = PAD_ID(PA, 15),
MX21_PAD_LD10 = PAD_ID(PA, 16),
MX21_PAD_LD11 = PAD_ID(PA, 17),
MX21_PAD_LD12 = PAD_ID(PA, 18),
MX21_PAD_LD13 = PAD_ID(PA, 19),
MX21_PAD_LD14 = PAD_ID(PA, 20),
MX21_PAD_LD15 = PAD_ID(PA, 21),
MX21_PAD_LD16 = PAD_ID(PA, 22),
MX21_PAD_LD17 = PAD_ID(PA, 23),
MX21_PAD_REV = PAD_ID(PA, 24),
MX21_PAD_CLS = PAD_ID(PA, 25),
MX21_PAD_PS = PAD_ID(PA, 26),
MX21_PAD_SPL_SPR = PAD_ID(PA, 27),
MX21_PAD_HSYNC = PAD_ID(PA, 28),
MX21_PAD_VSYNC = PAD_ID(PA, 29),
MX21_PAD_CONTRAST = PAD_ID(PA, 30),
MX21_PAD_OE_ACD = PAD_ID(PA, 31),
MX21_PAD_SD2_D0 = PAD_ID(PB, 4),
MX21_PAD_SD2_D1 = PAD_ID(PB, 5),
MX21_PAD_SD2_D2 = PAD_ID(PB, 6),
MX21_PAD_SD2_D3 = PAD_ID(PB, 7),
MX21_PAD_SD2_CMD = PAD_ID(PB, 8),
MX21_PAD_SD2_CLK = PAD_ID(PB, 9),
MX21_PAD_CSI_D0 = PAD_ID(PB, 10),
MX21_PAD_CSI_D1 = PAD_ID(PB, 11),
MX21_PAD_CSI_D2 = PAD_ID(PB, 12),
MX21_PAD_CSI_D3 = PAD_ID(PB, 13),
MX21_PAD_CSI_D4 = PAD_ID(PB, 14),
MX21_PAD_CSI_MCLK = PAD_ID(PB, 15),
MX21_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
MX21_PAD_CSI_D5 = PAD_ID(PB, 17),
MX21_PAD_CSI_D6 = PAD_ID(PB, 18),
MX21_PAD_CSI_D7 = PAD_ID(PB, 19),
MX21_PAD_CSI_VSYNC = PAD_ID(PB, 20),
MX21_PAD_CSI_HSYNC = PAD_ID(PB, 21),
MX21_PAD_USB_BYP = PAD_ID(PB, 22),
MX21_PAD_USB_PWR = PAD_ID(PB, 23),
MX21_PAD_USB_OC = PAD_ID(PB, 24),
MX21_PAD_USBH_ON = PAD_ID(PB, 25),
MX21_PAD_USBH1_FS = PAD_ID(PB, 26),
MX21_PAD_USBH1_OE = PAD_ID(PB, 27),
MX21_PAD_USBH1_TXDM = PAD_ID(PB, 28),
MX21_PAD_USBH1_TXDP = PAD_ID(PB, 29),
MX21_PAD_USBH1_RXDM = PAD_ID(PB, 30),
MX21_PAD_USBH1_RXDP = PAD_ID(PB, 31),
MX21_PAD_USBG_SDA = PAD_ID(PC, 5),
MX21_PAD_USBG_SCL = PAD_ID(PC, 6),
MX21_PAD_USBG_ON = PAD_ID(PC, 7),
MX21_PAD_USBG_FS = PAD_ID(PC, 8),
MX21_PAD_USBG_OE = PAD_ID(PC, 9),
MX21_PAD_USBG_TXDM = PAD_ID(PC, 10),
MX21_PAD_USBG_TXDP = PAD_ID(PC, 11),
MX21_PAD_USBG_RXDM = PAD_ID(PC, 12),
MX21_PAD_USBG_RXDP = PAD_ID(PC, 13),
MX21_PAD_TOUT = PAD_ID(PC, 14),
MX21_PAD_TIN = PAD_ID(PC, 15),
MX21_PAD_SAP_FS = PAD_ID(PC, 16),
MX21_PAD_SAP_RXD = PAD_ID(PC, 17),
MX21_PAD_SAP_TXD = PAD_ID(PC, 18),
MX21_PAD_SAP_CLK = PAD_ID(PC, 19),
MX21_PAD_SSI1_FS = PAD_ID(PC, 20),
MX21_PAD_SSI1_RXD = PAD_ID(PC, 21),
MX21_PAD_SSI1_TXD = PAD_ID(PC, 22),
MX21_PAD_SSI1_CLK = PAD_ID(PC, 23),
MX21_PAD_SSI2_FS = PAD_ID(PC, 24),
MX21_PAD_SSI2_RXD = PAD_ID(PC, 25),
MX21_PAD_SSI2_TXD = PAD_ID(PC, 26),
MX21_PAD_SSI2_CLK = PAD_ID(PC, 27),
MX21_PAD_SSI3_FS = PAD_ID(PC, 28),
MX21_PAD_SSI3_RXD = PAD_ID(PC, 29),
MX21_PAD_SSI3_TXD = PAD_ID(PC, 30),
MX21_PAD_SSI3_CLK = PAD_ID(PC, 31),
MX21_PAD_I2C_DATA = PAD_ID(PD, 17),
MX21_PAD_I2C_CLK = PAD_ID(PD, 18),
MX21_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
MX21_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
MX21_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
MX21_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
MX21_PAD_CSPI2_MISO = PAD_ID(PD, 23),
MX21_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
MX21_PAD_CSPI1_RDY = PAD_ID(PD, 25),
MX21_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
MX21_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
MX21_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
MX21_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
MX21_PAD_CSPI1_MISO = PAD_ID(PD, 30),
MX21_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
MX21_PAD_TEST_WB2 = PAD_ID(PE, 0),
MX21_PAD_TEST_WB1 = PAD_ID(PE, 1),
MX21_PAD_TEST_WB0 = PAD_ID(PE, 2),
MX21_PAD_UART2_CTS = PAD_ID(PE, 3),
MX21_PAD_UART2_RTS = PAD_ID(PE, 4),
MX21_PAD_PWMO = PAD_ID(PE, 5),
MX21_PAD_UART2_TXD = PAD_ID(PE, 6),
MX21_PAD_UART2_RXD = PAD_ID(PE, 7),
MX21_PAD_UART3_TXD = PAD_ID(PE, 8),
MX21_PAD_UART3_RXD = PAD_ID(PE, 9),
MX21_PAD_UART3_CTS = PAD_ID(PE, 10),
MX21_PAD_UART3_RTS = PAD_ID(PE, 11),
MX21_PAD_UART1_TXD = PAD_ID(PE, 12),
MX21_PAD_UART1_RXD = PAD_ID(PE, 13),
MX21_PAD_UART1_CTS = PAD_ID(PE, 14),
MX21_PAD_UART1_RTS = PAD_ID(PE, 15),
MX21_PAD_RTCK = PAD_ID(PE, 16),
MX21_PAD_RESET_OUT = PAD_ID(PE, 17),
MX21_PAD_SD1_D0 = PAD_ID(PE, 18),
MX21_PAD_SD1_D1 = PAD_ID(PE, 19),
MX21_PAD_SD1_D2 = PAD_ID(PE, 20),
MX21_PAD_SD1_D3 = PAD_ID(PE, 21),
MX21_PAD_SD1_CMD = PAD_ID(PE, 22),
MX21_PAD_SD1_CLK = PAD_ID(PE, 23),
MX21_PAD_NFRB = PAD_ID(PF, 0),
MX21_PAD_NFCE = PAD_ID(PF, 1),
MX21_PAD_NFWP = PAD_ID(PF, 2),
MX21_PAD_NFCLE = PAD_ID(PF, 3),
MX21_PAD_NFALE = PAD_ID(PF, 4),
MX21_PAD_NFRE = PAD_ID(PF, 5),
MX21_PAD_NFWE = PAD_ID(PF, 6),
MX21_PAD_NFIO0 = PAD_ID(PF, 7),
MX21_PAD_NFIO1 = PAD_ID(PF, 8),
MX21_PAD_NFIO2 = PAD_ID(PF, 9),
MX21_PAD_NFIO3 = PAD_ID(PF, 10),
MX21_PAD_NFIO4 = PAD_ID(PF, 11),
MX21_PAD_NFIO5 = PAD_ID(PF, 12),
MX21_PAD_NFIO6 = PAD_ID(PF, 13),
MX21_PAD_NFIO7 = PAD_ID(PF, 14),
MX21_PAD_CLKO = PAD_ID(PF, 15),
MX21_PAD_RESERVED = PAD_ID(PF, 16),
MX21_PAD_CS4 = PAD_ID(PF, 21),
MX21_PAD_CS5 = PAD_ID(PF, 22),
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx21_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX21_PAD_LSCLK),
IMX_PINCTRL_PIN(MX21_PAD_LD0),
IMX_PINCTRL_PIN(MX21_PAD_LD1),
IMX_PINCTRL_PIN(MX21_PAD_LD2),
IMX_PINCTRL_PIN(MX21_PAD_LD3),
IMX_PINCTRL_PIN(MX21_PAD_LD4),
IMX_PINCTRL_PIN(MX21_PAD_LD5),
IMX_PINCTRL_PIN(MX21_PAD_LD6),
IMX_PINCTRL_PIN(MX21_PAD_LD7),
IMX_PINCTRL_PIN(MX21_PAD_LD8),
IMX_PINCTRL_PIN(MX21_PAD_LD9),
IMX_PINCTRL_PIN(MX21_PAD_LD10),
IMX_PINCTRL_PIN(MX21_PAD_LD11),
IMX_PINCTRL_PIN(MX21_PAD_LD12),
IMX_PINCTRL_PIN(MX21_PAD_LD13),
IMX_PINCTRL_PIN(MX21_PAD_LD14),
IMX_PINCTRL_PIN(MX21_PAD_LD15),
IMX_PINCTRL_PIN(MX21_PAD_LD16),
IMX_PINCTRL_PIN(MX21_PAD_LD17),
IMX_PINCTRL_PIN(MX21_PAD_REV),
IMX_PINCTRL_PIN(MX21_PAD_CLS),
IMX_PINCTRL_PIN(MX21_PAD_PS),
IMX_PINCTRL_PIN(MX21_PAD_SPL_SPR),
IMX_PINCTRL_PIN(MX21_PAD_HSYNC),
IMX_PINCTRL_PIN(MX21_PAD_VSYNC),
IMX_PINCTRL_PIN(MX21_PAD_CONTRAST),
IMX_PINCTRL_PIN(MX21_PAD_OE_ACD),
IMX_PINCTRL_PIN(MX21_PAD_SD2_D0),
IMX_PINCTRL_PIN(MX21_PAD_SD2_D1),
IMX_PINCTRL_PIN(MX21_PAD_SD2_D2),
IMX_PINCTRL_PIN(MX21_PAD_SD2_D3),
IMX_PINCTRL_PIN(MX21_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX21_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX21_PAD_CSI_D0),
IMX_PINCTRL_PIN(MX21_PAD_CSI_D1),
IMX_PINCTRL_PIN(MX21_PAD_CSI_D2),
IMX_PINCTRL_PIN(MX21_PAD_CSI_D3),
IMX_PINCTRL_PIN(MX21_PAD_CSI_D4),
IMX_PINCTRL_PIN(MX21_PAD_CSI_MCLK),
IMX_PINCTRL_PIN(MX21_PAD_CSI_PIXCLK),
IMX_PINCTRL_PIN(MX21_PAD_CSI_D5),
IMX_PINCTRL_PIN(MX21_PAD_CSI_D6),
IMX_PINCTRL_PIN(MX21_PAD_CSI_D7),
IMX_PINCTRL_PIN(MX21_PAD_CSI_VSYNC),
IMX_PINCTRL_PIN(MX21_PAD_CSI_HSYNC),
IMX_PINCTRL_PIN(MX21_PAD_USB_BYP),
IMX_PINCTRL_PIN(MX21_PAD_USB_PWR),
IMX_PINCTRL_PIN(MX21_PAD_USB_OC),
IMX_PINCTRL_PIN(MX21_PAD_USBH_ON),
IMX_PINCTRL_PIN(MX21_PAD_USBH1_FS),
IMX_PINCTRL_PIN(MX21_PAD_USBH1_OE),
IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDM),
IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDP),
IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDM),
IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDP),
IMX_PINCTRL_PIN(MX21_PAD_USBG_SDA),
IMX_PINCTRL_PIN(MX21_PAD_USBG_SCL),
IMX_PINCTRL_PIN(MX21_PAD_USBG_ON),
IMX_PINCTRL_PIN(MX21_PAD_USBG_FS),
IMX_PINCTRL_PIN(MX21_PAD_USBG_OE),
IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDM),
IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDP),
IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDM),
IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDP),
IMX_PINCTRL_PIN(MX21_PAD_TOUT),
IMX_PINCTRL_PIN(MX21_PAD_TIN),
IMX_PINCTRL_PIN(MX21_PAD_SAP_FS),
IMX_PINCTRL_PIN(MX21_PAD_SAP_RXD),
IMX_PINCTRL_PIN(MX21_PAD_SAP_TXD),
IMX_PINCTRL_PIN(MX21_PAD_SAP_CLK),
IMX_PINCTRL_PIN(MX21_PAD_SSI1_FS),
IMX_PINCTRL_PIN(MX21_PAD_SSI1_RXD),
IMX_PINCTRL_PIN(MX21_PAD_SSI1_TXD),
IMX_PINCTRL_PIN(MX21_PAD_SSI1_CLK),
IMX_PINCTRL_PIN(MX21_PAD_SSI2_FS),
IMX_PINCTRL_PIN(MX21_PAD_SSI2_RXD),
IMX_PINCTRL_PIN(MX21_PAD_SSI2_TXD),
IMX_PINCTRL_PIN(MX21_PAD_SSI2_CLK),
IMX_PINCTRL_PIN(MX21_PAD_SSI3_FS),
IMX_PINCTRL_PIN(MX21_PAD_SSI3_RXD),
IMX_PINCTRL_PIN(MX21_PAD_SSI3_TXD),
IMX_PINCTRL_PIN(MX21_PAD_SSI3_CLK),
IMX_PINCTRL_PIN(MX21_PAD_I2C_DATA),
IMX_PINCTRL_PIN(MX21_PAD_I2C_CLK),
IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS2),
IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS1),
IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS0),
IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SCLK),
IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MISO),
IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MOSI),
IMX_PINCTRL_PIN(MX21_PAD_CSPI1_RDY),
IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS2),
IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS1),
IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS0),
IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SCLK),
IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MISO),
IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MOSI),
IMX_PINCTRL_PIN(MX21_PAD_TEST_WB2),
IMX_PINCTRL_PIN(MX21_PAD_TEST_WB1),
IMX_PINCTRL_PIN(MX21_PAD_TEST_WB0),
IMX_PINCTRL_PIN(MX21_PAD_UART2_CTS),
IMX_PINCTRL_PIN(MX21_PAD_UART2_RTS),
IMX_PINCTRL_PIN(MX21_PAD_PWMO),
IMX_PINCTRL_PIN(MX21_PAD_UART2_TXD),
IMX_PINCTRL_PIN(MX21_PAD_UART2_RXD),
IMX_PINCTRL_PIN(MX21_PAD_UART3_TXD),
IMX_PINCTRL_PIN(MX21_PAD_UART3_RXD),
IMX_PINCTRL_PIN(MX21_PAD_UART3_CTS),
IMX_PINCTRL_PIN(MX21_PAD_UART3_RTS),
IMX_PINCTRL_PIN(MX21_PAD_UART1_TXD),
IMX_PINCTRL_PIN(MX21_PAD_UART1_RXD),
IMX_PINCTRL_PIN(MX21_PAD_UART1_CTS),
IMX_PINCTRL_PIN(MX21_PAD_UART1_RTS),
IMX_PINCTRL_PIN(MX21_PAD_RTCK),
IMX_PINCTRL_PIN(MX21_PAD_RESET_OUT),
IMX_PINCTRL_PIN(MX21_PAD_SD1_D0),
IMX_PINCTRL_PIN(MX21_PAD_SD1_D1),
IMX_PINCTRL_PIN(MX21_PAD_SD1_D2),
IMX_PINCTRL_PIN(MX21_PAD_SD1_D3),
IMX_PINCTRL_PIN(MX21_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX21_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX21_PAD_NFRB),
IMX_PINCTRL_PIN(MX21_PAD_NFCE),
IMX_PINCTRL_PIN(MX21_PAD_NFWP),
IMX_PINCTRL_PIN(MX21_PAD_NFCLE),
IMX_PINCTRL_PIN(MX21_PAD_NFALE),
IMX_PINCTRL_PIN(MX21_PAD_NFRE),
IMX_PINCTRL_PIN(MX21_PAD_NFWE),
IMX_PINCTRL_PIN(MX21_PAD_NFIO0),
IMX_PINCTRL_PIN(MX21_PAD_NFIO1),
IMX_PINCTRL_PIN(MX21_PAD_NFIO2),
IMX_PINCTRL_PIN(MX21_PAD_NFIO3),
IMX_PINCTRL_PIN(MX21_PAD_NFIO4),
IMX_PINCTRL_PIN(MX21_PAD_NFIO5),
IMX_PINCTRL_PIN(MX21_PAD_NFIO6),
IMX_PINCTRL_PIN(MX21_PAD_NFIO7),
IMX_PINCTRL_PIN(MX21_PAD_CLKO),
IMX_PINCTRL_PIN(MX21_PAD_RESERVED),
IMX_PINCTRL_PIN(MX21_PAD_CS4),
IMX_PINCTRL_PIN(MX21_PAD_CS5),
};
static struct imx1_pinctrl_soc_info imx21_pinctrl_info = {
.pins = imx21_pinctrl_pads,
.npins = ARRAY_SIZE(imx21_pinctrl_pads),
};
static int __init imx21_pinctrl_probe(struct platform_device *pdev)
{
return imx1_pinctrl_core_probe(pdev, &imx21_pinctrl_info);
}
static const struct of_device_id imx21_pinctrl_of_match[] = {
{ .compatible = "fsl,imx21-iomuxc", },
{ }
};
MODULE_DEVICE_TABLE(of, imx21_pinctrl_of_match);
static struct platform_driver imx21_pinctrl_driver = {
.driver = {
.name = "imx21-pinctrl",
.owner = THIS_MODULE,
.of_match_table = imx21_pinctrl_of_match,
},
.remove = imx1_pinctrl_core_remove,
};
module_platform_driver_probe(imx21_pinctrl_driver, imx21_pinctrl_probe);
MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
MODULE_DESCRIPTION("Freescale i.MX21 pinctrl driver");
MODULE_LICENSE("GPL");

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drivers/pinctrl/freescale/pinctrl-imx23.c Normal file
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/*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mxs.h"
enum imx23_pin_enum {
GPMI_D00 = PINID(0, 0),
GPMI_D01 = PINID(0, 1),
GPMI_D02 = PINID(0, 2),
GPMI_D03 = PINID(0, 3),
GPMI_D04 = PINID(0, 4),
GPMI_D05 = PINID(0, 5),
GPMI_D06 = PINID(0, 6),
GPMI_D07 = PINID(0, 7),
GPMI_D08 = PINID(0, 8),
GPMI_D09 = PINID(0, 9),
GPMI_D10 = PINID(0, 10),
GPMI_D11 = PINID(0, 11),
GPMI_D12 = PINID(0, 12),
GPMI_D13 = PINID(0, 13),
GPMI_D14 = PINID(0, 14),
GPMI_D15 = PINID(0, 15),
GPMI_CLE = PINID(0, 16),
GPMI_ALE = PINID(0, 17),
GPMI_CE2N = PINID(0, 18),
GPMI_RDY0 = PINID(0, 19),
GPMI_RDY1 = PINID(0, 20),
GPMI_RDY2 = PINID(0, 21),
GPMI_RDY3 = PINID(0, 22),
GPMI_WPN = PINID(0, 23),
GPMI_WRN = PINID(0, 24),
GPMI_RDN = PINID(0, 25),
AUART1_CTS = PINID(0, 26),
AUART1_RTS = PINID(0, 27),
AUART1_RX = PINID(0, 28),
AUART1_TX = PINID(0, 29),
I2C_SCL = PINID(0, 30),
I2C_SDA = PINID(0, 31),
LCD_D00 = PINID(1, 0),
LCD_D01 = PINID(1, 1),
LCD_D02 = PINID(1, 2),
LCD_D03 = PINID(1, 3),
LCD_D04 = PINID(1, 4),
LCD_D05 = PINID(1, 5),
LCD_D06 = PINID(1, 6),
LCD_D07 = PINID(1, 7),
LCD_D08 = PINID(1, 8),
LCD_D09 = PINID(1, 9),
LCD_D10 = PINID(1, 10),
LCD_D11 = PINID(1, 11),
LCD_D12 = PINID(1, 12),
LCD_D13 = PINID(1, 13),
LCD_D14 = PINID(1, 14),
LCD_D15 = PINID(1, 15),
LCD_D16 = PINID(1, 16),
LCD_D17 = PINID(1, 17),
LCD_RESET = PINID(1, 18),
LCD_RS = PINID(1, 19),
LCD_WR = PINID(1, 20),
LCD_CS = PINID(1, 21),
LCD_DOTCK = PINID(1, 22),
LCD_ENABLE = PINID(1, 23),
LCD_HSYNC = PINID(1, 24),
LCD_VSYNC = PINID(1, 25),
PWM0 = PINID(1, 26),
PWM1 = PINID(1, 27),
PWM2 = PINID(1, 28),
PWM3 = PINID(1, 29),
PWM4 = PINID(1, 30),
SSP1_CMD = PINID(2, 0),
SSP1_DETECT = PINID(2, 1),
SSP1_DATA0 = PINID(2, 2),
SSP1_DATA1 = PINID(2, 3),
SSP1_DATA2 = PINID(2, 4),
SSP1_DATA3 = PINID(2, 5),
SSP1_SCK = PINID(2, 6),
ROTARYA = PINID(2, 7),
ROTARYB = PINID(2, 8),
EMI_A00 = PINID(2, 9),
EMI_A01 = PINID(2, 10),
EMI_A02 = PINID(2, 11),
EMI_A03 = PINID(2, 12),
EMI_A04 = PINID(2, 13),
EMI_A05 = PINID(2, 14),
EMI_A06 = PINID(2, 15),
EMI_A07 = PINID(2, 16),
EMI_A08 = PINID(2, 17),
EMI_A09 = PINID(2, 18),
EMI_A10 = PINID(2, 19),
EMI_A11 = PINID(2, 20),
EMI_A12 = PINID(2, 21),
EMI_BA0 = PINID(2, 22),
EMI_BA1 = PINID(2, 23),
EMI_CASN = PINID(2, 24),
EMI_CE0N = PINID(2, 25),
EMI_CE1N = PINID(2, 26),
GPMI_CE1N = PINID(2, 27),
GPMI_CE0N = PINID(2, 28),
EMI_CKE = PINID(2, 29),
EMI_RASN = PINID(2, 30),
EMI_WEN = PINID(2, 31),
EMI_D00 = PINID(3, 0),
EMI_D01 = PINID(3, 1),
EMI_D02 = PINID(3, 2),
EMI_D03 = PINID(3, 3),
EMI_D04 = PINID(3, 4),
EMI_D05 = PINID(3, 5),
EMI_D06 = PINID(3, 6),
EMI_D07 = PINID(3, 7),
EMI_D08 = PINID(3, 8),
EMI_D09 = PINID(3, 9),
EMI_D10 = PINID(3, 10),
EMI_D11 = PINID(3, 11),
EMI_D12 = PINID(3, 12),
EMI_D13 = PINID(3, 13),
EMI_D14 = PINID(3, 14),
EMI_D15 = PINID(3, 15),
EMI_DQM0 = PINID(3, 16),
EMI_DQM1 = PINID(3, 17),
EMI_DQS0 = PINID(3, 18),
EMI_DQS1 = PINID(3, 19),
EMI_CLK = PINID(3, 20),
EMI_CLKN = PINID(3, 21),
};
static const struct pinctrl_pin_desc imx23_pins[] = {
MXS_PINCTRL_PIN(GPMI_D00),
MXS_PINCTRL_PIN(GPMI_D01),
MXS_PINCTRL_PIN(GPMI_D02),
MXS_PINCTRL_PIN(GPMI_D03),
MXS_PINCTRL_PIN(GPMI_D04),
MXS_PINCTRL_PIN(GPMI_D05),
MXS_PINCTRL_PIN(GPMI_D06),
MXS_PINCTRL_PIN(GPMI_D07),
MXS_PINCTRL_PIN(GPMI_D08),
MXS_PINCTRL_PIN(GPMI_D09),
MXS_PINCTRL_PIN(GPMI_D10),
MXS_PINCTRL_PIN(GPMI_D11),
MXS_PINCTRL_PIN(GPMI_D12),
MXS_PINCTRL_PIN(GPMI_D13),
MXS_PINCTRL_PIN(GPMI_D14),
MXS_PINCTRL_PIN(GPMI_D15),
MXS_PINCTRL_PIN(GPMI_CLE),
MXS_PINCTRL_PIN(GPMI_ALE),
MXS_PINCTRL_PIN(GPMI_CE2N),
MXS_PINCTRL_PIN(GPMI_RDY0),
MXS_PINCTRL_PIN(GPMI_RDY1),
MXS_PINCTRL_PIN(GPMI_RDY2),
MXS_PINCTRL_PIN(GPMI_RDY3),
MXS_PINCTRL_PIN(GPMI_WPN),
MXS_PINCTRL_PIN(GPMI_WRN),
MXS_PINCTRL_PIN(GPMI_RDN),
MXS_PINCTRL_PIN(AUART1_CTS),
MXS_PINCTRL_PIN(AUART1_RTS),
MXS_PINCTRL_PIN(AUART1_RX),
MXS_PINCTRL_PIN(AUART1_TX),
MXS_PINCTRL_PIN(I2C_SCL),
MXS_PINCTRL_PIN(I2C_SDA),
MXS_PINCTRL_PIN(LCD_D00),
MXS_PINCTRL_PIN(LCD_D01),
MXS_PINCTRL_PIN(LCD_D02),
MXS_PINCTRL_PIN(LCD_D03),
MXS_PINCTRL_PIN(LCD_D04),
MXS_PINCTRL_PIN(LCD_D05),
MXS_PINCTRL_PIN(LCD_D06),
MXS_PINCTRL_PIN(LCD_D07),
MXS_PINCTRL_PIN(LCD_D08),
MXS_PINCTRL_PIN(LCD_D09),
MXS_PINCTRL_PIN(LCD_D10),
MXS_PINCTRL_PIN(LCD_D11),
MXS_PINCTRL_PIN(LCD_D12),
MXS_PINCTRL_PIN(LCD_D13),
MXS_PINCTRL_PIN(LCD_D14),
MXS_PINCTRL_PIN(LCD_D15),
MXS_PINCTRL_PIN(LCD_D16),
MXS_PINCTRL_PIN(LCD_D17),
MXS_PINCTRL_PIN(LCD_RESET),
MXS_PINCTRL_PIN(LCD_RS),
MXS_PINCTRL_PIN(LCD_WR),
MXS_PINCTRL_PIN(LCD_CS),
MXS_PINCTRL_PIN(LCD_DOTCK),
MXS_PINCTRL_PIN(LCD_ENABLE),
MXS_PINCTRL_PIN(LCD_HSYNC),
MXS_PINCTRL_PIN(LCD_VSYNC),
MXS_PINCTRL_PIN(PWM0),
MXS_PINCTRL_PIN(PWM1),
MXS_PINCTRL_PIN(PWM2),
MXS_PINCTRL_PIN(PWM3),
MXS_PINCTRL_PIN(PWM4),
MXS_PINCTRL_PIN(SSP1_CMD),
MXS_PINCTRL_PIN(SSP1_DETECT),
MXS_PINCTRL_PIN(SSP1_DATA0),
MXS_PINCTRL_PIN(SSP1_DATA1),
MXS_PINCTRL_PIN(SSP1_DATA2),
MXS_PINCTRL_PIN(SSP1_DATA3),
MXS_PINCTRL_PIN(SSP1_SCK),
MXS_PINCTRL_PIN(ROTARYA),
MXS_PINCTRL_PIN(ROTARYB),
MXS_PINCTRL_PIN(EMI_A00),
MXS_PINCTRL_PIN(EMI_A01),
MXS_PINCTRL_PIN(EMI_A02),
MXS_PINCTRL_PIN(EMI_A03),
MXS_PINCTRL_PIN(EMI_A04),
MXS_PINCTRL_PIN(EMI_A05),
MXS_PINCTRL_PIN(EMI_A06),
MXS_PINCTRL_PIN(EMI_A07),
MXS_PINCTRL_PIN(EMI_A08),
MXS_PINCTRL_PIN(EMI_A09),
MXS_PINCTRL_PIN(EMI_A10),
MXS_PINCTRL_PIN(EMI_A11),
MXS_PINCTRL_PIN(EMI_A12),
MXS_PINCTRL_PIN(EMI_BA0),
MXS_PINCTRL_PIN(EMI_BA1),
MXS_PINCTRL_PIN(EMI_CASN),
MXS_PINCTRL_PIN(EMI_CE0N),
MXS_PINCTRL_PIN(EMI_CE1N),
MXS_PINCTRL_PIN(GPMI_CE1N),
MXS_PINCTRL_PIN(GPMI_CE0N),
MXS_PINCTRL_PIN(EMI_CKE),
MXS_PINCTRL_PIN(EMI_RASN),
MXS_PINCTRL_PIN(EMI_WEN),
MXS_PINCTRL_PIN(EMI_D00),
MXS_PINCTRL_PIN(EMI_D01),
MXS_PINCTRL_PIN(EMI_D02),
MXS_PINCTRL_PIN(EMI_D03),
MXS_PINCTRL_PIN(EMI_D04),
MXS_PINCTRL_PIN(EMI_D05),
MXS_PINCTRL_PIN(EMI_D06),
MXS_PINCTRL_PIN(EMI_D07),
MXS_PINCTRL_PIN(EMI_D08),
MXS_PINCTRL_PIN(EMI_D09),
MXS_PINCTRL_PIN(EMI_D10),
MXS_PINCTRL_PIN(EMI_D11),
MXS_PINCTRL_PIN(EMI_D12),
MXS_PINCTRL_PIN(EMI_D13),
MXS_PINCTRL_PIN(EMI_D14),
MXS_PINCTRL_PIN(EMI_D15),
MXS_PINCTRL_PIN(EMI_DQM0),
MXS_PINCTRL_PIN(EMI_DQM1),
MXS_PINCTRL_PIN(EMI_DQS0),
MXS_PINCTRL_PIN(EMI_DQS1),
MXS_PINCTRL_PIN(EMI_CLK),
MXS_PINCTRL_PIN(EMI_CLKN),
};
static struct mxs_regs imx23_regs = {
.muxsel = 0x100,
.drive = 0x200,
.pull = 0x400,
};
static struct mxs_pinctrl_soc_data imx23_pinctrl_data = {
.regs = &imx23_regs,
.pins = imx23_pins,
.npins = ARRAY_SIZE(imx23_pins),
};
static int imx23_pinctrl_probe(struct platform_device *pdev)
{
return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data);
}
static const struct of_device_id imx23_pinctrl_of_match[] = {
{ .compatible = "fsl,imx23-pinctrl", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match);
static struct platform_driver imx23_pinctrl_driver = {
.driver = {
.name = "imx23-pinctrl",
.owner = THIS_MODULE,
.of_match_table = imx23_pinctrl_of_match,
},
.probe = imx23_pinctrl_probe,
.remove = mxs_pinctrl_remove,
};
static int __init imx23_pinctrl_init(void)
{
return platform_driver_register(&imx23_pinctrl_driver);
}
postcore_initcall(imx23_pinctrl_init);
static void __exit imx23_pinctrl_exit(void)
{
platform_driver_unregister(&imx23_pinctrl_driver);
}
module_exit(imx23_pinctrl_exit);
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver");
MODULE_LICENSE("GPL v2");

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/*
* imx25 pinctrl driver.
*
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
*
* This driver was mostly copied from the imx51 pinctrl driver which has:
*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro, Inc.
*
* Author: Denis Carikli <denis@eukrea.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx25_pads {
MX25_PAD_RESERVE0 = 1,
MX25_PAD_A10 = 2,
MX25_PAD_A13 = 3,
MX25_PAD_A14 = 4,
MX25_PAD_A15 = 5,
MX25_PAD_A16 = 6,
MX25_PAD_A17 = 7,
MX25_PAD_A18 = 8,
MX25_PAD_A19 = 9,
MX25_PAD_A20 = 10,
MX25_PAD_A21 = 11,
MX25_PAD_A22 = 12,
MX25_PAD_A23 = 13,
MX25_PAD_A24 = 14,
MX25_PAD_A25 = 15,
MX25_PAD_EB0 = 16,
MX25_PAD_EB1 = 17,
MX25_PAD_OE = 18,
MX25_PAD_CS0 = 19,
MX25_PAD_CS1 = 20,
MX25_PAD_CS4 = 21,
MX25_PAD_CS5 = 22,
MX25_PAD_NF_CE0 = 23,
MX25_PAD_ECB = 24,
MX25_PAD_LBA = 25,
MX25_PAD_BCLK = 26,
MX25_PAD_RW = 27,
MX25_PAD_NFWE_B = 28,
MX25_PAD_NFRE_B = 29,
MX25_PAD_NFALE = 30,
MX25_PAD_NFCLE = 31,
MX25_PAD_NFWP_B = 32,
MX25_PAD_NFRB = 33,
MX25_PAD_D15 = 34,
MX25_PAD_D14 = 35,
MX25_PAD_D13 = 36,
MX25_PAD_D12 = 37,
MX25_PAD_D11 = 38,
MX25_PAD_D10 = 39,
MX25_PAD_D9 = 40,
MX25_PAD_D8 = 41,
MX25_PAD_D7 = 42,
MX25_PAD_D6 = 43,
MX25_PAD_D5 = 44,
MX25_PAD_D4 = 45,
MX25_PAD_D3 = 46,
MX25_PAD_D2 = 47,
MX25_PAD_D1 = 48,
MX25_PAD_D0 = 49,
MX25_PAD_LD0 = 50,
MX25_PAD_LD1 = 51,
MX25_PAD_LD2 = 52,
MX25_PAD_LD3 = 53,
MX25_PAD_LD4 = 54,
MX25_PAD_LD5 = 55,
MX25_PAD_LD6 = 56,
MX25_PAD_LD7 = 57,
MX25_PAD_LD8 = 58,
MX25_PAD_LD9 = 59,
MX25_PAD_LD10 = 60,
MX25_PAD_LD11 = 61,
MX25_PAD_LD12 = 62,
MX25_PAD_LD13 = 63,
MX25_PAD_LD14 = 64,
MX25_PAD_LD15 = 65,
MX25_PAD_HSYNC = 66,
MX25_PAD_VSYNC = 67,
MX25_PAD_LSCLK = 68,
MX25_PAD_OE_ACD = 69,
MX25_PAD_CONTRAST = 70,
MX25_PAD_PWM = 71,
MX25_PAD_CSI_D2 = 72,
MX25_PAD_CSI_D3 = 73,
MX25_PAD_CSI_D4 = 74,
MX25_PAD_CSI_D5 = 75,
MX25_PAD_CSI_D6 = 76,
MX25_PAD_CSI_D7 = 77,
MX25_PAD_CSI_D8 = 78,
MX25_PAD_CSI_D9 = 79,
MX25_PAD_CSI_MCLK = 80,
MX25_PAD_CSI_VSYNC = 81,
MX25_PAD_CSI_HSYNC = 82,
MX25_PAD_CSI_PIXCLK = 83,
MX25_PAD_I2C1_CLK = 84,
MX25_PAD_I2C1_DAT = 85,
MX25_PAD_CSPI1_MOSI = 86,
MX25_PAD_CSPI1_MISO = 87,
MX25_PAD_CSPI1_SS0 = 88,
MX25_PAD_CSPI1_SS1 = 89,
MX25_PAD_CSPI1_SCLK = 90,
MX25_PAD_CSPI1_RDY = 91,
MX25_PAD_UART1_RXD = 92,
MX25_PAD_UART1_TXD = 93,
MX25_PAD_UART1_RTS = 94,
MX25_PAD_UART1_CTS = 95,
MX25_PAD_UART2_RXD = 96,
MX25_PAD_UART2_TXD = 97,
MX25_PAD_UART2_RTS = 98,
MX25_PAD_UART2_CTS = 99,
MX25_PAD_SD1_CMD = 100,
MX25_PAD_SD1_CLK = 101,
MX25_PAD_SD1_DATA0 = 102,
MX25_PAD_SD1_DATA1 = 103,
MX25_PAD_SD1_DATA2 = 104,
MX25_PAD_SD1_DATA3 = 105,
MX25_PAD_KPP_ROW0 = 106,
MX25_PAD_KPP_ROW1 = 107,
MX25_PAD_KPP_ROW2 = 108,
MX25_PAD_KPP_ROW3 = 109,
MX25_PAD_KPP_COL0 = 110,
MX25_PAD_KPP_COL1 = 111,
MX25_PAD_KPP_COL2 = 112,
MX25_PAD_KPP_COL3 = 113,
MX25_PAD_FEC_MDC = 114,
MX25_PAD_FEC_MDIO = 115,
MX25_PAD_FEC_TDATA0 = 116,
MX25_PAD_FEC_TDATA1 = 117,
MX25_PAD_FEC_TX_EN = 118,
MX25_PAD_FEC_RDATA0 = 119,
MX25_PAD_FEC_RDATA1 = 120,
MX25_PAD_FEC_RX_DV = 121,
MX25_PAD_FEC_TX_CLK = 122,
MX25_PAD_RTCK = 123,
MX25_PAD_DE_B = 124,
MX25_PAD_GPIO_A = 125,
MX25_PAD_GPIO_B = 126,
MX25_PAD_GPIO_C = 127,
MX25_PAD_GPIO_D = 128,
MX25_PAD_GPIO_E = 129,
MX25_PAD_GPIO_F = 130,
MX25_PAD_EXT_ARMCLK = 131,
MX25_PAD_UPLL_BYPCLK = 132,
MX25_PAD_VSTBY_REQ = 133,
MX25_PAD_VSTBY_ACK = 134,
MX25_PAD_POWER_FAIL = 135,
MX25_PAD_CLKO = 136,
MX25_PAD_BOOT_MODE0 = 137,
MX25_PAD_BOOT_MODE1 = 138,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX25_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX25_PAD_A10),
IMX_PINCTRL_PIN(MX25_PAD_A13),
IMX_PINCTRL_PIN(MX25_PAD_A14),
IMX_PINCTRL_PIN(MX25_PAD_A15),
IMX_PINCTRL_PIN(MX25_PAD_A16),
IMX_PINCTRL_PIN(MX25_PAD_A17),
IMX_PINCTRL_PIN(MX25_PAD_A18),
IMX_PINCTRL_PIN(MX25_PAD_A19),
IMX_PINCTRL_PIN(MX25_PAD_A20),
IMX_PINCTRL_PIN(MX25_PAD_A21),
IMX_PINCTRL_PIN(MX25_PAD_A22),
IMX_PINCTRL_PIN(MX25_PAD_A23),
IMX_PINCTRL_PIN(MX25_PAD_A24),
IMX_PINCTRL_PIN(MX25_PAD_A25),
IMX_PINCTRL_PIN(MX25_PAD_EB0),
IMX_PINCTRL_PIN(MX25_PAD_EB1),
IMX_PINCTRL_PIN(MX25_PAD_OE),
IMX_PINCTRL_PIN(MX25_PAD_CS0),
IMX_PINCTRL_PIN(MX25_PAD_CS1),
IMX_PINCTRL_PIN(MX25_PAD_CS4),
IMX_PINCTRL_PIN(MX25_PAD_CS5),
IMX_PINCTRL_PIN(MX25_PAD_NF_CE0),
IMX_PINCTRL_PIN(MX25_PAD_ECB),
IMX_PINCTRL_PIN(MX25_PAD_LBA),
IMX_PINCTRL_PIN(MX25_PAD_BCLK),
IMX_PINCTRL_PIN(MX25_PAD_RW),
IMX_PINCTRL_PIN(MX25_PAD_NFWE_B),
IMX_PINCTRL_PIN(MX25_PAD_NFRE_B),
IMX_PINCTRL_PIN(MX25_PAD_NFALE),
IMX_PINCTRL_PIN(MX25_PAD_NFCLE),
IMX_PINCTRL_PIN(MX25_PAD_NFWP_B),
IMX_PINCTRL_PIN(MX25_PAD_NFRB),
IMX_PINCTRL_PIN(MX25_PAD_D15),
IMX_PINCTRL_PIN(MX25_PAD_D14),
IMX_PINCTRL_PIN(MX25_PAD_D13),
IMX_PINCTRL_PIN(MX25_PAD_D12),
IMX_PINCTRL_PIN(MX25_PAD_D11),
IMX_PINCTRL_PIN(MX25_PAD_D10),
IMX_PINCTRL_PIN(MX25_PAD_D9),
IMX_PINCTRL_PIN(MX25_PAD_D8),
IMX_PINCTRL_PIN(MX25_PAD_D7),
IMX_PINCTRL_PIN(MX25_PAD_D6),
IMX_PINCTRL_PIN(MX25_PAD_D5),
IMX_PINCTRL_PIN(MX25_PAD_D4),
IMX_PINCTRL_PIN(MX25_PAD_D3),
IMX_PINCTRL_PIN(MX25_PAD_D2),
IMX_PINCTRL_PIN(MX25_PAD_D1),
IMX_PINCTRL_PIN(MX25_PAD_D0),
IMX_PINCTRL_PIN(MX25_PAD_LD0),
IMX_PINCTRL_PIN(MX25_PAD_LD1),
IMX_PINCTRL_PIN(MX25_PAD_LD2),
IMX_PINCTRL_PIN(MX25_PAD_LD3),
IMX_PINCTRL_PIN(MX25_PAD_LD4),
IMX_PINCTRL_PIN(MX25_PAD_LD5),
IMX_PINCTRL_PIN(MX25_PAD_LD6),
IMX_PINCTRL_PIN(MX25_PAD_LD7),
IMX_PINCTRL_PIN(MX25_PAD_LD8),
IMX_PINCTRL_PIN(MX25_PAD_LD9),
IMX_PINCTRL_PIN(MX25_PAD_LD10),
IMX_PINCTRL_PIN(MX25_PAD_LD11),
IMX_PINCTRL_PIN(MX25_PAD_LD12),
IMX_PINCTRL_PIN(MX25_PAD_LD13),
IMX_PINCTRL_PIN(MX25_PAD_LD14),
IMX_PINCTRL_PIN(MX25_PAD_LD15),
IMX_PINCTRL_PIN(MX25_PAD_HSYNC),
IMX_PINCTRL_PIN(MX25_PAD_VSYNC),
IMX_PINCTRL_PIN(MX25_PAD_LSCLK),
IMX_PINCTRL_PIN(MX25_PAD_OE_ACD),
IMX_PINCTRL_PIN(MX25_PAD_CONTRAST),
IMX_PINCTRL_PIN(MX25_PAD_PWM),
IMX_PINCTRL_PIN(MX25_PAD_CSI_D2),
IMX_PINCTRL_PIN(MX25_PAD_CSI_D3),
IMX_PINCTRL_PIN(MX25_PAD_CSI_D4),
IMX_PINCTRL_PIN(MX25_PAD_CSI_D5),
IMX_PINCTRL_PIN(MX25_PAD_CSI_D6),
IMX_PINCTRL_PIN(MX25_PAD_CSI_D7),
IMX_PINCTRL_PIN(MX25_PAD_CSI_D8),
IMX_PINCTRL_PIN(MX25_PAD_CSI_D9),
IMX_PINCTRL_PIN(MX25_PAD_CSI_MCLK),
IMX_PINCTRL_PIN(MX25_PAD_CSI_VSYNC),
IMX_PINCTRL_PIN(MX25_PAD_CSI_HSYNC),
IMX_PINCTRL_PIN(MX25_PAD_CSI_PIXCLK),
IMX_PINCTRL_PIN(MX25_PAD_I2C1_CLK),
IMX_PINCTRL_PIN(MX25_PAD_I2C1_DAT),
IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MOSI),
IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MISO),
IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS0),
IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS1),
IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SCLK),
IMX_PINCTRL_PIN(MX25_PAD_CSPI1_RDY),
IMX_PINCTRL_PIN(MX25_PAD_UART1_RXD),
IMX_PINCTRL_PIN(MX25_PAD_UART1_TXD),
IMX_PINCTRL_PIN(MX25_PAD_UART1_RTS),
IMX_PINCTRL_PIN(MX25_PAD_UART1_CTS),
IMX_PINCTRL_PIN(MX25_PAD_UART2_RXD),
IMX_PINCTRL_PIN(MX25_PAD_UART2_TXD),
IMX_PINCTRL_PIN(MX25_PAD_UART2_RTS),
IMX_PINCTRL_PIN(MX25_PAD_UART2_CTS),
IMX_PINCTRL_PIN(MX25_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX25_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA0),
IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA1),
IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA2),
IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA3),
IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW0),
IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW1),
IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW2),
IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW3),
IMX_PINCTRL_PIN(MX25_PAD_KPP_COL0),
IMX_PINCTRL_PIN(MX25_PAD_KPP_COL1),
IMX_PINCTRL_PIN(MX25_PAD_KPP_COL2),
IMX_PINCTRL_PIN(MX25_PAD_KPP_COL3),
IMX_PINCTRL_PIN(MX25_PAD_FEC_MDC),
IMX_PINCTRL_PIN(MX25_PAD_FEC_MDIO),
IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA0),
IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA1),
IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_EN),
IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA0),
IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA1),
IMX_PINCTRL_PIN(MX25_PAD_FEC_RX_DV),
IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_CLK),
IMX_PINCTRL_PIN(MX25_PAD_RTCK),
IMX_PINCTRL_PIN(MX25_PAD_DE_B),
IMX_PINCTRL_PIN(MX25_PAD_GPIO_A),
IMX_PINCTRL_PIN(MX25_PAD_GPIO_B),
IMX_PINCTRL_PIN(MX25_PAD_GPIO_C),
IMX_PINCTRL_PIN(MX25_PAD_GPIO_D),
IMX_PINCTRL_PIN(MX25_PAD_GPIO_E),
IMX_PINCTRL_PIN(MX25_PAD_GPIO_F),
IMX_PINCTRL_PIN(MX25_PAD_EXT_ARMCLK),
IMX_PINCTRL_PIN(MX25_PAD_UPLL_BYPCLK),
IMX_PINCTRL_PIN(MX25_PAD_VSTBY_REQ),
IMX_PINCTRL_PIN(MX25_PAD_VSTBY_ACK),
IMX_PINCTRL_PIN(MX25_PAD_POWER_FAIL),
IMX_PINCTRL_PIN(MX25_PAD_CLKO),
IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE0),
IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE1),
};
static struct imx_pinctrl_soc_info imx25_pinctrl_info = {
.pins = imx25_pinctrl_pads,
.npins = ARRAY_SIZE(imx25_pinctrl_pads),
};
static const struct of_device_id imx25_pinctrl_of_match[] = {
{ .compatible = "fsl,imx25-iomuxc", },
{ /* sentinel */ }
};
static int imx25_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx25_pinctrl_info);
}
static struct platform_driver imx25_pinctrl_driver = {
.driver = {
.name = "imx25-pinctrl",
.owner = THIS_MODULE,
.of_match_table = of_match_ptr(imx25_pinctrl_of_match),
},
.probe = imx25_pinctrl_probe,
.remove = imx_pinctrl_remove,
};
static int __init imx25_pinctrl_init(void)
{
return platform_driver_register(&imx25_pinctrl_driver);
}
arch_initcall(imx25_pinctrl_init);
static void __exit imx25_pinctrl_exit(void)
{
platform_driver_unregister(&imx25_pinctrl_driver);
}
module_exit(imx25_pinctrl_exit);
MODULE_AUTHOR("Denis Carikli <denis@eukrea.com>");
MODULE_DESCRIPTION("Freescale IMX25 pinctrl driver");
MODULE_LICENSE("GPL v2");

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/*
* imx27 pinctrl driver based on imx pinmux core
*
* Copyright (C) 2013 Pengutronix
*
* Author: Markus Pargmann <mpa@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx1.h"
#define PAD_ID(port, pin) (port*32 + pin)
#define PA 0
#define PB 1
#define PC 2
#define PD 3
#define PE 4
#define PF 5
enum imx27_pads {
MX27_PAD_USBH2_CLK = PAD_ID(PA, 0),
MX27_PAD_USBH2_DIR = PAD_ID(PA, 1),
MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2),
MX27_PAD_USBH2_NXT = PAD_ID(PA, 3),
MX27_PAD_USBH2_STP = PAD_ID(PA, 4),
MX27_PAD_LSCLK = PAD_ID(PA, 5),
MX27_PAD_LD0 = PAD_ID(PA, 6),
MX27_PAD_LD1 = PAD_ID(PA, 7),
MX27_PAD_LD2 = PAD_ID(PA, 8),
MX27_PAD_LD3 = PAD_ID(PA, 9),
MX27_PAD_LD4 = PAD_ID(PA, 10),
MX27_PAD_LD5 = PAD_ID(PA, 11),
MX27_PAD_LD6 = PAD_ID(PA, 12),
MX27_PAD_LD7 = PAD_ID(PA, 13),
MX27_PAD_LD8 = PAD_ID(PA, 14),
MX27_PAD_LD9 = PAD_ID(PA, 15),
MX27_PAD_LD10 = PAD_ID(PA, 16),
MX27_PAD_LD11 = PAD_ID(PA, 17),
MX27_PAD_LD12 = PAD_ID(PA, 18),
MX27_PAD_LD13 = PAD_ID(PA, 19),
MX27_PAD_LD14 = PAD_ID(PA, 20),
MX27_PAD_LD15 = PAD_ID(PA, 21),
MX27_PAD_LD16 = PAD_ID(PA, 22),
MX27_PAD_LD17 = PAD_ID(PA, 23),
MX27_PAD_REV = PAD_ID(PA, 24),
MX27_PAD_CLS = PAD_ID(PA, 25),
MX27_PAD_PS = PAD_ID(PA, 26),
MX27_PAD_SPL_SPR = PAD_ID(PA, 27),
MX27_PAD_HSYNC = PAD_ID(PA, 28),
MX27_PAD_VSYNC = PAD_ID(PA, 29),
MX27_PAD_CONTRAST = PAD_ID(PA, 30),
MX27_PAD_OE_ACD = PAD_ID(PA, 31),
MX27_PAD_SD2_D0 = PAD_ID(PB, 4),
MX27_PAD_SD2_D1 = PAD_ID(PB, 5),
MX27_PAD_SD2_D2 = PAD_ID(PB, 6),
MX27_PAD_SD2_D3 = PAD_ID(PB, 7),
MX27_PAD_SD2_CMD = PAD_ID(PB, 8),
MX27_PAD_SD2_CLK = PAD_ID(PB, 9),
MX27_PAD_CSI_D0 = PAD_ID(PB, 10),
MX27_PAD_CSI_D1 = PAD_ID(PB, 11),
MX27_PAD_CSI_D2 = PAD_ID(PB, 12),
MX27_PAD_CSI_D3 = PAD_ID(PB, 13),
MX27_PAD_CSI_D4 = PAD_ID(PB, 14),
MX27_PAD_CSI_MCLK = PAD_ID(PB, 15),
MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
MX27_PAD_CSI_D5 = PAD_ID(PB, 17),
MX27_PAD_CSI_D6 = PAD_ID(PB, 18),
MX27_PAD_CSI_D7 = PAD_ID(PB, 19),
MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20),
MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21),
MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22),
MX27_PAD_USB_PWR = PAD_ID(PB, 23),
MX27_PAD_USB_OC_B = PAD_ID(PB, 24),
MX27_PAD_USBH1_RCV = PAD_ID(PB, 25),
MX27_PAD_USBH1_FS = PAD_ID(PB, 26),
MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27),
MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28),
MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29),
MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30),
MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31),
MX27_PAD_I2C2_SDA = PAD_ID(PC, 5),
MX27_PAD_I2C2_SCL = PAD_ID(PC, 6),
MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7),
MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8),
MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9),
MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10),
MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11),
MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12),
MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13),
MX27_PAD_TOUT = PAD_ID(PC, 14),
MX27_PAD_TIN = PAD_ID(PC, 15),
MX27_PAD_SSI4_FS = PAD_ID(PC, 16),
MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17),
MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18),
MX27_PAD_SSI4_CLK = PAD_ID(PC, 19),
MX27_PAD_SSI1_FS = PAD_ID(PC, 20),
MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21),
MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22),
MX27_PAD_SSI1_CLK = PAD_ID(PC, 23),
MX27_PAD_SSI2_FS = PAD_ID(PC, 24),
MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25),
MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26),
MX27_PAD_SSI2_CLK = PAD_ID(PC, 27),
MX27_PAD_SSI3_FS = PAD_ID(PC, 28),
MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29),
MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30),
MX27_PAD_SSI3_CLK = PAD_ID(PC, 31),
MX27_PAD_SD3_CMD = PAD_ID(PD, 0),
MX27_PAD_SD3_CLK = PAD_ID(PD, 1),
MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2),
MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3),
MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4),
MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5),
MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6),
MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7),
MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8),
MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9),
MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10),
MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11),
MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12),
MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13),
MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14),
MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15),
MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16),
MX27_PAD_I2C_DATA = PAD_ID(PD, 17),
MX27_PAD_I2C_CLK = PAD_ID(PD, 18),
MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23),
MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25),
MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30),
MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0),
MX27_PAD_USBOTG_STP = PAD_ID(PE, 1),
MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2),
MX27_PAD_UART2_CTS = PAD_ID(PE, 3),
MX27_PAD_UART2_RTS = PAD_ID(PE, 4),
MX27_PAD_PWMO = PAD_ID(PE, 5),
MX27_PAD_UART2_TXD = PAD_ID(PE, 6),
MX27_PAD_UART2_RXD = PAD_ID(PE, 7),
MX27_PAD_UART3_TXD = PAD_ID(PE, 8),
MX27_PAD_UART3_RXD = PAD_ID(PE, 9),
MX27_PAD_UART3_CTS = PAD_ID(PE, 10),
MX27_PAD_UART3_RTS = PAD_ID(PE, 11),
MX27_PAD_UART1_TXD = PAD_ID(PE, 12),
MX27_PAD_UART1_RXD = PAD_ID(PE, 13),
MX27_PAD_UART1_CTS = PAD_ID(PE, 14),
MX27_PAD_UART1_RTS = PAD_ID(PE, 15),
MX27_PAD_RTCK = PAD_ID(PE, 16),
MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17),
MX27_PAD_SD1_D0 = PAD_ID(PE, 18),
MX27_PAD_SD1_D1 = PAD_ID(PE, 19),
MX27_PAD_SD1_D2 = PAD_ID(PE, 20),
MX27_PAD_SD1_D3 = PAD_ID(PE, 21),
MX27_PAD_SD1_CMD = PAD_ID(PE, 22),
MX27_PAD_SD1_CLK = PAD_ID(PE, 23),
MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24),
MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25),
MX27_PAD_NFRB = PAD_ID(PF, 0),
MX27_PAD_NFCLE = PAD_ID(PF, 1),
MX27_PAD_NFWP_B = PAD_ID(PF, 2),
MX27_PAD_NFCE_B = PAD_ID(PF, 3),
MX27_PAD_NFALE = PAD_ID(PF, 4),
MX27_PAD_NFRE_B = PAD_ID(PF, 5),
MX27_PAD_NFWE_B = PAD_ID(PF, 6),
MX27_PAD_PC_POE = PAD_ID(PF, 7),
MX27_PAD_PC_RW_B = PAD_ID(PF, 8),
MX27_PAD_IOIS16 = PAD_ID(PF, 9),
MX27_PAD_PC_RST = PAD_ID(PF, 10),
MX27_PAD_PC_BVD2 = PAD_ID(PF, 11),
MX27_PAD_PC_BVD1 = PAD_ID(PF, 12),
MX27_PAD_PC_VS2 = PAD_ID(PF, 13),
MX27_PAD_PC_VS1 = PAD_ID(PF, 14),
MX27_PAD_CLKO = PAD_ID(PF, 15),
MX27_PAD_PC_PWRON = PAD_ID(PF, 16),
MX27_PAD_PC_READY = PAD_ID(PF, 17),
MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18),
MX27_PAD_PC_CD2_B = PAD_ID(PF, 19),
MX27_PAD_PC_CD1_B = PAD_ID(PF, 20),
MX27_PAD_CS4_B = PAD_ID(PF, 21),
MX27_PAD_CS5_B = PAD_ID(PF, 22),
MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23),
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX27_PAD_USBH2_CLK),
IMX_PINCTRL_PIN(MX27_PAD_USBH2_DIR),
IMX_PINCTRL_PIN(MX27_PAD_USBH2_DATA7),
IMX_PINCTRL_PIN(MX27_PAD_USBH2_NXT),
IMX_PINCTRL_PIN(MX27_PAD_USBH2_STP),
IMX_PINCTRL_PIN(MX27_PAD_LSCLK),
IMX_PINCTRL_PIN(MX27_PAD_LD0),
IMX_PINCTRL_PIN(MX27_PAD_LD1),
IMX_PINCTRL_PIN(MX27_PAD_LD2),
IMX_PINCTRL_PIN(MX27_PAD_LD3),
IMX_PINCTRL_PIN(MX27_PAD_LD4),
IMX_PINCTRL_PIN(MX27_PAD_LD5),
IMX_PINCTRL_PIN(MX27_PAD_LD6),
IMX_PINCTRL_PIN(MX27_PAD_LD7),
IMX_PINCTRL_PIN(MX27_PAD_LD8),
IMX_PINCTRL_PIN(MX27_PAD_LD9),
IMX_PINCTRL_PIN(MX27_PAD_LD10),
IMX_PINCTRL_PIN(MX27_PAD_LD11),
IMX_PINCTRL_PIN(MX27_PAD_LD12),
IMX_PINCTRL_PIN(MX27_PAD_LD13),
IMX_PINCTRL_PIN(MX27_PAD_LD14),
IMX_PINCTRL_PIN(MX27_PAD_LD15),
IMX_PINCTRL_PIN(MX27_PAD_LD16),
IMX_PINCTRL_PIN(MX27_PAD_LD17),
IMX_PINCTRL_PIN(MX27_PAD_REV),
IMX_PINCTRL_PIN(MX27_PAD_CLS),
IMX_PINCTRL_PIN(MX27_PAD_PS),
IMX_PINCTRL_PIN(MX27_PAD_SPL_SPR),
IMX_PINCTRL_PIN(MX27_PAD_HSYNC),
IMX_PINCTRL_PIN(MX27_PAD_VSYNC),
IMX_PINCTRL_PIN(MX27_PAD_CONTRAST),
IMX_PINCTRL_PIN(MX27_PAD_OE_ACD),
IMX_PINCTRL_PIN(MX27_PAD_SD2_D0),
IMX_PINCTRL_PIN(MX27_PAD_SD2_D1),
IMX_PINCTRL_PIN(MX27_PAD_SD2_D2),
IMX_PINCTRL_PIN(MX27_PAD_SD2_D3),
IMX_PINCTRL_PIN(MX27_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX27_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX27_PAD_CSI_D0),
IMX_PINCTRL_PIN(MX27_PAD_CSI_D1),
IMX_PINCTRL_PIN(MX27_PAD_CSI_D2),
IMX_PINCTRL_PIN(MX27_PAD_CSI_D3),
IMX_PINCTRL_PIN(MX27_PAD_CSI_D4),
IMX_PINCTRL_PIN(MX27_PAD_CSI_MCLK),
IMX_PINCTRL_PIN(MX27_PAD_CSI_PIXCLK),
IMX_PINCTRL_PIN(MX27_PAD_CSI_D5),
IMX_PINCTRL_PIN(MX27_PAD_CSI_D6),
IMX_PINCTRL_PIN(MX27_PAD_CSI_D7),
IMX_PINCTRL_PIN(MX27_PAD_CSI_VSYNC),
IMX_PINCTRL_PIN(MX27_PAD_CSI_HSYNC),
IMX_PINCTRL_PIN(MX27_PAD_USBH1_SUSP),
IMX_PINCTRL_PIN(MX27_PAD_USB_PWR),
IMX_PINCTRL_PIN(MX27_PAD_USB_OC_B),
IMX_PINCTRL_PIN(MX27_PAD_USBH1_RCV),
IMX_PINCTRL_PIN(MX27_PAD_USBH1_FS),
IMX_PINCTRL_PIN(MX27_PAD_USBH1_OE_B),
IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDM),
IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDP),
IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM),
IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP),
IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA),
IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA6),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA0),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA2),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA1),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA4),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA3),
IMX_PINCTRL_PIN(MX27_PAD_TOUT),
IMX_PINCTRL_PIN(MX27_PAD_TIN),
IMX_PINCTRL_PIN(MX27_PAD_SSI4_FS),
IMX_PINCTRL_PIN(MX27_PAD_SSI4_RXDAT),
IMX_PINCTRL_PIN(MX27_PAD_SSI4_TXDAT),
IMX_PINCTRL_PIN(MX27_PAD_SSI4_CLK),
IMX_PINCTRL_PIN(MX27_PAD_SSI1_FS),
IMX_PINCTRL_PIN(MX27_PAD_SSI1_RXDAT),
IMX_PINCTRL_PIN(MX27_PAD_SSI1_TXDAT),
IMX_PINCTRL_PIN(MX27_PAD_SSI1_CLK),
IMX_PINCTRL_PIN(MX27_PAD_SSI2_FS),
IMX_PINCTRL_PIN(MX27_PAD_SSI2_RXDAT),
IMX_PINCTRL_PIN(MX27_PAD_SSI2_TXDAT),
IMX_PINCTRL_PIN(MX27_PAD_SSI2_CLK),
IMX_PINCTRL_PIN(MX27_PAD_SSI3_FS),
IMX_PINCTRL_PIN(MX27_PAD_SSI3_RXDAT),
IMX_PINCTRL_PIN(MX27_PAD_SSI3_TXDAT),
IMX_PINCTRL_PIN(MX27_PAD_SSI3_CLK),
IMX_PINCTRL_PIN(MX27_PAD_SD3_CMD),
IMX_PINCTRL_PIN(MX27_PAD_SD3_CLK),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA0),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA1),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA2),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA3),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA4),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA5),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA6),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA7),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA8),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA9),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA10),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA11),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA12),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA13),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA14),
IMX_PINCTRL_PIN(MX27_PAD_I2C_DATA),
IMX_PINCTRL_PIN(MX27_PAD_I2C_CLK),
IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS2),
IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS1),
IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS0),
IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SCLK),
IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MISO),
IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MOSI),
IMX_PINCTRL_PIN(MX27_PAD_CSPI1_RDY),
IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS2),
IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS1),
IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS0),
IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SCLK),
IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MISO),
IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MOSI),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_NXT),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_STP),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DIR),
IMX_PINCTRL_PIN(MX27_PAD_UART2_CTS),
IMX_PINCTRL_PIN(MX27_PAD_UART2_RTS),
IMX_PINCTRL_PIN(MX27_PAD_PWMO),
IMX_PINCTRL_PIN(MX27_PAD_UART2_TXD),
IMX_PINCTRL_PIN(MX27_PAD_UART2_RXD),
IMX_PINCTRL_PIN(MX27_PAD_UART3_TXD),
IMX_PINCTRL_PIN(MX27_PAD_UART3_RXD),
IMX_PINCTRL_PIN(MX27_PAD_UART3_CTS),
IMX_PINCTRL_PIN(MX27_PAD_UART3_RTS),
IMX_PINCTRL_PIN(MX27_PAD_UART1_TXD),
IMX_PINCTRL_PIN(MX27_PAD_UART1_RXD),
IMX_PINCTRL_PIN(MX27_PAD_UART1_CTS),
IMX_PINCTRL_PIN(MX27_PAD_UART1_RTS),
IMX_PINCTRL_PIN(MX27_PAD_RTCK),
IMX_PINCTRL_PIN(MX27_PAD_RESET_OUT_B),
IMX_PINCTRL_PIN(MX27_PAD_SD1_D0),
IMX_PINCTRL_PIN(MX27_PAD_SD1_D1),
IMX_PINCTRL_PIN(MX27_PAD_SD1_D2),
IMX_PINCTRL_PIN(MX27_PAD_SD1_D3),
IMX_PINCTRL_PIN(MX27_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7),
IMX_PINCTRL_PIN(MX27_PAD_NFRB),
IMX_PINCTRL_PIN(MX27_PAD_NFCLE),
IMX_PINCTRL_PIN(MX27_PAD_NFWP_B),
IMX_PINCTRL_PIN(MX27_PAD_NFCE_B),
IMX_PINCTRL_PIN(MX27_PAD_NFALE),
IMX_PINCTRL_PIN(MX27_PAD_NFRE_B),
IMX_PINCTRL_PIN(MX27_PAD_NFWE_B),
IMX_PINCTRL_PIN(MX27_PAD_PC_POE),
IMX_PINCTRL_PIN(MX27_PAD_PC_RW_B),
IMX_PINCTRL_PIN(MX27_PAD_IOIS16),
IMX_PINCTRL_PIN(MX27_PAD_PC_RST),
IMX_PINCTRL_PIN(MX27_PAD_PC_BVD2),
IMX_PINCTRL_PIN(MX27_PAD_PC_BVD1),
IMX_PINCTRL_PIN(MX27_PAD_PC_VS2),
IMX_PINCTRL_PIN(MX27_PAD_PC_VS1),
IMX_PINCTRL_PIN(MX27_PAD_CLKO),
IMX_PINCTRL_PIN(MX27_PAD_PC_PWRON),
IMX_PINCTRL_PIN(MX27_PAD_PC_READY),
IMX_PINCTRL_PIN(MX27_PAD_PC_WAIT_B),
IMX_PINCTRL_PIN(MX27_PAD_PC_CD2_B),
IMX_PINCTRL_PIN(MX27_PAD_PC_CD1_B),
IMX_PINCTRL_PIN(MX27_PAD_CS4_B),
IMX_PINCTRL_PIN(MX27_PAD_CS5_B),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15),
};
static struct imx1_pinctrl_soc_info imx27_pinctrl_info = {
.pins = imx27_pinctrl_pads,
.npins = ARRAY_SIZE(imx27_pinctrl_pads),
};
static const struct of_device_id imx27_pinctrl_of_match[] = {
{ .compatible = "fsl,imx27-iomuxc", },
{ /* sentinel */ }
};
static int imx27_pinctrl_probe(struct platform_device *pdev)
{
return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info);
}
static struct platform_driver imx27_pinctrl_driver = {
.driver = {
.name = "imx27-pinctrl",
.owner = THIS_MODULE,
.of_match_table = of_match_ptr(imx27_pinctrl_of_match),
},
.probe = imx27_pinctrl_probe,
.remove = imx1_pinctrl_core_remove,
};
static int __init imx27_pinctrl_init(void)
{
return platform_driver_register(&imx27_pinctrl_driver);
}
arch_initcall(imx27_pinctrl_init);
static void __exit imx27_pinctrl_exit(void)
{
platform_driver_unregister(&imx27_pinctrl_driver);
}
module_exit(imx27_pinctrl_exit);
MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>");
MODULE_DESCRIPTION("Freescale IMX27 pinctrl driver");
MODULE_LICENSE("GPL v2");

421
drivers/pinctrl/freescale/pinctrl-imx28.c Normal file
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/*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mxs.h"
enum imx28_pin_enum {
GPMI_D00 = PINID(0, 0),
GPMI_D01 = PINID(0, 1),
GPMI_D02 = PINID(0, 2),
GPMI_D03 = PINID(0, 3),
GPMI_D04 = PINID(0, 4),
GPMI_D05 = PINID(0, 5),
GPMI_D06 = PINID(0, 6),
GPMI_D07 = PINID(0, 7),
GPMI_CE0N = PINID(0, 16),
GPMI_CE1N = PINID(0, 17),
GPMI_CE2N = PINID(0, 18),
GPMI_CE3N = PINID(0, 19),
GPMI_RDY0 = PINID(0, 20),
GPMI_RDY1 = PINID(0, 21),
GPMI_RDY2 = PINID(0, 22),
GPMI_RDY3 = PINID(0, 23),
GPMI_RDN = PINID(0, 24),
GPMI_WRN = PINID(0, 25),
GPMI_ALE = PINID(0, 26),
GPMI_CLE = PINID(0, 27),
GPMI_RESETN = PINID(0, 28),
LCD_D00 = PINID(1, 0),
LCD_D01 = PINID(1, 1),
LCD_D02 = PINID(1, 2),
LCD_D03 = PINID(1, 3),
LCD_D04 = PINID(1, 4),
LCD_D05 = PINID(1, 5),
LCD_D06 = PINID(1, 6),
LCD_D07 = PINID(1, 7),
LCD_D08 = PINID(1, 8),
LCD_D09 = PINID(1, 9),
LCD_D10 = PINID(1, 10),
LCD_D11 = PINID(1, 11),
LCD_D12 = PINID(1, 12),
LCD_D13 = PINID(1, 13),
LCD_D14 = PINID(1, 14),
LCD_D15 = PINID(1, 15),
LCD_D16 = PINID(1, 16),
LCD_D17 = PINID(1, 17),
LCD_D18 = PINID(1, 18),
LCD_D19 = PINID(1, 19),
LCD_D20 = PINID(1, 20),
LCD_D21 = PINID(1, 21),
LCD_D22 = PINID(1, 22),
LCD_D23 = PINID(1, 23),
LCD_RD_E = PINID(1, 24),
LCD_WR_RWN = PINID(1, 25),
LCD_RS = PINID(1, 26),
LCD_CS = PINID(1, 27),
LCD_VSYNC = PINID(1, 28),
LCD_HSYNC = PINID(1, 29),
LCD_DOTCLK = PINID(1, 30),
LCD_ENABLE = PINID(1, 31),
SSP0_DATA0 = PINID(2, 0),
SSP0_DATA1 = PINID(2, 1),
SSP0_DATA2 = PINID(2, 2),
SSP0_DATA3 = PINID(2, 3),
SSP0_DATA4 = PINID(2, 4),
SSP0_DATA5 = PINID(2, 5),
SSP0_DATA6 = PINID(2, 6),
SSP0_DATA7 = PINID(2, 7),
SSP0_CMD = PINID(2, 8),
SSP0_DETECT = PINID(2, 9),
SSP0_SCK = PINID(2, 10),
SSP1_SCK = PINID(2, 12),
SSP1_CMD = PINID(2, 13),
SSP1_DATA0 = PINID(2, 14),
SSP1_DATA3 = PINID(2, 15),
SSP2_SCK = PINID(2, 16),
SSP2_MOSI = PINID(2, 17),
SSP2_MISO = PINID(2, 18),
SSP2_SS0 = PINID(2, 19),
SSP2_SS1 = PINID(2, 20),
SSP2_SS2 = PINID(2, 21),
SSP3_SCK = PINID(2, 24),
SSP3_MOSI = PINID(2, 25),
SSP3_MISO = PINID(2, 26),
SSP3_SS0 = PINID(2, 27),
AUART0_RX = PINID(3, 0),
AUART0_TX = PINID(3, 1),
AUART0_CTS = PINID(3, 2),
AUART0_RTS = PINID(3, 3),
AUART1_RX = PINID(3, 4),
AUART1_TX = PINID(3, 5),
AUART1_CTS = PINID(3, 6),
AUART1_RTS = PINID(3, 7),
AUART2_RX = PINID(3, 8),
AUART2_TX = PINID(3, 9),
AUART2_CTS = PINID(3, 10),
AUART2_RTS = PINID(3, 11),
AUART3_RX = PINID(3, 12),
AUART3_TX = PINID(3, 13),
AUART3_CTS = PINID(3, 14),
AUART3_RTS = PINID(3, 15),
PWM0 = PINID(3, 16),
PWM1 = PINID(3, 17),
PWM2 = PINID(3, 18),
SAIF0_MCLK = PINID(3, 20),
SAIF0_LRCLK = PINID(3, 21),
SAIF0_BITCLK = PINID(3, 22),
SAIF0_SDATA0 = PINID(3, 23),
I2C0_SCL = PINID(3, 24),
I2C0_SDA = PINID(3, 25),
SAIF1_SDATA0 = PINID(3, 26),
SPDIF = PINID(3, 27),
PWM3 = PINID(3, 28),
PWM4 = PINID(3, 29),
LCD_RESET = PINID(3, 30),
ENET0_MDC = PINID(4, 0),
ENET0_MDIO = PINID(4, 1),
ENET0_RX_EN = PINID(4, 2),
ENET0_RXD0 = PINID(4, 3),
ENET0_RXD1 = PINID(4, 4),
ENET0_TX_CLK = PINID(4, 5),
ENET0_TX_EN = PINID(4, 6),
ENET0_TXD0 = PINID(4, 7),
ENET0_TXD1 = PINID(4, 8),
ENET0_RXD2 = PINID(4, 9),
ENET0_RXD3 = PINID(4, 10),
ENET0_TXD2 = PINID(4, 11),
ENET0_TXD3 = PINID(4, 12),
ENET0_RX_CLK = PINID(4, 13),
ENET0_COL = PINID(4, 14),
ENET0_CRS = PINID(4, 15),
ENET_CLK = PINID(4, 16),
JTAG_RTCK = PINID(4, 20),
EMI_D00 = PINID(5, 0),
EMI_D01 = PINID(5, 1),
EMI_D02 = PINID(5, 2),
EMI_D03 = PINID(5, 3),
EMI_D04 = PINID(5, 4),
EMI_D05 = PINID(5, 5),
EMI_D06 = PINID(5, 6),
EMI_D07 = PINID(5, 7),
EMI_D08 = PINID(5, 8),
EMI_D09 = PINID(5, 9),
EMI_D10 = PINID(5, 10),
EMI_D11 = PINID(5, 11),
EMI_D12 = PINID(5, 12),
EMI_D13 = PINID(5, 13),
EMI_D14 = PINID(5, 14),
EMI_D15 = PINID(5, 15),
EMI_ODT0 = PINID(5, 16),
EMI_DQM0 = PINID(5, 17),
EMI_ODT1 = PINID(5, 18),
EMI_DQM1 = PINID(5, 19),
EMI_DDR_OPEN_FB = PINID(5, 20),
EMI_CLK = PINID(5, 21),
EMI_DQS0 = PINID(5, 22),
EMI_DQS1 = PINID(5, 23),
EMI_DDR_OPEN = PINID(5, 26),
EMI_A00 = PINID(6, 0),
EMI_A01 = PINID(6, 1),
EMI_A02 = PINID(6, 2),
EMI_A03 = PINID(6, 3),
EMI_A04 = PINID(6, 4),
EMI_A05 = PINID(6, 5),
EMI_A06 = PINID(6, 6),
EMI_A07 = PINID(6, 7),
EMI_A08 = PINID(6, 8),
EMI_A09 = PINID(6, 9),
EMI_A10 = PINID(6, 10),
EMI_A11 = PINID(6, 11),
EMI_A12 = PINID(6, 12),
EMI_A13 = PINID(6, 13),
EMI_A14 = PINID(6, 14),
EMI_BA0 = PINID(6, 16),
EMI_BA1 = PINID(6, 17),
EMI_BA2 = PINID(6, 18),
EMI_CASN = PINID(6, 19),
EMI_RASN = PINID(6, 20),
EMI_WEN = PINID(6, 21),
EMI_CE0N = PINID(6, 22),
EMI_CE1N = PINID(6, 23),
EMI_CKE = PINID(6, 24),
};
static const struct pinctrl_pin_desc imx28_pins[] = {
MXS_PINCTRL_PIN(GPMI_D00),
MXS_PINCTRL_PIN(GPMI_D01),
MXS_PINCTRL_PIN(GPMI_D02),
MXS_PINCTRL_PIN(GPMI_D03),
MXS_PINCTRL_PIN(GPMI_D04),
MXS_PINCTRL_PIN(GPMI_D05),
MXS_PINCTRL_PIN(GPMI_D06),
MXS_PINCTRL_PIN(GPMI_D07),
MXS_PINCTRL_PIN(GPMI_CE0N),
MXS_PINCTRL_PIN(GPMI_CE1N),
MXS_PINCTRL_PIN(GPMI_CE2N),
MXS_PINCTRL_PIN(GPMI_CE3N),
MXS_PINCTRL_PIN(GPMI_RDY0),
MXS_PINCTRL_PIN(GPMI_RDY1),
MXS_PINCTRL_PIN(GPMI_RDY2),
MXS_PINCTRL_PIN(GPMI_RDY3),
MXS_PINCTRL_PIN(GPMI_RDN),
MXS_PINCTRL_PIN(GPMI_WRN),
MXS_PINCTRL_PIN(GPMI_ALE),
MXS_PINCTRL_PIN(GPMI_CLE),
MXS_PINCTRL_PIN(GPMI_RESETN),
MXS_PINCTRL_PIN(LCD_D00),
MXS_PINCTRL_PIN(LCD_D01),
MXS_PINCTRL_PIN(LCD_D02),
MXS_PINCTRL_PIN(LCD_D03),
MXS_PINCTRL_PIN(LCD_D04),
MXS_PINCTRL_PIN(LCD_D05),
MXS_PINCTRL_PIN(LCD_D06),
MXS_PINCTRL_PIN(LCD_D07),
MXS_PINCTRL_PIN(LCD_D08),
MXS_PINCTRL_PIN(LCD_D09),
MXS_PINCTRL_PIN(LCD_D10),
MXS_PINCTRL_PIN(LCD_D11),
MXS_PINCTRL_PIN(LCD_D12),
MXS_PINCTRL_PIN(LCD_D13),
MXS_PINCTRL_PIN(LCD_D14),
MXS_PINCTRL_PIN(LCD_D15),
MXS_PINCTRL_PIN(LCD_D16),
MXS_PINCTRL_PIN(LCD_D17),
MXS_PINCTRL_PIN(LCD_D18),
MXS_PINCTRL_PIN(LCD_D19),
MXS_PINCTRL_PIN(LCD_D20),
MXS_PINCTRL_PIN(LCD_D21),
MXS_PINCTRL_PIN(LCD_D22),
MXS_PINCTRL_PIN(LCD_D23),
MXS_PINCTRL_PIN(LCD_RD_E),
MXS_PINCTRL_PIN(LCD_WR_RWN),
MXS_PINCTRL_PIN(LCD_RS),
MXS_PINCTRL_PIN(LCD_CS),
MXS_PINCTRL_PIN(LCD_VSYNC),
MXS_PINCTRL_PIN(LCD_HSYNC),
MXS_PINCTRL_PIN(LCD_DOTCLK),
MXS_PINCTRL_PIN(LCD_ENABLE),
MXS_PINCTRL_PIN(SSP0_DATA0),
MXS_PINCTRL_PIN(SSP0_DATA1),
MXS_PINCTRL_PIN(SSP0_DATA2),
MXS_PINCTRL_PIN(SSP0_DATA3),
MXS_PINCTRL_PIN(SSP0_DATA4),
MXS_PINCTRL_PIN(SSP0_DATA5),
MXS_PINCTRL_PIN(SSP0_DATA6),
MXS_PINCTRL_PIN(SSP0_DATA7),
MXS_PINCTRL_PIN(SSP0_CMD),
MXS_PINCTRL_PIN(SSP0_DETECT),
MXS_PINCTRL_PIN(SSP0_SCK),
MXS_PINCTRL_PIN(SSP1_SCK),
MXS_PINCTRL_PIN(SSP1_CMD),
MXS_PINCTRL_PIN(SSP1_DATA0),
MXS_PINCTRL_PIN(SSP1_DATA3),
MXS_PINCTRL_PIN(SSP2_SCK),
MXS_PINCTRL_PIN(SSP2_MOSI),
MXS_PINCTRL_PIN(SSP2_MISO),
MXS_PINCTRL_PIN(SSP2_SS0),
MXS_PINCTRL_PIN(SSP2_SS1),
MXS_PINCTRL_PIN(SSP2_SS2),
MXS_PINCTRL_PIN(SSP3_SCK),
MXS_PINCTRL_PIN(SSP3_MOSI),
MXS_PINCTRL_PIN(SSP3_MISO),
MXS_PINCTRL_PIN(SSP3_SS0),
MXS_PINCTRL_PIN(AUART0_RX),
MXS_PINCTRL_PIN(AUART0_TX),
MXS_PINCTRL_PIN(AUART0_CTS),
MXS_PINCTRL_PIN(AUART0_RTS),
MXS_PINCTRL_PIN(AUART1_RX),
MXS_PINCTRL_PIN(AUART1_TX),
MXS_PINCTRL_PIN(AUART1_CTS),
MXS_PINCTRL_PIN(AUART1_RTS),
MXS_PINCTRL_PIN(AUART2_RX),
MXS_PINCTRL_PIN(AUART2_TX),
MXS_PINCTRL_PIN(AUART2_CTS),
MXS_PINCTRL_PIN(AUART2_RTS),
MXS_PINCTRL_PIN(AUART3_RX),
MXS_PINCTRL_PIN(AUART3_TX),
MXS_PINCTRL_PIN(AUART3_CTS),
MXS_PINCTRL_PIN(AUART3_RTS),
MXS_PINCTRL_PIN(PWM0),
MXS_PINCTRL_PIN(PWM1),
MXS_PINCTRL_PIN(PWM2),
MXS_PINCTRL_PIN(SAIF0_MCLK),
MXS_PINCTRL_PIN(SAIF0_LRCLK),
MXS_PINCTRL_PIN(SAIF0_BITCLK),
MXS_PINCTRL_PIN(SAIF0_SDATA0),
MXS_PINCTRL_PIN(I2C0_SCL),
MXS_PINCTRL_PIN(I2C0_SDA),
MXS_PINCTRL_PIN(SAIF1_SDATA0),
MXS_PINCTRL_PIN(SPDIF),
MXS_PINCTRL_PIN(PWM3),
MXS_PINCTRL_PIN(PWM4),
MXS_PINCTRL_PIN(LCD_RESET),
MXS_PINCTRL_PIN(ENET0_MDC),
MXS_PINCTRL_PIN(ENET0_MDIO),
MXS_PINCTRL_PIN(ENET0_RX_EN),
MXS_PINCTRL_PIN(ENET0_RXD0),
MXS_PINCTRL_PIN(ENET0_RXD1),
MXS_PINCTRL_PIN(ENET0_TX_CLK),
MXS_PINCTRL_PIN(ENET0_TX_EN),
MXS_PINCTRL_PIN(ENET0_TXD0),
MXS_PINCTRL_PIN(ENET0_TXD1),
MXS_PINCTRL_PIN(ENET0_RXD2),
MXS_PINCTRL_PIN(ENET0_RXD3),
MXS_PINCTRL_PIN(ENET0_TXD2),
MXS_PINCTRL_PIN(ENET0_TXD3),
MXS_PINCTRL_PIN(ENET0_RX_CLK),
MXS_PINCTRL_PIN(ENET0_COL),
MXS_PINCTRL_PIN(ENET0_CRS),
MXS_PINCTRL_PIN(ENET_CLK),
MXS_PINCTRL_PIN(JTAG_RTCK),
MXS_PINCTRL_PIN(EMI_D00),
MXS_PINCTRL_PIN(EMI_D01),
MXS_PINCTRL_PIN(EMI_D02),
MXS_PINCTRL_PIN(EMI_D03),
MXS_PINCTRL_PIN(EMI_D04),
MXS_PINCTRL_PIN(EMI_D05),
MXS_PINCTRL_PIN(EMI_D06),
MXS_PINCTRL_PIN(EMI_D07),
MXS_PINCTRL_PIN(EMI_D08),
MXS_PINCTRL_PIN(EMI_D09),
MXS_PINCTRL_PIN(EMI_D10),
MXS_PINCTRL_PIN(EMI_D11),
MXS_PINCTRL_PIN(EMI_D12),
MXS_PINCTRL_PIN(EMI_D13),
MXS_PINCTRL_PIN(EMI_D14),
MXS_PINCTRL_PIN(EMI_D15),
MXS_PINCTRL_PIN(EMI_ODT0),
MXS_PINCTRL_PIN(EMI_DQM0),
MXS_PINCTRL_PIN(EMI_ODT1),
MXS_PINCTRL_PIN(EMI_DQM1),
MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB),
MXS_PINCTRL_PIN(EMI_CLK),
MXS_PINCTRL_PIN(EMI_DQS0),
MXS_PINCTRL_PIN(EMI_DQS1),
MXS_PINCTRL_PIN(EMI_DDR_OPEN),
MXS_PINCTRL_PIN(EMI_A00),
MXS_PINCTRL_PIN(EMI_A01),
MXS_PINCTRL_PIN(EMI_A02),
MXS_PINCTRL_PIN(EMI_A03),
MXS_PINCTRL_PIN(EMI_A04),
MXS_PINCTRL_PIN(EMI_A05),
MXS_PINCTRL_PIN(EMI_A06),
MXS_PINCTRL_PIN(EMI_A07),
MXS_PINCTRL_PIN(EMI_A08),
MXS_PINCTRL_PIN(EMI_A09),
MXS_PINCTRL_PIN(EMI_A10),
MXS_PINCTRL_PIN(EMI_A11),
MXS_PINCTRL_PIN(EMI_A12),
MXS_PINCTRL_PIN(EMI_A13),
MXS_PINCTRL_PIN(EMI_A14),
MXS_PINCTRL_PIN(EMI_BA0),
MXS_PINCTRL_PIN(EMI_BA1),
MXS_PINCTRL_PIN(EMI_BA2),
MXS_PINCTRL_PIN(EMI_CASN),
MXS_PINCTRL_PIN(EMI_RASN),
MXS_PINCTRL_PIN(EMI_WEN),
MXS_PINCTRL_PIN(EMI_CE0N),
MXS_PINCTRL_PIN(EMI_CE1N),
MXS_PINCTRL_PIN(EMI_CKE),
};
static struct mxs_regs imx28_regs = {
.muxsel = 0x100,
.drive = 0x300,
.pull = 0x600,
};
static struct mxs_pinctrl_soc_data imx28_pinctrl_data = {
.regs = &imx28_regs,
.pins = imx28_pins,
.npins = ARRAY_SIZE(imx28_pins),
};
static int imx28_pinctrl_probe(struct platform_device *pdev)
{
return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
}
static const struct of_device_id imx28_pinctrl_of_match[] = {
{ .compatible = "fsl,imx28-pinctrl", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match);
static struct platform_driver imx28_pinctrl_driver = {
.driver = {
.name = "imx28-pinctrl",
.owner = THIS_MODULE,
.of_match_table = imx28_pinctrl_of_match,
},
.probe = imx28_pinctrl_probe,
.remove = mxs_pinctrl_remove,
};
static int __init imx28_pinctrl_init(void)
{
return platform_driver_register(&imx28_pinctrl_driver);
}
postcore_initcall(imx28_pinctrl_init);
static void __exit imx28_pinctrl_exit(void)
{
platform_driver_unregister(&imx28_pinctrl_driver);
}
module_exit(imx28_pinctrl_exit);
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver");
MODULE_LICENSE("GPL v2");

1041
drivers/pinctrl/freescale/pinctrl-imx35.c Normal file
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426
drivers/pinctrl/freescale/pinctrl-imx50.c Normal file
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/*
* imx50 pinctrl driver based on imx pinmux core
*
* Copyright (C) 2013 Greg Ungerer <gerg@uclinux.org>
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx50_pads {
MX50_PAD_RESERVE0 = 0,
MX50_PAD_RESERVE1 = 1,
MX50_PAD_RESERVE2 = 2,
MX50_PAD_RESERVE3 = 3,
MX50_PAD_RESERVE4 = 4,
MX50_PAD_RESERVE5 = 5,
MX50_PAD_RESERVE6 = 6,
MX50_PAD_RESERVE7 = 7,
MX50_PAD_KEY_COL0 = 8,
MX50_PAD_KEY_ROW0 = 9,
MX50_PAD_KEY_COL1 = 10,
MX50_PAD_KEY_ROW1 = 11,
MX50_PAD_KEY_COL2 = 12,
MX50_PAD_KEY_ROW2 = 13,
MX50_PAD_KEY_COL3 = 14,
MX50_PAD_KEY_ROW3 = 15,
MX50_PAD_I2C1_SCL = 16,
MX50_PAD_I2C1_SDA = 17,
MX50_PAD_I2C2_SCL = 18,
MX50_PAD_I2C2_SDA = 19,
MX50_PAD_I2C3_SCL = 20,
MX50_PAD_I2C3_SDA = 21,
MX50_PAD_PWM1 = 22,
MX50_PAD_PWM2 = 23,
MX50_PAD_0WIRE = 24,
MX50_PAD_EPITO = 25,
MX50_PAD_WDOG = 26,
MX50_PAD_SSI_TXFS = 27,
MX50_PAD_SSI_TXC = 28,
MX50_PAD_SSI_TXD = 29,
MX50_PAD_SSI_RXD = 30,
MX50_PAD_SSI_RXF = 31,
MX50_PAD_SSI_RXC = 32,
MX50_PAD_UART1_TXD = 33,
MX50_PAD_UART1_RXD = 34,
MX50_PAD_UART1_CTS = 35,
MX50_PAD_UART1_RTS = 36,
MX50_PAD_UART2_TXD = 37,
MX50_PAD_UART2_RXD = 38,
MX50_PAD_UART2_CTS = 39,
MX50_PAD_UART2_RTS = 40,
MX50_PAD_UART3_TXD = 41,
MX50_PAD_UART3_RXD = 42,
MX50_PAD_UART4_TXD = 43,
MX50_PAD_UART4_RXD = 44,
MX50_PAD_CSPI_CLK = 45,
MX50_PAD_CSPI_MOSI = 46,
MX50_PAD_CSPI_MISO = 47,
MX50_PAD_CSPI_SS0 = 48,
MX50_PAD_ECSPI1_CLK = 49,
MX50_PAD_ECSPI1_MOSI = 50,
MX50_PAD_ECSPI1_MISO = 51,
MX50_PAD_ECSPI1_SS0 = 52,
MX50_PAD_ECSPI2_CLK = 53,
MX50_PAD_ECSPI2_MOSI = 54,
MX50_PAD_ECSPI2_MISO = 55,
MX50_PAD_ECSPI2_SS0 = 56,
MX50_PAD_SD1_CLK = 57,
MX50_PAD_SD1_CMD = 58,
MX50_PAD_SD1_D0 = 59,
MX50_PAD_SD1_D1 = 60,
MX50_PAD_SD1_D2 = 61,
MX50_PAD_SD1_D3 = 62,
MX50_PAD_SD2_CLK = 63,
MX50_PAD_SD2_CMD = 64,
MX50_PAD_SD2_D0 = 65,
MX50_PAD_SD2_D1 = 66,
MX50_PAD_SD2_D2 = 67,
MX50_PAD_SD2_D3 = 68,
MX50_PAD_SD2_D4 = 69,
MX50_PAD_SD2_D5 = 70,
MX50_PAD_SD2_D6 = 71,
MX50_PAD_SD2_D7 = 72,
MX50_PAD_SD2_WP = 73,
MX50_PAD_SD2_CD = 74,
MX50_PAD_DISP_D0 = 75,
MX50_PAD_DISP_D1 = 76,
MX50_PAD_DISP_D2 = 77,
MX50_PAD_DISP_D3 = 78,
MX50_PAD_DISP_D4 = 79,
MX50_PAD_DISP_D5 = 80,
MX50_PAD_DISP_D6 = 81,
MX50_PAD_DISP_D7 = 82,
MX50_PAD_DISP_WR = 83,
MX50_PAD_DISP_RD = 84,
MX50_PAD_DISP_RS = 85,
MX50_PAD_DISP_CS = 86,
MX50_PAD_DISP_BUSY = 87,
MX50_PAD_DISP_RESET = 88,
MX50_PAD_SD3_CLK = 89,
MX50_PAD_SD3_CMD = 90,
MX50_PAD_SD3_D0 = 91,
MX50_PAD_SD3_D1 = 92,
MX50_PAD_SD3_D2 = 93,
MX50_PAD_SD3_D3 = 94,
MX50_PAD_SD3_D4 = 95,
MX50_PAD_SD3_D5 = 96,
MX50_PAD_SD3_D6 = 97,
MX50_PAD_SD3_D7 = 98,
MX50_PAD_SD3_WP = 99,
MX50_PAD_DISP_D8 = 100,
MX50_PAD_DISP_D9 = 101,
MX50_PAD_DISP_D10 = 102,
MX50_PAD_DISP_D11 = 103,
MX50_PAD_DISP_D12 = 104,
MX50_PAD_DISP_D13 = 105,
MX50_PAD_DISP_D14 = 106,
MX50_PAD_DISP_D15 = 107,
MX50_PAD_EPDC_D0 = 108,
MX50_PAD_EPDC_D1 = 109,
MX50_PAD_EPDC_D2 = 110,
MX50_PAD_EPDC_D3 = 111,
MX50_PAD_EPDC_D4 = 112,
MX50_PAD_EPDC_D5 = 113,
MX50_PAD_EPDC_D6 = 114,
MX50_PAD_EPDC_D7 = 115,
MX50_PAD_EPDC_D8 = 116,
MX50_PAD_EPDC_D9 = 117,
MX50_PAD_EPDC_D10 = 118,
MX50_PAD_EPDC_D11 = 119,
MX50_PAD_EPDC_D12 = 120,
MX50_PAD_EPDC_D13 = 121,
MX50_PAD_EPDC_D14 = 122,
MX50_PAD_EPDC_D15 = 123,
MX50_PAD_EPDC_GDCLK = 124,
MX50_PAD_EPDC_GDSP = 125,
MX50_PAD_EPDC_GDOE = 126,
MX50_PAD_EPDC_GDRL = 127,
MX50_PAD_EPDC_SDCLK = 128,
MX50_PAD_EPDC_SDOEZ = 129,
MX50_PAD_EPDC_SDOED = 130,
MX50_PAD_EPDC_SDOE = 131,
MX50_PAD_EPDC_SDLE = 132,
MX50_PAD_EPDC_SDCLKN = 133,
MX50_PAD_EPDC_SDSHR = 134,
MX50_PAD_EPDC_PWRCOM = 135,
MX50_PAD_EPDC_PWRSTAT = 136,
MX50_PAD_EPDC_PWRCTRL0 = 137,
MX50_PAD_EPDC_PWRCTRL1 = 138,
MX50_PAD_EPDC_PWRCTRL2 = 139,
MX50_PAD_EPDC_PWRCTRL3 = 140,
MX50_PAD_EPDC_VCOM0 = 141,
MX50_PAD_EPDC_VCOM1 = 142,
MX50_PAD_EPDC_BDR0 = 143,
MX50_PAD_EPDC_BDR1 = 144,
MX50_PAD_EPDC_SDCE0 = 145,
MX50_PAD_EPDC_SDCE1 = 146,
MX50_PAD_EPDC_SDCE2 = 147,
MX50_PAD_EPDC_SDCE3 = 148,
MX50_PAD_EPDC_SDCE4 = 149,
MX50_PAD_EPDC_SDCE5 = 150,
MX50_PAD_EIM_DA0 = 151,
MX50_PAD_EIM_DA1 = 152,
MX50_PAD_EIM_DA2 = 153,
MX50_PAD_EIM_DA3 = 154,
MX50_PAD_EIM_DA4 = 155,
MX50_PAD_EIM_DA5 = 156,
MX50_PAD_EIM_DA6 = 157,
MX50_PAD_EIM_DA7 = 158,
MX50_PAD_EIM_DA8 = 159,
MX50_PAD_EIM_DA9 = 160,
MX50_PAD_EIM_DA10 = 161,
MX50_PAD_EIM_DA11 = 162,
MX50_PAD_EIM_DA12 = 163,
MX50_PAD_EIM_DA13 = 164,
MX50_PAD_EIM_DA14 = 165,
MX50_PAD_EIM_DA15 = 166,
MX50_PAD_EIM_CS2 = 167,
MX50_PAD_EIM_CS1 = 168,
MX50_PAD_EIM_CS0 = 169,
MX50_PAD_EIM_EB0 = 170,
MX50_PAD_EIM_EB1 = 171,
MX50_PAD_EIM_WAIT = 172,
MX50_PAD_EIM_BCLK = 173,
MX50_PAD_EIM_RDY = 174,
MX50_PAD_EIM_OE = 175,
MX50_PAD_EIM_RW = 176,
MX50_PAD_EIM_LBA = 177,
MX50_PAD_EIM_CRE = 178,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX50_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3),
IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL),
IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA),
IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL),
IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA),
IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL),
IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA),
IMX_PINCTRL_PIN(MX50_PAD_PWM1),
IMX_PINCTRL_PIN(MX50_PAD_PWM2),
IMX_PINCTRL_PIN(MX50_PAD_0WIRE),
IMX_PINCTRL_PIN(MX50_PAD_EPITO),
IMX_PINCTRL_PIN(MX50_PAD_WDOG),
IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS),
IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC),
IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD),
IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD),
IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF),
IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC),
IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD),
IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD),
IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS),
IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS),
IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD),
IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD),
IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS),
IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS),
IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD),
IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD),
IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD),
IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD),
IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK),
IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI),
IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO),
IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0),
IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK),
IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI),
IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO),
IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0),
IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK),
IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI),
IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO),
IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0),
IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX50_PAD_SD1_D0),
IMX_PINCTRL_PIN(MX50_PAD_SD1_D1),
IMX_PINCTRL_PIN(MX50_PAD_SD1_D2),
IMX_PINCTRL_PIN(MX50_PAD_SD1_D3),
IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX50_PAD_SD2_D0),
IMX_PINCTRL_PIN(MX50_PAD_SD2_D1),
IMX_PINCTRL_PIN(MX50_PAD_SD2_D2),
IMX_PINCTRL_PIN(MX50_PAD_SD2_D3),
IMX_PINCTRL_PIN(MX50_PAD_SD2_D4),
IMX_PINCTRL_PIN(MX50_PAD_SD2_D5),
IMX_PINCTRL_PIN(MX50_PAD_SD2_D6),
IMX_PINCTRL_PIN(MX50_PAD_SD2_D7),
IMX_PINCTRL_PIN(MX50_PAD_SD2_WP),
IMX_PINCTRL_PIN(MX50_PAD_SD2_CD),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D0),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D1),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D2),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D3),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D4),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D5),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D6),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D7),
IMX_PINCTRL_PIN(MX50_PAD_DISP_WR),
IMX_PINCTRL_PIN(MX50_PAD_DISP_RD),
IMX_PINCTRL_PIN(MX50_PAD_DISP_RS),
IMX_PINCTRL_PIN(MX50_PAD_DISP_CS),
IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY),
IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET),
IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK),
IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD),
IMX_PINCTRL_PIN(MX50_PAD_SD3_D0),
IMX_PINCTRL_PIN(MX50_PAD_SD3_D1),
IMX_PINCTRL_PIN(MX50_PAD_SD3_D2),
IMX_PINCTRL_PIN(MX50_PAD_SD3_D3),
IMX_PINCTRL_PIN(MX50_PAD_SD3_D4),
IMX_PINCTRL_PIN(MX50_PAD_SD3_D5),
IMX_PINCTRL_PIN(MX50_PAD_SD3_D6),
IMX_PINCTRL_PIN(MX50_PAD_SD3_D7),
IMX_PINCTRL_PIN(MX50_PAD_SD3_WP),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D8),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D9),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D10),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D11),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D12),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D13),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D14),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D15),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15),
IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2),
IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1),
IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0),
IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0),
IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1),
IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT),
IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK),
IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY),
IMX_PINCTRL_PIN(MX50_PAD_EIM_OE),
IMX_PINCTRL_PIN(MX50_PAD_EIM_RW),
IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA),
IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE),
};
static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
.pins = imx50_pinctrl_pads,
.npins = ARRAY_SIZE(imx50_pinctrl_pads),
};
static const struct of_device_id imx50_pinctrl_of_match[] = {
{ .compatible = "fsl,imx50-iomuxc", },
{ /* sentinel */ }
};
static int imx50_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx50_pinctrl_info);
}
static struct platform_driver imx50_pinctrl_driver = {
.driver = {
.name = "imx50-pinctrl",
.owner = THIS_MODULE,
.of_match_table = of_match_ptr(imx50_pinctrl_of_match),
},
.probe = imx50_pinctrl_probe,
.remove = imx_pinctrl_remove,
};
static int __init imx50_pinctrl_init(void)
{
return platform_driver_register(&imx50_pinctrl_driver);
}
arch_initcall(imx50_pinctrl_init);
static void __exit imx50_pinctrl_exit(void)
{
platform_driver_unregister(&imx50_pinctrl_driver);
}
module_exit(imx50_pinctrl_exit);
MODULE_DESCRIPTION("Freescale IMX50 pinctrl driver");
MODULE_LICENSE("GPL v2");

804
drivers/pinctrl/freescale/pinctrl-imx51.c Normal file
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@ -0,0 +1,804 @@
/*
* imx51 pinctrl driver based on imx pinmux core
*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro, Inc.
*
* Author: Dong Aisheng <dong.aisheng@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx51_pads {
MX51_PAD_RESERVE0 = 0,
MX51_PAD_RESERVE1 = 1,
MX51_PAD_RESERVE2 = 2,
MX51_PAD_RESERVE3 = 3,
MX51_PAD_RESERVE4 = 4,
MX51_PAD_RESERVE5 = 5,
MX51_PAD_RESERVE6 = 6,
MX51_PAD_EIM_DA0 = 7,
MX51_PAD_EIM_DA1 = 8,
MX51_PAD_EIM_DA2 = 9,
MX51_PAD_EIM_DA3 = 10,
MX51_PAD_EIM_DA4 = 11,
MX51_PAD_EIM_DA5 = 12,
MX51_PAD_EIM_DA6 = 13,
MX51_PAD_EIM_DA7 = 14,
MX51_PAD_EIM_DA8 = 15,
MX51_PAD_EIM_DA9 = 16,
MX51_PAD_EIM_DA10 = 17,
MX51_PAD_EIM_DA11 = 18,
MX51_PAD_EIM_DA12 = 19,
MX51_PAD_EIM_DA13 = 20,
MX51_PAD_EIM_DA14 = 21,
MX51_PAD_EIM_DA15 = 22,
MX51_PAD_EIM_D16 = 23,
MX51_PAD_EIM_D17 = 24,
MX51_PAD_EIM_D18 = 25,
MX51_PAD_EIM_D19 = 26,
MX51_PAD_EIM_D20 = 27,
MX51_PAD_EIM_D21 = 28,
MX51_PAD_EIM_D22 = 29,
MX51_PAD_EIM_D23 = 30,
MX51_PAD_EIM_D24 = 31,
MX51_PAD_EIM_D25 = 32,
MX51_PAD_EIM_D26 = 33,
MX51_PAD_EIM_D27 = 34,
MX51_PAD_EIM_D28 = 35,
MX51_PAD_EIM_D29 = 36,
MX51_PAD_EIM_D30 = 37,
MX51_PAD_EIM_D31 = 38,
MX51_PAD_EIM_A16 = 39,
MX51_PAD_EIM_A17 = 40,
MX51_PAD_EIM_A18 = 41,
MX51_PAD_EIM_A19 = 42,
MX51_PAD_EIM_A20 = 43,
MX51_PAD_EIM_A21 = 44,
MX51_PAD_EIM_A22 = 45,
MX51_PAD_EIM_A23 = 46,
MX51_PAD_EIM_A24 = 47,
MX51_PAD_EIM_A25 = 48,
MX51_PAD_EIM_A26 = 49,
MX51_PAD_EIM_A27 = 50,
MX51_PAD_EIM_EB0 = 51,
MX51_PAD_EIM_EB1 = 52,
MX51_PAD_EIM_EB2 = 53,
MX51_PAD_EIM_EB3 = 54,
MX51_PAD_EIM_OE = 55,
MX51_PAD_EIM_CS0 = 56,
MX51_PAD_EIM_CS1 = 57,
MX51_PAD_EIM_CS2 = 58,
MX51_PAD_EIM_CS3 = 59,
MX51_PAD_EIM_CS4 = 60,
MX51_PAD_EIM_CS5 = 61,
MX51_PAD_EIM_DTACK = 62,
MX51_PAD_EIM_LBA = 63,
MX51_PAD_EIM_CRE = 64,
MX51_PAD_DRAM_CS1 = 65,
MX51_PAD_NANDF_WE_B = 66,
MX51_PAD_NANDF_RE_B = 67,
MX51_PAD_NANDF_ALE = 68,
MX51_PAD_NANDF_CLE = 69,
MX51_PAD_NANDF_WP_B = 70,
MX51_PAD_NANDF_RB0 = 71,
MX51_PAD_NANDF_RB1 = 72,
MX51_PAD_NANDF_RB2 = 73,
MX51_PAD_NANDF_RB3 = 74,
MX51_PAD_GPIO_NAND = 75,
MX51_PAD_NANDF_CS0 = 76,
MX51_PAD_NANDF_CS1 = 77,
MX51_PAD_NANDF_CS2 = 78,
MX51_PAD_NANDF_CS3 = 79,
MX51_PAD_NANDF_CS4 = 80,
MX51_PAD_NANDF_CS5 = 81,
MX51_PAD_NANDF_CS6 = 82,
MX51_PAD_NANDF_CS7 = 83,
MX51_PAD_NANDF_RDY_INT = 84,
MX51_PAD_NANDF_D15 = 85,
MX51_PAD_NANDF_D14 = 86,
MX51_PAD_NANDF_D13 = 87,
MX51_PAD_NANDF_D12 = 88,
MX51_PAD_NANDF_D11 = 89,
MX51_PAD_NANDF_D10 = 90,
MX51_PAD_NANDF_D9 = 91,
MX51_PAD_NANDF_D8 = 92,
MX51_PAD_NANDF_D7 = 93,
MX51_PAD_NANDF_D6 = 94,
MX51_PAD_NANDF_D5 = 95,
MX51_PAD_NANDF_D4 = 96,
MX51_PAD_NANDF_D3 = 97,
MX51_PAD_NANDF_D2 = 98,
MX51_PAD_NANDF_D1 = 99,
MX51_PAD_NANDF_D0 = 100,
MX51_PAD_CSI1_D8 = 101,
MX51_PAD_CSI1_D9 = 102,
MX51_PAD_CSI1_D10 = 103,
MX51_PAD_CSI1_D11 = 104,
MX51_PAD_CSI1_D12 = 105,
MX51_PAD_CSI1_D13 = 106,
MX51_PAD_CSI1_D14 = 107,
MX51_PAD_CSI1_D15 = 108,
MX51_PAD_CSI1_D16 = 109,
MX51_PAD_CSI1_D17 = 110,
MX51_PAD_CSI1_D18 = 111,
MX51_PAD_CSI1_D19 = 112,
MX51_PAD_CSI1_VSYNC = 113,
MX51_PAD_CSI1_HSYNC = 114,
MX51_PAD_CSI2_D12 = 115,
MX51_PAD_CSI2_D13 = 116,
MX51_PAD_CSI2_D14 = 117,
MX51_PAD_CSI2_D15 = 118,
MX51_PAD_CSI2_D16 = 119,
MX51_PAD_CSI2_D17 = 120,
MX51_PAD_CSI2_D18 = 121,
MX51_PAD_CSI2_D19 = 122,
MX51_PAD_CSI2_VSYNC = 123,
MX51_PAD_CSI2_HSYNC = 124,
MX51_PAD_CSI2_PIXCLK = 125,
MX51_PAD_I2C1_CLK = 126,
MX51_PAD_I2C1_DAT = 127,
MX51_PAD_AUD3_BB_TXD = 128,
MX51_PAD_AUD3_BB_RXD = 129,
MX51_PAD_AUD3_BB_CK = 130,
MX51_PAD_AUD3_BB_FS = 131,
MX51_PAD_CSPI1_MOSI = 132,
MX51_PAD_CSPI1_MISO = 133,
MX51_PAD_CSPI1_SS0 = 134,
MX51_PAD_CSPI1_SS1 = 135,
MX51_PAD_CSPI1_RDY = 136,
MX51_PAD_CSPI1_SCLK = 137,
MX51_PAD_UART1_RXD = 138,
MX51_PAD_UART1_TXD = 139,
MX51_PAD_UART1_RTS = 140,
MX51_PAD_UART1_CTS = 141,
MX51_PAD_UART2_RXD = 142,
MX51_PAD_UART2_TXD = 143,
MX51_PAD_UART3_RXD = 144,
MX51_PAD_UART3_TXD = 145,
MX51_PAD_OWIRE_LINE = 146,
MX51_PAD_KEY_ROW0 = 147,
MX51_PAD_KEY_ROW1 = 148,
MX51_PAD_KEY_ROW2 = 149,
MX51_PAD_KEY_ROW3 = 150,
MX51_PAD_KEY_COL0 = 151,
MX51_PAD_KEY_COL1 = 152,
MX51_PAD_KEY_COL2 = 153,
MX51_PAD_KEY_COL3 = 154,
MX51_PAD_KEY_COL4 = 155,
MX51_PAD_KEY_COL5 = 156,
MX51_PAD_RESERVE7 = 157,
MX51_PAD_USBH1_CLK = 158,
MX51_PAD_USBH1_DIR = 159,
MX51_PAD_USBH1_STP = 160,
MX51_PAD_USBH1_NXT = 161,
MX51_PAD_USBH1_DATA0 = 162,
MX51_PAD_USBH1_DATA1 = 163,
MX51_PAD_USBH1_DATA2 = 164,
MX51_PAD_USBH1_DATA3 = 165,
MX51_PAD_USBH1_DATA4 = 166,
MX51_PAD_USBH1_DATA5 = 167,
MX51_PAD_USBH1_DATA6 = 168,
MX51_PAD_USBH1_DATA7 = 169,
MX51_PAD_DI1_PIN11 = 170,
MX51_PAD_DI1_PIN12 = 171,
MX51_PAD_DI1_PIN13 = 172,
MX51_PAD_DI1_D0_CS = 173,
MX51_PAD_DI1_D1_CS = 174,
MX51_PAD_DISPB2_SER_DIN = 175,
MX51_PAD_DISPB2_SER_DIO = 176,
MX51_PAD_DISPB2_SER_CLK = 177,
MX51_PAD_DISPB2_SER_RS = 178,
MX51_PAD_DISP1_DAT0 = 179,
MX51_PAD_DISP1_DAT1 = 180,
MX51_PAD_DISP1_DAT2 = 181,
MX51_PAD_DISP1_DAT3 = 182,
MX51_PAD_DISP1_DAT4 = 183,
MX51_PAD_DISP1_DAT5 = 184,
MX51_PAD_DISP1_DAT6 = 185,
MX51_PAD_DISP1_DAT7 = 186,
MX51_PAD_DISP1_DAT8 = 187,
MX51_PAD_DISP1_DAT9 = 188,
MX51_PAD_DISP1_DAT10 = 189,
MX51_PAD_DISP1_DAT11 = 190,
MX51_PAD_DISP1_DAT12 = 191,
MX51_PAD_DISP1_DAT13 = 192,
MX51_PAD_DISP1_DAT14 = 193,
MX51_PAD_DISP1_DAT15 = 194,
MX51_PAD_DISP1_DAT16 = 195,
MX51_PAD_DISP1_DAT17 = 196,
MX51_PAD_DISP1_DAT18 = 197,
MX51_PAD_DISP1_DAT19 = 198,
MX51_PAD_DISP1_DAT20 = 199,
MX51_PAD_DISP1_DAT21 = 200,
MX51_PAD_DISP1_DAT22 = 201,
MX51_PAD_DISP1_DAT23 = 202,
MX51_PAD_DI1_PIN3 = 203,
MX51_PAD_DI1_PIN2 = 204,
MX51_PAD_RESERVE8 = 205,
MX51_PAD_DI_GP2 = 206,
MX51_PAD_DI_GP3 = 207,
MX51_PAD_DI2_PIN4 = 208,
MX51_PAD_DI2_PIN2 = 209,
MX51_PAD_DI2_PIN3 = 210,
MX51_PAD_DI2_DISP_CLK = 211,
MX51_PAD_DI_GP4 = 212,
MX51_PAD_DISP2_DAT0 = 213,
MX51_PAD_DISP2_DAT1 = 214,
MX51_PAD_DISP2_DAT2 = 215,
MX51_PAD_DISP2_DAT3 = 216,
MX51_PAD_DISP2_DAT4 = 217,
MX51_PAD_DISP2_DAT5 = 218,
MX51_PAD_DISP2_DAT6 = 219,
MX51_PAD_DISP2_DAT7 = 220,
MX51_PAD_DISP2_DAT8 = 221,
MX51_PAD_DISP2_DAT9 = 222,
MX51_PAD_DISP2_DAT10 = 223,
MX51_PAD_DISP2_DAT11 = 224,
MX51_PAD_DISP2_DAT12 = 225,
MX51_PAD_DISP2_DAT13 = 226,
MX51_PAD_DISP2_DAT14 = 227,
MX51_PAD_DISP2_DAT15 = 228,
MX51_PAD_SD1_CMD = 229,
MX51_PAD_SD1_CLK = 230,
MX51_PAD_SD1_DATA0 = 231,
MX51_PAD_SD1_DATA1 = 232,
MX51_PAD_SD1_DATA2 = 233,
MX51_PAD_SD1_DATA3 = 234,
MX51_PAD_GPIO1_0 = 235,
MX51_PAD_GPIO1_1 = 236,
MX51_PAD_SD2_CMD = 237,
MX51_PAD_SD2_CLK = 238,
MX51_PAD_SD2_DATA0 = 239,
MX51_PAD_SD2_DATA1 = 240,
MX51_PAD_SD2_DATA2 = 241,
MX51_PAD_SD2_DATA3 = 242,
MX51_PAD_GPIO1_2 = 243,
MX51_PAD_GPIO1_3 = 244,
MX51_PAD_PMIC_INT_REQ = 245,
MX51_PAD_GPIO1_4 = 246,
MX51_PAD_GPIO1_5 = 247,
MX51_PAD_GPIO1_6 = 248,
MX51_PAD_GPIO1_7 = 249,
MX51_PAD_GPIO1_8 = 250,
MX51_PAD_GPIO1_9 = 251,
MX51_PAD_RESERVE9 = 252,
MX51_PAD_RESERVE10 = 253,
MX51_PAD_RESERVE11 = 254,
MX51_PAD_RESERVE12 = 255,
MX51_PAD_RESERVE13 = 256,
MX51_PAD_RESERVE14 = 257,
MX51_PAD_RESERVE15 = 258,
MX51_PAD_RESERVE16 = 259,
MX51_PAD_RESERVE17 = 260,
MX51_PAD_RESERVE18 = 261,
MX51_PAD_RESERVE19 = 262,
MX51_PAD_RESERVE20 = 263,
MX51_PAD_RESERVE21 = 264,
MX51_PAD_RESERVE22 = 265,
MX51_PAD_RESERVE23 = 266,
MX51_PAD_RESERVE24 = 267,
MX51_PAD_RESERVE25 = 268,
MX51_PAD_RESERVE26 = 269,
MX51_PAD_RESERVE27 = 270,
MX51_PAD_RESERVE28 = 271,
MX51_PAD_RESERVE29 = 272,
MX51_PAD_RESERVE30 = 273,
MX51_PAD_RESERVE31 = 274,
MX51_PAD_RESERVE32 = 275,
MX51_PAD_RESERVE33 = 276,
MX51_PAD_RESERVE34 = 277,
MX51_PAD_RESERVE35 = 278,
MX51_PAD_RESERVE36 = 279,
MX51_PAD_RESERVE37 = 280,
MX51_PAD_RESERVE38 = 281,
MX51_PAD_RESERVE39 = 282,
MX51_PAD_RESERVE40 = 283,
MX51_PAD_RESERVE41 = 284,
MX51_PAD_RESERVE42 = 285,
MX51_PAD_RESERVE43 = 286,
MX51_PAD_RESERVE44 = 287,
MX51_PAD_RESERVE45 = 288,
MX51_PAD_RESERVE46 = 289,
MX51_PAD_RESERVE47 = 290,
MX51_PAD_RESERVE48 = 291,
MX51_PAD_RESERVE49 = 292,
MX51_PAD_RESERVE50 = 293,
MX51_PAD_RESERVE51 = 294,
MX51_PAD_RESERVE52 = 295,
MX51_PAD_RESERVE53 = 296,
MX51_PAD_RESERVE54 = 297,
MX51_PAD_RESERVE55 = 298,
MX51_PAD_RESERVE56 = 299,
MX51_PAD_RESERVE57 = 300,
MX51_PAD_RESERVE58 = 301,
MX51_PAD_RESERVE59 = 302,
MX51_PAD_RESERVE60 = 303,
MX51_PAD_RESERVE61 = 304,
MX51_PAD_RESERVE62 = 305,
MX51_PAD_RESERVE63 = 306,
MX51_PAD_RESERVE64 = 307,
MX51_PAD_RESERVE65 = 308,
MX51_PAD_RESERVE66 = 309,
MX51_PAD_RESERVE67 = 310,
MX51_PAD_RESERVE68 = 311,
MX51_PAD_RESERVE69 = 312,
MX51_PAD_RESERVE70 = 313,
MX51_PAD_RESERVE71 = 314,
MX51_PAD_RESERVE72 = 315,
MX51_PAD_RESERVE73 = 316,
MX51_PAD_RESERVE74 = 317,
MX51_PAD_RESERVE75 = 318,
MX51_PAD_RESERVE76 = 319,
MX51_PAD_RESERVE77 = 320,
MX51_PAD_RESERVE78 = 321,
MX51_PAD_RESERVE79 = 322,
MX51_PAD_RESERVE80 = 323,
MX51_PAD_RESERVE81 = 324,
MX51_PAD_RESERVE82 = 325,
MX51_PAD_RESERVE83 = 326,
MX51_PAD_RESERVE84 = 327,
MX51_PAD_RESERVE85 = 328,
MX51_PAD_RESERVE86 = 329,
MX51_PAD_RESERVE87 = 330,
MX51_PAD_RESERVE88 = 331,
MX51_PAD_RESERVE89 = 332,
MX51_PAD_RESERVE90 = 333,
MX51_PAD_RESERVE91 = 334,
MX51_PAD_RESERVE92 = 335,
MX51_PAD_RESERVE93 = 336,
MX51_PAD_RESERVE94 = 337,
MX51_PAD_RESERVE95 = 338,
MX51_PAD_RESERVE96 = 339,
MX51_PAD_RESERVE97 = 340,
MX51_PAD_RESERVE98 = 341,
MX51_PAD_RESERVE99 = 342,
MX51_PAD_RESERVE100 = 343,
MX51_PAD_RESERVE101 = 344,
MX51_PAD_RESERVE102 = 345,
MX51_PAD_RESERVE103 = 346,
MX51_PAD_RESERVE104 = 347,
MX51_PAD_RESERVE105 = 348,
MX51_PAD_RESERVE106 = 349,
MX51_PAD_RESERVE107 = 350,
MX51_PAD_RESERVE108 = 351,
MX51_PAD_RESERVE109 = 352,
MX51_PAD_RESERVE110 = 353,
MX51_PAD_RESERVE111 = 354,
MX51_PAD_RESERVE112 = 355,
MX51_PAD_RESERVE113 = 356,
MX51_PAD_RESERVE114 = 357,
MX51_PAD_RESERVE115 = 358,
MX51_PAD_RESERVE116 = 359,
MX51_PAD_RESERVE117 = 360,
MX51_PAD_RESERVE118 = 361,
MX51_PAD_RESERVE119 = 362,
MX51_PAD_RESERVE120 = 363,
MX51_PAD_RESERVE121 = 364,
MX51_PAD_CSI1_PIXCLK = 365,
MX51_PAD_CSI1_MCLK = 366,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX51_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA9),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA10),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA11),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA12),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA13),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA14),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA15),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D16),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D17),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D18),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D19),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D20),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D21),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D22),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D23),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D24),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D25),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D26),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D27),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D28),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D29),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D30),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D31),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A16),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A17),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A18),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A19),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A20),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A21),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A22),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A23),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A24),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A25),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A26),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A27),
IMX_PINCTRL_PIN(MX51_PAD_EIM_EB0),
IMX_PINCTRL_PIN(MX51_PAD_EIM_EB1),
IMX_PINCTRL_PIN(MX51_PAD_EIM_EB2),
IMX_PINCTRL_PIN(MX51_PAD_EIM_EB3),
IMX_PINCTRL_PIN(MX51_PAD_EIM_OE),
IMX_PINCTRL_PIN(MX51_PAD_EIM_CS0),
IMX_PINCTRL_PIN(MX51_PAD_EIM_CS1),
IMX_PINCTRL_PIN(MX51_PAD_EIM_CS2),
IMX_PINCTRL_PIN(MX51_PAD_EIM_CS3),
IMX_PINCTRL_PIN(MX51_PAD_EIM_CS4),
IMX_PINCTRL_PIN(MX51_PAD_EIM_CS5),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DTACK),
IMX_PINCTRL_PIN(MX51_PAD_EIM_LBA),
IMX_PINCTRL_PIN(MX51_PAD_EIM_CRE),
IMX_PINCTRL_PIN(MX51_PAD_DRAM_CS1),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_WE_B),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_RE_B),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_ALE),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CLE),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_WP_B),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB0),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB1),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB2),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB3),
IMX_PINCTRL_PIN(MX51_PAD_GPIO_NAND),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS0),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS1),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS2),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS3),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS4),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS5),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS6),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS7),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_RDY_INT),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D15),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D14),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D13),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D12),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D11),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D10),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D9),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D8),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D7),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D6),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D5),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D4),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D3),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D2),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D1),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D0),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D8),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D9),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D10),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D11),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D12),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D13),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D14),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D15),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D16),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D17),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D18),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D19),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_VSYNC),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_HSYNC),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D12),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D13),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D14),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D15),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D16),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D17),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D18),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D19),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_VSYNC),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_HSYNC),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_PIXCLK),
IMX_PINCTRL_PIN(MX51_PAD_I2C1_CLK),
IMX_PINCTRL_PIN(MX51_PAD_I2C1_DAT),
IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_TXD),
IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_RXD),
IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_CK),
IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_FS),
IMX_PINCTRL_PIN(MX51_PAD_CSPI1_MOSI),
IMX_PINCTRL_PIN(MX51_PAD_CSPI1_MISO),
IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SS0),
IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SS1),
IMX_PINCTRL_PIN(MX51_PAD_CSPI1_RDY),
IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SCLK),
IMX_PINCTRL_PIN(MX51_PAD_UART1_RXD),
IMX_PINCTRL_PIN(MX51_PAD_UART1_TXD),
IMX_PINCTRL_PIN(MX51_PAD_UART1_RTS),
IMX_PINCTRL_PIN(MX51_PAD_UART1_CTS),
IMX_PINCTRL_PIN(MX51_PAD_UART2_RXD),
IMX_PINCTRL_PIN(MX51_PAD_UART2_TXD),
IMX_PINCTRL_PIN(MX51_PAD_UART3_RXD),
IMX_PINCTRL_PIN(MX51_PAD_UART3_TXD),
IMX_PINCTRL_PIN(MX51_PAD_OWIRE_LINE),
IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW3),
IMX_PINCTRL_PIN(MX51_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX51_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX51_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX51_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX51_PAD_KEY_COL4),
IMX_PINCTRL_PIN(MX51_PAD_KEY_COL5),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_CLK),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DIR),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_STP),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_NXT),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA0),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA1),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA2),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA3),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA4),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA5),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA6),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA7),
IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN11),
IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN12),
IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN13),
IMX_PINCTRL_PIN(MX51_PAD_DI1_D0_CS),
IMX_PINCTRL_PIN(MX51_PAD_DI1_D1_CS),
IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_DIN),
IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_DIO),
IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_CLK),
IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_RS),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT0),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT1),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT2),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT3),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT4),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT5),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT6),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT7),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT8),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT9),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT10),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT11),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT12),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT13),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT14),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT15),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT16),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT17),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT18),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT19),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT20),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT21),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT22),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT23),
IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN3),
IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN2),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX51_PAD_DI_GP2),
IMX_PINCTRL_PIN(MX51_PAD_DI_GP3),
IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN4),
IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN2),
IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN3),
IMX_PINCTRL_PIN(MX51_PAD_DI2_DISP_CLK),
IMX_PINCTRL_PIN(MX51_PAD_DI_GP4),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT0),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT1),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT2),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT3),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT4),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT5),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT6),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT7),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT8),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT9),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT10),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT11),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT12),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT13),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT14),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT15),
IMX_PINCTRL_PIN(MX51_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX51_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA0),
IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA1),
IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA2),
IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA3),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_0),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_1),
IMX_PINCTRL_PIN(MX51_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX51_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA0),
IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA1),
IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA2),
IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA3),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_2),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_3),
IMX_PINCTRL_PIN(MX51_PAD_PMIC_INT_REQ),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_4),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_5),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_6),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_7),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_8),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_9),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE9),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE10),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE11),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE12),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE13),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE14),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE15),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE16),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE17),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE18),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE19),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE20),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE21),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE22),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE23),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE24),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE25),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE26),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE27),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE28),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE29),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE30),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE31),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE32),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE33),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE34),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE35),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE36),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE37),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE38),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE39),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE40),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE41),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE42),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE43),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE44),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE45),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE46),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE47),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE48),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE49),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE50),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE51),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE52),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE53),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE54),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE55),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE56),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE57),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE58),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE59),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE60),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE61),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE62),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE63),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE64),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE65),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE66),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE67),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE68),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE69),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE70),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE71),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE72),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE73),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE74),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE75),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE76),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE77),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE78),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE79),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE80),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE81),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE82),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE83),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE84),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE85),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE86),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE87),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE88),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE89),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE90),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE91),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE92),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE93),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE94),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE95),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE96),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE97),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE98),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE99),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE100),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE101),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE102),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE103),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE104),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE105),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE106),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE107),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE108),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE109),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE110),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE111),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE112),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE113),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE114),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE115),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE116),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE117),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE118),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE119),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE120),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE121),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_PIXCLK),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK),
};
static struct imx_pinctrl_soc_info imx51_pinctrl_info = {
.pins = imx51_pinctrl_pads,
.npins = ARRAY_SIZE(imx51_pinctrl_pads),
};
static const struct of_device_id imx51_pinctrl_of_match[] = {
{ .compatible = "fsl,imx51-iomuxc", },
{ /* sentinel */ }
};
static int imx51_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx51_pinctrl_info);
}
static struct platform_driver imx51_pinctrl_driver = {
.driver = {
.name = "imx51-pinctrl",
.owner = THIS_MODULE,
.of_match_table = imx51_pinctrl_of_match,
},
.probe = imx51_pinctrl_probe,
.remove = imx_pinctrl_remove,
};
static int __init imx51_pinctrl_init(void)
{
return platform_driver_register(&imx51_pinctrl_driver);
}
arch_initcall(imx51_pinctrl_init);
static void __exit imx51_pinctrl_exit(void)
{
platform_driver_unregister(&imx51_pinctrl_driver);
}
module_exit(imx51_pinctrl_exit);
MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
MODULE_DESCRIPTION("Freescale IMX51 pinctrl driver");
MODULE_LICENSE("GPL v2");

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drivers/pinctrl/freescale/pinctrl-imx53.c Normal file
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/*
* imx53 pinctrl driver based on imx pinmux core
*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro, Inc.
*
* Author: Dong Aisheng <dong.aisheng@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx53_pads {
MX53_PAD_RESERVE0 = 0,
MX53_PAD_RESERVE1 = 1,
MX53_PAD_RESERVE2 = 2,
MX53_PAD_RESERVE3 = 3,
MX53_PAD_RESERVE4 = 4,
MX53_PAD_RESERVE5 = 5,
MX53_PAD_RESERVE6 = 6,
MX53_PAD_RESERVE7 = 7,
MX53_PAD_GPIO_19 = 8,
MX53_PAD_KEY_COL0 = 9,
MX53_PAD_KEY_ROW0 = 10,
MX53_PAD_KEY_COL1 = 11,
MX53_PAD_KEY_ROW1 = 12,
MX53_PAD_KEY_COL2 = 13,
MX53_PAD_KEY_ROW2 = 14,
MX53_PAD_KEY_COL3 = 15,
MX53_PAD_KEY_ROW3 = 16,
MX53_PAD_KEY_COL4 = 17,
MX53_PAD_KEY_ROW4 = 18,
MX53_PAD_DI0_DISP_CLK = 19,
MX53_PAD_DI0_PIN15 = 20,
MX53_PAD_DI0_PIN2 = 21,
MX53_PAD_DI0_PIN3 = 22,
MX53_PAD_DI0_PIN4 = 23,
MX53_PAD_DISP0_DAT0 = 24,
MX53_PAD_DISP0_DAT1 = 25,
MX53_PAD_DISP0_DAT2 = 26,
MX53_PAD_DISP0_DAT3 = 27,
MX53_PAD_DISP0_DAT4 = 28,
MX53_PAD_DISP0_DAT5 = 29,
MX53_PAD_DISP0_DAT6 = 30,
MX53_PAD_DISP0_DAT7 = 31,
MX53_PAD_DISP0_DAT8 = 32,
MX53_PAD_DISP0_DAT9 = 33,
MX53_PAD_DISP0_DAT10 = 34,
MX53_PAD_DISP0_DAT11 = 35,
MX53_PAD_DISP0_DAT12 = 36,
MX53_PAD_DISP0_DAT13 = 37,
MX53_PAD_DISP0_DAT14 = 38,
MX53_PAD_DISP0_DAT15 = 39,
MX53_PAD_DISP0_DAT16 = 40,
MX53_PAD_DISP0_DAT17 = 41,
MX53_PAD_DISP0_DAT18 = 42,
MX53_PAD_DISP0_DAT19 = 43,
MX53_PAD_DISP0_DAT20 = 44,
MX53_PAD_DISP0_DAT21 = 45,
MX53_PAD_DISP0_DAT22 = 46,
MX53_PAD_DISP0_DAT23 = 47,
MX53_PAD_CSI0_PIXCLK = 48,
MX53_PAD_CSI0_MCLK = 49,
MX53_PAD_CSI0_DATA_EN = 50,
MX53_PAD_CSI0_VSYNC = 51,
MX53_PAD_CSI0_DAT4 = 52,
MX53_PAD_CSI0_DAT5 = 53,
MX53_PAD_CSI0_DAT6 = 54,
MX53_PAD_CSI0_DAT7 = 55,
MX53_PAD_CSI0_DAT8 = 56,
MX53_PAD_CSI0_DAT9 = 57,
MX53_PAD_CSI0_DAT10 = 58,
MX53_PAD_CSI0_DAT11 = 59,
MX53_PAD_CSI0_DAT12 = 60,
MX53_PAD_CSI0_DAT13 = 61,
MX53_PAD_CSI0_DAT14 = 62,
MX53_PAD_CSI0_DAT15 = 63,
MX53_PAD_CSI0_DAT16 = 64,
MX53_PAD_CSI0_DAT17 = 65,
MX53_PAD_CSI0_DAT18 = 66,
MX53_PAD_CSI0_DAT19 = 67,
MX53_PAD_EIM_A25 = 68,
MX53_PAD_EIM_EB2 = 69,
MX53_PAD_EIM_D16 = 70,
MX53_PAD_EIM_D17 = 71,
MX53_PAD_EIM_D18 = 72,
MX53_PAD_EIM_D19 = 73,
MX53_PAD_EIM_D20 = 74,
MX53_PAD_EIM_D21 = 75,
MX53_PAD_EIM_D22 = 76,
MX53_PAD_EIM_D23 = 77,
MX53_PAD_EIM_EB3 = 78,
MX53_PAD_EIM_D24 = 79,
MX53_PAD_EIM_D25 = 80,
MX53_PAD_EIM_D26 = 81,
MX53_PAD_EIM_D27 = 82,
MX53_PAD_EIM_D28 = 83,
MX53_PAD_EIM_D29 = 84,
MX53_PAD_EIM_D30 = 85,
MX53_PAD_EIM_D31 = 86,
MX53_PAD_EIM_A24 = 87,
MX53_PAD_EIM_A23 = 88,
MX53_PAD_EIM_A22 = 89,
MX53_PAD_EIM_A21 = 90,
MX53_PAD_EIM_A20 = 91,
MX53_PAD_EIM_A19 = 92,
MX53_PAD_EIM_A18 = 93,
MX53_PAD_EIM_A17 = 94,
MX53_PAD_EIM_A16 = 95,
MX53_PAD_EIM_CS0 = 96,
MX53_PAD_EIM_CS1 = 97,
MX53_PAD_EIM_OE = 98,
MX53_PAD_EIM_RW = 99,
MX53_PAD_EIM_LBA = 100,
MX53_PAD_EIM_EB0 = 101,
MX53_PAD_EIM_EB1 = 102,
MX53_PAD_EIM_DA0 = 103,
MX53_PAD_EIM_DA1 = 104,
MX53_PAD_EIM_DA2 = 105,
MX53_PAD_EIM_DA3 = 106,
MX53_PAD_EIM_DA4 = 107,
MX53_PAD_EIM_DA5 = 108,
MX53_PAD_EIM_DA6 = 109,
MX53_PAD_EIM_DA7 = 110,
MX53_PAD_EIM_DA8 = 111,
MX53_PAD_EIM_DA9 = 112,
MX53_PAD_EIM_DA10 = 113,
MX53_PAD_EIM_DA11 = 114,
MX53_PAD_EIM_DA12 = 115,
MX53_PAD_EIM_DA13 = 116,
MX53_PAD_EIM_DA14 = 117,
MX53_PAD_EIM_DA15 = 118,
MX53_PAD_NANDF_WE_B = 119,
MX53_PAD_NANDF_RE_B = 120,
MX53_PAD_EIM_WAIT = 121,
MX53_PAD_RESERVE8 = 122,
MX53_PAD_LVDS1_TX3_P = 123,
MX53_PAD_LVDS1_TX2_P = 124,
MX53_PAD_LVDS1_CLK_P = 125,
MX53_PAD_LVDS1_TX1_P = 126,
MX53_PAD_LVDS1_TX0_P = 127,
MX53_PAD_LVDS0_TX3_P = 128,
MX53_PAD_LVDS0_CLK_P = 129,
MX53_PAD_LVDS0_TX2_P = 130,
MX53_PAD_LVDS0_TX1_P = 131,
MX53_PAD_LVDS0_TX0_P = 132,
MX53_PAD_GPIO_10 = 133,
MX53_PAD_GPIO_11 = 134,
MX53_PAD_GPIO_12 = 135,
MX53_PAD_GPIO_13 = 136,
MX53_PAD_GPIO_14 = 137,
MX53_PAD_NANDF_CLE = 138,
MX53_PAD_NANDF_ALE = 139,
MX53_PAD_NANDF_WP_B = 140,
MX53_PAD_NANDF_RB0 = 141,
MX53_PAD_NANDF_CS0 = 142,
MX53_PAD_NANDF_CS1 = 143,
MX53_PAD_NANDF_CS2 = 144,
MX53_PAD_NANDF_CS3 = 145,
MX53_PAD_FEC_MDIO = 146,
MX53_PAD_FEC_REF_CLK = 147,
MX53_PAD_FEC_RX_ER = 148,
MX53_PAD_FEC_CRS_DV = 149,
MX53_PAD_FEC_RXD1 = 150,
MX53_PAD_FEC_RXD0 = 151,
MX53_PAD_FEC_TX_EN = 152,
MX53_PAD_FEC_TXD1 = 153,
MX53_PAD_FEC_TXD0 = 154,
MX53_PAD_FEC_MDC = 155,
MX53_PAD_PATA_DIOW = 156,
MX53_PAD_PATA_DMACK = 157,
MX53_PAD_PATA_DMARQ = 158,
MX53_PAD_PATA_BUFFER_EN = 159,
MX53_PAD_PATA_INTRQ = 160,
MX53_PAD_PATA_DIOR = 161,
MX53_PAD_PATA_RESET_B = 162,
MX53_PAD_PATA_IORDY = 163,
MX53_PAD_PATA_DA_0 = 164,
MX53_PAD_PATA_DA_1 = 165,
MX53_PAD_PATA_DA_2 = 166,
MX53_PAD_PATA_CS_0 = 167,
MX53_PAD_PATA_CS_1 = 168,
MX53_PAD_PATA_DATA0 = 169,
MX53_PAD_PATA_DATA1 = 170,
MX53_PAD_PATA_DATA2 = 171,
MX53_PAD_PATA_DATA3 = 172,
MX53_PAD_PATA_DATA4 = 173,
MX53_PAD_PATA_DATA5 = 174,
MX53_PAD_PATA_DATA6 = 175,
MX53_PAD_PATA_DATA7 = 176,
MX53_PAD_PATA_DATA8 = 177,
MX53_PAD_PATA_DATA9 = 178,
MX53_PAD_PATA_DATA10 = 179,
MX53_PAD_PATA_DATA11 = 180,
MX53_PAD_PATA_DATA12 = 181,
MX53_PAD_PATA_DATA13 = 182,
MX53_PAD_PATA_DATA14 = 183,
MX53_PAD_PATA_DATA15 = 184,
MX53_PAD_SD1_DATA0 = 185,
MX53_PAD_SD1_DATA1 = 186,
MX53_PAD_SD1_CMD = 187,
MX53_PAD_SD1_DATA2 = 188,
MX53_PAD_SD1_CLK = 189,
MX53_PAD_SD1_DATA3 = 190,
MX53_PAD_SD2_CLK = 191,
MX53_PAD_SD2_CMD = 192,
MX53_PAD_SD2_DATA3 = 193,
MX53_PAD_SD2_DATA2 = 194,
MX53_PAD_SD2_DATA1 = 195,
MX53_PAD_SD2_DATA0 = 196,
MX53_PAD_GPIO_0 = 197,
MX53_PAD_GPIO_1 = 198,
MX53_PAD_GPIO_9 = 199,
MX53_PAD_GPIO_3 = 200,
MX53_PAD_GPIO_6 = 201,
MX53_PAD_GPIO_2 = 202,
MX53_PAD_GPIO_4 = 203,
MX53_PAD_GPIO_5 = 204,
MX53_PAD_GPIO_7 = 205,
MX53_PAD_GPIO_8 = 206,
MX53_PAD_GPIO_16 = 207,
MX53_PAD_GPIO_17 = 208,
MX53_PAD_GPIO_18 = 209,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX53_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_19),
IMX_PINCTRL_PIN(MX53_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX53_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX53_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX53_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW3),
IMX_PINCTRL_PIN(MX53_PAD_KEY_COL4),
IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW4),
IMX_PINCTRL_PIN(MX53_PAD_DI0_DISP_CLK),
IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN15),
IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN2),
IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN3),
IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN4),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT0),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT1),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT2),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT3),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT4),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT5),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT6),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT7),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT8),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT9),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT10),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT11),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT12),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT13),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT14),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT15),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT16),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT17),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT18),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT19),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT20),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT21),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT22),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT23),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_PIXCLK),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_MCLK),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DATA_EN),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_VSYNC),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT4),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT5),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT6),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT7),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT8),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT9),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT10),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT11),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT12),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT13),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT14),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT15),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT16),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT17),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT18),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT19),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A25),
IMX_PINCTRL_PIN(MX53_PAD_EIM_EB2),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D16),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D17),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D18),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D19),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D20),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D21),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D22),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D23),
IMX_PINCTRL_PIN(MX53_PAD_EIM_EB3),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D24),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D25),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D26),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D27),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D28),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D29),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D30),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D31),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A24),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A23),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A22),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A21),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A20),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A19),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A18),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A17),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A16),
IMX_PINCTRL_PIN(MX53_PAD_EIM_CS0),
IMX_PINCTRL_PIN(MX53_PAD_EIM_CS1),
IMX_PINCTRL_PIN(MX53_PAD_EIM_OE),
IMX_PINCTRL_PIN(MX53_PAD_EIM_RW),
IMX_PINCTRL_PIN(MX53_PAD_EIM_LBA),
IMX_PINCTRL_PIN(MX53_PAD_EIM_EB0),
IMX_PINCTRL_PIN(MX53_PAD_EIM_EB1),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA0),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA1),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA2),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA3),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA4),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA5),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA6),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA7),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA8),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA9),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA10),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA11),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA12),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA13),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA14),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA15),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_WE_B),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_RE_B),
IMX_PINCTRL_PIN(MX53_PAD_EIM_WAIT),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX3_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX2_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS1_CLK_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX1_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX0_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX3_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS0_CLK_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX2_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX1_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX0_P),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_10),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_11),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_12),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_13),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_14),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_CLE),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_ALE),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_WP_B),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_RB0),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS0),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS1),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS2),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS3),
IMX_PINCTRL_PIN(MX53_PAD_FEC_MDIO),
IMX_PINCTRL_PIN(MX53_PAD_FEC_REF_CLK),
IMX_PINCTRL_PIN(MX53_PAD_FEC_RX_ER),
IMX_PINCTRL_PIN(MX53_PAD_FEC_CRS_DV),
IMX_PINCTRL_PIN(MX53_PAD_FEC_RXD1),
IMX_PINCTRL_PIN(MX53_PAD_FEC_RXD0),
IMX_PINCTRL_PIN(MX53_PAD_FEC_TX_EN),
IMX_PINCTRL_PIN(MX53_PAD_FEC_TXD1),
IMX_PINCTRL_PIN(MX53_PAD_FEC_TXD0),
IMX_PINCTRL_PIN(MX53_PAD_FEC_MDC),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DIOW),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DMACK),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DMARQ),
IMX_PINCTRL_PIN(MX53_PAD_PATA_BUFFER_EN),
IMX_PINCTRL_PIN(MX53_PAD_PATA_INTRQ),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DIOR),
IMX_PINCTRL_PIN(MX53_PAD_PATA_RESET_B),
IMX_PINCTRL_PIN(MX53_PAD_PATA_IORDY),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_0),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_1),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_2),
IMX_PINCTRL_PIN(MX53_PAD_PATA_CS_0),
IMX_PINCTRL_PIN(MX53_PAD_PATA_CS_1),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA0),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA1),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA2),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA3),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA4),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA5),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA6),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA7),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA8),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA9),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA10),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA11),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA12),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA13),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA14),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA15),
IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA0),
IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA1),
IMX_PINCTRL_PIN(MX53_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA2),
IMX_PINCTRL_PIN(MX53_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA3),
IMX_PINCTRL_PIN(MX53_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX53_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA3),
IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA2),
IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA1),
IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA0),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_0),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_1),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_9),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_3),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_6),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_2),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_4),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_5),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_7),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_8),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_16),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_17),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_18),
};
static struct imx_pinctrl_soc_info imx53_pinctrl_info = {
.pins = imx53_pinctrl_pads,
.npins = ARRAY_SIZE(imx53_pinctrl_pads),
};
static const struct of_device_id imx53_pinctrl_of_match[] = {
{ .compatible = "fsl,imx53-iomuxc", },
{ /* sentinel */ }
};
static int imx53_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx53_pinctrl_info);
}
static struct platform_driver imx53_pinctrl_driver = {
.driver = {
.name = "imx53-pinctrl",
.owner = THIS_MODULE,
.of_match_table = imx53_pinctrl_of_match,
},
.probe = imx53_pinctrl_probe,
.remove = imx_pinctrl_remove,
};
static int __init imx53_pinctrl_init(void)
{
return platform_driver_register(&imx53_pinctrl_driver);
}
arch_initcall(imx53_pinctrl_init);
static void __exit imx53_pinctrl_exit(void)
{
platform_driver_unregister(&imx53_pinctrl_driver);
}
module_exit(imx53_pinctrl_exit);
MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
MODULE_DESCRIPTION("Freescale IMX53 pinctrl driver");
MODULE_LICENSE("GPL v2");

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drivers/pinctrl/freescale/pinctrl-imx6dl.c Normal file
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/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx6dl_pads {
MX6DL_PAD_RESERVE0 = 0,
MX6DL_PAD_RESERVE1 = 1,
MX6DL_PAD_RESERVE2 = 2,
MX6DL_PAD_RESERVE3 = 3,
MX6DL_PAD_RESERVE4 = 4,
MX6DL_PAD_RESERVE5 = 5,
MX6DL_PAD_RESERVE6 = 6,
MX6DL_PAD_RESERVE7 = 7,
MX6DL_PAD_RESERVE8 = 8,
MX6DL_PAD_RESERVE9 = 9,
MX6DL_PAD_RESERVE10 = 10,
MX6DL_PAD_RESERVE11 = 11,
MX6DL_PAD_RESERVE12 = 12,
MX6DL_PAD_RESERVE13 = 13,
MX6DL_PAD_RESERVE14 = 14,
MX6DL_PAD_RESERVE15 = 15,
MX6DL_PAD_RESERVE16 = 16,
MX6DL_PAD_RESERVE17 = 17,
MX6DL_PAD_RESERVE18 = 18,
MX6DL_PAD_CSI0_DAT10 = 19,
MX6DL_PAD_CSI0_DAT11 = 20,
MX6DL_PAD_CSI0_DAT12 = 21,
MX6DL_PAD_CSI0_DAT13 = 22,
MX6DL_PAD_CSI0_DAT14 = 23,
MX6DL_PAD_CSI0_DAT15 = 24,
MX6DL_PAD_CSI0_DAT16 = 25,
MX6DL_PAD_CSI0_DAT17 = 26,
MX6DL_PAD_CSI0_DAT18 = 27,
MX6DL_PAD_CSI0_DAT19 = 28,
MX6DL_PAD_CSI0_DAT4 = 29,
MX6DL_PAD_CSI0_DAT5 = 30,
MX6DL_PAD_CSI0_DAT6 = 31,
MX6DL_PAD_CSI0_DAT7 = 32,
MX6DL_PAD_CSI0_DAT8 = 33,
MX6DL_PAD_CSI0_DAT9 = 34,
MX6DL_PAD_CSI0_DATA_EN = 35,
MX6DL_PAD_CSI0_MCLK = 36,
MX6DL_PAD_CSI0_PIXCLK = 37,
MX6DL_PAD_CSI0_VSYNC = 38,
MX6DL_PAD_DI0_DISP_CLK = 39,
MX6DL_PAD_DI0_PIN15 = 40,
MX6DL_PAD_DI0_PIN2 = 41,
MX6DL_PAD_DI0_PIN3 = 42,
MX6DL_PAD_DI0_PIN4 = 43,
MX6DL_PAD_DISP0_DAT0 = 44,
MX6DL_PAD_DISP0_DAT1 = 45,
MX6DL_PAD_DISP0_DAT10 = 46,
MX6DL_PAD_DISP0_DAT11 = 47,
MX6DL_PAD_DISP0_DAT12 = 48,
MX6DL_PAD_DISP0_DAT13 = 49,
MX6DL_PAD_DISP0_DAT14 = 50,
MX6DL_PAD_DISP0_DAT15 = 51,
MX6DL_PAD_DISP0_DAT16 = 52,
MX6DL_PAD_DISP0_DAT17 = 53,
MX6DL_PAD_DISP0_DAT18 = 54,
MX6DL_PAD_DISP0_DAT19 = 55,
MX6DL_PAD_DISP0_DAT2 = 56,
MX6DL_PAD_DISP0_DAT20 = 57,
MX6DL_PAD_DISP0_DAT21 = 58,
MX6DL_PAD_DISP0_DAT22 = 59,
MX6DL_PAD_DISP0_DAT23 = 60,
MX6DL_PAD_DISP0_DAT3 = 61,
MX6DL_PAD_DISP0_DAT4 = 62,
MX6DL_PAD_DISP0_DAT5 = 63,
MX6DL_PAD_DISP0_DAT6 = 64,
MX6DL_PAD_DISP0_DAT7 = 65,
MX6DL_PAD_DISP0_DAT8 = 66,
MX6DL_PAD_DISP0_DAT9 = 67,
MX6DL_PAD_EIM_A16 = 68,
MX6DL_PAD_EIM_A17 = 69,
MX6DL_PAD_EIM_A18 = 70,
MX6DL_PAD_EIM_A19 = 71,
MX6DL_PAD_EIM_A20 = 72,
MX6DL_PAD_EIM_A21 = 73,
MX6DL_PAD_EIM_A22 = 74,
MX6DL_PAD_EIM_A23 = 75,
MX6DL_PAD_EIM_A24 = 76,
MX6DL_PAD_EIM_A25 = 77,
MX6DL_PAD_EIM_BCLK = 78,
MX6DL_PAD_EIM_CS0 = 79,
MX6DL_PAD_EIM_CS1 = 80,
MX6DL_PAD_EIM_D16 = 81,
MX6DL_PAD_EIM_D17 = 82,
MX6DL_PAD_EIM_D18 = 83,
MX6DL_PAD_EIM_D19 = 84,
MX6DL_PAD_EIM_D20 = 85,
MX6DL_PAD_EIM_D21 = 86,
MX6DL_PAD_EIM_D22 = 87,
MX6DL_PAD_EIM_D23 = 88,
MX6DL_PAD_EIM_D24 = 89,
MX6DL_PAD_EIM_D25 = 90,
MX6DL_PAD_EIM_D26 = 91,
MX6DL_PAD_EIM_D27 = 92,
MX6DL_PAD_EIM_D28 = 93,
MX6DL_PAD_EIM_D29 = 94,
MX6DL_PAD_EIM_D30 = 95,
MX6DL_PAD_EIM_D31 = 96,
MX6DL_PAD_EIM_DA0 = 97,
MX6DL_PAD_EIM_DA1 = 98,
MX6DL_PAD_EIM_DA10 = 99,
MX6DL_PAD_EIM_DA11 = 100,
MX6DL_PAD_EIM_DA12 = 101,
MX6DL_PAD_EIM_DA13 = 102,
MX6DL_PAD_EIM_DA14 = 103,
MX6DL_PAD_EIM_DA15 = 104,
MX6DL_PAD_EIM_DA2 = 105,
MX6DL_PAD_EIM_DA3 = 106,
MX6DL_PAD_EIM_DA4 = 107,
MX6DL_PAD_EIM_DA5 = 108,
MX6DL_PAD_EIM_DA6 = 109,
MX6DL_PAD_EIM_DA7 = 110,
MX6DL_PAD_EIM_DA8 = 111,
MX6DL_PAD_EIM_DA9 = 112,
MX6DL_PAD_EIM_EB0 = 113,
MX6DL_PAD_EIM_EB1 = 114,
MX6DL_PAD_EIM_EB2 = 115,
MX6DL_PAD_EIM_EB3 = 116,
MX6DL_PAD_EIM_LBA = 117,
MX6DL_PAD_EIM_OE = 118,
MX6DL_PAD_EIM_RW = 119,
MX6DL_PAD_EIM_WAIT = 120,
MX6DL_PAD_ENET_CRS_DV = 121,
MX6DL_PAD_ENET_MDC = 122,
MX6DL_PAD_ENET_MDIO = 123,
MX6DL_PAD_ENET_REF_CLK = 124,
MX6DL_PAD_ENET_RX_ER = 125,
MX6DL_PAD_ENET_RXD0 = 126,
MX6DL_PAD_ENET_RXD1 = 127,
MX6DL_PAD_ENET_TX_EN = 128,
MX6DL_PAD_ENET_TXD0 = 129,
MX6DL_PAD_ENET_TXD1 = 130,
MX6DL_PAD_GPIO_0 = 131,
MX6DL_PAD_GPIO_1 = 132,
MX6DL_PAD_GPIO_16 = 133,
MX6DL_PAD_GPIO_17 = 134,
MX6DL_PAD_GPIO_18 = 135,
MX6DL_PAD_GPIO_19 = 136,
MX6DL_PAD_GPIO_2 = 137,
MX6DL_PAD_GPIO_3 = 138,
MX6DL_PAD_GPIO_4 = 139,
MX6DL_PAD_GPIO_5 = 140,
MX6DL_PAD_GPIO_6 = 141,
MX6DL_PAD_GPIO_7 = 142,
MX6DL_PAD_GPIO_8 = 143,
MX6DL_PAD_GPIO_9 = 144,
MX6DL_PAD_KEY_COL0 = 145,
MX6DL_PAD_KEY_COL1 = 146,
MX6DL_PAD_KEY_COL2 = 147,
MX6DL_PAD_KEY_COL3 = 148,
MX6DL_PAD_KEY_COL4 = 149,
MX6DL_PAD_KEY_ROW0 = 150,
MX6DL_PAD_KEY_ROW1 = 151,
MX6DL_PAD_KEY_ROW2 = 152,
MX6DL_PAD_KEY_ROW3 = 153,
MX6DL_PAD_KEY_ROW4 = 154,
MX6DL_PAD_NANDF_ALE = 155,
MX6DL_PAD_NANDF_CLE = 156,
MX6DL_PAD_NANDF_CS0 = 157,
MX6DL_PAD_NANDF_CS1 = 158,
MX6DL_PAD_NANDF_CS2 = 159,
MX6DL_PAD_NANDF_CS3 = 160,
MX6DL_PAD_NANDF_D0 = 161,
MX6DL_PAD_NANDF_D1 = 162,
MX6DL_PAD_NANDF_D2 = 163,
MX6DL_PAD_NANDF_D3 = 164,
MX6DL_PAD_NANDF_D4 = 165,
MX6DL_PAD_NANDF_D5 = 166,
MX6DL_PAD_NANDF_D6 = 167,
MX6DL_PAD_NANDF_D7 = 168,
MX6DL_PAD_NANDF_RB0 = 169,
MX6DL_PAD_NANDF_WP_B = 170,
MX6DL_PAD_RGMII_RD0 = 171,
MX6DL_PAD_RGMII_RD1 = 172,
MX6DL_PAD_RGMII_RD2 = 173,
MX6DL_PAD_RGMII_RD3 = 174,
MX6DL_PAD_RGMII_RX_CTL = 175,
MX6DL_PAD_RGMII_RXC = 176,
MX6DL_PAD_RGMII_TD0 = 177,
MX6DL_PAD_RGMII_TD1 = 178,
MX6DL_PAD_RGMII_TD2 = 179,
MX6DL_PAD_RGMII_TD3 = 180,
MX6DL_PAD_RGMII_TX_CTL = 181,
MX6DL_PAD_RGMII_TXC = 182,
MX6DL_PAD_SD1_CLK = 183,
MX6DL_PAD_SD1_CMD = 184,
MX6DL_PAD_SD1_DAT0 = 185,
MX6DL_PAD_SD1_DAT1 = 186,
MX6DL_PAD_SD1_DAT2 = 187,
MX6DL_PAD_SD1_DAT3 = 188,
MX6DL_PAD_SD2_CLK = 189,
MX6DL_PAD_SD2_CMD = 190,
MX6DL_PAD_SD2_DAT0 = 191,
MX6DL_PAD_SD2_DAT1 = 192,
MX6DL_PAD_SD2_DAT2 = 193,
MX6DL_PAD_SD2_DAT3 = 194,
MX6DL_PAD_SD3_CLK = 195,
MX6DL_PAD_SD3_CMD = 196,
MX6DL_PAD_SD3_DAT0 = 197,
MX6DL_PAD_SD3_DAT1 = 198,
MX6DL_PAD_SD3_DAT2 = 199,
MX6DL_PAD_SD3_DAT3 = 200,
MX6DL_PAD_SD3_DAT4 = 201,
MX6DL_PAD_SD3_DAT5 = 202,
MX6DL_PAD_SD3_DAT6 = 203,
MX6DL_PAD_SD3_DAT7 = 204,
MX6DL_PAD_SD3_RST = 205,
MX6DL_PAD_SD4_CLK = 206,
MX6DL_PAD_SD4_CMD = 207,
MX6DL_PAD_SD4_DAT0 = 208,
MX6DL_PAD_SD4_DAT1 = 209,
MX6DL_PAD_SD4_DAT2 = 210,
MX6DL_PAD_SD4_DAT3 = 211,
MX6DL_PAD_SD4_DAT4 = 212,
MX6DL_PAD_SD4_DAT5 = 213,
MX6DL_PAD_SD4_DAT6 = 214,
MX6DL_PAD_SD4_DAT7 = 215,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx6dl_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE9),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE10),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE11),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE12),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE13),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE14),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE15),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE16),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE17),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE18),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT10),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT11),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT12),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT13),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT14),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT15),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT16),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT17),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT18),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT19),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT4),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT5),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT6),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT7),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT8),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT9),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DATA_EN),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_MCLK),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_PIXCLK),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_VSYNC),
IMX_PINCTRL_PIN(MX6DL_PAD_DI0_DISP_CLK),
IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN15),
IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN2),
IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN3),
IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN4),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT0),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT1),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT10),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT11),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT12),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT13),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT14),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT15),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT16),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT17),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT18),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT19),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT2),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT20),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT21),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT22),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT23),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT3),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT4),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT5),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT6),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT7),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT8),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT9),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A16),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A17),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A18),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A19),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A20),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A21),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A22),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A23),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A24),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A25),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_BCLK),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_CS0),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_CS1),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D16),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D17),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D18),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D19),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D20),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D21),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D22),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D23),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D24),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D25),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D26),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D27),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D28),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D29),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D30),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D31),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA0),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA1),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA10),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA11),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA12),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA13),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA14),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA15),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA2),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA3),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA4),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA5),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA6),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA7),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA8),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA9),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB0),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB1),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB2),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB3),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_LBA),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_OE),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_RW),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_WAIT),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_CRS_DV),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_MDC),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_MDIO),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_REF_CLK),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RX_ER),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RXD0),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RXD1),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TX_EN),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TXD0),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TXD1),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_0),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_1),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_16),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_17),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_18),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_19),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_2),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_3),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_4),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_5),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_6),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_7),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_8),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_9),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL4),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW3),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW4),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_ALE),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CLE),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS0),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS1),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS2),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS3),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D0),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D1),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D2),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D3),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D4),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D5),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D6),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D7),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_RB0),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_WP_B),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD0),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD1),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD2),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD3),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RX_CTL),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RXC),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD0),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD1),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD2),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD3),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TX_CTL),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TXC),
IMX_PINCTRL_PIN(MX6DL_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX6DL_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT0),
IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT1),
IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT2),
IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT3),
IMX_PINCTRL_PIN(MX6DL_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX6DL_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT0),
IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT1),
IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT2),
IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT3),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_CLK),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_CMD),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT0),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT1),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT2),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT3),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT4),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT5),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT6),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT7),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_RST),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_CLK),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_CMD),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT0),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT1),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT2),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT3),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT4),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT5),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT6),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT7),
};
static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {
.pins = imx6dl_pinctrl_pads,
.npins = ARRAY_SIZE(imx6dl_pinctrl_pads),
};
static const struct of_device_id imx6dl_pinctrl_of_match[] = {
{ .compatible = "fsl,imx6dl-iomuxc", },
{ /* sentinel */ }
};
static int imx6dl_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx6dl_pinctrl_info);
}
static struct platform_driver imx6dl_pinctrl_driver = {
.driver = {
.name = "imx6dl-pinctrl",
.owner = THIS_MODULE,
.of_match_table = imx6dl_pinctrl_of_match,
},
.probe = imx6dl_pinctrl_probe,
.remove = imx_pinctrl_remove,
};
static int __init imx6dl_pinctrl_init(void)
{
return platform_driver_register(&imx6dl_pinctrl_driver);
}
arch_initcall(imx6dl_pinctrl_init);
static void __exit imx6dl_pinctrl_exit(void)
{
platform_driver_unregister(&imx6dl_pinctrl_driver);
}
module_exit(imx6dl_pinctrl_exit);
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Freescale imx6dl pinctrl driver");
MODULE_LICENSE("GPL v2");

502
drivers/pinctrl/freescale/pinctrl-imx6q.c Normal file
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/*
* imx6q pinctrl driver based on imx pinmux core
*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro, Inc.
*
* Author: Dong Aisheng <dong.aisheng@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx6q_pads {
MX6Q_PAD_RESERVE0 = 0,
MX6Q_PAD_RESERVE1 = 1,
MX6Q_PAD_RESERVE2 = 2,
MX6Q_PAD_RESERVE3 = 3,
MX6Q_PAD_RESERVE4 = 4,
MX6Q_PAD_RESERVE5 = 5,
MX6Q_PAD_RESERVE6 = 6,
MX6Q_PAD_RESERVE7 = 7,
MX6Q_PAD_RESERVE8 = 8,
MX6Q_PAD_RESERVE9 = 9,
MX6Q_PAD_RESERVE10 = 10,
MX6Q_PAD_RESERVE11 = 11,
MX6Q_PAD_RESERVE12 = 12,
MX6Q_PAD_RESERVE13 = 13,
MX6Q_PAD_RESERVE14 = 14,
MX6Q_PAD_RESERVE15 = 15,
MX6Q_PAD_RESERVE16 = 16,
MX6Q_PAD_RESERVE17 = 17,
MX6Q_PAD_RESERVE18 = 18,
MX6Q_PAD_SD2_DAT1 = 19,
MX6Q_PAD_SD2_DAT2 = 20,
MX6Q_PAD_SD2_DAT0 = 21,
MX6Q_PAD_RGMII_TXC = 22,
MX6Q_PAD_RGMII_TD0 = 23,
MX6Q_PAD_RGMII_TD1 = 24,
MX6Q_PAD_RGMII_TD2 = 25,
MX6Q_PAD_RGMII_TD3 = 26,
MX6Q_PAD_RGMII_RX_CTL = 27,
MX6Q_PAD_RGMII_RD0 = 28,
MX6Q_PAD_RGMII_TX_CTL = 29,
MX6Q_PAD_RGMII_RD1 = 30,
MX6Q_PAD_RGMII_RD2 = 31,
MX6Q_PAD_RGMII_RD3 = 32,
MX6Q_PAD_RGMII_RXC = 33,
MX6Q_PAD_EIM_A25 = 34,
MX6Q_PAD_EIM_EB2 = 35,
MX6Q_PAD_EIM_D16 = 36,
MX6Q_PAD_EIM_D17 = 37,
MX6Q_PAD_EIM_D18 = 38,
MX6Q_PAD_EIM_D19 = 39,
MX6Q_PAD_EIM_D20 = 40,
MX6Q_PAD_EIM_D21 = 41,
MX6Q_PAD_EIM_D22 = 42,
MX6Q_PAD_EIM_D23 = 43,
MX6Q_PAD_EIM_EB3 = 44,
MX6Q_PAD_EIM_D24 = 45,
MX6Q_PAD_EIM_D25 = 46,
MX6Q_PAD_EIM_D26 = 47,
MX6Q_PAD_EIM_D27 = 48,
MX6Q_PAD_EIM_D28 = 49,
MX6Q_PAD_EIM_D29 = 50,
MX6Q_PAD_EIM_D30 = 51,
MX6Q_PAD_EIM_D31 = 52,
MX6Q_PAD_EIM_A24 = 53,
MX6Q_PAD_EIM_A23 = 54,
MX6Q_PAD_EIM_A22 = 55,
MX6Q_PAD_EIM_A21 = 56,
MX6Q_PAD_EIM_A20 = 57,
MX6Q_PAD_EIM_A19 = 58,
MX6Q_PAD_EIM_A18 = 59,
MX6Q_PAD_EIM_A17 = 60,
MX6Q_PAD_EIM_A16 = 61,
MX6Q_PAD_EIM_CS0 = 62,
MX6Q_PAD_EIM_CS1 = 63,
MX6Q_PAD_EIM_OE = 64,
MX6Q_PAD_EIM_RW = 65,
MX6Q_PAD_EIM_LBA = 66,
MX6Q_PAD_EIM_EB0 = 67,
MX6Q_PAD_EIM_EB1 = 68,
MX6Q_PAD_EIM_DA0 = 69,
MX6Q_PAD_EIM_DA1 = 70,
MX6Q_PAD_EIM_DA2 = 71,
MX6Q_PAD_EIM_DA3 = 72,
MX6Q_PAD_EIM_DA4 = 73,
MX6Q_PAD_EIM_DA5 = 74,
MX6Q_PAD_EIM_DA6 = 75,
MX6Q_PAD_EIM_DA7 = 76,
MX6Q_PAD_EIM_DA8 = 77,
MX6Q_PAD_EIM_DA9 = 78,
MX6Q_PAD_EIM_DA10 = 79,
MX6Q_PAD_EIM_DA11 = 80,
MX6Q_PAD_EIM_DA12 = 81,
MX6Q_PAD_EIM_DA13 = 82,
MX6Q_PAD_EIM_DA14 = 83,
MX6Q_PAD_EIM_DA15 = 84,
MX6Q_PAD_EIM_WAIT = 85,
MX6Q_PAD_EIM_BCLK = 86,
MX6Q_PAD_DI0_DISP_CLK = 87,
MX6Q_PAD_DI0_PIN15 = 88,
MX6Q_PAD_DI0_PIN2 = 89,
MX6Q_PAD_DI0_PIN3 = 90,
MX6Q_PAD_DI0_PIN4 = 91,
MX6Q_PAD_DISP0_DAT0 = 92,
MX6Q_PAD_DISP0_DAT1 = 93,
MX6Q_PAD_DISP0_DAT2 = 94,
MX6Q_PAD_DISP0_DAT3 = 95,
MX6Q_PAD_DISP0_DAT4 = 96,
MX6Q_PAD_DISP0_DAT5 = 97,
MX6Q_PAD_DISP0_DAT6 = 98,
MX6Q_PAD_DISP0_DAT7 = 99,
MX6Q_PAD_DISP0_DAT8 = 100,
MX6Q_PAD_DISP0_DAT9 = 101,
MX6Q_PAD_DISP0_DAT10 = 102,
MX6Q_PAD_DISP0_DAT11 = 103,
MX6Q_PAD_DISP0_DAT12 = 104,
MX6Q_PAD_DISP0_DAT13 = 105,
MX6Q_PAD_DISP0_DAT14 = 106,
MX6Q_PAD_DISP0_DAT15 = 107,
MX6Q_PAD_DISP0_DAT16 = 108,
MX6Q_PAD_DISP0_DAT17 = 109,
MX6Q_PAD_DISP0_DAT18 = 110,
MX6Q_PAD_DISP0_DAT19 = 111,
MX6Q_PAD_DISP0_DAT20 = 112,
MX6Q_PAD_DISP0_DAT21 = 113,
MX6Q_PAD_DISP0_DAT22 = 114,
MX6Q_PAD_DISP0_DAT23 = 115,
MX6Q_PAD_ENET_MDIO = 116,
MX6Q_PAD_ENET_REF_CLK = 117,
MX6Q_PAD_ENET_RX_ER = 118,
MX6Q_PAD_ENET_CRS_DV = 119,
MX6Q_PAD_ENET_RXD1 = 120,
MX6Q_PAD_ENET_RXD0 = 121,
MX6Q_PAD_ENET_TX_EN = 122,
MX6Q_PAD_ENET_TXD1 = 123,
MX6Q_PAD_ENET_TXD0 = 124,
MX6Q_PAD_ENET_MDC = 125,
MX6Q_PAD_KEY_COL0 = 126,
MX6Q_PAD_KEY_ROW0 = 127,
MX6Q_PAD_KEY_COL1 = 128,
MX6Q_PAD_KEY_ROW1 = 129,
MX6Q_PAD_KEY_COL2 = 130,
MX6Q_PAD_KEY_ROW2 = 131,
MX6Q_PAD_KEY_COL3 = 132,
MX6Q_PAD_KEY_ROW3 = 133,
MX6Q_PAD_KEY_COL4 = 134,
MX6Q_PAD_KEY_ROW4 = 135,
MX6Q_PAD_GPIO_0 = 136,
MX6Q_PAD_GPIO_1 = 137,
MX6Q_PAD_GPIO_9 = 138,
MX6Q_PAD_GPIO_3 = 139,
MX6Q_PAD_GPIO_6 = 140,
MX6Q_PAD_GPIO_2 = 141,
MX6Q_PAD_GPIO_4 = 142,
MX6Q_PAD_GPIO_5 = 143,
MX6Q_PAD_GPIO_7 = 144,
MX6Q_PAD_GPIO_8 = 145,
MX6Q_PAD_GPIO_16 = 146,
MX6Q_PAD_GPIO_17 = 147,
MX6Q_PAD_GPIO_18 = 148,
MX6Q_PAD_GPIO_19 = 149,
MX6Q_PAD_CSI0_PIXCLK = 150,
MX6Q_PAD_CSI0_MCLK = 151,
MX6Q_PAD_CSI0_DATA_EN = 152,
MX6Q_PAD_CSI0_VSYNC = 153,
MX6Q_PAD_CSI0_DAT4 = 154,
MX6Q_PAD_CSI0_DAT5 = 155,
MX6Q_PAD_CSI0_DAT6 = 156,
MX6Q_PAD_CSI0_DAT7 = 157,
MX6Q_PAD_CSI0_DAT8 = 158,
MX6Q_PAD_CSI0_DAT9 = 159,
MX6Q_PAD_CSI0_DAT10 = 160,
MX6Q_PAD_CSI0_DAT11 = 161,
MX6Q_PAD_CSI0_DAT12 = 162,
MX6Q_PAD_CSI0_DAT13 = 163,
MX6Q_PAD_CSI0_DAT14 = 164,
MX6Q_PAD_CSI0_DAT15 = 165,
MX6Q_PAD_CSI0_DAT16 = 166,
MX6Q_PAD_CSI0_DAT17 = 167,
MX6Q_PAD_CSI0_DAT18 = 168,
MX6Q_PAD_CSI0_DAT19 = 169,
MX6Q_PAD_SD3_DAT7 = 170,
MX6Q_PAD_SD3_DAT6 = 171,
MX6Q_PAD_SD3_DAT5 = 172,
MX6Q_PAD_SD3_DAT4 = 173,
MX6Q_PAD_SD3_CMD = 174,
MX6Q_PAD_SD3_CLK = 175,
MX6Q_PAD_SD3_DAT0 = 176,
MX6Q_PAD_SD3_DAT1 = 177,
MX6Q_PAD_SD3_DAT2 = 178,
MX6Q_PAD_SD3_DAT3 = 179,
MX6Q_PAD_SD3_RST = 180,
MX6Q_PAD_NANDF_CLE = 181,
MX6Q_PAD_NANDF_ALE = 182,
MX6Q_PAD_NANDF_WP_B = 183,
MX6Q_PAD_NANDF_RB0 = 184,
MX6Q_PAD_NANDF_CS0 = 185,
MX6Q_PAD_NANDF_CS1 = 186,
MX6Q_PAD_NANDF_CS2 = 187,
MX6Q_PAD_NANDF_CS3 = 188,
MX6Q_PAD_SD4_CMD = 189,
MX6Q_PAD_SD4_CLK = 190,
MX6Q_PAD_NANDF_D0 = 191,
MX6Q_PAD_NANDF_D1 = 192,
MX6Q_PAD_NANDF_D2 = 193,
MX6Q_PAD_NANDF_D3 = 194,
MX6Q_PAD_NANDF_D4 = 195,
MX6Q_PAD_NANDF_D5 = 196,
MX6Q_PAD_NANDF_D6 = 197,
MX6Q_PAD_NANDF_D7 = 198,
MX6Q_PAD_SD4_DAT0 = 199,
MX6Q_PAD_SD4_DAT1 = 200,
MX6Q_PAD_SD4_DAT2 = 201,
MX6Q_PAD_SD4_DAT3 = 202,
MX6Q_PAD_SD4_DAT4 = 203,
MX6Q_PAD_SD4_DAT5 = 204,
MX6Q_PAD_SD4_DAT6 = 205,
MX6Q_PAD_SD4_DAT7 = 206,
MX6Q_PAD_SD1_DAT1 = 207,
MX6Q_PAD_SD1_DAT0 = 208,
MX6Q_PAD_SD1_DAT3 = 209,
MX6Q_PAD_SD1_CMD = 210,
MX6Q_PAD_SD1_DAT2 = 211,
MX6Q_PAD_SD1_CLK = 212,
MX6Q_PAD_SD2_CLK = 213,
MX6Q_PAD_SD2_CMD = 214,
MX6Q_PAD_SD2_DAT3 = 215,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE9),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE10),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE11),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE12),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE13),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE14),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE15),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE16),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE17),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE18),
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1),
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2),
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK),
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK),
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15),
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2),
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3),
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7),
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1),
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0),
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3),
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2),
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3),
};
static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
.pins = imx6q_pinctrl_pads,
.npins = ARRAY_SIZE(imx6q_pinctrl_pads),
};
static const struct of_device_id imx6q_pinctrl_of_match[] = {
{ .compatible = "fsl,imx6q-iomuxc", },
{ /* sentinel */ }
};
static int imx6q_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info);
}
static struct platform_driver imx6q_pinctrl_driver = {
.driver = {
.name = "imx6q-pinctrl",
.owner = THIS_MODULE,
.of_match_table = imx6q_pinctrl_of_match,
},
.probe = imx6q_pinctrl_probe,
.remove = imx_pinctrl_remove,
};
static int __init imx6q_pinctrl_init(void)
{
return platform_driver_register(&imx6q_pinctrl_driver);
}
arch_initcall(imx6q_pinctrl_init);
static void __exit imx6q_pinctrl_exit(void)
{
platform_driver_unregister(&imx6q_pinctrl_driver);
}
module_exit(imx6q_pinctrl_exit);
MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver");
MODULE_LICENSE("GPL v2");

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drivers/pinctrl/freescale/pinctrl-imx6sl.c Normal file
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/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx6sl_pads {
MX6SL_PAD_RESERVE0 = 0,
MX6SL_PAD_RESERVE1 = 1,
MX6SL_PAD_RESERVE2 = 2,
MX6SL_PAD_RESERVE3 = 3,
MX6SL_PAD_RESERVE4 = 4,
MX6SL_PAD_RESERVE5 = 5,
MX6SL_PAD_RESERVE6 = 6,
MX6SL_PAD_RESERVE7 = 7,
MX6SL_PAD_RESERVE8 = 8,
MX6SL_PAD_RESERVE9 = 9,
MX6SL_PAD_RESERVE10 = 10,
MX6SL_PAD_RESERVE11 = 11,
MX6SL_PAD_RESERVE12 = 12,
MX6SL_PAD_RESERVE13 = 13,
MX6SL_PAD_RESERVE14 = 14,
MX6SL_PAD_RESERVE15 = 15,
MX6SL_PAD_RESERVE16 = 16,
MX6SL_PAD_RESERVE17 = 17,
MX6SL_PAD_RESERVE18 = 18,
MX6SL_PAD_AUD_MCLK = 19,
MX6SL_PAD_AUD_RXC = 20,
MX6SL_PAD_AUD_RXD = 21,
MX6SL_PAD_AUD_RXFS = 22,
MX6SL_PAD_AUD_TXC = 23,
MX6SL_PAD_AUD_TXD = 24,
MX6SL_PAD_AUD_TXFS = 25,
MX6SL_PAD_ECSPI1_MISO = 26,
MX6SL_PAD_ECSPI1_MOSI = 27,
MX6SL_PAD_ECSPI1_SCLK = 28,
MX6SL_PAD_ECSPI1_SS0 = 29,
MX6SL_PAD_ECSPI2_MISO = 30,
MX6SL_PAD_ECSPI2_MOSI = 31,
MX6SL_PAD_ECSPI2_SCLK = 32,
MX6SL_PAD_ECSPI2_SS0 = 33,
MX6SL_PAD_EPDC_BDR0 = 34,
MX6SL_PAD_EPDC_BDR1 = 35,
MX6SL_PAD_EPDC_D0 = 36,
MX6SL_PAD_EPDC_D1 = 37,
MX6SL_PAD_EPDC_D10 = 38,
MX6SL_PAD_EPDC_D11 = 39,
MX6SL_PAD_EPDC_D12 = 40,
MX6SL_PAD_EPDC_D13 = 41,
MX6SL_PAD_EPDC_D14 = 42,
MX6SL_PAD_EPDC_D15 = 43,
MX6SL_PAD_EPDC_D2 = 44,
MX6SL_PAD_EPDC_D3 = 45,
MX6SL_PAD_EPDC_D4 = 46,
MX6SL_PAD_EPDC_D5 = 47,
MX6SL_PAD_EPDC_D6 = 48,
MX6SL_PAD_EPDC_D7 = 49,
MX6SL_PAD_EPDC_D8 = 50,
MX6SL_PAD_EPDC_D9 = 51,
MX6SL_PAD_EPDC_GDCLK = 52,
MX6SL_PAD_EPDC_GDOE = 53,
MX6SL_PAD_EPDC_GDRL = 54,
MX6SL_PAD_EPDC_GDSP = 55,
MX6SL_PAD_EPDC_PWRCOM = 56,
MX6SL_PAD_EPDC_PWRCTRL0 = 57,
MX6SL_PAD_EPDC_PWRCTRL1 = 58,
MX6SL_PAD_EPDC_PWRCTRL2 = 59,
MX6SL_PAD_EPDC_PWRCTRL3 = 60,
MX6SL_PAD_EPDC_PWRINT = 61,
MX6SL_PAD_EPDC_PWRSTAT = 62,
MX6SL_PAD_EPDC_PWRWAKEUP = 63,
MX6SL_PAD_EPDC_SDCE0 = 64,
MX6SL_PAD_EPDC_SDCE1 = 65,
MX6SL_PAD_EPDC_SDCE2 = 66,
MX6SL_PAD_EPDC_SDCE3 = 67,
MX6SL_PAD_EPDC_SDCLK = 68,
MX6SL_PAD_EPDC_SDLE = 69,
MX6SL_PAD_EPDC_SDOE = 70,
MX6SL_PAD_EPDC_SDSHR = 71,
MX6SL_PAD_EPDC_VCOM0 = 72,
MX6SL_PAD_EPDC_VCOM1 = 73,
MX6SL_PAD_FEC_CRS_DV = 74,
MX6SL_PAD_FEC_MDC = 75,
MX6SL_PAD_FEC_MDIO = 76,
MX6SL_PAD_FEC_REF_CLK = 77,
MX6SL_PAD_FEC_RX_ER = 78,
MX6SL_PAD_FEC_RXD0 = 79,
MX6SL_PAD_FEC_RXD1 = 80,
MX6SL_PAD_FEC_TX_CLK = 81,
MX6SL_PAD_FEC_TX_EN = 82,
MX6SL_PAD_FEC_TXD0 = 83,
MX6SL_PAD_FEC_TXD1 = 84,
MX6SL_PAD_HSIC_DAT = 85,
MX6SL_PAD_HSIC_STROBE = 86,
MX6SL_PAD_I2C1_SCL = 87,
MX6SL_PAD_I2C1_SDA = 88,
MX6SL_PAD_I2C2_SCL = 89,
MX6SL_PAD_I2C2_SDA = 90,
MX6SL_PAD_KEY_COL0 = 91,
MX6SL_PAD_KEY_COL1 = 92,
MX6SL_PAD_KEY_COL2 = 93,
MX6SL_PAD_KEY_COL3 = 94,
MX6SL_PAD_KEY_COL4 = 95,
MX6SL_PAD_KEY_COL5 = 96,
MX6SL_PAD_KEY_COL6 = 97,
MX6SL_PAD_KEY_COL7 = 98,
MX6SL_PAD_KEY_ROW0 = 99,
MX6SL_PAD_KEY_ROW1 = 100,
MX6SL_PAD_KEY_ROW2 = 101,
MX6SL_PAD_KEY_ROW3 = 102,
MX6SL_PAD_KEY_ROW4 = 103,
MX6SL_PAD_KEY_ROW5 = 104,
MX6SL_PAD_KEY_ROW6 = 105,
MX6SL_PAD_KEY_ROW7 = 106,
MX6SL_PAD_LCD_CLK = 107,
MX6SL_PAD_LCD_DAT0 = 108,
MX6SL_PAD_LCD_DAT1 = 109,
MX6SL_PAD_LCD_DAT10 = 110,
MX6SL_PAD_LCD_DAT11 = 111,
MX6SL_PAD_LCD_DAT12 = 112,
MX6SL_PAD_LCD_DAT13 = 113,
MX6SL_PAD_LCD_DAT14 = 114,
MX6SL_PAD_LCD_DAT15 = 115,
MX6SL_PAD_LCD_DAT16 = 116,
MX6SL_PAD_LCD_DAT17 = 117,
MX6SL_PAD_LCD_DAT18 = 118,
MX6SL_PAD_LCD_DAT19 = 119,
MX6SL_PAD_LCD_DAT2 = 120,
MX6SL_PAD_LCD_DAT20 = 121,
MX6SL_PAD_LCD_DAT21 = 122,
MX6SL_PAD_LCD_DAT22 = 123,
MX6SL_PAD_LCD_DAT23 = 124,
MX6SL_PAD_LCD_DAT3 = 125,
MX6SL_PAD_LCD_DAT4 = 126,
MX6SL_PAD_LCD_DAT5 = 127,
MX6SL_PAD_LCD_DAT6 = 128,
MX6SL_PAD_LCD_DAT7 = 129,
MX6SL_PAD_LCD_DAT8 = 130,
MX6SL_PAD_LCD_DAT9 = 131,
MX6SL_PAD_LCD_ENABLE = 132,
MX6SL_PAD_LCD_HSYNC = 133,
MX6SL_PAD_LCD_RESET = 134,
MX6SL_PAD_LCD_VSYNC = 135,
MX6SL_PAD_PWM1 = 136,
MX6SL_PAD_REF_CLK_24M = 137,
MX6SL_PAD_REF_CLK_32K = 138,
MX6SL_PAD_SD1_CLK = 139,
MX6SL_PAD_SD1_CMD = 140,
MX6SL_PAD_SD1_DAT0 = 141,
MX6SL_PAD_SD1_DAT1 = 142,
MX6SL_PAD_SD1_DAT2 = 143,
MX6SL_PAD_SD1_DAT3 = 144,
MX6SL_PAD_SD1_DAT4 = 145,
MX6SL_PAD_SD1_DAT5 = 146,
MX6SL_PAD_SD1_DAT6 = 147,
MX6SL_PAD_SD1_DAT7 = 148,
MX6SL_PAD_SD2_CLK = 149,
MX6SL_PAD_SD2_CMD = 150,
MX6SL_PAD_SD2_DAT0 = 151,
MX6SL_PAD_SD2_DAT1 = 152,
MX6SL_PAD_SD2_DAT2 = 153,
MX6SL_PAD_SD2_DAT3 = 154,
MX6SL_PAD_SD2_DAT4 = 155,
MX6SL_PAD_SD2_DAT5 = 156,
MX6SL_PAD_SD2_DAT6 = 157,
MX6SL_PAD_SD2_DAT7 = 158,
MX6SL_PAD_SD2_RST = 159,
MX6SL_PAD_SD3_CLK = 160,
MX6SL_PAD_SD3_CMD = 161,
MX6SL_PAD_SD3_DAT0 = 162,
MX6SL_PAD_SD3_DAT1 = 163,
MX6SL_PAD_SD3_DAT2 = 164,
MX6SL_PAD_SD3_DAT3 = 165,
MX6SL_PAD_UART1_RXD = 166,
MX6SL_PAD_UART1_TXD = 167,
MX6SL_PAD_WDOG_B = 168,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx6sl_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE9),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE10),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE11),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE12),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE13),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE14),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE15),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE16),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE17),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE18),
IMX_PINCTRL_PIN(MX6SL_PAD_AUD_MCLK),
IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXC),
IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXD),
IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXFS),
IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXC),
IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXD),
IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXFS),
IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MISO),
IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MOSI),
IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SCLK),
IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SS0),
IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MISO),
IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MOSI),
IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SCLK),
IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SS0),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR0),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR1),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D0),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D1),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D10),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D11),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D12),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D13),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D14),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D15),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D2),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D3),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D4),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D5),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D6),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D7),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D8),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D9),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDCLK),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDOE),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDRL),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDSP),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCOM),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL0),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL1),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL2),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL3),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRINT),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRSTAT),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRWAKEUP),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE0),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE1),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE2),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE3),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCLK),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDLE),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDOE),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDSHR),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM0),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM1),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_CRS_DV),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDC),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDIO),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_REF_CLK),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RX_ER),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD0),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD1),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_CLK),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_EN),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD0),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD1),
IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_DAT),
IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_STROBE),
IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SCL),
IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SDA),
IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SCL),
IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SDA),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL4),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL5),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL6),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL7),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW3),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW4),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW5),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW6),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW7),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_CLK),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT0),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT1),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT10),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT11),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT12),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT13),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT14),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT15),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT16),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT17),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT18),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT19),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT2),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT20),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT21),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT22),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT23),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT3),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT4),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT5),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT6),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT7),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT8),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT9),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_ENABLE),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_HSYNC),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_RESET),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_VSYNC),
IMX_PINCTRL_PIN(MX6SL_PAD_PWM1),
IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_24M),
IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_32K),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT0),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT1),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT2),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT3),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT4),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT5),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT6),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT7),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT0),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT1),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT2),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT3),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT4),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT5),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT6),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT7),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_RST),
IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CLK),
IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CMD),
IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT0),
IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT1),
IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT2),
IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT3),
IMX_PINCTRL_PIN(MX6SL_PAD_UART1_RXD),
IMX_PINCTRL_PIN(MX6SL_PAD_UART1_TXD),
IMX_PINCTRL_PIN(MX6SL_PAD_WDOG_B),
};
static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = {
.pins = imx6sl_pinctrl_pads,
.npins = ARRAY_SIZE(imx6sl_pinctrl_pads),
};
static const struct of_device_id imx6sl_pinctrl_of_match[] = {
{ .compatible = "fsl,imx6sl-iomuxc", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx6sl_pinctrl_of_match);
static int imx6sl_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx6sl_pinctrl_info);
}
static struct platform_driver imx6sl_pinctrl_driver = {
.driver = {
.name = "imx6sl-pinctrl",
.owner = THIS_MODULE,
.of_match_table = imx6sl_pinctrl_of_match,
},
.probe = imx6sl_pinctrl_probe,
.remove = imx_pinctrl_remove,
};
static int __init imx6sl_pinctrl_init(void)
{
return platform_driver_register(&imx6sl_pinctrl_driver);
}
arch_initcall(imx6sl_pinctrl_init);
static void __exit imx6sl_pinctrl_exit(void)
{
platform_driver_unregister(&imx6sl_pinctrl_driver);
}
module_exit(imx6sl_pinctrl_exit);
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Freescale imx6sl pinctrl driver");
MODULE_LICENSE("GPL v2");

407
drivers/pinctrl/freescale/pinctrl-imx6sx.c Normal file
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@ -0,0 +1,407 @@
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx6sx_pads {
MX6Sx_PAD_RESERVE0 = 0,
MX6Sx_PAD_RESERVE1 = 1,
MX6Sx_PAD_RESERVE2 = 2,
MX6Sx_PAD_RESERVE3 = 3,
MX6Sx_PAD_RESERVE4 = 4,
MX6SX_PAD_GPIO1_IO00 = 5,
MX6SX_PAD_GPIO1_IO01 = 6,
MX6SX_PAD_GPIO1_IO02 = 7,
MX6SX_PAD_GPIO1_IO03 = 8,
MX6SX_PAD_GPIO1_IO04 = 9,
MX6SX_PAD_GPIO1_IO05 = 10,
MX6SX_PAD_GPIO1_IO06 = 11,
MX6SX_PAD_GPIO1_IO07 = 12,
MX6SX_PAD_GPIO1_IO08 = 13,
MX6SX_PAD_GPIO1_IO09 = 14,
MX6SX_PAD_GPIO1_IO10 = 15,
MX6SX_PAD_GPIO1_IO11 = 16,
MX6SX_PAD_GPIO1_IO12 = 17,
MX6SX_PAD_GPIO1_IO13 = 18,
MX6SX_PAD_CSI_DATA00 = 19,
MX6SX_PAD_CSI_DATA01 = 20,
MX6SX_PAD_CSI_DATA02 = 21,
MX6SX_PAD_CSI_DATA03 = 22,
MX6SX_PAD_CSI_DATA04 = 23,
MX6SX_PAD_CSI_DATA05 = 24,
MX6SX_PAD_CSI_DATA06 = 25,
MX6SX_PAD_CSI_DATA07 = 26,
MX6SX_PAD_CSI_HSYNC = 27,
MX6SX_PAD_CSI_MCLK = 28,
MX6SX_PAD_CSI_PIXCLK = 29,
MX6SX_PAD_CSI_VSYNC = 30,
MX6SX_PAD_ENET1_COL = 31,
MX6SX_PAD_ENET1_CRS = 32,
MX6SX_PAD_ENET1_MDC = 33,
MX6SX_PAD_ENET1_MDIO = 34,
MX6SX_PAD_ENET1_RX_CLK = 35,
MX6SX_PAD_ENET1_TX_CLK = 36,
MX6SX_PAD_ENET2_COL = 37,
MX6SX_PAD_ENET2_CRS = 38,
MX6SX_PAD_ENET2_RX_CLK = 39,
MX6SX_PAD_ENET2_TX_CLK = 40,
MX6SX_PAD_KEY_COL0 = 41,
MX6SX_PAD_KEY_COL1 = 42,
MX6SX_PAD_KEY_COL2 = 43,
MX6SX_PAD_KEY_COL3 = 44,
MX6SX_PAD_KEY_COL4 = 45,
MX6SX_PAD_KEY_ROW0 = 46,
MX6SX_PAD_KEY_ROW1 = 47,
MX6SX_PAD_KEY_ROW2 = 48,
MX6SX_PAD_KEY_ROW3 = 49,
MX6SX_PAD_KEY_ROW4 = 50,
MX6SX_PAD_LCD1_CLK = 51,
MX6SX_PAD_LCD1_DATA00 = 52,
MX6SX_PAD_LCD1_DATA01 = 53,
MX6SX_PAD_LCD1_DATA02 = 54,
MX6SX_PAD_LCD1_DATA03 = 55,
MX6SX_PAD_LCD1_DATA04 = 56,
MX6SX_PAD_LCD1_DATA05 = 57,
MX6SX_PAD_LCD1_DATA06 = 58,
MX6SX_PAD_LCD1_DATA07 = 59,
MX6SX_PAD_LCD1_DATA08 = 60,
MX6SX_PAD_LCD1_DATA09 = 61,
MX6SX_PAD_LCD1_DATA10 = 62,
MX6SX_PAD_LCD1_DATA11 = 63,
MX6SX_PAD_LCD1_DATA12 = 64,
MX6SX_PAD_LCD1_DATA13 = 65,
MX6SX_PAD_LCD1_DATA14 = 66,
MX6SX_PAD_LCD1_DATA15 = 67,
MX6SX_PAD_LCD1_DATA16 = 68,
MX6SX_PAD_LCD1_DATA17 = 69,
MX6SX_PAD_LCD1_DATA18 = 70,
MX6SX_PAD_LCD1_DATA19 = 71,
MX6SX_PAD_LCD1_DATA20 = 72,
MX6SX_PAD_LCD1_DATA21 = 73,
MX6SX_PAD_LCD1_DATA22 = 74,
MX6SX_PAD_LCD1_DATA23 = 75,
MX6SX_PAD_LCD1_ENABLE = 76,
MX6SX_PAD_LCD1_HSYNC = 77,
MX6SX_PAD_LCD1_RESET = 78,
MX6SX_PAD_LCD1_VSYNC = 79,
MX6SX_PAD_NAND_ALE = 80,
MX6SX_PAD_NAND_CE0_B = 81,
MX6SX_PAD_NAND_CE1_B = 82,
MX6SX_PAD_NAND_CLE = 83,
MX6SX_PAD_NAND_DATA00 = 84 ,
MX6SX_PAD_NAND_DATA01 = 85,
MX6SX_PAD_NAND_DATA02 = 86,
MX6SX_PAD_NAND_DATA03 = 87,
MX6SX_PAD_NAND_DATA04 = 88,
MX6SX_PAD_NAND_DATA05 = 89,
MX6SX_PAD_NAND_DATA06 = 90,
MX6SX_PAD_NAND_DATA07 = 91,
MX6SX_PAD_NAND_RE_B = 92,
MX6SX_PAD_NAND_READY_B = 93,
MX6SX_PAD_NAND_WE_B = 94,
MX6SX_PAD_NAND_WP_B = 95,
MX6SX_PAD_QSPI1A_DATA0 = 96,
MX6SX_PAD_QSPI1A_DATA1 = 97,
MX6SX_PAD_QSPI1A_DATA2 = 98,
MX6SX_PAD_QSPI1A_DATA3 = 99,
MX6SX_PAD_QSPI1A_DQS = 100,
MX6SX_PAD_QSPI1A_SCLK = 101,
MX6SX_PAD_QSPI1A_SS0_B = 102,
MX6SX_PAD_QSPI1A_SS1_B = 103,
MX6SX_PAD_QSPI1B_DATA0 = 104,
MX6SX_PAD_QSPI1B_DATA1 = 105,
MX6SX_PAD_QSPI1B_DATA2 = 106,
MX6SX_PAD_QSPI1B_DATA3 = 107,
MX6SX_PAD_QSPI1B_DQS = 108,
MX6SX_PAD_QSPI1B_SCLK = 109,
MX6SX_PAD_QSPI1B_SS0_B = 110,
MX6SX_PAD_QSPI1B_SS1_B = 111,
MX6SX_PAD_RGMII1_RD0 = 112,
MX6SX_PAD_RGMII1_RD1 = 113,
MX6SX_PAD_RGMII1_RD2 = 114,
MX6SX_PAD_RGMII1_RD3 = 115,
MX6SX_PAD_RGMII1_RX_CTL = 116,
MX6SX_PAD_RGMII1_RXC = 117,
MX6SX_PAD_RGMII1_TD0 = 118,
MX6SX_PAD_RGMII1_TD1 = 119,
MX6SX_PAD_RGMII1_TD2 = 120,
MX6SX_PAD_RGMII1_TD3 = 121,
MX6SX_PAD_RGMII1_TX_CTL = 122,
MX6SX_PAD_RGMII1_TXC = 123,
MX6SX_PAD_RGMII2_RD0 = 124,
MX6SX_PAD_RGMII2_RD1 = 125,
MX6SX_PAD_RGMII2_RD2 = 126,
MX6SX_PAD_RGMII2_RD3 = 127,
MX6SX_PAD_RGMII2_RX_CTL = 128,
MX6SX_PAD_RGMII2_RXC = 129,
MX6SX_PAD_RGMII2_TD0 = 130,
MX6SX_PAD_RGMII2_TD1 = 131,
MX6SX_PAD_RGMII2_TD2 = 132,
MX6SX_PAD_RGMII2_TD3 = 133,
MX6SX_PAD_RGMII2_TX_CTL = 134,
MX6SX_PAD_RGMII2_TXC = 135,
MX6SX_PAD_SD1_CLK = 136,
MX6SX_PAD_SD1_CMD = 137,
MX6SX_PAD_SD1_DATA0 = 138,
MX6SX_PAD_SD1_DATA1 = 139,
MX6SX_PAD_SD1_DATA2 = 140,
MX6SX_PAD_SD1_DATA3 = 141,
MX6SX_PAD_SD2_CLK = 142,
MX6SX_PAD_SD2_CMD = 143,
MX6SX_PAD_SD2_DATA0 = 144,
MX6SX_PAD_SD2_DATA1 = 145,
MX6SX_PAD_SD2_DATA2 = 146,
MX6SX_PAD_SD2_DATA3 = 147,
MX6SX_PAD_SD3_CLK = 148,
MX6SX_PAD_SD3_CMD = 149,
MX6SX_PAD_SD3_DATA0 = 150,
MX6SX_PAD_SD3_DATA1 = 151,
MX6SX_PAD_SD3_DATA2 = 152,
MX6SX_PAD_SD3_DATA3 = 153,
MX6SX_PAD_SD3_DATA4 = 154,
MX6SX_PAD_SD3_DATA5 = 155,
MX6SX_PAD_SD3_DATA6 = 156,
MX6SX_PAD_SD3_DATA7 = 157,
MX6SX_PAD_SD4_CLK = 158,
MX6SX_PAD_SD4_CMD = 159,
MX6SX_PAD_SD4_DATA0 = 160,
MX6SX_PAD_SD4_DATA1 = 161,
MX6SX_PAD_SD4_DATA2 = 162,
MX6SX_PAD_SD4_DATA3 = 163,
MX6SX_PAD_SD4_DATA4 = 164,
MX6SX_PAD_SD4_DATA5 = 165,
MX6SX_PAD_SD4_DATA6 = 166,
MX6SX_PAD_SD4_DATA7 = 167,
MX6SX_PAD_SD4_RESET_B = 168,
MX6SX_PAD_USB_H_DATA = 169,
MX6SX_PAD_USB_H_STROBE = 170,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO00),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO01),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO02),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO03),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO04),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO05),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO06),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO07),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO08),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO09),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO10),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO11),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO12),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO13),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA00),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA01),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA02),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA03),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA04),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA05),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA06),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA07),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_HSYNC),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_MCLK),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_PIXCLK),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_VSYNC),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_COL),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_CRS),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDC),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDIO),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_RX_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_TX_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_COL),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_CRS),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_RX_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_TX_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL4),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW3),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW4),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA00),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA01),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA02),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA03),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA04),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA05),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA06),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA07),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA08),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA09),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA10),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA11),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA12),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA13),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA14),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA15),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA16),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA17),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA18),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA19),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA20),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA21),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA22),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA23),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_ENABLE),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_HSYNC),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_RESET),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_VSYNC),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_ALE),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE0_B),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE1_B),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CLE),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA00),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA01),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA02),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA03),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA04),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA05),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA06),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA07),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_RE_B),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_READY_B),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WE_B),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WP_B),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA0),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA1),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA2),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA3),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DQS),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SCLK),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS0_B),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS1_B),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA0),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA1),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA2),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA3),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DQS),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SCLK),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS0_B),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS1_B),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD0),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD1),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD2),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD3),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RX_CTL),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RXC),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD0),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD1),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD2),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD3),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TX_CTL),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TXC),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD0),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD1),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD2),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD3),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RX_CTL),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RXC),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD0),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD1),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD2),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD3),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TX_CTL),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TXC),
IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA0),
IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA1),
IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA2),
IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA3),
IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA0),
IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA1),
IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA2),
IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA3),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CMD),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA0),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA1),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA2),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA3),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA4),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA5),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA6),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA7),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CMD),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA0),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA1),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA2),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA3),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA4),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA5),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA6),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA7),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_RESET_B),
IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_DATA),
IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_STROBE),
};
static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
.pins = imx6sx_pinctrl_pads,
.npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
};
static const struct of_device_id imx6sx_pinctrl_of_match[] = {
{ .compatible = "fsl,imx6sx-iomuxc", },
{ /* sentinel */ }
};
static int imx6sx_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx6sx_pinctrl_info);
}
static struct platform_driver imx6sx_pinctrl_driver = {
.driver = {
.name = "imx6sx-pinctrl",
.owner = THIS_MODULE,
.of_match_table = of_match_ptr(imx6sx_pinctrl_of_match),
},
.probe = imx6sx_pinctrl_probe,
.remove = imx_pinctrl_remove,
};
static int __init imx6sx_pinctrl_init(void)
{
return platform_driver_register(&imx6sx_pinctrl_driver);
}
arch_initcall(imx6sx_pinctrl_init);
static void __exit imx6sx_pinctrl_exit(void)
{
platform_driver_unregister(&imx6sx_pinctrl_driver);
}
module_exit(imx6sx_pinctrl_exit);
MODULE_AUTHOR("Anson Huang <Anson.Huang@freescale.com>");
MODULE_DESCRIPTION("Freescale imx6sx pinctrl driver");
MODULE_LICENSE("GPL v2");

541
drivers/pinctrl/freescale/pinctrl-mxs.c Normal file
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@ -0,0 +1,541 @@
/*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "../core.h"
#include "pinctrl-mxs.h"
#define SUFFIX_LEN 4
struct mxs_pinctrl_data {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
struct mxs_pinctrl_soc_data *soc;
};
static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
return d->soc->ngroups;
}
static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
return d->soc->groups[group].name;
}
static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
const unsigned **pins, unsigned *num_pins)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
*pins = d->soc->groups[group].pins;
*num_pins = d->soc->groups[group].npins;
return 0;
}
static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned offset)
{
seq_printf(s, " %s", dev_name(pctldev->dev));
}
static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map, unsigned *num_maps)
{
struct pinctrl_map *new_map;
char *group = NULL;
unsigned new_num = 1;
unsigned long config = 0;
unsigned long *pconfig;
int length = strlen(np->name) + SUFFIX_LEN;
bool purecfg = false;
u32 val, reg;
int ret, i = 0;
/* Check for pin config node which has no 'reg' property */
if (of_property_read_u32(np, "reg", &reg))
purecfg = true;
ret = of_property_read_u32(np, "fsl,drive-strength", &val);
if (!ret)
config = val | MA_PRESENT;
ret = of_property_read_u32(np, "fsl,voltage", &val);
if (!ret)
config |= val << VOL_SHIFT | VOL_PRESENT;
ret = of_property_read_u32(np, "fsl,pull-up", &val);
if (!ret)
config |= val << PULL_SHIFT | PULL_PRESENT;
/* Check for group node which has both mux and config settings */
if (!purecfg && config)
new_num = 2;
new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL);
if (!new_map)
return -ENOMEM;
if (!purecfg) {
new_map[i].type = PIN_MAP_TYPE_MUX_GROUP;
new_map[i].data.mux.function = np->name;
/* Compose group name */
group = kzalloc(length, GFP_KERNEL);
if (!group) {
ret = -ENOMEM;
goto free;
}
snprintf(group, length, "%s.%d", np->name, reg);
new_map[i].data.mux.group = group;
i++;
}
if (config) {
pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
if (!pconfig) {
ret = -ENOMEM;
goto free_group;
}
new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
new_map[i].data.configs.group_or_pin = purecfg ? np->name :
group;
new_map[i].data.configs.configs = pconfig;
new_map[i].data.configs.num_configs = 1;
}
*map = new_map;
*num_maps = new_num;
return 0;
free_group:
if (!purecfg)
kfree(group);
free:
kfree(new_map);
return ret;
}
static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
u32 i;
for (i = 0; i < num_maps; i++) {
if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
kfree(map[i].data.mux.group);
if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
kfree(map[i].data.configs.configs);
}
kfree(map);
}
static const struct pinctrl_ops mxs_pinctrl_ops = {
.get_groups_count = mxs_get_groups_count,
.get_group_name = mxs_get_group_name,
.get_group_pins = mxs_get_group_pins,
.pin_dbg_show = mxs_pin_dbg_show,
.dt_node_to_map = mxs_dt_node_to_map,
.dt_free_map = mxs_dt_free_map,
};
static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
return d->soc->nfunctions;
}
static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned function)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
return d->soc->functions[function].name;
}
static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
unsigned group,
const char * const **groups,
unsigned * const num_groups)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
*groups = d->soc->functions[group].groups;
*num_groups = d->soc->functions[group].ngroups;
return 0;
}
static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
struct mxs_group *g = &d->soc->groups[group];
void __iomem *reg;
u8 bank, shift;
u16 pin;
u32 i;
for (i = 0; i < g->npins; i++) {
bank = PINID_TO_BANK(g->pins[i]);
pin = PINID_TO_PIN(g->pins[i]);
reg = d->base + d->soc->regs->muxsel;
reg += bank * 0x20 + pin / 16 * 0x10;
shift = pin % 16 * 2;
writel(0x3 << shift, reg + CLR);
writel(g->muxsel[i] << shift, reg + SET);
}
return 0;
}
static const struct pinmux_ops mxs_pinmux_ops = {
.get_functions_count = mxs_pinctrl_get_funcs_count,
.get_function_name = mxs_pinctrl_get_func_name,
.get_function_groups = mxs_pinctrl_get_func_groups,
.set_mux = mxs_pinctrl_set_mux,
};
static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long *config)
{
return -ENOTSUPP;
}
static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long *configs,
unsigned num_configs)
{
return -ENOTSUPP;
}
static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned group, unsigned long *config)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
*config = d->soc->groups[group].config;
return 0;
}
static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned group, unsigned long *configs,
unsigned num_configs)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
struct mxs_group *g = &d->soc->groups[group];
void __iomem *reg;
u8 ma, vol, pull, bank, shift;
u16 pin;
u32 i;
int n;
unsigned long config;
for (n = 0; n < num_configs; n++) {
config = configs[n];
ma = CONFIG_TO_MA(config);
vol = CONFIG_TO_VOL(config);
pull = CONFIG_TO_PULL(config);
for (i = 0; i < g->npins; i++) {
bank = PINID_TO_BANK(g->pins[i]);
pin = PINID_TO_PIN(g->pins[i]);
/* drive */
reg = d->base + d->soc->regs->drive;
reg += bank * 0x40 + pin / 8 * 0x10;
/* mA */
if (config & MA_PRESENT) {
shift = pin % 8 * 4;
writel(0x3 << shift, reg + CLR);
writel(ma << shift, reg + SET);
}
/* vol */
if (config & VOL_PRESENT) {
shift = pin % 8 * 4 + 2;
if (vol)
writel(1 << shift, reg + SET);
else
writel(1 << shift, reg + CLR);
}
/* pull */
if (config & PULL_PRESENT) {
reg = d->base + d->soc->regs->pull;
reg += bank * 0x10;
shift = pin;
if (pull)
writel(1 << shift, reg + SET);
else
writel(1 << shift, reg + CLR);
}
}
/* cache the config value for mxs_pinconf_group_get() */
g->config = config;
} /* for each config */
return 0;
}
static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin)
{
/* Not support */
}
static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned group)
{
unsigned long config;
if (!mxs_pinconf_group_get(pctldev, group, &config))
seq_printf(s, "0x%lx", config);
}
static const struct pinconf_ops mxs_pinconf_ops = {
.pin_config_get = mxs_pinconf_get,
.pin_config_set = mxs_pinconf_set,
.pin_config_group_get = mxs_pinconf_group_get,
.pin_config_group_set = mxs_pinconf_group_set,
.pin_config_dbg_show = mxs_pinconf_dbg_show,
.pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
};
static struct pinctrl_desc mxs_pinctrl_desc = {
.pctlops = &mxs_pinctrl_ops,
.pmxops = &mxs_pinmux_ops,
.confops = &mxs_pinconf_ops,
.owner = THIS_MODULE,
};
static int mxs_pinctrl_parse_group(struct platform_device *pdev,
struct device_node *np, int idx,
const char **out_name)
{
struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
struct mxs_group *g = &d->soc->groups[idx];
struct property *prop;
const char *propname = "fsl,pinmux-ids";
char *group;
int length = strlen(np->name) + SUFFIX_LEN;
u32 val, i;
group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
if (!group)
return -ENOMEM;
if (of_property_read_u32(np, "reg", &val))
snprintf(group, length, "%s", np->name);
else
snprintf(group, length, "%s.%d", np->name, val);
g->name = group;
prop = of_find_property(np, propname, &length);
if (!prop)
return -EINVAL;
g->npins = length / sizeof(u32);
g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins),
GFP_KERNEL);
if (!g->pins)
return -ENOMEM;
g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel),
GFP_KERNEL);
if (!g->muxsel)
return -ENOMEM;
of_property_read_u32_array(np, propname, g->pins, g->npins);
for (i = 0; i < g->npins; i++) {
g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
g->pins[i] = MUXID_TO_PINID(g->pins[i]);
}
if (out_name)
*out_name = g->name;
return 0;
}
static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
struct mxs_pinctrl_data *d)
{
struct mxs_pinctrl_soc_data *soc = d->soc;
struct device_node *np = pdev->dev.of_node;
struct device_node *child;
struct mxs_function *f;
const char *gpio_compat = "fsl,mxs-gpio";
const char *fn, *fnull = "";
int i = 0, idxf = 0, idxg = 0;
int ret;
u32 val;
child = of_get_next_child(np, NULL);
if (!child) {
dev_err(&pdev->dev, "no group is defined\n");
return -ENOENT;
}
/* Count total functions and groups */
fn = fnull;
for_each_child_of_node(np, child) {
if (of_device_is_compatible(child, gpio_compat))
continue;
soc->ngroups++;
/* Skip pure pinconf node */
if (of_property_read_u32(child, "reg", &val))
continue;
if (strcmp(fn, child->name)) {
fn = child->name;
soc->nfunctions++;
}
}
soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions *
sizeof(*soc->functions), GFP_KERNEL);
if (!soc->functions)
return -ENOMEM;
soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups *
sizeof(*soc->groups), GFP_KERNEL);
if (!soc->groups)
return -ENOMEM;
/* Count groups for each function */
fn = fnull;
f = &soc->functions[idxf];
for_each_child_of_node(np, child) {
if (of_device_is_compatible(child, gpio_compat))
continue;
if (of_property_read_u32(child, "reg", &val))
continue;
if (strcmp(fn, child->name)) {
f = &soc->functions[idxf++];
f->name = fn = child->name;
}
f->ngroups++;
};
/* Get groups for each function */
idxf = 0;
fn = fnull;
for_each_child_of_node(np, child) {
if (of_device_is_compatible(child, gpio_compat))
continue;
if (of_property_read_u32(child, "reg", &val)) {
ret = mxs_pinctrl_parse_group(pdev, child,
idxg++, NULL);
if (ret)
return ret;
continue;
}
if (strcmp(fn, child->name)) {
f = &soc->functions[idxf++];
f->groups = devm_kzalloc(&pdev->dev, f->ngroups *
sizeof(*f->groups),
GFP_KERNEL);
if (!f->groups)
return -ENOMEM;
fn = child->name;
i = 0;
}
ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
&f->groups[i++]);
if (ret)
return ret;
}
return 0;
}
int mxs_pinctrl_probe(struct platform_device *pdev,
struct mxs_pinctrl_soc_data *soc)
{
struct device_node *np = pdev->dev.of_node;
struct mxs_pinctrl_data *d;
int ret;
d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
if (!d)
return -ENOMEM;
d->dev = &pdev->dev;
d->soc = soc;
d->base = of_iomap(np, 0);
if (!d->base)
return -EADDRNOTAVAIL;
mxs_pinctrl_desc.pins = d->soc->pins;
mxs_pinctrl_desc.npins = d->soc->npins;
mxs_pinctrl_desc.name = dev_name(&pdev->dev);
platform_set_drvdata(pdev, d);
ret = mxs_pinctrl_probe_dt(pdev, d);
if (ret) {
dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
goto err;
}
d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
if (!d->pctl) {
dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
ret = -EINVAL;
goto err;
}
return 0;
err:
iounmap(d->base);
return ret;
}
EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
int mxs_pinctrl_remove(struct platform_device *pdev)
{
struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
pinctrl_unregister(d->pctl);
iounmap(d->base);
return 0;
}
EXPORT_SYMBOL_GPL(mxs_pinctrl_remove);

91
drivers/pinctrl/freescale/pinctrl-mxs.h Normal file
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/*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __PINCTRL_MXS_H
#define __PINCTRL_MXS_H
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#define SET 0x4
#define CLR 0x8
#define TOG 0xc
#define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
#define PINID(bank, pin) ((bank) * 32 + (pin))
/*
* pinmux-id bit field definitions
*
* bank: 15..12 (4)
* pin: 11..4 (8)
* muxsel: 3..0 (4)
*/
#define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff)
#define MUXID_TO_MUXSEL(m) ((m) & 0xf)
#define PINID_TO_BANK(p) ((p) >> 5)
#define PINID_TO_PIN(p) ((p) % 32)
/*
* pin config bit field definitions
*
* pull-up: 6..5 (2)
* voltage: 4..3 (2)
* mA: 2..0 (3)
*
* MSB of each field is presence bit for the config.
*/
#define PULL_PRESENT (1 << 6)
#define PULL_SHIFT 5
#define VOL_PRESENT (1 << 4)
#define VOL_SHIFT 3
#define MA_PRESENT (1 << 2)
#define MA_SHIFT 0
#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
struct mxs_function {
const char *name;
const char **groups;
unsigned ngroups;
};
struct mxs_group {
const char *name;
unsigned int *pins;
unsigned npins;
u8 *muxsel;
u8 config;
};
struct mxs_regs {
u16 muxsel;
u16 drive;
u16 pull;
};
struct mxs_pinctrl_soc_data {
const struct mxs_regs *regs;
const struct pinctrl_pin_desc *pins;
unsigned npins;
struct mxs_function *functions;
unsigned nfunctions;
struct mxs_group *groups;
unsigned ngroups;
};
int mxs_pinctrl_probe(struct platform_device *pdev,
struct mxs_pinctrl_soc_data *soc);
int mxs_pinctrl_remove(struct platform_device *pdev);
#endif /* __PINCTRL_MXS_H */

338
drivers/pinctrl/freescale/pinctrl-vf610.c Normal file
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/*
* VF610 pinctrl driver based on imx pinmux and pinconf core
*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum vf610_pads {
VF610_PAD_PTA6 = 0,
VF610_PAD_PTA8 = 1,
VF610_PAD_PTA9 = 2,
VF610_PAD_PTA10 = 3,
VF610_PAD_PTA11 = 4,
VF610_PAD_PTA12 = 5,
VF610_PAD_PTA16 = 6,
VF610_PAD_PTA17 = 7,
VF610_PAD_PTA18 = 8,
VF610_PAD_PTA19 = 9,
VF610_PAD_PTA20 = 10,
VF610_PAD_PTA21 = 11,
VF610_PAD_PTA22 = 12,
VF610_PAD_PTA23 = 13,
VF610_PAD_PTA24 = 14,
VF610_PAD_PTA25 = 15,
VF610_PAD_PTA26 = 16,
VF610_PAD_PTA27 = 17,
VF610_PAD_PTA28 = 18,
VF610_PAD_PTA29 = 19,
VF610_PAD_PTA30 = 20,
VF610_PAD_PTA31 = 21,
VF610_PAD_PTB0 = 22,
VF610_PAD_PTB1 = 23,
VF610_PAD_PTB2 = 24,
VF610_PAD_PTB3 = 25,
VF610_PAD_PTB4 = 26,
VF610_PAD_PTB5 = 27,
VF610_PAD_PTB6 = 28,
VF610_PAD_PTB7 = 29,
VF610_PAD_PTB8 = 30,
VF610_PAD_PTB9 = 31,
VF610_PAD_PTB10 = 32,
VF610_PAD_PTB11 = 33,
VF610_PAD_PTB12 = 34,
VF610_PAD_PTB13 = 35,
VF610_PAD_PTB14 = 36,
VF610_PAD_PTB15 = 37,
VF610_PAD_PTB16 = 38,
VF610_PAD_PTB17 = 39,
VF610_PAD_PTB18 = 40,
VF610_PAD_PTB19 = 41,
VF610_PAD_PTB20 = 42,
VF610_PAD_PTB21 = 43,
VF610_PAD_PTB22 = 44,
VF610_PAD_PTC0 = 45,
VF610_PAD_PTC1 = 46,
VF610_PAD_PTC2 = 47,
VF610_PAD_PTC3 = 48,
VF610_PAD_PTC4 = 49,
VF610_PAD_PTC5 = 50,
VF610_PAD_PTC6 = 51,
VF610_PAD_PTC7 = 52,
VF610_PAD_PTC8 = 53,
VF610_PAD_PTC9 = 54,
VF610_PAD_PTC10 = 55,
VF610_PAD_PTC11 = 56,
VF610_PAD_PTC12 = 57,
VF610_PAD_PTC13 = 58,
VF610_PAD_PTC14 = 59,
VF610_PAD_PTC15 = 60,
VF610_PAD_PTC16 = 61,
VF610_PAD_PTC17 = 62,
VF610_PAD_PTD31 = 63,
VF610_PAD_PTD30 = 64,
VF610_PAD_PTD29 = 65,
VF610_PAD_PTD28 = 66,
VF610_PAD_PTD27 = 67,
VF610_PAD_PTD26 = 68,
VF610_PAD_PTD25 = 69,
VF610_PAD_PTD24 = 70,
VF610_PAD_PTD23 = 71,
VF610_PAD_PTD22 = 72,
VF610_PAD_PTD21 = 73,
VF610_PAD_PTD20 = 74,
VF610_PAD_PTD19 = 75,
VF610_PAD_PTD18 = 76,
VF610_PAD_PTD17 = 77,
VF610_PAD_PTD16 = 78,
VF610_PAD_PTD0 = 79,
VF610_PAD_PTD1 = 80,
VF610_PAD_PTD2 = 81,
VF610_PAD_PTD3 = 82,
VF610_PAD_PTD4 = 83,
VF610_PAD_PTD5 = 84,
VF610_PAD_PTD6 = 85,
VF610_PAD_PTD7 = 86,
VF610_PAD_PTD8 = 87,
VF610_PAD_PTD9 = 88,
VF610_PAD_PTD10 = 89,
VF610_PAD_PTD11 = 90,
VF610_PAD_PTD12 = 91,
VF610_PAD_PTD13 = 92,
VF610_PAD_PTB23 = 93,
VF610_PAD_PTB24 = 94,
VF610_PAD_PTB25 = 95,
VF610_PAD_PTB26 = 96,
VF610_PAD_PTB27 = 97,
VF610_PAD_PTB28 = 98,
VF610_PAD_PTC26 = 99,
VF610_PAD_PTC27 = 100,
VF610_PAD_PTC28 = 101,
VF610_PAD_PTC29 = 102,
VF610_PAD_PTC30 = 103,
VF610_PAD_PTC31 = 104,
VF610_PAD_PTE0 = 105,
VF610_PAD_PTE1 = 106,
VF610_PAD_PTE2 = 107,
VF610_PAD_PTE3 = 108,
VF610_PAD_PTE4 = 109,
VF610_PAD_PTE5 = 110,
VF610_PAD_PTE6 = 111,
VF610_PAD_PTE7 = 112,
VF610_PAD_PTE8 = 113,
VF610_PAD_PTE9 = 114,
VF610_PAD_PTE10 = 115,
VF610_PAD_PTE11 = 116,
VF610_PAD_PTE12 = 117,
VF610_PAD_PTE13 = 118,
VF610_PAD_PTE14 = 119,
VF610_PAD_PTE15 = 120,
VF610_PAD_PTE16 = 121,
VF610_PAD_PTE17 = 122,
VF610_PAD_PTE18 = 123,
VF610_PAD_PTE19 = 124,
VF610_PAD_PTE20 = 125,
VF610_PAD_PTE21 = 126,
VF610_PAD_PTE22 = 127,
VF610_PAD_PTE23 = 128,
VF610_PAD_PTE24 = 129,
VF610_PAD_PTE25 = 130,
VF610_PAD_PTE26 = 131,
VF610_PAD_PTE27 = 132,
VF610_PAD_PTE28 = 133,
VF610_PAD_PTA7 = 134,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = {
IMX_PINCTRL_PIN(VF610_PAD_PTA6),
IMX_PINCTRL_PIN(VF610_PAD_PTA8),
IMX_PINCTRL_PIN(VF610_PAD_PTA9),
IMX_PINCTRL_PIN(VF610_PAD_PTA10),
IMX_PINCTRL_PIN(VF610_PAD_PTA11),
IMX_PINCTRL_PIN(VF610_PAD_PTA12),
IMX_PINCTRL_PIN(VF610_PAD_PTA16),
IMX_PINCTRL_PIN(VF610_PAD_PTA17),
IMX_PINCTRL_PIN(VF610_PAD_PTA18),
IMX_PINCTRL_PIN(VF610_PAD_PTA19),
IMX_PINCTRL_PIN(VF610_PAD_PTA20),
IMX_PINCTRL_PIN(VF610_PAD_PTA21),
IMX_PINCTRL_PIN(VF610_PAD_PTA22),
IMX_PINCTRL_PIN(VF610_PAD_PTA23),
IMX_PINCTRL_PIN(VF610_PAD_PTA24),
IMX_PINCTRL_PIN(VF610_PAD_PTA25),
IMX_PINCTRL_PIN(VF610_PAD_PTA26),
IMX_PINCTRL_PIN(VF610_PAD_PTA27),
IMX_PINCTRL_PIN(VF610_PAD_PTA28),
IMX_PINCTRL_PIN(VF610_PAD_PTA29),
IMX_PINCTRL_PIN(VF610_PAD_PTA30),
IMX_PINCTRL_PIN(VF610_PAD_PTA31),
IMX_PINCTRL_PIN(VF610_PAD_PTB0),
IMX_PINCTRL_PIN(VF610_PAD_PTB1),
IMX_PINCTRL_PIN(VF610_PAD_PTB2),
IMX_PINCTRL_PIN(VF610_PAD_PTB3),
IMX_PINCTRL_PIN(VF610_PAD_PTB4),
IMX_PINCTRL_PIN(VF610_PAD_PTB5),
IMX_PINCTRL_PIN(VF610_PAD_PTB6),
IMX_PINCTRL_PIN(VF610_PAD_PTB7),
IMX_PINCTRL_PIN(VF610_PAD_PTB8),
IMX_PINCTRL_PIN(VF610_PAD_PTB9),
IMX_PINCTRL_PIN(VF610_PAD_PTB10),
IMX_PINCTRL_PIN(VF610_PAD_PTB11),
IMX_PINCTRL_PIN(VF610_PAD_PTB12),
IMX_PINCTRL_PIN(VF610_PAD_PTB13),
IMX_PINCTRL_PIN(VF610_PAD_PTB14),
IMX_PINCTRL_PIN(VF610_PAD_PTB15),
IMX_PINCTRL_PIN(VF610_PAD_PTB16),
IMX_PINCTRL_PIN(VF610_PAD_PTB17),
IMX_PINCTRL_PIN(VF610_PAD_PTB18),
IMX_PINCTRL_PIN(VF610_PAD_PTB19),
IMX_PINCTRL_PIN(VF610_PAD_PTB20),
IMX_PINCTRL_PIN(VF610_PAD_PTB21),
IMX_PINCTRL_PIN(VF610_PAD_PTB22),
IMX_PINCTRL_PIN(VF610_PAD_PTC0),
IMX_PINCTRL_PIN(VF610_PAD_PTC1),
IMX_PINCTRL_PIN(VF610_PAD_PTC2),
IMX_PINCTRL_PIN(VF610_PAD_PTC3),
IMX_PINCTRL_PIN(VF610_PAD_PTC4),
IMX_PINCTRL_PIN(VF610_PAD_PTC5),
IMX_PINCTRL_PIN(VF610_PAD_PTC6),
IMX_PINCTRL_PIN(VF610_PAD_PTC7),
IMX_PINCTRL_PIN(VF610_PAD_PTC8),
IMX_PINCTRL_PIN(VF610_PAD_PTC9),
IMX_PINCTRL_PIN(VF610_PAD_PTC10),
IMX_PINCTRL_PIN(VF610_PAD_PTC11),
IMX_PINCTRL_PIN(VF610_PAD_PTC12),
IMX_PINCTRL_PIN(VF610_PAD_PTC13),
IMX_PINCTRL_PIN(VF610_PAD_PTC14),
IMX_PINCTRL_PIN(VF610_PAD_PTC15),
IMX_PINCTRL_PIN(VF610_PAD_PTC16),
IMX_PINCTRL_PIN(VF610_PAD_PTC17),
IMX_PINCTRL_PIN(VF610_PAD_PTD31),
IMX_PINCTRL_PIN(VF610_PAD_PTD30),
IMX_PINCTRL_PIN(VF610_PAD_PTD29),
IMX_PINCTRL_PIN(VF610_PAD_PTD28),
IMX_PINCTRL_PIN(VF610_PAD_PTD27),
IMX_PINCTRL_PIN(VF610_PAD_PTD26),
IMX_PINCTRL_PIN(VF610_PAD_PTD25),
IMX_PINCTRL_PIN(VF610_PAD_PTD24),
IMX_PINCTRL_PIN(VF610_PAD_PTD23),
IMX_PINCTRL_PIN(VF610_PAD_PTD22),
IMX_PINCTRL_PIN(VF610_PAD_PTD21),
IMX_PINCTRL_PIN(VF610_PAD_PTD20),
IMX_PINCTRL_PIN(VF610_PAD_PTD19),
IMX_PINCTRL_PIN(VF610_PAD_PTD18),
IMX_PINCTRL_PIN(VF610_PAD_PTD17),
IMX_PINCTRL_PIN(VF610_PAD_PTD16),
IMX_PINCTRL_PIN(VF610_PAD_PTD0),
IMX_PINCTRL_PIN(VF610_PAD_PTD1),
IMX_PINCTRL_PIN(VF610_PAD_PTD2),
IMX_PINCTRL_PIN(VF610_PAD_PTD3),
IMX_PINCTRL_PIN(VF610_PAD_PTD4),
IMX_PINCTRL_PIN(VF610_PAD_PTD5),
IMX_PINCTRL_PIN(VF610_PAD_PTD6),
IMX_PINCTRL_PIN(VF610_PAD_PTD7),
IMX_PINCTRL_PIN(VF610_PAD_PTD8),
IMX_PINCTRL_PIN(VF610_PAD_PTD9),
IMX_PINCTRL_PIN(VF610_PAD_PTD10),
IMX_PINCTRL_PIN(VF610_PAD_PTD11),
IMX_PINCTRL_PIN(VF610_PAD_PTD12),
IMX_PINCTRL_PIN(VF610_PAD_PTD13),
IMX_PINCTRL_PIN(VF610_PAD_PTB23),
IMX_PINCTRL_PIN(VF610_PAD_PTB24),
IMX_PINCTRL_PIN(VF610_PAD_PTB25),
IMX_PINCTRL_PIN(VF610_PAD_PTB26),
IMX_PINCTRL_PIN(VF610_PAD_PTB27),
IMX_PINCTRL_PIN(VF610_PAD_PTB28),
IMX_PINCTRL_PIN(VF610_PAD_PTC26),
IMX_PINCTRL_PIN(VF610_PAD_PTC27),
IMX_PINCTRL_PIN(VF610_PAD_PTC28),
IMX_PINCTRL_PIN(VF610_PAD_PTC29),
IMX_PINCTRL_PIN(VF610_PAD_PTC30),
IMX_PINCTRL_PIN(VF610_PAD_PTC31),
IMX_PINCTRL_PIN(VF610_PAD_PTE0),
IMX_PINCTRL_PIN(VF610_PAD_PTE1),
IMX_PINCTRL_PIN(VF610_PAD_PTE2),
IMX_PINCTRL_PIN(VF610_PAD_PTE3),
IMX_PINCTRL_PIN(VF610_PAD_PTE4),
IMX_PINCTRL_PIN(VF610_PAD_PTE5),
IMX_PINCTRL_PIN(VF610_PAD_PTE6),
IMX_PINCTRL_PIN(VF610_PAD_PTE7),
IMX_PINCTRL_PIN(VF610_PAD_PTE8),
IMX_PINCTRL_PIN(VF610_PAD_PTE9),
IMX_PINCTRL_PIN(VF610_PAD_PTE10),
IMX_PINCTRL_PIN(VF610_PAD_PTE11),
IMX_PINCTRL_PIN(VF610_PAD_PTE12),
IMX_PINCTRL_PIN(VF610_PAD_PTE13),
IMX_PINCTRL_PIN(VF610_PAD_PTE14),
IMX_PINCTRL_PIN(VF610_PAD_PTE15),
IMX_PINCTRL_PIN(VF610_PAD_PTE16),
IMX_PINCTRL_PIN(VF610_PAD_PTE17),
IMX_PINCTRL_PIN(VF610_PAD_PTE18),
IMX_PINCTRL_PIN(VF610_PAD_PTE19),
IMX_PINCTRL_PIN(VF610_PAD_PTE20),
IMX_PINCTRL_PIN(VF610_PAD_PTE21),
IMX_PINCTRL_PIN(VF610_PAD_PTE22),
IMX_PINCTRL_PIN(VF610_PAD_PTE23),
IMX_PINCTRL_PIN(VF610_PAD_PTE24),
IMX_PINCTRL_PIN(VF610_PAD_PTE25),
IMX_PINCTRL_PIN(VF610_PAD_PTE26),
IMX_PINCTRL_PIN(VF610_PAD_PTE27),
IMX_PINCTRL_PIN(VF610_PAD_PTE28),
IMX_PINCTRL_PIN(VF610_PAD_PTA7),
};
static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
.pins = vf610_pinctrl_pads,
.npins = ARRAY_SIZE(vf610_pinctrl_pads),
.flags = SHARE_MUX_CONF_REG,
};
static struct of_device_id vf610_pinctrl_of_match[] = {
{ .compatible = "fsl,vf610-iomuxc", },
{ /* sentinel */ }
};
static int vf610_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &vf610_pinctrl_info);
}
static struct platform_driver vf610_pinctrl_driver = {
.driver = {
.name = "vf610-pinctrl",
.owner = THIS_MODULE,
.of_match_table = vf610_pinctrl_of_match,
},
.probe = vf610_pinctrl_probe,
.remove = imx_pinctrl_remove,
};
static int __init vf610_pinctrl_init(void)
{
return platform_driver_register(&vf610_pinctrl_driver);
}
arch_initcall(vf610_pinctrl_init);
static void __exit vf610_pinctrl_exit(void)
{
platform_driver_unregister(&vf610_pinctrl_driver);
}
module_exit(vf610_pinctrl_exit);
MODULE_DESCRIPTION("Freescale VF610 pinctrl driver");
MODULE_LICENSE("GPL v2");