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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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35
drivers/pinctrl/samsung/Kconfig Normal file
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#
# Samsung Pin control drivers
#
config PINCTRL_SAMSUNG
bool
select PINMUX
select PINCONF
config PINCTRL_EXYNOS
bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440"
depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210)
select PINCTRL_SAMSUNG
config PINCTRL_EXYNOS5440
bool "Samsung EXYNOS5440 SoC pinctrl driver"
depends on SOC_EXYNOS5440
select PINMUX
select PINCONF
config PINCTRL_S3C24XX
bool "Samsung S3C24XX SoC pinctrl driver"
depends on ARCH_S3C24XX
select PINCTRL_SAMSUNG
config PINCTRL_S3C64XX
bool "Samsung S3C64XX SoC pinctrl driver"
depends on ARCH_S3C64XX
select PINCTRL_SAMSUNG
config SEC_GPIO_DVS
tristate "setting Samsung GPIO debugging and verification system"
config SENSORS_FP_SPI_GPIO
depends on SENSORS_FINGERPRINT
string "Fingerprint spi gpio name"

8
drivers/pinctrl/samsung/Makefile Normal file
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# Samsung pin control drivers
ccflags-y := $(KBUILD_FP_SENSOR_CFLAGS)
obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o
obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o
obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o
obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o
obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
obj-$(CONFIG_SEC_GPIO_DVS) += secgpio_dvs.o

1711
drivers/pinctrl/samsung/pinctrl-exynos.c Normal file
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103
drivers/pinctrl/samsung/pinctrl-exynos.h Normal file
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/*
* Exynos specific definitions for Samsung pinctrl and gpiolib driver.
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2012 Linaro Ltd
* http://www.linaro.org
*
* This file contains the Exynos specific definitions for the Samsung
* pinctrl/gpiolib interface drivers.
*
* Author: Thomas Abraham <thomas.ab@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
/* External GPIO and wakeup interrupt related definitions */
#define EXYNOS_GPIO_ECON_OFFSET 0x700
#define EXYNOS_GPIO_EFLTCON_OFFSET 0x800
#define EXYNOS_GPIO_EMASK_OFFSET 0x900
#define EXYNOS_GPIO_EPEND_OFFSET 0xA00
#define EXYNOS_SVC_OFFSET 0xB08
#define EXYNOS_EINT_FUNC 0xF
/* helpers to access interrupt service register */
#define EXYNOS_SVC_GROUP_SHIFT 3
#define EXYNOS_SVC_GROUP_MASK 0x1f
#define EXYNOS_SVC_NUM_MASK 7
#define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \
EXYNOS_SVC_GROUP_MASK)
/* Exynos specific external interrupt trigger types */
#define EXYNOS_EINT_LEVEL_LOW 0
#define EXYNOS_EINT_LEVEL_HIGH 1
#define EXYNOS_EINT_EDGE_FALLING 2
#define EXYNOS_EINT_EDGE_RISING 3
#define EXYNOS_EINT_EDGE_BOTH 4
#define EXYNOS_EINT_CON_MASK 0xF
#define EXYNOS_EINT_CON_LEN 4
/* EINT filter configuration */
#define EXYNOS_EINT_FLTCON_EN (1 << 7)
#define EXYNOS_EINT_FLTCON_SEL (1 << 6)
#define EXYNOS_EINT_FLTCON_WIDTH(x) ((x) & 0x3f)
#define EXYNOS_EINT_FLTCON_MASK 0xFF
#define EXYNOS_EINT_FLTCON_LEN 8
#define EXYNOS_EINT_MAX_PER_BANK 8
#define EXYNOS_EINT_NR_WKUP_EINT
#define EXYNOS_PIN_BANK_EINTN(types, pins, reg, id) \
{ \
.type = &types, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_NONE, \
.name = id \
}
#define EXYNOS_PIN_BANK_EINTG(types, pins, reg, id, offs) \
{ \
.type = &types, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_offset = offs, \
.name = id \
}
#define EXYNOS_PIN_BANK_EINTW(types, pins, reg, id, offs) \
{ \
.type = &types, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_offset = offs, \
.name = id \
}
/**
* struct exynos_weint_data: irq specific data for all the wakeup interrupts
* generated by the external wakeup interrupt controller.
* @irq: interrupt number within the domain.
* @bank: bank responsible for this interrupt
*/
struct exynos_weint_data {
unsigned int irq;
struct samsung_pin_bank *bank;
};
/**
* struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts
* generated by the external wakeup interrupt controller.
* @nr_banks: count of banks being part of the mux
* @banks: array of banks being part of the mux
*/
struct exynos_muxed_weint_data {
unsigned int nr_banks;
struct samsung_pin_bank *banks[];
};

1058
drivers/pinctrl/samsung/pinctrl-exynos5440.c Normal file
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drivers/pinctrl/samsung/pinctrl-s3c24xx.c Normal file
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/*
* S3C24XX specific support for Samsung pinctrl/gpiolib driver.
*
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This file contains the SamsungS3C24XX specific information required by the
* Samsung pinctrl/gpiolib driver. It also includes the implementation of
* external gpio and wakeup interrupt support.
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/of_irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/err.h>
#include "pinctrl-samsung.h"
#define NUM_EINT 24
#define NUM_EINT_IRQ 6
#define EINT_MAX_PER_GROUP 8
#define EINTPEND_REG 0xa8
#define EINTMASK_REG 0xa4
#define EINT_GROUP(i) ((int)((i) / EINT_MAX_PER_GROUP))
#define EINT_REG(i) ((EINT_GROUP(i) * 4) + 0x88)
#define EINT_OFFS(i) ((i) % EINT_MAX_PER_GROUP * 4)
#define EINT_LEVEL_LOW 0
#define EINT_LEVEL_HIGH 1
#define EINT_EDGE_FALLING 2
#define EINT_EDGE_RISING 4
#define EINT_EDGE_BOTH 6
#define EINT_MASK 0xf
static struct samsung_pin_bank_type bank_type_1bit = {
.fld_width = { 1, 1, },
.reg_offset = { 0x00, 0x04, },
};
static struct samsung_pin_bank_type bank_type_2bit = {
.fld_width = { 2, 1, 2, },
.reg_offset = { 0x00, 0x04, 0x08, },
};
#define PIN_BANK_A(pins, reg, id) \
{ \
.type = &bank_type_1bit, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_NONE, \
.name = id \
}
#define PIN_BANK_2BIT(pins, reg, id) \
{ \
.type = &bank_type_2bit, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_NONE, \
.name = id \
}
#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\
{ \
.type = &bank_type_2bit, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_func = 2, \
.eint_mask = emask, \
.eint_offset = eoffs, \
.name = id \
}
/**
* struct s3c24xx_eint_data: EINT common data
* @drvdata: pin controller driver data
* @domains: IRQ domains of particular EINT interrupts
* @parents: mapped parent irqs in the main interrupt controller
*/
struct s3c24xx_eint_data {
struct samsung_pinctrl_drv_data *drvdata;
struct irq_domain *domains[NUM_EINT];
int parents[NUM_EINT_IRQ];
};
/**
* struct s3c24xx_eint_domain_data: per irq-domain data
* @bank: pin bank related to the domain
* @eint_data: common data
* eint0_3_parent_only: live eints 0-3 only in the main intc
*/
struct s3c24xx_eint_domain_data {
struct samsung_pin_bank *bank;
struct s3c24xx_eint_data *eint_data;
bool eint0_3_parent_only;
};
static int s3c24xx_eint_get_trigger(unsigned int type)
{
switch (type) {
case IRQ_TYPE_EDGE_RISING:
return EINT_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
return EINT_EDGE_FALLING;
break;
case IRQ_TYPE_EDGE_BOTH:
return EINT_EDGE_BOTH;
break;
case IRQ_TYPE_LEVEL_HIGH:
return EINT_LEVEL_HIGH;
break;
case IRQ_TYPE_LEVEL_LOW:
return EINT_LEVEL_LOW;
break;
default:
return -EINVAL;
}
}
static void s3c24xx_eint_set_handler(unsigned int irq, unsigned int type)
{
/* Edge- and level-triggered interrupts need different handlers */
if (type & IRQ_TYPE_EDGE_BOTH)
__irq_set_handler_locked(irq, handle_edge_irq);
else
__irq_set_handler_locked(irq, handle_level_irq);
}
static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d,
struct samsung_pin_bank *bank, int pin)
{
struct samsung_pin_bank_type *bank_type = bank->type;
unsigned long flags;
void __iomem *reg;
u8 shift;
u32 mask;
u32 val;
/* Make sure that pin is configured as interrupt */
reg = d->virt_base + bank->pctl_offset;
shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
spin_lock_irqsave(&bank->slock, flags);
val = readl(reg);
val &= ~(mask << shift);
val |= bank->eint_func << shift;
writel(val, reg);
spin_unlock_irqrestore(&bank->slock, flags);
}
static int s3c24xx_eint_type(struct irq_data *data, unsigned int type)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
int index = bank->eint_offset + data->hwirq;
void __iomem *reg;
int trigger;
u8 shift;
u32 val;
trigger = s3c24xx_eint_get_trigger(type);
if (trigger < 0) {
dev_err(d->dev, "unsupported external interrupt type\n");
return -EINVAL;
}
s3c24xx_eint_set_handler(data->irq, type);
/* Set up interrupt trigger */
reg = d->virt_base + EINT_REG(index);
shift = EINT_OFFS(index);
val = readl(reg);
val &= ~(EINT_MASK << shift);
val |= trigger << shift;
writel(val, reg);
s3c24xx_eint_set_function(d, bank, data->hwirq);
return 0;
}
/* Handling of EINTs 0-3 on all except S3C2412 and S3C2413 */
static void s3c2410_eint0_3_ack(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
struct s3c24xx_eint_data *eint_data = ddata->eint_data;
int parent_irq = eint_data->parents[data->hwirq];
struct irq_chip *parent_chip = irq_get_chip(parent_irq);
parent_chip->irq_ack(irq_get_irq_data(parent_irq));
}
static void s3c2410_eint0_3_mask(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
struct s3c24xx_eint_data *eint_data = ddata->eint_data;
int parent_irq = eint_data->parents[data->hwirq];
struct irq_chip *parent_chip = irq_get_chip(parent_irq);
parent_chip->irq_mask(irq_get_irq_data(parent_irq));
}
static void s3c2410_eint0_3_unmask(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
struct s3c24xx_eint_data *eint_data = ddata->eint_data;
int parent_irq = eint_data->parents[data->hwirq];
struct irq_chip *parent_chip = irq_get_chip(parent_irq);
parent_chip->irq_unmask(irq_get_irq_data(parent_irq));
}
static struct irq_chip s3c2410_eint0_3_chip = {
.name = "s3c2410-eint0_3",
.irq_ack = s3c2410_eint0_3_ack,
.irq_mask = s3c2410_eint0_3_mask,
.irq_unmask = s3c2410_eint0_3_unmask,
.irq_set_type = s3c24xx_eint_type,
};
static void s3c2410_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
{
struct irq_data *data = irq_desc_get_irq_data(desc);
struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq);
unsigned int virq;
/* the first 4 eints have a simple 1 to 1 mapping */
virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
/* Something must be really wrong if an unmapped EINT is unmasked */
BUG_ON(!virq);
generic_handle_irq(virq);
}
/* Handling of EINTs 0-3 on S3C2412 and S3C2413 */
static void s3c2412_eint0_3_ack(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned long bitval = 1UL << data->hwirq;
writel(bitval, d->virt_base + EINTPEND_REG);
}
static void s3c2412_eint0_3_mask(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned long mask;
mask = readl(d->virt_base + EINTMASK_REG);
mask |= (1UL << data->hwirq);
writel(mask, d->virt_base + EINTMASK_REG);
}
static void s3c2412_eint0_3_unmask(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned long mask;
mask = readl(d->virt_base + EINTMASK_REG);
mask &= ~(1UL << data->hwirq);
writel(mask, d->virt_base + EINTMASK_REG);
}
static struct irq_chip s3c2412_eint0_3_chip = {
.name = "s3c2412-eint0_3",
.irq_ack = s3c2412_eint0_3_ack,
.irq_mask = s3c2412_eint0_3_mask,
.irq_unmask = s3c2412_eint0_3_unmask,
.irq_set_type = s3c24xx_eint_type,
};
static void s3c2412_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_get_chip(irq);
struct irq_data *data = irq_desc_get_irq_data(desc);
struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq);
unsigned int virq;
chained_irq_enter(chip, desc);
/* the first 4 eints have a simple 1 to 1 mapping */
virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
/* Something must be really wrong if an unmapped EINT is unmasked */
BUG_ON(!virq);
generic_handle_irq(virq);
chained_irq_exit(chip, desc);
}
/* Handling of all other eints */
static void s3c24xx_eint_ack(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned char index = bank->eint_offset + data->hwirq;
writel(1UL << index, d->virt_base + EINTPEND_REG);
}
static void s3c24xx_eint_mask(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned char index = bank->eint_offset + data->hwirq;
unsigned long mask;
mask = readl(d->virt_base + EINTMASK_REG);
mask |= (1UL << index);
writel(mask, d->virt_base + EINTMASK_REG);
}
static void s3c24xx_eint_unmask(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned char index = bank->eint_offset + data->hwirq;
unsigned long mask;
mask = readl(d->virt_base + EINTMASK_REG);
mask &= ~(1UL << index);
writel(mask, d->virt_base + EINTMASK_REG);
}
static struct irq_chip s3c24xx_eint_chip = {
.name = "s3c-eint",
.irq_ack = s3c24xx_eint_ack,
.irq_mask = s3c24xx_eint_mask,
.irq_unmask = s3c24xx_eint_unmask,
.irq_set_type = s3c24xx_eint_type,
};
static inline void s3c24xx_demux_eint(unsigned int irq, struct irq_desc *desc,
u32 offset, u32 range)
{
struct irq_chip *chip = irq_get_chip(irq);
struct s3c24xx_eint_data *data = irq_get_handler_data(irq);
struct samsung_pinctrl_drv_data *d = data->drvdata;
unsigned int pend, mask;
chained_irq_enter(chip, desc);
pend = readl(d->virt_base + EINTPEND_REG);
mask = readl(d->virt_base + EINTMASK_REG);
pend &= ~mask;
pend &= range;
while (pend) {
unsigned int virq;
irq = __ffs(pend);
pend &= ~(1 << irq);
virq = irq_linear_revmap(data->domains[irq], irq - offset);
/* Something is really wrong if an unmapped EINT is unmasked */
BUG_ON(!virq);
generic_handle_irq(virq);
}
chained_irq_exit(chip, desc);
}
static void s3c24xx_demux_eint4_7(unsigned int irq, struct irq_desc *desc)
{
s3c24xx_demux_eint(irq, desc, 0, 0xf0);
}
static void s3c24xx_demux_eint8_23(unsigned int irq, struct irq_desc *desc)
{
s3c24xx_demux_eint(irq, desc, 8, 0xffff00);
}
static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = {
s3c2410_demux_eint0_3,
s3c2410_demux_eint0_3,
s3c2410_demux_eint0_3,
s3c2410_demux_eint0_3,
s3c24xx_demux_eint4_7,
s3c24xx_demux_eint8_23,
};
static irq_flow_handler_t s3c2412_eint_handlers[NUM_EINT_IRQ] = {
s3c2412_demux_eint0_3,
s3c2412_demux_eint0_3,
s3c2412_demux_eint0_3,
s3c2412_demux_eint0_3,
s3c24xx_demux_eint4_7,
s3c24xx_demux_eint8_23,
};
static int s3c24xx_gpf_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct s3c24xx_eint_domain_data *ddata = h->host_data;
struct samsung_pin_bank *bank = ddata->bank;
if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
return -EINVAL;
if (hw <= 3) {
if (ddata->eint0_3_parent_only)
irq_set_chip_and_handler(virq, &s3c2410_eint0_3_chip,
handle_edge_irq);
else
irq_set_chip_and_handler(virq, &s3c2412_eint0_3_chip,
handle_edge_irq);
} else {
irq_set_chip_and_handler(virq, &s3c24xx_eint_chip,
handle_edge_irq);
}
irq_set_chip_data(virq, bank);
set_irq_flags(virq, IRQF_VALID);
return 0;
}
static const struct irq_domain_ops s3c24xx_gpf_irq_ops = {
.map = s3c24xx_gpf_irq_map,
.xlate = irq_domain_xlate_twocell,
};
static int s3c24xx_gpg_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct s3c24xx_eint_domain_data *ddata = h->host_data;
struct samsung_pin_bank *bank = ddata->bank;
if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
return -EINVAL;
irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq);
irq_set_chip_data(virq, bank);
set_irq_flags(virq, IRQF_VALID);
return 0;
}
static const struct irq_domain_ops s3c24xx_gpg_irq_ops = {
.map = s3c24xx_gpg_irq_map,
.xlate = irq_domain_xlate_twocell,
};
static const struct of_device_id s3c24xx_eint_irq_ids[] = {
{ .compatible = "samsung,s3c2410-wakeup-eint", .data = (void *)1 },
{ .compatible = "samsung,s3c2412-wakeup-eint", .data = (void *)0 },
{ }
};
static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d)
{
struct device *dev = d->dev;
const struct of_device_id *match;
struct device_node *eint_np = NULL;
struct device_node *np;
struct samsung_pin_bank *bank;
struct s3c24xx_eint_data *eint_data;
const struct irq_domain_ops *ops;
unsigned int i;
bool eint0_3_parent_only;
irq_flow_handler_t *handlers;
for_each_child_of_node(dev->of_node, np) {
match = of_match_node(s3c24xx_eint_irq_ids, np);
if (match) {
eint_np = np;
eint0_3_parent_only = (bool)match->data;
break;
}
}
if (!eint_np)
return -ENODEV;
eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL);
if (!eint_data)
return -ENOMEM;
eint_data->drvdata = d;
handlers = eint0_3_parent_only ? s3c2410_eint_handlers
: s3c2412_eint_handlers;
for (i = 0; i < NUM_EINT_IRQ; ++i) {
unsigned int irq;
irq = irq_of_parse_and_map(eint_np, i);
if (!irq) {
dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
return -ENXIO;
}
eint_data->parents[i] = irq;
irq_set_chained_handler(irq, handlers[i]);
irq_set_handler_data(irq, eint_data);
}
bank = d->ctrl->pin_banks;
for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
struct s3c24xx_eint_domain_data *ddata;
unsigned int mask;
unsigned int irq;
unsigned int pin;
if (bank->eint_type != EINT_TYPE_WKUP)
continue;
ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
ddata->bank = bank;
ddata->eint_data = eint_data;
ddata->eint0_3_parent_only = eint0_3_parent_only;
ops = (bank->eint_offset == 0) ? &s3c24xx_gpf_irq_ops
: &s3c24xx_gpg_irq_ops;
bank->irq_domain = irq_domain_add_linear(bank->of_node,
bank->nr_pins, ops, ddata);
if (!bank->irq_domain) {
dev_err(dev, "wkup irq domain add failed\n");
return -ENXIO;
}
irq = bank->eint_offset;
mask = bank->eint_mask;
for (pin = 0; mask; ++pin, mask >>= 1) {
if (irq >= NUM_EINT)
break;
if (!(mask & 1))
continue;
eint_data->domains[irq] = bank->irq_domain;
++irq;
}
}
return 0;
}
static struct samsung_pin_bank s3c2412_pin_banks[] = {
PIN_BANK_A(23, 0x000, "gpa"),
PIN_BANK_2BIT(11, 0x010, "gpb"),
PIN_BANK_2BIT(16, 0x020, "gpc"),
PIN_BANK_2BIT(16, 0x030, "gpd"),
PIN_BANK_2BIT(16, 0x040, "gpe"),
PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
PIN_BANK_2BIT(11, 0x070, "gph"),
PIN_BANK_2BIT(13, 0x080, "gpj"),
};
struct samsung_pin_ctrl s3c2412_pin_ctrl[] = {
{
.pin_banks = s3c2412_pin_banks,
.nr_banks = ARRAY_SIZE(s3c2412_pin_banks),
.eint_wkup_init = s3c24xx_eint_init,
.label = "S3C2412-GPIO",
},
};
static struct samsung_pin_bank s3c2416_pin_banks[] = {
PIN_BANK_A(27, 0x000, "gpa"),
PIN_BANK_2BIT(11, 0x010, "gpb"),
PIN_BANK_2BIT(16, 0x020, "gpc"),
PIN_BANK_2BIT(16, 0x030, "gpd"),
PIN_BANK_2BIT(16, 0x040, "gpe"),
PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
PIN_BANK_2BIT_EINTW(8, 0x060, "gpg", 8, 0xff00),
PIN_BANK_2BIT(15, 0x070, "gph"),
PIN_BANK_2BIT(16, 0x0e0, "gpk"),
PIN_BANK_2BIT(14, 0x0f0, "gpl"),
PIN_BANK_2BIT(2, 0x100, "gpm"),
};
struct samsung_pin_ctrl s3c2416_pin_ctrl[] = {
{
.pin_banks = s3c2416_pin_banks,
.nr_banks = ARRAY_SIZE(s3c2416_pin_banks),
.eint_wkup_init = s3c24xx_eint_init,
.label = "S3C2416-GPIO",
},
};
static struct samsung_pin_bank s3c2440_pin_banks[] = {
PIN_BANK_A(25, 0x000, "gpa"),
PIN_BANK_2BIT(11, 0x010, "gpb"),
PIN_BANK_2BIT(16, 0x020, "gpc"),
PIN_BANK_2BIT(16, 0x030, "gpd"),
PIN_BANK_2BIT(16, 0x040, "gpe"),
PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
PIN_BANK_2BIT(11, 0x070, "gph"),
PIN_BANK_2BIT(13, 0x0d0, "gpj"),
};
struct samsung_pin_ctrl s3c2440_pin_ctrl[] = {
{
.pin_banks = s3c2440_pin_banks,
.nr_banks = ARRAY_SIZE(s3c2440_pin_banks),
.eint_wkup_init = s3c24xx_eint_init,
.label = "S3C2440-GPIO",
},
};
static struct samsung_pin_bank s3c2450_pin_banks[] = {
PIN_BANK_A(28, 0x000, "gpa"),
PIN_BANK_2BIT(11, 0x010, "gpb"),
PIN_BANK_2BIT(16, 0x020, "gpc"),
PIN_BANK_2BIT(16, 0x030, "gpd"),
PIN_BANK_2BIT(16, 0x040, "gpe"),
PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
PIN_BANK_2BIT(15, 0x070, "gph"),
PIN_BANK_2BIT(16, 0x0d0, "gpj"),
PIN_BANK_2BIT(16, 0x0e0, "gpk"),
PIN_BANK_2BIT(15, 0x0f0, "gpl"),
PIN_BANK_2BIT(2, 0x100, "gpm"),
};
struct samsung_pin_ctrl s3c2450_pin_ctrl[] = {
{
.pin_banks = s3c2450_pin_banks,
.nr_banks = ARRAY_SIZE(s3c2450_pin_banks),
.eint_wkup_init = s3c24xx_eint_init,
.label = "S3C2450-GPIO",
},
};

816
drivers/pinctrl/samsung/pinctrl-s3c64xx.c Normal file
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/*
* S3C64xx specific support for pinctrl-samsung driver.
*
* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
*
* Based on pinctrl-exynos.c, please see the file for original copyrights.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This file contains the Samsung S3C64xx specific information required by the
* the Samsung pinctrl/gpiolib driver. It also includes the implementation of
* external gpio and wakeup interrupt support.
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/of_irq.h>
#include <linux/io.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/slab.h>
#include <linux/err.h>
#include "pinctrl-samsung.h"
#define NUM_EINT0 28
#define NUM_EINT0_IRQ 4
#define EINT_MAX_PER_REG 16
#define EINT_MAX_PER_GROUP 16
/* External GPIO and wakeup interrupt related definitions */
#define SVC_GROUP_SHIFT 4
#define SVC_GROUP_MASK 0xf
#define SVC_NUM_MASK 0xf
#define SVC_GROUP(x) ((x >> SVC_GROUP_SHIFT) & \
SVC_GROUP_MASK)
#define EINT12CON_REG 0x200
#define EINT12MASK_REG 0x240
#define EINT12PEND_REG 0x260
#define EINT_OFFS(i) ((i) % (2 * EINT_MAX_PER_GROUP))
#define EINT_GROUP(i) ((i) / EINT_MAX_PER_GROUP)
#define EINT_REG(g) (4 * ((g) / 2))
#define EINTCON_REG(i) (EINT12CON_REG + EINT_REG(EINT_GROUP(i)))
#define EINTMASK_REG(i) (EINT12MASK_REG + EINT_REG(EINT_GROUP(i)))
#define EINTPEND_REG(i) (EINT12PEND_REG + EINT_REG(EINT_GROUP(i)))
#define SERVICE_REG 0x284
#define SERVICEPEND_REG 0x288
#define EINT0CON0_REG 0x900
#define EINT0MASK_REG 0x920
#define EINT0PEND_REG 0x924
/* S3C64xx specific external interrupt trigger types */
#define EINT_LEVEL_LOW 0
#define EINT_LEVEL_HIGH 1
#define EINT_EDGE_FALLING 2
#define EINT_EDGE_RISING 4
#define EINT_EDGE_BOTH 6
#define EINT_CON_MASK 0xF
#define EINT_CON_LEN 4
static struct samsung_pin_bank_type bank_type_4bit_off = {
.fld_width = { 4, 1, 2, 0, 2, 2, },
.reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
};
static struct samsung_pin_bank_type bank_type_4bit_alive = {
.fld_width = { 4, 1, 2, },
.reg_offset = { 0x00, 0x04, 0x08, },
};
static struct samsung_pin_bank_type bank_type_4bit2_off = {
.fld_width = { 4, 1, 2, 0, 2, 2, },
.reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, },
};
static struct samsung_pin_bank_type bank_type_4bit2_alive = {
.fld_width = { 4, 1, 2, },
.reg_offset = { 0x00, 0x08, 0x0c, },
};
static struct samsung_pin_bank_type bank_type_2bit_off = {
.fld_width = { 2, 1, 2, 0, 2, 2, },
.reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
};
static struct samsung_pin_bank_type bank_type_2bit_alive = {
.fld_width = { 2, 1, 2, },
.reg_offset = { 0x00, 0x04, 0x08, },
};
#define PIN_BANK_4BIT(pins, reg, id) \
{ \
.type = &bank_type_4bit_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_NONE, \
.name = id \
}
#define PIN_BANK_4BIT_EINTG(pins, reg, id, eoffs) \
{ \
.type = &bank_type_4bit_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_func = 7, \
.eint_mask = (1 << (pins)) - 1, \
.eint_offset = eoffs, \
.name = id \
}
#define PIN_BANK_4BIT_EINTW(pins, reg, id, eoffs, emask) \
{ \
.type = &bank_type_4bit_alive,\
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_func = 3, \
.eint_mask = emask, \
.eint_offset = eoffs, \
.name = id \
}
#define PIN_BANK_4BIT2_EINTG(pins, reg, id, eoffs) \
{ \
.type = &bank_type_4bit2_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_func = 7, \
.eint_mask = (1 << (pins)) - 1, \
.eint_offset = eoffs, \
.name = id \
}
#define PIN_BANK_4BIT2_EINTW(pins, reg, id, eoffs, emask) \
{ \
.type = &bank_type_4bit2_alive,\
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_func = 3, \
.eint_mask = emask, \
.eint_offset = eoffs, \
.name = id \
}
#define PIN_BANK_4BIT2_ALIVE(pins, reg, id) \
{ \
.type = &bank_type_4bit2_alive,\
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_NONE, \
.name = id \
}
#define PIN_BANK_2BIT(pins, reg, id) \
{ \
.type = &bank_type_2bit_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_NONE, \
.name = id \
}
#define PIN_BANK_2BIT_EINTG(pins, reg, id, eoffs, emask) \
{ \
.type = &bank_type_2bit_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_func = 3, \
.eint_mask = emask, \
.eint_offset = eoffs, \
.name = id \
}
#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs) \
{ \
.type = &bank_type_2bit_alive,\
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_func = 2, \
.eint_mask = (1 << (pins)) - 1, \
.eint_offset = eoffs, \
.name = id \
}
/**
* struct s3c64xx_eint0_data: EINT0 common data
* @drvdata: pin controller driver data
* @domains: IRQ domains of particular EINT0 interrupts
* @pins: pin offsets inside of banks of particular EINT0 interrupts
*/
struct s3c64xx_eint0_data {
struct samsung_pinctrl_drv_data *drvdata;
struct irq_domain *domains[NUM_EINT0];
u8 pins[NUM_EINT0];
};
/**
* struct s3c64xx_eint0_domain_data: EINT0 per-domain data
* @bank: pin bank related to the domain
* @eints: EINT0 interrupts related to the domain
*/
struct s3c64xx_eint0_domain_data {
struct samsung_pin_bank *bank;
u8 eints[];
};
/**
* struct s3c64xx_eint_gpio_data: GPIO EINT data
* @drvdata: pin controller driver data
* @domains: array of domains related to EINT interrupt groups
*/
struct s3c64xx_eint_gpio_data {
struct samsung_pinctrl_drv_data *drvdata;
struct irq_domain *domains[];
};
/*
* Common functions for S3C64xx EINT configuration
*/
static int s3c64xx_irq_get_trigger(unsigned int type)
{
int trigger;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
trigger = EINT_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
trigger = EINT_EDGE_FALLING;
break;
case IRQ_TYPE_EDGE_BOTH:
trigger = EINT_EDGE_BOTH;
break;
case IRQ_TYPE_LEVEL_HIGH:
trigger = EINT_LEVEL_HIGH;
break;
case IRQ_TYPE_LEVEL_LOW:
trigger = EINT_LEVEL_LOW;
break;
default:
return -EINVAL;
}
return trigger;
}
static void s3c64xx_irq_set_handler(unsigned int irq, unsigned int type)
{
/* Edge- and level-triggered interrupts need different handlers */
if (type & IRQ_TYPE_EDGE_BOTH)
__irq_set_handler_locked(irq, handle_edge_irq);
else
__irq_set_handler_locked(irq, handle_level_irq);
}
static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d,
struct samsung_pin_bank *bank, int pin)
{
struct samsung_pin_bank_type *bank_type = bank->type;
unsigned long flags;
void __iomem *reg;
u8 shift;
u32 mask;
u32 val;
/* Make sure that pin is configured as interrupt */
reg = d->virt_base + bank->pctl_offset;
shift = pin;
if (bank_type->fld_width[PINCFG_TYPE_FUNC] * shift >= 32) {
/* 4-bit bank type with 2 con regs */
reg += 4;
shift -= 8;
}
shift = shift * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
spin_lock_irqsave(&bank->slock, flags);
val = readl(reg);
val &= ~(mask << shift);
val |= bank->eint_func << shift;
writel(val, reg);
spin_unlock_irqrestore(&bank->slock, flags);
}
/*
* Functions for EINT GPIO configuration (EINT groups 1-9)
*/
static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset);
u32 val;
val = readl(reg);
if (mask)
val |= 1 << index;
else
val &= ~(1 << index);
writel(val, reg);
}
static void s3c64xx_gpio_irq_unmask(struct irq_data *irqd)
{
s3c64xx_gpio_irq_set_mask(irqd, false);
}
static void s3c64xx_gpio_irq_mask(struct irq_data *irqd)
{
s3c64xx_gpio_irq_set_mask(irqd, true);
}
static void s3c64xx_gpio_irq_ack(struct irq_data *irqd)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset);
writel(1 << index, reg);
}
static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
void __iomem *reg;
int trigger;
u8 shift;
u32 val;
trigger = s3c64xx_irq_get_trigger(type);
if (trigger < 0) {
pr_err("unsupported external interrupt type\n");
return -EINVAL;
}
s3c64xx_irq_set_handler(irqd->irq, type);
/* Set up interrupt trigger */
reg = d->virt_base + EINTCON_REG(bank->eint_offset);
shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
shift = 4 * (shift / 4); /* 4 EINTs per trigger selector */
val = readl(reg);
val &= ~(EINT_CON_MASK << shift);
val |= trigger << shift;
writel(val, reg);
s3c64xx_irq_set_function(d, bank, irqd->hwirq);
return 0;
}
/*
* irq_chip for gpio interrupts.
*/
static struct irq_chip s3c64xx_gpio_irq_chip = {
.name = "GPIO",
.irq_unmask = s3c64xx_gpio_irq_unmask,
.irq_mask = s3c64xx_gpio_irq_mask,
.irq_ack = s3c64xx_gpio_irq_ack,
.irq_set_type = s3c64xx_gpio_irq_set_type,
};
static int s3c64xx_gpio_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct samsung_pin_bank *bank = h->host_data;
if (!(bank->eint_mask & (1 << hw)))
return -EINVAL;
irq_set_chip_and_handler(virq,
&s3c64xx_gpio_irq_chip, handle_level_irq);
irq_set_chip_data(virq, bank);
set_irq_flags(virq, IRQF_VALID);
return 0;
}
/*
* irq domain callbacks for external gpio interrupt controller.
*/
static const struct irq_domain_ops s3c64xx_gpio_irqd_ops = {
.map = s3c64xx_gpio_irq_map,
.xlate = irq_domain_xlate_twocell,
};
static void s3c64xx_eint_gpio_irq(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_get_chip(irq);
struct s3c64xx_eint_gpio_data *data = irq_get_handler_data(irq);
struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
chained_irq_enter(chip, desc);
do {
unsigned int svc;
unsigned int group;
unsigned int pin;
unsigned int virq;
svc = readl(drvdata->virt_base + SERVICE_REG);
group = SVC_GROUP(svc);
pin = svc & SVC_NUM_MASK;
if (!group)
break;
/* Group 1 is used for two pin banks */
if (group == 1) {
if (pin < 8)
group = 0;
else
pin -= 8;
}
virq = irq_linear_revmap(data->domains[group], pin);
/*
* Something must be really wrong if an unmapped EINT
* was unmasked...
*/
BUG_ON(!virq);
generic_handle_irq(virq);
} while (1);
chained_irq_exit(chip, desc);
}
/**
* s3c64xx_eint_gpio_init() - setup handling of external gpio interrupts.
* @d: driver data of samsung pinctrl driver.
*/
static int s3c64xx_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
{
struct s3c64xx_eint_gpio_data *data;
struct samsung_pin_bank *bank;
struct device *dev = d->dev;
unsigned int nr_domains;
unsigned int i;
if (!d->irq) {
dev_err(dev, "irq number not available\n");
return -EINVAL;
}
nr_domains = 0;
bank = d->ctrl->pin_banks;
for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
unsigned int nr_eints;
unsigned int mask;
if (bank->eint_type != EINT_TYPE_GPIO)
continue;
mask = bank->eint_mask;
nr_eints = fls(mask);
bank->irq_domain = irq_domain_add_linear(bank->of_node,
nr_eints, &s3c64xx_gpio_irqd_ops, bank);
if (!bank->irq_domain) {
dev_err(dev, "gpio irq domain add failed\n");
return -ENXIO;
}
++nr_domains;
}
data = devm_kzalloc(dev, sizeof(*data)
+ nr_domains * sizeof(*data->domains), GFP_KERNEL);
if (!data) {
dev_err(dev, "failed to allocate handler data\n");
return -ENOMEM;
}
data->drvdata = d;
bank = d->ctrl->pin_banks;
nr_domains = 0;
for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
if (bank->eint_type != EINT_TYPE_GPIO)
continue;
data->domains[nr_domains++] = bank->irq_domain;
}
irq_set_chained_handler(d->irq, s3c64xx_eint_gpio_irq);
irq_set_handler_data(d->irq, data);
return 0;
}
/*
* Functions for configuration of EINT0 wake-up interrupts
*/
static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask)
{
struct s3c64xx_eint0_domain_data *ddata =
irq_data_get_irq_chip_data(irqd);
struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
u32 val;
val = readl(d->virt_base + EINT0MASK_REG);
if (mask)
val |= 1 << ddata->eints[irqd->hwirq];
else
val &= ~(1 << ddata->eints[irqd->hwirq]);
writel(val, d->virt_base + EINT0MASK_REG);
}
static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd)
{
s3c64xx_eint0_irq_set_mask(irqd, false);
}
static void s3c64xx_eint0_irq_mask(struct irq_data *irqd)
{
s3c64xx_eint0_irq_set_mask(irqd, true);
}
static void s3c64xx_eint0_irq_ack(struct irq_data *irqd)
{
struct s3c64xx_eint0_domain_data *ddata =
irq_data_get_irq_chip_data(irqd);
struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
writel(1 << ddata->eints[irqd->hwirq],
d->virt_base + EINT0PEND_REG);
}
static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)
{
struct s3c64xx_eint0_domain_data *ddata =
irq_data_get_irq_chip_data(irqd);
struct samsung_pin_bank *bank = ddata->bank;
struct samsung_pinctrl_drv_data *d = bank->drvdata;
void __iomem *reg;
int trigger;
u8 shift;
u32 val;
trigger = s3c64xx_irq_get_trigger(type);
if (trigger < 0) {
pr_err("unsupported external interrupt type\n");
return -EINVAL;
}
s3c64xx_irq_set_handler(irqd->irq, type);
/* Set up interrupt trigger */
reg = d->virt_base + EINT0CON0_REG;
shift = ddata->eints[irqd->hwirq];
if (shift >= EINT_MAX_PER_REG) {
reg += 4;
shift -= EINT_MAX_PER_REG;
}
shift = EINT_CON_LEN * (shift / 2);
val = readl(reg);
val &= ~(EINT_CON_MASK << shift);
val |= trigger << shift;
writel(val, reg);
s3c64xx_irq_set_function(d, bank, irqd->hwirq);
return 0;
}
/*
* irq_chip for wakeup interrupts
*/
static struct irq_chip s3c64xx_eint0_irq_chip = {
.name = "EINT0",
.irq_unmask = s3c64xx_eint0_irq_unmask,
.irq_mask = s3c64xx_eint0_irq_mask,
.irq_ack = s3c64xx_eint0_irq_ack,
.irq_set_type = s3c64xx_eint0_irq_set_type,
};
static inline void s3c64xx_irq_demux_eint(unsigned int irq,
struct irq_desc *desc, u32 range)
{
struct irq_chip *chip = irq_get_chip(irq);
struct s3c64xx_eint0_data *data = irq_get_handler_data(irq);
struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
unsigned int pend, mask;
chained_irq_enter(chip, desc);
pend = readl(drvdata->virt_base + EINT0PEND_REG);
mask = readl(drvdata->virt_base + EINT0MASK_REG);
pend = pend & range & ~mask;
pend &= range;
while (pend) {
unsigned int virq;
irq = fls(pend) - 1;
pend &= ~(1 << irq);
virq = irq_linear_revmap(data->domains[irq], data->pins[irq]);
/*
* Something must be really wrong if an unmapped EINT
* was unmasked...
*/
BUG_ON(!virq);
generic_handle_irq(virq);
}
chained_irq_exit(chip, desc);
}
static void s3c64xx_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
{
s3c64xx_irq_demux_eint(irq, desc, 0xf);
}
static void s3c64xx_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
{
s3c64xx_irq_demux_eint(irq, desc, 0xff0);
}
static void s3c64xx_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
{
s3c64xx_irq_demux_eint(irq, desc, 0xff000);
}
static void s3c64xx_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
{
s3c64xx_irq_demux_eint(irq, desc, 0xff00000);
}
static irq_flow_handler_t s3c64xx_eint0_handlers[NUM_EINT0_IRQ] = {
s3c64xx_demux_eint0_3,
s3c64xx_demux_eint4_11,
s3c64xx_demux_eint12_19,
s3c64xx_demux_eint20_27,
};
static int s3c64xx_eint0_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct s3c64xx_eint0_domain_data *ddata = h->host_data;
struct samsung_pin_bank *bank = ddata->bank;
if (!(bank->eint_mask & (1 << hw)))
return -EINVAL;
irq_set_chip_and_handler(virq,
&s3c64xx_eint0_irq_chip, handle_level_irq);
irq_set_chip_data(virq, ddata);
set_irq_flags(virq, IRQF_VALID);
return 0;
}
/*
* irq domain callbacks for external wakeup interrupt controller.
*/
static const struct irq_domain_ops s3c64xx_eint0_irqd_ops = {
.map = s3c64xx_eint0_irq_map,
.xlate = irq_domain_xlate_twocell,
};
/* list of external wakeup controllers supported */
static const struct of_device_id s3c64xx_eint0_irq_ids[] = {
{ .compatible = "samsung,s3c64xx-wakeup-eint", },
{ }
};
/**
* s3c64xx_eint_eint0_init() - setup handling of external wakeup interrupts.
* @d: driver data of samsung pinctrl driver.
*/
static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d)
{
struct device *dev = d->dev;
struct device_node *eint0_np = NULL;
struct device_node *np;
struct samsung_pin_bank *bank;
struct s3c64xx_eint0_data *data;
unsigned int i;
for_each_child_of_node(dev->of_node, np) {
if (of_match_node(s3c64xx_eint0_irq_ids, np)) {
eint0_np = np;
break;
}
}
if (!eint0_np)
return -ENODEV;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data) {
dev_err(dev, "could not allocate memory for wkup eint data\n");
return -ENOMEM;
}
data->drvdata = d;
for (i = 0; i < NUM_EINT0_IRQ; ++i) {
unsigned int irq;
irq = irq_of_parse_and_map(eint0_np, i);
if (!irq) {
dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
return -ENXIO;
}
irq_set_chained_handler(irq, s3c64xx_eint0_handlers[i]);
irq_set_handler_data(irq, data);
}
bank = d->ctrl->pin_banks;
for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
struct s3c64xx_eint0_domain_data *ddata;
unsigned int nr_eints;
unsigned int mask;
unsigned int irq;
unsigned int pin;
if (bank->eint_type != EINT_TYPE_WKUP)
continue;
mask = bank->eint_mask;
nr_eints = fls(mask);
ddata = devm_kzalloc(dev,
sizeof(*ddata) + nr_eints, GFP_KERNEL);
if (!ddata) {
dev_err(dev, "failed to allocate domain data\n");
return -ENOMEM;
}
ddata->bank = bank;
bank->irq_domain = irq_domain_add_linear(bank->of_node,
nr_eints, &s3c64xx_eint0_irqd_ops, ddata);
if (!bank->irq_domain) {
dev_err(dev, "wkup irq domain add failed\n");
return -ENXIO;
}
irq = bank->eint_offset;
mask = bank->eint_mask;
for (pin = 0; mask; ++pin, mask >>= 1) {
if (!(mask & 1))
continue;
data->domains[irq] = bank->irq_domain;
data->pins[irq] = pin;
ddata->eints[pin] = irq;
++irq;
}
}
return 0;
}
/* pin banks of s3c64xx pin-controller 0 */
static struct samsung_pin_bank s3c64xx_pin_banks0[] = {
PIN_BANK_4BIT_EINTG(8, 0x000, "gpa", 0),
PIN_BANK_4BIT_EINTG(7, 0x020, "gpb", 8),
PIN_BANK_4BIT_EINTG(8, 0x040, "gpc", 16),
PIN_BANK_4BIT_EINTG(5, 0x060, "gpd", 32),
PIN_BANK_4BIT(5, 0x080, "gpe"),
PIN_BANK_2BIT_EINTG(16, 0x0a0, "gpf", 48, 0x3fff),
PIN_BANK_4BIT_EINTG(7, 0x0c0, "gpg", 64),
PIN_BANK_4BIT2_EINTG(10, 0x0e0, "gph", 80),
PIN_BANK_2BIT(16, 0x100, "gpi"),
PIN_BANK_2BIT(12, 0x120, "gpj"),
PIN_BANK_4BIT2_ALIVE(16, 0x800, "gpk"),
PIN_BANK_4BIT2_EINTW(15, 0x810, "gpl", 16, 0x7f00),
PIN_BANK_4BIT_EINTW(6, 0x820, "gpm", 23, 0x1f),
PIN_BANK_2BIT_EINTW(16, 0x830, "gpn", 0),
PIN_BANK_2BIT_EINTG(16, 0x140, "gpo", 96, 0xffff),
PIN_BANK_2BIT_EINTG(15, 0x160, "gpp", 112, 0x7fff),
PIN_BANK_2BIT_EINTG(9, 0x180, "gpq", 128, 0x1ff),
};
/*
* Samsung pinctrl driver data for S3C64xx SoC. S3C64xx SoC includes
* one gpio/pin-mux/pinconfig controller.
*/
struct samsung_pin_ctrl s3c64xx_pin_ctrl[] = {
{
/* pin-controller instance 1 data */
.pin_banks = s3c64xx_pin_banks0,
.nr_banks = ARRAY_SIZE(s3c64xx_pin_banks0),
.eint_gpio_init = s3c64xx_eint_gpio_init,
.eint_wkup_init = s3c64xx_eint_eint0_init,
.label = "S3C64xx-GPIO",
},
};

1939
drivers/pinctrl/samsung/pinctrl-samsung.c Normal file
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262
drivers/pinctrl/samsung/pinctrl-samsung.h Normal file
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/*
* pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2012 Linaro Ltd
* http://www.linaro.org
*
* Author: Thomas Abraham <thomas.ab@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __PINCTRL_SAMSUNG_H
#define __PINCTRL_SAMSUNG_H
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <linux/gpio.h>
/* pinmux function number for pin as gpio output line */
#define FUNC_INPUT 0x0
#define FUNC_OUTPUT 0x1
/**
* enum pincfg_type - possible pin configuration types supported.
* @PINCFG_TYPE_FUNC: Function configuration.
* @PINCFG_TYPE_DAT: Pin value configuration.
* @PINCFG_TYPE_PUD: Pull up/down configuration.
* @PINCFG_TYPE_DRV: Drive strength configuration.
* @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
* @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.
*/
enum pincfg_type {
PINCFG_TYPE_FUNC,
PINCFG_TYPE_DAT,
PINCFG_TYPE_PUD,
PINCFG_TYPE_DRV,
PINCFG_TYPE_CON_PDN,
PINCFG_TYPE_PUD_PDN,
PINCFG_TYPE_NUM
};
/*
* pin configuration (pull up/down and drive strength) type and its value are
* packed together into a 16-bits. The upper 8-bits represent the configuration
* type and the lower 8-bits hold the value of the configuration type.
*/
#define PINCFG_TYPE_MASK 0xFF
#define PINCFG_VALUE_SHIFT 8
#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
PINCFG_VALUE_SHIFT)
/**
* enum eint_type - possible external interrupt types.
* @EINT_TYPE_NONE: bank does not support external interrupts
* @EINT_TYPE_GPIO: bank supportes external gpio interrupts
* @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
* @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
*
* Samsung GPIO controller groups all the available pins into banks. The pins
* in a pin bank can support external gpio interrupts or external wakeup
* interrupts or no interrupts at all. From a software perspective, the only
* difference between external gpio and external wakeup interrupts is that
* the wakeup interrupts can additionally wakeup the system if it is in
* suspended state.
*/
enum eint_type {
EINT_TYPE_NONE,
EINT_TYPE_GPIO,
EINT_TYPE_WKUP,
EINT_TYPE_WKUP_MUX,
};
/* maximum length of a pin in pin descriptor (example: "gpa0-0") */
#define PIN_NAME_LENGTH 10
#define PIN_GROUP(n, p, f) \
{ \
.name = n, \
.pins = p, \
.num_pins = ARRAY_SIZE(p), \
.func = f \
}
#define PMX_FUNC(n, g) \
{ \
.name = n, \
.groups = g, \
.num_groups = ARRAY_SIZE(g), \
}
struct samsung_pinctrl_drv_data;
/**
* struct samsung_pin_bank_type: pin bank type description
* @fld_width: widths of configuration bitfields (0 if unavailable)
* @reg_offset: offsets of configuration registers (don't care of width is 0)
*/
struct samsung_pin_bank_type {
u8 fld_width[PINCFG_TYPE_NUM];
u8 reg_offset[PINCFG_TYPE_NUM];
};
/**
* struct samsung_pin_bank: represent a controller pin-bank.
* @type: type of the bank (register offsets and bitfield widths)
* @pctl_offset: starting offset of the pin-bank registers.
* @pin_base: starting pin number of the bank.
* @nr_pins: number of pins included in this bank.
* @eint_func: function to set in CON register to configure pin as EINT.
* @eint_type: type of the external interrupt supported by the bank.
* @eint_mask: bit mask of pins which support EINT function.
* @name: name to be prefixed for each pin in this pin bank.
* @of_node: OF node of the bank.
* @drvdata: link to controller driver data
* @irq_domain: IRQ domain of the bank.
* @gpio_chip: GPIO chip of the bank.
* @grange: linux gpio pin range supported by this bank.
* @slock: spinlock protecting bank registers
* @pm_save: saved register values during suspend
*/
struct samsung_pin_bank {
struct samsung_pin_bank_type *type;
u32 pctl_offset;
u32 pin_base;
u8 nr_pins;
u8 eint_func;
enum eint_type eint_type;
u32 eint_mask;
u32 eint_offset;
char *name;
void *soc_priv;
struct device_node *of_node;
struct samsung_pinctrl_drv_data *drvdata;
struct irq_domain *irq_domain;
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range grange;
spinlock_t slock;
u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
};
/**
* struct samsung_pin_ctrl: represent a pin controller.
* @pin_banks: list of pin banks included in this controller.
* @nr_banks: number of pin banks.
* @weint_fltcon: offset of the ext-wakeup filter controller registers.
* @base: starting system wide pin number.
* @nr_pins: number of pins supported by the controller.
* @eint_gpio_init: platform specific callback to setup the external gpio
* interrupts for the controller.
* @eint_wkup_init: platform specific callback to setup the external wakeup
* interrupts for the controller.
* @label: for debug information.
*/
struct samsung_pin_ctrl {
struct samsung_pin_bank *pin_banks;
u32 nr_banks;
u32 base;
u32 nr_pins;
u32 weint_fltcon;
int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
void (*suspend)(struct samsung_pinctrl_drv_data *);
void (*resume)(struct samsung_pinctrl_drv_data *);
char *label;
struct pinctrl *pinctrl;
struct pinctrl_state *pins_default;
struct pinctrl_state *pins_sleep;
};
/**
* struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
* @node: global list node
* @virt_base: register base address of the controller.
* @dev: device instance representing the controller.
* @irq: interrpt number used by the controller to notify gpio interrupts.
* @ctrl: pin controller instance managed by the driver.
* @pctl: pin controller descriptor registered with the pinctrl subsystem.
* @pctl_dev: cookie representing pinctrl device instance.
* @pin_groups: list of pin groups available to the driver.
* @nr_groups: number of such pin groups.
* @pmx_functions: list of pin functions available to the driver.
* @nr_function: number of such pin functions.
*/
struct samsung_pinctrl_drv_data {
struct list_head node;
void __iomem *virt_base;
struct device *dev;
int irq;
struct samsung_pin_ctrl *ctrl;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
const struct samsung_pin_group *pin_groups;
unsigned int nr_groups;
const struct samsung_pmx_func *pmx_functions;
unsigned int nr_functions;
};
/**
* struct samsung_pin_group: represent group of pins of a pinmux function.
* @name: name of the pin group, used to lookup the group.
* @pins: the pins included in this group.
* @num_pins: number of pins included in this group.
* @func: the function number to be programmed when selected.
*/
struct samsung_pin_group {
const char *name;
const unsigned int *pins;
u8 num_pins;
u8 func;
};
/**
* struct samsung_pmx_func: represent a pin function.
* @name: name of the pin function, used to lookup the function.
* @groups: one or more names of pin groups that provide this function.
* @num_groups: number of groups included in @groups.
*/
struct samsung_pmx_func {
const char *name;
const char **groups;
u8 num_groups;
u32 val;
};
/* list of all exported SoC specific data */
extern struct samsung_pin_ctrl exynos3250_pin_ctrl[];
extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
extern struct samsung_pin_ctrl exynos5260_pin_ctrl[];
extern struct samsung_pin_ctrl exynos5420_pin_ctrl[];
extern struct samsung_pin_ctrl exynos7570_pin_ctrl[];
extern struct samsung_pin_ctrl exynos7870_pin_ctrl[];
extern struct samsung_pin_ctrl exynos8890_pin_ctrl[];
extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
extern struct samsung_pin_ctrl s3c2412_pin_ctrl[];
extern struct samsung_pin_ctrl s3c2416_pin_ctrl[];
extern struct samsung_pin_ctrl s3c2440_pin_ctrl[];
extern struct samsung_pin_ctrl s3c2450_pin_ctrl[];
extern struct samsung_pin_ctrl s5pv210_pin_ctrl[];
#endif /* __PINCTRL_SAMSUNG_H */

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drivers/pinctrl/samsung/secgpio_dvs.c Normal file
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/*
* Samsung Mobile VE Group.
*
* drivers/gpio/secgpio_dvs.c
*
* Drivers for samsung gpio debugging & verification.
*
* Copyright (C) 2013, Samsung Electronics.
*
* This program is free software. You can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include "secgpio_dvs.h"
/*sys fs*/
struct class *secgpio_dvs_class;
EXPORT_SYMBOL(secgpio_dvs_class);
struct device *secgpio_dotest;
EXPORT_SYMBOL(secgpio_dotest);
/* extern GPIOMAP_RESULT GpioMap_result; */
static struct gpio_dvs_t *gdvs_info;
static ssize_t checked_init_secgpio_file_read(
struct device *dev, struct device_attribute *attr, char *buf);
static ssize_t checked_sleep_secgpio_file_read(
struct device *dev, struct device_attribute *attr, char *buf);
static ssize_t checked_secgpio_init_read_details(
struct device *dev, struct device_attribute *attr, char *buf);
static ssize_t checked_secgpio_sleep_read_details(
struct device *dev, struct device_attribute *attr, char *buf);
static ssize_t secgpio_checked_sleepgpio_read(
struct device *dev, struct device_attribute *attr, char *buf);
static DEVICE_ATTR(gpioinit_check, 0660,
checked_init_secgpio_file_read, NULL);
static DEVICE_ATTR(gpiosleep_check, 0660,
checked_sleep_secgpio_file_read, NULL);
static DEVICE_ATTR(check_init_detail, 0660,
checked_secgpio_init_read_details, NULL);
static DEVICE_ATTR(check_sleep_detail, 0660,
checked_secgpio_sleep_read_details, NULL);
static DEVICE_ATTR(checked_sleepGPIO, 0660,
secgpio_checked_sleepgpio_read, NULL);
static struct attribute *secgpio_dvs_attributes[] = {
&dev_attr_gpioinit_check.attr,
&dev_attr_gpiosleep_check.attr,
&dev_attr_check_init_detail.attr,
&dev_attr_check_sleep_detail.attr,
&dev_attr_checked_sleepGPIO.attr,
NULL,
};
static struct attribute_group secgpio_dvs_attr_group = {
.attrs = secgpio_dvs_attributes,
};
static ssize_t checked_init_secgpio_file_read(
struct device *dev, struct device_attribute *attr, char *buf)
{
int i = 0;
char temp_buf[20];
struct gpio_dvs_t *gdvs = dev_get_drvdata(dev);
for (i = 0; i < gdvs->count; i++) {
memset(temp_buf, 0, sizeof(char)*20);
snprintf(temp_buf, 20, "%x ", gdvs->result->init[i]);
strlcat(buf, temp_buf, PAGE_SIZE);
}
return strlen(buf);
}
static ssize_t checked_sleep_secgpio_file_read(
struct device *dev, struct device_attribute *attr, char *buf)
{
int i = 0;
char temp_buf[20];
struct gpio_dvs_t *gdvs = dev_get_drvdata(dev);
for (i = 0; i < gdvs->count; i++) {
memset(temp_buf, 0, sizeof(char)*20);
snprintf(temp_buf, 20, "%x ", gdvs->result->sleep[i]);
strlcat(buf, temp_buf, PAGE_SIZE);
}
return strlen(buf);
}
static ssize_t checked_secgpio_init_read_details(
struct device *dev, struct device_attribute *attr, char *buf)
{
int i = 0;
char temp_buf[20];
struct gpio_dvs_t *gdvs = dev_get_drvdata(dev);
for (i = 0; i < gdvs->count; i++) {
memset(temp_buf, 0, sizeof(char)*20);
snprintf(temp_buf, 20, "GI[%d] - %x\n ",
i, gdvs->result->init[i]);
strlcat(buf, temp_buf, PAGE_SIZE);
}
return strlen(buf);
}
static ssize_t checked_secgpio_sleep_read_details(
struct device *dev, struct device_attribute *attr, char *buf)
{
int i = 0;
char temp_buf[20];
struct gpio_dvs_t *gdvs = dev_get_drvdata(dev);
for (i = 0; i < gdvs->count; i++) {
memset(temp_buf, 0, sizeof(char)*20);
snprintf(temp_buf, 20, "GS[%d] - %x\n ",
i, gdvs->result->sleep[i]);
strlcat(buf, temp_buf, PAGE_SIZE);
}
return strlen(buf);
}
static ssize_t secgpio_checked_sleepgpio_read(
struct device *dev, struct device_attribute *attr, char *buf)
{
struct gpio_dvs_t *gdvs = dev_get_drvdata(dev);
if (gdvs->check_sleep)
return snprintf(buf, PAGE_SIZE, "1");
else
return snprintf(buf, PAGE_SIZE, "0");
}
void gpio_dvs_check_initgpio(void)
{
if (gdvs_info && gdvs_info->check_gpio_status) {
gdvs_info->check_gpio_status(PHONE_INIT);
}
}
void gpio_dvs_check_sleepgpio(void)
{
if (unlikely(!gdvs_info->check_sleep) && gdvs_info) {
// if (gdvs_info && gdvs_info->check_gpio_status) {
gdvs_info->check_gpio_status(PHONE_SLEEP);
gdvs_info->check_sleep = true;
}
}
#ifdef CONFIG_OF
static const struct of_device_id secgpio_dvs_dt_match[] = {
{ .compatible = "samsung,exynos7570-secgpio-dvs",
.data = (void *)&exynos7570_secgpio_dvs },
{ },
};
MODULE_DEVICE_TABLE(of, secgpio_dvs_dt_match);
static struct gpio_dvs_t *secgpio_dvs_get_soc_data(struct platform_device *pdev)
{
const struct of_device_id *match;
struct device_node *node = pdev->dev.of_node;
struct gpio_dvs_t *gdvs;
match = of_match_node(secgpio_dvs_dt_match, node);
if (!match) {
dev_err(&pdev->dev, "failed to get SoC node\n");
return NULL;
}
gdvs = (struct gpio_dvs_t *)match->data;
if (!gdvs) {
dev_err(&pdev->dev, "failed to get SoC data\n");
return NULL;
}
return gdvs;
}
#else
static struct gpio_dvs_t *secgpio_dvs_get_soc_data(struct platform_device *pdev)
{
return dev_get_platdata(&pdev->dev);
}
#endif
static int secgpio_dvs_probe(struct platform_device *pdev)
{
int ret = 0;
struct class *secgpio_dvs_class;
struct device *secgpio_dotest;
struct gpio_dvs_t *gdvs = secgpio_dvs_get_soc_data(pdev);
if (!gdvs)
return -ENODEV;
gdvs->count = gdvs->get_nr_gpio();
pr_info("[GPIO_DVS] gpio nr:%d\n", gdvs->count);
gdvs->result->init = devm_kzalloc(&pdev->dev, gdvs->count, GFP_KERNEL);
if (!gdvs->result->init)
return -ENOMEM;
gdvs->result->sleep = devm_kzalloc(&pdev->dev, gdvs->count, GFP_KERNEL);
if (!gdvs->result->sleep)
return -ENOMEM;
secgpio_dvs_class = class_create(THIS_MODULE, "secgpio_check");
if (IS_ERR(secgpio_dvs_class)) {
ret = PTR_ERR(secgpio_dvs_class);
pr_err("Failed to create class(secgpio_check_all)");
goto fail_out;
}
secgpio_dotest = device_create(secgpio_dvs_class,
NULL, 0, NULL, "secgpio_check_all");
if (IS_ERR(secgpio_dotest)) {
ret = PTR_ERR(secgpio_dotest);
pr_err("Failed to create device(secgpio_check_all)");
goto fail_device_create;
}
dev_set_drvdata(secgpio_dotest, gdvs);
gdvs_info = gdvs;
ret = sysfs_create_group(&secgpio_dotest->kobj,
&secgpio_dvs_attr_group);
if (ret) {
pr_err("Failed to create sysfs group");
goto fail_create_group;
}
return 0;
fail_create_group:
device_unregister(secgpio_dotest);
fail_device_create:
class_destroy(secgpio_dvs_class);
fail_out:
if (ret)
pr_err("%s: (err = %d)!\n", __func__, ret);
return ret;
}
static int secgpio_dvs_remove(struct platform_device *pdev)
{
return 0;
}
static struct platform_driver secgpio_dvs = {
.driver = {
.name = "secgpio_dvs",
.owner = THIS_MODULE,
#ifdef CONFIG_OF
.of_match_table = of_match_ptr(secgpio_dvs_dt_match),
#endif
},
.probe = secgpio_dvs_probe,
.remove = secgpio_dvs_remove,
};
module_platform_driver(secgpio_dvs);
MODULE_AUTHOR("intae.jun@samsung.com");
MODULE_DESCRIPTION("GPIO debugging and verification");
MODULE_LICENSE("GPL");

35
drivers/pinctrl/samsung/secgpio_dvs.h Normal file
View file

@ -0,0 +1,35 @@
/*
* secgpio_dvs.h -- Samsung GPIO debugging and verification system
*/
#ifndef __SECGPIO_DVS_H
#define __SECGPIO_DVS_H
#include <linux/types.h>
enum gdvs_phone_status {
PHONE_INIT = 0,
PHONE_SLEEP,
GDVS_PHONE_STATUS_MAX
};
struct gpiomap_result_t {
unsigned char *init;
unsigned char *sleep;
};
struct gpio_dvs_t {
struct gpiomap_result_t *result;
unsigned int count;
bool check_sleep;
void (*check_gpio_status)(unsigned char phonestate);
int (*get_nr_gpio)(void);
};
void gpio_dvs_check_initgpio(void);
void gpio_dvs_check_sleepgpio(void);
/* list of all exported SoC specific data */
extern struct gpio_dvs_t exynos7570_secgpio_dvs;
extern int exynos7570_secgpio_get_nr_gpio(void);
#endif /* __SECGPIO_DVS_H */