mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-28 23:08:52 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
24
drivers/rapidio/switches/Kconfig
Normal file
24
drivers/rapidio/switches/Kconfig
Normal file
|
|
@ -0,0 +1,24 @@
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#
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# RapidIO switches configuration
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#
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config RAPIDIO_TSI57X
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tristate "IDT Tsi57x SRIO switches support"
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---help---
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Includes support for IDT Tsi57x family of serial RapidIO switches.
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config RAPIDIO_CPS_XX
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tristate "IDT CPS-xx SRIO switches support"
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---help---
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Includes support for IDT CPS-16/12/10/8 serial RapidIO switches.
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config RAPIDIO_TSI568
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tristate "Tsi568 SRIO switch support"
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default n
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---help---
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Includes support for IDT Tsi568 serial RapidIO switch.
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config RAPIDIO_CPS_GEN2
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tristate "IDT CPS Gen.2 SRIO switch support"
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default n
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---help---
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Includes support for ITD CPS Gen.2 serial RapidIO switches.
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8
drivers/rapidio/switches/Makefile
Normal file
8
drivers/rapidio/switches/Makefile
Normal file
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@ -0,0 +1,8 @@
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#
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# Makefile for RIO switches
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#
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obj-$(CONFIG_RAPIDIO_TSI57X) += tsi57x.o
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obj-$(CONFIG_RAPIDIO_CPS_XX) += idtcps.o
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obj-$(CONFIG_RAPIDIO_TSI568) += tsi568.o
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obj-$(CONFIG_RAPIDIO_CPS_GEN2) += idt_gen2.o
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495
drivers/rapidio/switches/idt_gen2.c
Normal file
495
drivers/rapidio/switches/idt_gen2.c
Normal file
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@ -0,0 +1,495 @@
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|||
/*
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* IDT CPS Gen.2 Serial RapidIO switch family support
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*
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* Copyright 2010 Integrated Device Technology, Inc.
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* Alexandre Bounine <alexandre.bounine@idt.com>
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*
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stat.h>
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#include <linux/module.h>
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#include <linux/rio.h>
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#include <linux/rio_drv.h>
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#include <linux/rio_ids.h>
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#include <linux/delay.h>
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#include <asm/page.h>
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#include "../rio.h"
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#define LOCAL_RTE_CONF_DESTID_SEL 0x010070
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#define LOCAL_RTE_CONF_DESTID_SEL_PSEL 0x0000001f
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#define IDT_LT_ERR_REPORT_EN 0x03100c
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|
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#define IDT_PORT_ERR_REPORT_EN(n) (0x031044 + (n)*0x40)
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#define IDT_PORT_ERR_REPORT_EN_BC 0x03ff04
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#define IDT_PORT_ISERR_REPORT_EN(n) (0x03104C + (n)*0x40)
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#define IDT_PORT_ISERR_REPORT_EN_BC 0x03ff0c
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#define IDT_PORT_INIT_TX_ACQUIRED 0x00000020
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#define IDT_LANE_ERR_REPORT_EN(n) (0x038010 + (n)*0x100)
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#define IDT_LANE_ERR_REPORT_EN_BC 0x03ff10
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|
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#define IDT_DEV_CTRL_1 0xf2000c
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#define IDT_DEV_CTRL_1_GENPW 0x02000000
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#define IDT_DEV_CTRL_1_PRSTBEH 0x00000001
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|
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#define IDT_CFGBLK_ERR_CAPTURE_EN 0x020008
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#define IDT_CFGBLK_ERR_REPORT 0xf20014
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#define IDT_CFGBLK_ERR_REPORT_GENPW 0x00000002
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|
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#define IDT_AUX_PORT_ERR_CAP_EN 0x020000
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#define IDT_AUX_ERR_REPORT_EN 0xf20018
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#define IDT_AUX_PORT_ERR_LOG_I2C 0x00000002
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#define IDT_AUX_PORT_ERR_LOG_JTAG 0x00000001
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|
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#define IDT_ISLTL_ADDRESS_CAP 0x021014
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#define IDT_RIO_DOMAIN 0xf20020
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#define IDT_RIO_DOMAIN_MASK 0x000000ff
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#define IDT_PW_INFO_CSR 0xf20024
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#define IDT_SOFT_RESET 0xf20040
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#define IDT_SOFT_RESET_REQ 0x00030097
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|
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#define IDT_I2C_MCTRL 0xf20050
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#define IDT_I2C_MCTRL_GENPW 0x04000000
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#define IDT_JTAG_CTRL 0xf2005c
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#define IDT_JTAG_CTRL_GENPW 0x00000002
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#define IDT_LANE_CTRL(n) (0xff8000 + (n)*0x100)
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#define IDT_LANE_CTRL_BC 0xffff00
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#define IDT_LANE_CTRL_GENPW 0x00200000
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#define IDT_LANE_DFE_1_BC 0xffff18
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#define IDT_LANE_DFE_2_BC 0xffff1c
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#define IDT_PORT_OPS(n) (0xf40004 + (n)*0x100)
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#define IDT_PORT_OPS_GENPW 0x08000000
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#define IDT_PORT_OPS_PL_ELOG 0x00000040
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#define IDT_PORT_OPS_LL_ELOG 0x00000020
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#define IDT_PORT_OPS_LT_ELOG 0x00000010
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#define IDT_PORT_OPS_BC 0xf4ff04
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#define IDT_PORT_ISERR_DET(n) (0xf40008 + (n)*0x100)
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#define IDT_ERR_CAP 0xfd0000
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#define IDT_ERR_CAP_LOG_OVERWR 0x00000004
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#define IDT_ERR_RD 0xfd0004
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#define IDT_DEFAULT_ROUTE 0xde
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#define IDT_NO_ROUTE 0xdf
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static int
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idtg2_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
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u16 table, u16 route_destid, u8 route_port)
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{
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/*
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* Select routing table to update
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*/
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if (table == RIO_GLOBAL_TABLE)
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table = 0;
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else
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table++;
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if (route_port == RIO_INVALID_ROUTE)
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route_port = IDT_DEFAULT_ROUTE;
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rio_mport_write_config_32(mport, destid, hopcount,
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LOCAL_RTE_CONF_DESTID_SEL, table);
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/*
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* Program destination port for the specified destID
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*/
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rio_mport_write_config_32(mport, destid, hopcount,
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RIO_STD_RTE_CONF_DESTID_SEL_CSR,
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(u32)route_destid);
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rio_mport_write_config_32(mport, destid, hopcount,
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RIO_STD_RTE_CONF_PORT_SEL_CSR,
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(u32)route_port);
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udelay(10);
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return 0;
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}
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static int
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idtg2_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
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u16 table, u16 route_destid, u8 *route_port)
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{
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u32 result;
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/*
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* Select routing table to read
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*/
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if (table == RIO_GLOBAL_TABLE)
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table = 0;
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else
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table++;
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rio_mport_write_config_32(mport, destid, hopcount,
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LOCAL_RTE_CONF_DESTID_SEL, table);
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rio_mport_write_config_32(mport, destid, hopcount,
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RIO_STD_RTE_CONF_DESTID_SEL_CSR,
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route_destid);
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rio_mport_read_config_32(mport, destid, hopcount,
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RIO_STD_RTE_CONF_PORT_SEL_CSR, &result);
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|
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if (IDT_DEFAULT_ROUTE == (u8)result || IDT_NO_ROUTE == (u8)result)
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*route_port = RIO_INVALID_ROUTE;
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else
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*route_port = (u8)result;
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return 0;
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}
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static int
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idtg2_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
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u16 table)
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{
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u32 i;
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/*
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* Select routing table to read
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*/
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if (table == RIO_GLOBAL_TABLE)
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table = 0;
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else
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table++;
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rio_mport_write_config_32(mport, destid, hopcount,
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LOCAL_RTE_CONF_DESTID_SEL, table);
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for (i = RIO_STD_RTE_CONF_EXTCFGEN;
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i <= (RIO_STD_RTE_CONF_EXTCFGEN | 0xff);) {
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rio_mport_write_config_32(mport, destid, hopcount,
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RIO_STD_RTE_CONF_DESTID_SEL_CSR, i);
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rio_mport_write_config_32(mport, destid, hopcount,
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RIO_STD_RTE_CONF_PORT_SEL_CSR,
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(IDT_DEFAULT_ROUTE << 24) | (IDT_DEFAULT_ROUTE << 16) |
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(IDT_DEFAULT_ROUTE << 8) | IDT_DEFAULT_ROUTE);
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i += 4;
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}
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return 0;
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}
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static int
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idtg2_set_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
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u8 sw_domain)
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{
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/*
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* Switch domain configuration operates only at global level
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*/
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rio_mport_write_config_32(mport, destid, hopcount,
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IDT_RIO_DOMAIN, (u32)sw_domain);
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return 0;
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}
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static int
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idtg2_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
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u8 *sw_domain)
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{
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u32 regval;
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/*
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* Switch domain configuration operates only at global level
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*/
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rio_mport_read_config_32(mport, destid, hopcount,
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IDT_RIO_DOMAIN, ®val);
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*sw_domain = (u8)(regval & 0xff);
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return 0;
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}
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static int
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idtg2_em_init(struct rio_dev *rdev)
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{
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u32 regval;
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int i, tmp;
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|
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/*
|
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* This routine performs device-specific initialization only.
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* All standard EM configuration should be performed at upper level.
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*/
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pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount);
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/* Set Port-Write info CSR: PRIO=3 and CRF=1 */
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rio_write_config_32(rdev, IDT_PW_INFO_CSR, 0x0000e000);
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|
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/*
|
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* Configure LT LAYER error reporting.
|
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*/
|
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|
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/* Enable standard (RIO.p8) error reporting */
|
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rio_write_config_32(rdev, IDT_LT_ERR_REPORT_EN,
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REM_LTL_ERR_ILLTRAN | REM_LTL_ERR_UNSOLR |
|
||||
REM_LTL_ERR_UNSUPTR);
|
||||
|
||||
/* Use Port-Writes for LT layer error reporting.
|
||||
* Enable per-port reset
|
||||
*/
|
||||
rio_read_config_32(rdev, IDT_DEV_CTRL_1, ®val);
|
||||
rio_write_config_32(rdev, IDT_DEV_CTRL_1,
|
||||
regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH);
|
||||
|
||||
/*
|
||||
* Configure PORT error reporting.
|
||||
*/
|
||||
|
||||
/* Report all RIO.p8 errors supported by device */
|
||||
rio_write_config_32(rdev, IDT_PORT_ERR_REPORT_EN_BC, 0x807e8037);
|
||||
|
||||
/* Configure reporting of implementation specific errors/events */
|
||||
rio_write_config_32(rdev, IDT_PORT_ISERR_REPORT_EN_BC,
|
||||
IDT_PORT_INIT_TX_ACQUIRED);
|
||||
|
||||
/* Use Port-Writes for port error reporting and enable error logging */
|
||||
tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo);
|
||||
for (i = 0; i < tmp; i++) {
|
||||
rio_read_config_32(rdev, IDT_PORT_OPS(i), ®val);
|
||||
rio_write_config_32(rdev,
|
||||
IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW |
|
||||
IDT_PORT_OPS_PL_ELOG |
|
||||
IDT_PORT_OPS_LL_ELOG |
|
||||
IDT_PORT_OPS_LT_ELOG);
|
||||
}
|
||||
/* Overwrite error log if full */
|
||||
rio_write_config_32(rdev, IDT_ERR_CAP, IDT_ERR_CAP_LOG_OVERWR);
|
||||
|
||||
/*
|
||||
* Configure LANE error reporting.
|
||||
*/
|
||||
|
||||
/* Disable line error reporting */
|
||||
rio_write_config_32(rdev, IDT_LANE_ERR_REPORT_EN_BC, 0);
|
||||
|
||||
/* Use Port-Writes for lane error reporting (when enabled)
|
||||
* (do per-lane update because lanes may have different configuration)
|
||||
*/
|
||||
tmp = (rdev->did == RIO_DID_IDTCPS1848) ? 48 : 16;
|
||||
for (i = 0; i < tmp; i++) {
|
||||
rio_read_config_32(rdev, IDT_LANE_CTRL(i), ®val);
|
||||
rio_write_config_32(rdev, IDT_LANE_CTRL(i),
|
||||
regval | IDT_LANE_CTRL_GENPW);
|
||||
}
|
||||
|
||||
/*
|
||||
* Configure AUX error reporting.
|
||||
*/
|
||||
|
||||
/* Disable JTAG and I2C Error capture */
|
||||
rio_write_config_32(rdev, IDT_AUX_PORT_ERR_CAP_EN, 0);
|
||||
|
||||
/* Disable JTAG and I2C Error reporting/logging */
|
||||
rio_write_config_32(rdev, IDT_AUX_ERR_REPORT_EN, 0);
|
||||
|
||||
/* Disable Port-Write notification from JTAG */
|
||||
rio_write_config_32(rdev, IDT_JTAG_CTRL, 0);
|
||||
|
||||
/* Disable Port-Write notification from I2C */
|
||||
rio_read_config_32(rdev, IDT_I2C_MCTRL, ®val);
|
||||
rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW);
|
||||
|
||||
/*
|
||||
* Configure CFG_BLK error reporting.
|
||||
*/
|
||||
|
||||
/* Disable Configuration Block error capture */
|
||||
rio_write_config_32(rdev, IDT_CFGBLK_ERR_CAPTURE_EN, 0);
|
||||
|
||||
/* Disable Port-Writes for Configuration Block error reporting */
|
||||
rio_read_config_32(rdev, IDT_CFGBLK_ERR_REPORT, ®val);
|
||||
rio_write_config_32(rdev, IDT_CFGBLK_ERR_REPORT,
|
||||
regval & ~IDT_CFGBLK_ERR_REPORT_GENPW);
|
||||
|
||||
/* set TVAL = ~50us */
|
||||
rio_write_config_32(rdev,
|
||||
rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
idtg2_em_handler(struct rio_dev *rdev, u8 portnum)
|
||||
{
|
||||
u32 regval, em_perrdet, em_ltlerrdet;
|
||||
|
||||
rio_read_config_32(rdev,
|
||||
rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet);
|
||||
if (em_ltlerrdet) {
|
||||
/* Service Logical/Transport Layer Error(s) */
|
||||
if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) {
|
||||
/* Implementation specific error reported */
|
||||
rio_read_config_32(rdev,
|
||||
IDT_ISLTL_ADDRESS_CAP, ®val);
|
||||
|
||||
pr_debug("RIO: %s Implementation Specific LTL errors" \
|
||||
" 0x%x @(0x%x)\n",
|
||||
rio_name(rdev), em_ltlerrdet, regval);
|
||||
|
||||
/* Clear implementation specific address capture CSR */
|
||||
rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
rio_read_config_32(rdev,
|
||||
rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet);
|
||||
if (em_perrdet) {
|
||||
/* Service Port-Level Error(s) */
|
||||
if (em_perrdet & REM_PED_IMPL_SPEC) {
|
||||
/* Implementation Specific port error reported */
|
||||
|
||||
/* Get IS errors reported */
|
||||
rio_read_config_32(rdev,
|
||||
IDT_PORT_ISERR_DET(portnum), ®val);
|
||||
|
||||
pr_debug("RIO: %s Implementation Specific Port" \
|
||||
" errors 0x%x\n", rio_name(rdev), regval);
|
||||
|
||||
/* Clear all implementation specific events */
|
||||
rio_write_config_32(rdev,
|
||||
IDT_PORT_ISERR_DET(portnum), 0);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static ssize_t
|
||||
idtg2_show_errlog(struct device *dev, struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct rio_dev *rdev = to_rio_dev(dev);
|
||||
ssize_t len = 0;
|
||||
u32 regval;
|
||||
|
||||
while (!rio_read_config_32(rdev, IDT_ERR_RD, ®val)) {
|
||||
if (!regval) /* 0 = end of log */
|
||||
break;
|
||||
len += snprintf(buf + len, PAGE_SIZE - len,
|
||||
"%08x\n", regval);
|
||||
if (len >= (PAGE_SIZE - 10))
|
||||
break;
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(errlog, S_IRUGO, idtg2_show_errlog, NULL);
|
||||
|
||||
static int idtg2_sysfs(struct rio_dev *rdev, bool create)
|
||||
{
|
||||
struct device *dev = &rdev->dev;
|
||||
int err = 0;
|
||||
|
||||
if (create) {
|
||||
/* Initialize sysfs entries */
|
||||
err = device_create_file(dev, &dev_attr_errlog);
|
||||
if (err)
|
||||
dev_err(dev, "Unable create sysfs errlog file\n");
|
||||
} else
|
||||
device_remove_file(dev, &dev_attr_errlog);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static struct rio_switch_ops idtg2_switch_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.add_entry = idtg2_route_add_entry,
|
||||
.get_entry = idtg2_route_get_entry,
|
||||
.clr_table = idtg2_route_clr_table,
|
||||
.set_domain = idtg2_set_domain,
|
||||
.get_domain = idtg2_get_domain,
|
||||
.em_init = idtg2_em_init,
|
||||
.em_handle = idtg2_em_handler,
|
||||
};
|
||||
|
||||
static int idtg2_probe(struct rio_dev *rdev, const struct rio_device_id *id)
|
||||
{
|
||||
pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
|
||||
|
||||
spin_lock(&rdev->rswitch->lock);
|
||||
|
||||
if (rdev->rswitch->ops) {
|
||||
spin_unlock(&rdev->rswitch->lock);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
rdev->rswitch->ops = &idtg2_switch_ops;
|
||||
|
||||
if (rdev->do_enum) {
|
||||
/* Ensure that default routing is disabled on startup */
|
||||
rio_write_config_32(rdev,
|
||||
RIO_STD_RTE_DEFAULT_PORT, IDT_NO_ROUTE);
|
||||
}
|
||||
|
||||
/* Create device-specific sysfs attributes */
|
||||
idtg2_sysfs(rdev, true);
|
||||
|
||||
spin_unlock(&rdev->rswitch->lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void idtg2_remove(struct rio_dev *rdev)
|
||||
{
|
||||
pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
|
||||
spin_lock(&rdev->rswitch->lock);
|
||||
if (rdev->rswitch->ops != &idtg2_switch_ops) {
|
||||
spin_unlock(&rdev->rswitch->lock);
|
||||
return;
|
||||
}
|
||||
rdev->rswitch->ops = NULL;
|
||||
|
||||
/* Remove device-specific sysfs attributes */
|
||||
idtg2_sysfs(rdev, false);
|
||||
|
||||
spin_unlock(&rdev->rswitch->lock);
|
||||
}
|
||||
|
||||
static struct rio_device_id idtg2_id_table[] = {
|
||||
{RIO_DEVICE(RIO_DID_IDTCPS1848, RIO_VID_IDT)},
|
||||
{RIO_DEVICE(RIO_DID_IDTCPS1616, RIO_VID_IDT)},
|
||||
{RIO_DEVICE(RIO_DID_IDTVPS1616, RIO_VID_IDT)},
|
||||
{RIO_DEVICE(RIO_DID_IDTSPS1616, RIO_VID_IDT)},
|
||||
{RIO_DEVICE(RIO_DID_IDTCPS1432, RIO_VID_IDT)},
|
||||
{ 0, } /* terminate list */
|
||||
};
|
||||
|
||||
static struct rio_driver idtg2_driver = {
|
||||
.name = "idt_gen2",
|
||||
.id_table = idtg2_id_table,
|
||||
.probe = idtg2_probe,
|
||||
.remove = idtg2_remove,
|
||||
};
|
||||
|
||||
static int __init idtg2_init(void)
|
||||
{
|
||||
return rio_register_driver(&idtg2_driver);
|
||||
}
|
||||
|
||||
static void __exit idtg2_exit(void)
|
||||
{
|
||||
pr_debug("RIO: %s\n", __func__);
|
||||
rio_unregister_driver(&idtg2_driver);
|
||||
pr_debug("RIO: %s done\n", __func__);
|
||||
}
|
||||
|
||||
device_initcall(idtg2_init);
|
||||
module_exit(idtg2_exit);
|
||||
|
||||
MODULE_DESCRIPTION("IDT CPS Gen.2 Serial RapidIO switch family driver");
|
||||
MODULE_AUTHOR("Integrated Device Technology, Inc.");
|
||||
MODULE_LICENSE("GPL");
|
||||
203
drivers/rapidio/switches/idtcps.c
Normal file
203
drivers/rapidio/switches/idtcps.c
Normal file
|
|
@ -0,0 +1,203 @@
|
|||
/*
|
||||
* IDT CPS RapidIO switches support
|
||||
*
|
||||
* Copyright 2009-2010 Integrated Device Technology, Inc.
|
||||
* Alexandre Bounine <alexandre.bounine@idt.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/rio.h>
|
||||
#include <linux/rio_drv.h>
|
||||
#include <linux/rio_ids.h>
|
||||
#include <linux/module.h>
|
||||
#include "../rio.h"
|
||||
|
||||
#define CPS_DEFAULT_ROUTE 0xde
|
||||
#define CPS_NO_ROUTE 0xdf
|
||||
|
||||
#define IDTCPS_RIO_DOMAIN 0xf20020
|
||||
|
||||
static int
|
||||
idtcps_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
|
||||
u16 table, u16 route_destid, u8 route_port)
|
||||
{
|
||||
u32 result;
|
||||
|
||||
if (route_port == RIO_INVALID_ROUTE)
|
||||
route_port = CPS_DEFAULT_ROUTE;
|
||||
|
||||
if (table == RIO_GLOBAL_TABLE) {
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
RIO_STD_RTE_CONF_DESTID_SEL_CSR, route_destid);
|
||||
|
||||
rio_mport_read_config_32(mport, destid, hopcount,
|
||||
RIO_STD_RTE_CONF_PORT_SEL_CSR, &result);
|
||||
|
||||
result = (0xffffff00 & result) | (u32)route_port;
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
RIO_STD_RTE_CONF_PORT_SEL_CSR, result);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
idtcps_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
|
||||
u16 table, u16 route_destid, u8 *route_port)
|
||||
{
|
||||
u32 result;
|
||||
|
||||
if (table == RIO_GLOBAL_TABLE) {
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
RIO_STD_RTE_CONF_DESTID_SEL_CSR, route_destid);
|
||||
|
||||
rio_mport_read_config_32(mport, destid, hopcount,
|
||||
RIO_STD_RTE_CONF_PORT_SEL_CSR, &result);
|
||||
|
||||
if (CPS_DEFAULT_ROUTE == (u8)result ||
|
||||
CPS_NO_ROUTE == (u8)result)
|
||||
*route_port = RIO_INVALID_ROUTE;
|
||||
else
|
||||
*route_port = (u8)result;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
idtcps_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
|
||||
u16 table)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
if (table == RIO_GLOBAL_TABLE) {
|
||||
for (i = 0x80000000; i <= 0x800000ff;) {
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
RIO_STD_RTE_CONF_DESTID_SEL_CSR, i);
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
RIO_STD_RTE_CONF_PORT_SEL_CSR,
|
||||
(CPS_DEFAULT_ROUTE << 24) |
|
||||
(CPS_DEFAULT_ROUTE << 16) |
|
||||
(CPS_DEFAULT_ROUTE << 8) | CPS_DEFAULT_ROUTE);
|
||||
i += 4;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
idtcps_set_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
|
||||
u8 sw_domain)
|
||||
{
|
||||
/*
|
||||
* Switch domain configuration operates only at global level
|
||||
*/
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
IDTCPS_RIO_DOMAIN, (u32)sw_domain);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
idtcps_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
|
||||
u8 *sw_domain)
|
||||
{
|
||||
u32 regval;
|
||||
|
||||
/*
|
||||
* Switch domain configuration operates only at global level
|
||||
*/
|
||||
rio_mport_read_config_32(mport, destid, hopcount,
|
||||
IDTCPS_RIO_DOMAIN, ®val);
|
||||
|
||||
*sw_domain = (u8)(regval & 0xff);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct rio_switch_ops idtcps_switch_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.add_entry = idtcps_route_add_entry,
|
||||
.get_entry = idtcps_route_get_entry,
|
||||
.clr_table = idtcps_route_clr_table,
|
||||
.set_domain = idtcps_set_domain,
|
||||
.get_domain = idtcps_get_domain,
|
||||
.em_init = NULL,
|
||||
.em_handle = NULL,
|
||||
};
|
||||
|
||||
static int idtcps_probe(struct rio_dev *rdev, const struct rio_device_id *id)
|
||||
{
|
||||
pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
|
||||
|
||||
spin_lock(&rdev->rswitch->lock);
|
||||
|
||||
if (rdev->rswitch->ops) {
|
||||
spin_unlock(&rdev->rswitch->lock);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
rdev->rswitch->ops = &idtcps_switch_ops;
|
||||
|
||||
if (rdev->do_enum) {
|
||||
/* set TVAL = ~50us */
|
||||
rio_write_config_32(rdev,
|
||||
rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8);
|
||||
/* Ensure that default routing is disabled on startup */
|
||||
rio_write_config_32(rdev,
|
||||
RIO_STD_RTE_DEFAULT_PORT, CPS_NO_ROUTE);
|
||||
}
|
||||
|
||||
spin_unlock(&rdev->rswitch->lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void idtcps_remove(struct rio_dev *rdev)
|
||||
{
|
||||
pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
|
||||
spin_lock(&rdev->rswitch->lock);
|
||||
if (rdev->rswitch->ops != &idtcps_switch_ops) {
|
||||
spin_unlock(&rdev->rswitch->lock);
|
||||
return;
|
||||
}
|
||||
rdev->rswitch->ops = NULL;
|
||||
spin_unlock(&rdev->rswitch->lock);
|
||||
}
|
||||
|
||||
static struct rio_device_id idtcps_id_table[] = {
|
||||
{RIO_DEVICE(RIO_DID_IDTCPS6Q, RIO_VID_IDT)},
|
||||
{RIO_DEVICE(RIO_DID_IDTCPS8, RIO_VID_IDT)},
|
||||
{RIO_DEVICE(RIO_DID_IDTCPS10Q, RIO_VID_IDT)},
|
||||
{RIO_DEVICE(RIO_DID_IDTCPS12, RIO_VID_IDT)},
|
||||
{RIO_DEVICE(RIO_DID_IDTCPS16, RIO_VID_IDT)},
|
||||
{RIO_DEVICE(RIO_DID_IDT70K200, RIO_VID_IDT)},
|
||||
{ 0, } /* terminate list */
|
||||
};
|
||||
|
||||
static struct rio_driver idtcps_driver = {
|
||||
.name = "idtcps",
|
||||
.id_table = idtcps_id_table,
|
||||
.probe = idtcps_probe,
|
||||
.remove = idtcps_remove,
|
||||
};
|
||||
|
||||
static int __init idtcps_init(void)
|
||||
{
|
||||
return rio_register_driver(&idtcps_driver);
|
||||
}
|
||||
|
||||
static void __exit idtcps_exit(void)
|
||||
{
|
||||
rio_unregister_driver(&idtcps_driver);
|
||||
}
|
||||
|
||||
device_initcall(idtcps_init);
|
||||
module_exit(idtcps_exit);
|
||||
|
||||
MODULE_DESCRIPTION("IDT CPS Gen.1 Serial RapidIO switch family driver");
|
||||
MODULE_AUTHOR("Integrated Device Technology, Inc.");
|
||||
MODULE_LICENSE("GPL");
|
||||
199
drivers/rapidio/switches/tsi568.c
Normal file
199
drivers/rapidio/switches/tsi568.c
Normal file
|
|
@ -0,0 +1,199 @@
|
|||
/*
|
||||
* RapidIO Tsi568 switch support
|
||||
*
|
||||
* Copyright 2009-2010 Integrated Device Technology, Inc.
|
||||
* Alexandre Bounine <alexandre.bounine@idt.com>
|
||||
* - Added EM support
|
||||
* - Modified switch operations initialization.
|
||||
*
|
||||
* Copyright 2005 MontaVista Software, Inc.
|
||||
* Matt Porter <mporter@kernel.crashing.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/rio.h>
|
||||
#include <linux/rio_drv.h>
|
||||
#include <linux/rio_ids.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/module.h>
|
||||
#include "../rio.h"
|
||||
|
||||
/* Global (broadcast) route registers */
|
||||
#define SPBC_ROUTE_CFG_DESTID 0x10070
|
||||
#define SPBC_ROUTE_CFG_PORT 0x10074
|
||||
|
||||
/* Per port route registers */
|
||||
#define SPP_ROUTE_CFG_DESTID(n) (0x11070 + 0x100*n)
|
||||
#define SPP_ROUTE_CFG_PORT(n) (0x11074 + 0x100*n)
|
||||
|
||||
#define TSI568_SP_MODE(n) (0x11004 + 0x100*n)
|
||||
#define TSI568_SP_MODE_PW_DIS 0x08000000
|
||||
|
||||
static int
|
||||
tsi568_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
|
||||
u16 table, u16 route_destid, u8 route_port)
|
||||
{
|
||||
if (table == RIO_GLOBAL_TABLE) {
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPBC_ROUTE_CFG_DESTID, route_destid);
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPBC_ROUTE_CFG_PORT, route_port);
|
||||
} else {
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPP_ROUTE_CFG_DESTID(table),
|
||||
route_destid);
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPP_ROUTE_CFG_PORT(table), route_port);
|
||||
}
|
||||
|
||||
udelay(10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
tsi568_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
|
||||
u16 table, u16 route_destid, u8 *route_port)
|
||||
{
|
||||
int ret = 0;
|
||||
u32 result;
|
||||
|
||||
if (table == RIO_GLOBAL_TABLE) {
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPBC_ROUTE_CFG_DESTID, route_destid);
|
||||
rio_mport_read_config_32(mport, destid, hopcount,
|
||||
SPBC_ROUTE_CFG_PORT, &result);
|
||||
} else {
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPP_ROUTE_CFG_DESTID(table),
|
||||
route_destid);
|
||||
rio_mport_read_config_32(mport, destid, hopcount,
|
||||
SPP_ROUTE_CFG_PORT(table), &result);
|
||||
}
|
||||
|
||||
*route_port = result;
|
||||
if (*route_port > 15)
|
||||
ret = -1;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
tsi568_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
|
||||
u16 table)
|
||||
{
|
||||
u32 route_idx;
|
||||
u32 lut_size;
|
||||
|
||||
lut_size = (mport->sys_size) ? 0x1ff : 0xff;
|
||||
|
||||
if (table == RIO_GLOBAL_TABLE) {
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPBC_ROUTE_CFG_DESTID, 0x80000000);
|
||||
for (route_idx = 0; route_idx <= lut_size; route_idx++)
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPBC_ROUTE_CFG_PORT,
|
||||
RIO_INVALID_ROUTE);
|
||||
} else {
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPP_ROUTE_CFG_DESTID(table),
|
||||
0x80000000);
|
||||
for (route_idx = 0; route_idx <= lut_size; route_idx++)
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPP_ROUTE_CFG_PORT(table),
|
||||
RIO_INVALID_ROUTE);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
tsi568_em_init(struct rio_dev *rdev)
|
||||
{
|
||||
u32 regval;
|
||||
int portnum;
|
||||
|
||||
pr_debug("TSI568 %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount);
|
||||
|
||||
/* Make sure that Port-Writes are disabled (for all ports) */
|
||||
for (portnum = 0;
|
||||
portnum < RIO_GET_TOTAL_PORTS(rdev->swpinfo); portnum++) {
|
||||
rio_read_config_32(rdev, TSI568_SP_MODE(portnum), ®val);
|
||||
rio_write_config_32(rdev, TSI568_SP_MODE(portnum),
|
||||
regval | TSI568_SP_MODE_PW_DIS);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct rio_switch_ops tsi568_switch_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.add_entry = tsi568_route_add_entry,
|
||||
.get_entry = tsi568_route_get_entry,
|
||||
.clr_table = tsi568_route_clr_table,
|
||||
.set_domain = NULL,
|
||||
.get_domain = NULL,
|
||||
.em_init = tsi568_em_init,
|
||||
.em_handle = NULL,
|
||||
};
|
||||
|
||||
static int tsi568_probe(struct rio_dev *rdev, const struct rio_device_id *id)
|
||||
{
|
||||
pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
|
||||
|
||||
spin_lock(&rdev->rswitch->lock);
|
||||
|
||||
if (rdev->rswitch->ops) {
|
||||
spin_unlock(&rdev->rswitch->lock);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
rdev->rswitch->ops = &tsi568_switch_ops;
|
||||
spin_unlock(&rdev->rswitch->lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tsi568_remove(struct rio_dev *rdev)
|
||||
{
|
||||
pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
|
||||
spin_lock(&rdev->rswitch->lock);
|
||||
if (rdev->rswitch->ops != &tsi568_switch_ops) {
|
||||
spin_unlock(&rdev->rswitch->lock);
|
||||
return;
|
||||
}
|
||||
rdev->rswitch->ops = NULL;
|
||||
spin_unlock(&rdev->rswitch->lock);
|
||||
}
|
||||
|
||||
static struct rio_device_id tsi568_id_table[] = {
|
||||
{RIO_DEVICE(RIO_DID_TSI568, RIO_VID_TUNDRA)},
|
||||
{ 0, } /* terminate list */
|
||||
};
|
||||
|
||||
static struct rio_driver tsi568_driver = {
|
||||
.name = "tsi568",
|
||||
.id_table = tsi568_id_table,
|
||||
.probe = tsi568_probe,
|
||||
.remove = tsi568_remove,
|
||||
};
|
||||
|
||||
static int __init tsi568_init(void)
|
||||
{
|
||||
return rio_register_driver(&tsi568_driver);
|
||||
}
|
||||
|
||||
static void __exit tsi568_exit(void)
|
||||
{
|
||||
rio_unregister_driver(&tsi568_driver);
|
||||
}
|
||||
|
||||
device_initcall(tsi568_init);
|
||||
module_exit(tsi568_exit);
|
||||
|
||||
MODULE_DESCRIPTION("IDT Tsi568 Serial RapidIO switch driver");
|
||||
MODULE_AUTHOR("Integrated Device Technology, Inc.");
|
||||
MODULE_LICENSE("GPL");
|
||||
371
drivers/rapidio/switches/tsi57x.c
Normal file
371
drivers/rapidio/switches/tsi57x.c
Normal file
|
|
@ -0,0 +1,371 @@
|
|||
/*
|
||||
* RapidIO Tsi57x switch family support
|
||||
*
|
||||
* Copyright 2009-2010 Integrated Device Technology, Inc.
|
||||
* Alexandre Bounine <alexandre.bounine@idt.com>
|
||||
* - Added EM support
|
||||
* - Modified switch operations initialization.
|
||||
*
|
||||
* Copyright 2005 MontaVista Software, Inc.
|
||||
* Matt Porter <mporter@kernel.crashing.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/rio.h>
|
||||
#include <linux/rio_drv.h>
|
||||
#include <linux/rio_ids.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/module.h>
|
||||
#include "../rio.h"
|
||||
|
||||
/* Global (broadcast) route registers */
|
||||
#define SPBC_ROUTE_CFG_DESTID 0x10070
|
||||
#define SPBC_ROUTE_CFG_PORT 0x10074
|
||||
|
||||
/* Per port route registers */
|
||||
#define SPP_ROUTE_CFG_DESTID(n) (0x11070 + 0x100*n)
|
||||
#define SPP_ROUTE_CFG_PORT(n) (0x11074 + 0x100*n)
|
||||
|
||||
#define TSI578_SP_MODE(n) (0x11004 + n*0x100)
|
||||
#define TSI578_SP_MODE_GLBL 0x10004
|
||||
#define TSI578_SP_MODE_PW_DIS 0x08000000
|
||||
#define TSI578_SP_MODE_LUT_512 0x01000000
|
||||
|
||||
#define TSI578_SP_CTL_INDEP(n) (0x13004 + n*0x100)
|
||||
#define TSI578_SP_LUT_PEINF(n) (0x13010 + n*0x100)
|
||||
#define TSI578_SP_CS_TX(n) (0x13014 + n*0x100)
|
||||
#define TSI578_SP_INT_STATUS(n) (0x13018 + n*0x100)
|
||||
|
||||
#define TSI578_GLBL_ROUTE_BASE 0x10078
|
||||
|
||||
static int
|
||||
tsi57x_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
|
||||
u16 table, u16 route_destid, u8 route_port)
|
||||
{
|
||||
if (table == RIO_GLOBAL_TABLE) {
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPBC_ROUTE_CFG_DESTID, route_destid);
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPBC_ROUTE_CFG_PORT, route_port);
|
||||
} else {
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPP_ROUTE_CFG_DESTID(table), route_destid);
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPP_ROUTE_CFG_PORT(table), route_port);
|
||||
}
|
||||
|
||||
udelay(10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
tsi57x_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
|
||||
u16 table, u16 route_destid, u8 *route_port)
|
||||
{
|
||||
int ret = 0;
|
||||
u32 result;
|
||||
|
||||
if (table == RIO_GLOBAL_TABLE) {
|
||||
/* Use local RT of the ingress port to avoid possible
|
||||
race condition */
|
||||
rio_mport_read_config_32(mport, destid, hopcount,
|
||||
RIO_SWP_INFO_CAR, &result);
|
||||
table = (result & RIO_SWP_INFO_PORT_NUM_MASK);
|
||||
}
|
||||
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPP_ROUTE_CFG_DESTID(table), route_destid);
|
||||
rio_mport_read_config_32(mport, destid, hopcount,
|
||||
SPP_ROUTE_CFG_PORT(table), &result);
|
||||
|
||||
*route_port = (u8)result;
|
||||
if (*route_port > 15)
|
||||
ret = -1;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
tsi57x_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
|
||||
u16 table)
|
||||
{
|
||||
u32 route_idx;
|
||||
u32 lut_size;
|
||||
|
||||
lut_size = (mport->sys_size) ? 0x1ff : 0xff;
|
||||
|
||||
if (table == RIO_GLOBAL_TABLE) {
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPBC_ROUTE_CFG_DESTID, 0x80000000);
|
||||
for (route_idx = 0; route_idx <= lut_size; route_idx++)
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPBC_ROUTE_CFG_PORT,
|
||||
RIO_INVALID_ROUTE);
|
||||
} else {
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPP_ROUTE_CFG_DESTID(table), 0x80000000);
|
||||
for (route_idx = 0; route_idx <= lut_size; route_idx++)
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
SPP_ROUTE_CFG_PORT(table) , RIO_INVALID_ROUTE);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
tsi57x_set_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
|
||||
u8 sw_domain)
|
||||
{
|
||||
u32 regval;
|
||||
|
||||
/*
|
||||
* Switch domain configuration operates only at global level
|
||||
*/
|
||||
|
||||
/* Turn off flat (LUT_512) mode */
|
||||
rio_mport_read_config_32(mport, destid, hopcount,
|
||||
TSI578_SP_MODE_GLBL, ®val);
|
||||
rio_mport_write_config_32(mport, destid, hopcount, TSI578_SP_MODE_GLBL,
|
||||
regval & ~TSI578_SP_MODE_LUT_512);
|
||||
/* Set switch domain base */
|
||||
rio_mport_write_config_32(mport, destid, hopcount,
|
||||
TSI578_GLBL_ROUTE_BASE,
|
||||
(u32)(sw_domain << 24));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
tsi57x_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
|
||||
u8 *sw_domain)
|
||||
{
|
||||
u32 regval;
|
||||
|
||||
/*
|
||||
* Switch domain configuration operates only at global level
|
||||
*/
|
||||
rio_mport_read_config_32(mport, destid, hopcount,
|
||||
TSI578_GLBL_ROUTE_BASE, ®val);
|
||||
|
||||
*sw_domain = (u8)(regval >> 24);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
tsi57x_em_init(struct rio_dev *rdev)
|
||||
{
|
||||
u32 regval;
|
||||
int portnum;
|
||||
|
||||
pr_debug("TSI578 %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount);
|
||||
|
||||
for (portnum = 0;
|
||||
portnum < RIO_GET_TOTAL_PORTS(rdev->swpinfo); portnum++) {
|
||||
/* Make sure that Port-Writes are enabled (for all ports) */
|
||||
rio_read_config_32(rdev,
|
||||
TSI578_SP_MODE(portnum), ®val);
|
||||
rio_write_config_32(rdev,
|
||||
TSI578_SP_MODE(portnum),
|
||||
regval & ~TSI578_SP_MODE_PW_DIS);
|
||||
|
||||
/* Clear all pending interrupts */
|
||||
rio_read_config_32(rdev,
|
||||
rdev->phys_efptr +
|
||||
RIO_PORT_N_ERR_STS_CSR(portnum),
|
||||
®val);
|
||||
rio_write_config_32(rdev,
|
||||
rdev->phys_efptr +
|
||||
RIO_PORT_N_ERR_STS_CSR(portnum),
|
||||
regval & 0x07120214);
|
||||
|
||||
rio_read_config_32(rdev,
|
||||
TSI578_SP_INT_STATUS(portnum), ®val);
|
||||
rio_write_config_32(rdev,
|
||||
TSI578_SP_INT_STATUS(portnum),
|
||||
regval & 0x000700bd);
|
||||
|
||||
/* Enable all interrupts to allow ports to send a port-write */
|
||||
rio_read_config_32(rdev,
|
||||
TSI578_SP_CTL_INDEP(portnum), ®val);
|
||||
rio_write_config_32(rdev,
|
||||
TSI578_SP_CTL_INDEP(portnum),
|
||||
regval | 0x000b0000);
|
||||
|
||||
/* Skip next (odd) port if the current port is in x4 mode */
|
||||
rio_read_config_32(rdev,
|
||||
rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
|
||||
®val);
|
||||
if ((regval & RIO_PORT_N_CTL_PWIDTH) == RIO_PORT_N_CTL_PWIDTH_4)
|
||||
portnum++;
|
||||
}
|
||||
|
||||
/* set TVAL = ~50us */
|
||||
rio_write_config_32(rdev,
|
||||
rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x9a << 8);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
tsi57x_em_handler(struct rio_dev *rdev, u8 portnum)
|
||||
{
|
||||
struct rio_mport *mport = rdev->net->hport;
|
||||
u32 intstat, err_status;
|
||||
int sendcount, checkcount;
|
||||
u8 route_port;
|
||||
u32 regval;
|
||||
|
||||
rio_read_config_32(rdev,
|
||||
rdev->phys_efptr + RIO_PORT_N_ERR_STS_CSR(portnum),
|
||||
&err_status);
|
||||
|
||||
if ((err_status & RIO_PORT_N_ERR_STS_PORT_OK) &&
|
||||
(err_status & (RIO_PORT_N_ERR_STS_PW_OUT_ES |
|
||||
RIO_PORT_N_ERR_STS_PW_INP_ES))) {
|
||||
/* Remove any queued packets by locking/unlocking port */
|
||||
rio_read_config_32(rdev,
|
||||
rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
|
||||
®val);
|
||||
if (!(regval & RIO_PORT_N_CTL_LOCKOUT)) {
|
||||
rio_write_config_32(rdev,
|
||||
rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
|
||||
regval | RIO_PORT_N_CTL_LOCKOUT);
|
||||
udelay(50);
|
||||
rio_write_config_32(rdev,
|
||||
rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
|
||||
regval);
|
||||
}
|
||||
|
||||
/* Read from link maintenance response register to clear
|
||||
* valid bit
|
||||
*/
|
||||
rio_read_config_32(rdev,
|
||||
rdev->phys_efptr + RIO_PORT_N_MNT_RSP_CSR(portnum),
|
||||
®val);
|
||||
|
||||
/* Send a Packet-Not-Accepted/Link-Request-Input-Status control
|
||||
* symbol to recover from IES/OES
|
||||
*/
|
||||
sendcount = 3;
|
||||
while (sendcount) {
|
||||
rio_write_config_32(rdev,
|
||||
TSI578_SP_CS_TX(portnum), 0x40fc8000);
|
||||
checkcount = 3;
|
||||
while (checkcount--) {
|
||||
udelay(50);
|
||||
rio_read_config_32(rdev,
|
||||
rdev->phys_efptr +
|
||||
RIO_PORT_N_MNT_RSP_CSR(portnum),
|
||||
®val);
|
||||
if (regval & RIO_PORT_N_MNT_RSP_RVAL)
|
||||
goto exit_es;
|
||||
}
|
||||
|
||||
sendcount--;
|
||||
}
|
||||
}
|
||||
|
||||
exit_es:
|
||||
/* Clear implementation specific error status bits */
|
||||
rio_read_config_32(rdev, TSI578_SP_INT_STATUS(portnum), &intstat);
|
||||
pr_debug("TSI578[%x:%x] SP%d_INT_STATUS=0x%08x\n",
|
||||
rdev->destid, rdev->hopcount, portnum, intstat);
|
||||
|
||||
if (intstat & 0x10000) {
|
||||
rio_read_config_32(rdev,
|
||||
TSI578_SP_LUT_PEINF(portnum), ®val);
|
||||
regval = (mport->sys_size) ? (regval >> 16) : (regval >> 24);
|
||||
route_port = rdev->rswitch->route_table[regval];
|
||||
pr_debug("RIO: TSI578[%s] P%d LUT Parity Error (destID=%d)\n",
|
||||
rio_name(rdev), portnum, regval);
|
||||
tsi57x_route_add_entry(mport, rdev->destid, rdev->hopcount,
|
||||
RIO_GLOBAL_TABLE, regval, route_port);
|
||||
}
|
||||
|
||||
rio_write_config_32(rdev, TSI578_SP_INT_STATUS(portnum),
|
||||
intstat & 0x000700bd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct rio_switch_ops tsi57x_switch_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.add_entry = tsi57x_route_add_entry,
|
||||
.get_entry = tsi57x_route_get_entry,
|
||||
.clr_table = tsi57x_route_clr_table,
|
||||
.set_domain = tsi57x_set_domain,
|
||||
.get_domain = tsi57x_get_domain,
|
||||
.em_init = tsi57x_em_init,
|
||||
.em_handle = tsi57x_em_handler,
|
||||
};
|
||||
|
||||
static int tsi57x_probe(struct rio_dev *rdev, const struct rio_device_id *id)
|
||||
{
|
||||
pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
|
||||
|
||||
spin_lock(&rdev->rswitch->lock);
|
||||
|
||||
if (rdev->rswitch->ops) {
|
||||
spin_unlock(&rdev->rswitch->lock);
|
||||
return -EINVAL;
|
||||
}
|
||||
rdev->rswitch->ops = &tsi57x_switch_ops;
|
||||
|
||||
if (rdev->do_enum) {
|
||||
/* Ensure that default routing is disabled on startup */
|
||||
rio_write_config_32(rdev, RIO_STD_RTE_DEFAULT_PORT,
|
||||
RIO_INVALID_ROUTE);
|
||||
}
|
||||
|
||||
spin_unlock(&rdev->rswitch->lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tsi57x_remove(struct rio_dev *rdev)
|
||||
{
|
||||
pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
|
||||
spin_lock(&rdev->rswitch->lock);
|
||||
if (rdev->rswitch->ops != &tsi57x_switch_ops) {
|
||||
spin_unlock(&rdev->rswitch->lock);
|
||||
return;
|
||||
}
|
||||
rdev->rswitch->ops = NULL;
|
||||
spin_unlock(&rdev->rswitch->lock);
|
||||
}
|
||||
|
||||
static struct rio_device_id tsi57x_id_table[] = {
|
||||
{RIO_DEVICE(RIO_DID_TSI572, RIO_VID_TUNDRA)},
|
||||
{RIO_DEVICE(RIO_DID_TSI574, RIO_VID_TUNDRA)},
|
||||
{RIO_DEVICE(RIO_DID_TSI577, RIO_VID_TUNDRA)},
|
||||
{RIO_DEVICE(RIO_DID_TSI578, RIO_VID_TUNDRA)},
|
||||
{ 0, } /* terminate list */
|
||||
};
|
||||
|
||||
static struct rio_driver tsi57x_driver = {
|
||||
.name = "tsi57x",
|
||||
.id_table = tsi57x_id_table,
|
||||
.probe = tsi57x_probe,
|
||||
.remove = tsi57x_remove,
|
||||
};
|
||||
|
||||
static int __init tsi57x_init(void)
|
||||
{
|
||||
return rio_register_driver(&tsi57x_driver);
|
||||
}
|
||||
|
||||
static void __exit tsi57x_exit(void)
|
||||
{
|
||||
rio_unregister_driver(&tsi57x_driver);
|
||||
}
|
||||
|
||||
device_initcall(tsi57x_init);
|
||||
module_exit(tsi57x_exit);
|
||||
|
||||
MODULE_DESCRIPTION("IDT Tsi57x Serial RapidIO switch family driver");
|
||||
MODULE_AUTHOR("Integrated Device Technology, Inc.");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Add table
Add a link
Reference in a new issue