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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
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/*
3w-9xxx.h -- 3ware 9000 Storage Controller device driver for Linux.
Written By: Adam Radford <linuxraid@lsi.com>
Modifications By: Tom Couch <linuxraid@lsi.com>
Copyright (C) 2004-2009 Applied Micro Circuits Corporation.
Copyright (C) 2010 LSI Corporation.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; version 2 of the License.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
NO WARRANTY
THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
solely responsible for determining the appropriateness of using and
distributing the Program and assumes all risks associated with its
exercise of rights under this Agreement, including but not limited to
the risks and costs of program errors, damage to or loss of data,
programs or equipment, and unavailability or interruption of operations.
DISCLAIMER OF LIABILITY
NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Bugs/Comments/Suggestions should be mailed to:
linuxraid@lsi.com
For more information, goto:
http://www.lsi.com
*/
#ifndef _3W_9XXX_H
#define _3W_9XXX_H
/* AEN string type */
typedef struct TAG_twa_message_type {
unsigned int code;
char* text;
} twa_message_type;
/* AEN strings */
static twa_message_type twa_aen_table[] = {
{0x0000, "AEN queue empty"},
{0x0001, "Controller reset occurred"},
{0x0002, "Degraded unit detected"},
{0x0003, "Controller error occurred"},
{0x0004, "Background rebuild failed"},
{0x0005, "Background rebuild done"},
{0x0006, "Incomplete unit detected"},
{0x0007, "Background initialize done"},
{0x0008, "Unclean shutdown detected"},
{0x0009, "Drive timeout detected"},
{0x000A, "Drive error detected"},
{0x000B, "Rebuild started"},
{0x000C, "Background initialize started"},
{0x000D, "Entire logical unit was deleted"},
{0x000E, "Background initialize failed"},
{0x000F, "SMART attribute exceeded threshold"},
{0x0010, "Power supply reported AC under range"},
{0x0011, "Power supply reported DC out of range"},
{0x0012, "Power supply reported a malfunction"},
{0x0013, "Power supply predicted malfunction"},
{0x0014, "Battery charge is below threshold"},
{0x0015, "Fan speed is below threshold"},
{0x0016, "Temperature sensor is above threshold"},
{0x0017, "Power supply was removed"},
{0x0018, "Power supply was inserted"},
{0x0019, "Drive was removed from a bay"},
{0x001A, "Drive was inserted into a bay"},
{0x001B, "Drive bay cover door was opened"},
{0x001C, "Drive bay cover door was closed"},
{0x001D, "Product case was opened"},
{0x0020, "Prepare for shutdown (power-off)"},
{0x0021, "Downgrade UDMA mode to lower speed"},
{0x0022, "Upgrade UDMA mode to higher speed"},
{0x0023, "Sector repair completed"},
{0x0024, "Sbuf memory test failed"},
{0x0025, "Error flushing cached write data to array"},
{0x0026, "Drive reported data ECC error"},
{0x0027, "DCB has checksum error"},
{0x0028, "DCB version is unsupported"},
{0x0029, "Background verify started"},
{0x002A, "Background verify failed"},
{0x002B, "Background verify done"},
{0x002C, "Bad sector overwritten during rebuild"},
{0x002D, "Background rebuild error on source drive"},
{0x002E, "Replace failed because replacement drive too small"},
{0x002F, "Verify failed because array was never initialized"},
{0x0030, "Unsupported ATA drive"},
{0x0031, "Synchronize host/controller time"},
{0x0032, "Spare capacity is inadequate for some units"},
{0x0033, "Background migration started"},
{0x0034, "Background migration failed"},
{0x0035, "Background migration done"},
{0x0036, "Verify detected and fixed data/parity mismatch"},
{0x0037, "SO-DIMM incompatible"},
{0x0038, "SO-DIMM not detected"},
{0x0039, "Corrected Sbuf ECC error"},
{0x003A, "Drive power on reset detected"},
{0x003B, "Background rebuild paused"},
{0x003C, "Background initialize paused"},
{0x003D, "Background verify paused"},
{0x003E, "Background migration paused"},
{0x003F, "Corrupt flash file system detected"},
{0x0040, "Flash file system repaired"},
{0x0041, "Unit number assignments were lost"},
{0x0042, "Error during read of primary DCB"},
{0x0043, "Latent error found in backup DCB"},
{0x00FC, "Recovered/finished array membership update"},
{0x00FD, "Handler lockup"},
{0x00FE, "Retrying PCI transfer"},
{0x00FF, "AEN queue is full"},
{0xFFFFFFFF, (char*) 0}
};
/* AEN severity table */
static char *twa_aen_severity_table[] =
{
"None", "ERROR", "WARNING", "INFO", "DEBUG", (char*) 0
};
/* Error strings */
static twa_message_type twa_error_table[] = {
{0x0100, "SGL entry contains zero data"},
{0x0101, "Invalid command opcode"},
{0x0102, "SGL entry has unaligned address"},
{0x0103, "SGL size does not match command"},
{0x0104, "SGL entry has illegal length"},
{0x0105, "Command packet is not aligned"},
{0x0106, "Invalid request ID"},
{0x0107, "Duplicate request ID"},
{0x0108, "ID not locked"},
{0x0109, "LBA out of range"},
{0x010A, "Logical unit not supported"},
{0x010B, "Parameter table does not exist"},
{0x010C, "Parameter index does not exist"},
{0x010D, "Invalid field in CDB"},
{0x010E, "Specified port has invalid drive"},
{0x010F, "Parameter item size mismatch"},
{0x0110, "Failed memory allocation"},
{0x0111, "Memory request too large"},
{0x0112, "Out of memory segments"},
{0x0113, "Invalid address to deallocate"},
{0x0114, "Out of memory"},
{0x0115, "Out of heap"},
{0x0120, "Double degrade"},
{0x0121, "Drive not degraded"},
{0x0122, "Reconstruct error"},
{0x0123, "Replace not accepted"},
{0x0124, "Replace drive capacity too small"},
{0x0125, "Sector count not allowed"},
{0x0126, "No spares left"},
{0x0127, "Reconstruct error"},
{0x0128, "Unit is offline"},
{0x0129, "Cannot update status to DCB"},
{0x0130, "Invalid stripe handle"},
{0x0131, "Handle that was not locked"},
{0x0132, "Handle that was not empty"},
{0x0133, "Handle has different owner"},
{0x0140, "IPR has parent"},
{0x0150, "Illegal Pbuf address alignment"},
{0x0151, "Illegal Pbuf transfer length"},
{0x0152, "Illegal Sbuf address alignment"},
{0x0153, "Illegal Sbuf transfer length"},
{0x0160, "Command packet too large"},
{0x0161, "SGL exceeds maximum length"},
{0x0162, "SGL has too many entries"},
{0x0170, "Insufficient resources for rebuilder"},
{0x0171, "Verify error (data != parity)"},
{0x0180, "Requested segment not in directory of this DCB"},
{0x0181, "DCB segment has unsupported version"},
{0x0182, "DCB segment has checksum error"},
{0x0183, "DCB support (settings) segment invalid"},
{0x0184, "DCB UDB (unit descriptor block) segment invalid"},
{0x0185, "DCB GUID (globally unique identifier) segment invalid"},
{0x01A0, "Could not clear Sbuf"},
{0x01C0, "Flash identify failed"},
{0x01C1, "Flash out of bounds"},
{0x01C2, "Flash verify error"},
{0x01C3, "Flash file object not found"},
{0x01C4, "Flash file already present"},
{0x01C5, "Flash file system full"},
{0x01C6, "Flash file not present"},
{0x01C7, "Flash file size error"},
{0x01C8, "Bad flash file checksum"},
{0x01CA, "Corrupt flash file system detected"},
{0x01D0, "Invalid field in parameter list"},
{0x01D1, "Parameter list length error"},
{0x01D2, "Parameter item is not changeable"},
{0x01D3, "Parameter item is not saveable"},
{0x0200, "UDMA CRC error"},
{0x0201, "Internal CRC error"},
{0x0202, "Data ECC error"},
{0x0203, "ADP level 1 error"},
{0x0204, "Port timeout"},
{0x0205, "Drive power on reset"},
{0x0206, "ADP level 2 error"},
{0x0207, "Soft reset failed"},
{0x0208, "Drive not ready"},
{0x0209, "Unclassified port error"},
{0x020A, "Drive aborted command"},
{0x0210, "Internal CRC error"},
{0x0211, "PCI abort error"},
{0x0212, "PCI parity error"},
{0x0213, "Port handler error"},
{0x0214, "Token interrupt count error"},
{0x0215, "Timeout waiting for PCI transfer"},
{0x0216, "Corrected buffer ECC"},
{0x0217, "Uncorrected buffer ECC"},
{0x0230, "Unsupported command during flash recovery"},
{0x0231, "Next image buffer expected"},
{0x0232, "Binary image architecture incompatible"},
{0x0233, "Binary image has no signature"},
{0x0234, "Binary image has bad checksum"},
{0x0235, "Image downloaded overflowed buffer"},
{0x0240, "I2C device not found"},
{0x0241, "I2C transaction aborted"},
{0x0242, "SO-DIMM parameter(s) incompatible using defaults"},
{0x0243, "SO-DIMM unsupported"},
{0x0248, "SPI transfer status error"},
{0x0249, "SPI transfer timeout error"},
{0x0250, "Invalid unit descriptor size in CreateUnit"},
{0x0251, "Unit descriptor size exceeds data buffer in CreateUnit"},
{0x0252, "Invalid value in CreateUnit descriptor"},
{0x0253, "Inadequate disk space to support descriptor in CreateUnit"},
{0x0254, "Unable to create data channel for this unit descriptor"},
{0x0255, "CreateUnit descriptor specifies a drive already in use"},
{0x0256, "Unable to write configuration to all disks during CreateUnit"},
{0x0257, "CreateUnit does not support this descriptor version"},
{0x0258, "Invalid subunit for RAID 0 or 5 in CreateUnit"},
{0x0259, "Too many descriptors in CreateUnit"},
{0x025A, "Invalid configuration specified in CreateUnit descriptor"},
{0x025B, "Invalid LBA offset specified in CreateUnit descriptor"},
{0x025C, "Invalid stripelet size specified in CreateUnit descriptor"},
{0x0260, "SMART attribute exceeded threshold"},
{0xFFFFFFFF, (char*) 0}
};
/* Control register bit definitions */
#define TW_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000
#define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000
#define TW_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000
#define TW_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000
#define TW_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000
#define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000
#define TW_CONTROL_CLEAR_ERROR_STATUS 0x00000200
#define TW_CONTROL_ISSUE_SOFT_RESET 0x00000100
#define TW_CONTROL_ENABLE_INTERRUPTS 0x00000080
#define TW_CONTROL_DISABLE_INTERRUPTS 0x00000040
#define TW_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020
#define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000
#define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000
#define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000
/* Status register bit definitions */
#define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000
#define TW_STATUS_MINOR_VERSION_MASK 0x0F000000
#define TW_STATUS_PCI_PARITY_ERROR 0x00800000
#define TW_STATUS_QUEUE_ERROR 0x00400000
#define TW_STATUS_MICROCONTROLLER_ERROR 0x00200000
#define TW_STATUS_PCI_ABORT 0x00100000
#define TW_STATUS_HOST_INTERRUPT 0x00080000
#define TW_STATUS_ATTENTION_INTERRUPT 0x00040000
#define TW_STATUS_COMMAND_INTERRUPT 0x00020000
#define TW_STATUS_RESPONSE_INTERRUPT 0x00010000
#define TW_STATUS_COMMAND_QUEUE_FULL 0x00008000
#define TW_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
#define TW_STATUS_MICROCONTROLLER_READY 0x00002000
#define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
#define TW_STATUS_EXPECTED_BITS 0x00002000
#define TW_STATUS_UNEXPECTED_BITS 0x00F00000
#define TW_STATUS_VALID_INTERRUPT 0x00DF0000
/* PCI related defines */
#define TW_PCI_CLEAR_PARITY_ERRORS 0xc100
#define TW_PCI_CLEAR_PCI_ABORT 0x2000
/* Command packet opcodes used by the driver */
#define TW_OP_INIT_CONNECTION 0x1
#define TW_OP_GET_PARAM 0x12
#define TW_OP_SET_PARAM 0x13
#define TW_OP_EXECUTE_SCSI 0x10
#define TW_OP_DOWNLOAD_FIRMWARE 0x16
#define TW_OP_RESET 0x1C
/* Asynchronous Event Notification (AEN) codes used by the driver */
#define TW_AEN_QUEUE_EMPTY 0x0000
#define TW_AEN_SOFT_RESET 0x0001
#define TW_AEN_SYNC_TIME_WITH_HOST 0x031
#define TW_AEN_SEVERITY_ERROR 0x1
#define TW_AEN_SEVERITY_DEBUG 0x4
#define TW_AEN_NOT_RETRIEVED 0x1
#define TW_AEN_RETRIEVED 0x2
/* Command state defines */
#define TW_S_INITIAL 0x1 /* Initial state */
#define TW_S_STARTED 0x2 /* Id in use */
#define TW_S_POSTED 0x4 /* Posted to the controller */
#define TW_S_PENDING 0x8 /* Waiting to be posted in isr */
#define TW_S_COMPLETED 0x10 /* Completed by isr */
#define TW_S_FINISHED 0x20 /* I/O completely done */
/* Compatibility defines */
#define TW_9000_ARCH_ID 0x5
#define TW_CURRENT_DRIVER_SRL 35
#define TW_CURRENT_DRIVER_BUILD 0
#define TW_CURRENT_DRIVER_BRANCH 0
/* Misc defines */
#define TW_9550SX_DRAIN_COMPLETED 0xFFFF
#define TW_SECTOR_SIZE 512
#define TW_ALIGNMENT_9000 4 /* 4 bytes */
#define TW_ALIGNMENT_9000_SGL 0x3
#define TW_MAX_UNITS 16
#define TW_MAX_UNITS_9650SE 32
#define TW_INIT_MESSAGE_CREDITS 0x100
#define TW_INIT_COMMAND_PACKET_SIZE 0x3
#define TW_INIT_COMMAND_PACKET_SIZE_EXTENDED 0x6
#define TW_EXTENDED_INIT_CONNECT 0x2
#define TW_BUNDLED_FW_SAFE_TO_FLASH 0x4
#define TW_CTLR_FW_RECOMMENDS_FLASH 0x8
#define TW_CTLR_FW_COMPATIBLE 0x2
#define TW_BASE_FW_SRL 24
#define TW_BASE_FW_BRANCH 0
#define TW_BASE_FW_BUILD 1
#define TW_FW_SRL_LUNS_SUPPORTED 28
#define TW_Q_LENGTH 256
#define TW_Q_START 0
#define TW_MAX_SLOT 32
#define TW_MAX_RESET_TRIES 2
#define TW_MAX_CMDS_PER_LUN 254
#define TW_MAX_RESPONSE_DRAIN 256
#define TW_MAX_AEN_DRAIN 255
#define TW_IN_RESET 2
#define TW_USING_MSI 3
#define TW_IN_ATTENTION_LOOP 4
#define TW_MAX_SECTORS 256
#define TW_AEN_WAIT_TIME 1000
#define TW_IOCTL_WAIT_TIME (1 * HZ) /* 1 second */
#define TW_MAX_CDB_LEN 16
#define TW_ISR_DONT_COMPLETE 2
#define TW_ISR_DONT_RESULT 3
#define TW_IOCTL_CHRDEV_TIMEOUT 60 /* 60 seconds */
#define TW_IOCTL_CHRDEV_FREE -1
#define TW_COMMAND_OFFSET 128 /* 128 bytes */
#define TW_VERSION_TABLE 0x0402
#define TW_TIMEKEEP_TABLE 0x040A
#define TW_INFORMATION_TABLE 0x0403
#define TW_PARAM_FWVER 3
#define TW_PARAM_FWVER_LENGTH 16
#define TW_PARAM_BIOSVER 4
#define TW_PARAM_BIOSVER_LENGTH 16
#define TW_PARAM_PORTCOUNT 3
#define TW_PARAM_PORTCOUNT_LENGTH 1
#define TW_MIN_SGL_LENGTH 0x200 /* 512 bytes */
#define TW_MAX_SENSE_LENGTH 256
#define TW_EVENT_SOURCE_AEN 0x1000
#define TW_EVENT_SOURCE_COMMAND 0x1001
#define TW_EVENT_SOURCE_PCHIP 0x1002
#define TW_EVENT_SOURCE_DRIVER 0x1003
#define TW_IOCTL_GET_COMPATIBILITY_INFO 0x101
#define TW_IOCTL_GET_LAST_EVENT 0x102
#define TW_IOCTL_GET_FIRST_EVENT 0x103
#define TW_IOCTL_GET_NEXT_EVENT 0x104
#define TW_IOCTL_GET_PREVIOUS_EVENT 0x105
#define TW_IOCTL_GET_LOCK 0x106
#define TW_IOCTL_RELEASE_LOCK 0x107
#define TW_IOCTL_FIRMWARE_PASS_THROUGH 0x108
#define TW_IOCTL_ERROR_STATUS_NOT_LOCKED 0x1001 // Not locked
#define TW_IOCTL_ERROR_STATUS_LOCKED 0x1002 // Already locked
#define TW_IOCTL_ERROR_STATUS_NO_MORE_EVENTS 0x1003 // No more events
#define TW_IOCTL_ERROR_STATUS_AEN_CLOBBER 0x1004 // AEN clobber occurred
#define TW_IOCTL_ERROR_OS_EFAULT -EFAULT // Bad address
#define TW_IOCTL_ERROR_OS_EINTR -EINTR // Interrupted system call
#define TW_IOCTL_ERROR_OS_EINVAL -EINVAL // Invalid argument
#define TW_IOCTL_ERROR_OS_ENOMEM -ENOMEM // Out of memory
#define TW_IOCTL_ERROR_OS_ERESTARTSYS -ERESTARTSYS // Restart system call
#define TW_IOCTL_ERROR_OS_EIO -EIO // I/O error
#define TW_IOCTL_ERROR_OS_ENOTTY -ENOTTY // Not a typewriter
#define TW_IOCTL_ERROR_OS_ENODEV -ENODEV // No such device
#define TW_ALLOCATION_LENGTH 128
#define TW_SENSE_DATA_LENGTH 18
#define TW_STATUS_CHECK_CONDITION 2
#define TW_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x10a
#define TW_ERROR_UNIT_OFFLINE 0x128
#define TW_MESSAGE_SOURCE_CONTROLLER_ERROR 3
#define TW_MESSAGE_SOURCE_CONTROLLER_EVENT 4
#define TW_MESSAGE_SOURCE_LINUX_DRIVER 6
#define TW_DRIVER TW_MESSAGE_SOURCE_LINUX_DRIVER
#define TW_MESSAGE_SOURCE_LINUX_OS 9
#define TW_OS TW_MESSAGE_SOURCE_LINUX_OS
#ifndef PCI_DEVICE_ID_3WARE_9000
#define PCI_DEVICE_ID_3WARE_9000 0x1002
#endif
#ifndef PCI_DEVICE_ID_3WARE_9550SX
#define PCI_DEVICE_ID_3WARE_9550SX 0x1003
#endif
#ifndef PCI_DEVICE_ID_3WARE_9650SE
#define PCI_DEVICE_ID_3WARE_9650SE 0x1004
#endif
#ifndef PCI_DEVICE_ID_3WARE_9690SA
#define PCI_DEVICE_ID_3WARE_9690SA 0x1005
#endif
/* Bitmask macros to eliminate bitfields */
/* opcode: 5, reserved: 3 */
#define TW_OPRES_IN(x,y) ((x << 5) | (y & 0x1f))
#define TW_OP_OUT(x) (x & 0x1f)
/* opcode: 5, sgloffset: 3 */
#define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
#define TW_SGL_OUT(x) ((x >> 5) & 0x7)
/* severity: 3, reserved: 5 */
#define TW_SEV_OUT(x) (x & 0x7)
/* reserved_1: 4, response_id: 8, reserved_2: 20 */
#define TW_RESID_OUT(x) ((x >> 4) & 0xff)
/* request_id: 12, lun: 4 */
#define TW_REQ_LUN_IN(lun, request_id) (((lun << 12) & 0xf000) | (request_id & 0xfff))
#define TW_LUN_OUT(lun) ((lun >> 12) & 0xf)
/* Macros */
#define TW_CONTROL_REG_ADDR(x) (x->base_addr)
#define TW_STATUS_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0x4)
#define TW_COMMAND_QUEUE_REG_ADDR(x) (sizeof(dma_addr_t) > 4 ? ((unsigned char __iomem *)x->base_addr + 0x20) : ((unsigned char __iomem *)x->base_addr + 0x8))
#define TW_COMMAND_QUEUE_REG_ADDR_LARGE(x) ((unsigned char __iomem *)x->base_addr + 0x20)
#define TW_RESPONSE_QUEUE_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0xC)
#define TW_RESPONSE_QUEUE_REG_ADDR_LARGE(x) ((unsigned char __iomem *)x->base_addr + 0x30)
#define TW_CLEAR_ALL_INTERRUPTS(x) (writel(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_CLEAR_ATTENTION_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_CLEAR_HOST_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_DISABLE_INTERRUPTS(x) (writel(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
#define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
#define TW_MASK_COMMAND_INTERRUPT(x) (writel(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_UNMASK_COMMAND_INTERRUPT(x) (writel(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_SOFT_RESET(x) (writel(TW_CONTROL_ISSUE_SOFT_RESET | \
TW_CONTROL_CLEAR_HOST_INTERRUPT | \
TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
TW_CONTROL_MASK_COMMAND_INTERRUPT | \
TW_CONTROL_MASK_RESPONSE_INTERRUPT | \
TW_CONTROL_CLEAR_ERROR_STATUS | \
TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
#define TW_PRINTK(h,a,b,c) { \
if (h) \
printk(KERN_WARNING "3w-9xxx: scsi%d: ERROR: (0x%02X:0x%04X): %s.\n",h->host_no,a,b,c); \
else \
printk(KERN_WARNING "3w-9xxx: ERROR: (0x%02X:0x%04X): %s.\n",a,b,c); \
}
#define TW_MAX_LUNS(srl) (srl < TW_FW_SRL_LUNS_SUPPORTED ? 1 : 16)
#define TW_COMMAND_SIZE (sizeof(dma_addr_t) > 4 ? 5 : 4)
#define TW_APACHE_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 72 : 109)
#define TW_ESCALADE_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 41 : 62)
#define TW_PADDING_LENGTH (sizeof(dma_addr_t) > 4 ? 8 : 0)
#define TW_CPU_TO_SGL(x) (sizeof(dma_addr_t) > 4 ? cpu_to_le64(x) : cpu_to_le32(x))
#pragma pack(1)
/* Scatter Gather List Entry */
typedef struct TAG_TW_SG_Entry {
dma_addr_t address;
u32 length;
} TW_SG_Entry;
/* Command Packet */
typedef struct TW_Command {
unsigned char opcode__sgloffset;
unsigned char size;
unsigned char request_id;
unsigned char unit__hostid;
/* Second DWORD */
unsigned char status;
unsigned char flags;
union {
unsigned short block_count;
unsigned short parameter_count;
} byte6_offset;
union {
struct {
u32 lba;
TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH];
dma_addr_t padding;
} io;
struct {
TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH];
u32 padding;
dma_addr_t padding2;
} param;
} byte8_offset;
} TW_Command;
/* Command Packet for 9000+ controllers */
typedef struct TAG_TW_Command_Apache {
unsigned char opcode__reserved;
unsigned char unit;
unsigned short request_id__lunl;
unsigned char status;
unsigned char sgl_offset;
unsigned short sgl_entries__lunh;
unsigned char cdb[16];
TW_SG_Entry sg_list[TW_APACHE_MAX_SGL_LENGTH];
unsigned char padding[TW_PADDING_LENGTH];
} TW_Command_Apache;
/* New command packet header */
typedef struct TAG_TW_Command_Apache_Header {
unsigned char sense_data[TW_SENSE_DATA_LENGTH];
struct {
char reserved[4];
unsigned short error;
unsigned char padding;
unsigned char severity__reserved;
} status_block;
unsigned char err_specific_desc[98];
struct {
unsigned char size_header;
unsigned short reserved;
unsigned char size_sense;
} header_desc;
} TW_Command_Apache_Header;
/* This struct is a union of the 2 command packets */
typedef struct TAG_TW_Command_Full {
TW_Command_Apache_Header header;
union {
TW_Command oldcommand;
TW_Command_Apache newcommand;
} command;
} TW_Command_Full;
/* Initconnection structure */
typedef struct TAG_TW_Initconnect {
unsigned char opcode__reserved;
unsigned char size;
unsigned char request_id;
unsigned char res2;
unsigned char status;
unsigned char flags;
unsigned short message_credits;
u32 features;
unsigned short fw_srl;
unsigned short fw_arch_id;
unsigned short fw_branch;
unsigned short fw_build;
u32 result;
} TW_Initconnect;
/* Event info structure */
typedef struct TAG_TW_Event
{
unsigned int sequence_id;
unsigned int time_stamp_sec;
unsigned short aen_code;
unsigned char severity;
unsigned char retrieved;
unsigned char repeat_count;
unsigned char parameter_len;
unsigned char parameter_data[98];
} TW_Event;
typedef struct TAG_TW_Ioctl_Driver_Command {
unsigned int control_code;
unsigned int status;
unsigned int unique_id;
unsigned int sequence_id;
unsigned int os_specific;
unsigned int buffer_length;
} TW_Ioctl_Driver_Command;
typedef struct TAG_TW_Ioctl_Apache {
TW_Ioctl_Driver_Command driver_command;
char padding[488];
TW_Command_Full firmware_command;
char data_buffer[1];
} TW_Ioctl_Buf_Apache;
/* Lock structure for ioctl get/release lock */
typedef struct TAG_TW_Lock {
unsigned long timeout_msec;
unsigned long time_remaining_msec;
unsigned long force_flag;
} TW_Lock;
/* GetParam descriptor */
typedef struct {
unsigned short table_id;
unsigned short parameter_id;
unsigned short parameter_size_bytes;
unsigned short actual_parameter_size_bytes;
unsigned char data[1];
} TW_Param_Apache, *PTW_Param_Apache;
/* Response queue */
typedef union TAG_TW_Response_Queue {
u32 response_id;
u32 value;
} TW_Response_Queue;
/* Compatibility information structure */
typedef struct TAG_TW_Compatibility_Info
{
char driver_version[32];
unsigned short working_srl;
unsigned short working_branch;
unsigned short working_build;
unsigned short driver_srl_high;
unsigned short driver_branch_high;
unsigned short driver_build_high;
unsigned short driver_srl_low;
unsigned short driver_branch_low;
unsigned short driver_build_low;
unsigned short fw_on_ctlr_srl;
unsigned short fw_on_ctlr_branch;
unsigned short fw_on_ctlr_build;
} TW_Compatibility_Info;
#pragma pack()
typedef struct TAG_TW_Device_Extension {
u32 __iomem *base_addr;
unsigned long *generic_buffer_virt[TW_Q_LENGTH];
dma_addr_t generic_buffer_phys[TW_Q_LENGTH];
TW_Command_Full *command_packet_virt[TW_Q_LENGTH];
dma_addr_t command_packet_phys[TW_Q_LENGTH];
struct pci_dev *tw_pci_dev;
struct scsi_cmnd *srb[TW_Q_LENGTH];
unsigned char free_queue[TW_Q_LENGTH];
unsigned char free_head;
unsigned char free_tail;
unsigned char pending_queue[TW_Q_LENGTH];
unsigned char pending_head;
unsigned char pending_tail;
int state[TW_Q_LENGTH];
unsigned int posted_request_count;
unsigned int max_posted_request_count;
unsigned int pending_request_count;
unsigned int max_pending_request_count;
unsigned int max_sgl_entries;
unsigned int sgl_entries;
unsigned int num_resets;
unsigned int sector_count;
unsigned int max_sector_count;
unsigned int aen_count;
struct Scsi_Host *host;
long flags;
int reset_print;
TW_Event *event_queue[TW_Q_LENGTH];
unsigned char error_index;
unsigned char event_queue_wrapped;
unsigned int error_sequence_id;
int ioctl_sem_lock;
u32 ioctl_msec;
int chrdev_request_id;
wait_queue_head_t ioctl_wqueue;
struct mutex ioctl_lock;
char aen_clobber;
TW_Compatibility_Info tw_compat_info;
} TW_Device_Extension;
#endif /* _3W_9XXX_H */

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/*
3w-sas.h -- LSI 3ware SAS/SATA-RAID Controller device driver for Linux.
Written By: Adam Radford <linuxraid@lsi.com>
Copyright (C) 2009 LSI Corporation.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; version 2 of the License.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
NO WARRANTY
THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
solely responsible for determining the appropriateness of using and
distributing the Program and assumes all risks associated with its
exercise of rights under this Agreement, including but not limited to
the risks and costs of program errors, damage to or loss of data,
programs or equipment, and unavailability or interruption of operations.
DISCLAIMER OF LIABILITY
NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Bugs/Comments/Suggestions should be mailed to:
linuxraid@lsi.com
For more information, goto:
http://www.lsi.com
*/
#ifndef _3W_SAS_H
#define _3W_SAS_H
/* AEN severity table */
static char *twl_aen_severity_table[] =
{
"None", "ERROR", "WARNING", "INFO", "DEBUG", NULL
};
/* Liberator register offsets */
#define TWL_STATUS 0x0 /* Status */
#define TWL_HIBDB 0x20 /* Inbound doorbell */
#define TWL_HISTAT 0x30 /* Host interrupt status */
#define TWL_HIMASK 0x34 /* Host interrupt mask */
#define TWL_HOBDB 0x9C /* Outbound doorbell */
#define TWL_HOBDBC 0xA0 /* Outbound doorbell clear */
#define TWL_SCRPD3 0xBC /* Scratchpad */
#define TWL_HIBQPL 0xC0 /* Host inbound Q low */
#define TWL_HIBQPH 0xC4 /* Host inbound Q high */
#define TWL_HOBQPL 0xC8 /* Host outbound Q low */
#define TWL_HOBQPH 0xCC /* Host outbound Q high */
#define TWL_HISTATUS_VALID_INTERRUPT 0xC
#define TWL_HISTATUS_ATTENTION_INTERRUPT 0x4
#define TWL_HISTATUS_RESPONSE_INTERRUPT 0x8
#define TWL_STATUS_OVERRUN_SUBMIT 0x2000
#define TWL_ISSUE_SOFT_RESET 0x100
#define TWL_CONTROLLER_READY 0x2000
#define TWL_DOORBELL_CONTROLLER_ERROR 0x200000
#define TWL_DOORBELL_ATTENTION_INTERRUPT 0x40000
#define TWL_PULL_MODE 0x1
/* Command packet opcodes used by the driver */
#define TW_OP_INIT_CONNECTION 0x1
#define TW_OP_GET_PARAM 0x12
#define TW_OP_SET_PARAM 0x13
#define TW_OP_EXECUTE_SCSI 0x10
/* Asynchronous Event Notification (AEN) codes used by the driver */
#define TW_AEN_QUEUE_EMPTY 0x0000
#define TW_AEN_SOFT_RESET 0x0001
#define TW_AEN_SYNC_TIME_WITH_HOST 0x031
#define TW_AEN_SEVERITY_ERROR 0x1
#define TW_AEN_SEVERITY_DEBUG 0x4
#define TW_AEN_NOT_RETRIEVED 0x1
/* Command state defines */
#define TW_S_INITIAL 0x1 /* Initial state */
#define TW_S_STARTED 0x2 /* Id in use */
#define TW_S_POSTED 0x4 /* Posted to the controller */
#define TW_S_COMPLETED 0x8 /* Completed by isr */
#define TW_S_FINISHED 0x10 /* I/O completely done */
/* Compatibility defines */
#define TW_9750_ARCH_ID 10
#define TW_CURRENT_DRIVER_SRL 40
#define TW_CURRENT_DRIVER_BUILD 0
#define TW_CURRENT_DRIVER_BRANCH 0
/* Misc defines */
#define TW_SECTOR_SIZE 512
#define TW_MAX_UNITS 32
#define TW_INIT_MESSAGE_CREDITS 0x100
#define TW_INIT_COMMAND_PACKET_SIZE 0x3
#define TW_INIT_COMMAND_PACKET_SIZE_EXTENDED 0x6
#define TW_EXTENDED_INIT_CONNECT 0x2
#define TW_BASE_FW_SRL 24
#define TW_BASE_FW_BRANCH 0
#define TW_BASE_FW_BUILD 1
#define TW_Q_LENGTH 256
#define TW_Q_START 0
#define TW_MAX_SLOT 32
#define TW_MAX_RESET_TRIES 2
#define TW_MAX_CMDS_PER_LUN 254
#define TW_MAX_AEN_DRAIN 255
#define TW_IN_RESET 2
#define TW_USING_MSI 3
#define TW_IN_ATTENTION_LOOP 4
#define TW_MAX_SECTORS 256
#define TW_MAX_CDB_LEN 16
#define TW_IOCTL_CHRDEV_TIMEOUT 60 /* 60 seconds */
#define TW_IOCTL_CHRDEV_FREE -1
#define TW_COMMAND_OFFSET 128 /* 128 bytes */
#define TW_VERSION_TABLE 0x0402
#define TW_TIMEKEEP_TABLE 0x040A
#define TW_INFORMATION_TABLE 0x0403
#define TW_PARAM_FWVER 3
#define TW_PARAM_FWVER_LENGTH 16
#define TW_PARAM_BIOSVER 4
#define TW_PARAM_BIOSVER_LENGTH 16
#define TW_PARAM_MODEL 8
#define TW_PARAM_MODEL_LENGTH 16
#define TW_PARAM_PHY_SUMMARY_TABLE 1
#define TW_PARAM_PHYCOUNT 2
#define TW_PARAM_PHYCOUNT_LENGTH 1
#define TW_IOCTL_FIRMWARE_PASS_THROUGH 0x108 // Used by smartmontools
#define TW_ALLOCATION_LENGTH 128
#define TW_SENSE_DATA_LENGTH 18
#define TW_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x10a
#define TW_ERROR_INVALID_FIELD_IN_CDB 0x10d
#define TW_ERROR_UNIT_OFFLINE 0x128
#define TW_MESSAGE_SOURCE_CONTROLLER_ERROR 3
#define TW_MESSAGE_SOURCE_CONTROLLER_EVENT 4
#define TW_DRIVER 6
#ifndef PCI_DEVICE_ID_3WARE_9750
#define PCI_DEVICE_ID_3WARE_9750 0x1010
#endif
/* Bitmask macros to eliminate bitfields */
/* opcode: 5, reserved: 3 */
#define TW_OPRES_IN(x,y) ((x << 5) | (y & 0x1f))
#define TW_OP_OUT(x) (x & 0x1f)
/* opcode: 5, sgloffset: 3 */
#define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
#define TW_SGL_OUT(x) ((x >> 5) & 0x7)
/* severity: 3, reserved: 5 */
#define TW_SEV_OUT(x) (x & 0x7)
/* not_mfa: 1, reserved: 7, status: 8, request_id: 16 */
#define TW_RESID_OUT(x) ((x >> 16) & 0xffff)
#define TW_NOTMFA_OUT(x) (x & 0x1)
/* request_id: 12, lun: 4 */
#define TW_REQ_LUN_IN(lun, request_id) (((lun << 12) & 0xf000) | (request_id & 0xfff))
#define TW_LUN_OUT(lun) ((lun >> 12) & 0xf)
/* Register access macros */
#define TWL_STATUS_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_STATUS)
#define TWL_HOBQPL_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HOBQPL)
#define TWL_HOBQPH_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HOBQPH)
#define TWL_HOBDB_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HOBDB)
#define TWL_HOBDBC_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HOBDBC)
#define TWL_HIMASK_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HIMASK)
#define TWL_HISTAT_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HISTAT)
#define TWL_HIBQPH_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HIBQPH)
#define TWL_HIBQPL_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HIBQPL)
#define TWL_HIBDB_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HIBDB)
#define TWL_SCRPD3_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_SCRPD3)
#define TWL_MASK_INTERRUPTS(x) (writel(~0, TWL_HIMASK_REG_ADDR(tw_dev)))
#define TWL_UNMASK_INTERRUPTS(x) (writel(~TWL_HISTATUS_VALID_INTERRUPT, TWL_HIMASK_REG_ADDR(tw_dev)))
#define TWL_CLEAR_DB_INTERRUPT(x) (writel(~0, TWL_HOBDBC_REG_ADDR(tw_dev)))
#define TWL_SOFT_RESET(x) (writel(TWL_ISSUE_SOFT_RESET, TWL_HIBDB_REG_ADDR(tw_dev)))
/* Macros */
#define TW_PRINTK(h,a,b,c) { \
if (h) \
printk(KERN_WARNING "3w-sas: scsi%d: ERROR: (0x%02X:0x%04X): %s.\n",h->host_no,a,b,c); \
else \
printk(KERN_WARNING "3w-sas: ERROR: (0x%02X:0x%04X): %s.\n",a,b,c); \
}
#define TW_MAX_LUNS 16
#define TW_COMMAND_SIZE (sizeof(dma_addr_t) > 4 ? 6 : 4)
#define TW_LIBERATOR_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 46 : 92)
#define TW_LIBERATOR_MAX_SGL_LENGTH_OLD (sizeof(dma_addr_t) > 4 ? 47 : 94)
#define TW_PADDING_LENGTH_LIBERATOR 136
#define TW_PADDING_LENGTH_LIBERATOR_OLD 132
#define TW_CPU_TO_SGL(x) (sizeof(dma_addr_t) > 4 ? cpu_to_le64(x) : cpu_to_le32(x))
#pragma pack(1)
/* SGL entry */
typedef struct TAG_TW_SG_Entry_ISO {
dma_addr_t address;
dma_addr_t length;
} TW_SG_Entry_ISO;
/* Old Command Packet with ISO SGL */
typedef struct TW_Command {
unsigned char opcode__sgloffset;
unsigned char size;
unsigned char request_id;
unsigned char unit__hostid;
/* Second DWORD */
unsigned char status;
unsigned char flags;
union {
unsigned short block_count;
unsigned short parameter_count;
} byte6_offset;
union {
struct {
u32 lba;
TW_SG_Entry_ISO sgl[TW_LIBERATOR_MAX_SGL_LENGTH_OLD];
unsigned char padding[TW_PADDING_LENGTH_LIBERATOR_OLD];
} io;
struct {
TW_SG_Entry_ISO sgl[TW_LIBERATOR_MAX_SGL_LENGTH_OLD];
u32 padding;
unsigned char padding2[TW_PADDING_LENGTH_LIBERATOR_OLD];
} param;
} byte8_offset;
} TW_Command;
/* New Command Packet with ISO SGL */
typedef struct TAG_TW_Command_Apache {
unsigned char opcode__reserved;
unsigned char unit;
unsigned short request_id__lunl;
unsigned char status;
unsigned char sgl_offset;
unsigned short sgl_entries__lunh;
unsigned char cdb[16];
TW_SG_Entry_ISO sg_list[TW_LIBERATOR_MAX_SGL_LENGTH];
unsigned char padding[TW_PADDING_LENGTH_LIBERATOR];
} TW_Command_Apache;
/* New command packet header */
typedef struct TAG_TW_Command_Apache_Header {
unsigned char sense_data[TW_SENSE_DATA_LENGTH];
struct {
char reserved[4];
unsigned short error;
unsigned char padding;
unsigned char severity__reserved;
} status_block;
unsigned char err_specific_desc[98];
struct {
unsigned char size_header;
unsigned short request_id;
unsigned char size_sense;
} header_desc;
} TW_Command_Apache_Header;
/* This struct is a union of the 2 command packets */
typedef struct TAG_TW_Command_Full {
TW_Command_Apache_Header header;
union {
TW_Command oldcommand;
TW_Command_Apache newcommand;
} command;
} TW_Command_Full;
/* Initconnection structure */
typedef struct TAG_TW_Initconnect {
unsigned char opcode__reserved;
unsigned char size;
unsigned char request_id;
unsigned char res2;
unsigned char status;
unsigned char flags;
unsigned short message_credits;
u32 features;
unsigned short fw_srl;
unsigned short fw_arch_id;
unsigned short fw_branch;
unsigned short fw_build;
u32 result;
} TW_Initconnect;
/* Event info structure */
typedef struct TAG_TW_Event
{
unsigned int sequence_id;
unsigned int time_stamp_sec;
unsigned short aen_code;
unsigned char severity;
unsigned char retrieved;
unsigned char repeat_count;
unsigned char parameter_len;
unsigned char parameter_data[98];
} TW_Event;
typedef struct TAG_TW_Ioctl_Driver_Command {
unsigned int control_code;
unsigned int status;
unsigned int unique_id;
unsigned int sequence_id;
unsigned int os_specific;
unsigned int buffer_length;
} TW_Ioctl_Driver_Command;
typedef struct TAG_TW_Ioctl_Apache {
TW_Ioctl_Driver_Command driver_command;
char padding[488];
TW_Command_Full firmware_command;
char data_buffer[1];
} TW_Ioctl_Buf_Apache;
/* GetParam descriptor */
typedef struct {
unsigned short table_id;
unsigned short parameter_id;
unsigned short parameter_size_bytes;
unsigned short actual_parameter_size_bytes;
unsigned char data[1];
} TW_Param_Apache;
/* Compatibility information structure */
typedef struct TAG_TW_Compatibility_Info
{
char driver_version[32];
unsigned short working_srl;
unsigned short working_branch;
unsigned short working_build;
unsigned short driver_srl_high;
unsigned short driver_branch_high;
unsigned short driver_build_high;
unsigned short driver_srl_low;
unsigned short driver_branch_low;
unsigned short driver_build_low;
unsigned short fw_on_ctlr_srl;
unsigned short fw_on_ctlr_branch;
unsigned short fw_on_ctlr_build;
} TW_Compatibility_Info;
#pragma pack()
typedef struct TAG_TW_Device_Extension {
void __iomem *base_addr;
unsigned long *generic_buffer_virt[TW_Q_LENGTH];
dma_addr_t generic_buffer_phys[TW_Q_LENGTH];
TW_Command_Full *command_packet_virt[TW_Q_LENGTH];
dma_addr_t command_packet_phys[TW_Q_LENGTH];
TW_Command_Apache_Header *sense_buffer_virt[TW_Q_LENGTH];
dma_addr_t sense_buffer_phys[TW_Q_LENGTH];
struct pci_dev *tw_pci_dev;
struct scsi_cmnd *srb[TW_Q_LENGTH];
unsigned char free_queue[TW_Q_LENGTH];
unsigned char free_head;
unsigned char free_tail;
int state[TW_Q_LENGTH];
unsigned int posted_request_count;
unsigned int max_posted_request_count;
unsigned int max_sgl_entries;
unsigned int sgl_entries;
unsigned int num_resets;
unsigned int sector_count;
unsigned int max_sector_count;
unsigned int aen_count;
struct Scsi_Host *host;
long flags;
TW_Event *event_queue[TW_Q_LENGTH];
unsigned char error_index;
unsigned int error_sequence_id;
int chrdev_request_id;
wait_queue_head_t ioctl_wqueue;
struct mutex ioctl_lock;
TW_Compatibility_Info tw_compat_info;
char online;
} TW_Device_Extension;
#endif /* _3W_SAS_H */

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/*
3w-xxxx.h -- 3ware Storage Controller device driver for Linux.
Written By: Adam Radford <linuxraid@lsi.com>
Modifications By: Joel Jacobson <linux@3ware.com>
Arnaldo Carvalho de Melo <acme@conectiva.com.br>
Brad Strand <linux@3ware.com>
Copyright (C) 1999-2010 3ware Inc.
Kernel compatibility By: Andre Hedrick <andre@suse.com>
Non-Copyright (C) 2000 Andre Hedrick <andre@suse.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; version 2 of the License.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
NO WARRANTY
THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
solely responsible for determining the appropriateness of using and
distributing the Program and assumes all risks associated with its
exercise of rights under this Agreement, including but not limited to
the risks and costs of program errors, damage to or loss of data,
programs or equipment, and unavailability or interruption of operations.
DISCLAIMER OF LIABILITY
NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Bugs/Comments/Suggestions should be mailed to:
linuxraid@lsi.com
For more information, goto:
http://www.lsi.com
*/
#ifndef _3W_XXXX_H
#define _3W_XXXX_H
#include <linux/types.h>
/* AEN strings */
static char *tw_aen_string[] = {
[0x000] = "INFO: AEN queue empty",
[0x001] = "INFO: Soft reset occurred",
[0x002] = "ERROR: Unit degraded: Unit #",
[0x003] = "ERROR: Controller error",
[0x004] = "ERROR: Rebuild failed: Unit #",
[0x005] = "INFO: Rebuild complete: Unit #",
[0x006] = "ERROR: Incomplete unit detected: Unit #",
[0x007] = "INFO: Initialization complete: Unit #",
[0x008] = "WARNING: Unclean shutdown detected: Unit #",
[0x009] = "WARNING: ATA port timeout: Port #",
[0x00A] = "ERROR: Drive error: Port #",
[0x00B] = "INFO: Rebuild started: Unit #",
[0x00C] = "INFO: Initialization started: Unit #",
[0x00D] = "ERROR: Logical unit deleted: Unit #",
[0x00F] = "WARNING: SMART threshold exceeded: Port #",
[0x021] = "WARNING: ATA UDMA downgrade: Port #",
[0x022] = "WARNING: ATA UDMA upgrade: Port #",
[0x023] = "WARNING: Sector repair occurred: Port #",
[0x024] = "ERROR: SBUF integrity check failure",
[0x025] = "ERROR: Lost cached write: Port #",
[0x026] = "ERROR: Drive ECC error detected: Port #",
[0x027] = "ERROR: DCB checksum error: Port #",
[0x028] = "ERROR: DCB unsupported version: Port #",
[0x029] = "INFO: Verify started: Unit #",
[0x02A] = "ERROR: Verify failed: Port #",
[0x02B] = "INFO: Verify complete: Unit #",
[0x02C] = "WARNING: Overwrote bad sector during rebuild: Port #",
[0x02D] = "ERROR: Encountered bad sector during rebuild: Port #",
[0x02E] = "ERROR: Replacement drive is too small: Port #",
[0x02F] = "WARNING: Verify error: Unit not previously initialized: Unit #",
[0x030] = "ERROR: Drive not supported: Port #"
};
/*
Sense key lookup table
Format: ESDC/flags,SenseKey,AdditionalSenseCode,AdditionalSenseCodeQualifier
*/
static unsigned char tw_sense_table[][4] =
{
/* Codes for newer firmware */
// ATA Error SCSI Error
{0x01, 0x03, 0x13, 0x00}, // Address mark not found Address mark not found for data field
{0x04, 0x0b, 0x00, 0x00}, // Aborted command Aborted command
{0x10, 0x0b, 0x14, 0x00}, // ID not found Recorded entity not found
{0x40, 0x03, 0x11, 0x00}, // Uncorrectable ECC error Unrecovered read error
{0x61, 0x04, 0x00, 0x00}, // Device fault Hardware error
{0x84, 0x0b, 0x47, 0x00}, // Data CRC error SCSI parity error
{0xd0, 0x0b, 0x00, 0x00}, // Device busy Aborted command
{0xd1, 0x0b, 0x00, 0x00}, // Device busy Aborted command
{0x37, 0x02, 0x04, 0x00}, // Unit offline Not ready
{0x09, 0x02, 0x04, 0x00}, // Unrecovered disk error Not ready
/* Codes for older firmware */
// 3ware Error SCSI Error
{0x51, 0x0b, 0x00, 0x00} // Unspecified Aborted command
};
/* Control register bit definitions */
#define TW_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000
#define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000
#define TW_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000
#define TW_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000
#define TW_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000
#define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000
#define TW_CONTROL_CLEAR_ERROR_STATUS 0x00000200
#define TW_CONTROL_ISSUE_SOFT_RESET 0x00000100
#define TW_CONTROL_ENABLE_INTERRUPTS 0x00000080
#define TW_CONTROL_DISABLE_INTERRUPTS 0x00000040
#define TW_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020
#define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000
#define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000
#define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000
#define TW_CONTROL_CLEAR_SBUF_WRITE_ERROR 0x00000008
/* Status register bit definitions */
#define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000
#define TW_STATUS_MINOR_VERSION_MASK 0x0F000000
#define TW_STATUS_PCI_PARITY_ERROR 0x00800000
#define TW_STATUS_QUEUE_ERROR 0x00400000
#define TW_STATUS_MICROCONTROLLER_ERROR 0x00200000
#define TW_STATUS_PCI_ABORT 0x00100000
#define TW_STATUS_HOST_INTERRUPT 0x00080000
#define TW_STATUS_ATTENTION_INTERRUPT 0x00040000
#define TW_STATUS_COMMAND_INTERRUPT 0x00020000
#define TW_STATUS_RESPONSE_INTERRUPT 0x00010000
#define TW_STATUS_COMMAND_QUEUE_FULL 0x00008000
#define TW_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
#define TW_STATUS_MICROCONTROLLER_READY 0x00002000
#define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
#define TW_STATUS_ALL_INTERRUPTS 0x000F0000
#define TW_STATUS_CLEARABLE_BITS 0x00D00000
#define TW_STATUS_EXPECTED_BITS 0x00002000
#define TW_STATUS_UNEXPECTED_BITS 0x00F00008
#define TW_STATUS_SBUF_WRITE_ERROR 0x00000008
#define TW_STATUS_VALID_INTERRUPT 0x00DF0008
/* RESPONSE QUEUE BIT DEFINITIONS */
#define TW_RESPONSE_ID_MASK 0x00000FF0
/* PCI related defines */
#define TW_IO_ADDRESS_RANGE 0x10
#define TW_DEVICE_NAME "3ware Storage Controller"
#define TW_VENDOR_ID (0x13C1) /* 3ware */
#define TW_DEVICE_ID (0x1000) /* Storage Controller */
#define TW_DEVICE_ID2 (0x1001) /* 7000 series controller */
#define TW_NUMDEVICES 2
#define TW_PCI_CLEAR_PARITY_ERRORS 0xc100
#define TW_PCI_CLEAR_PCI_ABORT 0x2000
/* Command packet opcodes */
#define TW_OP_NOP 0x0
#define TW_OP_INIT_CONNECTION 0x1
#define TW_OP_READ 0x2
#define TW_OP_WRITE 0x3
#define TW_OP_VERIFY 0x4
#define TW_OP_GET_PARAM 0x12
#define TW_OP_SET_PARAM 0x13
#define TW_OP_SECTOR_INFO 0x1a
#define TW_OP_AEN_LISTEN 0x1c
#define TW_OP_FLUSH_CACHE 0x0e
#define TW_CMD_PACKET 0x1d
#define TW_CMD_PACKET_WITH_DATA 0x1f
/* Asynchronous Event Notification (AEN) Codes */
#define TW_AEN_QUEUE_EMPTY 0x0000
#define TW_AEN_SOFT_RESET 0x0001
#define TW_AEN_DEGRADED_MIRROR 0x0002
#define TW_AEN_CONTROLLER_ERROR 0x0003
#define TW_AEN_REBUILD_FAIL 0x0004
#define TW_AEN_REBUILD_DONE 0x0005
#define TW_AEN_QUEUE_FULL 0x00ff
#define TW_AEN_TABLE_UNDEFINED 0x15
#define TW_AEN_APORT_TIMEOUT 0x0009
#define TW_AEN_DRIVE_ERROR 0x000A
#define TW_AEN_SMART_FAIL 0x000F
#define TW_AEN_SBUF_FAIL 0x0024
/* Misc defines */
#define TW_ALIGNMENT_6000 64 /* 64 bytes */
#define TW_ALIGNMENT_7000 4 /* 4 bytes */
#define TW_MAX_UNITS 16
#define TW_COMMAND_ALIGNMENT_MASK 0x1ff
#define TW_INIT_MESSAGE_CREDITS 0x100
#define TW_INIT_COMMAND_PACKET_SIZE 0x3
#define TW_POLL_MAX_RETRIES 20000
#define TW_MAX_SGL_LENGTH 62
#define TW_ATA_PASS_SGL_MAX 60
#define TW_Q_LENGTH 256
#define TW_Q_START 0
#define TW_MAX_SLOT 32
#define TW_MAX_PCI_BUSES 255
#define TW_MAX_RESET_TRIES 3
#define TW_UNIT_INFORMATION_TABLE_BASE 0x300
#define TW_MAX_CMDS_PER_LUN 254 /* 254 for io, 1 for
chrdev ioctl, one for
internal aen post */
#define TW_BLOCK_SIZE 0x200 /* 512-byte blocks */
#define TW_IOCTL 0x80
#define TW_UNIT_ONLINE 1
#define TW_IN_INTR 1
#define TW_IN_RESET 2
#define TW_IN_CHRDEV_IOCTL 3
#define TW_MAX_SECTORS 256
#define TW_MAX_IOCTL_SECTORS 512
#define TW_AEN_WAIT_TIME 1000
#define TW_IOCTL_WAIT_TIME (1 * HZ) /* 1 second */
#define TW_ISR_DONT_COMPLETE 2
#define TW_ISR_DONT_RESULT 3
#define TW_IOCTL_TIMEOUT 25 /* 25 seconds */
#define TW_IOCTL_CHRDEV_TIMEOUT 60 /* 60 seconds */
#define TW_IOCTL_CHRDEV_FREE -1
#define TW_DMA_MASK DMA_BIT_MASK(32)
#define TW_MAX_CDB_LEN 16
/* Bitmask macros to eliminate bitfields */
/* opcode: 5, sgloffset: 3 */
#define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
#define TW_SGL_OUT(x) ((x >> 5) & 0x7)
/* reserved_1: 4, response_id: 8, reserved_2: 20 */
#define TW_RESID_OUT(x) ((x >> 4) & 0xff)
/* unit: 4, host_id: 4 */
#define TW_UNITHOST_IN(x,y) ((x << 4) | ( y & 0xf))
#define TW_UNIT_OUT(x) (x & 0xf)
/* Macros */
#define TW_CONTROL_REG_ADDR(x) (x->base_addr)
#define TW_STATUS_REG_ADDR(x) (x->base_addr + 0x4)
#define TW_COMMAND_QUEUE_REG_ADDR(x) (x->base_addr + 0x8)
#define TW_RESPONSE_QUEUE_REG_ADDR(x) (x->base_addr + 0xC)
#define TW_CLEAR_ALL_INTERRUPTS(x) (outl(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_CLEAR_ATTENTION_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_CLEAR_HOST_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_DISABLE_INTERRUPTS(x) (outl(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
#define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
#define TW_MASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_UNMASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_SOFT_RESET(x) (outl(TW_CONTROL_ISSUE_SOFT_RESET | \
TW_CONTROL_CLEAR_HOST_INTERRUPT | \
TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
TW_CONTROL_MASK_COMMAND_INTERRUPT | \
TW_CONTROL_MASK_RESPONSE_INTERRUPT | \
TW_CONTROL_CLEAR_ERROR_STATUS | \
TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
#define TW_STATUS_ERRORS(x) \
(((x & TW_STATUS_PCI_ABORT) || \
(x & TW_STATUS_PCI_PARITY_ERROR) || \
(x & TW_STATUS_QUEUE_ERROR) || \
(x & TW_STATUS_MICROCONTROLLER_ERROR)) && \
(x & TW_STATUS_MICROCONTROLLER_READY))
#ifdef TW_DEBUG
#define dprintk(msg...) printk(msg)
#else
#define dprintk(msg...) do { } while(0)
#endif
#pragma pack(1)
/* Scatter Gather List Entry */
typedef struct TAG_TW_SG_Entry {
u32 address;
u32 length;
} TW_SG_Entry;
typedef unsigned char TW_Sector[512];
/* Command Packet */
typedef struct TW_Command {
unsigned char opcode__sgloffset;
unsigned char size;
unsigned char request_id;
unsigned char unit__hostid;
/* Second DWORD */
unsigned char status;
unsigned char flags;
union {
unsigned short block_count;
unsigned short parameter_count;
unsigned short message_credits;
} byte6;
union {
struct {
u32 lba;
TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
u32 padding; /* pad to 512 bytes */
} io;
struct {
TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
u32 padding[2];
} param;
struct {
u32 response_queue_pointer;
u32 padding[125];
} init_connection;
struct {
char version[504];
} ioctl_miniport_version;
} byte8;
} TW_Command;
#pragma pack()
typedef struct TAG_TW_Ioctl {
unsigned char opcode;
unsigned short table_id;
unsigned char parameter_id;
unsigned char parameter_size_bytes;
unsigned char unit_index;
unsigned char data[1];
} TW_Ioctl;
#pragma pack(1)
/* Structure for new chardev ioctls */
typedef struct TAG_TW_New_Ioctl {
unsigned int data_buffer_length;
unsigned char padding [508];
TW_Command firmware_command;
char data_buffer[1];
} TW_New_Ioctl;
/* GetParam descriptor */
typedef struct {
unsigned short table_id;
unsigned char parameter_id;
unsigned char parameter_size_bytes;
unsigned char data[1];
} TW_Param, *PTW_Param;
/* Response queue */
typedef union TAG_TW_Response_Queue {
u32 response_id;
u32 value;
} TW_Response_Queue;
typedef int TW_Cmd_State;
#define TW_S_INITIAL 0x1 /* Initial state */
#define TW_S_STARTED 0x2 /* Id in use */
#define TW_S_POSTED 0x4 /* Posted to the controller */
#define TW_S_PENDING 0x8 /* Waiting to be posted in isr */
#define TW_S_COMPLETED 0x10 /* Completed by isr */
#define TW_S_FINISHED 0x20 /* I/O completely done */
#define TW_START_MASK (TW_S_STARTED | TW_S_POSTED | TW_S_PENDING | TW_S_COMPLETED)
/* Command header for ATA pass-thru */
typedef struct TAG_TW_Passthru
{
unsigned char opcode__sgloffset;
unsigned char size;
unsigned char request_id;
unsigned char aport__hostid;
unsigned char status;
unsigned char flags;
unsigned short param;
unsigned short features;
unsigned short sector_count;
unsigned short sector_num;
unsigned short cylinder_lo;
unsigned short cylinder_hi;
unsigned char drive_head;
unsigned char command;
TW_SG_Entry sg_list[TW_ATA_PASS_SGL_MAX];
unsigned char padding[12];
} TW_Passthru;
#pragma pack()
typedef struct TAG_TW_Device_Extension {
u32 base_addr;
unsigned long *alignment_virtual_address[TW_Q_LENGTH];
unsigned long alignment_physical_address[TW_Q_LENGTH];
int is_unit_present[TW_MAX_UNITS];
unsigned long *command_packet_virtual_address[TW_Q_LENGTH];
unsigned long command_packet_physical_address[TW_Q_LENGTH];
struct pci_dev *tw_pci_dev;
struct scsi_cmnd *srb[TW_Q_LENGTH];
unsigned char free_queue[TW_Q_LENGTH];
unsigned char free_head;
unsigned char free_tail;
unsigned char pending_queue[TW_Q_LENGTH];
unsigned char pending_head;
unsigned char pending_tail;
TW_Cmd_State state[TW_Q_LENGTH];
u32 posted_request_count;
u32 max_posted_request_count;
u32 request_count_marked_pending;
u32 pending_request_count;
u32 max_pending_request_count;
u32 max_sgl_entries;
u32 sgl_entries;
u32 num_resets;
u32 sector_count;
u32 max_sector_count;
u32 aen_count;
struct Scsi_Host *host;
struct mutex ioctl_lock;
unsigned short aen_queue[TW_Q_LENGTH];
unsigned char aen_head;
unsigned char aen_tail;
volatile long flags; /* long req'd for set_bit --RR */
int reset_print;
volatile int chrdev_request_id;
wait_queue_head_t ioctl_wqueue;
} TW_Device_Extension;
#endif /* _3W_XXXX_H */

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/* -*- mode: c; c-basic-offset: 8 -*- */
/* Driver for 53c700 and 53c700-66 chips from NCR and Symbios
*
* Copyright (C) 2001 by James.Bottomley@HansenPartnership.com
*/
#ifndef _53C700_H
#define _53C700_H
#include <linux/interrupt.h>
#include <asm/io.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_cmnd.h>
/* Turn on for general debugging---too verbose for normal use */
#undef NCR_700_DEBUG
/* Debug the tag queues, checking hash queue allocation and deallocation
* and search for duplicate tags */
#undef NCR_700_TAG_DEBUG
#ifdef NCR_700_DEBUG
#define DEBUG(x) printk x
#define DDEBUG(prefix, sdev, fmt, a...) \
sdev_printk(prefix, sdev, fmt, ##a)
#define CDEBUG(prefix, scmd, fmt, a...) \
scmd_printk(prefix, scmd, fmt, ##a)
#else
#define DEBUG(x) do {} while (0)
#define DDEBUG(prefix, scmd, fmt, a...) do {} while (0)
#define CDEBUG(prefix, scmd, fmt, a...) do {} while (0)
#endif
/* The number of available command slots */
#define NCR_700_COMMAND_SLOTS_PER_HOST 64
/* The maximum number of Scatter Gathers we allow */
#define NCR_700_SG_SEGMENTS 32
/* The maximum number of luns (make this of the form 2^n) */
#define NCR_700_MAX_LUNS 32
#define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1)
/* Maximum number of tags the driver ever allows per device */
#define NCR_700_MAX_TAGS 16
/* Tag depth the driver starts out with (can be altered in sysfs) */
#define NCR_700_DEFAULT_TAGS 4
/* This is the default number of commands per LUN in the untagged case.
* two is a good value because it means we can have one command active and
* one command fully prepared and waiting
*/
#define NCR_700_CMD_PER_LUN 2
/* magic byte identifying an internally generated REQUEST_SENSE command */
#define NCR_700_INTERNAL_SENSE_MAGIC 0x42
struct NCR_700_Host_Parameters;
/* These are the externally used routines */
struct Scsi_Host *NCR_700_detect(struct scsi_host_template *,
struct NCR_700_Host_Parameters *, struct device *);
int NCR_700_release(struct Scsi_Host *host);
irqreturn_t NCR_700_intr(int, void *);
enum NCR_700_Host_State {
NCR_700_HOST_BUSY,
NCR_700_HOST_FREE,
};
struct NCR_700_SG_List {
/* The following is a script fragment to move the buffer onto the
* bus and then link the next fragment or return */
#define SCRIPT_MOVE_DATA_IN 0x09000000
#define SCRIPT_MOVE_DATA_OUT 0x08000000
__u32 ins;
__u32 pAddr;
#define SCRIPT_NOP 0x80000000
#define SCRIPT_RETURN 0x90080000
};
struct NCR_700_Device_Parameters {
/* space for creating a request sense command. Really, except
* for the annoying SCSI-2 requirement for LUN information in
* cmnd[1], this could be in static storage */
unsigned char cmnd[MAX_COMMAND_SIZE];
__u8 depth;
};
/* The SYNC negotiation sequence looks like:
*
* If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the
* initial identify for the device and set DEV_BEGIN_SYNC_NEGOTATION
* If we get an SDTR reply, work out the SXFER parameters, squirrel
* them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set
* DEV_NEGOTIATED_SYNC. If we get a REJECT msg, squirrel
*
*
* 0:7 SXFER_REG negotiated value for this device
* 8:15 Current queue depth
* 16 negotiated SYNC flag
* 17 begin SYNC negotiation flag
* 18 device supports tag queueing */
#define NCR_700_DEV_NEGOTIATED_SYNC (1<<16)
#define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION (1<<17)
#define NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19)
static inline char *NCR_700_get_sense_cmnd(struct scsi_device *SDp)
{
struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
return hostdata->cmnd;
}
static inline void
NCR_700_set_depth(struct scsi_device *SDp, __u8 depth)
{
struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
hostdata->depth = depth;
}
static inline __u8
NCR_700_get_depth(struct scsi_device *SDp)
{
struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
return hostdata->depth;
}
static inline int
NCR_700_is_flag_set(struct scsi_device *SDp, __u32 flag)
{
return (spi_flags(SDp->sdev_target) & flag) == flag;
}
static inline int
NCR_700_is_flag_clear(struct scsi_device *SDp, __u32 flag)
{
return (spi_flags(SDp->sdev_target) & flag) == 0;
}
static inline void
NCR_700_set_flag(struct scsi_device *SDp, __u32 flag)
{
spi_flags(SDp->sdev_target) |= flag;
}
static inline void
NCR_700_clear_flag(struct scsi_device *SDp, __u32 flag)
{
spi_flags(SDp->sdev_target) &= ~flag;
}
enum NCR_700_tag_neg_state {
NCR_700_START_TAG_NEGOTIATION = 0,
NCR_700_DURING_TAG_NEGOTIATION = 1,
NCR_700_FINISHED_TAG_NEGOTIATION = 2,
};
static inline enum NCR_700_tag_neg_state
NCR_700_get_tag_neg_state(struct scsi_device *SDp)
{
return (enum NCR_700_tag_neg_state)((spi_flags(SDp->sdev_target)>>20) & 0x3);
}
static inline void
NCR_700_set_tag_neg_state(struct scsi_device *SDp,
enum NCR_700_tag_neg_state state)
{
/* clear the slot */
spi_flags(SDp->sdev_target) &= ~(0x3 << 20);
spi_flags(SDp->sdev_target) |= ((__u32)state) << 20;
}
struct NCR_700_command_slot {
struct NCR_700_SG_List SG[NCR_700_SG_SEGMENTS+1];
struct NCR_700_SG_List *pSG;
#define NCR_700_SLOT_MASK 0xFC
#define NCR_700_SLOT_MAGIC 0xb8
#define NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */
#define NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */
#define NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */
__u8 state;
#define NCR_700_FLAG_AUTOSENSE 0x01
__u8 flags;
__u8 pad1[2]; /* Needed for m68k where min alignment is 2 bytes */
int tag;
__u32 resume_offset;
struct scsi_cmnd *cmnd;
/* The pci_mapped address of the actual command in cmnd */
dma_addr_t pCmd;
__u32 temp;
/* if this command is a pci_single mapping, holds the dma address
* for later unmapping in the done routine */
dma_addr_t dma_handle;
/* historical remnant, now used to link free commands */
struct NCR_700_command_slot *ITL_forw;
};
struct NCR_700_Host_Parameters {
/* These must be filled in by the calling driver */
int clock; /* board clock speed in MHz */
void __iomem *base; /* the base for the port (copied to host) */
struct device *dev;
__u32 dmode_extra; /* adjustable bus settings */
__u32 dcntl_extra; /* adjustable bus settings */
__u32 ctest7_extra; /* adjustable bus settings */
__u32 differential:1; /* if we are differential */
#ifdef CONFIG_53C700_LE_ON_BE
/* This option is for HP only. Set it if your chip is wired for
* little endian on this platform (which is big endian) */
__u32 force_le_on_be:1;
#endif
__u32 chip710:1; /* set if really a 710 not 700 */
__u32 burst_length:4; /* set to 0 to disable 710 bursting */
/* NOTHING BELOW HERE NEEDS ALTERING */
__u32 fast:1; /* if we can alter the SCSI bus clock
speed (so can negiotiate sync) */
int sync_clock; /* The speed of the SYNC core */
__u32 *script; /* pointer to script location */
__u32 pScript; /* physical mem addr of script */
enum NCR_700_Host_State state; /* protected by state lock */
struct scsi_cmnd *cmd;
/* Note: pScript contains the single consistent block of
* memory. All the msgin, msgout and status are allocated in
* this memory too (at separate cache lines). TOTAL_MEM_SIZE
* represents the total size of this area */
#define MSG_ARRAY_SIZE 8
#define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT)))
__u8 *msgout;
#define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
__u8 *msgin;
#define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
__u8 *status;
#define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
struct NCR_700_command_slot *slots;
#define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST))
int saved_slot_position;
int command_slot_count; /* protected by state lock */
__u8 tag_negotiated;
__u8 rev;
__u8 reselection_id;
__u8 min_period;
/* Free list, singly linked by ITL_forw elements */
struct NCR_700_command_slot *free_list;
/* Completion for waited for ops, like reset, abort or
* device reset.
*
* NOTE: relies on single threading in the error handler to
* have only one outstanding at once */
struct completion *eh_complete;
};
/*
* 53C700 Register Interface - the offset from the Selected base
* I/O address */
#ifdef CONFIG_53C700_LE_ON_BE
#define bE (hostdata->force_le_on_be ? 0 : 3)
#define bSWAP (hostdata->force_le_on_be)
#define bEBus (!hostdata->force_le_on_be)
#elif defined(__BIG_ENDIAN)
#define bE 3
#define bSWAP 0
#elif defined(__LITTLE_ENDIAN)
#define bE 0
#define bSWAP 0
#else
#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?"
#endif
#ifndef bEBus
#ifdef CONFIG_53C700_BE_BUS
#define bEBus 1
#else
#define bEBus 0
#endif
#endif
#define bS_to_cpu(x) (bSWAP ? le32_to_cpu(x) : (x))
#define bS_to_host(x) (bSWAP ? cpu_to_le32(x) : (x))
/* NOTE: These registers are in the LE register space only, the required byte
* swapping is done by the NCR_700_{read|write}[b] functions */
#define SCNTL0_REG 0x00
#define FULL_ARBITRATION 0xc0
#define PARITY 0x08
#define ENABLE_PARITY 0x04
#define AUTO_ATN 0x02
#define SCNTL1_REG 0x01
#define SLOW_BUS 0x80
#define ENABLE_SELECT 0x20
#define ASSERT_RST 0x08
#define ASSERT_EVEN_PARITY 0x04
#define SDID_REG 0x02
#define SIEN_REG 0x03
#define PHASE_MM_INT 0x80
#define FUNC_COMP_INT 0x40
#define SEL_TIMEOUT_INT 0x20
#define SELECT_INT 0x10
#define GROSS_ERR_INT 0x08
#define UX_DISC_INT 0x04
#define RST_INT 0x02
#define PAR_ERR_INT 0x01
#define SCID_REG 0x04
#define SXFER_REG 0x05
#define ASYNC_OPERATION 0x00
#define SODL_REG 0x06
#define SOCL_REG 0x07
#define SFBR_REG 0x08
#define SIDL_REG 0x09
#define SBDL_REG 0x0A
#define SBCL_REG 0x0B
/* read bits */
#define SBCL_IO 0x01
/*write bits */
#define SYNC_DIV_AS_ASYNC 0x00
#define SYNC_DIV_1_0 0x01
#define SYNC_DIV_1_5 0x02
#define SYNC_DIV_2_0 0x03
#define DSTAT_REG 0x0C
#define ILGL_INST_DETECTED 0x01
#define WATCH_DOG_INTERRUPT 0x02
#define SCRIPT_INT_RECEIVED 0x04
#define ABORTED 0x10
#define SSTAT0_REG 0x0D
#define PARITY_ERROR 0x01
#define SCSI_RESET_DETECTED 0x02
#define UNEXPECTED_DISCONNECT 0x04
#define SCSI_GROSS_ERROR 0x08
#define SELECTED 0x10
#define SELECTION_TIMEOUT 0x20
#define FUNCTION_COMPLETE 0x40
#define PHASE_MISMATCH 0x80
#define SSTAT1_REG 0x0E
#define SIDL_REG_FULL 0x80
#define SODR_REG_FULL 0x40
#define SODL_REG_FULL 0x20
#define SSTAT2_REG 0x0F
#define CTEST0_REG 0x14
#define BTB_TIMER_DISABLE 0x40
#define CTEST1_REG 0x15
#define CTEST2_REG 0x16
#define CTEST3_REG 0x17
#define CTEST4_REG 0x18
#define DISABLE_FIFO 0x00
#define SLBE 0x10
#define SFWR 0x08
#define BYTE_LANE0 0x04
#define BYTE_LANE1 0x05
#define BYTE_LANE2 0x06
#define BYTE_LANE3 0x07
#define SCSI_ZMODE 0x20
#define ZMODE 0x40
#define CTEST5_REG 0x19
#define MASTER_CONTROL 0x10
#define DMA_DIRECTION 0x08
#define CTEST7_REG 0x1B
#define BURST_DISABLE 0x80 /* 710 only */
#define SEL_TIMEOUT_DISABLE 0x10 /* 710 only */
#define DFP 0x08
#define EVP 0x04
#define CTEST7_TT1 0x02
#define DIFF 0x01
#define CTEST6_REG 0x1A
#define TEMP_REG 0x1C
#define DFIFO_REG 0x20
#define FLUSH_DMA_FIFO 0x80
#define CLR_FIFO 0x40
#define ISTAT_REG 0x21
#define ABORT_OPERATION 0x80
#define SOFTWARE_RESET_710 0x40
#define DMA_INT_PENDING 0x01
#define SCSI_INT_PENDING 0x02
#define CONNECTED 0x08
#define CTEST8_REG 0x22
#define LAST_DIS_ENBL 0x01
#define SHORTEN_FILTERING 0x04
#define ENABLE_ACTIVE_NEGATION 0x10
#define GENERATE_RECEIVE_PARITY 0x20
#define CLR_FIFO_710 0x04
#define FLUSH_DMA_FIFO_710 0x08
#define CTEST9_REG 0x23
#define DBC_REG 0x24
#define DCMD_REG 0x27
#define DNAD_REG 0x28
#define DIEN_REG 0x39
#define BUS_FAULT 0x20
#define ABORT_INT 0x10
#define INT_INST_INT 0x04
#define WD_INT 0x02
#define ILGL_INST_INT 0x01
#define DCNTL_REG 0x3B
#define SOFTWARE_RESET 0x01
#define COMPAT_700_MODE 0x01
#define SCRPTS_16BITS 0x20
#define EA_710 0x20
#define ASYNC_DIV_2_0 0x00
#define ASYNC_DIV_1_5 0x40
#define ASYNC_DIV_1_0 0x80
#define ASYNC_DIV_3_0 0xc0
#define DMODE_710_REG 0x38
#define DMODE_700_REG 0x34
#define BURST_LENGTH_1 0x00
#define BURST_LENGTH_2 0x40
#define BURST_LENGTH_4 0x80
#define BURST_LENGTH_8 0xC0
#define DMODE_FC1 0x10
#define DMODE_FC2 0x20
#define BW16 32
#define MODE_286 16
#define IO_XFER 8
#define FIXED_ADDR 4
#define DSP_REG 0x2C
#define DSPS_REG 0x30
/* Parameters to begin SDTR negotiations. Empirically, I find that
* the 53c700-66 cannot handle an offset >8, so don't change this */
#define NCR_700_MAX_OFFSET 8
/* Was hoping the max offset would be greater for the 710, but
* empirically it seems to be 8 also */
#define NCR_710_MAX_OFFSET 8
#define NCR_700_MIN_XFERP 1
#define NCR_710_MIN_XFERP 0
#define NCR_700_MIN_PERIOD 25 /* for SDTR message, 100ns */
#define script_patch_32(dev, script, symbol, value) \
{ \
int i; \
for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
__u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + value; \
(script)[A_##symbol##_used[i]] = bS_to_host(val); \
dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
DEBUG((" script, patching %s at %d to 0x%lx\n", \
#symbol, A_##symbol##_used[i], (value))); \
} \
}
#define script_patch_32_abs(dev, script, symbol, value) \
{ \
int i; \
for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
(script)[A_##symbol##_used[i]] = bS_to_host(value); \
dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
DEBUG((" script, patching %s at %d to 0x%lx\n", \
#symbol, A_##symbol##_used[i], (value))); \
} \
}
/* Used for patching the SCSI ID in the SELECT instruction */
#define script_patch_ID(dev, script, symbol, value) \
{ \
int i; \
for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
__u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
val &= 0xff00ffff; \
val |= ((value) & 0xff) << 16; \
(script)[A_##symbol##_used[i]] = bS_to_host(val); \
dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
DEBUG((" script, patching ID field %s at %d to 0x%x\n", \
#symbol, A_##symbol##_used[i], val)); \
} \
}
#define script_patch_16(dev, script, symbol, value) \
{ \
int i; \
for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
__u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
val &= 0xffff0000; \
val |= ((value) & 0xffff); \
(script)[A_##symbol##_used[i]] = bS_to_host(val); \
dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
DEBUG((" script, patching short field %s at %d to 0x%x\n", \
#symbol, A_##symbol##_used[i], val)); \
} \
}
static inline __u8
NCR_700_readb(struct Scsi_Host *host, __u32 reg)
{
const struct NCR_700_Host_Parameters *hostdata
= (struct NCR_700_Host_Parameters *)host->hostdata[0];
return ioread8(hostdata->base + (reg^bE));
}
static inline __u32
NCR_700_readl(struct Scsi_Host *host, __u32 reg)
{
const struct NCR_700_Host_Parameters *hostdata
= (struct NCR_700_Host_Parameters *)host->hostdata[0];
__u32 value = bEBus ? ioread32be(hostdata->base + reg) :
ioread32(hostdata->base + reg);
#if 1
/* sanity check the register */
BUG_ON((reg & 0x3) != 0);
#endif
return value;
}
static inline void
NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
{
const struct NCR_700_Host_Parameters *hostdata
= (struct NCR_700_Host_Parameters *)host->hostdata[0];
iowrite8(value, hostdata->base + (reg^bE));
}
static inline void
NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
{
const struct NCR_700_Host_Parameters *hostdata
= (struct NCR_700_Host_Parameters *)host->hostdata[0];
#if 1
/* sanity check the register */
BUG_ON((reg & 0x3) != 0);
#endif
bEBus ? iowrite32be(value, hostdata->base + reg):
iowrite32(value, hostdata->base + reg);
}
#endif

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; Script for the NCR (or symbios) 53c700 and 53c700-66 chip
;
; Copyright (C) 2001 James.Bottomley@HansenPartnership.com
;;-----------------------------------------------------------------------------
;;
;; This program is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2 of the License, or
;; (at your option) any later version.
;;
;; This program is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with this program; if not, write to the Free Software
;; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
;;
;;-----------------------------------------------------------------------------
;
; This script is designed to be modified for the particular command in
; operation. The particular variables pertaining to the commands are:
;
ABSOLUTE Device_ID = 0 ; ID of target for command
ABSOLUTE MessageCount = 0 ; Number of bytes in message
ABSOLUTE MessageLocation = 0 ; Addr of message
ABSOLUTE CommandCount = 0 ; Number of bytes in command
ABSOLUTE CommandAddress = 0 ; Addr of Command
ABSOLUTE StatusAddress = 0 ; Addr to receive status return
ABSOLUTE ReceiveMsgAddress = 0 ; Addr to receive msg
;
; This is the magic component for handling scatter-gather. Each of the
; SG components is preceded by a script fragment which moves the
; necessary amount of data and jumps to the next SG segment. The final
; SG segment jumps back to . However, this address is the first SG script
; segment.
;
ABSOLUTE SGScriptStartAddress = 0
; The following represent status interrupts we use 3 hex digits for
; this: 0xPRS where
; P:
ABSOLUTE AFTER_SELECTION = 0x100
ABSOLUTE BEFORE_CMD = 0x200
ABSOLUTE AFTER_CMD = 0x300
ABSOLUTE AFTER_STATUS = 0x400
ABSOLUTE AFTER_DATA_IN = 0x500
ABSOLUTE AFTER_DATA_OUT = 0x600
ABSOLUTE DURING_DATA_IN = 0x700
; R:
ABSOLUTE NOT_MSG_OUT = 0x10
ABSOLUTE UNEXPECTED_PHASE = 0x20
ABSOLUTE NOT_MSG_IN = 0x30
ABSOLUTE UNEXPECTED_MSG = 0x40
ABSOLUTE MSG_IN = 0x50
ABSOLUTE SDTR_MSG_R = 0x60
ABSOLUTE REJECT_MSG_R = 0x70
ABSOLUTE DISCONNECT = 0x80
ABSOLUTE MSG_OUT = 0x90
ABSOLUTE WDTR_MSG_R = 0xA0
; S:
ABSOLUTE GOOD_STATUS = 0x1
; Combinations, since the script assembler can't process |
ABSOLUTE NOT_MSG_OUT_AFTER_SELECTION = 0x110
ABSOLUTE UNEXPECTED_PHASE_BEFORE_CMD = 0x220
ABSOLUTE UNEXPECTED_PHASE_AFTER_CMD = 0x320
ABSOLUTE NOT_MSG_IN_AFTER_STATUS = 0x430
ABSOLUTE GOOD_STATUS_AFTER_STATUS = 0x401
ABSOLUTE UNEXPECTED_PHASE_AFTER_DATA_IN = 0x520
ABSOLUTE UNEXPECTED_PHASE_AFTER_DATA_OUT = 0x620
ABSOLUTE UNEXPECTED_MSG_BEFORE_CMD = 0x240
ABSOLUTE MSG_IN_BEFORE_CMD = 0x250
ABSOLUTE MSG_IN_AFTER_CMD = 0x350
ABSOLUTE SDTR_MSG_BEFORE_CMD = 0x260
ABSOLUTE REJECT_MSG_BEFORE_CMD = 0x270
ABSOLUTE DISCONNECT_AFTER_CMD = 0x380
ABSOLUTE SDTR_MSG_AFTER_CMD = 0x360
ABSOLUTE WDTR_MSG_AFTER_CMD = 0x3A0
ABSOLUTE MSG_IN_AFTER_STATUS = 0x440
ABSOLUTE DISCONNECT_AFTER_DATA = 0x580
ABSOLUTE MSG_IN_AFTER_DATA_IN = 0x550
ABSOLUTE MSG_IN_AFTER_DATA_OUT = 0x650
ABSOLUTE MSG_OUT_AFTER_DATA_IN = 0x590
ABSOLUTE DATA_IN_AFTER_DATA_IN = 0x5a0
ABSOLUTE MSG_IN_DURING_DATA_IN = 0x750
ABSOLUTE DISCONNECT_DURING_DATA = 0x780
;
; Other interrupt conditions
;
ABSOLUTE RESELECTED_DURING_SELECTION = 0x1000
ABSOLUTE COMPLETED_SELECTION_AS_TARGET = 0x1001
ABSOLUTE RESELECTION_IDENTIFIED = 0x1003
;
; Fatal interrupt conditions. If you add to this, also add to the
; array of corresponding messages
;
ABSOLUTE FATAL = 0x2000
ABSOLUTE FATAL_UNEXPECTED_RESELECTION_MSG = 0x2000
ABSOLUTE FATAL_SEND_MSG = 0x2001
ABSOLUTE FATAL_NOT_MSG_IN_AFTER_SELECTION = 0x2002
ABSOLUTE FATAL_ILLEGAL_MSG_LENGTH = 0x2003
ABSOLUTE DEBUG_INTERRUPT = 0x3000
ABSOLUTE DEBUG_INTERRUPT1 = 0x3001
ABSOLUTE DEBUG_INTERRUPT2 = 0x3002
ABSOLUTE DEBUG_INTERRUPT3 = 0x3003
ABSOLUTE DEBUG_INTERRUPT4 = 0x3004
ABSOLUTE DEBUG_INTERRUPT5 = 0x3005
ABSOLUTE DEBUG_INTERRUPT6 = 0x3006
;
; SCSI Messages we interpret in the script
;
ABSOLUTE COMMAND_COMPLETE_MSG = 0x00
ABSOLUTE EXTENDED_MSG = 0x01
ABSOLUTE SDTR_MSG = 0x01
ABSOLUTE SAVE_DATA_PTRS_MSG = 0x02
ABSOLUTE RESTORE_DATA_PTRS_MSG = 0x03
ABSOLUTE WDTR_MSG = 0x03
ABSOLUTE DISCONNECT_MSG = 0x04
ABSOLUTE REJECT_MSG = 0x07
ABSOLUTE PARITY_ERROR_MSG = 0x09
ABSOLUTE SIMPLE_TAG_MSG = 0x20
ABSOLUTE IDENTIFY_MSG = 0x80
ABSOLUTE IDENTIFY_MSG_MASK = 0x7F
ABSOLUTE TWO_BYTE_MSG = 0x20
ABSOLUTE TWO_BYTE_MSG_MASK = 0x0F
; This is where the script begins
ENTRY StartUp
StartUp:
SELECT ATN Device_ID, Reselect
JUMP Finish, WHEN STATUS
JUMP SendIdentifyMsg, IF MSG_OUT
INT NOT_MSG_OUT_AFTER_SELECTION
Reselect:
WAIT RESELECT SelectedAsTarget
INT RESELECTED_DURING_SELECTION, WHEN MSG_IN
INT FATAL_NOT_MSG_IN_AFTER_SELECTION
ENTRY GetReselectionData
GetReselectionData:
MOVE 1, ReceiveMsgAddress, WHEN MSG_IN
INT RESELECTION_IDENTIFIED
ENTRY GetReselectionWithTag
GetReselectionWithTag:
MOVE 3, ReceiveMsgAddress, WHEN MSG_IN
INT RESELECTION_IDENTIFIED
ENTRY SelectedAsTarget
SelectedAsTarget:
; Basically tell the selecting device that there's nothing here
SET TARGET
DISCONNECT
CLEAR TARGET
INT COMPLETED_SELECTION_AS_TARGET
;
; These are the messaging entries
;
; Send a message. Message count should be correctly patched
ENTRY SendMessage
SendMessage:
MOVE MessageCount, MessageLocation, WHEN MSG_OUT
ResumeSendMessage:
RETURN, WHEN NOT MSG_OUT
INT FATAL_SEND_MSG
ENTRY SendMessagePhaseMismatch
SendMessagePhaseMismatch:
CLEAR ACK
JUMP ResumeSendMessage
;
; Receive a message. Need to identify the message to
; receive it correctly
ENTRY ReceiveMessage
ReceiveMessage:
MOVE 1, ReceiveMsgAddress, WHEN MSG_IN
;
; Use this entry if we've just tried to look at the first byte
; of the message and want to process it further
ProcessReceiveMessage:
JUMP ReceiveExtendedMessage, IF EXTENDED_MSG
RETURN, IF NOT TWO_BYTE_MSG, AND MASK TWO_BYTE_MSG_MASK
CLEAR ACK
MOVE 1, ReceiveMsgAddress + 1, WHEN MSG_IN
RETURN
ReceiveExtendedMessage:
CLEAR ACK
MOVE 1, ReceiveMsgAddress + 1, WHEN MSG_IN
JUMP Receive1Byte, IF 0x01
JUMP Receive2Byte, IF 0x02
JUMP Receive3Byte, IF 0x03
JUMP Receive4Byte, IF 0x04
JUMP Receive5Byte, IF 0x05
INT FATAL_ILLEGAL_MSG_LENGTH
Receive1Byte:
CLEAR ACK
MOVE 1, ReceiveMsgAddress + 2, WHEN MSG_IN
RETURN
Receive2Byte:
CLEAR ACK
MOVE 2, ReceiveMsgAddress + 2, WHEN MSG_IN
RETURN
Receive3Byte:
CLEAR ACK
MOVE 3, ReceiveMsgAddress + 2, WHEN MSG_IN
RETURN
Receive4Byte:
CLEAR ACK
MOVE 4, ReceiveMsgAddress + 2, WHEN MSG_IN
RETURN
Receive5Byte:
CLEAR ACK
MOVE 5, ReceiveMsgAddress + 2, WHEN MSG_IN
RETURN
;
; Come here from the message processor to ignore the message
;
ENTRY IgnoreMessage
IgnoreMessage:
CLEAR ACK
RETURN
;
; Come here to send a reply to a message
;
ENTRY SendMessageWithATN
SendMessageWithATN:
SET ATN
CLEAR ACK
JUMP SendMessage
SendIdentifyMsg:
CALL SendMessage
CLEAR ATN
IgnoreMsgBeforeCommand:
CLEAR ACK
ENTRY SendCommand
SendCommand:
JUMP Finish, WHEN STATUS
JUMP MsgInBeforeCommand, IF MSG_IN
INT UNEXPECTED_PHASE_BEFORE_CMD, IF NOT CMD
MOVE CommandCount, CommandAddress, WHEN CMD
ResumeSendCommand:
JUMP Finish, WHEN STATUS
JUMP MsgInAfterCmd, IF MSG_IN
JUMP DataIn, IF DATA_IN
JUMP DataOut, IF DATA_OUT
INT UNEXPECTED_PHASE_AFTER_CMD
IgnoreMsgDuringData:
CLEAR ACK
; fall through to MsgInDuringData
Entry MsgInDuringData
MsgInDuringData:
;
; Could be we have nothing more to transfer
;
JUMP Finish, WHEN STATUS
MOVE 1, ReceiveMsgAddress, WHEN MSG_IN
JUMP DisconnectDuringDataIn, IF DISCONNECT_MSG
JUMP IgnoreMsgDuringData, IF SAVE_DATA_PTRS_MSG
JUMP IgnoreMsgDuringData, IF RESTORE_DATA_PTRS_MSG
INT MSG_IN_DURING_DATA_IN
MsgInAfterCmd:
MOVE 1, ReceiveMsgAddress, WHEN MSG_IN
JUMP DisconnectAfterCmd, IF DISCONNECT_MSG
JUMP IgnoreMsgInAfterCmd, IF SAVE_DATA_PTRS_MSG
JUMP IgnoreMsgInAfterCmd, IF RESTORE_DATA_PTRS_MSG
CALL ProcessReceiveMessage
INT MSG_IN_AFTER_CMD
CLEAR ACK
JUMP ResumeSendCommand
IgnoreMsgInAfterCmd:
CLEAR ACK
JUMP ResumeSendCommand
DisconnectAfterCmd:
CLEAR ACK
WAIT DISCONNECT
ENTRY Disconnect1
Disconnect1:
INT DISCONNECT_AFTER_CMD
ENTRY Disconnect2
Disconnect2:
; We return here after a reselection
CLEAR ACK
JUMP ResumeSendCommand
MsgInBeforeCommand:
MOVE 1, ReceiveMsgAddress, WHEN MSG_IN
JUMP IgnoreMsgBeforeCommand, IF SAVE_DATA_PTRS_MSG
JUMP IgnoreMsgBeforeCommand, IF RESTORE_DATA_PTRS_MSG
CALL ProcessReceiveMessage
INT MSG_IN_BEFORE_CMD
CLEAR ACK
JUMP SendCommand
DataIn:
CALL SGScriptStartAddress
ResumeDataIn:
JUMP Finish, WHEN STATUS
JUMP MsgInAfterDataIn, IF MSG_IN
JUMP DataInAfterDataIn, if DATA_IN
INT MSG_OUT_AFTER_DATA_IN, if MSG_OUT
INT UNEXPECTED_PHASE_AFTER_DATA_IN
DataInAfterDataIn:
INT DATA_IN_AFTER_DATA_IN
JUMP ResumeDataIn
DataOut:
CALL SGScriptStartAddress
ResumeDataOut:
JUMP Finish, WHEN STATUS
JUMP MsgInAfterDataOut, IF MSG_IN
INT UNEXPECTED_PHASE_AFTER_DATA_OUT
MsgInAfterDataIn:
MOVE 1, ReceiveMsgAddress, WHEN MSG_IN
JUMP DisconnectAfterDataIn, IF DISCONNECT_MSG
JUMP IgnoreMsgAfterData, IF SAVE_DATA_PTRS_MSG
JUMP IgnoreMsgAfterData, IF RESTORE_DATA_PTRS_MSG
CALL ProcessReceiveMessage
INT MSG_IN_AFTER_DATA_IN
CLEAR ACK
JUMP ResumeDataIn
DisconnectDuringDataIn:
CLEAR ACK
WAIT DISCONNECT
ENTRY Disconnect3
Disconnect3:
INT DISCONNECT_DURING_DATA
ENTRY Disconnect4
Disconnect4:
; we return here after a reselection
CLEAR ACK
JUMP ResumeSendCommand
DisconnectAfterDataIn:
CLEAR ACK
WAIT DISCONNECT
ENTRY Disconnect5
Disconnect5:
INT DISCONNECT_AFTER_DATA
ENTRY Disconnect6
Disconnect6:
; we return here after a reselection
CLEAR ACK
JUMP ResumeDataIn
MsgInAfterDataOut:
MOVE 1, ReceiveMsgAddress, WHEN MSG_IN
JUMP DisconnectAfterDataOut, if DISCONNECT_MSG
JUMP IgnoreMsgAfterData, IF SAVE_DATA_PTRS_MSG
JUMP IgnoreMsgAfterData, IF RESTORE_DATA_PTRS_MSG
CALL ProcessReceiveMessage
INT MSG_IN_AFTER_DATA_OUT
CLEAR ACK
JUMP ResumeDataOut
IgnoreMsgAfterData:
CLEAR ACK
; Data in and out do the same thing on resume, so pick one
JUMP ResumeDataIn
DisconnectAfterDataOut:
CLEAR ACK
WAIT DISCONNECT
ENTRY Disconnect7
Disconnect7:
INT DISCONNECT_AFTER_DATA
ENTRY Disconnect8
Disconnect8:
; we return here after a reselection
CLEAR ACK
JUMP ResumeDataOut
Finish:
MOVE 1, StatusAddress, WHEN STATUS
INT NOT_MSG_IN_AFTER_STATUS, WHEN NOT MSG_IN
MOVE 1, ReceiveMsgAddress, WHEN MSG_IN
JUMP FinishCommandComplete, IF COMMAND_COMPLETE_MSG
CALL ProcessReceiveMessage
INT MSG_IN_AFTER_STATUS
ENTRY FinishCommandComplete
FinishCommandComplete:
CLEAR ACK
WAIT DISCONNECT
ENTRY Finish1
Finish1:
INT GOOD_STATUS_AFTER_STATUS
ENTRY Finish2
Finish2:

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#
# Makefile for linux/drivers/scsi
#
# 30 May 2000, Christoph Hellwig <hch@infradead.org>
# Rewritten to use lists instead of if-statements.
#
# 20 Sep 2000, Torben Mathiasen <tmm@image.dk>
# Changed link order to reflect new scsi initialization.
#
# *!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!
# The link order must be, SCSI Core, SCSI HBA drivers, and
# lastly SCSI peripheral drivers (disk/tape/cdrom/etc.) to
# satisfy certain initialization assumptions in the SCSI layer.
# *!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!
CFLAGS_aha152x.o = -DAHA152X_STAT -DAUTOCONF
CFLAGS_gdth.o = # -DDEBUG_GDTH=2 -D__SERIAL__ -D__COM2__ -DGDTH_STATISTICS
obj-$(CONFIG_PCMCIA) += pcmcia/
obj-$(CONFIG_SCSI) += scsi_mod.o
obj-$(CONFIG_RAID_ATTRS) += raid_class.o
# --- NOTE ORDERING HERE ---
# For kernel non-modular link, transport attributes need to
# be initialised before drivers
# --------------------------
obj-$(CONFIG_SCSI_SPI_ATTRS) += scsi_transport_spi.o
obj-$(CONFIG_SCSI_FC_ATTRS) += scsi_transport_fc.o
obj-$(CONFIG_SCSI_ISCSI_ATTRS) += scsi_transport_iscsi.o
obj-$(CONFIG_SCSI_SAS_ATTRS) += scsi_transport_sas.o
obj-$(CONFIG_SCSI_SAS_LIBSAS) += libsas/
obj-$(CONFIG_SCSI_SRP_ATTRS) += scsi_transport_srp.o
obj-$(CONFIG_SCSI_DH) += device_handler/
obj-$(CONFIG_LIBFC) += libfc/
obj-$(CONFIG_LIBFCOE) += fcoe/
obj-$(CONFIG_FCOE) += fcoe/
obj-$(CONFIG_FCOE_FNIC) += fnic/
obj-$(CONFIG_SCSI_BNX2X_FCOE) += libfc/ fcoe/ bnx2fc/
obj-$(CONFIG_ISCSI_TCP) += libiscsi.o libiscsi_tcp.o iscsi_tcp.o
obj-$(CONFIG_INFINIBAND_ISER) += libiscsi.o
obj-$(CONFIG_ISCSI_BOOT_SYSFS) += iscsi_boot_sysfs.o
obj-$(CONFIG_SCSI_A4000T) += 53c700.o a4000t.o
obj-$(CONFIG_SCSI_ZORRO7XX) += 53c700.o zorro7xx.o
obj-$(CONFIG_A3000_SCSI) += a3000.o wd33c93.o
obj-$(CONFIG_A2091_SCSI) += a2091.o wd33c93.o
obj-$(CONFIG_GVP11_SCSI) += gvp11.o wd33c93.o
obj-$(CONFIG_MVME147_SCSI) += mvme147.o wd33c93.o
obj-$(CONFIG_SGIWD93_SCSI) += sgiwd93.o wd33c93.o
obj-$(CONFIG_ATARI_SCSI) += atari_scsi.o
obj-$(CONFIG_MAC_SCSI) += mac_scsi.o
obj-$(CONFIG_SCSI_MAC_ESP) += esp_scsi.o mac_esp.o
obj-$(CONFIG_SUN3_SCSI) += sun3_scsi.o sun3_scsi_vme.o
obj-$(CONFIG_MVME16x_SCSI) += 53c700.o mvme16x_scsi.o
obj-$(CONFIG_BVME6000_SCSI) += 53c700.o bvme6000_scsi.o
obj-$(CONFIG_SCSI_SIM710) += 53c700.o sim710.o
obj-$(CONFIG_SCSI_ADVANSYS) += advansys.o
obj-$(CONFIG_SCSI_BUSLOGIC) += BusLogic.o
obj-$(CONFIG_SCSI_DPT_I2O) += dpt_i2o.o
obj-$(CONFIG_SCSI_U14_34F) += u14-34f.o
obj-$(CONFIG_SCSI_ARCMSR) += arcmsr/
obj-$(CONFIG_SCSI_ULTRASTOR) += ultrastor.o
obj-$(CONFIG_SCSI_AHA152X) += aha152x.o
obj-$(CONFIG_SCSI_AHA1542) += aha1542.o
obj-$(CONFIG_SCSI_AHA1740) += aha1740.o
obj-$(CONFIG_SCSI_AIC7XXX) += aic7xxx/
obj-$(CONFIG_SCSI_AIC79XX) += aic7xxx/
obj-$(CONFIG_SCSI_AACRAID) += aacraid/
obj-$(CONFIG_SCSI_AIC94XX) += aic94xx/
obj-$(CONFIG_SCSI_PM8001) += pm8001/
obj-$(CONFIG_SCSI_ISCI) += isci/
obj-$(CONFIG_SCSI_IPS) += ips.o
obj-$(CONFIG_SCSI_FUTURE_DOMAIN)+= fdomain.o
obj-$(CONFIG_SCSI_IN2000) += in2000.o
obj-$(CONFIG_SCSI_GENERIC_NCR5380) += g_NCR5380.o
obj-$(CONFIG_SCSI_GENERIC_NCR5380_MMIO) += g_NCR5380_mmio.o
obj-$(CONFIG_SCSI_NCR53C406A) += NCR53c406a.o
obj-$(CONFIG_SCSI_NCR_D700) += 53c700.o NCR_D700.o
obj-$(CONFIG_SCSI_NCR_Q720) += NCR_Q720_mod.o
obj-$(CONFIG_SCSI_SYM53C416) += sym53c416.o
obj-$(CONFIG_SCSI_QLOGIC_FAS) += qlogicfas408.o qlogicfas.o
obj-$(CONFIG_PCMCIA_QLOGIC) += qlogicfas408.o
obj-$(CONFIG_SCSI_QLOGIC_1280) += qla1280.o
obj-$(CONFIG_SCSI_QLA_FC) += qla2xxx/
obj-$(CONFIG_SCSI_QLA_ISCSI) += libiscsi.o qla4xxx/
obj-$(CONFIG_SCSI_LPFC) += lpfc/
obj-$(CONFIG_SCSI_BFA_FC) += bfa/
obj-$(CONFIG_SCSI_CHELSIO_FCOE) += csiostor/
obj-$(CONFIG_SCSI_PAS16) += pas16.o
obj-$(CONFIG_SCSI_T128) += t128.o
obj-$(CONFIG_SCSI_DMX3191D) += dmx3191d.o
obj-$(CONFIG_SCSI_HPSA) += hpsa.o
obj-$(CONFIG_SCSI_DTC3280) += dtc.o
obj-$(CONFIG_SCSI_SYM53C8XX_2) += sym53c8xx_2/
obj-$(CONFIG_SCSI_ZALON) += zalon7xx.o
obj-$(CONFIG_SCSI_EATA_PIO) += eata_pio.o
obj-$(CONFIG_SCSI_7000FASST) += wd7000.o
obj-$(CONFIG_SCSI_EATA) += eata.o
obj-$(CONFIG_SCSI_DC395x) += dc395x.o
obj-$(CONFIG_SCSI_DC390T) += tmscsim.o
obj-$(CONFIG_MEGARAID_LEGACY) += megaraid.o
obj-$(CONFIG_MEGARAID_NEWGEN) += megaraid/
obj-$(CONFIG_MEGARAID_SAS) += megaraid/
obj-$(CONFIG_SCSI_MPT2SAS) += mpt2sas/
obj-$(CONFIG_SCSI_MPT3SAS) += mpt3sas/
obj-$(CONFIG_SCSI_UFSHCD) += ufs/
obj-$(CONFIG_SCSI_ACARD) += atp870u.o
obj-$(CONFIG_SCSI_SUNESP) += esp_scsi.o sun_esp.o
obj-$(CONFIG_SCSI_GDTH) += gdth.o
obj-$(CONFIG_SCSI_INITIO) += initio.o
obj-$(CONFIG_SCSI_INIA100) += a100u2w.o
obj-$(CONFIG_SCSI_QLOGICPTI) += qlogicpti.o
obj-$(CONFIG_SCSI_MESH) += mesh.o
obj-$(CONFIG_SCSI_MAC53C94) += mac53c94.o
obj-$(CONFIG_BLK_DEV_3W_XXXX_RAID) += 3w-xxxx.o
obj-$(CONFIG_SCSI_3W_9XXX) += 3w-9xxx.o
obj-$(CONFIG_SCSI_3W_SAS) += 3w-sas.o
obj-$(CONFIG_SCSI_PPA) += ppa.o
obj-$(CONFIG_SCSI_IMM) += imm.o
obj-$(CONFIG_JAZZ_ESP) += esp_scsi.o jazz_esp.o
obj-$(CONFIG_SUN3X_ESP) += esp_scsi.o sun3x_esp.o
obj-$(CONFIG_SCSI_LASI700) += 53c700.o lasi700.o
obj-$(CONFIG_SCSI_SNI_53C710) += 53c700.o sni_53c710.o
obj-$(CONFIG_SCSI_NSP32) += nsp32.o
obj-$(CONFIG_SCSI_IPR) += ipr.o
obj-$(CONFIG_SCSI_IBMVSCSI) += ibmvscsi/
obj-$(CONFIG_SCSI_IBMVFC) += ibmvscsi/
obj-$(CONFIG_SCSI_HPTIOP) += hptiop.o
obj-$(CONFIG_SCSI_STEX) += stex.o
obj-$(CONFIG_SCSI_MVSAS) += mvsas/
obj-$(CONFIG_SCSI_MVUMI) += mvumi.o
obj-$(CONFIG_PS3_ROM) += ps3rom.o
obj-$(CONFIG_SCSI_CXGB3_ISCSI) += libiscsi.o libiscsi_tcp.o cxgbi/
obj-$(CONFIG_SCSI_CXGB4_ISCSI) += libiscsi.o libiscsi_tcp.o cxgbi/
obj-$(CONFIG_SCSI_BNX2_ISCSI) += libiscsi.o bnx2i/
obj-$(CONFIG_BE2ISCSI) += libiscsi.o be2iscsi/
obj-$(CONFIG_SCSI_ESAS2R) += esas2r/
obj-$(CONFIG_SCSI_PMCRAID) += pmcraid.o
obj-$(CONFIG_SCSI_VIRTIO) += virtio_scsi.o
obj-$(CONFIG_VMWARE_PVSCSI) += vmw_pvscsi.o
obj-$(CONFIG_XEN_SCSI_FRONTEND) += xen-scsifront.o
obj-$(CONFIG_HYPERV_STORAGE) += hv_storvsc.o
obj-$(CONFIG_ARM) += arm/
obj-$(CONFIG_CHR_DEV_ST) += st.o
obj-$(CONFIG_CHR_DEV_OSST) += osst.o
obj-$(CONFIG_BLK_DEV_SD) += sd_mod.o
obj-$(CONFIG_BLK_DEV_SR) += sr_mod.o
obj-$(CONFIG_CHR_DEV_SG) += sg.o
obj-$(CONFIG_CHR_DEV_SCH) += ch.o
obj-$(CONFIG_SCSI_ENCLOSURE) += ses.o
obj-$(CONFIG_SCSI_OSD_INITIATOR) += osd/
# This goes last, so that "real" scsi devices probe earlier
obj-$(CONFIG_SCSI_DEBUG) += scsi_debug.o
scsi_mod-y += scsi.o hosts.o scsi_ioctl.o constants.o \
scsicam.o scsi_error.o scsi_lib.o
scsi_mod-$(CONFIG_SCSI_DMA) += scsi_lib_dma.o
scsi_mod-y += scsi_scan.o scsi_sysfs.o scsi_devinfo.o
scsi_mod-$(CONFIG_SCSI_NETLINK) += scsi_netlink.o
scsi_mod-$(CONFIG_SYSCTL) += scsi_sysctl.o
scsi_mod-$(CONFIG_SCSI_PROC_FS) += scsi_proc.o
scsi_mod-y += scsi_trace.o
scsi_mod-$(CONFIG_PM) += scsi_pm.o
hv_storvsc-y := storvsc_drv.o
sd_mod-objs := sd.o
sd_mod-$(CONFIG_BLK_DEV_INTEGRITY) += sd_dif.o
sr_mod-objs := sr.o sr_ioctl.o sr_vendor.o
ncr53c8xx-flags-$(CONFIG_SCSI_ZALON) \
:= -DCONFIG_NCR53C8XX_PREFETCH -DSCSI_NCR_BIG_ENDIAN \
-DCONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
CFLAGS_ncr53c8xx.o := $(ncr53c8xx-flags-y) $(ncr53c8xx-flags-m)
zalon7xx-objs := zalon.o ncr53c8xx.o
NCR_Q720_mod-objs := NCR_Q720.o ncr53c8xx.o
oktagon_esp_mod-objs := oktagon_esp.o oktagon_io.o
# Files generated that shall be removed upon make clean
clean-files := 53c700_d.h 53c700_u.h
$(obj)/53c700.o $(MODVERDIR)/$(obj)/53c700.ver: $(obj)/53c700_d.h
# If you want to play with the firmware, uncomment
# GENERATE_FIRMWARE := 1
ifdef GENERATE_FIRMWARE
$(obj)/53c700_d.h: $(src)/53c700.scr $(src)/script_asm.pl
$(PERL) -s $(src)/script_asm.pl -ncr7x0_family $@ $(@:_d.h=_u.h) < $<
endif

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/*
* NCR 5380 defines
*
* Copyright 1993, Drew Eckhardt
* Visionary Computing
* (Unix consulting and custom programming)
* drew@colorado.edu
* +1 (303) 666-5836
*
* DISTRIBUTION RELEASE 7
*
* For more information, please consult
*
* NCR 5380 Family
* SCSI Protocol Controller
* Databook
* NCR Microelectronics
* 1635 Aeroplaza Drive
* Colorado Springs, CO 80916
* 1+ (719) 578-3400
* 1+ (800) 334-5454
*/
#ifndef NCR5380_H
#define NCR5380_H
#include <linux/interrupt.h>
#ifdef AUTOSENSE
#include <scsi/scsi_eh.h>
#endif
#define NCR5380_PUBLIC_RELEASE 7
#define NCR53C400_PUBLIC_RELEASE 2
#define NDEBUG_ARBITRATION 0x1
#define NDEBUG_AUTOSENSE 0x2
#define NDEBUG_DMA 0x4
#define NDEBUG_HANDSHAKE 0x8
#define NDEBUG_INFORMATION 0x10
#define NDEBUG_INIT 0x20
#define NDEBUG_INTR 0x40
#define NDEBUG_LINKED 0x80
#define NDEBUG_MAIN 0x100
#define NDEBUG_NO_DATAOUT 0x200
#define NDEBUG_NO_WRITE 0x400
#define NDEBUG_PIO 0x800
#define NDEBUG_PSEUDO_DMA 0x1000
#define NDEBUG_QUEUES 0x2000
#define NDEBUG_RESELECTION 0x4000
#define NDEBUG_SELECTION 0x8000
#define NDEBUG_USLEEP 0x10000
#define NDEBUG_LAST_BYTE_SENT 0x20000
#define NDEBUG_RESTART_SELECT 0x40000
#define NDEBUG_EXTENDED 0x80000
#define NDEBUG_C400_PREAD 0x100000
#define NDEBUG_C400_PWRITE 0x200000
#define NDEBUG_LISTS 0x400000
#define NDEBUG_ABORT 0x800000
#define NDEBUG_TAGS 0x1000000
#define NDEBUG_MERGING 0x2000000
#define NDEBUG_ANY 0xFFFFFFFFUL
/*
* The contents of the OUTPUT DATA register are asserted on the bus when
* either arbitration is occurring or the phase-indicating signals (
* IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
* bit in the INITIATOR COMMAND register is set.
*/
#define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */
#define CURRENT_SCSI_DATA_REG 0 /* ro same */
#define INITIATOR_COMMAND_REG 1 /* rw */
#define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
#define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */
#define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
#define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */
#define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */
#define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
#define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
#define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
#define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
#define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
#ifdef DIFFERENTIAL
#define ICR_BASE ICR_DIFF_ENABLE
#else
#define ICR_BASE 0
#endif
#define MODE_REG 2
/*
* Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
* transfer, causing the chip to hog the bus. You probably don't want
* this.
*/
#define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
#define MR_TARGET 0x40 /* rw target mode */
#define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
#define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
#define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */
#define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
#define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
#define MR_ARBITRATE 0x01 /* rw start arbitration */
#ifdef PARITY
#define MR_BASE MR_ENABLE_PAR_CHECK
#else
#define MR_BASE 0
#endif
#define TARGET_COMMAND_REG 3
#define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */
#define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
#define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
#define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
#define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
#define STATUS_REG 4 /* ro */
/*
* Note : a set bit indicates an active signal, driven by us or another
* device.
*/
#define SR_RST 0x80
#define SR_BSY 0x40
#define SR_REQ 0x20
#define SR_MSG 0x10
#define SR_CD 0x08
#define SR_IO 0x04
#define SR_SEL 0x02
#define SR_DBP 0x01
/*
* Setting a bit in this register will cause an interrupt to be generated when
* BSY is false and SEL true and this bit is asserted on the bus.
*/
#define SELECT_ENABLE_REG 4 /* wo */
#define BUS_AND_STATUS_REG 5 /* ro */
#define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
#define BASR_DRQ 0x40 /* ro mirror of DRQ pin */
#define BASR_PARITY_ERROR 0x20 /* ro parity error detected */
#define BASR_IRQ 0x10 /* ro mirror of IRQ pin */
#define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */
#define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */
#define BASR_ATN 0x02 /* ro BUS status */
#define BASR_ACK 0x01 /* ro BUS status */
/* Write any value to this register to start a DMA send */
#define START_DMA_SEND_REG 5 /* wo */
/*
* Used in DMA transfer mode, data is latched from the SCSI bus on
* the falling edge of REQ (ini) or ACK (tgt)
*/
#define INPUT_DATA_REG 6 /* ro */
/* Write any value to this register to start a DMA receive */
#define START_DMA_TARGET_RECEIVE_REG 6 /* wo */
/* Read this register to clear interrupt conditions */
#define RESET_PARITY_INTERRUPT_REG 7 /* ro */
/* Write any value to this register to start an ini mode DMA receive */
#define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */
#define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */
#define CSR_RESET 0x80 /* wo Resets 53c400 */
#define CSR_53C80_REG 0x80 /* ro 5380 registers busy */
#define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
#define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
#define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */
#define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
#define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */
#define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */
#define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */
#if 0
#define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
#else
#define CSR_BASE CSR_53C80_INTR
#endif
/* Number of 128-byte blocks to be transferred */
#define C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7 /* rw */
/* Resume transfer after disconnect */
#define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6 /* wo */
/* Access to host buffer stack */
#define C400_HOST_BUFFER NCR53C400_register_offset-4 /* rw */
/* Note : PHASE_* macros are based on the values of the STATUS register */
#define PHASE_MASK (SR_MSG | SR_CD | SR_IO)
#define PHASE_DATAOUT 0
#define PHASE_DATAIN SR_IO
#define PHASE_CMDOUT SR_CD
#define PHASE_STATIN (SR_CD | SR_IO)
#define PHASE_MSGOUT (SR_MSG | SR_CD)
#define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO)
#define PHASE_UNKNOWN 0xff
/*
* Convert status register phase to something we can use to set phase in
* the target register so we can get phase mismatch interrupts on DMA
* transfers.
*/
#define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
/*
* The internal should_disconnect() function returns these based on the
* expected length of a disconnect if a device supports disconnect/
* reconnect.
*/
#define DISCONNECT_NONE 0
#define DISCONNECT_TIME_TO_DATA 1
#define DISCONNECT_LONG 2
/*
* These are "special" values for the tag parameter passed to NCR5380_select.
*/
#define TAG_NEXT -1 /* Use next free tag */
#define TAG_NONE -2 /*
* Establish I_T_L nexus instead of I_T_L_Q
* even on SCSI-II devices.
*/
/*
* These are "special" values for the irq and dma_channel fields of the
* Scsi_Host structure
*/
#define SCSI_IRQ_NONE 255
#define DMA_NONE 255
#define IRQ_AUTO 254
#define DMA_AUTO 254
#define PORT_AUTO 0xffff /* autoprobe io port for 53c400a */
#define FLAG_HAS_LAST_BYTE_SENT 1 /* NCR53c81 or better */
#define FLAG_CHECK_LAST_BYTE_SENT 2 /* Only test once */
#define FLAG_NCR53C400 4 /* NCR53c400 */
#define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */
#define FLAG_DTC3181E 16 /* DTC3181E */
#ifndef ASM
struct NCR5380_hostdata {
NCR5380_implementation_fields; /* implementation specific */
struct Scsi_Host *host; /* Host backpointer */
unsigned char id_mask, id_higher_mask; /* 1 << id, all bits greater */
unsigned char targets_present; /* targets we have connected
to, so we can call a select
failure a retryable condition */
volatile unsigned char busy[8]; /* index = target, bit = lun */
#if defined(REAL_DMA) || defined(REAL_DMA_POLL)
volatile int dma_len; /* requested length of DMA */
#endif
volatile unsigned char last_message; /* last message OUT */
volatile Scsi_Cmnd *connected; /* currently connected command */
volatile Scsi_Cmnd *issue_queue; /* waiting to be issued */
volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */
volatile int restart_select; /* we have disconnected,
used to restart
NCR5380_select() */
volatile unsigned aborted:1; /* flag, says aborted */
int flags;
unsigned long time_expires; /* in jiffies, set prior to sleeping */
int select_time; /* timer in select for target response */
volatile Scsi_Cmnd *selecting;
struct delayed_work coroutine; /* our co-routine */
#ifdef NCR5380_STATS
unsigned timebase; /* Base for time calcs */
long time_read[8]; /* time to do reads */
long time_write[8]; /* time to do writes */
unsigned long bytes_read[8]; /* bytes read */
unsigned long bytes_write[8]; /* bytes written */
unsigned pendingr;
unsigned pendingw;
#endif
#ifdef AUTOSENSE
struct scsi_eh_save ses;
#endif
};
#ifdef __KERNEL__
#ifndef NDEBUG
#define NDEBUG (0)
#endif
#define dprintk(flg, fmt, ...) \
do { if ((NDEBUG) & (flg)) pr_debug(fmt, ## __VA_ARGS__); } while (0)
#if NDEBUG
#define NCR5380_dprint(flg, arg) \
do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0)
#define NCR5380_dprint_phase(flg, arg) \
do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0)
static void NCR5380_print_phase(struct Scsi_Host *instance);
static void NCR5380_print(struct Scsi_Host *instance);
#else
#define NCR5380_dprint(flg, arg) do {} while (0)
#define NCR5380_dprint_phase(flg, arg) do {} while (0)
#endif
#if defined(AUTOPROBE_IRQ)
static int NCR5380_probe_irq(struct Scsi_Host *instance, int possible);
#endif
static int NCR5380_init(struct Scsi_Host *instance, int flags);
static void NCR5380_exit(struct Scsi_Host *instance);
static void NCR5380_information_transfer(struct Scsi_Host *instance);
#ifndef DONT_USE_INTR
static irqreturn_t NCR5380_intr(int irq, void *dev_id);
#endif
static void NCR5380_main(struct work_struct *work);
static void __maybe_unused NCR5380_print_options(struct Scsi_Host *instance);
static int NCR5380_abort(Scsi_Cmnd * cmd);
static int NCR5380_bus_reset(Scsi_Cmnd * cmd);
static int NCR5380_queue_command(struct Scsi_Host *, struct scsi_cmnd *);
static int __maybe_unused NCR5380_show_info(struct seq_file *,
struct Scsi_Host *);
static int __maybe_unused NCR5380_write_info(struct Scsi_Host *instance,
char *buffer, int length);
static void NCR5380_reselect(struct Scsi_Host *instance);
static int NCR5380_select(struct Scsi_Host *instance, Scsi_Cmnd * cmd, int tag);
#if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
#endif
static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
#if (defined(REAL_DMA) || defined(REAL_DMA_POLL))
#if defined(i386) || defined(__alpha__)
/**
* NCR5380_pc_dma_setup - setup ISA DMA
* @instance: adapter to set up
* @ptr: block to transfer (virtual address)
* @count: number of bytes to transfer
* @mode: DMA controller mode to use
*
* Program the DMA controller ready to perform an ISA DMA transfer
* on this chip.
*
* Locks: takes and releases the ISA DMA lock.
*/
static __inline__ int NCR5380_pc_dma_setup(struct Scsi_Host *instance, unsigned char *ptr, unsigned int count, unsigned char mode)
{
unsigned limit;
unsigned long bus_addr = virt_to_bus(ptr);
unsigned long flags;
if (instance->dma_channel <= 3) {
if (count > 65536)
count = 65536;
limit = 65536 - (bus_addr & 0xFFFF);
} else {
if (count > 65536 * 2)
count = 65536 * 2;
limit = 65536 * 2 - (bus_addr & 0x1FFFF);
}
if (count > limit)
count = limit;
if ((count & 1) || (bus_addr & 1))
panic("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
flags=claim_dma_lock();
disable_dma(instance->dma_channel);
clear_dma_ff(instance->dma_channel);
set_dma_addr(instance->dma_channel, bus_addr);
set_dma_count(instance->dma_channel, count);
set_dma_mode(instance->dma_channel, mode);
enable_dma(instance->dma_channel);
release_dma_lock(flags);
return count;
}
/**
* NCR5380_pc_dma_write_setup - setup ISA DMA write
* @instance: adapter to set up
* @ptr: block to transfer (virtual address)
* @count: number of bytes to transfer
*
* Program the DMA controller ready to perform an ISA DMA write to the
* SCSI controller.
*
* Locks: called routines take and release the ISA DMA lock.
*/
static __inline__ int NCR5380_pc_dma_write_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
{
return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_WRITE);
}
/**
* NCR5380_pc_dma_read_setup - setup ISA DMA read
* @instance: adapter to set up
* @ptr: block to transfer (virtual address)
* @count: number of bytes to transfer
*
* Program the DMA controller ready to perform an ISA DMA read from the
* SCSI controller.
*
* Locks: called routines take and release the ISA DMA lock.
*/
static __inline__ int NCR5380_pc_dma_read_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
{
return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_READ);
}
/**
* NCR5380_pc_dma_residual - return bytes left
* @instance: adapter
*
* Reports the number of bytes left over after the DMA was terminated.
*
* Locks: takes and releases the ISA DMA lock.
*/
static __inline__ int NCR5380_pc_dma_residual(struct Scsi_Host *instance)
{
unsigned long flags;
int tmp;
flags = claim_dma_lock();
clear_dma_ff(instance->dma_channel);
tmp = get_dma_residue(instance->dma_channel);
release_dma_lock(flags);
return tmp;
}
#endif /* defined(i386) || defined(__alpha__) */
#endif /* defined(REAL_DMA) */
#endif /* __KERNEL__ */
#endif /* ndef ASM */
#endif /* NCR5380_H */

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/* -*- mode: c; c-basic-offset: 8 -*- */
/* NCR Dual 700 MCA SCSI Driver
*
* Copyright (C) 2001 by James.Bottomley@HansenPartnership.com
**-----------------------------------------------------------------------------
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program; if not, write to the Free Software
** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
**
**-----------------------------------------------------------------------------
*/
/* Notes:
*
* Most of the work is done in the chip specific module, 53c700.o
*
* TODO List:
*
* 1. Extract the SCSI ID from the voyager CMOS table (necessary to
* support multi-host environments.
*
* */
/* CHANGELOG
*
* Version 2.2
*
* Added mca_set_adapter_name().
*
* Version 2.1
*
* Modularise the driver into a Board piece (this file) and a chip
* piece 53c700.[ch] and 53c700.scr, added module options. You can
* now specify the scsi id by the parameters
*
* NCR_D700=slot:<n> [siop:<n>] id:<n> ....
*
* They need to be comma separated if compiled into the kernel
*
* Version 2.0
*
* Initial implementation of TCQ (Tag Command Queueing). TCQ is full
* featured and uses the clock algorithm to keep track of outstanding
* tags and guard against individual tag starvation. Also fixed a bug
* in all of the 1.x versions where the D700_data_residue() function
* was returning results off by 32 bytes (and thus causing the same 32
* bytes to be written twice corrupting the data block). It turns out
* the 53c700 only has a 6 bit DBC and DFIFO registers not 7 bit ones
* like the 53c710 (The 710 is the only data manual still available,
* which I'd been using to program the 700).
*
* Version 1.2
*
* Much improved message handling engine
*
* Version 1.1
*
* Add code to handle selection reasonably correctly. By the time we
* get the selection interrupt, we've already responded, but drop off the
* bus and hope the selector will go away.
*
* Version 1.0:
*
* Initial release. Fully functional except for procfs and tag
* command queueing. Has only been tested on cards with 53c700-66
* chips and only single ended. Features are
*
* 1. Synchronous data transfers to offset 8 (limit of 700-66) and
* 100ns (10MHz) limit of SCSI-2
*
* 2. Disconnection and reselection
*
* Testing:
*
* I've only really tested this with the 700-66 chip, but have done
* soak tests in multi-device environments to verify that
* disconnections and reselections are being processed correctly.
* */
#define NCR_D700_VERSION "2.2"
#include <linux/blkdev.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mca.h>
#include <linux/slab.h>
#include <asm/io.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_transport.h>
#include <scsi/scsi_transport_spi.h>
#include "53c700.h"
#include "NCR_D700.h"
static char *NCR_D700; /* command line from insmod */
MODULE_AUTHOR("James Bottomley");
MODULE_DESCRIPTION("NCR Dual700 SCSI Driver");
MODULE_LICENSE("GPL");
module_param(NCR_D700, charp, 0);
static __u8 id_array[2*(MCA_MAX_SLOT_NR + 1)] =
{ [0 ... 2*(MCA_MAX_SLOT_NR + 1)-1] = 7 };
#ifdef MODULE
#define ARG_SEP ' '
#else
#define ARG_SEP ','
#endif
static int __init
param_setup(char *string)
{
char *pos = string, *next;
int slot = -1, siop = -1;
while(pos != NULL && (next = strchr(pos, ':')) != NULL) {
int val = (int)simple_strtoul(++next, NULL, 0);
if(!strncmp(pos, "slot:", 5))
slot = val;
else if(!strncmp(pos, "siop:", 5))
siop = val;
else if(!strncmp(pos, "id:", 3)) {
if(slot == -1) {
printk(KERN_WARNING "NCR D700: Must specify slot for id parameter\n");
} else if(slot > MCA_MAX_SLOT_NR) {
printk(KERN_WARNING "NCR D700: Illegal slot %d for id %d\n", slot, val);
} else {
if(siop != 0 && siop != 1) {
id_array[slot*2] = val;
id_array[slot*2 + 1] =val;
} else {
id_array[slot*2 + siop] = val;
}
}
}
if((pos = strchr(pos, ARG_SEP)) != NULL)
pos++;
}
return 1;
}
/* Host template. The 53c700 routine NCR_700_detect will
* fill in all of the missing routines */
static struct scsi_host_template NCR_D700_driver_template = {
.module = THIS_MODULE,
.name = "NCR Dual 700 MCA",
.proc_name = "NCR_D700",
.this_id = 7,
};
/* We needs this helper because we have two hosts per struct device */
struct NCR_D700_private {
struct device *dev;
struct Scsi_Host *hosts[2];
char name[30];
char pad;
};
static int
NCR_D700_probe_one(struct NCR_D700_private *p, int siop, int irq,
int slot, u32 region, int differential)
{
struct NCR_700_Host_Parameters *hostdata;
struct Scsi_Host *host;
int ret;
hostdata = kzalloc(sizeof(*hostdata), GFP_KERNEL);
if (!hostdata) {
printk(KERN_ERR "NCR D700: SIOP%d: Failed to allocate host"
"data, detatching\n", siop);
return -ENOMEM;
}
if (!request_region(region, 64, "NCR_D700")) {
printk(KERN_ERR "NCR D700: Failed to reserve IO region 0x%x\n",
region);
ret = -ENODEV;
goto region_failed;
}
/* Fill in the three required pieces of hostdata */
hostdata->base = ioport_map(region, 64);
hostdata->differential = (((1<<siop) & differential) != 0);
hostdata->clock = NCR_D700_CLOCK_MHZ;
hostdata->burst_length = 8;
/* and register the siop */
host = NCR_700_detect(&NCR_D700_driver_template, hostdata, p->dev);
if (!host) {
ret = -ENOMEM;
goto detect_failed;
}
p->hosts[siop] = host;
/* FIXME: read this from SUS */
host->this_id = id_array[slot * 2 + siop];
host->irq = irq;
host->base = region;
scsi_scan_host(host);
return 0;
detect_failed:
release_region(region, 64);
region_failed:
kfree(hostdata);
return ret;
}
static irqreturn_t
NCR_D700_intr(int irq, void *data)
{
struct NCR_D700_private *p = (struct NCR_D700_private *)data;
int i, found = 0;
for (i = 0; i < 2; i++)
if (p->hosts[i] &&
NCR_700_intr(irq, p->hosts[i]) == IRQ_HANDLED)
found++;
return found ? IRQ_HANDLED : IRQ_NONE;
}
/* Detect a D700 card. Note, because of the setup --- the chips are
* essentially connectecd to the MCA bus independently, it is easier
* to set them up as two separate host adapters, rather than one
* adapter with two channels */
static int
NCR_D700_probe(struct device *dev)
{
struct NCR_D700_private *p;
int differential;
static int banner = 1;
struct mca_device *mca_dev = to_mca_device(dev);
int slot = mca_dev->slot;
int found = 0;
int irq, i;
int pos3j, pos3k, pos3a, pos3b, pos4;
__u32 base_addr, offset_addr;
/* enable board interrupt */
pos4 = mca_device_read_pos(mca_dev, 4);
pos4 |= 0x4;
mca_device_write_pos(mca_dev, 4, pos4);
mca_device_write_pos(mca_dev, 6, 9);
pos3j = mca_device_read_pos(mca_dev, 3);
mca_device_write_pos(mca_dev, 6, 10);
pos3k = mca_device_read_pos(mca_dev, 3);
mca_device_write_pos(mca_dev, 6, 0);
pos3a = mca_device_read_pos(mca_dev, 3);
mca_device_write_pos(mca_dev, 6, 1);
pos3b = mca_device_read_pos(mca_dev, 3);
base_addr = ((pos3j << 8) | pos3k) & 0xfffffff0;
offset_addr = ((pos3a << 8) | pos3b) & 0xffffff70;
irq = (pos4 & 0x3) + 11;
if(irq >= 13)
irq++;
if(banner) {
printk(KERN_NOTICE "NCR D700: Driver Version " NCR_D700_VERSION "\n"
"NCR D700: Copyright (c) 2001 by James.Bottomley@HansenPartnership.com\n"
"NCR D700:\n");
banner = 0;
}
/* now do the bus related transforms */
irq = mca_device_transform_irq(mca_dev, irq);
base_addr = mca_device_transform_ioport(mca_dev, base_addr);
offset_addr = mca_device_transform_ioport(mca_dev, offset_addr);
printk(KERN_NOTICE "NCR D700: found in slot %d irq = %d I/O base = 0x%x\n", slot, irq, offset_addr);
/*outb(BOARD_RESET, base_addr);*/
/* clear any pending interrupts */
(void)inb(base_addr + 0x08);
/* get modctl, used later for setting diff bits */
switch(differential = (inb(base_addr + 0x08) >> 6)) {
case 0x00:
/* only SIOP1 differential */
differential = 0x02;
break;
case 0x01:
/* Both SIOPs differential */
differential = 0x03;
break;
case 0x03:
/* No SIOPs differential */
differential = 0x00;
break;
default:
printk(KERN_ERR "D700: UNEXPECTED DIFFERENTIAL RESULT 0x%02x\n",
differential);
differential = 0x00;
break;
}
p = kzalloc(sizeof(*p), GFP_KERNEL);
if (!p)
return -ENOMEM;
p->dev = dev;
snprintf(p->name, sizeof(p->name), "D700(%s)", dev_name(dev));
if (request_irq(irq, NCR_D700_intr, IRQF_SHARED, p->name, p)) {
printk(KERN_ERR "D700: request_irq failed\n");
kfree(p);
return -EBUSY;
}
/* plumb in both 700 chips */
for (i = 0; i < 2; i++) {
int err;
if ((err = NCR_D700_probe_one(p, i, irq, slot,
offset_addr + (0x80 * i),
differential)) != 0)
printk("D700: SIOP%d: probe failed, error = %d\n",
i, err);
else
found++;
}
if (!found) {
kfree(p);
return -ENODEV;
}
mca_device_set_claim(mca_dev, 1);
mca_device_set_name(mca_dev, "NCR_D700");
dev_set_drvdata(dev, p);
return 0;
}
static void
NCR_D700_remove_one(struct Scsi_Host *host)
{
scsi_remove_host(host);
NCR_700_release(host);
kfree((struct NCR_700_Host_Parameters *)host->hostdata[0]);
free_irq(host->irq, host);
release_region(host->base, 64);
}
static int
NCR_D700_remove(struct device *dev)
{
struct NCR_D700_private *p = dev_get_drvdata(dev);
int i;
for (i = 0; i < 2; i++)
NCR_D700_remove_one(p->hosts[i]);
kfree(p);
return 0;
}
static short NCR_D700_id_table[] = { NCR_D700_MCA_ID, 0 };
static struct mca_driver NCR_D700_driver = {
.id_table = NCR_D700_id_table,
.driver = {
.name = "NCR_D700",
.bus = &mca_bus_type,
.probe = NCR_D700_probe,
.remove = NCR_D700_remove,
},
};
static int __init NCR_D700_init(void)
{
#ifdef MODULE
if (NCR_D700)
param_setup(NCR_D700);
#endif
return mca_register_driver(&NCR_D700_driver);
}
static void __exit NCR_D700_exit(void)
{
mca_unregister_driver(&NCR_D700_driver);
}
module_init(NCR_D700_init);
module_exit(NCR_D700_exit);
__setup("NCR_D700=", param_setup);

29
drivers/scsi/NCR_D700.h Normal file
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/* -*- mode: c; c-basic-offset: 8 -*- */
/* NCR Dual 700 MCA SCSI Driver
*
* Copyright (C) 2001 by James.Bottomley@HansenPartnership.com
*/
#ifndef _NCR_D700_H
#define _NCR_D700_H
/* Don't turn on debugging messages */
#undef NCR_D700_DEBUG
/* The MCA identifier */
#define NCR_D700_MCA_ID 0x0092
/* Defines for the Board registers */
#define BOARD_RESET 0x80 /* board level reset */
#define ADD_PARENB 0x04 /* Address Parity Enabled */
#define DAT_PARENB 0x01 /* Data Parity Enabled */
#define SFBK_ENB 0x10 /* SFDBK Interrupt Enabled */
#define LED0GREEN 0x20 /* Led 0 (red 0; green 1) */
#define LED1GREEN 0x40 /* Led 1 (red 0; green 1) */
#define LED0RED 0xDF /* Led 0 (red 0; green 1) */
#define LED1RED 0xBF /* Led 1 (red 0; green 1) */
#define NCR_D700_CLOCK_MHZ 50
#endif

377
drivers/scsi/NCR_Q720.c Normal file
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/* -*- mode: c; c-basic-offset: 8 -*- */
/* NCR Quad 720 MCA SCSI Driver
*
* Copyright (C) 2003 by James.Bottomley@HansenPartnership.com
*/
#include <linux/blkdev.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mca.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <asm/io.h>
#include "scsi.h"
#include <scsi/scsi_host.h>
#include "ncr53c8xx.h"
#include "NCR_Q720.h"
static struct ncr_chip q720_chip __initdata = {
.revision_id = 0x0f,
.burst_max = 3,
.offset_max = 8,
.nr_divisor = 4,
.features = FE_WIDE | FE_DIFF | FE_VARCLK,
};
MODULE_AUTHOR("James Bottomley");
MODULE_DESCRIPTION("NCR Quad 720 SCSI Driver");
MODULE_LICENSE("GPL");
#define NCR_Q720_VERSION "0.9"
/* We needs this helper because we have up to four hosts per struct device */
struct NCR_Q720_private {
struct device *dev;
void __iomem * mem_base;
__u32 phys_mem_base;
__u32 mem_size;
__u8 irq;
__u8 siops;
__u8 irq_enable;
struct Scsi_Host *hosts[4];
};
static struct scsi_host_template NCR_Q720_tpnt = {
.module = THIS_MODULE,
.proc_name = "NCR_Q720",
};
static irqreturn_t
NCR_Q720_intr(int irq, void *data)
{
struct NCR_Q720_private *p = (struct NCR_Q720_private *)data;
__u8 sir = (readb(p->mem_base + 0x0d) & 0xf0) >> 4;
__u8 siop;
sir |= ~p->irq_enable;
if(sir == 0xff)
return IRQ_NONE;
while((siop = ffz(sir)) < p->siops) {
sir |= 1<<siop;
ncr53c8xx_intr(irq, p->hosts[siop]);
}
return IRQ_HANDLED;
}
static int __init
NCR_Q720_probe_one(struct NCR_Q720_private *p, int siop,
int irq, int slot, __u32 paddr, void __iomem *vaddr)
{
struct ncr_device device;
__u8 scsi_id;
static int unit = 0;
__u8 scsr1 = readb(vaddr + NCR_Q720_SCSR_OFFSET + 1);
__u8 differential = readb(vaddr + NCR_Q720_SCSR_OFFSET) & 0x20;
__u8 version;
int error;
scsi_id = scsr1 >> 4;
/* enable burst length 16 (FIXME: should allow this) */
scsr1 |= 0x02;
/* force a siop reset */
scsr1 |= 0x04;
writeb(scsr1, vaddr + NCR_Q720_SCSR_OFFSET + 1);
udelay(10);
version = readb(vaddr + 0x18) >> 4;
memset(&device, 0, sizeof(struct ncr_device));
/* Initialise ncr_device structure with items required by ncr_attach. */
device.chip = q720_chip;
device.chip.revision_id = version;
device.host_id = scsi_id;
device.dev = p->dev;
device.slot.base = paddr;
device.slot.base_c = paddr;
device.slot.base_v = vaddr;
device.slot.irq = irq;
device.differential = differential ? 2 : 0;
printk("Q720 probe unit %d (siop%d) at 0x%lx, diff = %d, vers = %d\n", unit, siop,
(unsigned long)paddr, differential, version);
p->hosts[siop] = ncr_attach(&NCR_Q720_tpnt, unit++, &device);
if (!p->hosts[siop])
goto fail;
p->irq_enable |= (1<<siop);
scsr1 = readb(vaddr + NCR_Q720_SCSR_OFFSET + 1);
/* clear the disable interrupt bit */
scsr1 &= ~0x01;
writeb(scsr1, vaddr + NCR_Q720_SCSR_OFFSET + 1);
error = scsi_add_host(p->hosts[siop], p->dev);
if (error)
ncr53c8xx_release(p->hosts[siop]);
else
scsi_scan_host(p->hosts[siop]);
return error;
fail:
return -ENODEV;
}
/* Detect a Q720 card. Note, because of the setup --- the chips are
* essentially connectecd to the MCA bus independently, it is easier
* to set them up as two separate host adapters, rather than one
* adapter with two channels */
static int __init
NCR_Q720_probe(struct device *dev)
{
struct NCR_Q720_private *p;
static int banner = 1;
struct mca_device *mca_dev = to_mca_device(dev);
int slot = mca_dev->slot;
int found = 0;
int irq, i, siops;
__u8 pos2, pos4, asr2, asr9, asr10;
__u16 io_base;
__u32 base_addr, mem_size;
void __iomem *mem_base;
p = kzalloc(sizeof(*p), GFP_KERNEL);
if (!p)
return -ENOMEM;
pos2 = mca_device_read_pos(mca_dev, 2);
/* enable device */
pos2 |= NCR_Q720_POS2_BOARD_ENABLE | NCR_Q720_POS2_INTERRUPT_ENABLE;
mca_device_write_pos(mca_dev, 2, pos2);
io_base = (pos2 & NCR_Q720_POS2_IO_MASK) << NCR_Q720_POS2_IO_SHIFT;
if(banner) {
printk(KERN_NOTICE "NCR Q720: Driver Version " NCR_Q720_VERSION "\n"
"NCR Q720: Copyright (c) 2003 by James.Bottomley@HansenPartnership.com\n"
"NCR Q720:\n");
banner = 0;
}
io_base = mca_device_transform_ioport(mca_dev, io_base);
/* OK, this is phase one of the bootstrap, we now know the
* I/O space base address. All the configuration registers
* are mapped here (including pos) */
/* sanity check I/O mapping */
i = inb(io_base) | (inb(io_base+1)<<8);
if(i != NCR_Q720_MCA_ID) {
printk(KERN_ERR "NCR_Q720, adapter failed to I/O map registers correctly at 0x%x(0x%x)\n", io_base, i);
kfree(p);
return -ENODEV;
}
/* Phase II, find the ram base and memory map the board register */
pos4 = inb(io_base + 4);
/* enable streaming data */
pos4 |= 0x01;
outb(pos4, io_base + 4);
base_addr = (pos4 & 0x7e) << 20;
base_addr += (pos4 & 0x80) << 23;
asr10 = inb(io_base + 0x12);
base_addr += (asr10 & 0x80) << 24;
base_addr += (asr10 & 0x70) << 23;
/* OK, got the base addr, now we need to find the ram size,
* enable and map it */
asr9 = inb(io_base + 0x11);
i = (asr9 & 0xc0) >> 6;
if(i == 0)
mem_size = 1024;
else
mem_size = 1 << (19 + i);
/* enable the sram mapping */
asr9 |= 0x20;
/* disable the rom mapping */
asr9 &= ~0x10;
outb(asr9, io_base + 0x11);
if(!request_mem_region(base_addr, mem_size, "NCR_Q720")) {
printk(KERN_ERR "NCR_Q720: Failed to claim memory region 0x%lx\n-0x%lx",
(unsigned long)base_addr,
(unsigned long)(base_addr + mem_size));
goto out_free;
}
if (dma_declare_coherent_memory(dev, base_addr, base_addr,
mem_size, DMA_MEMORY_MAP)
!= DMA_MEMORY_MAP) {
printk(KERN_ERR "NCR_Q720: DMA declare memory failed\n");
goto out_release_region;
}
/* The first 1k of the memory buffer is a memory map of the registers
*/
mem_base = dma_mark_declared_memory_occupied(dev, base_addr,
1024);
if (IS_ERR(mem_base)) {
printk("NCR_Q720 failed to reserve memory mapped region\n");
goto out_release;
}
/* now also enable accesses in asr 2 */
asr2 = inb(io_base + 0x0a);
asr2 |= 0x01;
outb(asr2, io_base + 0x0a);
/* get the number of SIOPs (this should be 2 or 4) */
siops = ((asr2 & 0xe0) >> 5) + 1;
/* sanity check mapping (again) */
i = readw(mem_base);
if(i != NCR_Q720_MCA_ID) {
printk(KERN_ERR "NCR_Q720, adapter failed to memory map registers correctly at 0x%lx(0x%x)\n", (unsigned long)base_addr, i);
goto out_release;
}
irq = readb(mem_base + 5) & 0x0f;
/* now do the bus related transforms */
irq = mca_device_transform_irq(mca_dev, irq);
printk(KERN_NOTICE "NCR Q720: found in slot %d irq = %d mem base = 0x%lx siops = %d\n", slot, irq, (unsigned long)base_addr, siops);
printk(KERN_NOTICE "NCR Q720: On board ram %dk\n", mem_size/1024);
p->dev = dev;
p->mem_base = mem_base;
p->phys_mem_base = base_addr;
p->mem_size = mem_size;
p->irq = irq;
p->siops = siops;
if (request_irq(irq, NCR_Q720_intr, IRQF_SHARED, "NCR_Q720", p)) {
printk(KERN_ERR "NCR_Q720: request irq %d failed\n", irq);
goto out_release;
}
/* disable all the siop interrupts */
for(i = 0; i < siops; i++) {
void __iomem *reg_scsr1 = mem_base + NCR_Q720_CHIP_REGISTER_OFFSET
+ i*NCR_Q720_SIOP_SHIFT + NCR_Q720_SCSR_OFFSET + 1;
__u8 scsr1 = readb(reg_scsr1);
scsr1 |= 0x01;
writeb(scsr1, reg_scsr1);
}
/* plumb in all 720 chips */
for (i = 0; i < siops; i++) {
void __iomem *siop_v_base = mem_base + NCR_Q720_CHIP_REGISTER_OFFSET
+ i*NCR_Q720_SIOP_SHIFT;
__u32 siop_p_base = base_addr + NCR_Q720_CHIP_REGISTER_OFFSET
+ i*NCR_Q720_SIOP_SHIFT;
__u16 port = io_base + NCR_Q720_CHIP_REGISTER_OFFSET
+ i*NCR_Q720_SIOP_SHIFT;
int err;
outb(0xff, port + 0x40);
outb(0x07, port + 0x41);
if ((err = NCR_Q720_probe_one(p, i, irq, slot,
siop_p_base, siop_v_base)) != 0)
printk("Q720: SIOP%d: probe failed, error = %d\n",
i, err);
else
found++;
}
if (!found) {
kfree(p);
return -ENODEV;
}
mca_device_set_claim(mca_dev, 1);
mca_device_set_name(mca_dev, "NCR_Q720");
dev_set_drvdata(dev, p);
return 0;
out_release:
dma_release_declared_memory(dev);
out_release_region:
release_mem_region(base_addr, mem_size);
out_free:
kfree(p);
return -ENODEV;
}
static void __exit
NCR_Q720_remove_one(struct Scsi_Host *host)
{
scsi_remove_host(host);
ncr53c8xx_release(host);
}
static int __exit
NCR_Q720_remove(struct device *dev)
{
struct NCR_Q720_private *p = dev_get_drvdata(dev);
int i;
for (i = 0; i < p->siops; i++)
if(p->hosts[i])
NCR_Q720_remove_one(p->hosts[i]);
dma_release_declared_memory(dev);
release_mem_region(p->phys_mem_base, p->mem_size);
free_irq(p->irq, p);
kfree(p);
return 0;
}
static short NCR_Q720_id_table[] = { NCR_Q720_MCA_ID, 0 };
static struct mca_driver NCR_Q720_driver = {
.id_table = NCR_Q720_id_table,
.driver = {
.name = "NCR_Q720",
.bus = &mca_bus_type,
.probe = NCR_Q720_probe,
.remove = NCR_Q720_remove,
},
};
static int __init
NCR_Q720_init(void)
{
int ret = ncr53c8xx_init();
if (!ret)
ret = mca_register_driver(&NCR_Q720_driver);
if (ret)
ncr53c8xx_exit();
return ret;
}
static void __exit
NCR_Q720_exit(void)
{
mca_unregister_driver(&NCR_Q720_driver);
ncr53c8xx_exit();
}
module_init(NCR_Q720_init);
module_exit(NCR_Q720_exit);

28
drivers/scsi/NCR_Q720.h Normal file
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/* -*- mode: c; c-basic-offset: 8 -*- */
/* NCR Quad 720 MCA SCSI Driver
*
* Copyright (C) 2003 by James.Bottomley@HansenPartnership.com
*/
#ifndef _NCR_Q720_H
#define _NCR_Q720_H
/* The MCA identifier */
#define NCR_Q720_MCA_ID 0x0720
#define NCR_Q720_CLOCK_MHZ 30
#define NCR_Q720_POS2_BOARD_ENABLE 0x01
#define NCR_Q720_POS2_INTERRUPT_ENABLE 0x02
#define NCR_Q720_POS2_PARITY_DISABLE 0x04
#define NCR_Q720_POS2_IO_MASK 0xf8
#define NCR_Q720_POS2_IO_SHIFT 8
#define NCR_Q720_CHIP_REGISTER_OFFSET 0x200
#define NCR_Q720_SCSR_OFFSET 0x070
#define NCR_Q720_SIOP_SHIFT 0x080
#endif

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/*
* Initio A100 device driver for Linux.
*
* Copyright (c) 1994-1998 Initio Corporation
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* Revision History:
* 06/18/98 HL, Initial production Version 1.02
* 12/19/98 bv, Use spinlocks for 2.1.95 and up
* 06/25/02 Doug Ledford <dledford@redhat.com>
* - This and the i60uscsi.h file are almost identical,
* merged them into a single header used by both .c files.
* 14/06/07 Alan Cox <alan@redhat.com>
* - Grand cleanup and Linuxisation
*/
#define inia100_REVID "Initio INI-A100U2W SCSI device driver; Revision: 1.02d"
#if 1
#define ORC_MAXQUEUE 245
#define ORC_MAXTAGS 64
#else
#define ORC_MAXQUEUE 25
#define ORC_MAXTAGS 8
#endif
#define TOTAL_SG_ENTRY 32
#define MAX_TARGETS 16
#define IMAX_CDB 15
#define SENSE_SIZE 14
/************************************************************************/
/* Scatter-Gather Element Structure */
/************************************************************************/
struct orc_sgent {
u32 base; /* Data Pointer */
u32 length; /* Data Length */
};
/* SCSI related definition */
#define DISC_NOT_ALLOW 0x80 /* Disconnect is not allowed */
#define DISC_ALLOW 0xC0 /* Disconnect is allowed */
#define ORC_OFFSET_SCB 16
#define ORC_MAX_SCBS 250
#define MAX_CHANNELS 2
#define MAX_ESCB_ELE 64
#define TCF_DRV_255_63 0x0400
/********************************************************/
/* Orchid Host Command Set */
/********************************************************/
#define ORC_CMD_NOP 0x00 /* Host command - NOP */
#define ORC_CMD_VERSION 0x01 /* Host command - Get F/W version */
#define ORC_CMD_ECHO 0x02 /* Host command - ECHO */
#define ORC_CMD_SET_NVM 0x03 /* Host command - Set NVRAM */
#define ORC_CMD_GET_NVM 0x04 /* Host command - Get NVRAM */
#define ORC_CMD_GET_BUS_STATUS 0x05 /* Host command - Get SCSI bus status */
#define ORC_CMD_ABORT_SCB 0x06 /* Host command - Abort SCB */
#define ORC_CMD_ISSUE_SCB 0x07 /* Host command - Issue SCB */
/********************************************************/
/* Orchid Register Set */
/********************************************************/
#define ORC_GINTS 0xA0 /* Global Interrupt Status */
#define QINT 0x04 /* Reply Queue Interrupt */
#define ORC_GIMSK 0xA1 /* Global Interrupt MASK */
#define MQINT 0x04 /* Mask Reply Queue Interrupt */
#define ORC_GCFG 0xA2 /* Global Configure */
#define EEPRG 0x01 /* Enable EEPROM programming */
#define ORC_GSTAT 0xA3 /* Global status */
#define WIDEBUS 0x10 /* Wide SCSI Devices connected */
#define ORC_HDATA 0xA4 /* Host Data */
#define ORC_HCTRL 0xA5 /* Host Control */
#define SCSIRST 0x80 /* SCSI bus reset */
#define HDO 0x40 /* Host data out */
#define HOSTSTOP 0x02 /* Host stop RISC engine */
#define DEVRST 0x01 /* Device reset */
#define ORC_HSTUS 0xA6 /* Host Status */
#define HDI 0x02 /* Host data in */
#define RREADY 0x01 /* RISC engine is ready to receive */
#define ORC_NVRAM 0xA7 /* Nvram port address */
#define SE2CS 0x008
#define SE2CLK 0x004
#define SE2DO 0x002
#define SE2DI 0x001
#define ORC_PQUEUE 0xA8 /* Posting queue FIFO */
#define ORC_PQCNT 0xA9 /* Posting queue FIFO Cnt */
#define ORC_RQUEUE 0xAA /* Reply queue FIFO */
#define ORC_RQUEUECNT 0xAB /* Reply queue FIFO Cnt */
#define ORC_FWBASEADR 0xAC /* Firmware base address */
#define ORC_EBIOSADR0 0xB0 /* External Bios address */
#define ORC_EBIOSADR1 0xB1 /* External Bios address */
#define ORC_EBIOSADR2 0xB2 /* External Bios address */
#define ORC_EBIOSDATA 0xB3 /* External Bios address */
#define ORC_SCBSIZE 0xB7 /* SCB size register */
#define ORC_SCBBASE0 0xB8 /* SCB base address 0 */
#define ORC_SCBBASE1 0xBC /* SCB base address 1 */
#define ORC_RISCCTL 0xE0 /* RISC Control */
#define PRGMRST 0x002
#define DOWNLOAD 0x001
#define ORC_PRGMCTR0 0xE2 /* RISC program counter */
#define ORC_PRGMCTR1 0xE3 /* RISC program counter */
#define ORC_RISCRAM 0xEC /* RISC RAM data port 4 bytes */
struct orc_extended_scb { /* Extended SCB */
struct orc_sgent sglist[TOTAL_SG_ENTRY]; /*0 Start of SG list */
struct scsi_cmnd *srb; /*50 SRB Pointer */
};
/***********************************************************************
SCSI Control Block
0x40 bytes long, the last 8 are user bytes
************************************************************************/
struct orc_scb { /* Scsi_Ctrl_Blk */
u8 opcode; /*00 SCB command code&residual */
u8 flags; /*01 SCB Flags */
u8 target; /*02 Target Id */
u8 lun; /*03 Lun */
u32 reserved0; /*04 Reserved for ORCHID must 0 */
u32 xferlen; /*08 Data Transfer Length */
u32 reserved1; /*0C Reserved for ORCHID must 0 */
u32 sg_len; /*10 SG list # * 8 */
u32 sg_addr; /*14 SG List Buf physical Addr */
u32 sg_addrhigh; /*18 SG Buffer high physical Addr */
u8 hastat; /*1C Host Status */
u8 tastat; /*1D Target Status */
u8 status; /*1E SCB status */
u8 link; /*1F Link pointer, default 0xFF */
u8 sense_len; /*20 Sense Allocation Length */
u8 cdb_len; /*21 CDB Length */
u8 ident; /*22 Identify */
u8 tag_msg; /*23 Tag Message */
u8 cdb[IMAX_CDB]; /*24 SCSI CDBs */
u8 scbidx; /*3C Index for this ORCSCB */
u32 sense_addr; /*34 Sense Buffer physical Addr */
struct orc_extended_scb *escb; /*38 Extended SCB Pointer */
/* 64bit pointer or 32bit pointer + reserved ? */
#ifndef CONFIG_64BIT
u8 reserved2[4]; /*3E Reserved for Driver use */
#endif
};
/* Opcodes of ORCSCB_Opcode */
#define ORC_EXECSCSI 0x00 /* SCSI initiator command with residual */
#define ORC_BUSDEVRST 0x01 /* SCSI Bus Device Reset */
/* Status of ORCSCB_Status */
#define ORCSCB_COMPLETE 0x00 /* SCB request completed */
#define ORCSCB_POST 0x01 /* SCB is posted by the HOST */
/* Bit Definition for ORCSCB_Flags */
#define SCF_DISINT 0x01 /* Disable HOST interrupt */
#define SCF_DIR 0x18 /* Direction bits */
#define SCF_NO_DCHK 0x00 /* Direction determined by SCSI */
#define SCF_DIN 0x08 /* From Target to Initiator */
#define SCF_DOUT 0x10 /* From Initiator to Target */
#define SCF_NO_XF 0x18 /* No data transfer */
#define SCF_POLL 0x40
/* Error Codes for ORCSCB_HaStat */
#define HOST_SEL_TOUT 0x11
#define HOST_DO_DU 0x12
#define HOST_BUS_FREE 0x13
#define HOST_BAD_PHAS 0x14
#define HOST_INV_CMD 0x16
#define HOST_SCSI_RST 0x1B
#define HOST_DEV_RST 0x1C
/* Error Codes for ORCSCB_TaStat */
#define TARGET_CHK_COND 0x02
#define TARGET_BUSY 0x08
#define TARGET_TAG_FULL 0x28
/***********************************************************************
Target Device Control Structure
**********************************************************************/
struct orc_target {
u8 TCS_DrvDASD; /* 6 */
u8 TCS_DrvSCSI; /* 7 */
u8 TCS_DrvHead; /* 8 */
u16 TCS_DrvFlags; /* 4 */
u8 TCS_DrvSector; /* 7 */
};
/* Bit Definition for TCF_DrvFlags */
#define TCS_DF_NODASD_SUPT 0x20 /* Suppress OS/2 DASD Mgr support */
#define TCS_DF_NOSCSI_SUPT 0x40 /* Suppress OS/2 SCSI Mgr support */
/***********************************************************************
Host Adapter Control Structure
************************************************************************/
struct orc_host {
unsigned long base; /* Base address */
u8 index; /* Index (Channel)*/
u8 scsi_id; /* H/A SCSI ID */
u8 BIOScfg; /*BIOS configuration */
u8 flags;
u8 max_targets; /* SCSI0MAXTags */
struct orc_scb *scb_virt; /* Virtual Pointer to SCB array */
dma_addr_t scb_phys; /* Scb Physical address */
struct orc_extended_scb *escb_virt; /* Virtual pointer to ESCB Scatter list */
dma_addr_t escb_phys; /* scatter list Physical address */
u8 target_flag[16]; /* target configuration, TCF_EN_TAG */
u8 max_tags[16]; /* ORC_MAX_SCBS */
u32 allocation_map[MAX_CHANNELS][8]; /* Max STB is 256, So 256/32 */
spinlock_t allocation_lock;
struct pci_dev *pdev;
};
/* Bit Definition for HCS_Flags */
#define HCF_SCSI_RESET 0x01 /* SCSI BUS RESET */
#define HCF_PARITY 0x02 /* parity card */
#define HCF_LVDS 0x10 /* parity card */
/* Bit Definition for TargetFlag */
#define TCF_EN_255 0x08
#define TCF_EN_TAG 0x10
#define TCF_BUSY 0x20
#define TCF_DISCONNECT 0x40
#define TCF_SPIN_UP 0x80
/* Bit Definition for HCS_AFlags */
#define HCS_AF_IGNORE 0x01 /* Adapter ignore */
#define HCS_AF_DISABLE_RESET 0x10 /* Adapter disable reset */
#define HCS_AF_DISABLE_ADPT 0x80 /* Adapter disable */
struct orc_nvram {
/*----------header ---------------*/
u8 SubVendorID0; /* 00 - Sub Vendor ID */
u8 SubVendorID1; /* 00 - Sub Vendor ID */
u8 SubSysID0; /* 02 - Sub System ID */
u8 SubSysID1; /* 02 - Sub System ID */
u8 SubClass; /* 04 - Sub Class */
u8 VendorID0; /* 05 - Vendor ID */
u8 VendorID1; /* 05 - Vendor ID */
u8 DeviceID0; /* 07 - Device ID */
u8 DeviceID1; /* 07 - Device ID */
u8 Reserved0[2]; /* 09 - Reserved */
u8 revision; /* 0B - revision of data structure */
/* ----Host Adapter Structure ---- */
u8 NumOfCh; /* 0C - Number of SCSI channel */
u8 BIOSConfig1; /* 0D - BIOS configuration 1 */
u8 BIOSConfig2; /* 0E - BIOS boot channel&target ID */
u8 BIOSConfig3; /* 0F - BIOS configuration 3 */
/* ----SCSI channel Structure ---- */
/* from "CTRL-I SCSI Host Adapter SetUp menu " */
u8 scsi_id; /* 10 - Channel 0 SCSI ID */
u8 SCSI0Config; /* 11 - Channel 0 SCSI configuration */
u8 SCSI0MaxTags; /* 12 - Channel 0 Maximum tags */
u8 SCSI0ResetTime; /* 13 - Channel 0 Reset recovering time */
u8 ReservedforChannel0[2]; /* 14 - Reserved */
/* ----SCSI target Structure ---- */
/* from "CTRL-I SCSI device SetUp menu " */
u8 Target00Config; /* 16 - Channel 0 Target 0 config */
u8 Target01Config; /* 17 - Channel 0 Target 1 config */
u8 Target02Config; /* 18 - Channel 0 Target 2 config */
u8 Target03Config; /* 19 - Channel 0 Target 3 config */
u8 Target04Config; /* 1A - Channel 0 Target 4 config */
u8 Target05Config; /* 1B - Channel 0 Target 5 config */
u8 Target06Config; /* 1C - Channel 0 Target 6 config */
u8 Target07Config; /* 1D - Channel 0 Target 7 config */
u8 Target08Config; /* 1E - Channel 0 Target 8 config */
u8 Target09Config; /* 1F - Channel 0 Target 9 config */
u8 Target0AConfig; /* 20 - Channel 0 Target A config */
u8 Target0BConfig; /* 21 - Channel 0 Target B config */
u8 Target0CConfig; /* 22 - Channel 0 Target C config */
u8 Target0DConfig; /* 23 - Channel 0 Target D config */
u8 Target0EConfig; /* 24 - Channel 0 Target E config */
u8 Target0FConfig; /* 25 - Channel 0 Target F config */
u8 SCSI1Id; /* 26 - Channel 1 SCSI ID */
u8 SCSI1Config; /* 27 - Channel 1 SCSI configuration */
u8 SCSI1MaxTags; /* 28 - Channel 1 Maximum tags */
u8 SCSI1ResetTime; /* 29 - Channel 1 Reset recovering time */
u8 ReservedforChannel1[2]; /* 2A - Reserved */
/* ----SCSI target Structure ---- */
/* from "CTRL-I SCSI device SetUp menu " */
u8 Target10Config; /* 2C - Channel 1 Target 0 config */
u8 Target11Config; /* 2D - Channel 1 Target 1 config */
u8 Target12Config; /* 2E - Channel 1 Target 2 config */
u8 Target13Config; /* 2F - Channel 1 Target 3 config */
u8 Target14Config; /* 30 - Channel 1 Target 4 config */
u8 Target15Config; /* 31 - Channel 1 Target 5 config */
u8 Target16Config; /* 32 - Channel 1 Target 6 config */
u8 Target17Config; /* 33 - Channel 1 Target 7 config */
u8 Target18Config; /* 34 - Channel 1 Target 8 config */
u8 Target19Config; /* 35 - Channel 1 Target 9 config */
u8 Target1AConfig; /* 36 - Channel 1 Target A config */
u8 Target1BConfig; /* 37 - Channel 1 Target B config */
u8 Target1CConfig; /* 38 - Channel 1 Target C config */
u8 Target1DConfig; /* 39 - Channel 1 Target D config */
u8 Target1EConfig; /* 3A - Channel 1 Target E config */
u8 Target1FConfig; /* 3B - Channel 1 Target F config */
u8 reserved[3]; /* 3C - Reserved */
/* ---------- CheckSum ---------- */
u8 CheckSum; /* 3F - Checksum of NVRam */
};
/* Bios Configuration for nvram->BIOSConfig1 */
#define NBC_BIOSENABLE 0x01 /* BIOS enable */
#define NBC_CDROM 0x02 /* Support bootable CDROM */
#define NBC_REMOVABLE 0x04 /* Support removable drive */
/* Bios Configuration for nvram->BIOSConfig2 */
#define NBB_TARGET_MASK 0x0F /* Boot SCSI target ID number */
#define NBB_CHANL_MASK 0xF0 /* Boot SCSI channel number */
/* Bit definition for nvram->SCSIConfig */
#define NCC_BUSRESET 0x01 /* Reset SCSI bus at power up */
#define NCC_PARITYCHK 0x02 /* SCSI parity enable */
#define NCC_LVDS 0x10 /* Enable LVDS */
#define NCC_ACTTERM1 0x20 /* Enable active terminator 1 */
#define NCC_ACTTERM2 0x40 /* Enable active terminator 2 */
#define NCC_AUTOTERM 0x80 /* Enable auto termination */
/* Bit definition for nvram->TargetxConfig */
#define NTC_PERIOD 0x07 /* Maximum Sync. Speed */
#define NTC_1GIGA 0x08 /* 255 head / 63 sectors (64/32) */
#define NTC_NO_SYNC 0x10 /* NO SYNC. NEGO */
#define NTC_NO_WIDESYNC 0x20 /* NO WIDE SYNC. NEGO */
#define NTC_DISC_ENABLE 0x40 /* Enable SCSI disconnect */
#define NTC_SPINUP 0x80 /* Start disk drive */
/* Default NVRam values */
#define NBC_DEFAULT (NBC_ENABLE)
#define NCC_DEFAULT (NCC_BUSRESET | NCC_AUTOTERM | NCC_PARITYCHK)
#define NCC_MAX_TAGS 0x20 /* Maximum tags per target */
#define NCC_RESET_TIME 0x0A /* SCSI RESET recovering time */
#define NTC_DEFAULT (NTC_1GIGA | NTC_NO_WIDESYNC | NTC_DISC_ENABLE)

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#include <linux/types.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/zorro.h>
#include <linux/module.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/amigaints.h>
#include <asm/amigahw.h>
#include "scsi.h"
#include "wd33c93.h"
#include "a2091.h"
struct a2091_hostdata {
struct WD33C93_hostdata wh;
struct a2091_scsiregs *regs;
};
static irqreturn_t a2091_intr(int irq, void *data)
{
struct Scsi_Host *instance = data;
struct a2091_hostdata *hdata = shost_priv(instance);
unsigned int status = hdata->regs->ISTR;
unsigned long flags;
if (!(status & (ISTR_INT_F | ISTR_INT_P)) || !(status & ISTR_INTS))
return IRQ_NONE;
spin_lock_irqsave(instance->host_lock, flags);
wd33c93_intr(instance);
spin_unlock_irqrestore(instance->host_lock, flags);
return IRQ_HANDLED;
}
static int dma_setup(struct scsi_cmnd *cmd, int dir_in)
{
struct Scsi_Host *instance = cmd->device->host;
struct a2091_hostdata *hdata = shost_priv(instance);
struct WD33C93_hostdata *wh = &hdata->wh;
struct a2091_scsiregs *regs = hdata->regs;
unsigned short cntr = CNTR_PDMD | CNTR_INTEN;
unsigned long addr = virt_to_bus(cmd->SCp.ptr);
/* don't allow DMA if the physical address is bad */
if (addr & A2091_XFER_MASK) {
wh->dma_bounce_len = (cmd->SCp.this_residual + 511) & ~0x1ff;
wh->dma_bounce_buffer = kmalloc(wh->dma_bounce_len,
GFP_KERNEL);
/* can't allocate memory; use PIO */
if (!wh->dma_bounce_buffer) {
wh->dma_bounce_len = 0;
return 1;
}
/* get the physical address of the bounce buffer */
addr = virt_to_bus(wh->dma_bounce_buffer);
/* the bounce buffer may not be in the first 16M of physmem */
if (addr & A2091_XFER_MASK) {
/* we could use chipmem... maybe later */
kfree(wh->dma_bounce_buffer);
wh->dma_bounce_buffer = NULL;
wh->dma_bounce_len = 0;
return 1;
}
if (!dir_in) {
/* copy to bounce buffer for a write */
memcpy(wh->dma_bounce_buffer, cmd->SCp.ptr,
cmd->SCp.this_residual);
}
}
/* setup dma direction */
if (!dir_in)
cntr |= CNTR_DDIR;
/* remember direction */
wh->dma_dir = dir_in;
regs->CNTR = cntr;
/* setup DMA *physical* address */
regs->ACR = addr;
if (dir_in) {
/* invalidate any cache */
cache_clear(addr, cmd->SCp.this_residual);
} else {
/* push any dirty cache */
cache_push(addr, cmd->SCp.this_residual);
}
/* start DMA */
regs->ST_DMA = 1;
/* return success */
return 0;
}
static void dma_stop(struct Scsi_Host *instance, struct scsi_cmnd *SCpnt,
int status)
{
struct a2091_hostdata *hdata = shost_priv(instance);
struct WD33C93_hostdata *wh = &hdata->wh;
struct a2091_scsiregs *regs = hdata->regs;
/* disable SCSI interrupts */
unsigned short cntr = CNTR_PDMD;
if (!wh->dma_dir)
cntr |= CNTR_DDIR;
/* disable SCSI interrupts */
regs->CNTR = cntr;
/* flush if we were reading */
if (wh->dma_dir) {
regs->FLUSH = 1;
while (!(regs->ISTR & ISTR_FE_FLG))
;
}
/* clear a possible interrupt */
regs->CINT = 1;
/* stop DMA */
regs->SP_DMA = 1;
/* restore the CONTROL bits (minus the direction flag) */
regs->CNTR = CNTR_PDMD | CNTR_INTEN;
/* copy from a bounce buffer, if necessary */
if (status && wh->dma_bounce_buffer) {
if (wh->dma_dir)
memcpy(SCpnt->SCp.ptr, wh->dma_bounce_buffer,
SCpnt->SCp.this_residual);
kfree(wh->dma_bounce_buffer);
wh->dma_bounce_buffer = NULL;
wh->dma_bounce_len = 0;
}
}
static int a2091_bus_reset(struct scsi_cmnd *cmd)
{
struct Scsi_Host *instance = cmd->device->host;
/* FIXME perform bus-specific reset */
/* FIXME 2: kill this function, and let midlayer fall back
to the same action, calling wd33c93_host_reset() */
spin_lock_irq(instance->host_lock);
wd33c93_host_reset(cmd);
spin_unlock_irq(instance->host_lock);
return SUCCESS;
}
static struct scsi_host_template a2091_scsi_template = {
.module = THIS_MODULE,
.name = "Commodore A2091/A590 SCSI",
.show_info = wd33c93_show_info,
.write_info = wd33c93_write_info,
.proc_name = "A2901",
.queuecommand = wd33c93_queuecommand,
.eh_abort_handler = wd33c93_abort,
.eh_bus_reset_handler = a2091_bus_reset,
.eh_host_reset_handler = wd33c93_host_reset,
.can_queue = CAN_QUEUE,
.this_id = 7,
.sg_tablesize = SG_ALL,
.cmd_per_lun = CMD_PER_LUN,
.use_clustering = DISABLE_CLUSTERING
};
static int a2091_probe(struct zorro_dev *z, const struct zorro_device_id *ent)
{
struct Scsi_Host *instance;
int error;
struct a2091_scsiregs *regs;
wd33c93_regs wdregs;
struct a2091_hostdata *hdata;
if (!request_mem_region(z->resource.start, 256, "wd33c93"))
return -EBUSY;
instance = scsi_host_alloc(&a2091_scsi_template,
sizeof(struct a2091_hostdata));
if (!instance) {
error = -ENOMEM;
goto fail_alloc;
}
instance->irq = IRQ_AMIGA_PORTS;
instance->unique_id = z->slotaddr;
regs = ZTWO_VADDR(z->resource.start);
regs->DAWR = DAWR_A2091;
wdregs.SASR = &regs->SASR;
wdregs.SCMD = &regs->SCMD;
hdata = shost_priv(instance);
hdata->wh.no_sync = 0xff;
hdata->wh.fast = 0;
hdata->wh.dma_mode = CTRL_DMA;
hdata->regs = regs;
wd33c93_init(instance, wdregs, dma_setup, dma_stop, WD33C93_FS_8_10);
error = request_irq(IRQ_AMIGA_PORTS, a2091_intr, IRQF_SHARED,
"A2091 SCSI", instance);
if (error)
goto fail_irq;
regs->CNTR = CNTR_PDMD | CNTR_INTEN;
error = scsi_add_host(instance, NULL);
if (error)
goto fail_host;
zorro_set_drvdata(z, instance);
scsi_scan_host(instance);
return 0;
fail_host:
free_irq(IRQ_AMIGA_PORTS, instance);
fail_irq:
scsi_host_put(instance);
fail_alloc:
release_mem_region(z->resource.start, 256);
return error;
}
static void a2091_remove(struct zorro_dev *z)
{
struct Scsi_Host *instance = zorro_get_drvdata(z);
struct a2091_hostdata *hdata = shost_priv(instance);
hdata->regs->CNTR = 0;
scsi_remove_host(instance);
free_irq(IRQ_AMIGA_PORTS, instance);
scsi_host_put(instance);
release_mem_region(z->resource.start, 256);
}
static struct zorro_device_id a2091_zorro_tbl[] = {
{ ZORRO_PROD_CBM_A590_A2091_1 },
{ ZORRO_PROD_CBM_A590_A2091_2 },
{ 0 }
};
MODULE_DEVICE_TABLE(zorro, a2091_zorro_tbl);
static struct zorro_driver a2091_driver = {
.name = "a2091",
.id_table = a2091_zorro_tbl,
.probe = a2091_probe,
.remove = a2091_remove,
};
static int __init a2091_init(void)
{
return zorro_register_driver(&a2091_driver);
}
module_init(a2091_init);
static void __exit a2091_exit(void)
{
zorro_unregister_driver(&a2091_driver);
}
module_exit(a2091_exit);
MODULE_DESCRIPTION("Commodore A2091/A590 SCSI");
MODULE_LICENSE("GPL");

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#ifndef A2091_H
#define A2091_H
/* $Id: a2091.h,v 1.4 1997/01/19 23:07:09 davem Exp $
*
* Header file for the Commodore A2091 Zorro II SCSI controller for Linux
*
* Written and (C) 1993, Hamish Macdonald, see a2091.c for more info
*
*/
#include <linux/types.h>
#ifndef CMD_PER_LUN
#define CMD_PER_LUN 2
#endif
#ifndef CAN_QUEUE
#define CAN_QUEUE 16
#endif
/*
* if the transfer address ANDed with this results in a non-zero
* result, then we can't use DMA.
*/
#define A2091_XFER_MASK (0xff000001)
struct a2091_scsiregs {
unsigned char pad1[64];
volatile unsigned short ISTR;
volatile unsigned short CNTR;
unsigned char pad2[60];
volatile unsigned int WTC;
volatile unsigned long ACR;
unsigned char pad3[6];
volatile unsigned short DAWR;
unsigned char pad4;
volatile unsigned char SASR;
unsigned char pad5;
volatile unsigned char SCMD;
unsigned char pad6[76];
volatile unsigned short ST_DMA;
volatile unsigned short SP_DMA;
volatile unsigned short CINT;
unsigned char pad7[2];
volatile unsigned short FLUSH;
};
#define DAWR_A2091 (3)
/* CNTR bits. */
#define CNTR_TCEN (1<<7)
#define CNTR_PREST (1<<6)
#define CNTR_PDMD (1<<5)
#define CNTR_INTEN (1<<4)
#define CNTR_DDIR (1<<3)
/* ISTR bits. */
#define ISTR_INTX (1<<8)
#define ISTR_INT_F (1<<7)
#define ISTR_INTS (1<<6)
#define ISTR_E_INT (1<<5)
#define ISTR_INT_P (1<<4)
#define ISTR_UE_INT (1<<3)
#define ISTR_OE_INT (1<<2)
#define ISTR_FF_FLG (1<<1)
#define ISTR_FE_FLG (1<<0)
#endif /* A2091_H */

287
drivers/scsi/a3000.c Normal file
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#include <linux/types.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/amigaints.h>
#include <asm/amigahw.h>
#include "scsi.h"
#include "wd33c93.h"
#include "a3000.h"
struct a3000_hostdata {
struct WD33C93_hostdata wh;
struct a3000_scsiregs *regs;
};
static irqreturn_t a3000_intr(int irq, void *data)
{
struct Scsi_Host *instance = data;
struct a3000_hostdata *hdata = shost_priv(instance);
unsigned int status = hdata->regs->ISTR;
unsigned long flags;
if (!(status & ISTR_INT_P))
return IRQ_NONE;
if (status & ISTR_INTS) {
spin_lock_irqsave(instance->host_lock, flags);
wd33c93_intr(instance);
spin_unlock_irqrestore(instance->host_lock, flags);
return IRQ_HANDLED;
}
pr_warning("Non-serviced A3000 SCSI-interrupt? ISTR = %02x\n", status);
return IRQ_NONE;
}
static int dma_setup(struct scsi_cmnd *cmd, int dir_in)
{
struct Scsi_Host *instance = cmd->device->host;
struct a3000_hostdata *hdata = shost_priv(instance);
struct WD33C93_hostdata *wh = &hdata->wh;
struct a3000_scsiregs *regs = hdata->regs;
unsigned short cntr = CNTR_PDMD | CNTR_INTEN;
unsigned long addr = virt_to_bus(cmd->SCp.ptr);
/*
* if the physical address has the wrong alignment, or if
* physical address is bad, or if it is a write and at the
* end of a physical memory chunk, then allocate a bounce
* buffer
*/
if (addr & A3000_XFER_MASK) {
wh->dma_bounce_len = (cmd->SCp.this_residual + 511) & ~0x1ff;
wh->dma_bounce_buffer = kmalloc(wh->dma_bounce_len,
GFP_KERNEL);
/* can't allocate memory; use PIO */
if (!wh->dma_bounce_buffer) {
wh->dma_bounce_len = 0;
return 1;
}
if (!dir_in) {
/* copy to bounce buffer for a write */
memcpy(wh->dma_bounce_buffer, cmd->SCp.ptr,
cmd->SCp.this_residual);
}
addr = virt_to_bus(wh->dma_bounce_buffer);
}
/* setup dma direction */
if (!dir_in)
cntr |= CNTR_DDIR;
/* remember direction */
wh->dma_dir = dir_in;
regs->CNTR = cntr;
/* setup DMA *physical* address */
regs->ACR = addr;
if (dir_in) {
/* invalidate any cache */
cache_clear(addr, cmd->SCp.this_residual);
} else {
/* push any dirty cache */
cache_push(addr, cmd->SCp.this_residual);
}
/* start DMA */
mb(); /* make sure setup is completed */
regs->ST_DMA = 1;
mb(); /* make sure DMA has started before next IO */
/* return success */
return 0;
}
static void dma_stop(struct Scsi_Host *instance, struct scsi_cmnd *SCpnt,
int status)
{
struct a3000_hostdata *hdata = shost_priv(instance);
struct WD33C93_hostdata *wh = &hdata->wh;
struct a3000_scsiregs *regs = hdata->regs;
/* disable SCSI interrupts */
unsigned short cntr = CNTR_PDMD;
if (!wh->dma_dir)
cntr |= CNTR_DDIR;
regs->CNTR = cntr;
mb(); /* make sure CNTR is updated before next IO */
/* flush if we were reading */
if (wh->dma_dir) {
regs->FLUSH = 1;
mb(); /* don't allow prefetch */
while (!(regs->ISTR & ISTR_FE_FLG))
barrier();
mb(); /* no IO until FLUSH is done */
}
/* clear a possible interrupt */
/* I think that this CINT is only necessary if you are
* using the terminal count features. HM 7 Mar 1994
*/
regs->CINT = 1;
/* stop DMA */
regs->SP_DMA = 1;
mb(); /* make sure DMA is stopped before next IO */
/* restore the CONTROL bits (minus the direction flag) */
regs->CNTR = CNTR_PDMD | CNTR_INTEN;
mb(); /* make sure CNTR is updated before next IO */
/* copy from a bounce buffer, if necessary */
if (status && wh->dma_bounce_buffer) {
if (SCpnt) {
if (wh->dma_dir && SCpnt)
memcpy(SCpnt->SCp.ptr, wh->dma_bounce_buffer,
SCpnt->SCp.this_residual);
kfree(wh->dma_bounce_buffer);
wh->dma_bounce_buffer = NULL;
wh->dma_bounce_len = 0;
} else {
kfree(wh->dma_bounce_buffer);
wh->dma_bounce_buffer = NULL;
wh->dma_bounce_len = 0;
}
}
}
static int a3000_bus_reset(struct scsi_cmnd *cmd)
{
struct Scsi_Host *instance = cmd->device->host;
/* FIXME perform bus-specific reset */
/* FIXME 2: kill this entire function, which should
cause mid-layer to call wd33c93_host_reset anyway? */
spin_lock_irq(instance->host_lock);
wd33c93_host_reset(cmd);
spin_unlock_irq(instance->host_lock);
return SUCCESS;
}
static struct scsi_host_template amiga_a3000_scsi_template = {
.module = THIS_MODULE,
.name = "Amiga 3000 built-in SCSI",
.show_info = wd33c93_show_info,
.write_info = wd33c93_write_info,
.proc_name = "A3000",
.queuecommand = wd33c93_queuecommand,
.eh_abort_handler = wd33c93_abort,
.eh_bus_reset_handler = a3000_bus_reset,
.eh_host_reset_handler = wd33c93_host_reset,
.can_queue = CAN_QUEUE,
.this_id = 7,
.sg_tablesize = SG_ALL,
.cmd_per_lun = CMD_PER_LUN,
.use_clustering = ENABLE_CLUSTERING
};
static int __init amiga_a3000_scsi_probe(struct platform_device *pdev)
{
struct resource *res;
struct Scsi_Host *instance;
int error;
struct a3000_scsiregs *regs;
wd33c93_regs wdregs;
struct a3000_hostdata *hdata;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENODEV;
if (!request_mem_region(res->start, resource_size(res), "wd33c93"))
return -EBUSY;
instance = scsi_host_alloc(&amiga_a3000_scsi_template,
sizeof(struct a3000_hostdata));
if (!instance) {
error = -ENOMEM;
goto fail_alloc;
}
instance->irq = IRQ_AMIGA_PORTS;
regs = ZTWO_VADDR(res->start);
regs->DAWR = DAWR_A3000;
wdregs.SASR = &regs->SASR;
wdregs.SCMD = &regs->SCMD;
hdata = shost_priv(instance);
hdata->wh.no_sync = 0xff;
hdata->wh.fast = 0;
hdata->wh.dma_mode = CTRL_DMA;
hdata->regs = regs;
wd33c93_init(instance, wdregs, dma_setup, dma_stop, WD33C93_FS_12_15);
error = request_irq(IRQ_AMIGA_PORTS, a3000_intr, IRQF_SHARED,
"A3000 SCSI", instance);
if (error)
goto fail_irq;
regs->CNTR = CNTR_PDMD | CNTR_INTEN;
error = scsi_add_host(instance, NULL);
if (error)
goto fail_host;
platform_set_drvdata(pdev, instance);
scsi_scan_host(instance);
return 0;
fail_host:
free_irq(IRQ_AMIGA_PORTS, instance);
fail_irq:
scsi_host_put(instance);
fail_alloc:
release_mem_region(res->start, resource_size(res));
return error;
}
static int __exit amiga_a3000_scsi_remove(struct platform_device *pdev)
{
struct Scsi_Host *instance = platform_get_drvdata(pdev);
struct a3000_hostdata *hdata = shost_priv(instance);
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
hdata->regs->CNTR = 0;
scsi_remove_host(instance);
free_irq(IRQ_AMIGA_PORTS, instance);
scsi_host_put(instance);
release_mem_region(res->start, resource_size(res));
return 0;
}
static struct platform_driver amiga_a3000_scsi_driver = {
.remove = __exit_p(amiga_a3000_scsi_remove),
.driver = {
.name = "amiga-a3000-scsi",
.owner = THIS_MODULE,
},
};
module_platform_driver_probe(amiga_a3000_scsi_driver, amiga_a3000_scsi_probe);
MODULE_DESCRIPTION("Amiga 3000 built-in SCSI");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:amiga-a3000-scsi");

72
drivers/scsi/a3000.h Normal file
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#ifndef A3000_H
#define A3000_H
/* $Id: a3000.h,v 1.4 1997/01/19 23:07:10 davem Exp $
*
* Header file for the Amiga 3000 built-in SCSI controller for Linux
*
* Written and (C) 1993, Hamish Macdonald, see a3000.c for more info
*
*/
#include <linux/types.h>
#ifndef CMD_PER_LUN
#define CMD_PER_LUN 2
#endif
#ifndef CAN_QUEUE
#define CAN_QUEUE 16
#endif
/*
* if the transfer address ANDed with this results in a non-zero
* result, then we can't use DMA.
*/
#define A3000_XFER_MASK (0x00000003)
struct a3000_scsiregs {
unsigned char pad1[2];
volatile unsigned short DAWR;
volatile unsigned int WTC;
unsigned char pad2[2];
volatile unsigned short CNTR;
volatile unsigned long ACR;
unsigned char pad3[2];
volatile unsigned short ST_DMA;
unsigned char pad4[2];
volatile unsigned short FLUSH;
unsigned char pad5[2];
volatile unsigned short CINT;
unsigned char pad6[2];
volatile unsigned short ISTR;
unsigned char pad7[30];
volatile unsigned short SP_DMA;
unsigned char pad8;
volatile unsigned char SASR;
unsigned char pad9;
volatile unsigned char SCMD;
};
#define DAWR_A3000 (3)
/* CNTR bits. */
#define CNTR_TCEN (1<<5)
#define CNTR_PREST (1<<4)
#define CNTR_PDMD (1<<3)
#define CNTR_INTEN (1<<2)
#define CNTR_DDIR (1<<1)
#define CNTR_IO_DX (1<<0)
/* ISTR bits. */
#define ISTR_INTX (1<<8)
#define ISTR_INT_F (1<<7)
#define ISTR_INTS (1<<6)
#define ISTR_E_INT (1<<5)
#define ISTR_INT_P (1<<4)
#define ISTR_UE_INT (1<<3)
#define ISTR_OE_INT (1<<2)
#define ISTR_FF_FLG (1<<1)
#define ISTR_FE_FLG (1<<0)
#endif /* A3000_H */

125
drivers/scsi/a4000t.c Normal file
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/*
* Detection routine for the NCR53c710 based Amiga SCSI Controllers for Linux.
* Amiga Technologies A4000T SCSI controller.
*
* Written 1997 by Alan Hourihane <alanh@fairlite.demon.co.uk>
* plus modifications of the 53c7xx.c driver to support the Amiga.
*
* Rewritten to use 53c700.c by Kars de Jong <jongk@linux-m68k.org>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <asm/amigahw.h>
#include <asm/amigaints.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_transport_spi.h>
#include "53c700.h"
static struct scsi_host_template a4000t_scsi_driver_template = {
.name = "A4000T builtin SCSI",
.proc_name = "A4000t",
.this_id = 7,
.module = THIS_MODULE,
};
#define A4000T_SCSI_OFFSET 0x40
static int __init amiga_a4000t_scsi_probe(struct platform_device *pdev)
{
struct resource *res;
phys_addr_t scsi_addr;
struct NCR_700_Host_Parameters *hostdata;
struct Scsi_Host *host;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENODEV;
if (!request_mem_region(res->start, resource_size(res),
"A4000T builtin SCSI"))
return -EBUSY;
hostdata = kzalloc(sizeof(struct NCR_700_Host_Parameters),
GFP_KERNEL);
if (!hostdata) {
dev_err(&pdev->dev, "Failed to allocate host data\n");
goto out_release;
}
scsi_addr = res->start + A4000T_SCSI_OFFSET;
/* Fill in the required pieces of hostdata */
hostdata->base = ZTWO_VADDR(scsi_addr);
hostdata->clock = 50;
hostdata->chip710 = 1;
hostdata->dmode_extra = DMODE_FC2;
hostdata->dcntl_extra = EA_710;
/* and register the chip */
host = NCR_700_detect(&a4000t_scsi_driver_template, hostdata,
&pdev->dev);
if (!host) {
dev_err(&pdev->dev,
"No host detected; board configuration problem?\n");
goto out_free;
}
host->this_id = 7;
host->base = scsi_addr;
host->irq = IRQ_AMIGA_PORTS;
if (request_irq(host->irq, NCR_700_intr, IRQF_SHARED, "a4000t-scsi",
host)) {
dev_err(&pdev->dev, "request_irq failed\n");
goto out_put_host;
}
platform_set_drvdata(pdev, host);
scsi_scan_host(host);
return 0;
out_put_host:
scsi_host_put(host);
out_free:
kfree(hostdata);
out_release:
release_mem_region(res->start, resource_size(res));
return -ENODEV;
}
static int __exit amiga_a4000t_scsi_remove(struct platform_device *pdev)
{
struct Scsi_Host *host = platform_get_drvdata(pdev);
struct NCR_700_Host_Parameters *hostdata = shost_priv(host);
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
scsi_remove_host(host);
NCR_700_release(host);
kfree(hostdata);
free_irq(host->irq, host);
release_mem_region(res->start, resource_size(res));
return 0;
}
static struct platform_driver amiga_a4000t_scsi_driver = {
.remove = __exit_p(amiga_a4000t_scsi_remove),
.driver = {
.name = "amiga-a4000t-scsi",
.owner = THIS_MODULE,
},
};
module_platform_driver_probe(amiga_a4000t_scsi_driver, amiga_a4000t_scsi_probe);
MODULE_AUTHOR("Alan Hourihane <alanh@fairlite.demon.co.uk> / "
"Kars de Jong <jongk@linux-m68k.org>");
MODULE_DESCRIPTION("Amiga A4000T NCR53C710 driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:amiga-a4000t-scsi");

8
drivers/scsi/aacraid/Makefile Normal file
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# Adaptec aacraid
obj-$(CONFIG_SCSI_AACRAID) := aacraid.o
aacraid-objs := linit.o aachba.o commctrl.o comminit.o commsup.o \
dpcsup.o rx.o sa.o rkt.o nark.o src.o
ccflags-y := -Idrivers/scsi

3
drivers/scsi/aacraid/TODO Normal file
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@ -0,0 +1,3 @@
o Testing
o More testing
o I/O size increase

3215
drivers/scsi/aacraid/aachba.c Normal file
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File diff suppressed because it is too large Load diff

2073
drivers/scsi/aacraid/aacraid.h Normal file
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File diff suppressed because it is too large Load diff

889
drivers/scsi/aacraid/commctrl.c Normal file
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/*
* Adaptec AAC series RAID controller driver
* (c) Copyright 2001 Red Hat Inc.
*
* based on the old aacraid driver that is..
* Adaptec aacraid device driver for Linux.
*
* Copyright (c) 2000-2010 Adaptec, Inc.
* 2010 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Module Name:
* commctrl.c
*
* Abstract: Contains all routines for control of the AFA comm layer
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/completion.h>
#include <linux/dma-mapping.h>
#include <linux/blkdev.h>
#include <linux/delay.h> /* ssleep prototype */
#include <linux/kthread.h>
#include <linux/semaphore.h>
#include <asm/uaccess.h>
#include <scsi/scsi_host.h>
#include "aacraid.h"
/**
* ioctl_send_fib - send a FIB from userspace
* @dev: adapter is being processed
* @arg: arguments to the ioctl call
*
* This routine sends a fib to the adapter on behalf of a user level
* program.
*/
# define AAC_DEBUG_PREAMBLE KERN_INFO
# define AAC_DEBUG_POSTAMBLE
static int ioctl_send_fib(struct aac_dev * dev, void __user *arg)
{
struct hw_fib * kfib;
struct fib *fibptr;
struct hw_fib * hw_fib = (struct hw_fib *)0;
dma_addr_t hw_fib_pa = (dma_addr_t)0LL;
unsigned size;
int retval;
if (dev->in_reset) {
return -EBUSY;
}
fibptr = aac_fib_alloc(dev);
if(fibptr == NULL) {
return -ENOMEM;
}
kfib = fibptr->hw_fib_va;
/*
* First copy in the header so that we can check the size field.
*/
if (copy_from_user((void *)kfib, arg, sizeof(struct aac_fibhdr))) {
aac_fib_free(fibptr);
return -EFAULT;
}
/*
* Since we copy based on the fib header size, make sure that we
* will not overrun the buffer when we copy the memory. Return
* an error if we would.
*/
size = le16_to_cpu(kfib->header.Size) + sizeof(struct aac_fibhdr);
if (size < le16_to_cpu(kfib->header.SenderSize))
size = le16_to_cpu(kfib->header.SenderSize);
if (size > dev->max_fib_size) {
dma_addr_t daddr;
if (size > 2048) {
retval = -EINVAL;
goto cleanup;
}
kfib = pci_alloc_consistent(dev->pdev, size, &daddr);
if (!kfib) {
retval = -ENOMEM;
goto cleanup;
}
/* Highjack the hw_fib */
hw_fib = fibptr->hw_fib_va;
hw_fib_pa = fibptr->hw_fib_pa;
fibptr->hw_fib_va = kfib;
fibptr->hw_fib_pa = daddr;
memset(((char *)kfib) + dev->max_fib_size, 0, size - dev->max_fib_size);
memcpy(kfib, hw_fib, dev->max_fib_size);
}
if (copy_from_user(kfib, arg, size)) {
retval = -EFAULT;
goto cleanup;
}
if (kfib->header.Command == cpu_to_le16(TakeABreakPt)) {
aac_adapter_interrupt(dev);
/*
* Since we didn't really send a fib, zero out the state to allow
* cleanup code not to assert.
*/
kfib->header.XferState = 0;
} else {
retval = aac_fib_send(le16_to_cpu(kfib->header.Command), fibptr,
le16_to_cpu(kfib->header.Size) , FsaNormal,
1, 1, NULL, NULL);
if (retval) {
goto cleanup;
}
if (aac_fib_complete(fibptr) != 0) {
retval = -EINVAL;
goto cleanup;
}
}
/*
* Make sure that the size returned by the adapter (which includes
* the header) is less than or equal to the size of a fib, so we
* don't corrupt application data. Then copy that size to the user
* buffer. (Don't try to add the header information again, since it
* was already included by the adapter.)
*/
retval = 0;
if (copy_to_user(arg, (void *)kfib, size))
retval = -EFAULT;
cleanup:
if (hw_fib) {
pci_free_consistent(dev->pdev, size, kfib, fibptr->hw_fib_pa);
fibptr->hw_fib_pa = hw_fib_pa;
fibptr->hw_fib_va = hw_fib;
}
if (retval != -ERESTARTSYS)
aac_fib_free(fibptr);
return retval;
}
/**
* open_getadapter_fib - Get the next fib
*
* This routine will get the next Fib, if available, from the AdapterFibContext
* passed in from the user.
*/
static int open_getadapter_fib(struct aac_dev * dev, void __user *arg)
{
struct aac_fib_context * fibctx;
int status;
fibctx = kmalloc(sizeof(struct aac_fib_context), GFP_KERNEL);
if (fibctx == NULL) {
status = -ENOMEM;
} else {
unsigned long flags;
struct list_head * entry;
struct aac_fib_context * context;
fibctx->type = FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT;
fibctx->size = sizeof(struct aac_fib_context);
/*
* Yes yes, I know this could be an index, but we have a
* better guarantee of uniqueness for the locked loop below.
* Without the aid of a persistent history, this also helps
* reduce the chance that the opaque context would be reused.
*/
fibctx->unique = (u32)((ulong)fibctx & 0xFFFFFFFF);
/*
* Initialize the mutex used to wait for the next AIF.
*/
sema_init(&fibctx->wait_sem, 0);
fibctx->wait = 0;
/*
* Initialize the fibs and set the count of fibs on
* the list to 0.
*/
fibctx->count = 0;
INIT_LIST_HEAD(&fibctx->fib_list);
fibctx->jiffies = jiffies/HZ;
/*
* Now add this context onto the adapter's
* AdapterFibContext list.
*/
spin_lock_irqsave(&dev->fib_lock, flags);
/* Ensure that we have a unique identifier */
entry = dev->fib_list.next;
while (entry != &dev->fib_list) {
context = list_entry(entry, struct aac_fib_context, next);
if (context->unique == fibctx->unique) {
/* Not unique (32 bits) */
fibctx->unique++;
entry = dev->fib_list.next;
} else {
entry = entry->next;
}
}
list_add_tail(&fibctx->next, &dev->fib_list);
spin_unlock_irqrestore(&dev->fib_lock, flags);
if (copy_to_user(arg, &fibctx->unique,
sizeof(fibctx->unique))) {
status = -EFAULT;
} else {
status = 0;
}
}
return status;
}
/**
* next_getadapter_fib - get the next fib
* @dev: adapter to use
* @arg: ioctl argument
*
* This routine will get the next Fib, if available, from the AdapterFibContext
* passed in from the user.
*/
static int next_getadapter_fib(struct aac_dev * dev, void __user *arg)
{
struct fib_ioctl f;
struct fib *fib;
struct aac_fib_context *fibctx;
int status;
struct list_head * entry;
unsigned long flags;
if(copy_from_user((void *)&f, arg, sizeof(struct fib_ioctl)))
return -EFAULT;
/*
* Verify that the HANDLE passed in was a valid AdapterFibContext
*
* Search the list of AdapterFibContext addresses on the adapter
* to be sure this is a valid address
*/
spin_lock_irqsave(&dev->fib_lock, flags);
entry = dev->fib_list.next;
fibctx = NULL;
while (entry != &dev->fib_list) {
fibctx = list_entry(entry, struct aac_fib_context, next);
/*
* Extract the AdapterFibContext from the Input parameters.
*/
if (fibctx->unique == f.fibctx) { /* We found a winner */
break;
}
entry = entry->next;
fibctx = NULL;
}
if (!fibctx) {
spin_unlock_irqrestore(&dev->fib_lock, flags);
dprintk ((KERN_INFO "Fib Context not found\n"));
return -EINVAL;
}
if((fibctx->type != FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT) ||
(fibctx->size != sizeof(struct aac_fib_context))) {
spin_unlock_irqrestore(&dev->fib_lock, flags);
dprintk ((KERN_INFO "Fib Context corrupt?\n"));
return -EINVAL;
}
status = 0;
/*
* If there are no fibs to send back, then either wait or return
* -EAGAIN
*/
return_fib:
if (!list_empty(&fibctx->fib_list)) {
/*
* Pull the next fib from the fibs
*/
entry = fibctx->fib_list.next;
list_del(entry);
fib = list_entry(entry, struct fib, fiblink);
fibctx->count--;
spin_unlock_irqrestore(&dev->fib_lock, flags);
if (copy_to_user(f.fib, fib->hw_fib_va, sizeof(struct hw_fib))) {
kfree(fib->hw_fib_va);
kfree(fib);
return -EFAULT;
}
/*
* Free the space occupied by this copy of the fib.
*/
kfree(fib->hw_fib_va);
kfree(fib);
status = 0;
} else {
spin_unlock_irqrestore(&dev->fib_lock, flags);
/* If someone killed the AIF aacraid thread, restart it */
status = !dev->aif_thread;
if (status && !dev->in_reset && dev->queues && dev->fsa_dev) {
/* Be paranoid, be very paranoid! */
kthread_stop(dev->thread);
ssleep(1);
dev->aif_thread = 0;
dev->thread = kthread_run(aac_command_thread, dev,
"%s", dev->name);
ssleep(1);
}
if (f.wait) {
if(down_interruptible(&fibctx->wait_sem) < 0) {
status = -ERESTARTSYS;
} else {
/* Lock again and retry */
spin_lock_irqsave(&dev->fib_lock, flags);
goto return_fib;
}
} else {
status = -EAGAIN;
}
}
fibctx->jiffies = jiffies/HZ;
return status;
}
int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context * fibctx)
{
struct fib *fib;
/*
* First free any FIBs that have not been consumed.
*/
while (!list_empty(&fibctx->fib_list)) {
struct list_head * entry;
/*
* Pull the next fib from the fibs
*/
entry = fibctx->fib_list.next;
list_del(entry);
fib = list_entry(entry, struct fib, fiblink);
fibctx->count--;
/*
* Free the space occupied by this copy of the fib.
*/
kfree(fib->hw_fib_va);
kfree(fib);
}
/*
* Remove the Context from the AdapterFibContext List
*/
list_del(&fibctx->next);
/*
* Invalidate context
*/
fibctx->type = 0;
/*
* Free the space occupied by the Context
*/
kfree(fibctx);
return 0;
}
/**
* close_getadapter_fib - close down user fib context
* @dev: adapter
* @arg: ioctl arguments
*
* This routine will close down the fibctx passed in from the user.
*/
static int close_getadapter_fib(struct aac_dev * dev, void __user *arg)
{
struct aac_fib_context *fibctx;
int status;
unsigned long flags;
struct list_head * entry;
/*
* Verify that the HANDLE passed in was a valid AdapterFibContext
*
* Search the list of AdapterFibContext addresses on the adapter
* to be sure this is a valid address
*/
entry = dev->fib_list.next;
fibctx = NULL;
while(entry != &dev->fib_list) {
fibctx = list_entry(entry, struct aac_fib_context, next);
/*
* Extract the fibctx from the input parameters
*/
if (fibctx->unique == (u32)(uintptr_t)arg) /* We found a winner */
break;
entry = entry->next;
fibctx = NULL;
}
if (!fibctx)
return 0; /* Already gone */
if((fibctx->type != FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT) ||
(fibctx->size != sizeof(struct aac_fib_context)))
return -EINVAL;
spin_lock_irqsave(&dev->fib_lock, flags);
status = aac_close_fib_context(dev, fibctx);
spin_unlock_irqrestore(&dev->fib_lock, flags);
return status;
}
/**
* check_revision - close down user fib context
* @dev: adapter
* @arg: ioctl arguments
*
* This routine returns the driver version.
* Under Linux, there have been no version incompatibilities, so this is
* simple!
*/
static int check_revision(struct aac_dev *dev, void __user *arg)
{
struct revision response;
char *driver_version = aac_driver_version;
u32 version;
response.compat = 1;
version = (simple_strtol(driver_version,
&driver_version, 10) << 24) | 0x00000400;
version += simple_strtol(driver_version + 1, &driver_version, 10) << 16;
version += simple_strtol(driver_version + 1, NULL, 10);
response.version = cpu_to_le32(version);
# ifdef AAC_DRIVER_BUILD
response.build = cpu_to_le32(AAC_DRIVER_BUILD);
# else
response.build = cpu_to_le32(9999);
# endif
if (copy_to_user(arg, &response, sizeof(response)))
return -EFAULT;
return 0;
}
/**
*
* aac_send_raw_scb
*
*/
static int aac_send_raw_srb(struct aac_dev* dev, void __user * arg)
{
struct fib* srbfib;
int status;
struct aac_srb *srbcmd = NULL;
struct user_aac_srb *user_srbcmd = NULL;
struct user_aac_srb __user *user_srb = arg;
struct aac_srb_reply __user *user_reply;
struct aac_srb_reply* reply;
u32 fibsize = 0;
u32 flags = 0;
s32 rcode = 0;
u32 data_dir;
void __user *sg_user[32];
void *sg_list[32];
u32 sg_indx = 0;
u32 byte_count = 0;
u32 actual_fibsize64, actual_fibsize = 0;
int i;
if (dev->in_reset) {
dprintk((KERN_DEBUG"aacraid: send raw srb -EBUSY\n"));
return -EBUSY;
}
if (!capable(CAP_SYS_ADMIN)){
dprintk((KERN_DEBUG"aacraid: No permission to send raw srb\n"));
return -EPERM;
}
/*
* Allocate and initialize a Fib then setup a SRB command
*/
if (!(srbfib = aac_fib_alloc(dev))) {
return -ENOMEM;
}
aac_fib_init(srbfib);
/* raw_srb FIB is not FastResponseCapable */
srbfib->hw_fib_va->header.XferState &= ~cpu_to_le32(FastResponseCapable);
srbcmd = (struct aac_srb*) fib_data(srbfib);
memset(sg_list, 0, sizeof(sg_list)); /* cleanup may take issue */
if(copy_from_user(&fibsize, &user_srb->count,sizeof(u32))){
dprintk((KERN_DEBUG"aacraid: Could not copy data size from user\n"));
rcode = -EFAULT;
goto cleanup;
}
if ((fibsize < (sizeof(struct user_aac_srb) - sizeof(struct user_sgentry))) ||
(fibsize > (dev->max_fib_size - sizeof(struct aac_fibhdr)))) {
rcode = -EINVAL;
goto cleanup;
}
user_srbcmd = kmalloc(fibsize, GFP_KERNEL);
if (!user_srbcmd) {
dprintk((KERN_DEBUG"aacraid: Could not make a copy of the srb\n"));
rcode = -ENOMEM;
goto cleanup;
}
if(copy_from_user(user_srbcmd, user_srb,fibsize)){
dprintk((KERN_DEBUG"aacraid: Could not copy srb from user\n"));
rcode = -EFAULT;
goto cleanup;
}
user_reply = arg+fibsize;
flags = user_srbcmd->flags; /* from user in cpu order */
// Fix up srb for endian and force some values
srbcmd->function = cpu_to_le32(SRBF_ExecuteScsi); // Force this
srbcmd->channel = cpu_to_le32(user_srbcmd->channel);
srbcmd->id = cpu_to_le32(user_srbcmd->id);
srbcmd->lun = cpu_to_le32(user_srbcmd->lun);
srbcmd->timeout = cpu_to_le32(user_srbcmd->timeout);
srbcmd->flags = cpu_to_le32(flags);
srbcmd->retry_limit = 0; // Obsolete parameter
srbcmd->cdb_size = cpu_to_le32(user_srbcmd->cdb_size);
memcpy(srbcmd->cdb, user_srbcmd->cdb, sizeof(srbcmd->cdb));
switch (flags & (SRB_DataIn | SRB_DataOut)) {
case SRB_DataOut:
data_dir = DMA_TO_DEVICE;
break;
case (SRB_DataIn | SRB_DataOut):
data_dir = DMA_BIDIRECTIONAL;
break;
case SRB_DataIn:
data_dir = DMA_FROM_DEVICE;
break;
default:
data_dir = DMA_NONE;
}
if (user_srbcmd->sg.count > ARRAY_SIZE(sg_list)) {
dprintk((KERN_DEBUG"aacraid: too many sg entries %d\n",
le32_to_cpu(srbcmd->sg.count)));
rcode = -EINVAL;
goto cleanup;
}
actual_fibsize = sizeof(struct aac_srb) - sizeof(struct sgentry) +
((user_srbcmd->sg.count & 0xff) * sizeof(struct sgentry));
actual_fibsize64 = actual_fibsize + (user_srbcmd->sg.count & 0xff) *
(sizeof(struct sgentry64) - sizeof(struct sgentry));
/* User made a mistake - should not continue */
if ((actual_fibsize != fibsize) && (actual_fibsize64 != fibsize)) {
dprintk((KERN_DEBUG"aacraid: Bad Size specified in "
"Raw SRB command calculated fibsize=%lu;%lu "
"user_srbcmd->sg.count=%d aac_srb=%lu sgentry=%lu;%lu "
"issued fibsize=%d\n",
actual_fibsize, actual_fibsize64, user_srbcmd->sg.count,
sizeof(struct aac_srb), sizeof(struct sgentry),
sizeof(struct sgentry64), fibsize));
rcode = -EINVAL;
goto cleanup;
}
if ((data_dir == DMA_NONE) && user_srbcmd->sg.count) {
dprintk((KERN_DEBUG"aacraid: SG with no direction specified in Raw SRB command\n"));
rcode = -EINVAL;
goto cleanup;
}
byte_count = 0;
if (dev->adapter_info.options & AAC_OPT_SGMAP_HOST64) {
struct user_sgmap64* upsg = (struct user_sgmap64*)&user_srbcmd->sg;
struct sgmap64* psg = (struct sgmap64*)&srbcmd->sg;
/*
* This should also catch if user used the 32 bit sgmap
*/
if (actual_fibsize64 == fibsize) {
actual_fibsize = actual_fibsize64;
for (i = 0; i < upsg->count; i++) {
u64 addr;
void* p;
if (upsg->sg[i].count >
((dev->adapter_info.options &
AAC_OPT_NEW_COMM) ?
(dev->scsi_host_ptr->max_sectors << 9) :
65536)) {
rcode = -EINVAL;
goto cleanup;
}
/* Does this really need to be GFP_DMA? */
p = kmalloc(upsg->sg[i].count,GFP_KERNEL|__GFP_DMA);
if(!p) {
dprintk((KERN_DEBUG"aacraid: Could not allocate SG buffer - size = %d buffer number %d of %d\n",
upsg->sg[i].count,i,upsg->count));
rcode = -ENOMEM;
goto cleanup;
}
addr = (u64)upsg->sg[i].addr[0];
addr += ((u64)upsg->sg[i].addr[1]) << 32;
sg_user[i] = (void __user *)(uintptr_t)addr;
sg_list[i] = p; // save so we can clean up later
sg_indx = i;
if (flags & SRB_DataOut) {
if(copy_from_user(p,sg_user[i],upsg->sg[i].count)){
dprintk((KERN_DEBUG"aacraid: Could not copy sg data from user\n"));
rcode = -EFAULT;
goto cleanup;
}
}
addr = pci_map_single(dev->pdev, p, upsg->sg[i].count, data_dir);
psg->sg[i].addr[0] = cpu_to_le32(addr & 0xffffffff);
psg->sg[i].addr[1] = cpu_to_le32(addr>>32);
byte_count += upsg->sg[i].count;
psg->sg[i].count = cpu_to_le32(upsg->sg[i].count);
}
} else {
struct user_sgmap* usg;
usg = kmalloc(actual_fibsize - sizeof(struct aac_srb)
+ sizeof(struct sgmap), GFP_KERNEL);
if (!usg) {
dprintk((KERN_DEBUG"aacraid: Allocation error in Raw SRB command\n"));
rcode = -ENOMEM;
goto cleanup;
}
memcpy (usg, upsg, actual_fibsize - sizeof(struct aac_srb)
+ sizeof(struct sgmap));
actual_fibsize = actual_fibsize64;
for (i = 0; i < usg->count; i++) {
u64 addr;
void* p;
if (usg->sg[i].count >
((dev->adapter_info.options &
AAC_OPT_NEW_COMM) ?
(dev->scsi_host_ptr->max_sectors << 9) :
65536)) {
kfree(usg);
rcode = -EINVAL;
goto cleanup;
}
/* Does this really need to be GFP_DMA? */
p = kmalloc(usg->sg[i].count,GFP_KERNEL|__GFP_DMA);
if(!p) {
dprintk((KERN_DEBUG "aacraid: Could not allocate SG buffer - size = %d buffer number %d of %d\n",
usg->sg[i].count,i,usg->count));
kfree(usg);
rcode = -ENOMEM;
goto cleanup;
}
sg_user[i] = (void __user *)(uintptr_t)usg->sg[i].addr;
sg_list[i] = p; // save so we can clean up later
sg_indx = i;
if (flags & SRB_DataOut) {
if(copy_from_user(p,sg_user[i],upsg->sg[i].count)){
kfree (usg);
dprintk((KERN_DEBUG"aacraid: Could not copy sg data from user\n"));
rcode = -EFAULT;
goto cleanup;
}
}
addr = pci_map_single(dev->pdev, p, usg->sg[i].count, data_dir);
psg->sg[i].addr[0] = cpu_to_le32(addr & 0xffffffff);
psg->sg[i].addr[1] = cpu_to_le32(addr>>32);
byte_count += usg->sg[i].count;
psg->sg[i].count = cpu_to_le32(usg->sg[i].count);
}
kfree (usg);
}
srbcmd->count = cpu_to_le32(byte_count);
psg->count = cpu_to_le32(sg_indx+1);
status = aac_fib_send(ScsiPortCommand64, srbfib, actual_fibsize, FsaNormal, 1, 1,NULL,NULL);
} else {
struct user_sgmap* upsg = &user_srbcmd->sg;
struct sgmap* psg = &srbcmd->sg;
if (actual_fibsize64 == fibsize) {
struct user_sgmap64* usg = (struct user_sgmap64 *)upsg;
for (i = 0; i < upsg->count; i++) {
uintptr_t addr;
void* p;
if (usg->sg[i].count >
((dev->adapter_info.options &
AAC_OPT_NEW_COMM) ?
(dev->scsi_host_ptr->max_sectors << 9) :
65536)) {
rcode = -EINVAL;
goto cleanup;
}
/* Does this really need to be GFP_DMA? */
p = kmalloc(usg->sg[i].count,GFP_KERNEL|__GFP_DMA);
if(!p) {
dprintk((KERN_DEBUG"aacraid: Could not allocate SG buffer - size = %d buffer number %d of %d\n",
usg->sg[i].count,i,usg->count));
rcode = -ENOMEM;
goto cleanup;
}
addr = (u64)usg->sg[i].addr[0];
addr += ((u64)usg->sg[i].addr[1]) << 32;
sg_user[i] = (void __user *)addr;
sg_list[i] = p; // save so we can clean up later
sg_indx = i;
if (flags & SRB_DataOut) {
if(copy_from_user(p,sg_user[i],usg->sg[i].count)){
dprintk((KERN_DEBUG"aacraid: Could not copy sg data from user\n"));
rcode = -EFAULT;
goto cleanup;
}
}
addr = pci_map_single(dev->pdev, p, usg->sg[i].count, data_dir);
psg->sg[i].addr = cpu_to_le32(addr & 0xffffffff);
byte_count += usg->sg[i].count;
psg->sg[i].count = cpu_to_le32(usg->sg[i].count);
}
} else {
for (i = 0; i < upsg->count; i++) {
dma_addr_t addr;
void* p;
if (upsg->sg[i].count >
((dev->adapter_info.options &
AAC_OPT_NEW_COMM) ?
(dev->scsi_host_ptr->max_sectors << 9) :
65536)) {
rcode = -EINVAL;
goto cleanup;
}
p = kmalloc(upsg->sg[i].count, GFP_KERNEL);
if (!p) {
dprintk((KERN_DEBUG"aacraid: Could not allocate SG buffer - size = %d buffer number %d of %d\n",
upsg->sg[i].count, i, upsg->count));
rcode = -ENOMEM;
goto cleanup;
}
sg_user[i] = (void __user *)(uintptr_t)upsg->sg[i].addr;
sg_list[i] = p; // save so we can clean up later
sg_indx = i;
if (flags & SRB_DataOut) {
if(copy_from_user(p, sg_user[i],
upsg->sg[i].count)) {
dprintk((KERN_DEBUG"aacraid: Could not copy sg data from user\n"));
rcode = -EFAULT;
goto cleanup;
}
}
addr = pci_map_single(dev->pdev, p,
upsg->sg[i].count, data_dir);
psg->sg[i].addr = cpu_to_le32(addr);
byte_count += upsg->sg[i].count;
psg->sg[i].count = cpu_to_le32(upsg->sg[i].count);
}
}
srbcmd->count = cpu_to_le32(byte_count);
psg->count = cpu_to_le32(sg_indx+1);
status = aac_fib_send(ScsiPortCommand, srbfib, actual_fibsize, FsaNormal, 1, 1, NULL, NULL);
}
if (status == -ERESTARTSYS) {
rcode = -ERESTARTSYS;
goto cleanup;
}
if (status != 0){
dprintk((KERN_DEBUG"aacraid: Could not send raw srb fib to hba\n"));
rcode = -ENXIO;
goto cleanup;
}
if (flags & SRB_DataIn) {
for(i = 0 ; i <= sg_indx; i++){
byte_count = le32_to_cpu(
(dev->adapter_info.options & AAC_OPT_SGMAP_HOST64)
? ((struct sgmap64*)&srbcmd->sg)->sg[i].count
: srbcmd->sg.sg[i].count);
if(copy_to_user(sg_user[i], sg_list[i], byte_count)){
dprintk((KERN_DEBUG"aacraid: Could not copy sg data to user\n"));
rcode = -EFAULT;
goto cleanup;
}
}
}
reply = (struct aac_srb_reply *) fib_data(srbfib);
if(copy_to_user(user_reply,reply,sizeof(struct aac_srb_reply))){
dprintk((KERN_DEBUG"aacraid: Could not copy reply to user\n"));
rcode = -EFAULT;
goto cleanup;
}
cleanup:
kfree(user_srbcmd);
for(i=0; i <= sg_indx; i++){
kfree(sg_list[i]);
}
if (rcode != -ERESTARTSYS) {
aac_fib_complete(srbfib);
aac_fib_free(srbfib);
}
return rcode;
}
struct aac_pci_info {
u32 bus;
u32 slot;
};
static int aac_get_pci_info(struct aac_dev* dev, void __user *arg)
{
struct aac_pci_info pci_info;
pci_info.bus = dev->pdev->bus->number;
pci_info.slot = PCI_SLOT(dev->pdev->devfn);
if (copy_to_user(arg, &pci_info, sizeof(struct aac_pci_info))) {
dprintk((KERN_DEBUG "aacraid: Could not copy pci info\n"));
return -EFAULT;
}
return 0;
}
int aac_do_ioctl(struct aac_dev * dev, int cmd, void __user *arg)
{
int status;
/*
* HBA gets first crack
*/
status = aac_dev_ioctl(dev, cmd, arg);
if (status != -ENOTTY)
return status;
switch (cmd) {
case FSACTL_MINIPORT_REV_CHECK:
status = check_revision(dev, arg);
break;
case FSACTL_SEND_LARGE_FIB:
case FSACTL_SENDFIB:
status = ioctl_send_fib(dev, arg);
break;
case FSACTL_OPEN_GET_ADAPTER_FIB:
status = open_getadapter_fib(dev, arg);
break;
case FSACTL_GET_NEXT_ADAPTER_FIB:
status = next_getadapter_fib(dev, arg);
break;
case FSACTL_CLOSE_GET_ADAPTER_FIB:
status = close_getadapter_fib(dev, arg);
break;
case FSACTL_SEND_RAW_SRB:
status = aac_send_raw_srb(dev,arg);
break;
case FSACTL_GET_PCI_INFO:
status = aac_get_pci_info(dev,arg);
break;
default:
status = -ENOTTY;
break;
}
return status;
}

492
drivers/scsi/aacraid/comminit.c Normal file
View file

@ -0,0 +1,492 @@
/*
* Adaptec AAC series RAID controller driver
* (c) Copyright 2001 Red Hat Inc.
*
* based on the old aacraid driver that is..
* Adaptec aacraid device driver for Linux.
*
* Copyright (c) 2000-2010 Adaptec, Inc.
* 2010 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Module Name:
* comminit.c
*
* Abstract: This supports the initialization of the host adapter commuication interface.
* This is a platform dependent module for the pci cyclone board.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/blkdev.h>
#include <linux/completion.h>
#include <linux/mm.h>
#include <scsi/scsi_host.h>
#include "aacraid.h"
struct aac_common aac_config = {
.irq_mod = 1
};
static int aac_alloc_comm(struct aac_dev *dev, void **commaddr, unsigned long commsize, unsigned long commalign)
{
unsigned char *base;
unsigned long size, align;
const unsigned long fibsize = 4096;
const unsigned long printfbufsiz = 256;
unsigned long host_rrq_size = 0;
struct aac_init *init;
dma_addr_t phys;
unsigned long aac_max_hostphysmempages;
if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE1 ||
dev->comm_interface == AAC_COMM_MESSAGE_TYPE2)
host_rrq_size = (dev->scsi_host_ptr->can_queue
+ AAC_NUM_MGT_FIB) * sizeof(u32);
size = fibsize + sizeof(struct aac_init) + commsize +
commalign + printfbufsiz + host_rrq_size;
base = pci_alloc_consistent(dev->pdev, size, &phys);
if(base == NULL)
{
printk(KERN_ERR "aacraid: unable to create mapping.\n");
return 0;
}
dev->comm_addr = (void *)base;
dev->comm_phys = phys;
dev->comm_size = size;
if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE1 ||
dev->comm_interface == AAC_COMM_MESSAGE_TYPE2) {
dev->host_rrq = (u32 *)(base + fibsize);
dev->host_rrq_pa = phys + fibsize;
memset(dev->host_rrq, 0, host_rrq_size);
}
dev->init = (struct aac_init *)(base + fibsize + host_rrq_size);
dev->init_pa = phys + fibsize + host_rrq_size;
init = dev->init;
init->InitStructRevision = cpu_to_le32(ADAPTER_INIT_STRUCT_REVISION);
if (dev->max_fib_size != sizeof(struct hw_fib))
init->InitStructRevision = cpu_to_le32(ADAPTER_INIT_STRUCT_REVISION_4);
init->MiniPortRevision = cpu_to_le32(Sa_MINIPORT_REVISION);
init->fsrev = cpu_to_le32(dev->fsrev);
/*
* Adapter Fibs are the first thing allocated so that they
* start page aligned
*/
dev->aif_base_va = (struct hw_fib *)base;
init->AdapterFibsVirtualAddress = 0;
init->AdapterFibsPhysicalAddress = cpu_to_le32((u32)phys);
init->AdapterFibsSize = cpu_to_le32(fibsize);
init->AdapterFibAlign = cpu_to_le32(sizeof(struct hw_fib));
/*
* number of 4k pages of host physical memory. The aacraid fw needs
* this number to be less than 4gb worth of pages. New firmware doesn't
* have any issues with the mapping system, but older Firmware did, and
* had *troubles* dealing with the math overloading past 32 bits, thus
* we must limit this field.
*/
aac_max_hostphysmempages = dma_get_required_mask(&dev->pdev->dev) >> 12;
if (aac_max_hostphysmempages < AAC_MAX_HOSTPHYSMEMPAGES)
init->HostPhysMemPages = cpu_to_le32(aac_max_hostphysmempages);
else
init->HostPhysMemPages = cpu_to_le32(AAC_MAX_HOSTPHYSMEMPAGES);
init->InitFlags = cpu_to_le32(INITFLAGS_DRIVER_USES_UTC_TIME |
INITFLAGS_DRIVER_SUPPORTS_PM);
init->MaxIoCommands = cpu_to_le32(dev->scsi_host_ptr->can_queue + AAC_NUM_MGT_FIB);
init->MaxIoSize = cpu_to_le32(dev->scsi_host_ptr->max_sectors << 9);
init->MaxFibSize = cpu_to_le32(dev->max_fib_size);
init->MaxNumAif = cpu_to_le32(dev->max_num_aif);
if (dev->comm_interface == AAC_COMM_MESSAGE) {
init->InitFlags |= cpu_to_le32(INITFLAGS_NEW_COMM_SUPPORTED);
dprintk((KERN_WARNING"aacraid: New Comm Interface enabled\n"));
} else if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE1) {
init->InitStructRevision = cpu_to_le32(ADAPTER_INIT_STRUCT_REVISION_6);
init->InitFlags |= cpu_to_le32(INITFLAGS_NEW_COMM_SUPPORTED |
INITFLAGS_NEW_COMM_TYPE1_SUPPORTED | INITFLAGS_FAST_JBOD_SUPPORTED);
init->HostRRQ_AddrHigh = cpu_to_le32((u32)((u64)dev->host_rrq_pa >> 32));
init->HostRRQ_AddrLow = cpu_to_le32((u32)(dev->host_rrq_pa & 0xffffffff));
dprintk((KERN_WARNING"aacraid: New Comm Interface type1 enabled\n"));
} else if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE2) {
init->InitStructRevision = cpu_to_le32(ADAPTER_INIT_STRUCT_REVISION_7);
init->InitFlags |= cpu_to_le32(INITFLAGS_NEW_COMM_SUPPORTED |
INITFLAGS_NEW_COMM_TYPE2_SUPPORTED | INITFLAGS_FAST_JBOD_SUPPORTED);
init->HostRRQ_AddrHigh = cpu_to_le32((u32)((u64)dev->host_rrq_pa >> 32));
init->HostRRQ_AddrLow = cpu_to_le32((u32)(dev->host_rrq_pa & 0xffffffff));
init->MiniPortRevision = cpu_to_le32(0L); /* number of MSI-X */
dprintk((KERN_WARNING"aacraid: New Comm Interface type2 enabled\n"));
}
/*
* Increment the base address by the amount already used
*/
base = base + fibsize + host_rrq_size + sizeof(struct aac_init);
phys = (dma_addr_t)((ulong)phys + fibsize + host_rrq_size +
sizeof(struct aac_init));
/*
* Align the beginning of Headers to commalign
*/
align = (commalign - ((uintptr_t)(base) & (commalign - 1)));
base = base + align;
phys = phys + align;
/*
* Fill in addresses of the Comm Area Headers and Queues
*/
*commaddr = base;
init->CommHeaderAddress = cpu_to_le32((u32)phys);
/*
* Increment the base address by the size of the CommArea
*/
base = base + commsize;
phys = phys + commsize;
/*
* Place the Printf buffer area after the Fast I/O comm area.
*/
dev->printfbuf = (void *)base;
init->printfbuf = cpu_to_le32(phys);
init->printfbufsiz = cpu_to_le32(printfbufsiz);
memset(base, 0, printfbufsiz);
return 1;
}
static void aac_queue_init(struct aac_dev * dev, struct aac_queue * q, u32 *mem, int qsize)
{
q->numpending = 0;
q->dev = dev;
init_waitqueue_head(&q->cmdready);
INIT_LIST_HEAD(&q->cmdq);
init_waitqueue_head(&q->qfull);
spin_lock_init(&q->lockdata);
q->lock = &q->lockdata;
q->headers.producer = (__le32 *)mem;
q->headers.consumer = (__le32 *)(mem+1);
*(q->headers.producer) = cpu_to_le32(qsize);
*(q->headers.consumer) = cpu_to_le32(qsize);
q->entries = qsize;
}
/**
* aac_send_shutdown - shutdown an adapter
* @dev: Adapter to shutdown
*
* This routine will send a VM_CloseAll (shutdown) request to the adapter.
*/
int aac_send_shutdown(struct aac_dev * dev)
{
struct fib * fibctx;
struct aac_close *cmd;
int status;
fibctx = aac_fib_alloc(dev);
if (!fibctx)
return -ENOMEM;
aac_fib_init(fibctx);
cmd = (struct aac_close *) fib_data(fibctx);
cmd->command = cpu_to_le32(VM_CloseAll);
cmd->cid = cpu_to_le32(0xfffffffe);
status = aac_fib_send(ContainerCommand,
fibctx,
sizeof(struct aac_close),
FsaNormal,
-2 /* Timeout silently */, 1,
NULL, NULL);
if (status >= 0)
aac_fib_complete(fibctx);
/* FIB should be freed only after getting the response from the F/W */
if (status != -ERESTARTSYS)
aac_fib_free(fibctx);
return status;
}
/**
* aac_comm_init - Initialise FSA data structures
* @dev: Adapter to initialise
*
* Initializes the data structures that are required for the FSA commuication
* interface to operate.
* Returns
* 1 - if we were able to init the commuication interface.
* 0 - If there were errors initing. This is a fatal error.
*/
static int aac_comm_init(struct aac_dev * dev)
{
unsigned long hdrsize = (sizeof(u32) * NUMBER_OF_COMM_QUEUES) * 2;
unsigned long queuesize = sizeof(struct aac_entry) * TOTAL_QUEUE_ENTRIES;
u32 *headers;
struct aac_entry * queues;
unsigned long size;
struct aac_queue_block * comm = dev->queues;
/*
* Now allocate and initialize the zone structures used as our
* pool of FIB context records. The size of the zone is based
* on the system memory size. We also initialize the mutex used
* to protect the zone.
*/
spin_lock_init(&dev->fib_lock);
/*
* Allocate the physically contiguous space for the commuication
* queue headers.
*/
size = hdrsize + queuesize;
if (!aac_alloc_comm(dev, (void * *)&headers, size, QUEUE_ALIGNMENT))
return -ENOMEM;
queues = (struct aac_entry *)(((ulong)headers) + hdrsize);
/* Adapter to Host normal priority Command queue */
comm->queue[HostNormCmdQueue].base = queues;
aac_queue_init(dev, &comm->queue[HostNormCmdQueue], headers, HOST_NORM_CMD_ENTRIES);
queues += HOST_NORM_CMD_ENTRIES;
headers += 2;
/* Adapter to Host high priority command queue */
comm->queue[HostHighCmdQueue].base = queues;
aac_queue_init(dev, &comm->queue[HostHighCmdQueue], headers, HOST_HIGH_CMD_ENTRIES);
queues += HOST_HIGH_CMD_ENTRIES;
headers +=2;
/* Host to adapter normal priority command queue */
comm->queue[AdapNormCmdQueue].base = queues;
aac_queue_init(dev, &comm->queue[AdapNormCmdQueue], headers, ADAP_NORM_CMD_ENTRIES);
queues += ADAP_NORM_CMD_ENTRIES;
headers += 2;
/* host to adapter high priority command queue */
comm->queue[AdapHighCmdQueue].base = queues;
aac_queue_init(dev, &comm->queue[AdapHighCmdQueue], headers, ADAP_HIGH_CMD_ENTRIES);
queues += ADAP_HIGH_CMD_ENTRIES;
headers += 2;
/* adapter to host normal priority response queue */
comm->queue[HostNormRespQueue].base = queues;
aac_queue_init(dev, &comm->queue[HostNormRespQueue], headers, HOST_NORM_RESP_ENTRIES);
queues += HOST_NORM_RESP_ENTRIES;
headers += 2;
/* adapter to host high priority response queue */
comm->queue[HostHighRespQueue].base = queues;
aac_queue_init(dev, &comm->queue[HostHighRespQueue], headers, HOST_HIGH_RESP_ENTRIES);
queues += HOST_HIGH_RESP_ENTRIES;
headers += 2;
/* host to adapter normal priority response queue */
comm->queue[AdapNormRespQueue].base = queues;
aac_queue_init(dev, &comm->queue[AdapNormRespQueue], headers, ADAP_NORM_RESP_ENTRIES);
queues += ADAP_NORM_RESP_ENTRIES;
headers += 2;
/* host to adapter high priority response queue */
comm->queue[AdapHighRespQueue].base = queues;
aac_queue_init(dev, &comm->queue[AdapHighRespQueue], headers, ADAP_HIGH_RESP_ENTRIES);
comm->queue[AdapNormCmdQueue].lock = comm->queue[HostNormRespQueue].lock;
comm->queue[AdapHighCmdQueue].lock = comm->queue[HostHighRespQueue].lock;
comm->queue[AdapNormRespQueue].lock = comm->queue[HostNormCmdQueue].lock;
comm->queue[AdapHighRespQueue].lock = comm->queue[HostHighCmdQueue].lock;
return 0;
}
struct aac_dev *aac_init_adapter(struct aac_dev *dev)
{
u32 status[5];
struct Scsi_Host * host = dev->scsi_host_ptr;
extern int aac_sync_mode;
/*
* Check the preferred comm settings, defaults from template.
*/
dev->management_fib_count = 0;
spin_lock_init(&dev->manage_lock);
spin_lock_init(&dev->sync_lock);
dev->max_fib_size = sizeof(struct hw_fib);
dev->sg_tablesize = host->sg_tablesize = (dev->max_fib_size
- sizeof(struct aac_fibhdr)
- sizeof(struct aac_write) + sizeof(struct sgentry))
/ sizeof(struct sgentry);
dev->comm_interface = AAC_COMM_PRODUCER;
dev->raw_io_interface = dev->raw_io_64 = 0;
if ((!aac_adapter_sync_cmd(dev, GET_ADAPTER_PROPERTIES,
0, 0, 0, 0, 0, 0, status+0, status+1, status+2, NULL, NULL)) &&
(status[0] == 0x00000001)) {
if (status[1] & le32_to_cpu(AAC_OPT_NEW_COMM_64))
dev->raw_io_64 = 1;
dev->sync_mode = aac_sync_mode;
if (dev->a_ops.adapter_comm &&
(status[1] & le32_to_cpu(AAC_OPT_NEW_COMM))) {
dev->comm_interface = AAC_COMM_MESSAGE;
dev->raw_io_interface = 1;
if ((status[1] & le32_to_cpu(AAC_OPT_NEW_COMM_TYPE1))) {
/* driver supports TYPE1 (Tupelo) */
dev->comm_interface = AAC_COMM_MESSAGE_TYPE1;
} else if ((status[1] & le32_to_cpu(AAC_OPT_NEW_COMM_TYPE2))) {
/* driver supports TYPE2 (Denali) */
dev->comm_interface = AAC_COMM_MESSAGE_TYPE2;
} else if ((status[1] & le32_to_cpu(AAC_OPT_NEW_COMM_TYPE4)) ||
(status[1] & le32_to_cpu(AAC_OPT_NEW_COMM_TYPE3))) {
/* driver doesn't TYPE3 and TYPE4 */
/* switch to sync. mode */
dev->comm_interface = AAC_COMM_MESSAGE_TYPE2;
dev->sync_mode = 1;
}
}
if ((dev->comm_interface == AAC_COMM_MESSAGE) &&
(status[2] > dev->base_size)) {
aac_adapter_ioremap(dev, 0);
dev->base_size = status[2];
if (aac_adapter_ioremap(dev, status[2])) {
/* remap failed, go back ... */
dev->comm_interface = AAC_COMM_PRODUCER;
if (aac_adapter_ioremap(dev, AAC_MIN_FOOTPRINT_SIZE)) {
printk(KERN_WARNING
"aacraid: unable to map adapter.\n");
return NULL;
}
}
}
}
if ((!aac_adapter_sync_cmd(dev, GET_COMM_PREFERRED_SETTINGS,
0, 0, 0, 0, 0, 0,
status+0, status+1, status+2, status+3, status+4))
&& (status[0] == 0x00000001)) {
/*
* status[1] >> 16 maximum command size in KB
* status[1] & 0xFFFF maximum FIB size
* status[2] >> 16 maximum SG elements to driver
* status[2] & 0xFFFF maximum SG elements from driver
* status[3] & 0xFFFF maximum number FIBs outstanding
*/
host->max_sectors = (status[1] >> 16) << 1;
/* Multiple of 32 for PMC */
dev->max_fib_size = status[1] & 0xFFE0;
host->sg_tablesize = status[2] >> 16;
dev->sg_tablesize = status[2] & 0xFFFF;
if (dev->pdev->device == PMC_DEVICE_S7 ||
dev->pdev->device == PMC_DEVICE_S8 ||
dev->pdev->device == PMC_DEVICE_S9)
host->can_queue = ((status[3] >> 16) ? (status[3] >> 16) :
(status[3] & 0xFFFF)) - AAC_NUM_MGT_FIB;
else
host->can_queue = (status[3] & 0xFFFF) - AAC_NUM_MGT_FIB;
dev->max_num_aif = status[4] & 0xFFFF;
/*
* NOTE:
* All these overrides are based on a fixed internal
* knowledge and understanding of existing adapters,
* acbsize should be set with caution.
*/
if (acbsize == 512) {
host->max_sectors = AAC_MAX_32BIT_SGBCOUNT;
dev->max_fib_size = 512;
dev->sg_tablesize = host->sg_tablesize
= (512 - sizeof(struct aac_fibhdr)
- sizeof(struct aac_write) + sizeof(struct sgentry))
/ sizeof(struct sgentry);
host->can_queue = AAC_NUM_IO_FIB;
} else if (acbsize == 2048) {
host->max_sectors = 512;
dev->max_fib_size = 2048;
host->sg_tablesize = 65;
dev->sg_tablesize = 81;
host->can_queue = 512 - AAC_NUM_MGT_FIB;
} else if (acbsize == 4096) {
host->max_sectors = 1024;
dev->max_fib_size = 4096;
host->sg_tablesize = 129;
dev->sg_tablesize = 166;
host->can_queue = 256 - AAC_NUM_MGT_FIB;
} else if (acbsize == 8192) {
host->max_sectors = 2048;
dev->max_fib_size = 8192;
host->sg_tablesize = 257;
dev->sg_tablesize = 337;
host->can_queue = 128 - AAC_NUM_MGT_FIB;
} else if (acbsize > 0) {
printk("Illegal acbsize=%d ignored\n", acbsize);
}
}
{
if (numacb > 0) {
if (numacb < host->can_queue)
host->can_queue = numacb;
else
printk("numacb=%d ignored\n", numacb);
}
}
if (host->can_queue > AAC_NUM_IO_FIB)
host->can_queue = AAC_NUM_IO_FIB;
/*
* Ok now init the communication subsystem
*/
dev->queues = kzalloc(sizeof(struct aac_queue_block), GFP_KERNEL);
if (dev->queues == NULL) {
printk(KERN_ERR "Error could not allocate comm region.\n");
return NULL;
}
if (aac_comm_init(dev)<0){
kfree(dev->queues);
return NULL;
}
/*
* Initialize the list of fibs
*/
if (aac_fib_setup(dev) < 0) {
kfree(dev->queues);
return NULL;
}
INIT_LIST_HEAD(&dev->fib_list);
INIT_LIST_HEAD(&dev->sync_fib_list);
return dev;
}

1930
drivers/scsi/aacraid/commsup.c Normal file
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420
drivers/scsi/aacraid/dpcsup.c Normal file
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@ -0,0 +1,420 @@
/*
* Adaptec AAC series RAID controller driver
* (c) Copyright 2001 Red Hat Inc.
*
* based on the old aacraid driver that is..
* Adaptec aacraid device driver for Linux.
*
* Copyright (c) 2000-2010 Adaptec, Inc.
* 2010 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Module Name:
* dpcsup.c
*
* Abstract: All DPC processing routines for the cyclone board occur here.
*
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/completion.h>
#include <linux/blkdev.h>
#include <linux/semaphore.h>
#include "aacraid.h"
/**
* aac_response_normal - Handle command replies
* @q: Queue to read from
*
* This DPC routine will be run when the adapter interrupts us to let us
* know there is a response on our normal priority queue. We will pull off
* all QE there are and wake up all the waiters before exiting. We will
* take a spinlock out on the queue before operating on it.
*/
unsigned int aac_response_normal(struct aac_queue * q)
{
struct aac_dev * dev = q->dev;
struct aac_entry *entry;
struct hw_fib * hwfib;
struct fib * fib;
int consumed = 0;
unsigned long flags, mflags;
spin_lock_irqsave(q->lock, flags);
/*
* Keep pulling response QEs off the response queue and waking
* up the waiters until there are no more QEs. We then return
* back to the system. If no response was requesed we just
* deallocate the Fib here and continue.
*/
while(aac_consumer_get(dev, q, &entry))
{
int fast;
u32 index = le32_to_cpu(entry->addr);
fast = index & 0x01;
fib = &dev->fibs[index >> 2];
hwfib = fib->hw_fib_va;
aac_consumer_free(dev, q, HostNormRespQueue);
/*
* Remove this fib from the Outstanding I/O queue.
* But only if it has not already been timed out.
*
* If the fib has been timed out already, then just
* continue. The caller has already been notified that
* the fib timed out.
*/
dev->queues->queue[AdapNormCmdQueue].numpending--;
if (unlikely(fib->flags & FIB_CONTEXT_FLAG_TIMED_OUT)) {
spin_unlock_irqrestore(q->lock, flags);
aac_fib_complete(fib);
aac_fib_free(fib);
spin_lock_irqsave(q->lock, flags);
continue;
}
spin_unlock_irqrestore(q->lock, flags);
if (fast) {
/*
* Doctor the fib
*/
*(__le32 *)hwfib->data = cpu_to_le32(ST_OK);
hwfib->header.XferState |= cpu_to_le32(AdapterProcessed);
fib->flags |= FIB_CONTEXT_FLAG_FASTRESP;
}
FIB_COUNTER_INCREMENT(aac_config.FibRecved);
if (hwfib->header.Command == cpu_to_le16(NuFileSystem))
{
__le32 *pstatus = (__le32 *)hwfib->data;
if (*pstatus & cpu_to_le32(0xffff0000))
*pstatus = cpu_to_le32(ST_OK);
}
if (hwfib->header.XferState & cpu_to_le32(NoResponseExpected | Async))
{
if (hwfib->header.XferState & cpu_to_le32(NoResponseExpected))
FIB_COUNTER_INCREMENT(aac_config.NoResponseRecved);
else
FIB_COUNTER_INCREMENT(aac_config.AsyncRecved);
/*
* NOTE: we cannot touch the fib after this
* call, because it may have been deallocated.
*/
fib->flags &= FIB_CONTEXT_FLAG_FASTRESP;
fib->callback(fib->callback_data, fib);
} else {
unsigned long flagv;
spin_lock_irqsave(&fib->event_lock, flagv);
if (!fib->done) {
fib->done = 1;
up(&fib->event_wait);
}
spin_unlock_irqrestore(&fib->event_lock, flagv);
spin_lock_irqsave(&dev->manage_lock, mflags);
dev->management_fib_count--;
spin_unlock_irqrestore(&dev->manage_lock, mflags);
FIB_COUNTER_INCREMENT(aac_config.NormalRecved);
if (fib->done == 2) {
spin_lock_irqsave(&fib->event_lock, flagv);
fib->done = 0;
spin_unlock_irqrestore(&fib->event_lock, flagv);
aac_fib_complete(fib);
aac_fib_free(fib);
}
}
consumed++;
spin_lock_irqsave(q->lock, flags);
}
if (consumed > aac_config.peak_fibs)
aac_config.peak_fibs = consumed;
if (consumed == 0)
aac_config.zero_fibs++;
spin_unlock_irqrestore(q->lock, flags);
return 0;
}
/**
* aac_command_normal - handle commands
* @q: queue to process
*
* This DPC routine will be queued when the adapter interrupts us to
* let us know there is a command on our normal priority queue. We will
* pull off all QE there are and wake up all the waiters before exiting.
* We will take a spinlock out on the queue before operating on it.
*/
unsigned int aac_command_normal(struct aac_queue *q)
{
struct aac_dev * dev = q->dev;
struct aac_entry *entry;
unsigned long flags;
spin_lock_irqsave(q->lock, flags);
/*
* Keep pulling response QEs off the response queue and waking
* up the waiters until there are no more QEs. We then return
* back to the system.
*/
while(aac_consumer_get(dev, q, &entry))
{
struct fib fibctx;
struct hw_fib * hw_fib;
u32 index;
struct fib *fib = &fibctx;
index = le32_to_cpu(entry->addr) / sizeof(struct hw_fib);
hw_fib = &dev->aif_base_va[index];
/*
* Allocate a FIB at all costs. For non queued stuff
* we can just use the stack so we are happy. We need
* a fib object in order to manage the linked lists
*/
if (dev->aif_thread)
if((fib = kmalloc(sizeof(struct fib), GFP_ATOMIC)) == NULL)
fib = &fibctx;
memset(fib, 0, sizeof(struct fib));
INIT_LIST_HEAD(&fib->fiblink);
fib->type = FSAFS_NTC_FIB_CONTEXT;
fib->size = sizeof(struct fib);
fib->hw_fib_va = hw_fib;
fib->data = hw_fib->data;
fib->dev = dev;
if (dev->aif_thread && fib != &fibctx) {
list_add_tail(&fib->fiblink, &q->cmdq);
aac_consumer_free(dev, q, HostNormCmdQueue);
wake_up_interruptible(&q->cmdready);
} else {
aac_consumer_free(dev, q, HostNormCmdQueue);
spin_unlock_irqrestore(q->lock, flags);
/*
* Set the status of this FIB
*/
*(__le32 *)hw_fib->data = cpu_to_le32(ST_OK);
aac_fib_adapter_complete(fib, sizeof(u32));
spin_lock_irqsave(q->lock, flags);
}
}
spin_unlock_irqrestore(q->lock, flags);
return 0;
}
/*
*
* aac_aif_callback
* @context: the context set in the fib - here it is scsi cmd
* @fibptr: pointer to the fib
*
* Handles the AIFs - new method (SRC)
*
*/
static void aac_aif_callback(void *context, struct fib * fibptr)
{
struct fib *fibctx;
struct aac_dev *dev;
struct aac_aifcmd *cmd;
int status;
fibctx = (struct fib *)context;
BUG_ON(fibptr == NULL);
dev = fibptr->dev;
if (fibptr->hw_fib_va->header.XferState &
cpu_to_le32(NoMoreAifDataAvailable)) {
aac_fib_complete(fibptr);
aac_fib_free(fibptr);
return;
}
aac_intr_normal(dev, 0, 1, 0, fibptr->hw_fib_va);
aac_fib_init(fibctx);
cmd = (struct aac_aifcmd *) fib_data(fibctx);
cmd->command = cpu_to_le32(AifReqEvent);
status = aac_fib_send(AifRequest,
fibctx,
sizeof(struct hw_fib)-sizeof(struct aac_fibhdr),
FsaNormal,
0, 1,
(fib_callback)aac_aif_callback, fibctx);
}
/**
* aac_intr_normal - Handle command replies
* @dev: Device
* @index: completion reference
*
* This DPC routine will be run when the adapter interrupts us to let us
* know there is a response on our normal priority queue. We will pull off
* all QE there are and wake up all the waiters before exiting.
*/
unsigned int aac_intr_normal(struct aac_dev *dev, u32 index,
int isAif, int isFastResponse, struct hw_fib *aif_fib)
{
unsigned long mflags;
dprintk((KERN_INFO "aac_intr_normal(%p,%x)\n", dev, index));
if (isAif == 1) { /* AIF - common */
struct hw_fib * hw_fib;
struct fib * fib;
struct aac_queue *q = &dev->queues->queue[HostNormCmdQueue];
unsigned long flags;
/*
* Allocate a FIB. For non queued stuff we can just use
* the stack so we are happy. We need a fib object in order to
* manage the linked lists.
*/
if ((!dev->aif_thread)
|| (!(fib = kzalloc(sizeof(struct fib),GFP_ATOMIC))))
return 1;
if (!(hw_fib = kzalloc(sizeof(struct hw_fib),GFP_ATOMIC))) {
kfree (fib);
return 1;
}
if (aif_fib != NULL) {
memcpy(hw_fib, aif_fib, sizeof(struct hw_fib));
} else {
memcpy(hw_fib,
(struct hw_fib *)(((uintptr_t)(dev->regs.sa)) +
index), sizeof(struct hw_fib));
}
INIT_LIST_HEAD(&fib->fiblink);
fib->type = FSAFS_NTC_FIB_CONTEXT;
fib->size = sizeof(struct fib);
fib->hw_fib_va = hw_fib;
fib->data = hw_fib->data;
fib->dev = dev;
spin_lock_irqsave(q->lock, flags);
list_add_tail(&fib->fiblink, &q->cmdq);
wake_up_interruptible(&q->cmdready);
spin_unlock_irqrestore(q->lock, flags);
return 1;
} else if (isAif == 2) { /* AIF - new (SRC) */
struct fib *fibctx;
struct aac_aifcmd *cmd;
fibctx = aac_fib_alloc(dev);
if (!fibctx)
return 1;
aac_fib_init(fibctx);
cmd = (struct aac_aifcmd *) fib_data(fibctx);
cmd->command = cpu_to_le32(AifReqEvent);
return aac_fib_send(AifRequest,
fibctx,
sizeof(struct hw_fib)-sizeof(struct aac_fibhdr),
FsaNormal,
0, 1,
(fib_callback)aac_aif_callback, fibctx);
} else {
struct fib *fib = &dev->fibs[index];
struct hw_fib * hwfib = fib->hw_fib_va;
/*
* Remove this fib from the Outstanding I/O queue.
* But only if it has not already been timed out.
*
* If the fib has been timed out already, then just
* continue. The caller has already been notified that
* the fib timed out.
*/
dev->queues->queue[AdapNormCmdQueue].numpending--;
if (unlikely(fib->flags & FIB_CONTEXT_FLAG_TIMED_OUT)) {
aac_fib_complete(fib);
aac_fib_free(fib);
return 0;
}
if (isFastResponse) {
/*
* Doctor the fib
*/
*(__le32 *)hwfib->data = cpu_to_le32(ST_OK);
hwfib->header.XferState |= cpu_to_le32(AdapterProcessed);
fib->flags |= FIB_CONTEXT_FLAG_FASTRESP;
}
FIB_COUNTER_INCREMENT(aac_config.FibRecved);
if (hwfib->header.Command == cpu_to_le16(NuFileSystem))
{
__le32 *pstatus = (__le32 *)hwfib->data;
if (*pstatus & cpu_to_le32(0xffff0000))
*pstatus = cpu_to_le32(ST_OK);
}
if (hwfib->header.XferState & cpu_to_le32(NoResponseExpected | Async))
{
if (hwfib->header.XferState & cpu_to_le32(NoResponseExpected))
FIB_COUNTER_INCREMENT(aac_config.NoResponseRecved);
else
FIB_COUNTER_INCREMENT(aac_config.AsyncRecved);
/*
* NOTE: we cannot touch the fib after this
* call, because it may have been deallocated.
*/
fib->flags &= FIB_CONTEXT_FLAG_FASTRESP;
fib->callback(fib->callback_data, fib);
} else {
unsigned long flagv;
dprintk((KERN_INFO "event_wait up\n"));
spin_lock_irqsave(&fib->event_lock, flagv);
if (!fib->done) {
fib->done = 1;
up(&fib->event_wait);
}
spin_unlock_irqrestore(&fib->event_lock, flagv);
spin_lock_irqsave(&dev->manage_lock, mflags);
dev->management_fib_count--;
spin_unlock_irqrestore(&dev->manage_lock, mflags);
FIB_COUNTER_INCREMENT(aac_config.NormalRecved);
if (fib->done == 2) {
spin_lock_irqsave(&fib->event_lock, flagv);
fib->done = 0;
spin_unlock_irqrestore(&fib->event_lock, flagv);
aac_fib_complete(fib);
aac_fib_free(fib);
}
}
return 0;
}
}

1373
drivers/scsi/aacraid/linit.c Normal file
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84
drivers/scsi/aacraid/nark.c Normal file
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@ -0,0 +1,84 @@
/*
* Adaptec AAC series RAID controller driver
*
* based on the old aacraid driver that is..
* Adaptec aacraid device driver for Linux.
*
* Copyright (c) 2000-2010 Adaptec, Inc.
* 2010 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Module Name:
* nark.c
*
* Abstract: Hardware Device Interface for NEMER/ARK
*
*/
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <scsi/scsi_host.h>
#include "aacraid.h"
/**
* aac_nark_ioremap
* @size: mapping resize request
*
*/
static int aac_nark_ioremap(struct aac_dev * dev, u32 size)
{
if (!size) {
iounmap(dev->regs.rx);
dev->regs.rx = NULL;
iounmap(dev->base);
dev->base = NULL;
return 0;
}
dev->base_start = pci_resource_start(dev->pdev, 2);
dev->regs.rx = ioremap((u64)pci_resource_start(dev->pdev, 0) |
((u64)pci_resource_start(dev->pdev, 1) << 32),
sizeof(struct rx_registers) - sizeof(struct rx_inbound));
dev->base = NULL;
if (dev->regs.rx == NULL)
return -1;
dev->base = ioremap(dev->base_start, size);
if (dev->base == NULL) {
iounmap(dev->regs.rx);
dev->regs.rx = NULL;
return -1;
}
dev->IndexRegs = &((struct rx_registers __iomem *)dev->base)->IndexRegs;
return 0;
}
/**
* aac_nark_init - initialize an NEMER/ARK Split Bar card
* @dev: device to configure
*
*/
int aac_nark_init(struct aac_dev * dev)
{
/*
* Fill in the function dispatch table.
*/
dev->a_ops.adapter_ioremap = aac_nark_ioremap;
dev->a_ops.adapter_comm = aac_rx_select_comm;
return _aac_rx_init(dev);
}

107
drivers/scsi/aacraid/rkt.c Normal file
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/*
* Adaptec AAC series RAID controller driver
* (c) Copyright 2001 Red Hat Inc.
*
* based on the old aacraid driver that is..
* Adaptec aacraid device driver for Linux.
*
* Copyright (c) 2000-2010 Adaptec, Inc.
* 2010 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Module Name:
* rkt.c
*
* Abstract: Hardware miniport for Drawbridge specific hardware functions.
*
*/
#include <linux/blkdev.h>
#include <scsi/scsi_host.h>
#include "aacraid.h"
#define AAC_NUM_IO_FIB_RKT (246 - AAC_NUM_MGT_FIB)
/**
* aac_rkt_select_comm - Select communications method
* @dev: Adapter
* @comm: communications method
*/
static int aac_rkt_select_comm(struct aac_dev *dev, int comm)
{
int retval;
retval = aac_rx_select_comm(dev, comm);
if (comm == AAC_COMM_MESSAGE) {
/*
* FIB Setup has already been done, but we can minimize the
* damage by at least ensuring the OS never issues more
* commands than we can handle. The Rocket adapters currently
* can only handle 246 commands and 8 AIFs at the same time,
* and in fact do notify us accordingly if we negotiate the
* FIB size. The problem that causes us to add this check is
* to ensure that we do not overdo it with the adapter when a
* hard coded FIB override is being utilized. This special
* case warrants this half baked, but convenient, check here.
*/
if (dev->scsi_host_ptr->can_queue > AAC_NUM_IO_FIB_RKT) {
dev->init->MaxIoCommands =
cpu_to_le32(AAC_NUM_IO_FIB_RKT + AAC_NUM_MGT_FIB);
dev->scsi_host_ptr->can_queue = AAC_NUM_IO_FIB_RKT;
}
}
return retval;
}
/**
* aac_rkt_ioremap
* @size: mapping resize request
*
*/
static int aac_rkt_ioremap(struct aac_dev * dev, u32 size)
{
if (!size) {
iounmap(dev->regs.rkt);
return 0;
}
dev->base = dev->regs.rkt = ioremap(dev->base_start, size);
if (dev->base == NULL)
return -1;
dev->IndexRegs = &dev->regs.rkt->IndexRegs;
return 0;
}
/**
* aac_rkt_init - initialize an i960 based AAC card
* @dev: device to configure
*
* Allocate and set up resources for the i960 based AAC variants. The
* device_interface in the commregion will be allocated and linked
* to the comm region.
*/
int aac_rkt_init(struct aac_dev *dev)
{
/*
* Fill in the function dispatch table.
*/
dev->a_ops.adapter_ioremap = aac_rkt_ioremap;
dev->a_ops.adapter_comm = aac_rkt_select_comm;
return _aac_rx_init(dev);
}

684
drivers/scsi/aacraid/rx.c Normal file
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@ -0,0 +1,684 @@
/*
* Adaptec AAC series RAID controller driver
* (c) Copyright 2001 Red Hat Inc.
*
* based on the old aacraid driver that is..
* Adaptec aacraid device driver for Linux.
*
* Copyright (c) 2000-2010 Adaptec, Inc.
* 2010 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Module Name:
* rx.c
*
* Abstract: Hardware miniport for Drawbridge specific hardware functions.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/completion.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <scsi/scsi_host.h>
#include "aacraid.h"
static irqreturn_t aac_rx_intr_producer(int irq, void *dev_id)
{
struct aac_dev *dev = dev_id;
unsigned long bellbits;
u8 intstat = rx_readb(dev, MUnit.OISR);
/*
* Read mask and invert because drawbridge is reversed.
* This allows us to only service interrupts that have
* been enabled.
* Check to see if this is our interrupt. If it isn't just return
*/
if (likely(intstat & ~(dev->OIMR))) {
bellbits = rx_readl(dev, OutboundDoorbellReg);
if (unlikely(bellbits & DoorBellPrintfReady)) {
aac_printf(dev, readl (&dev->IndexRegs->Mailbox[5]));
rx_writel(dev, MUnit.ODR,DoorBellPrintfReady);
rx_writel(dev, InboundDoorbellReg,DoorBellPrintfDone);
}
else if (unlikely(bellbits & DoorBellAdapterNormCmdReady)) {
rx_writel(dev, MUnit.ODR, DoorBellAdapterNormCmdReady);
aac_command_normal(&dev->queues->queue[HostNormCmdQueue]);
}
else if (likely(bellbits & DoorBellAdapterNormRespReady)) {
rx_writel(dev, MUnit.ODR,DoorBellAdapterNormRespReady);
aac_response_normal(&dev->queues->queue[HostNormRespQueue]);
}
else if (unlikely(bellbits & DoorBellAdapterNormCmdNotFull)) {
rx_writel(dev, MUnit.ODR, DoorBellAdapterNormCmdNotFull);
}
else if (unlikely(bellbits & DoorBellAdapterNormRespNotFull)) {
rx_writel(dev, MUnit.ODR, DoorBellAdapterNormCmdNotFull);
rx_writel(dev, MUnit.ODR, DoorBellAdapterNormRespNotFull);
}
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static irqreturn_t aac_rx_intr_message(int irq, void *dev_id)
{
int isAif, isFastResponse, isSpecial;
struct aac_dev *dev = dev_id;
u32 Index = rx_readl(dev, MUnit.OutboundQueue);
if (unlikely(Index == 0xFFFFFFFFL))
Index = rx_readl(dev, MUnit.OutboundQueue);
if (likely(Index != 0xFFFFFFFFL)) {
do {
isAif = isFastResponse = isSpecial = 0;
if (Index & 0x00000002L) {
isAif = 1;
if (Index == 0xFFFFFFFEL)
isSpecial = 1;
Index &= ~0x00000002L;
} else {
if (Index & 0x00000001L)
isFastResponse = 1;
Index >>= 2;
}
if (!isSpecial) {
if (unlikely(aac_intr_normal(dev,
Index, isAif,
isFastResponse, NULL))) {
rx_writel(dev,
MUnit.OutboundQueue,
Index);
rx_writel(dev,
MUnit.ODR,
DoorBellAdapterNormRespReady);
}
}
Index = rx_readl(dev, MUnit.OutboundQueue);
} while (Index != 0xFFFFFFFFL);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
/**
* aac_rx_disable_interrupt - Disable interrupts
* @dev: Adapter
*/
static void aac_rx_disable_interrupt(struct aac_dev *dev)
{
rx_writeb(dev, MUnit.OIMR, dev->OIMR = 0xff);
}
/**
* aac_rx_enable_interrupt_producer - Enable interrupts
* @dev: Adapter
*/
static void aac_rx_enable_interrupt_producer(struct aac_dev *dev)
{
rx_writeb(dev, MUnit.OIMR, dev->OIMR = 0xfb);
}
/**
* aac_rx_enable_interrupt_message - Enable interrupts
* @dev: Adapter
*/
static void aac_rx_enable_interrupt_message(struct aac_dev *dev)
{
rx_writeb(dev, MUnit.OIMR, dev->OIMR = 0xf7);
}
/**
* rx_sync_cmd - send a command and wait
* @dev: Adapter
* @command: Command to execute
* @p1: first parameter
* @ret: adapter status
*
* This routine will send a synchronous command to the adapter and wait
* for its completion.
*/
static int rx_sync_cmd(struct aac_dev *dev, u32 command,
u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6,
u32 *status, u32 * r1, u32 * r2, u32 * r3, u32 * r4)
{
unsigned long start;
int ok;
/*
* Write the command into Mailbox 0
*/
writel(command, &dev->IndexRegs->Mailbox[0]);
/*
* Write the parameters into Mailboxes 1 - 6
*/
writel(p1, &dev->IndexRegs->Mailbox[1]);
writel(p2, &dev->IndexRegs->Mailbox[2]);
writel(p3, &dev->IndexRegs->Mailbox[3]);
writel(p4, &dev->IndexRegs->Mailbox[4]);
/*
* Clear the synch command doorbell to start on a clean slate.
*/
rx_writel(dev, OutboundDoorbellReg, OUTBOUNDDOORBELL_0);
/*
* Disable doorbell interrupts
*/
rx_writeb(dev, MUnit.OIMR, dev->OIMR = 0xff);
/*
* Force the completion of the mask register write before issuing
* the interrupt.
*/
rx_readb (dev, MUnit.OIMR);
/*
* Signal that there is a new synch command
*/
rx_writel(dev, InboundDoorbellReg, INBOUNDDOORBELL_0);
ok = 0;
start = jiffies;
/*
* Wait up to 30 seconds
*/
while (time_before(jiffies, start+30*HZ))
{
udelay(5); /* Delay 5 microseconds to let Mon960 get info. */
/*
* Mon960 will set doorbell0 bit when it has completed the command.
*/
if (rx_readl(dev, OutboundDoorbellReg) & OUTBOUNDDOORBELL_0) {
/*
* Clear the doorbell.
*/
rx_writel(dev, OutboundDoorbellReg, OUTBOUNDDOORBELL_0);
ok = 1;
break;
}
/*
* Yield the processor in case we are slow
*/
msleep(1);
}
if (unlikely(ok != 1)) {
/*
* Restore interrupt mask even though we timed out
*/
aac_adapter_enable_int(dev);
return -ETIMEDOUT;
}
/*
* Pull the synch status from Mailbox 0.
*/
if (status)
*status = readl(&dev->IndexRegs->Mailbox[0]);
if (r1)
*r1 = readl(&dev->IndexRegs->Mailbox[1]);
if (r2)
*r2 = readl(&dev->IndexRegs->Mailbox[2]);
if (r3)
*r3 = readl(&dev->IndexRegs->Mailbox[3]);
if (r4)
*r4 = readl(&dev->IndexRegs->Mailbox[4]);
/*
* Clear the synch command doorbell.
*/
rx_writel(dev, OutboundDoorbellReg, OUTBOUNDDOORBELL_0);
/*
* Restore interrupt mask
*/
aac_adapter_enable_int(dev);
return 0;
}
/**
* aac_rx_interrupt_adapter - interrupt adapter
* @dev: Adapter
*
* Send an interrupt to the i960 and breakpoint it.
*/
static void aac_rx_interrupt_adapter(struct aac_dev *dev)
{
rx_sync_cmd(dev, BREAKPOINT_REQUEST, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL);
}
/**
* aac_rx_notify_adapter - send an event to the adapter
* @dev: Adapter
* @event: Event to send
*
* Notify the i960 that something it probably cares about has
* happened.
*/
static void aac_rx_notify_adapter(struct aac_dev *dev, u32 event)
{
switch (event) {
case AdapNormCmdQue:
rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_1);
break;
case HostNormRespNotFull:
rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_4);
break;
case AdapNormRespQue:
rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_2);
break;
case HostNormCmdNotFull:
rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_3);
break;
case HostShutdown:
break;
case FastIo:
rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_6);
break;
case AdapPrintfDone:
rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_5);
break;
default:
BUG();
break;
}
}
/**
* aac_rx_start_adapter - activate adapter
* @dev: Adapter
*
* Start up processing on an i960 based AAC adapter
*/
static void aac_rx_start_adapter(struct aac_dev *dev)
{
struct aac_init *init;
init = dev->init;
init->HostElapsedSeconds = cpu_to_le32(get_seconds());
// We can only use a 32 bit address here
rx_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS, (u32)(ulong)dev->init_pa,
0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL);
}
/**
* aac_rx_check_health
* @dev: device to check if healthy
*
* Will attempt to determine if the specified adapter is alive and
* capable of handling requests, returning 0 if alive.
*/
static int aac_rx_check_health(struct aac_dev *dev)
{
u32 status = rx_readl(dev, MUnit.OMRx[0]);
/*
* Check to see if the board failed any self tests.
*/
if (unlikely(status & SELF_TEST_FAILED))
return -1;
/*
* Check to see if the board panic'd.
*/
if (unlikely(status & KERNEL_PANIC)) {
char * buffer;
struct POSTSTATUS {
__le32 Post_Command;
__le32 Post_Address;
} * post;
dma_addr_t paddr, baddr;
int ret;
if (likely((status & 0xFF000000L) == 0xBC000000L))
return (status >> 16) & 0xFF;
buffer = pci_alloc_consistent(dev->pdev, 512, &baddr);
ret = -2;
if (unlikely(buffer == NULL))
return ret;
post = pci_alloc_consistent(dev->pdev,
sizeof(struct POSTSTATUS), &paddr);
if (unlikely(post == NULL)) {
pci_free_consistent(dev->pdev, 512, buffer, baddr);
return ret;
}
memset(buffer, 0, 512);
post->Post_Command = cpu_to_le32(COMMAND_POST_RESULTS);
post->Post_Address = cpu_to_le32(baddr);
rx_writel(dev, MUnit.IMRx[0], paddr);
rx_sync_cmd(dev, COMMAND_POST_RESULTS, baddr, 0, 0, 0, 0, 0,
NULL, NULL, NULL, NULL, NULL);
pci_free_consistent(dev->pdev, sizeof(struct POSTSTATUS),
post, paddr);
if (likely((buffer[0] == '0') && ((buffer[1] == 'x') || (buffer[1] == 'X')))) {
ret = (hex_to_bin(buffer[2]) << 4) +
hex_to_bin(buffer[3]);
}
pci_free_consistent(dev->pdev, 512, buffer, baddr);
return ret;
}
/*
* Wait for the adapter to be up and running.
*/
if (unlikely(!(status & KERNEL_UP_AND_RUNNING)))
return -3;
/*
* Everything is OK
*/
return 0;
}
/**
* aac_rx_deliver_producer
* @fib: fib to issue
*
* Will send a fib, returning 0 if successful.
*/
int aac_rx_deliver_producer(struct fib * fib)
{
struct aac_dev *dev = fib->dev;
struct aac_queue *q = &dev->queues->queue[AdapNormCmdQueue];
unsigned long qflags;
u32 Index;
unsigned long nointr = 0;
spin_lock_irqsave(q->lock, qflags);
aac_queue_get( dev, &Index, AdapNormCmdQueue, fib->hw_fib_va, 1, fib, &nointr);
q->numpending++;
*(q->headers.producer) = cpu_to_le32(Index + 1);
spin_unlock_irqrestore(q->lock, qflags);
if (!(nointr & aac_config.irq_mod))
aac_adapter_notify(dev, AdapNormCmdQueue);
return 0;
}
/**
* aac_rx_deliver_message
* @fib: fib to issue
*
* Will send a fib, returning 0 if successful.
*/
static int aac_rx_deliver_message(struct fib * fib)
{
struct aac_dev *dev = fib->dev;
struct aac_queue *q = &dev->queues->queue[AdapNormCmdQueue];
unsigned long qflags;
u32 Index;
u64 addr;
volatile void __iomem *device;
unsigned long count = 10000000L; /* 50 seconds */
spin_lock_irqsave(q->lock, qflags);
q->numpending++;
spin_unlock_irqrestore(q->lock, qflags);
for(;;) {
Index = rx_readl(dev, MUnit.InboundQueue);
if (unlikely(Index == 0xFFFFFFFFL))
Index = rx_readl(dev, MUnit.InboundQueue);
if (likely(Index != 0xFFFFFFFFL))
break;
if (--count == 0) {
spin_lock_irqsave(q->lock, qflags);
q->numpending--;
spin_unlock_irqrestore(q->lock, qflags);
return -ETIMEDOUT;
}
udelay(5);
}
device = dev->base + Index;
addr = fib->hw_fib_pa;
writel((u32)(addr & 0xffffffff), device);
device += sizeof(u32);
writel((u32)(addr >> 32), device);
device += sizeof(u32);
writel(le16_to_cpu(fib->hw_fib_va->header.Size), device);
rx_writel(dev, MUnit.InboundQueue, Index);
return 0;
}
/**
* aac_rx_ioremap
* @size: mapping resize request
*
*/
static int aac_rx_ioremap(struct aac_dev * dev, u32 size)
{
if (!size) {
iounmap(dev->regs.rx);
return 0;
}
dev->base = dev->regs.rx = ioremap(dev->base_start, size);
if (dev->base == NULL)
return -1;
dev->IndexRegs = &dev->regs.rx->IndexRegs;
return 0;
}
static int aac_rx_restart_adapter(struct aac_dev *dev, int bled)
{
u32 var = 0;
if (!(dev->supplement_adapter_info.SupportedOptions2 &
AAC_OPTION_MU_RESET) || (bled >= 0) || (bled == -2)) {
if (bled)
printk(KERN_ERR "%s%d: adapter kernel panic'd %x.\n",
dev->name, dev->id, bled);
else {
bled = aac_adapter_sync_cmd(dev, IOP_RESET_ALWAYS,
0, 0, 0, 0, 0, 0, &var, NULL, NULL, NULL, NULL);
if (!bled && (var != 0x00000001) && (var != 0x3803000F))
bled = -EINVAL;
}
if (bled && (bled != -ETIMEDOUT))
bled = aac_adapter_sync_cmd(dev, IOP_RESET,
0, 0, 0, 0, 0, 0, &var, NULL, NULL, NULL, NULL);
if (bled && (bled != -ETIMEDOUT))
return -EINVAL;
}
if (bled && (var == 0x3803000F)) { /* USE_OTHER_METHOD */
rx_writel(dev, MUnit.reserved2, 3);
msleep(5000); /* Delay 5 seconds */
var = 0x00000001;
}
if (bled && (var != 0x00000001))
return -EINVAL;
ssleep(5);
if (rx_readl(dev, MUnit.OMRx[0]) & KERNEL_PANIC)
return -ENODEV;
if (startup_timeout < 300)
startup_timeout = 300;
return 0;
}
/**
* aac_rx_select_comm - Select communications method
* @dev: Adapter
* @comm: communications method
*/
int aac_rx_select_comm(struct aac_dev *dev, int comm)
{
switch (comm) {
case AAC_COMM_PRODUCER:
dev->a_ops.adapter_enable_int = aac_rx_enable_interrupt_producer;
dev->a_ops.adapter_intr = aac_rx_intr_producer;
dev->a_ops.adapter_deliver = aac_rx_deliver_producer;
break;
case AAC_COMM_MESSAGE:
dev->a_ops.adapter_enable_int = aac_rx_enable_interrupt_message;
dev->a_ops.adapter_intr = aac_rx_intr_message;
dev->a_ops.adapter_deliver = aac_rx_deliver_message;
break;
default:
return 1;
}
return 0;
}
/**
* aac_rx_init - initialize an i960 based AAC card
* @dev: device to configure
*
* Allocate and set up resources for the i960 based AAC variants. The
* device_interface in the commregion will be allocated and linked
* to the comm region.
*/
int _aac_rx_init(struct aac_dev *dev)
{
unsigned long start;
unsigned long status;
int restart = 0;
int instance = dev->id;
const char * name = dev->name;
if (aac_adapter_ioremap(dev, dev->base_size)) {
printk(KERN_WARNING "%s: unable to map adapter.\n", name);
goto error_iounmap;
}
/* Failure to reset here is an option ... */
dev->a_ops.adapter_sync_cmd = rx_sync_cmd;
dev->a_ops.adapter_enable_int = aac_rx_disable_interrupt;
dev->OIMR = status = rx_readb (dev, MUnit.OIMR);
if ((((status & 0x0c) != 0x0c) || aac_reset_devices || reset_devices) &&
!aac_rx_restart_adapter(dev, 0))
/* Make sure the Hardware FIFO is empty */
while ((++restart < 512) &&
(rx_readl(dev, MUnit.OutboundQueue) != 0xFFFFFFFFL));
/*
* Check to see if the board panic'd while booting.
*/
status = rx_readl(dev, MUnit.OMRx[0]);
if (status & KERNEL_PANIC) {
if (aac_rx_restart_adapter(dev, aac_rx_check_health(dev)))
goto error_iounmap;
++restart;
}
/*
* Check to see if the board failed any self tests.
*/
status = rx_readl(dev, MUnit.OMRx[0]);
if (status & SELF_TEST_FAILED) {
printk(KERN_ERR "%s%d: adapter self-test failed.\n", dev->name, instance);
goto error_iounmap;
}
/*
* Check to see if the monitor panic'd while booting.
*/
if (status & MONITOR_PANIC) {
printk(KERN_ERR "%s%d: adapter monitor panic.\n", dev->name, instance);
goto error_iounmap;
}
start = jiffies;
/*
* Wait for the adapter to be up and running. Wait up to 3 minutes
*/
while (!((status = rx_readl(dev, MUnit.OMRx[0])) & KERNEL_UP_AND_RUNNING))
{
if ((restart &&
(status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) ||
time_after(jiffies, start+HZ*startup_timeout)) {
printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n",
dev->name, instance, status);
goto error_iounmap;
}
if (!restart &&
((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) ||
time_after(jiffies, start + HZ *
((startup_timeout > 60)
? (startup_timeout - 60)
: (startup_timeout / 2))))) {
if (likely(!aac_rx_restart_adapter(dev, aac_rx_check_health(dev))))
start = jiffies;
++restart;
}
msleep(1);
}
if (restart && aac_commit)
aac_commit = 1;
/*
* Fill in the common function dispatch table.
*/
dev->a_ops.adapter_interrupt = aac_rx_interrupt_adapter;
dev->a_ops.adapter_disable_int = aac_rx_disable_interrupt;
dev->a_ops.adapter_notify = aac_rx_notify_adapter;
dev->a_ops.adapter_sync_cmd = rx_sync_cmd;
dev->a_ops.adapter_check_health = aac_rx_check_health;
dev->a_ops.adapter_restart = aac_rx_restart_adapter;
/*
* First clear out all interrupts. Then enable the one's that we
* can handle.
*/
aac_adapter_comm(dev, AAC_COMM_PRODUCER);
aac_adapter_disable_int(dev);
rx_writel(dev, MUnit.ODR, 0xffffffff);
aac_adapter_enable_int(dev);
if (aac_init_adapter(dev) == NULL)
goto error_iounmap;
aac_adapter_comm(dev, dev->comm_interface);
dev->sync_mode = 0; /* sync. mode not supported */
dev->msi = aac_msi && !pci_enable_msi(dev->pdev);
if (request_irq(dev->pdev->irq, dev->a_ops.adapter_intr,
IRQF_SHARED, "aacraid", dev) < 0) {
if (dev->msi)
pci_disable_msi(dev->pdev);
printk(KERN_ERR "%s%d: Interrupt unavailable.\n",
name, instance);
goto error_iounmap;
}
dev->dbg_base = dev->base_start;
dev->dbg_base_mapped = dev->base;
dev->dbg_size = dev->base_size;
aac_adapter_enable_int(dev);
/*
* Tell the adapter that all is configured, and it can
* start accepting requests
*/
aac_rx_start_adapter(dev);
return 0;
error_iounmap:
return -1;
}
int aac_rx_init(struct aac_dev *dev)
{
/*
* Fill in the function dispatch table.
*/
dev->a_ops.adapter_ioremap = aac_rx_ioremap;
dev->a_ops.adapter_comm = aac_rx_select_comm;
return _aac_rx_init(dev);
}

416
drivers/scsi/aacraid/sa.c Normal file
View file

@ -0,0 +1,416 @@
/*
* Adaptec AAC series RAID controller driver
* (c) Copyright 2001 Red Hat Inc.
*
* based on the old aacraid driver that is..
* Adaptec aacraid device driver for Linux.
*
* Copyright (c) 2000-2010 Adaptec, Inc.
* 2010 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Module Name:
* sa.c
*
* Abstract: Drawbridge specific support functions
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/completion.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <scsi/scsi_host.h>
#include "aacraid.h"
static irqreturn_t aac_sa_intr(int irq, void *dev_id)
{
struct aac_dev *dev = dev_id;
unsigned short intstat, mask;
intstat = sa_readw(dev, DoorbellReg_p);
/*
* Read mask and invert because drawbridge is reversed.
* This allows us to only service interrupts that have been enabled.
*/
mask = ~(sa_readw(dev, SaDbCSR.PRISETIRQMASK));
/* Check to see if this is our interrupt. If it isn't just return */
if (intstat & mask) {
if (intstat & PrintfReady) {
aac_printf(dev, sa_readl(dev, Mailbox5));
sa_writew(dev, DoorbellClrReg_p, PrintfReady); /* clear PrintfReady */
sa_writew(dev, DoorbellReg_s, PrintfDone);
} else if (intstat & DOORBELL_1) { // dev -> Host Normal Command Ready
sa_writew(dev, DoorbellClrReg_p, DOORBELL_1);
aac_command_normal(&dev->queues->queue[HostNormCmdQueue]);
} else if (intstat & DOORBELL_2) { // dev -> Host Normal Response Ready
sa_writew(dev, DoorbellClrReg_p, DOORBELL_2);
aac_response_normal(&dev->queues->queue[HostNormRespQueue]);
} else if (intstat & DOORBELL_3) { // dev -> Host Normal Command Not Full
sa_writew(dev, DoorbellClrReg_p, DOORBELL_3);
} else if (intstat & DOORBELL_4) { // dev -> Host Normal Response Not Full
sa_writew(dev, DoorbellClrReg_p, DOORBELL_4);
}
return IRQ_HANDLED;
}
return IRQ_NONE;
}
/**
* aac_sa_disable_interrupt - disable interrupt
* @dev: Which adapter to enable.
*/
static void aac_sa_disable_interrupt (struct aac_dev *dev)
{
sa_writew(dev, SaDbCSR.PRISETIRQMASK, 0xffff);
}
/**
* aac_sa_enable_interrupt - enable interrupt
* @dev: Which adapter to enable.
*/
static void aac_sa_enable_interrupt (struct aac_dev *dev)
{
sa_writew(dev, SaDbCSR.PRICLEARIRQMASK, (PrintfReady | DOORBELL_1 |
DOORBELL_2 | DOORBELL_3 | DOORBELL_4));
}
/**
* aac_sa_notify_adapter - handle adapter notification
* @dev: Adapter that notification is for
* @event: Event to notidy
*
* Notify the adapter of an event
*/
static void aac_sa_notify_adapter(struct aac_dev *dev, u32 event)
{
switch (event) {
case AdapNormCmdQue:
sa_writew(dev, DoorbellReg_s,DOORBELL_1);
break;
case HostNormRespNotFull:
sa_writew(dev, DoorbellReg_s,DOORBELL_4);
break;
case AdapNormRespQue:
sa_writew(dev, DoorbellReg_s,DOORBELL_2);
break;
case HostNormCmdNotFull:
sa_writew(dev, DoorbellReg_s,DOORBELL_3);
break;
case HostShutdown:
/*
sa_sync_cmd(dev, HOST_CRASHING, 0, 0, 0, 0, 0, 0,
NULL, NULL, NULL, NULL, NULL);
*/
break;
case FastIo:
sa_writew(dev, DoorbellReg_s,DOORBELL_6);
break;
case AdapPrintfDone:
sa_writew(dev, DoorbellReg_s,DOORBELL_5);
break;
default:
BUG();
break;
}
}
/**
* sa_sync_cmd - send a command and wait
* @dev: Adapter
* @command: Command to execute
* @p1: first parameter
* @ret: adapter status
*
* This routine will send a synchronous command to the adapter and wait
* for its completion.
*/
static int sa_sync_cmd(struct aac_dev *dev, u32 command,
u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6,
u32 *ret, u32 *r1, u32 *r2, u32 *r3, u32 *r4)
{
unsigned long start;
int ok;
/*
* Write the Command into Mailbox 0
*/
sa_writel(dev, Mailbox0, command);
/*
* Write the parameters into Mailboxes 1 - 4
*/
sa_writel(dev, Mailbox1, p1);
sa_writel(dev, Mailbox2, p2);
sa_writel(dev, Mailbox3, p3);
sa_writel(dev, Mailbox4, p4);
/*
* Clear the synch command doorbell to start on a clean slate.
*/
sa_writew(dev, DoorbellClrReg_p, DOORBELL_0);
/*
* Signal that there is a new synch command
*/
sa_writew(dev, DoorbellReg_s, DOORBELL_0);
ok = 0;
start = jiffies;
while(time_before(jiffies, start+30*HZ))
{
/*
* Delay 5uS so that the monitor gets access
*/
udelay(5);
/*
* Mon110 will set doorbell0 bit when it has
* completed the command.
*/
if(sa_readw(dev, DoorbellReg_p) & DOORBELL_0) {
ok = 1;
break;
}
msleep(1);
}
if (ok != 1)
return -ETIMEDOUT;
/*
* Clear the synch command doorbell.
*/
sa_writew(dev, DoorbellClrReg_p, DOORBELL_0);
/*
* Pull the synch status from Mailbox 0.
*/
if (ret)
*ret = sa_readl(dev, Mailbox0);
if (r1)
*r1 = sa_readl(dev, Mailbox1);
if (r2)
*r2 = sa_readl(dev, Mailbox2);
if (r3)
*r3 = sa_readl(dev, Mailbox3);
if (r4)
*r4 = sa_readl(dev, Mailbox4);
return 0;
}
/**
* aac_sa_interrupt_adapter - interrupt an adapter
* @dev: Which adapter to enable.
*
* Breakpoint an adapter.
*/
static void aac_sa_interrupt_adapter (struct aac_dev *dev)
{
sa_sync_cmd(dev, BREAKPOINT_REQUEST, 0, 0, 0, 0, 0, 0,
NULL, NULL, NULL, NULL, NULL);
}
/**
* aac_sa_start_adapter - activate adapter
* @dev: Adapter
*
* Start up processing on an ARM based AAC adapter
*/
static void aac_sa_start_adapter(struct aac_dev *dev)
{
struct aac_init *init;
/*
* Fill in the remaining pieces of the init.
*/
init = dev->init;
init->HostElapsedSeconds = cpu_to_le32(get_seconds());
/* We can only use a 32 bit address here */
sa_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS,
(u32)(ulong)dev->init_pa, 0, 0, 0, 0, 0,
NULL, NULL, NULL, NULL, NULL);
}
static int aac_sa_restart_adapter(struct aac_dev *dev, int bled)
{
return -EINVAL;
}
/**
* aac_sa_check_health
* @dev: device to check if healthy
*
* Will attempt to determine if the specified adapter is alive and
* capable of handling requests, returning 0 if alive.
*/
static int aac_sa_check_health(struct aac_dev *dev)
{
long status = sa_readl(dev, Mailbox7);
/*
* Check to see if the board failed any self tests.
*/
if (status & SELF_TEST_FAILED)
return -1;
/*
* Check to see if the board panic'd while booting.
*/
if (status & KERNEL_PANIC)
return -2;
/*
* Wait for the adapter to be up and running. Wait up to 3 minutes
*/
if (!(status & KERNEL_UP_AND_RUNNING))
return -3;
/*
* Everything is OK
*/
return 0;
}
/**
* aac_sa_ioremap
* @size: mapping resize request
*
*/
static int aac_sa_ioremap(struct aac_dev * dev, u32 size)
{
if (!size) {
iounmap(dev->regs.sa);
return 0;
}
dev->base = dev->regs.sa = ioremap(dev->base_start, size);
return (dev->base == NULL) ? -1 : 0;
}
/**
* aac_sa_init - initialize an ARM based AAC card
* @dev: device to configure
*
* Allocate and set up resources for the ARM based AAC variants. The
* device_interface in the commregion will be allocated and linked
* to the comm region.
*/
int aac_sa_init(struct aac_dev *dev)
{
unsigned long start;
unsigned long status;
int instance;
const char *name;
instance = dev->id;
name = dev->name;
if (aac_sa_ioremap(dev, dev->base_size)) {
printk(KERN_WARNING "%s: unable to map adapter.\n", name);
goto error_iounmap;
}
/*
* Check to see if the board failed any self tests.
*/
if (sa_readl(dev, Mailbox7) & SELF_TEST_FAILED) {
printk(KERN_WARNING "%s%d: adapter self-test failed.\n", name, instance);
goto error_iounmap;
}
/*
* Check to see if the board panic'd while booting.
*/
if (sa_readl(dev, Mailbox7) & KERNEL_PANIC) {
printk(KERN_WARNING "%s%d: adapter kernel panic'd.\n", name, instance);
goto error_iounmap;
}
start = jiffies;
/*
* Wait for the adapter to be up and running. Wait up to 3 minutes.
*/
while (!(sa_readl(dev, Mailbox7) & KERNEL_UP_AND_RUNNING)) {
if (time_after(jiffies, start+startup_timeout*HZ)) {
status = sa_readl(dev, Mailbox7);
printk(KERN_WARNING "%s%d: adapter kernel failed to start, init status = %lx.\n",
name, instance, status);
goto error_iounmap;
}
msleep(1);
}
/*
* Fill in the function dispatch table.
*/
dev->a_ops.adapter_interrupt = aac_sa_interrupt_adapter;
dev->a_ops.adapter_disable_int = aac_sa_disable_interrupt;
dev->a_ops.adapter_enable_int = aac_sa_enable_interrupt;
dev->a_ops.adapter_notify = aac_sa_notify_adapter;
dev->a_ops.adapter_sync_cmd = sa_sync_cmd;
dev->a_ops.adapter_check_health = aac_sa_check_health;
dev->a_ops.adapter_restart = aac_sa_restart_adapter;
dev->a_ops.adapter_intr = aac_sa_intr;
dev->a_ops.adapter_deliver = aac_rx_deliver_producer;
dev->a_ops.adapter_ioremap = aac_sa_ioremap;
/*
* First clear out all interrupts. Then enable the one's that
* we can handle.
*/
aac_adapter_disable_int(dev);
aac_adapter_enable_int(dev);
if(aac_init_adapter(dev) == NULL)
goto error_irq;
dev->sync_mode = 0; /* sync. mode not supported */
if (request_irq(dev->pdev->irq, dev->a_ops.adapter_intr,
IRQF_SHARED, "aacraid", (void *)dev) < 0) {
printk(KERN_WARNING "%s%d: Interrupt unavailable.\n",
name, instance);
goto error_iounmap;
}
dev->dbg_base = dev->base_start;
dev->dbg_base_mapped = dev->base;
dev->dbg_size = dev->base_size;
aac_adapter_enable_int(dev);
/*
* Tell the adapter that all is configure, and it can start
* accepting requests
*/
aac_sa_start_adapter(dev);
return 0;
error_irq:
aac_sa_disable_interrupt(dev);
free_irq(dev->pdev->irq, (void *)dev);
error_iounmap:
return -1;
}

833
drivers/scsi/aacraid/src.c Normal file
View file

@ -0,0 +1,833 @@
/*
* Adaptec AAC series RAID controller driver
* (c) Copyright 2001 Red Hat Inc.
*
* based on the old aacraid driver that is..
* Adaptec aacraid device driver for Linux.
*
* Copyright (c) 2000-2010 Adaptec, Inc.
* 2010 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Module Name:
* src.c
*
* Abstract: Hardware Device Interface for PMC SRC based controllers
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/completion.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <scsi/scsi_host.h>
#include "aacraid.h"
static irqreturn_t aac_src_intr_message(int irq, void *dev_id)
{
struct aac_dev *dev = dev_id;
unsigned long bellbits, bellbits_shifted;
int our_interrupt = 0;
int isFastResponse;
u32 index, handle;
bellbits = src_readl(dev, MUnit.ODR_R);
if (bellbits & PmDoorBellResponseSent) {
bellbits = PmDoorBellResponseSent;
/* handle async. status */
src_writel(dev, MUnit.ODR_C, bellbits);
src_readl(dev, MUnit.ODR_C);
our_interrupt = 1;
index = dev->host_rrq_idx;
for (;;) {
isFastResponse = 0;
/* remove toggle bit (31) */
handle = le32_to_cpu(dev->host_rrq[index]) & 0x7fffffff;
/* check fast response bit (30) */
if (handle & 0x40000000)
isFastResponse = 1;
handle &= 0x0000ffff;
if (handle == 0)
break;
aac_intr_normal(dev, handle-1, 0, isFastResponse, NULL);
dev->host_rrq[index++] = 0;
if (index == dev->scsi_host_ptr->can_queue +
AAC_NUM_MGT_FIB)
index = 0;
dev->host_rrq_idx = index;
}
} else {
bellbits_shifted = (bellbits >> SRC_ODR_SHIFT);
if (bellbits_shifted & DoorBellAifPending) {
src_writel(dev, MUnit.ODR_C, bellbits);
src_readl(dev, MUnit.ODR_C);
our_interrupt = 1;
/* handle AIF */
aac_intr_normal(dev, 0, 2, 0, NULL);
} else if (bellbits_shifted & OUTBOUNDDOORBELL_0) {
unsigned long sflags;
struct list_head *entry;
int send_it = 0;
extern int aac_sync_mode;
src_writel(dev, MUnit.ODR_C, bellbits);
src_readl(dev, MUnit.ODR_C);
if (!aac_sync_mode) {
src_writel(dev, MUnit.ODR_C, bellbits);
src_readl(dev, MUnit.ODR_C);
our_interrupt = 1;
}
if (dev->sync_fib) {
our_interrupt = 1;
if (dev->sync_fib->callback)
dev->sync_fib->callback(dev->sync_fib->callback_data,
dev->sync_fib);
spin_lock_irqsave(&dev->sync_fib->event_lock, sflags);
if (dev->sync_fib->flags & FIB_CONTEXT_FLAG_WAIT) {
dev->management_fib_count--;
up(&dev->sync_fib->event_wait);
}
spin_unlock_irqrestore(&dev->sync_fib->event_lock, sflags);
spin_lock_irqsave(&dev->sync_lock, sflags);
if (!list_empty(&dev->sync_fib_list)) {
entry = dev->sync_fib_list.next;
dev->sync_fib = list_entry(entry, struct fib, fiblink);
list_del(entry);
send_it = 1;
} else {
dev->sync_fib = NULL;
}
spin_unlock_irqrestore(&dev->sync_lock, sflags);
if (send_it) {
aac_adapter_sync_cmd(dev, SEND_SYNCHRONOUS_FIB,
(u32)dev->sync_fib->hw_fib_pa, 0, 0, 0, 0, 0,
NULL, NULL, NULL, NULL, NULL);
}
}
}
}
if (our_interrupt) {
return IRQ_HANDLED;
}
return IRQ_NONE;
}
/**
* aac_src_disable_interrupt - Disable interrupts
* @dev: Adapter
*/
static void aac_src_disable_interrupt(struct aac_dev *dev)
{
src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff);
}
/**
* aac_src_enable_interrupt_message - Enable interrupts
* @dev: Adapter
*/
static void aac_src_enable_interrupt_message(struct aac_dev *dev)
{
src_writel(dev, MUnit.OIMR, dev->OIMR = 0xfffffff8);
}
/**
* src_sync_cmd - send a command and wait
* @dev: Adapter
* @command: Command to execute
* @p1: first parameter
* @ret: adapter status
*
* This routine will send a synchronous command to the adapter and wait
* for its completion.
*/
static int src_sync_cmd(struct aac_dev *dev, u32 command,
u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6,
u32 *status, u32 * r1, u32 * r2, u32 * r3, u32 * r4)
{
unsigned long start;
int ok;
/*
* Write the command into Mailbox 0
*/
writel(command, &dev->IndexRegs->Mailbox[0]);
/*
* Write the parameters into Mailboxes 1 - 6
*/
writel(p1, &dev->IndexRegs->Mailbox[1]);
writel(p2, &dev->IndexRegs->Mailbox[2]);
writel(p3, &dev->IndexRegs->Mailbox[3]);
writel(p4, &dev->IndexRegs->Mailbox[4]);
/*
* Clear the synch command doorbell to start on a clean slate.
*/
src_writel(dev, MUnit.ODR_C, OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
/*
* Disable doorbell interrupts
*/
src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff);
/*
* Force the completion of the mask register write before issuing
* the interrupt.
*/
src_readl(dev, MUnit.OIMR);
/*
* Signal that there is a new synch command
*/
src_writel(dev, MUnit.IDR, INBOUNDDOORBELL_0 << SRC_IDR_SHIFT);
if (!dev->sync_mode || command != SEND_SYNCHRONOUS_FIB) {
ok = 0;
start = jiffies;
/*
* Wait up to 5 minutes
*/
while (time_before(jiffies, start+300*HZ)) {
udelay(5); /* Delay 5 microseconds to let Mon960 get info. */
/*
* Mon960 will set doorbell0 bit when it has completed the command.
*/
if ((src_readl(dev, MUnit.ODR_R) >> SRC_ODR_SHIFT) & OUTBOUNDDOORBELL_0) {
/*
* Clear the doorbell.
*/
src_writel(dev, MUnit.ODR_C, OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
ok = 1;
break;
}
/*
* Yield the processor in case we are slow
*/
msleep(1);
}
if (unlikely(ok != 1)) {
/*
* Restore interrupt mask even though we timed out
*/
aac_adapter_enable_int(dev);
return -ETIMEDOUT;
}
/*
* Pull the synch status from Mailbox 0.
*/
if (status)
*status = readl(&dev->IndexRegs->Mailbox[0]);
if (r1)
*r1 = readl(&dev->IndexRegs->Mailbox[1]);
if (r2)
*r2 = readl(&dev->IndexRegs->Mailbox[2]);
if (r3)
*r3 = readl(&dev->IndexRegs->Mailbox[3]);
if (r4)
*r4 = readl(&dev->IndexRegs->Mailbox[4]);
/*
* Clear the synch command doorbell.
*/
src_writel(dev, MUnit.ODR_C, OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
}
/*
* Restore interrupt mask
*/
aac_adapter_enable_int(dev);
return 0;
}
/**
* aac_src_interrupt_adapter - interrupt adapter
* @dev: Adapter
*
* Send an interrupt to the i960 and breakpoint it.
*/
static void aac_src_interrupt_adapter(struct aac_dev *dev)
{
src_sync_cmd(dev, BREAKPOINT_REQUEST,
0, 0, 0, 0, 0, 0,
NULL, NULL, NULL, NULL, NULL);
}
/**
* aac_src_notify_adapter - send an event to the adapter
* @dev: Adapter
* @event: Event to send
*
* Notify the i960 that something it probably cares about has
* happened.
*/
static void aac_src_notify_adapter(struct aac_dev *dev, u32 event)
{
switch (event) {
case AdapNormCmdQue:
src_writel(dev, MUnit.ODR_C,
INBOUNDDOORBELL_1 << SRC_ODR_SHIFT);
break;
case HostNormRespNotFull:
src_writel(dev, MUnit.ODR_C,
INBOUNDDOORBELL_4 << SRC_ODR_SHIFT);
break;
case AdapNormRespQue:
src_writel(dev, MUnit.ODR_C,
INBOUNDDOORBELL_2 << SRC_ODR_SHIFT);
break;
case HostNormCmdNotFull:
src_writel(dev, MUnit.ODR_C,
INBOUNDDOORBELL_3 << SRC_ODR_SHIFT);
break;
case FastIo:
src_writel(dev, MUnit.ODR_C,
INBOUNDDOORBELL_6 << SRC_ODR_SHIFT);
break;
case AdapPrintfDone:
src_writel(dev, MUnit.ODR_C,
INBOUNDDOORBELL_5 << SRC_ODR_SHIFT);
break;
default:
BUG();
break;
}
}
/**
* aac_src_start_adapter - activate adapter
* @dev: Adapter
*
* Start up processing on an i960 based AAC adapter
*/
static void aac_src_start_adapter(struct aac_dev *dev)
{
struct aac_init *init;
/* reset host_rrq_idx first */
dev->host_rrq_idx = 0;
init = dev->init;
init->HostElapsedSeconds = cpu_to_le32(get_seconds());
/* We can only use a 32 bit address here */
src_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS, (u32)(ulong)dev->init_pa,
0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL);
}
/**
* aac_src_check_health
* @dev: device to check if healthy
*
* Will attempt to determine if the specified adapter is alive and
* capable of handling requests, returning 0 if alive.
*/
static int aac_src_check_health(struct aac_dev *dev)
{
u32 status = src_readl(dev, MUnit.OMR);
/*
* Check to see if the board failed any self tests.
*/
if (unlikely(status & SELF_TEST_FAILED))
return -1;
/*
* Check to see if the board panic'd.
*/
if (unlikely(status & KERNEL_PANIC))
return (status >> 16) & 0xFF;
/*
* Wait for the adapter to be up and running.
*/
if (unlikely(!(status & KERNEL_UP_AND_RUNNING)))
return -3;
/*
* Everything is OK
*/
return 0;
}
/**
* aac_src_deliver_message
* @fib: fib to issue
*
* Will send a fib, returning 0 if successful.
*/
static int aac_src_deliver_message(struct fib *fib)
{
struct aac_dev *dev = fib->dev;
struct aac_queue *q = &dev->queues->queue[AdapNormCmdQueue];
unsigned long qflags;
u32 fibsize;
dma_addr_t address;
struct aac_fib_xporthdr *pFibX;
u16 hdr_size = le16_to_cpu(fib->hw_fib_va->header.Size);
spin_lock_irqsave(q->lock, qflags);
q->numpending++;
spin_unlock_irqrestore(q->lock, qflags);
if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE2) {
/* Calculate the amount to the fibsize bits */
fibsize = (hdr_size + 127) / 128 - 1;
if (fibsize > (ALIGN32 - 1))
return -EMSGSIZE;
/* New FIB header, 32-bit */
address = fib->hw_fib_pa;
fib->hw_fib_va->header.StructType = FIB_MAGIC2;
fib->hw_fib_va->header.SenderFibAddress = (u32)address;
fib->hw_fib_va->header.u.TimeStamp = 0;
BUG_ON(upper_32_bits(address) != 0L);
address |= fibsize;
} else {
/* Calculate the amount to the fibsize bits */
fibsize = (sizeof(struct aac_fib_xporthdr) + hdr_size + 127) / 128 - 1;
if (fibsize > (ALIGN32 - 1))
return -EMSGSIZE;
/* Fill XPORT header */
pFibX = (void *)fib->hw_fib_va - sizeof(struct aac_fib_xporthdr);
pFibX->Handle = cpu_to_le32(fib->hw_fib_va->header.Handle);
pFibX->HostAddress = cpu_to_le64(fib->hw_fib_pa);
pFibX->Size = cpu_to_le32(hdr_size);
/*
* The xport header has been 32-byte aligned for us so that fibsize
* can be masked out of this address by hardware. -- BenC
*/
address = fib->hw_fib_pa - sizeof(struct aac_fib_xporthdr);
if (address & (ALIGN32 - 1))
return -EINVAL;
address |= fibsize;
}
src_writel(dev, MUnit.IQ_H, upper_32_bits(address) & 0xffffffff);
src_writel(dev, MUnit.IQ_L, address & 0xffffffff);
return 0;
}
/**
* aac_src_ioremap
* @size: mapping resize request
*
*/
static int aac_src_ioremap(struct aac_dev *dev, u32 size)
{
if (!size) {
iounmap(dev->regs.src.bar1);
dev->regs.src.bar1 = NULL;
iounmap(dev->regs.src.bar0);
dev->base = dev->regs.src.bar0 = NULL;
return 0;
}
dev->regs.src.bar1 = ioremap(pci_resource_start(dev->pdev, 2),
AAC_MIN_SRC_BAR1_SIZE);
dev->base = NULL;
if (dev->regs.src.bar1 == NULL)
return -1;
dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size);
if (dev->base == NULL) {
iounmap(dev->regs.src.bar1);
dev->regs.src.bar1 = NULL;
return -1;
}
dev->IndexRegs = &((struct src_registers __iomem *)
dev->base)->u.tupelo.IndexRegs;
return 0;
}
/**
* aac_srcv_ioremap
* @size: mapping resize request
*
*/
static int aac_srcv_ioremap(struct aac_dev *dev, u32 size)
{
if (!size) {
iounmap(dev->regs.src.bar0);
dev->base = dev->regs.src.bar0 = NULL;
return 0;
}
dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size);
if (dev->base == NULL)
return -1;
dev->IndexRegs = &((struct src_registers __iomem *)
dev->base)->u.denali.IndexRegs;
return 0;
}
static int aac_src_restart_adapter(struct aac_dev *dev, int bled)
{
u32 var, reset_mask;
if (bled >= 0) {
if (bled)
printk(KERN_ERR "%s%d: adapter kernel panic'd %x.\n",
dev->name, dev->id, bled);
bled = aac_adapter_sync_cmd(dev, IOP_RESET_ALWAYS,
0, 0, 0, 0, 0, 0, &var, &reset_mask, NULL, NULL, NULL);
if (bled || (var != 0x00000001))
return -EINVAL;
if (dev->supplement_adapter_info.SupportedOptions2 &
AAC_OPTION_DOORBELL_RESET) {
src_writel(dev, MUnit.IDR, reset_mask);
msleep(5000); /* Delay 5 seconds */
}
}
if (src_readl(dev, MUnit.OMR) & KERNEL_PANIC)
return -ENODEV;
if (startup_timeout < 300)
startup_timeout = 300;
return 0;
}
/**
* aac_src_select_comm - Select communications method
* @dev: Adapter
* @comm: communications method
*/
int aac_src_select_comm(struct aac_dev *dev, int comm)
{
switch (comm) {
case AAC_COMM_MESSAGE:
dev->a_ops.adapter_enable_int = aac_src_enable_interrupt_message;
dev->a_ops.adapter_intr = aac_src_intr_message;
dev->a_ops.adapter_deliver = aac_src_deliver_message;
break;
default:
return 1;
}
return 0;
}
/**
* aac_src_init - initialize an Cardinal Frey Bar card
* @dev: device to configure
*
*/
int aac_src_init(struct aac_dev *dev)
{
unsigned long start;
unsigned long status;
int restart = 0;
int instance = dev->id;
const char *name = dev->name;
dev->a_ops.adapter_ioremap = aac_src_ioremap;
dev->a_ops.adapter_comm = aac_src_select_comm;
dev->base_size = AAC_MIN_SRC_BAR0_SIZE;
if (aac_adapter_ioremap(dev, dev->base_size)) {
printk(KERN_WARNING "%s: unable to map adapter.\n", name);
goto error_iounmap;
}
/* Failure to reset here is an option ... */
dev->a_ops.adapter_sync_cmd = src_sync_cmd;
dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
if ((aac_reset_devices || reset_devices) &&
!aac_src_restart_adapter(dev, 0))
++restart;
/*
* Check to see if the board panic'd while booting.
*/
status = src_readl(dev, MUnit.OMR);
if (status & KERNEL_PANIC) {
if (aac_src_restart_adapter(dev, aac_src_check_health(dev)))
goto error_iounmap;
++restart;
}
/*
* Check to see if the board failed any self tests.
*/
status = src_readl(dev, MUnit.OMR);
if (status & SELF_TEST_FAILED) {
printk(KERN_ERR "%s%d: adapter self-test failed.\n",
dev->name, instance);
goto error_iounmap;
}
/*
* Check to see if the monitor panic'd while booting.
*/
if (status & MONITOR_PANIC) {
printk(KERN_ERR "%s%d: adapter monitor panic.\n",
dev->name, instance);
goto error_iounmap;
}
start = jiffies;
/*
* Wait for the adapter to be up and running. Wait up to 3 minutes
*/
while (!((status = src_readl(dev, MUnit.OMR)) &
KERNEL_UP_AND_RUNNING)) {
if ((restart &&
(status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) ||
time_after(jiffies, start+HZ*startup_timeout)) {
printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n",
dev->name, instance, status);
goto error_iounmap;
}
if (!restart &&
((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) ||
time_after(jiffies, start + HZ *
((startup_timeout > 60)
? (startup_timeout - 60)
: (startup_timeout / 2))))) {
if (likely(!aac_src_restart_adapter(dev,
aac_src_check_health(dev))))
start = jiffies;
++restart;
}
msleep(1);
}
if (restart && aac_commit)
aac_commit = 1;
/*
* Fill in the common function dispatch table.
*/
dev->a_ops.adapter_interrupt = aac_src_interrupt_adapter;
dev->a_ops.adapter_disable_int = aac_src_disable_interrupt;
dev->a_ops.adapter_notify = aac_src_notify_adapter;
dev->a_ops.adapter_sync_cmd = src_sync_cmd;
dev->a_ops.adapter_check_health = aac_src_check_health;
dev->a_ops.adapter_restart = aac_src_restart_adapter;
/*
* First clear out all interrupts. Then enable the one's that we
* can handle.
*/
aac_adapter_comm(dev, AAC_COMM_MESSAGE);
aac_adapter_disable_int(dev);
src_writel(dev, MUnit.ODR_C, 0xffffffff);
aac_adapter_enable_int(dev);
if (aac_init_adapter(dev) == NULL)
goto error_iounmap;
if (dev->comm_interface != AAC_COMM_MESSAGE_TYPE1)
goto error_iounmap;
dev->msi = aac_msi && !pci_enable_msi(dev->pdev);
if (request_irq(dev->pdev->irq, dev->a_ops.adapter_intr,
IRQF_SHARED, "aacraid", dev) < 0) {
if (dev->msi)
pci_disable_msi(dev->pdev);
printk(KERN_ERR "%s%d: Interrupt unavailable.\n",
name, instance);
goto error_iounmap;
}
dev->dbg_base = pci_resource_start(dev->pdev, 2);
dev->dbg_base_mapped = dev->regs.src.bar1;
dev->dbg_size = AAC_MIN_SRC_BAR1_SIZE;
aac_adapter_enable_int(dev);
if (!dev->sync_mode) {
/*
* Tell the adapter that all is configured, and it can
* start accepting requests
*/
aac_src_start_adapter(dev);
}
return 0;
error_iounmap:
return -1;
}
/**
* aac_srcv_init - initialize an SRCv card
* @dev: device to configure
*
*/
int aac_srcv_init(struct aac_dev *dev)
{
unsigned long start;
unsigned long status;
int restart = 0;
int instance = dev->id;
const char *name = dev->name;
dev->a_ops.adapter_ioremap = aac_srcv_ioremap;
dev->a_ops.adapter_comm = aac_src_select_comm;
dev->base_size = AAC_MIN_SRCV_BAR0_SIZE;
if (aac_adapter_ioremap(dev, dev->base_size)) {
printk(KERN_WARNING "%s: unable to map adapter.\n", name);
goto error_iounmap;
}
/* Failure to reset here is an option ... */
dev->a_ops.adapter_sync_cmd = src_sync_cmd;
dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
if ((aac_reset_devices || reset_devices) &&
!aac_src_restart_adapter(dev, 0))
++restart;
/*
* Check to see if flash update is running.
* Wait for the adapter to be up and running. Wait up to 5 minutes
*/
status = src_readl(dev, MUnit.OMR);
if (status & FLASH_UPD_PENDING) {
start = jiffies;
do {
status = src_readl(dev, MUnit.OMR);
if (time_after(jiffies, start+HZ*FWUPD_TIMEOUT)) {
printk(KERN_ERR "%s%d: adapter flash update failed.\n",
dev->name, instance);
goto error_iounmap;
}
} while (!(status & FLASH_UPD_SUCCESS) &&
!(status & FLASH_UPD_FAILED));
/* Delay 10 seconds.
* Because right now FW is doing a soft reset,
* do not read scratch pad register at this time
*/
ssleep(10);
}
/*
* Check to see if the board panic'd while booting.
*/
status = src_readl(dev, MUnit.OMR);
if (status & KERNEL_PANIC) {
if (aac_src_restart_adapter(dev, aac_src_check_health(dev)))
goto error_iounmap;
++restart;
}
/*
* Check to see if the board failed any self tests.
*/
status = src_readl(dev, MUnit.OMR);
if (status & SELF_TEST_FAILED) {
printk(KERN_ERR "%s%d: adapter self-test failed.\n", dev->name, instance);
goto error_iounmap;
}
/*
* Check to see if the monitor panic'd while booting.
*/
if (status & MONITOR_PANIC) {
printk(KERN_ERR "%s%d: adapter monitor panic.\n", dev->name, instance);
goto error_iounmap;
}
start = jiffies;
/*
* Wait for the adapter to be up and running. Wait up to 3 minutes
*/
while (!((status = src_readl(dev, MUnit.OMR)) &
KERNEL_UP_AND_RUNNING) ||
status == 0xffffffff) {
if ((restart &&
(status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) ||
time_after(jiffies, start+HZ*startup_timeout)) {
printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n",
dev->name, instance, status);
goto error_iounmap;
}
if (!restart &&
((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) ||
time_after(jiffies, start + HZ *
((startup_timeout > 60)
? (startup_timeout - 60)
: (startup_timeout / 2))))) {
if (likely(!aac_src_restart_adapter(dev, aac_src_check_health(dev))))
start = jiffies;
++restart;
}
msleep(1);
}
if (restart && aac_commit)
aac_commit = 1;
/*
* Fill in the common function dispatch table.
*/
dev->a_ops.adapter_interrupt = aac_src_interrupt_adapter;
dev->a_ops.adapter_disable_int = aac_src_disable_interrupt;
dev->a_ops.adapter_notify = aac_src_notify_adapter;
dev->a_ops.adapter_sync_cmd = src_sync_cmd;
dev->a_ops.adapter_check_health = aac_src_check_health;
dev->a_ops.adapter_restart = aac_src_restart_adapter;
/*
* First clear out all interrupts. Then enable the one's that we
* can handle.
*/
aac_adapter_comm(dev, AAC_COMM_MESSAGE);
aac_adapter_disable_int(dev);
src_writel(dev, MUnit.ODR_C, 0xffffffff);
aac_adapter_enable_int(dev);
if (aac_init_adapter(dev) == NULL)
goto error_iounmap;
if (dev->comm_interface != AAC_COMM_MESSAGE_TYPE2)
goto error_iounmap;
dev->msi = aac_msi && !pci_enable_msi(dev->pdev);
if (request_irq(dev->pdev->irq, dev->a_ops.adapter_intr,
IRQF_SHARED, "aacraid", dev) < 0) {
if (dev->msi)
pci_disable_msi(dev->pdev);
printk(KERN_ERR "%s%d: Interrupt unavailable.\n",
name, instance);
goto error_iounmap;
}
dev->dbg_base = dev->base_start;
dev->dbg_base_mapped = dev->base;
dev->dbg_size = dev->base_size;
aac_adapter_enable_int(dev);
if (!dev->sync_mode) {
/*
* Tell the adapter that all is configured, and it can
* start accepting requests
*/
aac_src_start_adapter(dev);
}
return 0;
error_iounmap:
return -1;
}

12345
drivers/scsi/advansys.c Normal file
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File diff suppressed because it is too large Load diff

3947
drivers/scsi/aha152x.c Normal file
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File diff suppressed because it is too large Load diff

337
drivers/scsi/aha152x.h Normal file
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@ -0,0 +1,337 @@
#ifndef _AHA152X_H
#define _AHA152X_H
/*
* $Id: aha152x.h,v 2.7 2004/01/24 11:39:03 fischer Exp $
*/
/* number of queueable commands
(unless we support more than 1 cmd_per_lun this should do) */
#define AHA152X_MAXQUEUE 7
#define AHA152X_REVID "Adaptec 152x SCSI driver; $Revision: 2.7 $"
/* port addresses */
#define SCSISEQ (HOSTIOPORT0+0x00) /* SCSI sequence control */
#define SXFRCTL0 (HOSTIOPORT0+0x01) /* SCSI transfer control 0 */
#define SXFRCTL1 (HOSTIOPORT0+0x02) /* SCSI transfer control 1 */
#define SCSISIG (HOSTIOPORT0+0x03) /* SCSI signal in/out */
#define SCSIRATE (HOSTIOPORT0+0x04) /* SCSI rate control */
#define SELID (HOSTIOPORT0+0x05) /* selection/reselection ID */
#define SCSIID SELID /* SCSI ID */
#define SCSIDAT (HOSTIOPORT0+0x06) /* SCSI latched data */
#define SCSIBUS (HOSTIOPORT0+0x07) /* SCSI data bus */
#define STCNT0 (HOSTIOPORT0+0x08) /* SCSI transfer count 0 */
#define STCNT1 (HOSTIOPORT0+0x09) /* SCSI transfer count 1 */
#define STCNT2 (HOSTIOPORT0+0x0a) /* SCSI transfer count 2 */
#define SSTAT0 (HOSTIOPORT0+0x0b) /* SCSI interrupt status 0 */
#define SSTAT1 (HOSTIOPORT0+0x0c) /* SCSI interrupt status 1 */
#define SSTAT2 (HOSTIOPORT0+0x0d) /* SCSI interrupt status 2 */
#define SCSITEST (HOSTIOPORT0+0x0e) /* SCSI test control */
#define SSTAT3 SCSITEST /* SCSI interrupt status 3 */
#define SSTAT4 (HOSTIOPORT0+0x0f) /* SCSI status 4 */
#define SIMODE0 (HOSTIOPORT1+0x10) /* SCSI interrupt mode 0 */
#define SIMODE1 (HOSTIOPORT1+0x11) /* SCSI interrupt mode 1 */
#define DMACNTRL0 (HOSTIOPORT1+0x12) /* DMA control 0 */
#define DMACNTRL1 (HOSTIOPORT1+0x13) /* DMA control 1 */
#define DMASTAT (HOSTIOPORT1+0x14) /* DMA status */
#define FIFOSTAT (HOSTIOPORT1+0x15) /* FIFO status */
#define DATAPORT (HOSTIOPORT1+0x16) /* DATA port */
#define BRSTCNTRL (HOSTIOPORT1+0x18) /* burst control */
#define PORTA (HOSTIOPORT1+0x1a) /* PORT A */
#define PORTB (HOSTIOPORT1+0x1b) /* PORT B */
#define REV (HOSTIOPORT1+0x1c) /* revision */
#define STACK (HOSTIOPORT1+0x1d) /* stack */
#define TEST (HOSTIOPORT1+0x1e) /* test register */
#define IO_RANGE 0x20
/* used in aha152x_porttest */
#define O_PORTA 0x1a /* PORT A */
#define O_PORTB 0x1b /* PORT B */
#define O_DMACNTRL1 0x13 /* DMA control 1 */
#define O_STACK 0x1d /* stack */
/* used in tc1550_porttest */
#define O_TC_PORTA 0x0a /* PORT A */
#define O_TC_PORTB 0x0b /* PORT B */
#define O_TC_DMACNTRL1 0x03 /* DMA control 1 */
#define O_TC_STACK 0x0d /* stack */
/* bits and bitmasks to ports */
/* SCSI sequence control */
#define TEMODEO 0x80
#define ENSELO 0x40
#define ENSELI 0x20
#define ENRESELI 0x10
#define ENAUTOATNO 0x08
#define ENAUTOATNI 0x04
#define ENAUTOATNP 0x02
#define SCSIRSTO 0x01
/* SCSI transfer control 0 */
#define SCSIEN 0x80
#define DMAEN 0x40
#define CH1 0x20
#define CLRSTCNT 0x10
#define SPIOEN 0x08
#define CLRCH1 0x02
/* SCSI transfer control 1 */
#define BITBUCKET 0x80
#define SWRAPEN 0x40
#define ENSPCHK 0x20
#define STIMESEL 0x18 /* mask */
#define STIMESEL_ 3
#define ENSTIMER 0x04
#define BYTEALIGN 0x02
/* SCSI signal IN */
#define SIG_CDI 0x80
#define SIG_IOI 0x40
#define SIG_MSGI 0x20
#define SIG_ATNI 0x10
#define SIG_SELI 0x08
#define SIG_BSYI 0x04
#define SIG_REQI 0x02
#define SIG_ACKI 0x01
/* SCSI Phases */
#define P_MASK (SIG_MSGI|SIG_CDI|SIG_IOI)
#define P_DATAO (0)
#define P_DATAI (SIG_IOI)
#define P_CMD (SIG_CDI)
#define P_STATUS (SIG_CDI|SIG_IOI)
#define P_MSGO (SIG_MSGI|SIG_CDI)
#define P_MSGI (SIG_MSGI|SIG_CDI|SIG_IOI)
/* SCSI signal OUT */
#define SIG_CDO 0x80
#define SIG_IOO 0x40
#define SIG_MSGO 0x20
#define SIG_ATNO 0x10
#define SIG_SELO 0x08
#define SIG_BSYO 0x04
#define SIG_REQO 0x02
#define SIG_ACKO 0x01
/* SCSI rate control */
#define SXFR 0x70 /* mask */
#define SXFR_ 4
#define SOFS 0x0f /* mask */
/* SCSI ID */
#define OID 0x70
#define OID_ 4
#define TID 0x07
/* SCSI transfer count */
#define GETSTCNT() ( (GETPORT(STCNT2)<<16) \
+ (GETPORT(STCNT1)<< 8) \
+ GETPORT(STCNT0) )
#define SETSTCNT(X) { SETPORT(STCNT2, ((X) & 0xFF0000) >> 16); \
SETPORT(STCNT1, ((X) & 0x00FF00) >> 8); \
SETPORT(STCNT0, ((X) & 0x0000FF) ); }
/* SCSI interrupt status */
#define TARGET 0x80
#define SELDO 0x40
#define SELDI 0x20
#define SELINGO 0x10
#define SWRAP 0x08
#define SDONE 0x04
#define SPIORDY 0x02
#define DMADONE 0x01
#define SETSDONE 0x80
#define CLRSELDO 0x40
#define CLRSELDI 0x20
#define CLRSELINGO 0x10
#define CLRSWRAP 0x08
#define CLRSDONE 0x04
#define CLRSPIORDY 0x02
#define CLRDMADONE 0x01
/* SCSI status 1 */
#define SELTO 0x80
#define ATNTARG 0x40
#define SCSIRSTI 0x20
#define PHASEMIS 0x10
#define BUSFREE 0x08
#define SCSIPERR 0x04
#define PHASECHG 0x02
#define REQINIT 0x01
#define CLRSELTIMO 0x80
#define CLRATNO 0x40
#define CLRSCSIRSTI 0x20
#define CLRBUSFREE 0x08
#define CLRSCSIPERR 0x04
#define CLRPHASECHG 0x02
#define CLRREQINIT 0x01
/* SCSI status 2 */
#define SOFFSET 0x20
#define SEMPTY 0x10
#define SFULL 0x08
#define SFCNT 0x07 /* mask */
/* SCSI status 3 */
#define SCSICNT 0xf0 /* mask */
#define SCSICNT_ 4
#define OFFCNT 0x0f /* mask */
/* SCSI TEST control */
#define SCTESTU 0x08
#define SCTESTD 0x04
#define STCTEST 0x01
/* SCSI status 4 */
#define SYNCERR 0x04
#define FWERR 0x02
#define FRERR 0x01
#define CLRSYNCERR 0x04
#define CLRFWERR 0x02
#define CLRFRERR 0x01
/* SCSI interrupt mode 0 */
#define ENSELDO 0x40
#define ENSELDI 0x20
#define ENSELINGO 0x10
#define ENSWRAP 0x08
#define ENSDONE 0x04
#define ENSPIORDY 0x02
#define ENDMADONE 0x01
/* SCSI interrupt mode 1 */
#define ENSELTIMO 0x80
#define ENATNTARG 0x40
#define ENSCSIRST 0x20
#define ENPHASEMIS 0x10
#define ENBUSFREE 0x08
#define ENSCSIPERR 0x04
#define ENPHASECHG 0x02
#define ENREQINIT 0x01
/* DMA control 0 */
#define ENDMA 0x80
#define _8BIT 0x40
#define DMA 0x20
#define WRITE_READ 0x08
#define INTEN 0x04
#define RSTFIFO 0x02
#define SWINT 0x01
/* DMA control 1 */
#define PWRDWN 0x80
#define STK 0x07 /* mask */
/* DMA status */
#define ATDONE 0x80
#define WORDRDY 0x40
#define INTSTAT 0x20
#define DFIFOFULL 0x10
#define DFIFOEMP 0x08
/* BURST control */
#define BON 0xf0
#define BOFF 0x0f
/* TEST REGISTER */
#define BOFFTMR 0x40
#define BONTMR 0x20
#define STCNTH 0x10
#define STCNTM 0x08
#define STCNTL 0x04
#define SCSIBLK 0x02
#define DMABLK 0x01
/* On the AHA-152x board PORTA and PORTB contain
some information about the board's configuration. */
typedef union {
struct {
unsigned reserved:2; /* reserved */
unsigned tardisc:1; /* Target disconnect: 0=disabled, 1=enabled */
unsigned syncneg:1; /* Initial sync neg: 0=disabled, 1=enabled */
unsigned msgclasses:2; /* Message classes
0=#4
1=#0, #1, #2, #3, #4
2=#0, #3, #4
3=#0, #4
*/
unsigned boot:1; /* boot: 0=disabled, 1=enabled */
unsigned dma:1; /* Transfer mode: 0=PIO; 1=DMA */
unsigned id:3; /* SCSI-id */
unsigned irq:2; /* IRQ-Channel: 0,3=12, 1=10, 2=11 */
unsigned dmachan:2; /* DMA-Channel: 0=0, 1=5, 2=6, 3=7 */
unsigned parity:1; /* SCSI-parity: 1=enabled 0=disabled */
} fields;
unsigned short port;
} aha152x_config ;
#define cf_parity fields.parity
#define cf_dmachan fields.dmachan
#define cf_irq fields.irq
#define cf_id fields.id
#define cf_dma fields.dma
#define cf_boot fields.boot
#define cf_msgclasses fields.msgclasses
#define cf_syncneg fields.syncneg
#define cf_tardisc fields.tardisc
#define cf_port port
/* Some macros to manipulate ports and their bits */
#define SETPORT(PORT, VAL) outb( (VAL), (PORT) )
#define GETPORT(PORT) inb( PORT )
#define SETBITS(PORT, BITS) outb( (inb(PORT) | (BITS)), (PORT) )
#define CLRBITS(PORT, BITS) outb( (inb(PORT) & ~(BITS)), (PORT) )
#define TESTHI(PORT, BITS) ((inb(PORT) & (BITS)) == (BITS))
#define TESTLO(PORT, BITS) ((inb(PORT) & (BITS)) == 0)
#define SETRATE(RATE) SETPORT(SCSIRATE,(RATE) & 0x7f)
#if defined(AHA152X_DEBUG)
enum {
debug_procinfo = 0x0001,
debug_queue = 0x0002,
debug_locking = 0x0004,
debug_intr = 0x0008,
debug_selection = 0x0010,
debug_msgo = 0x0020,
debug_msgi = 0x0040,
debug_status = 0x0080,
debug_cmd = 0x0100,
debug_datai = 0x0200,
debug_datao = 0x0400,
debug_eh = 0x0800,
debug_done = 0x1000,
debug_phases = 0x2000,
};
#endif
/* for the pcmcia stub */
struct aha152x_setup {
int io_port;
int irq;
int scsiid;
int reconnect;
int parity;
int synchronous;
int delay;
int ext_trans;
int tc1550;
#if defined(AHA152X_DEBUG)
int debug;
#endif
char *conf;
};
struct Scsi_Host *aha152x_probe_one(struct aha152x_setup *);
void aha152x_release(struct Scsi_Host *);
int aha152x_host_reset_host(struct Scsi_Host *);
#endif /* _AHA152X_H */

1682
drivers/scsi/aha1542.c Normal file
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150
drivers/scsi/aha1542.h Normal file
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#ifndef _AHA1542_H
/* $Id: aha1542.h,v 1.1 1992/07/24 06:27:38 root Exp root $
*
* Header file for the adaptec 1542 driver for Linux
*
* $Log: aha1542.h,v $
* Revision 1.1 1992/07/24 06:27:38 root
* Initial revision
*
* Revision 1.2 1992/07/04 18:41:49 root
* Replaced distribution with current drivers
*
* Revision 1.3 1992/06/23 23:58:20 root
* Fixes.
*
* Revision 1.2 1992/05/26 22:13:23 root
* Changed bug that prevented DMA above first 2 mbytes.
*
* Revision 1.1 1992/05/22 21:00:29 root
* Initial revision
*
* Revision 1.1 1992/04/24 18:01:50 root
* Initial revision
*
* Revision 1.1 1992/04/02 03:23:13 drew
* Initial revision
*
* Revision 1.3 1992/01/27 14:46:29 tthorn
* *** empty log message ***
*
*/
#include <linux/types.h>
/* I/O Port interface 4.2 */
/* READ */
#define STATUS(base) base
#define STST 0x80 /* Self Test in Progress */
#define DIAGF 0x40 /* Internal Diagnostic Failure */
#define INIT 0x20 /* Mailbox Initialization Required */
#define IDLE 0x10 /* SCSI Host Adapter Idle */
#define CDF 0x08 /* Command/Data Out Port Full */
#define DF 0x04 /* Data In Port Full */
#define INVDCMD 0x01 /* Invalid H A Command */
#define STATMASK 0xfd /* 0x02 is reserved */
#define INTRFLAGS(base) (STATUS(base)+2)
#define ANYINTR 0x80 /* Any Interrupt */
#define SCRD 0x08 /* SCSI Reset Detected */
#define HACC 0x04 /* HA Command Complete */
#define MBOA 0x02 /* MBO Empty */
#define MBIF 0x01 /* MBI Full */
#define INTRMASK 0x8f
/* WRITE */
#define CONTROL(base) STATUS(base)
#define HRST 0x80 /* Hard Reset */
#define SRST 0x40 /* Soft Reset */
#define IRST 0x20 /* Interrupt Reset */
#define SCRST 0x10 /* SCSI Bus Reset */
/* READ/WRITE */
#define DATA(base) (STATUS(base)+1)
#define CMD_NOP 0x00 /* No Operation */
#define CMD_MBINIT 0x01 /* Mailbox Initialization */
#define CMD_START_SCSI 0x02 /* Start SCSI Command */
#define CMD_INQUIRY 0x04 /* Adapter Inquiry */
#define CMD_EMBOI 0x05 /* Enable MailBox Out Interrupt */
#define CMD_BUSON_TIME 0x07 /* Set Bus-On Time */
#define CMD_BUSOFF_TIME 0x08 /* Set Bus-Off Time */
#define CMD_DMASPEED 0x09 /* Set AT Bus Transfer Speed */
#define CMD_RETDEVS 0x0a /* Return Installed Devices */
#define CMD_RETCONF 0x0b /* Return Configuration Data */
#define CMD_RETSETUP 0x0d /* Return Setup Data */
#define CMD_ECHO 0x1f /* ECHO Command Data */
#define CMD_EXTBIOS 0x28 /* Return extend bios information only 1542C */
#define CMD_MBENABLE 0x29 /* Set Mailbox Interface enable only 1542C */
/* Mailbox Definition 5.2.1 and 5.2.2 */
struct mailbox {
unchar status; /* Command/Status */
unchar ccbptr[3]; /* msb, .., lsb */
};
/* This is used with scatter-gather */
struct chain {
unchar datalen[3]; /* Size of this part of chain */
unchar dataptr[3]; /* Location of data */
};
/* These belong in scsi.h also */
static inline void any2scsi(u8 *p, u32 v)
{
p[0] = v >> 16;
p[1] = v >> 8;
p[2] = v;
}
#define scsi2int(up) ( (((long)*(up)) << 16) + (((long)(up)[1]) << 8) + ((long)(up)[2]) )
#define xany2scsi(up, p) \
(up)[0] = ((long)(p)) >> 24; \
(up)[1] = ((long)(p)) >> 16; \
(up)[2] = ((long)(p)) >> 8; \
(up)[3] = ((long)(p));
#define xscsi2int(up) ( (((long)(up)[0]) << 24) + (((long)(up)[1]) << 16) \
+ (((long)(up)[2]) << 8) + ((long)(up)[3]) )
#define MAX_CDB 12
#define MAX_SENSE 14
struct ccb { /* Command Control Block 5.3 */
unchar op; /* Command Control Block Operation Code */
unchar idlun; /* op=0,2:Target Id, op=1:Initiator Id */
/* Outbound data transfer, length is checked*/
/* Inbound data transfer, length is checked */
/* Logical Unit Number */
unchar cdblen; /* SCSI Command Length */
unchar rsalen; /* Request Sense Allocation Length/Disable */
unchar datalen[3]; /* Data Length (msb, .., lsb) */
unchar dataptr[3]; /* Data Pointer */
unchar linkptr[3]; /* Link Pointer */
unchar commlinkid; /* Command Linking Identifier */
unchar hastat; /* Host Adapter Status (HASTAT) */
unchar tarstat; /* Target Device Status */
unchar reserved[2];
unchar cdb[MAX_CDB+MAX_SENSE];/* SCSI Command Descriptor Block */
/* REQUEST SENSE */
};
static int aha1542_detect(struct scsi_host_template *);
static int aha1542_queuecommand(struct Scsi_Host *, struct scsi_cmnd *);
static int aha1542_bus_reset(Scsi_Cmnd * SCpnt);
static int aha1542_dev_reset(Scsi_Cmnd * SCpnt);
static int aha1542_host_reset(Scsi_Cmnd * SCpnt);
#if 0
static int aha1542_old_abort(Scsi_Cmnd * SCpnt);
static int aha1542_old_reset(Scsi_Cmnd *, unsigned int);
#endif
static int aha1542_biosparam(struct scsi_device *, struct block_device *,
sector_t, int *);
#define AHA1542_MAILBOXES 8
#define AHA1542_SCATTER 16
#define AHA1542_CMDLUN 1
#endif

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drivers/scsi/aha1740.c Normal file
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/* $Id$
* 1993/03/31
* linux/kernel/aha1740.c
*
* Based loosely on aha1542.c which is
* Copyright (C) 1992 Tommy Thorn and
* Modified by Eric Youngdale
*
* This file is aha1740.c, written and
* Copyright (C) 1992,1993 Brad McLean
* brad@saturn.gaylord.com or brad@bradpc.gaylord.com.
*
* Modifications to makecode and queuecommand
* for proper handling of multiple devices courteously
* provided by Michael Weller, March, 1993
*
* Multiple adapter support, extended translation detection,
* update to current scsi subsystem changes, proc fs support,
* working (!) module support based on patches from Andreas Arens,
* by Andreas Degert <ad@papyrus.hamburg.com>, 2/1997
*
* aha1740_makecode may still need even more work
* if it doesn't work for your devices, take a look.
*
* Reworked for new_eh and new locking by Alan Cox <alan@lxorguk.ukuu.org.uk>
*
* Converted to EISA and generic DMA APIs by Marc Zyngier
* <maz@wild-wind.fr.eu.org>, 4/2003.
*
* Shared interrupt support added by Rask Ingemann Lambertsen
* <rask@sygehus.dk>, 10/2003
*
* For the avoidance of doubt the "preferred form" of this code is one which
* is in an open non patent encumbered format. Where cryptographic key signing
* forms part of the process of creating an executable the information
* including keys needed to generate an equivalently functional executable
* are deemed to be part of the source code.
*/
#include <linux/blkdev.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/ioport.h>
#include <linux/proc_fs.h>
#include <linux/stat.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/eisa.h>
#include <linux/dma-mapping.h>
#include <linux/gfp.h>
#include <asm/dma.h>
#include <asm/io.h>
#include "scsi.h"
#include <scsi/scsi_host.h>
#include "aha1740.h"
/* IF YOU ARE HAVING PROBLEMS WITH THIS DRIVER, AND WANT TO WATCH
IT WORK, THEN:
#define DEBUG
*/
#ifdef DEBUG
#define DEB(x) x
#else
#define DEB(x)
#endif
struct aha1740_hostdata {
struct eisa_device *edev;
unsigned int translation;
unsigned int last_ecb_used;
dma_addr_t ecb_dma_addr;
struct ecb ecb[AHA1740_ECBS];
};
struct aha1740_sg {
struct aha1740_chain sg_chain[AHA1740_SCATTER];
dma_addr_t sg_dma_addr;
dma_addr_t buf_dma_addr;
};
#define HOSTDATA(host) ((struct aha1740_hostdata *) &host->hostdata)
static inline struct ecb *ecb_dma_to_cpu (struct Scsi_Host *host,
dma_addr_t dma)
{
struct aha1740_hostdata *hdata = HOSTDATA (host);
dma_addr_t offset;
offset = dma - hdata->ecb_dma_addr;
return (struct ecb *)(((char *) hdata->ecb) + (unsigned int) offset);
}
static inline dma_addr_t ecb_cpu_to_dma (struct Scsi_Host *host, void *cpu)
{
struct aha1740_hostdata *hdata = HOSTDATA (host);
dma_addr_t offset;
offset = (char *) cpu - (char *) hdata->ecb;
return hdata->ecb_dma_addr + offset;
}
static int aha1740_show_info(struct seq_file *m, struct Scsi_Host *shpnt)
{
struct aha1740_hostdata *host = HOSTDATA(shpnt);
seq_printf(m, "aha174x at IO:%lx, IRQ %d, SLOT %d.\n"
"Extended translation %sabled.\n",
shpnt->io_port, shpnt->irq, host->edev->slot,
host->translation ? "en" : "dis");
return 0;
}
static int aha1740_makecode(unchar *sense, unchar *status)
{
struct statusword
{
ushort don:1, /* Command Done - No Error */
du:1, /* Data underrun */
:1, qf:1, /* Queue full */
sc:1, /* Specification Check */
dor:1, /* Data overrun */
ch:1, /* Chaining Halted */
intr:1, /* Interrupt issued */
asa:1, /* Additional Status Available */
sns:1, /* Sense information Stored */
:1, ini:1, /* Initialization Required */
me:1, /* Major error or exception */
:1, eca:1, /* Extended Contingent alliance */
:1;
} status_word;
int retval = DID_OK;
status_word = * (struct statusword *) status;
#ifdef DEBUG
printk("makecode from %x,%x,%x,%x %x,%x,%x,%x",
status[0], status[1], status[2], status[3],
sense[0], sense[1], sense[2], sense[3]);
#endif
if (!status_word.don) { /* Anything abnormal was detected */
if ( (status[1]&0x18) || status_word.sc ) {
/*Additional info available*/
/* Use the supplied info for further diagnostics */
switch ( status[2] ) {
case 0x12:
if ( status_word.dor )
retval=DID_ERROR; /* It's an Overrun */
/* If not overrun, assume underrun and
* ignore it! */
case 0x00: /* No info, assume no error, should
* not occur */
break;
case 0x11:
case 0x21:
retval=DID_TIME_OUT;
break;
case 0x0a:
retval=DID_BAD_TARGET;
break;
case 0x04:
case 0x05:
retval=DID_ABORT;
/* Either by this driver or the
* AHA1740 itself */
break;
default:
retval=DID_ERROR; /* No further
* diagnostics
* possible */
}
} else {
/* Michael suggests, and Brad concurs: */
if ( status_word.qf ) {
retval = DID_TIME_OUT; /* forces a redo */
/* I think this specific one should
* not happen -Brad */
printk("aha1740.c: WARNING: AHA1740 queue overflow!\n");
} else
if ( status[0]&0x60 ) {
/* Didn't find a better error */
retval = DID_ERROR;
}
/* In any other case return DID_OK so for example
CONDITION_CHECKS make it through to the appropriate
device driver */
}
}
/* Under all circumstances supply the target status -Michael */
return status[3] | retval << 16;
}
static int aha1740_test_port(unsigned int base)
{
if ( inb(PORTADR(base)) & PORTADDR_ENH )
return 1; /* Okay, we're all set */
printk("aha174x: Board detected, but not in enhanced mode, so disabled it.\n");
return 0;
}
/* A "high" level interrupt handler */
static irqreturn_t aha1740_intr_handle(int irq, void *dev_id)
{
struct Scsi_Host *host = (struct Scsi_Host *) dev_id;
void (*my_done)(Scsi_Cmnd *);
int errstatus, adapstat;
int number_serviced;
struct ecb *ecbptr;
Scsi_Cmnd *SCtmp;
unsigned int base;
unsigned long flags;
int handled = 0;
struct aha1740_sg *sgptr;
struct eisa_device *edev;
if (!host)
panic("aha1740.c: Irq from unknown host!\n");
spin_lock_irqsave(host->host_lock, flags);
base = host->io_port;
number_serviced = 0;
edev = HOSTDATA(host)->edev;
while(inb(G2STAT(base)) & G2STAT_INTPEND) {
handled = 1;
DEB(printk("aha1740_intr top of loop.\n"));
adapstat = inb(G2INTST(base));
ecbptr = ecb_dma_to_cpu (host, inl(MBOXIN0(base)));
outb(G2CNTRL_IRST,G2CNTRL(base)); /* interrupt reset */
switch ( adapstat & G2INTST_MASK ) {
case G2INTST_CCBRETRY:
case G2INTST_CCBERROR:
case G2INTST_CCBGOOD:
/* Host Ready -> Mailbox in complete */
outb(G2CNTRL_HRDY,G2CNTRL(base));
if (!ecbptr) {
printk("Aha1740 null ecbptr in interrupt (%x,%x,%x,%d)\n",
inb(G2STAT(base)),adapstat,
inb(G2INTST(base)), number_serviced++);
continue;
}
SCtmp = ecbptr->SCpnt;
if (!SCtmp) {
printk("Aha1740 null SCtmp in interrupt (%x,%x,%x,%d)\n",
inb(G2STAT(base)),adapstat,
inb(G2INTST(base)), number_serviced++);
continue;
}
sgptr = (struct aha1740_sg *) SCtmp->host_scribble;
scsi_dma_unmap(SCtmp);
/* Free the sg block */
dma_free_coherent (&edev->dev,
sizeof (struct aha1740_sg),
SCtmp->host_scribble,
sgptr->sg_dma_addr);
/* Fetch the sense data, and tuck it away, in
the required slot. The Adaptec
automatically fetches it, and there is no
guarantee that we will still have it in the
cdb when we come back */
if ( (adapstat & G2INTST_MASK) == G2INTST_CCBERROR ) {
memcpy(SCtmp->sense_buffer, ecbptr->sense,
SCSI_SENSE_BUFFERSIZE);
errstatus = aha1740_makecode(ecbptr->sense,ecbptr->status);
} else
errstatus = 0;
DEB(if (errstatus)
printk("aha1740_intr_handle: returning %6x\n",
errstatus));
SCtmp->result = errstatus;
my_done = ecbptr->done;
memset(ecbptr,0,sizeof(struct ecb));
if ( my_done )
my_done(SCtmp);
break;
case G2INTST_HARDFAIL:
printk(KERN_ALERT "aha1740 hardware failure!\n");
panic("aha1740.c"); /* Goodbye */
case G2INTST_ASNEVENT:
printk("aha1740 asynchronous event: %02x %02x %02x %02x %02x\n",
adapstat,
inb(MBOXIN0(base)),
inb(MBOXIN1(base)),
inb(MBOXIN2(base)),
inb(MBOXIN3(base))); /* Say What? */
/* Host Ready -> Mailbox in complete */
outb(G2CNTRL_HRDY,G2CNTRL(base));
break;
case G2INTST_CMDGOOD:
/* set immediate command success flag here: */
break;
case G2INTST_CMDERROR:
/* Set immediate command failure flag here: */
break;
}
number_serviced++;
}
spin_unlock_irqrestore(host->host_lock, flags);
return IRQ_RETVAL(handled);
}
static int aha1740_queuecommand_lck(Scsi_Cmnd * SCpnt, void (*done)(Scsi_Cmnd *))
{
unchar direction;
unchar *cmd = (unchar *) SCpnt->cmnd;
unchar target = scmd_id(SCpnt);
struct aha1740_hostdata *host = HOSTDATA(SCpnt->device->host);
unsigned long flags;
dma_addr_t sg_dma;
struct aha1740_sg *sgptr;
int ecbno, nseg;
DEB(int i);
if(*cmd == REQUEST_SENSE) {
SCpnt->result = 0;
done(SCpnt);
return 0;
}
#ifdef DEBUG
if (*cmd == READ_10 || *cmd == WRITE_10)
i = xscsi2int(cmd+2);
else if (*cmd == READ_6 || *cmd == WRITE_6)
i = scsi2int(cmd+2);
else
i = -1;
printk("aha1740_queuecommand: dev %d cmd %02x pos %d len %d ",
target, *cmd, i, bufflen);
printk("scsi cmd:");
for (i = 0; i < SCpnt->cmd_len; i++) printk("%02x ", cmd[i]);
printk("\n");
#endif
/* locate an available ecb */
spin_lock_irqsave(SCpnt->device->host->host_lock, flags);
ecbno = host->last_ecb_used + 1; /* An optimization */
if (ecbno >= AHA1740_ECBS)
ecbno = 0;
do {
if (!host->ecb[ecbno].cmdw)
break;
ecbno++;
if (ecbno >= AHA1740_ECBS)
ecbno = 0;
} while (ecbno != host->last_ecb_used);
if (host->ecb[ecbno].cmdw)
panic("Unable to find empty ecb for aha1740.\n");
host->ecb[ecbno].cmdw = AHA1740CMD_INIT; /* SCSI Initiator Command
doubles as reserved flag */
host->last_ecb_used = ecbno;
spin_unlock_irqrestore(SCpnt->device->host->host_lock, flags);
#ifdef DEBUG
printk("Sending command (%d %x)...", ecbno, done);
#endif
host->ecb[ecbno].cdblen = SCpnt->cmd_len; /* SCSI Command
* Descriptor Block
* Length */
direction = 0;
if (*cmd == READ_10 || *cmd == READ_6)
direction = 1;
else if (*cmd == WRITE_10 || *cmd == WRITE_6)
direction = 0;
memcpy(host->ecb[ecbno].cdb, cmd, SCpnt->cmd_len);
SCpnt->host_scribble = dma_alloc_coherent (&host->edev->dev,
sizeof (struct aha1740_sg),
&sg_dma, GFP_ATOMIC);
if(SCpnt->host_scribble == NULL) {
printk(KERN_WARNING "aha1740: out of memory in queuecommand!\n");
return 1;
}
sgptr = (struct aha1740_sg *) SCpnt->host_scribble;
sgptr->sg_dma_addr = sg_dma;
nseg = scsi_dma_map(SCpnt);
BUG_ON(nseg < 0);
if (nseg) {
struct scatterlist *sg;
struct aha1740_chain * cptr;
int i;
DEB(unsigned char * ptr);
host->ecb[ecbno].sg = 1; /* SCSI Initiator Command
* w/scatter-gather*/
cptr = sgptr->sg_chain;
scsi_for_each_sg(SCpnt, sg, nseg, i) {
cptr[i].datalen = sg_dma_len (sg);
cptr[i].dataptr = sg_dma_address (sg);
}
host->ecb[ecbno].datalen = nseg * sizeof(struct aha1740_chain);
host->ecb[ecbno].dataptr = sg_dma;
#ifdef DEBUG
printk("cptr %x: ",cptr);
ptr = (unsigned char *) cptr;
for(i=0;i<24;i++) printk("%02x ", ptr[i]);
#endif
} else {
host->ecb[ecbno].datalen = 0;
host->ecb[ecbno].dataptr = 0;
}
host->ecb[ecbno].lun = SCpnt->device->lun;
host->ecb[ecbno].ses = 1; /* Suppress underrun errors */
host->ecb[ecbno].dir = direction;
host->ecb[ecbno].ars = 1; /* Yes, get the sense on an error */
host->ecb[ecbno].senselen = 12;
host->ecb[ecbno].senseptr = ecb_cpu_to_dma (SCpnt->device->host,
host->ecb[ecbno].sense);
host->ecb[ecbno].statusptr = ecb_cpu_to_dma (SCpnt->device->host,
host->ecb[ecbno].status);
host->ecb[ecbno].done = done;
host->ecb[ecbno].SCpnt = SCpnt;
#ifdef DEBUG
{
int i;
printk("aha1740_command: sending.. ");
for (i = 0; i < sizeof(host->ecb[ecbno]) - 10; i++)
printk("%02x ", ((unchar *)&host->ecb[ecbno])[i]);
}
printk("\n");
#endif
if (done) {
/* The Adaptec Spec says the card is so fast that the loops
will only be executed once in the code below. Even if this
was true with the fastest processors when the spec was
written, it doesn't seem to be true with today's fast
processors. We print a warning if the code is executed more
often than LOOPCNT_WARN. If this happens, it should be
investigated. If the count reaches LOOPCNT_MAX, we assume
something is broken; since there is no way to return an
error (the return value is ignored by the mid-level scsi
layer) we have to panic (and maybe that's the best thing we
can do then anyhow). */
#define LOOPCNT_WARN 10 /* excessive mbxout wait -> syslog-msg */
#define LOOPCNT_MAX 1000000 /* mbxout deadlock -> panic() after ~ 2 sec. */
int loopcnt;
unsigned int base = SCpnt->device->host->io_port;
DEB(printk("aha1740[%d] critical section\n",ecbno));
spin_lock_irqsave(SCpnt->device->host->host_lock, flags);
for (loopcnt = 0; ; loopcnt++) {
if (inb(G2STAT(base)) & G2STAT_MBXOUT) break;
if (loopcnt == LOOPCNT_WARN) {
printk("aha1740[%d]_mbxout wait!\n",ecbno);
}
if (loopcnt == LOOPCNT_MAX)
panic("aha1740.c: mbxout busy!\n");
}
outl (ecb_cpu_to_dma (SCpnt->device->host, host->ecb + ecbno),
MBOXOUT0(base));
for (loopcnt = 0; ; loopcnt++) {
if (! (inb(G2STAT(base)) & G2STAT_BUSY)) break;
if (loopcnt == LOOPCNT_WARN) {
printk("aha1740[%d]_attn wait!\n",ecbno);
}
if (loopcnt == LOOPCNT_MAX)
panic("aha1740.c: attn wait failed!\n");
}
outb(ATTN_START | (target & 7), ATTN(base)); /* Start it up */
spin_unlock_irqrestore(SCpnt->device->host->host_lock, flags);
DEB(printk("aha1740[%d] request queued.\n",ecbno));
} else
printk(KERN_ALERT "aha1740_queuecommand: done can't be NULL\n");
return 0;
}
static DEF_SCSI_QCMD(aha1740_queuecommand)
/* Query the board for its irq_level and irq_type. Nothing else matters
in enhanced mode on an EISA bus. */
static void aha1740_getconfig(unsigned int base, unsigned int *irq_level,
unsigned int *irq_type,
unsigned int *translation)
{
static int intab[] = { 9, 10, 11, 12, 0, 14, 15, 0 };
*irq_level = intab[inb(INTDEF(base)) & 0x7];
*irq_type = (inb(INTDEF(base)) & 0x8) >> 3;
*translation = inb(RESV1(base)) & 0x1;
outb(inb(INTDEF(base)) | 0x10, INTDEF(base));
}
static int aha1740_biosparam(struct scsi_device *sdev,
struct block_device *dev,
sector_t capacity, int* ip)
{
int size = capacity;
int extended = HOSTDATA(sdev->host)->translation;
DEB(printk("aha1740_biosparam\n"));
if (extended && (ip[2] > 1024)) {
ip[0] = 255;
ip[1] = 63;
ip[2] = size / (255 * 63);
} else {
ip[0] = 64;
ip[1] = 32;
ip[2] = size >> 11;
}
return 0;
}
static int aha1740_eh_abort_handler (Scsi_Cmnd *dummy)
{
/*
* From Alan Cox :
* The AHA1740 has firmware handled abort/reset handling. The "head in
* sand" kernel code is correct for once 8)
*
* So we define a dummy handler just to keep the kernel SCSI code as
* quiet as possible...
*/
return SUCCESS;
}
static struct scsi_host_template aha1740_template = {
.module = THIS_MODULE,
.proc_name = "aha1740",
.show_info = aha1740_show_info,
.name = "Adaptec 174x (EISA)",
.queuecommand = aha1740_queuecommand,
.bios_param = aha1740_biosparam,
.can_queue = AHA1740_ECBS,
.this_id = 7,
.sg_tablesize = AHA1740_SCATTER,
.cmd_per_lun = AHA1740_CMDLUN,
.use_clustering = ENABLE_CLUSTERING,
.eh_abort_handler = aha1740_eh_abort_handler,
};
static int aha1740_probe (struct device *dev)
{
int slotbase, rc;
unsigned int irq_level, irq_type, translation;
struct Scsi_Host *shpnt;
struct aha1740_hostdata *host;
struct eisa_device *edev = to_eisa_device (dev);
DEB(printk("aha1740_probe: \n"));
slotbase = edev->base_addr + EISA_VENDOR_ID_OFFSET;
if (!request_region(slotbase, SLOTSIZE, "aha1740")) /* See if in use */
return -EBUSY;
if (!aha1740_test_port(slotbase))
goto err_release_region;
aha1740_getconfig(slotbase,&irq_level,&irq_type,&translation);
if ((inb(G2STAT(slotbase)) &
(G2STAT_MBXOUT|G2STAT_BUSY)) != G2STAT_MBXOUT) {
/* If the card isn't ready, hard reset it */
outb(G2CNTRL_HRST, G2CNTRL(slotbase));
outb(0, G2CNTRL(slotbase));
}
printk(KERN_INFO "Configuring slot %d at IO:%x, IRQ %u (%s)\n",
edev->slot, slotbase, irq_level, irq_type ? "edge" : "level");
printk(KERN_INFO "aha174x: Extended translation %sabled.\n",
translation ? "en" : "dis");
shpnt = scsi_host_alloc(&aha1740_template,
sizeof(struct aha1740_hostdata));
if(shpnt == NULL)
goto err_release_region;
shpnt->base = 0;
shpnt->io_port = slotbase;
shpnt->n_io_port = SLOTSIZE;
shpnt->irq = irq_level;
shpnt->dma_channel = 0xff;
host = HOSTDATA(shpnt);
host->edev = edev;
host->translation = translation;
host->ecb_dma_addr = dma_map_single (&edev->dev, host->ecb,
sizeof (host->ecb),
DMA_BIDIRECTIONAL);
if (!host->ecb_dma_addr) {
printk (KERN_ERR "aha1740_probe: Couldn't map ECB, giving up\n");
scsi_unregister (shpnt);
goto err_host_put;
}
DEB(printk("aha1740_probe: enable interrupt channel %d\n",irq_level));
if (request_irq(irq_level,aha1740_intr_handle,irq_type ? 0 : IRQF_SHARED,
"aha1740",shpnt)) {
printk(KERN_ERR "aha1740_probe: Unable to allocate IRQ %d.\n",
irq_level);
goto err_unmap;
}
eisa_set_drvdata (edev, shpnt);
rc = scsi_add_host (shpnt, dev);
if (rc)
goto err_irq;
scsi_scan_host (shpnt);
return 0;
err_irq:
free_irq(irq_level, shpnt);
err_unmap:
dma_unmap_single (&edev->dev, host->ecb_dma_addr,
sizeof (host->ecb), DMA_BIDIRECTIONAL);
err_host_put:
scsi_host_put (shpnt);
err_release_region:
release_region(slotbase, SLOTSIZE);
return -ENODEV;
}
static int aha1740_remove (struct device *dev)
{
struct Scsi_Host *shpnt = dev_get_drvdata(dev);
struct aha1740_hostdata *host = HOSTDATA (shpnt);
scsi_remove_host(shpnt);
free_irq (shpnt->irq, shpnt);
dma_unmap_single (dev, host->ecb_dma_addr,
sizeof (host->ecb), DMA_BIDIRECTIONAL);
release_region (shpnt->io_port, SLOTSIZE);
scsi_host_put (shpnt);
return 0;
}
static struct eisa_device_id aha1740_ids[] = {
{ "ADP0000" }, /* 1740 */
{ "ADP0001" }, /* 1740A */
{ "ADP0002" }, /* 1742A */
{ "ADP0400" }, /* 1744 */
{ "" }
};
MODULE_DEVICE_TABLE(eisa, aha1740_ids);
static struct eisa_driver aha1740_driver = {
.id_table = aha1740_ids,
.driver = {
.name = "aha1740",
.probe = aha1740_probe,
.remove = aha1740_remove,
},
};
static __init int aha1740_init (void)
{
return eisa_driver_register (&aha1740_driver);
}
static __exit void aha1740_exit (void)
{
eisa_driver_unregister (&aha1740_driver);
}
module_init (aha1740_init);
module_exit (aha1740_exit);
MODULE_LICENSE("GPL");

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#ifndef _AHA1740_H
/* $Id$
*
* Header file for the adaptec 1740 driver for Linux
*
* With minor revisions 3/31/93
* Written and (C) 1992,1993 Brad McLean. See aha1740.c
* for more info
*
*/
#include <linux/types.h>
#define SLOTSIZE 0x5c
/* EISA configuration registers & values */
#define HID0(base) (base + 0x0)
#define HID1(base) (base + 0x1)
#define HID2(base) (base + 0x2)
#define HID3(base) (base + 0x3)
#define EBCNTRL(base) (base + 0x4)
#define PORTADR(base) (base + 0x40)
#define BIOSADR(base) (base + 0x41)
#define INTDEF(base) (base + 0x42)
#define SCSIDEF(base) (base + 0x43)
#define BUSDEF(base) (base + 0x44)
#define RESV0(base) (base + 0x45)
#define RESV1(base) (base + 0x46)
#define RESV2(base) (base + 0x47)
#define HID_MFG "ADP"
#define HID_PRD 0
#define HID_REV 2
#define EBCNTRL_VALUE 1
#define PORTADDR_ENH 0x80
/* READ */
#define G2INTST(base) (base + 0x56)
#define G2STAT(base) (base + 0x57)
#define MBOXIN0(base) (base + 0x58)
#define MBOXIN1(base) (base + 0x59)
#define MBOXIN2(base) (base + 0x5a)
#define MBOXIN3(base) (base + 0x5b)
#define G2STAT2(base) (base + 0x5c)
#define G2INTST_MASK 0xf0 /* isolate the status */
#define G2INTST_CCBGOOD 0x10 /* CCB Completed */
#define G2INTST_CCBRETRY 0x50 /* CCB Completed with a retry */
#define G2INTST_HARDFAIL 0x70 /* Adapter Hardware Failure */
#define G2INTST_CMDGOOD 0xa0 /* Immediate command success */
#define G2INTST_CCBERROR 0xc0 /* CCB Completed with error */
#define G2INTST_ASNEVENT 0xd0 /* Asynchronous Event Notification */
#define G2INTST_CMDERROR 0xe0 /* Immediate command error */
#define G2STAT_MBXOUT 4 /* Mailbox Out Empty Bit */
#define G2STAT_INTPEND 2 /* Interrupt Pending Bit */
#define G2STAT_BUSY 1 /* Busy Bit (attention pending) */
#define G2STAT2_READY 0 /* Host Ready Bit */
/* WRITE (and ReadBack) */
#define MBOXOUT0(base) (base + 0x50)
#define MBOXOUT1(base) (base + 0x51)
#define MBOXOUT2(base) (base + 0x52)
#define MBOXOUT3(base) (base + 0x53)
#define ATTN(base) (base + 0x54)
#define G2CNTRL(base) (base + 0x55)
#define ATTN_IMMED 0x10 /* Immediate Command */
#define ATTN_START 0x40 /* Start CCB */
#define ATTN_ABORT 0x50 /* Abort CCB */
#define G2CNTRL_HRST 0x80 /* Hard Reset */
#define G2CNTRL_IRST 0x40 /* Clear EISA Interrupt */
#define G2CNTRL_HRDY 0x20 /* Sets HOST ready */
/* This is used with scatter-gather */
struct aha1740_chain {
u32 dataptr; /* Location of data */
u32 datalen; /* Size of this part of chain */
};
/* These belong in scsi.h */
#define any2scsi(up, p) \
(up)[0] = (((unsigned long)(p)) >> 16) ; \
(up)[1] = (((unsigned long)(p)) >> 8); \
(up)[2] = ((unsigned long)(p));
#define scsi2int(up) ( (((long)*(up)) << 16) + (((long)(up)[1]) << 8) + ((long)(up)[2]) )
#define xany2scsi(up, p) \
(up)[0] = ((long)(p)) >> 24; \
(up)[1] = ((long)(p)) >> 16; \
(up)[2] = ((long)(p)) >> 8; \
(up)[3] = ((long)(p));
#define xscsi2int(up) ( (((long)(up)[0]) << 24) + (((long)(up)[1]) << 16) \
+ (((long)(up)[2]) << 8) + ((long)(up)[3]) )
#define MAX_CDB 12
#define MAX_SENSE 14
#define MAX_STATUS 32
struct ecb { /* Enhanced Control Block 6.1 */
u16 cmdw; /* Command Word */
/* Flag Word 1 */
u16 cne:1, /* Control Block Chaining */
:6, di:1, /* Disable Interrupt */
:2, ses:1, /* Suppress Underrun error */
:1, sg:1, /* Scatter/Gather */
:1, dsb:1, /* Disable Status Block */
ars:1; /* Automatic Request Sense */
/* Flag Word 2 */
u16 lun:3, /* Logical Unit */
tag:1, /* Tagged Queuing */
tt:2, /* Tag Type */
nd:1, /* No Disconnect */
:1, dat:1, /* Data transfer - check direction */
dir:1, /* Direction of transfer 1 = datain */
st:1, /* Suppress Transfer */
chk:1, /* Calculate Checksum */
:2, rec:1,:1; /* Error Recovery */
u16 nil0; /* nothing */
u32 dataptr; /* Data or Scatter List ptr */
u32 datalen; /* Data or Scatter List len */
u32 statusptr; /* Status Block ptr */
u32 linkptr; /* Chain Address */
u32 nil1; /* nothing */
u32 senseptr; /* Sense Info Pointer */
u8 senselen; /* Sense Length */
u8 cdblen; /* CDB Length */
u16 datacheck; /* Data checksum */
u8 cdb[MAX_CDB]; /* CDB area */
/* Hardware defined portion ends here, rest is driver defined */
u8 sense[MAX_SENSE]; /* Sense area */
u8 status[MAX_STATUS]; /* Status area */
Scsi_Cmnd *SCpnt; /* Link to the SCSI Command Block */
void (*done) (Scsi_Cmnd *); /* Completion Function */
};
#define AHA1740CMD_NOP 0x00 /* No OP */
#define AHA1740CMD_INIT 0x01 /* Initiator SCSI Command */
#define AHA1740CMD_DIAG 0x05 /* Run Diagnostic Command */
#define AHA1740CMD_SCSI 0x06 /* Initialize SCSI */
#define AHA1740CMD_SENSE 0x08 /* Read Sense Information */
#define AHA1740CMD_DOWN 0x09 /* Download Firmware (yeah, I bet!) */
#define AHA1740CMD_RINQ 0x0a /* Read Host Adapter Inquiry Data */
#define AHA1740CMD_TARG 0x10 /* Target SCSI Command */
#define AHA1740_ECBS 32
#define AHA1740_SCATTER 16
#define AHA1740_CMDLUN 1
#endif

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drivers/scsi/aic7xxx/Kconfig.aic79xx Normal file
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#
# AIC79XX 2.5.X Kernel configuration File.
# $Id: //depot/linux-aic79xx-2.5.0/drivers/scsi/aic7xxx/Kconfig.aic79xx#4 $
#
config SCSI_AIC79XX
tristate "Adaptec AIC79xx U320 support"
depends on PCI && SCSI
select SCSI_SPI_ATTRS
help
This driver supports all of Adaptec's Ultra 320 PCI-X
based SCSI controllers.
config AIC79XX_CMDS_PER_DEVICE
int "Maximum number of TCQ commands per device"
depends on SCSI_AIC79XX
default "32"
---help---
Specify the number of commands you would like to allocate per SCSI
device when Tagged Command Queueing (TCQ) is enabled on that device.
This is an upper bound value for the number of tagged transactions
to be used for any device. The aic7xxx driver will automatically
vary this number based on device behavior. For devices with a
fixed maximum, the driver will eventually lock to this maximum
and display a console message indicating this value.
Due to resource allocation issues in the Linux SCSI mid-layer, using
a high number of commands per device may result in memory allocation
failures when many devices are attached to the system. For this reason,
the default is set to 32. Higher values may result in higher performance
on some devices. The upper bound is 253. 0 disables tagged queueing.
Per device tag depth can be controlled via the kernel command line
"tag_info" option. See Documentation/scsi/aic79xx.txt for details.
config AIC79XX_RESET_DELAY_MS
int "Initial bus reset delay in milli-seconds"
depends on SCSI_AIC79XX
default "5000"
---help---
The number of milliseconds to delay after an initial bus reset.
The bus settle delay following all error recovery actions is
dictated by the SCSI layer and is not affected by this value.
Default: 5000 (5 seconds)
config AIC79XX_BUILD_FIRMWARE
bool "Build Adapter Firmware with Kernel Build"
depends on SCSI_AIC79XX && !PREVENT_FIRMWARE_BUILD
help
This option should only be enabled if you are modifying the firmware
source to the aic79xx driver and wish to have the generated firmware
include files updated during a normal kernel build. The assembler
for the firmware requires lex and yacc or their equivalents, as well
as the db v1 library. You may have to install additional packages
or modify the assembler Makefile or the files it includes if your
build environment is different than that of the author.
config AIC79XX_DEBUG_ENABLE
bool "Compile in Debugging Code"
depends on SCSI_AIC79XX
default y
help
Compile in aic79xx debugging code that can be useful in diagnosing
driver errors.
config AIC79XX_DEBUG_MASK
int "Debug code enable mask (16383 for all debugging)"
depends on SCSI_AIC79XX
default "0"
help
Bit mask of debug options that is only valid if the
CONFIG_AIC79XX_DEBUG_ENABLE option is enabled. The bits in this mask
are defined in the drivers/scsi/aic7xxx/aic79xx.h - search for the
variable ahd_debug in that file to find them.
config AIC79XX_REG_PRETTY_PRINT
bool "Decode registers during diagnostics"
depends on SCSI_AIC79XX
default y
help
Compile in register value tables for the output of expanded register
contents in diagnostics. This make it much easier to understand debug
output without having to refer to a data book and/or the aic7xxx.reg
file.

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#
# AIC7XXX and AIC79XX 2.5.X Kernel configuration File.
# $Id: //depot/linux-aic79xx-2.5.0/drivers/scsi/aic7xxx/Kconfig.aic7xxx#7 $
#
config SCSI_AIC7XXX
tristate "Adaptec AIC7xxx Fast -> U160 support (New Driver)"
depends on (PCI || EISA) && SCSI
select SCSI_SPI_ATTRS
---help---
This driver supports all of Adaptec's Fast through Ultra 160 PCI
based SCSI controllers as well as the aic7770 based EISA and VLB
SCSI controllers (the 274x and 284x series). For AAA and ARO based
configurations, only SCSI functionality is provided.
To compile this driver as a module, choose M here: the
module will be called aic7xxx.
config AIC7XXX_CMDS_PER_DEVICE
int "Maximum number of TCQ commands per device"
depends on SCSI_AIC7XXX
default "32"
---help---
Specify the number of commands you would like to allocate per SCSI
device when Tagged Command Queueing (TCQ) is enabled on that device.
This is an upper bound value for the number of tagged transactions
to be used for any device. The aic7xxx driver will automatically
vary this number based on device behavior. For devices with a
fixed maximum, the driver will eventually lock to this maximum
and display a console message indicating this value.
Due to resource allocation issues in the Linux SCSI mid-layer, using
a high number of commands per device may result in memory allocation
failures when many devices are attached to the system. For this reason,
the default is set to 32. Higher values may result in higher performance
on some devices. The upper bound is 253. 0 disables tagged queueing.
Per device tag depth can be controlled via the kernel command line
"tag_info" option. See Documentation/scsi/aic7xxx.txt for details.
config AIC7XXX_RESET_DELAY_MS
int "Initial bus reset delay in milli-seconds"
depends on SCSI_AIC7XXX
default "5000"
---help---
The number of milliseconds to delay after an initial bus reset.
The bus settle delay following all error recovery actions is
dictated by the SCSI layer and is not affected by this value.
Default: 5000 (5 seconds)
config AIC7XXX_BUILD_FIRMWARE
bool "Build Adapter Firmware with Kernel Build"
depends on SCSI_AIC7XXX && !PREVENT_FIRMWARE_BUILD
help
This option should only be enabled if you are modifying the firmware
source to the aic7xxx driver and wish to have the generated firmware
include files updated during a normal kernel build. The assembler
for the firmware requires lex and yacc or their equivalents, as well
as the db v1 library. You may have to install additional packages
or modify the assembler Makefile or the files it includes if your
build environment is different than that of the author.
config AIC7XXX_DEBUG_ENABLE
bool "Compile in Debugging Code"
depends on SCSI_AIC7XXX
default y
help
Compile in aic7xxx debugging code that can be useful in diagnosing
driver errors.
config AIC7XXX_DEBUG_MASK
int "Debug code enable mask (2047 for all debugging)"
depends on SCSI_AIC7XXX
default "0"
help
Bit mask of debug options that is only valid if the
CONFIG_AIC7XXX_DEBUG_ENABLE option is enabled. The bits in this mask
are defined in the drivers/scsi/aic7xxx/aic7xxx.h - search for the
variable ahc_debug in that file to find them.
config AIC7XXX_REG_PRETTY_PRINT
bool "Decode registers during diagnostics"
depends on SCSI_AIC7XXX
default y
help
Compile in register value tables for the output of expanded register
contents in diagnostics. This make it much easier to understand debug
output without having to refer to a data book and/or the aic7xxx.reg
file.

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#
# Makefile for the Linux aic7xxx SCSI driver.
#
# $Id: //depot/linux-aic79xx-2.5.0/drivers/scsi/aic7xxx/Makefile#8 $
#
# Let kbuild descend into aicasm when cleaning
subdir- += aicasm
obj-$(CONFIG_SCSI_AIC7XXX) += aic7xxx.o
obj-$(CONFIG_SCSI_AIC79XX) += aic79xx.o
# Core Fast -> U160 files
aic7xxx-y += aic7xxx_core.o \
aic7xxx_93cx6.o
aic7xxx-$(CONFIG_EISA) += aic7770.o
aic7xxx-$(CONFIG_PCI) += aic7xxx_pci.o
aic7xxx-$(CONFIG_AIC7XXX_REG_PRETTY_PRINT) += aic7xxx_reg_print.o
# Platform Specific Fast -> U160 Files
aic7xxx-y += aic7xxx_osm.o \
aic7xxx_proc.o
aic7xxx-$(CONFIG_EISA) += aic7770_osm.o
aic7xxx-$(CONFIG_PCI) += aic7xxx_osm_pci.o
# Core U320 files
aic79xx-y += aic79xx_core.o \
aic79xx_pci.o
aic79xx-$(CONFIG_AIC79XX_REG_PRETTY_PRINT) += aic79xx_reg_print.o
# Platform Specific U320 Files
aic79xx-y += aic79xx_osm.o \
aic79xx_proc.o \
aic79xx_osm_pci.o
ccflags-y += -Idrivers/scsi
ifdef WARNINGS_BECOME_ERRORS
ccflags-y += -Werror
endif
# Files generated that shall be removed upon make clean
clean-files := aic7xxx_seq.h aic7xxx_reg.h aic7xxx_reg_print.c
clean-files += aic79xx_seq.h aic79xx_reg.h aic79xx_reg_print.c
# Dependencies for generated files need to be listed explicitly
$(addprefix $(obj)/,$(aic7xxx-y)): $(obj)/aic7xxx_seq.h $(obj)/aic7xxx_reg.h
$(addprefix $(obj)/,$(aic79xx-y)): $(obj)/aic79xx_seq.h $(obj)/aic79xx_reg.h
aic7xxx-gen-$(CONFIG_AIC7XXX_BUILD_FIRMWARE) := $(obj)/aic7xxx_reg.h
aic7xxx-gen-$(CONFIG_AIC7XXX_REG_PRETTY_PRINT) += $(obj)/aic7xxx_reg_print.c
aicasm-7xxx-opts-$(CONFIG_AIC7XXX_REG_PRETTY_PRINT) := \
-p $(obj)/aic7xxx_reg_print.c -i aic7xxx_osm.h
ifeq ($(CONFIG_AIC7XXX_BUILD_FIRMWARE),y)
$(obj)/aic7xxx_seq.h: $(src)/aic7xxx.seq $(src)/aic7xxx.reg $(obj)/aicasm/aicasm
$(obj)/aicasm/aicasm -I$(src) -r $(obj)/aic7xxx_reg.h \
$(aicasm-7xxx-opts-y) -o $(obj)/aic7xxx_seq.h \
$(src)/aic7xxx.seq
$(aic7xxx-gen-y): $(obj)/aic7xxx_seq.h
else
$(obj)/aic7xxx_reg_print.c: $(src)/aic7xxx_reg_print.c_shipped
endif
aic79xx-gen-$(CONFIG_AIC79XX_BUILD_FIRMWARE) := $(obj)/aic79xx_reg.h
aic79xx-gen-$(CONFIG_AIC79XX_REG_PRETTY_PRINT) += $(obj)/aic79xx_reg_print.c
aicasm-79xx-opts-$(CONFIG_AIC79XX_REG_PRETTY_PRINT) := \
-p $(obj)/aic79xx_reg_print.c -i aic79xx_osm.h
ifeq ($(CONFIG_AIC79XX_BUILD_FIRMWARE),y)
$(obj)/aic79xx_seq.h: $(src)/aic79xx.seq $(src)/aic79xx.reg $(obj)/aicasm/aicasm
$(obj)/aicasm/aicasm -I$(src) -r $(obj)/aic79xx_reg.h \
$(aicasm-79xx-opts-y) -o $(obj)/aic79xx_seq.h \
$(src)/aic79xx.seq
$(aic79xx-gen-y): $(obj)/aic79xx_seq.h
else
$(obj)/aic79xx_reg_print.c: $(src)/aic79xx_reg_print.c_shipped
endif
$(obj)/aicasm/aicasm: $(src)/aicasm/*.[chyl]
$(MAKE) -C $(src)/aicasm

391
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/*
* Product specific probe and attach routines for:
* 27/284X and aic7770 motherboard SCSI controllers
*
* Copyright (c) 1994-1998, 2000, 2001 Justin T. Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aic7770.c#32 $
*
* $FreeBSD$
*/
#ifdef __linux__
#include "aic7xxx_osm.h"
#include "aic7xxx_inline.h"
#include "aic7xxx_93cx6.h"
#else
#include <dev/aic7xxx/aic7xxx_osm.h>
#include <dev/aic7xxx/aic7xxx_inline.h>
#include <dev/aic7xxx/aic7xxx_93cx6.h>
#endif
#define ID_AIC7770 0x04907770
#define ID_AHA_274x 0x04907771
#define ID_AHA_284xB 0x04907756 /* BIOS enabled */
#define ID_AHA_284x 0x04907757 /* BIOS disabled*/
#define ID_OLV_274x 0x04907782 /* Olivetti OEM */
#define ID_OLV_274xD 0x04907783 /* Olivetti OEM (Differential) */
static int aic7770_chip_init(struct ahc_softc *ahc);
static int aha2840_load_seeprom(struct ahc_softc *ahc);
static ahc_device_setup_t ahc_aic7770_VL_setup;
static ahc_device_setup_t ahc_aic7770_EISA_setup;
static ahc_device_setup_t ahc_aic7770_setup;
struct aic7770_identity aic7770_ident_table[] =
{
{
ID_AHA_274x,
0xFFFFFFFF,
"Adaptec 274X SCSI adapter",
ahc_aic7770_EISA_setup
},
{
ID_AHA_284xB,
0xFFFFFFFE,
"Adaptec 284X SCSI adapter",
ahc_aic7770_VL_setup
},
{
ID_AHA_284x,
0xFFFFFFFE,
"Adaptec 284X SCSI adapter (BIOS Disabled)",
ahc_aic7770_VL_setup
},
{
ID_OLV_274x,
0xFFFFFFFF,
"Adaptec (Olivetti OEM) 274X SCSI adapter",
ahc_aic7770_EISA_setup
},
{
ID_OLV_274xD,
0xFFFFFFFF,
"Adaptec (Olivetti OEM) 274X Differential SCSI adapter",
ahc_aic7770_EISA_setup
},
/* Generic chip probes for devices we don't know 'exactly' */
{
ID_AIC7770,
0xFFFFFFFF,
"Adaptec aic7770 SCSI adapter",
ahc_aic7770_EISA_setup
}
};
const int ahc_num_aic7770_devs = ARRAY_SIZE(aic7770_ident_table);
struct aic7770_identity *
aic7770_find_device(uint32_t id)
{
struct aic7770_identity *entry;
int i;
for (i = 0; i < ahc_num_aic7770_devs; i++) {
entry = &aic7770_ident_table[i];
if (entry->full_id == (id & entry->id_mask))
return (entry);
}
return (NULL);
}
int
aic7770_config(struct ahc_softc *ahc, struct aic7770_identity *entry, u_int io)
{
int error;
int have_seeprom;
u_int hostconf;
u_int irq;
u_int intdef;
error = entry->setup(ahc);
have_seeprom = 0;
if (error != 0)
return (error);
error = aic7770_map_registers(ahc, io);
if (error != 0)
return (error);
/*
* Before we continue probing the card, ensure that
* its interrupts are *disabled*. We don't want
* a misstep to hang the machine in an interrupt
* storm.
*/
ahc_intr_enable(ahc, FALSE);
ahc->description = entry->name;
error = ahc_softc_init(ahc);
if (error != 0)
return (error);
ahc->bus_chip_init = aic7770_chip_init;
error = ahc_reset(ahc, /*reinit*/FALSE);
if (error != 0)
return (error);
/* Make sure we have a valid interrupt vector */
intdef = ahc_inb(ahc, INTDEF);
irq = intdef & VECTOR;
switch (irq) {
case 9:
case 10:
case 11:
case 12:
case 14:
case 15:
break;
default:
printk("aic7770_config: invalid irq setting %d\n", intdef);
return (ENXIO);
}
if ((intdef & EDGE_TRIG) != 0)
ahc->flags |= AHC_EDGE_INTERRUPT;
switch (ahc->chip & (AHC_EISA|AHC_VL)) {
case AHC_EISA:
{
u_int biosctrl;
u_int scsiconf;
u_int scsiconf1;
biosctrl = ahc_inb(ahc, HA_274_BIOSCTRL);
scsiconf = ahc_inb(ahc, SCSICONF);
scsiconf1 = ahc_inb(ahc, SCSICONF + 1);
/* Get the primary channel information */
if ((biosctrl & CHANNEL_B_PRIMARY) != 0)
ahc->flags |= 1;
if ((biosctrl & BIOSMODE) == BIOSDISABLED) {
ahc->flags |= AHC_USEDEFAULTS;
} else {
if ((ahc->features & AHC_WIDE) != 0) {
ahc->our_id = scsiconf1 & HWSCSIID;
if (scsiconf & TERM_ENB)
ahc->flags |= AHC_TERM_ENB_A;
} else {
ahc->our_id = scsiconf & HSCSIID;
ahc->our_id_b = scsiconf1 & HSCSIID;
if (scsiconf & TERM_ENB)
ahc->flags |= AHC_TERM_ENB_A;
if (scsiconf1 & TERM_ENB)
ahc->flags |= AHC_TERM_ENB_B;
}
}
if ((ahc_inb(ahc, HA_274_BIOSGLOBAL) & HA_274_EXTENDED_TRANS))
ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B;
break;
}
case AHC_VL:
{
have_seeprom = aha2840_load_seeprom(ahc);
break;
}
default:
break;
}
if (have_seeprom == 0) {
kfree(ahc->seep_config);
ahc->seep_config = NULL;
}
/*
* Ensure autoflush is enabled
*/
ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~AUTOFLUSHDIS);
/* Setup the FIFO threshold and the bus off time */
hostconf = ahc_inb(ahc, HOSTCONF);
ahc_outb(ahc, BUSSPD, hostconf & DFTHRSH);
ahc_outb(ahc, BUSTIME, (hostconf << 2) & BOFF);
ahc->bus_softc.aic7770_softc.busspd = hostconf & DFTHRSH;
ahc->bus_softc.aic7770_softc.bustime = (hostconf << 2) & BOFF;
/*
* Generic aic7xxx initialization.
*/
error = ahc_init(ahc);
if (error != 0)
return (error);
error = aic7770_map_int(ahc, irq);
if (error != 0)
return (error);
ahc->init_level++;
/*
* Enable the board's BUS drivers
*/
ahc_outb(ahc, BCTL, ENABLE);
return (0);
}
static int
aic7770_chip_init(struct ahc_softc *ahc)
{
ahc_outb(ahc, BUSSPD, ahc->bus_softc.aic7770_softc.busspd);
ahc_outb(ahc, BUSTIME, ahc->bus_softc.aic7770_softc.bustime);
ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~AUTOFLUSHDIS);
ahc_outb(ahc, BCTL, ENABLE);
return (ahc_chip_init(ahc));
}
/*
* Read the 284x SEEPROM.
*/
static int
aha2840_load_seeprom(struct ahc_softc *ahc)
{
struct seeprom_descriptor sd;
struct seeprom_config *sc;
int have_seeprom;
uint8_t scsi_conf;
sd.sd_ahc = ahc;
sd.sd_control_offset = SEECTL_2840;
sd.sd_status_offset = STATUS_2840;
sd.sd_dataout_offset = STATUS_2840;
sd.sd_chip = C46;
sd.sd_MS = 0;
sd.sd_RDY = EEPROM_TF;
sd.sd_CS = CS_2840;
sd.sd_CK = CK_2840;
sd.sd_DO = DO_2840;
sd.sd_DI = DI_2840;
sc = ahc->seep_config;
if (bootverbose)
printk("%s: Reading SEEPROM...", ahc_name(ahc));
have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
/*start_addr*/0, sizeof(*sc)/2);
if (have_seeprom) {
if (ahc_verify_cksum(sc) == 0) {
if(bootverbose)
printk ("checksum error\n");
have_seeprom = 0;
} else if (bootverbose) {
printk("done.\n");
}
}
if (!have_seeprom) {
if (bootverbose)
printk("%s: No SEEPROM available\n", ahc_name(ahc));
ahc->flags |= AHC_USEDEFAULTS;
} else {
/*
* Put the data we've collected down into SRAM
* where ahc_init will find it.
*/
int i;
int max_targ;
uint16_t discenable;
max_targ = (ahc->features & AHC_WIDE) != 0 ? 16 : 8;
discenable = 0;
for (i = 0; i < max_targ; i++){
uint8_t target_settings;
target_settings = (sc->device_flags[i] & CFXFER) << 4;
if (sc->device_flags[i] & CFSYNCH)
target_settings |= SOFS;
if (sc->device_flags[i] & CFWIDEB)
target_settings |= WIDEXFER;
if (sc->device_flags[i] & CFDISC)
discenable |= (0x01 << i);
ahc_outb(ahc, TARG_SCSIRATE + i, target_settings);
}
ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
ahc->our_id = sc->brtime_id & CFSCSIID;
scsi_conf = (ahc->our_id & 0x7);
if (sc->adapter_control & CFSPARITY)
scsi_conf |= ENSPCHK;
if (sc->adapter_control & CFRESETB)
scsi_conf |= RESET_SCSI;
if (sc->bios_control & CF284XEXTEND)
ahc->flags |= AHC_EXTENDED_TRANS_A;
/* Set SCSICONF info */
ahc_outb(ahc, SCSICONF, scsi_conf);
if (sc->adapter_control & CF284XSTERM)
ahc->flags |= AHC_TERM_ENB_A;
}
return (have_seeprom);
}
static int
ahc_aic7770_VL_setup(struct ahc_softc *ahc)
{
int error;
error = ahc_aic7770_setup(ahc);
ahc->chip |= AHC_VL;
return (error);
}
static int
ahc_aic7770_EISA_setup(struct ahc_softc *ahc)
{
int error;
error = ahc_aic7770_setup(ahc);
ahc->chip |= AHC_EISA;
return (error);
}
static int
ahc_aic7770_setup(struct ahc_softc *ahc)
{
ahc->channel = 'A';
ahc->channel_b = 'B';
ahc->chip = AHC_AIC7770;
ahc->features = AHC_AIC7770_FE;
ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
ahc->flags |= AHC_PAGESCBS;
ahc->instruction_ram_size = 448;
return (0);
}

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/*
* Linux driver attachment glue for aic7770 based controllers.
*
* Copyright (c) 2000-2003 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic7770_osm.c#14 $
*/
#include "aic7xxx_osm.h"
#include <linux/device.h>
#include <linux/eisa.h>
int
aic7770_map_registers(struct ahc_softc *ahc, u_int port)
{
/*
* Lock out other contenders for our i/o space.
*/
if (!request_region(port, AHC_EISA_IOSIZE, "aic7xxx"))
return (ENOMEM);
ahc->tag = BUS_SPACE_PIO;
ahc->bsh.ioport = port;
return (0);
}
int
aic7770_map_int(struct ahc_softc *ahc, u_int irq)
{
int error;
int shared;
shared = 0;
if ((ahc->flags & AHC_EDGE_INTERRUPT) == 0)
shared = IRQF_SHARED;
error = request_irq(irq, ahc_linux_isr, shared, "aic7xxx", ahc);
if (error == 0)
ahc->platform_data->irq = irq;
return (-error);
}
static int
aic7770_probe(struct device *dev)
{
struct eisa_device *edev = to_eisa_device(dev);
u_int eisaBase = edev->base_addr+AHC_EISA_SLOT_OFFSET;
struct ahc_softc *ahc;
char buf[80];
char *name;
int error;
sprintf(buf, "ahc_eisa:%d", eisaBase >> 12);
name = kstrdup(buf, GFP_ATOMIC);
if (name == NULL)
return (ENOMEM);
ahc = ahc_alloc(&aic7xxx_driver_template, name);
if (ahc == NULL)
return (ENOMEM);
error = aic7770_config(ahc, aic7770_ident_table + edev->id.driver_data,
eisaBase);
if (error != 0) {
ahc->bsh.ioport = 0;
ahc_free(ahc);
return (error);
}
dev_set_drvdata(dev, ahc);
error = ahc_linux_register_host(ahc, &aic7xxx_driver_template);
return (error);
}
static int
aic7770_remove(struct device *dev)
{
struct ahc_softc *ahc = dev_get_drvdata(dev);
u_long s;
if (ahc->platform_data && ahc->platform_data->host)
scsi_remove_host(ahc->platform_data->host);
ahc_lock(ahc, &s);
ahc_intr_enable(ahc, FALSE);
ahc_unlock(ahc, &s);
ahc_free(ahc);
return 0;
}
static struct eisa_device_id aic7770_ids[] = {
{ "ADP7771", 0 }, /* AHA 274x */
{ "ADP7756", 1 }, /* AHA 284x BIOS enabled */
{ "ADP7757", 2 }, /* AHA 284x BIOS disabled */
{ "ADP7782", 3 }, /* AHA 274x Olivetti OEM */
{ "ADP7783", 4 }, /* AHA 274x Olivetti OEM (Differential) */
{ "ADP7770", 5 }, /* AIC7770 generic */
{ "" }
};
MODULE_DEVICE_TABLE(eisa, aic7770_ids);
static struct eisa_driver aic7770_driver = {
.id_table = aic7770_ids,
.driver = {
.name = "aic7xxx",
.probe = aic7770_probe,
.remove = aic7770_remove,
}
};
int
ahc_linux_eisa_init(void)
{
return eisa_driver_register(&aic7770_driver);
}
void
ahc_linux_eisa_exit(void)
{
eisa_driver_unregister(&aic7770_driver);
}

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/*
* Inline routines shareable across OS platforms.
*
* Copyright (c) 1994-2001 Justin T. Gibbs.
* Copyright (c) 2000-2003 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aic79xx_inline.h#59 $
*
* $FreeBSD$
*/
#ifndef _AIC79XX_INLINE_H_
#define _AIC79XX_INLINE_H_
/******************************** Debugging ***********************************/
static inline char *ahd_name(struct ahd_softc *ahd);
static inline char *ahd_name(struct ahd_softc *ahd)
{
return (ahd->name);
}
/************************ Sequencer Execution Control *************************/
static inline void ahd_known_modes(struct ahd_softc *ahd,
ahd_mode src, ahd_mode dst);
static inline ahd_mode_state ahd_build_mode_state(struct ahd_softc *ahd,
ahd_mode src,
ahd_mode dst);
static inline void ahd_extract_mode_state(struct ahd_softc *ahd,
ahd_mode_state state,
ahd_mode *src, ahd_mode *dst);
void ahd_set_modes(struct ahd_softc *ahd, ahd_mode src,
ahd_mode dst);
ahd_mode_state ahd_save_modes(struct ahd_softc *ahd);
void ahd_restore_modes(struct ahd_softc *ahd,
ahd_mode_state state);
int ahd_is_paused(struct ahd_softc *ahd);
void ahd_pause(struct ahd_softc *ahd);
void ahd_unpause(struct ahd_softc *ahd);
static inline void
ahd_known_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst)
{
ahd->src_mode = src;
ahd->dst_mode = dst;
ahd->saved_src_mode = src;
ahd->saved_dst_mode = dst;
}
static inline ahd_mode_state
ahd_build_mode_state(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst)
{
return ((src << SRC_MODE_SHIFT) | (dst << DST_MODE_SHIFT));
}
static inline void
ahd_extract_mode_state(struct ahd_softc *ahd, ahd_mode_state state,
ahd_mode *src, ahd_mode *dst)
{
*src = (state & SRC_MODE) >> SRC_MODE_SHIFT;
*dst = (state & DST_MODE) >> DST_MODE_SHIFT;
}
/*********************** Scatter Gather List Handling *************************/
void *ahd_sg_setup(struct ahd_softc *ahd, struct scb *scb,
void *sgptr, dma_addr_t addr,
bus_size_t len, int last);
/************************** Memory mapping routines ***************************/
static inline size_t ahd_sg_size(struct ahd_softc *ahd);
void ahd_sync_sglist(struct ahd_softc *ahd,
struct scb *scb, int op);
static inline size_t ahd_sg_size(struct ahd_softc *ahd)
{
if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
return (sizeof(struct ahd_dma64_seg));
return (sizeof(struct ahd_dma_seg));
}
/*********************** Miscellaneous Support Functions ***********************/
struct ahd_initiator_tinfo *
ahd_fetch_transinfo(struct ahd_softc *ahd,
char channel, u_int our_id,
u_int remote_id,
struct ahd_tmode_tstate **tstate);
uint16_t
ahd_inw(struct ahd_softc *ahd, u_int port);
void ahd_outw(struct ahd_softc *ahd, u_int port,
u_int value);
uint32_t
ahd_inl(struct ahd_softc *ahd, u_int port);
void ahd_outl(struct ahd_softc *ahd, u_int port,
uint32_t value);
uint64_t
ahd_inq(struct ahd_softc *ahd, u_int port);
void ahd_outq(struct ahd_softc *ahd, u_int port,
uint64_t value);
u_int ahd_get_scbptr(struct ahd_softc *ahd);
void ahd_set_scbptr(struct ahd_softc *ahd, u_int scbptr);
u_int ahd_inb_scbram(struct ahd_softc *ahd, u_int offset);
u_int ahd_inw_scbram(struct ahd_softc *ahd, u_int offset);
struct scb *
ahd_lookup_scb(struct ahd_softc *ahd, u_int tag);
void ahd_queue_scb(struct ahd_softc *ahd, struct scb *scb);
static inline uint8_t *ahd_get_sense_buf(struct ahd_softc *ahd,
struct scb *scb);
static inline uint32_t ahd_get_sense_bufaddr(struct ahd_softc *ahd,
struct scb *scb);
#if 0 /* unused */
#define AHD_COPY_COL_IDX(dst, src) \
do { \
dst->hscb->scsiid = src->hscb->scsiid; \
dst->hscb->lun = src->hscb->lun; \
} while (0)
#endif
static inline uint8_t *
ahd_get_sense_buf(struct ahd_softc *ahd, struct scb *scb)
{
return (scb->sense_data);
}
static inline uint32_t
ahd_get_sense_bufaddr(struct ahd_softc *ahd, struct scb *scb)
{
return (scb->sense_busaddr);
}
/************************** Interrupt Processing ******************************/
int ahd_intr(struct ahd_softc *ahd);
#endif /* _AIC79XX_INLINE_H_ */

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/*
* Adaptec AIC79xx device driver for Linux.
*
* Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic79xx_osm.h#166 $
*
*/
#ifndef _AIC79XX_LINUX_H_
#define _AIC79XX_LINUX_H_
#include <linux/types.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <scsi/scsi.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_eh.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_tcq.h>
#include <scsi/scsi_transport.h>
#include <scsi/scsi_transport_spi.h>
/* Core SCSI definitions */
#define AIC_LIB_PREFIX ahd
/* Name space conflict with BSD queue macros */
#ifdef LIST_HEAD
#undef LIST_HEAD
#endif
#include "cam.h"
#include "queue.h"
#include "scsi_message.h"
#include "scsi_iu.h"
#include "aiclib.h"
/*********************************** Debugging ********************************/
#ifdef CONFIG_AIC79XX_DEBUG_ENABLE
#ifdef CONFIG_AIC79XX_DEBUG_MASK
#define AHD_DEBUG 1
#define AHD_DEBUG_OPTS CONFIG_AIC79XX_DEBUG_MASK
#else
/*
* Compile in debugging code, but do not enable any printfs.
*/
#define AHD_DEBUG 1
#define AHD_DEBUG_OPTS 0
#endif
/* No debugging code. */
#endif
/********************************** Misc Macros *******************************/
#define powerof2(x) ((((x)-1)&(x))==0)
/************************* Forward Declarations *******************************/
struct ahd_softc;
typedef struct pci_dev *ahd_dev_softc_t;
typedef struct scsi_cmnd *ahd_io_ctx_t;
/******************************* Byte Order ***********************************/
#define ahd_htobe16(x) cpu_to_be16(x)
#define ahd_htobe32(x) cpu_to_be32(x)
#define ahd_htobe64(x) cpu_to_be64(x)
#define ahd_htole16(x) cpu_to_le16(x)
#define ahd_htole32(x) cpu_to_le32(x)
#define ahd_htole64(x) cpu_to_le64(x)
#define ahd_be16toh(x) be16_to_cpu(x)
#define ahd_be32toh(x) be32_to_cpu(x)
#define ahd_be64toh(x) be64_to_cpu(x)
#define ahd_le16toh(x) le16_to_cpu(x)
#define ahd_le32toh(x) le32_to_cpu(x)
#define ahd_le64toh(x) le64_to_cpu(x)
/************************* Configuration Data *********************************/
extern uint32_t aic79xx_allow_memio;
extern struct scsi_host_template aic79xx_driver_template;
/***************************** Bus Space/DMA **********************************/
typedef uint32_t bus_size_t;
typedef enum {
BUS_SPACE_MEMIO,
BUS_SPACE_PIO
} bus_space_tag_t;
typedef union {
u_long ioport;
volatile uint8_t __iomem *maddr;
} bus_space_handle_t;
typedef struct bus_dma_segment
{
dma_addr_t ds_addr;
bus_size_t ds_len;
} bus_dma_segment_t;
struct ahd_linux_dma_tag
{
bus_size_t alignment;
bus_size_t boundary;
bus_size_t maxsize;
};
typedef struct ahd_linux_dma_tag* bus_dma_tag_t;
typedef dma_addr_t bus_dmamap_t;
typedef int bus_dma_filter_t(void*, dma_addr_t);
typedef void bus_dmamap_callback_t(void *, bus_dma_segment_t *, int, int);
#define BUS_DMA_WAITOK 0x0
#define BUS_DMA_NOWAIT 0x1
#define BUS_DMA_ALLOCNOW 0x2
#define BUS_DMA_LOAD_SEGS 0x4 /*
* Argument is an S/G list not
* a single buffer.
*/
#define BUS_SPACE_MAXADDR 0xFFFFFFFF
#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF
#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF
int ahd_dma_tag_create(struct ahd_softc *, bus_dma_tag_t /*parent*/,
bus_size_t /*alignment*/, bus_size_t /*boundary*/,
dma_addr_t /*lowaddr*/, dma_addr_t /*highaddr*/,
bus_dma_filter_t*/*filter*/, void */*filterarg*/,
bus_size_t /*maxsize*/, int /*nsegments*/,
bus_size_t /*maxsegsz*/, int /*flags*/,
bus_dma_tag_t */*dma_tagp*/);
void ahd_dma_tag_destroy(struct ahd_softc *, bus_dma_tag_t /*tag*/);
int ahd_dmamem_alloc(struct ahd_softc *, bus_dma_tag_t /*dmat*/,
void** /*vaddr*/, int /*flags*/,
bus_dmamap_t* /*mapp*/);
void ahd_dmamem_free(struct ahd_softc *, bus_dma_tag_t /*dmat*/,
void* /*vaddr*/, bus_dmamap_t /*map*/);
void ahd_dmamap_destroy(struct ahd_softc *, bus_dma_tag_t /*tag*/,
bus_dmamap_t /*map*/);
int ahd_dmamap_load(struct ahd_softc *ahd, bus_dma_tag_t /*dmat*/,
bus_dmamap_t /*map*/, void * /*buf*/,
bus_size_t /*buflen*/, bus_dmamap_callback_t *,
void */*callback_arg*/, int /*flags*/);
int ahd_dmamap_unload(struct ahd_softc *, bus_dma_tag_t, bus_dmamap_t);
/*
* Operations performed by ahd_dmamap_sync().
*/
#define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
#define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
#define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
#define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
/*
* XXX
* ahd_dmamap_sync is only used on buffers allocated with
* the pci_alloc_consistent() API. Although I'm not sure how
* this works on architectures with a write buffer, Linux does
* not have an API to sync "coherent" memory. Perhaps we need
* to do an mb()?
*/
#define ahd_dmamap_sync(ahd, dma_tag, dmamap, offset, len, op)
/************************** Timer DataStructures ******************************/
typedef struct timer_list ahd_timer_t;
/********************************** Includes **********************************/
#ifdef CONFIG_AIC79XX_REG_PRETTY_PRINT
#define AIC_DEBUG_REGISTERS 1
#else
#define AIC_DEBUG_REGISTERS 0
#endif
#include "aic79xx.h"
/***************************** Timer Facilities *******************************/
#define ahd_timer_init init_timer
#define ahd_timer_stop del_timer_sync
/***************************** SMP support ************************************/
#include <linux/spinlock.h>
#define AIC79XX_DRIVER_VERSION "3.0"
/*************************** Device Data Structures ***************************/
/*
* A per probed device structure used to deal with some error recovery
* scenarios that the Linux mid-layer code just doesn't know how to
* handle. The structure allocated for a device only becomes persistent
* after a successfully completed inquiry command to the target when
* that inquiry data indicates a lun is present.
*/
typedef enum {
AHD_DEV_FREEZE_TIL_EMPTY = 0x02, /* Freeze queue until active == 0 */
AHD_DEV_Q_BASIC = 0x10, /* Allow basic device queuing */
AHD_DEV_Q_TAGGED = 0x20, /* Allow full SCSI2 command queueing */
AHD_DEV_PERIODIC_OTAG = 0x40, /* Send OTAG to prevent starvation */
} ahd_linux_dev_flags;
struct ahd_linux_device {
TAILQ_ENTRY(ahd_linux_device) links;
/*
* The number of transactions currently
* queued to the device.
*/
int active;
/*
* The currently allowed number of
* transactions that can be queued to
* the device. Must be signed for
* conversion from tagged to untagged
* mode where the device may have more
* than one outstanding active transaction.
*/
int openings;
/*
* A positive count indicates that this
* device's queue is halted.
*/
u_int qfrozen;
/*
* Cumulative command counter.
*/
u_long commands_issued;
/*
* The number of tagged transactions when
* running at our current opening level
* that have been successfully received by
* this device since the last QUEUE FULL.
*/
u_int tag_success_count;
#define AHD_TAG_SUCCESS_INTERVAL 50
ahd_linux_dev_flags flags;
/*
* Per device timer.
*/
struct timer_list timer;
/*
* The high limit for the tags variable.
*/
u_int maxtags;
/*
* The computed number of tags outstanding
* at the time of the last QUEUE FULL event.
*/
u_int tags_on_last_queuefull;
/*
* How many times we have seen a queue full
* with the same number of tags. This is used
* to stop our adaptive queue depth algorithm
* on devices with a fixed number of tags.
*/
u_int last_queuefull_same_count;
#define AHD_LOCK_TAGS_COUNT 50
/*
* How many transactions have been queued
* without the device going idle. We use
* this statistic to determine when to issue
* an ordered tag to prevent transaction
* starvation. This statistic is only updated
* if the AHD_DEV_PERIODIC_OTAG flag is set
* on this device.
*/
u_int commands_since_idle_or_otag;
#define AHD_OTAG_THRESH 500
};
/********************* Definitions Required by the Core ***********************/
/*
* Number of SG segments we require. So long as the S/G segments for
* a particular transaction are allocated in a physically contiguous
* manner and are allocated below 4GB, the number of S/G segments is
* unrestricted.
*/
#define AHD_NSEG 128
/*
* Per-SCB OSM storage.
*/
struct scb_platform_data {
struct ahd_linux_device *dev;
dma_addr_t buf_busaddr;
uint32_t xfer_len;
uint32_t sense_resid; /* Auto-Sense residual */
};
/*
* Define a structure used for each host adapter. All members are
* aligned on a boundary >= the size of the member to honor the
* alignment restrictions of the various platforms supported by
* this driver.
*/
struct ahd_platform_data {
/*
* Fields accessed from interrupt context.
*/
struct scsi_target *starget[AHD_NUM_TARGETS];
spinlock_t spin_lock;
struct completion *eh_done;
struct Scsi_Host *host; /* pointer to scsi host */
#define AHD_LINUX_NOIRQ ((uint32_t)~0)
uint32_t irq; /* IRQ for this adapter */
uint32_t bios_address;
resource_size_t mem_busaddr; /* Mem Base Addr */
};
void ahd_delay(long);
/***************************** Low Level I/O **********************************/
uint8_t ahd_inb(struct ahd_softc * ahd, long port);
void ahd_outb(struct ahd_softc * ahd, long port, uint8_t val);
void ahd_outw_atomic(struct ahd_softc * ahd,
long port, uint16_t val);
void ahd_outsb(struct ahd_softc * ahd, long port,
uint8_t *, int count);
void ahd_insb(struct ahd_softc * ahd, long port,
uint8_t *, int count);
/**************************** Initialization **********************************/
int ahd_linux_register_host(struct ahd_softc *,
struct scsi_host_template *);
/******************************** Locking *************************************/
static inline void
ahd_lockinit(struct ahd_softc *ahd)
{
spin_lock_init(&ahd->platform_data->spin_lock);
}
static inline void
ahd_lock(struct ahd_softc *ahd, unsigned long *flags)
{
spin_lock_irqsave(&ahd->platform_data->spin_lock, *flags);
}
static inline void
ahd_unlock(struct ahd_softc *ahd, unsigned long *flags)
{
spin_unlock_irqrestore(&ahd->platform_data->spin_lock, *flags);
}
/******************************* PCI Definitions ******************************/
/*
* PCIM_xxx: mask to locate subfield in register
* PCIR_xxx: config register offset
* PCIC_xxx: device class
* PCIS_xxx: device subclass
* PCIP_xxx: device programming interface
* PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
* PCID_xxx: device ID
*/
#define PCIR_DEVVENDOR 0x00
#define PCIR_VENDOR 0x00
#define PCIR_DEVICE 0x02
#define PCIR_COMMAND 0x04
#define PCIM_CMD_PORTEN 0x0001
#define PCIM_CMD_MEMEN 0x0002
#define PCIM_CMD_BUSMASTEREN 0x0004
#define PCIM_CMD_MWRICEN 0x0010
#define PCIM_CMD_PERRESPEN 0x0040
#define PCIM_CMD_SERRESPEN 0x0100
#define PCIR_STATUS 0x06
#define PCIR_REVID 0x08
#define PCIR_PROGIF 0x09
#define PCIR_SUBCLASS 0x0a
#define PCIR_CLASS 0x0b
#define PCIR_CACHELNSZ 0x0c
#define PCIR_LATTIMER 0x0d
#define PCIR_HEADERTYPE 0x0e
#define PCIM_MFDEV 0x80
#define PCIR_BIST 0x0f
#define PCIR_CAP_PTR 0x34
/* config registers for header type 0 devices */
#define PCIR_MAPS 0x10
#define PCIR_SUBVEND_0 0x2c
#define PCIR_SUBDEV_0 0x2e
/****************************** PCI-X definitions *****************************/
#define PCIXR_COMMAND 0x96
#define PCIXR_DEVADDR 0x98
#define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */
#define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */
#define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */
#define PCIXR_STATUS 0x9A
#define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */
#define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */
#define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */
#define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */
#define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */
#define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */
#define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */
#define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */
#define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */
typedef enum
{
AHD_POWER_STATE_D0,
AHD_POWER_STATE_D1,
AHD_POWER_STATE_D2,
AHD_POWER_STATE_D3
} ahd_power_state;
void ahd_power_state_change(struct ahd_softc *ahd,
ahd_power_state new_state);
/******************************* PCI Routines *********************************/
int ahd_linux_pci_init(void);
void ahd_linux_pci_exit(void);
int ahd_pci_map_registers(struct ahd_softc *ahd);
int ahd_pci_map_int(struct ahd_softc *ahd);
uint32_t ahd_pci_read_config(ahd_dev_softc_t pci,
int reg, int width);
void ahd_pci_write_config(ahd_dev_softc_t pci,
int reg, uint32_t value,
int width);
static inline int ahd_get_pci_function(ahd_dev_softc_t);
static inline int
ahd_get_pci_function(ahd_dev_softc_t pci)
{
return (PCI_FUNC(pci->devfn));
}
static inline int ahd_get_pci_slot(ahd_dev_softc_t);
static inline int
ahd_get_pci_slot(ahd_dev_softc_t pci)
{
return (PCI_SLOT(pci->devfn));
}
static inline int ahd_get_pci_bus(ahd_dev_softc_t);
static inline int
ahd_get_pci_bus(ahd_dev_softc_t pci)
{
return (pci->bus->number);
}
static inline void ahd_flush_device_writes(struct ahd_softc *);
static inline void
ahd_flush_device_writes(struct ahd_softc *ahd)
{
/* XXX Is this sufficient for all architectures??? */
ahd_inb(ahd, INTSTAT);
}
/**************************** Proc FS Support *********************************/
int ahd_proc_write_seeprom(struct Scsi_Host *, char *, int);
int ahd_linux_show_info(struct seq_file *,struct Scsi_Host *);
/*********************** Transaction Access Wrappers **************************/
static inline void ahd_cmd_set_transaction_status(struct scsi_cmnd *, uint32_t);
static inline void ahd_set_transaction_status(struct scb *, uint32_t);
static inline void ahd_cmd_set_scsi_status(struct scsi_cmnd *, uint32_t);
static inline void ahd_set_scsi_status(struct scb *, uint32_t);
static inline uint32_t ahd_cmd_get_transaction_status(struct scsi_cmnd *cmd);
static inline uint32_t ahd_get_transaction_status(struct scb *);
static inline uint32_t ahd_cmd_get_scsi_status(struct scsi_cmnd *cmd);
static inline uint32_t ahd_get_scsi_status(struct scb *);
static inline void ahd_set_transaction_tag(struct scb *, int, u_int);
static inline u_long ahd_get_transfer_length(struct scb *);
static inline int ahd_get_transfer_dir(struct scb *);
static inline void ahd_set_residual(struct scb *, u_long);
static inline void ahd_set_sense_residual(struct scb *scb, u_long resid);
static inline u_long ahd_get_residual(struct scb *);
static inline u_long ahd_get_sense_residual(struct scb *);
static inline int ahd_perform_autosense(struct scb *);
static inline uint32_t ahd_get_sense_bufsize(struct ahd_softc *,
struct scb *);
static inline void ahd_notify_xfer_settings_change(struct ahd_softc *,
struct ahd_devinfo *);
static inline void ahd_platform_scb_free(struct ahd_softc *ahd,
struct scb *scb);
static inline void ahd_freeze_scb(struct scb *scb);
static inline
void ahd_cmd_set_transaction_status(struct scsi_cmnd *cmd, uint32_t status)
{
cmd->result &= ~(CAM_STATUS_MASK << 16);
cmd->result |= status << 16;
}
static inline
void ahd_set_transaction_status(struct scb *scb, uint32_t status)
{
ahd_cmd_set_transaction_status(scb->io_ctx,status);
}
static inline
void ahd_cmd_set_scsi_status(struct scsi_cmnd *cmd, uint32_t status)
{
cmd->result &= ~0xFFFF;
cmd->result |= status;
}
static inline
void ahd_set_scsi_status(struct scb *scb, uint32_t status)
{
ahd_cmd_set_scsi_status(scb->io_ctx, status);
}
static inline
uint32_t ahd_cmd_get_transaction_status(struct scsi_cmnd *cmd)
{
return ((cmd->result >> 16) & CAM_STATUS_MASK);
}
static inline
uint32_t ahd_get_transaction_status(struct scb *scb)
{
return (ahd_cmd_get_transaction_status(scb->io_ctx));
}
static inline
uint32_t ahd_cmd_get_scsi_status(struct scsi_cmnd *cmd)
{
return (cmd->result & 0xFFFF);
}
static inline
uint32_t ahd_get_scsi_status(struct scb *scb)
{
return (ahd_cmd_get_scsi_status(scb->io_ctx));
}
static inline
void ahd_set_transaction_tag(struct scb *scb, int enabled, u_int type)
{
/*
* Nothing to do for linux as the incoming transaction
* has no concept of tag/non tagged, etc.
*/
}
static inline
u_long ahd_get_transfer_length(struct scb *scb)
{
return (scb->platform_data->xfer_len);
}
static inline
int ahd_get_transfer_dir(struct scb *scb)
{
return (scb->io_ctx->sc_data_direction);
}
static inline
void ahd_set_residual(struct scb *scb, u_long resid)
{
scsi_set_resid(scb->io_ctx, resid);
}
static inline
void ahd_set_sense_residual(struct scb *scb, u_long resid)
{
scb->platform_data->sense_resid = resid;
}
static inline
u_long ahd_get_residual(struct scb *scb)
{
return scsi_get_resid(scb->io_ctx);
}
static inline
u_long ahd_get_sense_residual(struct scb *scb)
{
return (scb->platform_data->sense_resid);
}
static inline
int ahd_perform_autosense(struct scb *scb)
{
/*
* We always perform autosense in Linux.
* On other platforms this is set on a
* per-transaction basis.
*/
return (1);
}
static inline uint32_t
ahd_get_sense_bufsize(struct ahd_softc *ahd, struct scb *scb)
{
return (sizeof(struct scsi_sense_data));
}
static inline void
ahd_notify_xfer_settings_change(struct ahd_softc *ahd,
struct ahd_devinfo *devinfo)
{
/* Nothing to do here for linux */
}
static inline void
ahd_platform_scb_free(struct ahd_softc *ahd, struct scb *scb)
{
ahd->flags &= ~AHD_RESOURCE_SHORTAGE;
}
int ahd_platform_alloc(struct ahd_softc *ahd, void *platform_arg);
void ahd_platform_free(struct ahd_softc *ahd);
void ahd_platform_init(struct ahd_softc *ahd);
void ahd_platform_freeze_devq(struct ahd_softc *ahd, struct scb *scb);
static inline void
ahd_freeze_scb(struct scb *scb)
{
if ((scb->io_ctx->result & (CAM_DEV_QFRZN << 16)) == 0) {
scb->io_ctx->result |= CAM_DEV_QFRZN << 16;
scb->platform_data->dev->qfrozen++;
}
}
void ahd_platform_set_tags(struct ahd_softc *ahd, struct scsi_device *sdev,
struct ahd_devinfo *devinfo, ahd_queue_alg);
int ahd_platform_abort_scbs(struct ahd_softc *ahd, int target,
char channel, int lun, u_int tag,
role_t role, uint32_t status);
irqreturn_t
ahd_linux_isr(int irq, void *dev_id);
void ahd_done(struct ahd_softc*, struct scb*);
void ahd_send_async(struct ahd_softc *, char channel,
u_int target, u_int lun, ac_code);
void ahd_print_path(struct ahd_softc *, struct scb *);
#ifdef CONFIG_PCI
#define AHD_PCI_CONFIG 1
#else
#define AHD_PCI_CONFIG 0
#endif
#define bootverbose aic79xx_verbose
extern uint32_t aic79xx_verbose;
#endif /* _AIC79XX_LINUX_H_ */

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/*
* Linux driver attachment glue for PCI based U320 controllers.
*
* Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic79xx_osm_pci.c#25 $
*/
#include "aic79xx_osm.h"
#include "aic79xx_inline.h"
#include "aic79xx_pci.h"
/* Define the macro locally since it's different for different class of chips.
*/
#define ID(x) \
ID2C(x), \
ID2C(IDIROC(x))
static const struct pci_device_id ahd_linux_pci_id_table[] = {
/* aic7901 based controllers */
ID(ID_AHA_29320A),
ID(ID_AHA_29320ALP),
ID(ID_AHA_29320LPE),
/* aic7902 based controllers */
ID(ID_AHA_29320),
ID(ID_AHA_29320B),
ID(ID_AHA_29320LP),
ID(ID_AHA_39320),
ID(ID_AHA_39320_B),
ID(ID_AHA_39320A),
ID(ID_AHA_39320D),
ID(ID_AHA_39320D_HP),
ID(ID_AHA_39320D_B),
ID(ID_AHA_39320D_B_HP),
/* Generic chip probes for devices we don't know exactly. */
ID16(ID_AIC7901 & ID_9005_GENERIC_MASK),
ID(ID_AIC7901A & ID_DEV_VENDOR_MASK),
ID16(ID_AIC7902 & ID_9005_GENERIC_MASK),
{ 0 }
};
MODULE_DEVICE_TABLE(pci, ahd_linux_pci_id_table);
#ifdef CONFIG_PM
static int
ahd_linux_pci_dev_suspend(struct pci_dev *pdev, pm_message_t mesg)
{
struct ahd_softc *ahd = pci_get_drvdata(pdev);
int rc;
if ((rc = ahd_suspend(ahd)))
return rc;
ahd_pci_suspend(ahd);
pci_save_state(pdev);
pci_disable_device(pdev);
if (mesg.event & PM_EVENT_SLEEP)
pci_set_power_state(pdev, PCI_D3hot);
return rc;
}
static int
ahd_linux_pci_dev_resume(struct pci_dev *pdev)
{
struct ahd_softc *ahd = pci_get_drvdata(pdev);
int rc;
pci_set_power_state(pdev, PCI_D0);
pci_restore_state(pdev);
if ((rc = pci_enable_device(pdev))) {
dev_printk(KERN_ERR, &pdev->dev,
"failed to enable device after resume (%d)\n", rc);
return rc;
}
pci_set_master(pdev);
ahd_pci_resume(ahd);
ahd_resume(ahd);
return rc;
}
#endif
static void
ahd_linux_pci_dev_remove(struct pci_dev *pdev)
{
struct ahd_softc *ahd = pci_get_drvdata(pdev);
u_long s;
if (ahd->platform_data && ahd->platform_data->host)
scsi_remove_host(ahd->platform_data->host);
ahd_lock(ahd, &s);
ahd_intr_enable(ahd, FALSE);
ahd_unlock(ahd, &s);
ahd_free(ahd);
}
static void
ahd_linux_pci_inherit_flags(struct ahd_softc *ahd)
{
struct pci_dev *pdev = ahd->dev_softc, *master_pdev;
unsigned int master_devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
master_pdev = pci_get_slot(pdev->bus, master_devfn);
if (master_pdev) {
struct ahd_softc *master = pci_get_drvdata(master_pdev);
if (master) {
ahd->flags &= ~AHD_BIOS_ENABLED;
ahd->flags |= master->flags & AHD_BIOS_ENABLED;
} else
printk(KERN_ERR "aic79xx: no multichannel peer found!\n");
pci_dev_put(master_pdev);
}
}
static int
ahd_linux_pci_dev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
char buf[80];
struct ahd_softc *ahd;
ahd_dev_softc_t pci;
const struct ahd_pci_identity *entry;
char *name;
int error;
struct device *dev = &pdev->dev;
pci = pdev;
entry = ahd_find_pci_device(pci);
if (entry == NULL)
return (-ENODEV);
/*
* Allocate a softc for this card and
* set it up for attachment by our
* common detect routine.
*/
sprintf(buf, "ahd_pci:%d:%d:%d",
ahd_get_pci_bus(pci),
ahd_get_pci_slot(pci),
ahd_get_pci_function(pci));
name = kstrdup(buf, GFP_ATOMIC);
if (name == NULL)
return (-ENOMEM);
ahd = ahd_alloc(NULL, name);
if (ahd == NULL)
return (-ENOMEM);
if (pci_enable_device(pdev)) {
ahd_free(ahd);
return (-ENODEV);
}
pci_set_master(pdev);
if (sizeof(dma_addr_t) > 4) {
const u64 required_mask = dma_get_required_mask(dev);
if (required_mask > DMA_BIT_MASK(39) &&
dma_set_mask(dev, DMA_BIT_MASK(64)) == 0)
ahd->flags |= AHD_64BIT_ADDRESSING;
else if (required_mask > DMA_BIT_MASK(32) &&
dma_set_mask(dev, DMA_BIT_MASK(39)) == 0)
ahd->flags |= AHD_39BIT_ADDRESSING;
else
dma_set_mask(dev, DMA_BIT_MASK(32));
} else {
dma_set_mask(dev, DMA_BIT_MASK(32));
}
ahd->dev_softc = pci;
error = ahd_pci_config(ahd, entry);
if (error != 0) {
ahd_free(ahd);
return (-error);
}
/*
* Second Function PCI devices need to inherit some
* * settings from function 0.
*/
if ((ahd->features & AHD_MULTI_FUNC) && PCI_FUNC(pdev->devfn) != 0)
ahd_linux_pci_inherit_flags(ahd);
pci_set_drvdata(pdev, ahd);
ahd_linux_register_host(ahd, &aic79xx_driver_template);
return (0);
}
static struct pci_driver aic79xx_pci_driver = {
.name = "aic79xx",
.probe = ahd_linux_pci_dev_probe,
#ifdef CONFIG_PM
.suspend = ahd_linux_pci_dev_suspend,
.resume = ahd_linux_pci_dev_resume,
#endif
.remove = ahd_linux_pci_dev_remove,
.id_table = ahd_linux_pci_id_table
};
int
ahd_linux_pci_init(void)
{
return pci_register_driver(&aic79xx_pci_driver);
}
void
ahd_linux_pci_exit(void)
{
pci_unregister_driver(&aic79xx_pci_driver);
}
static int
ahd_linux_pci_reserve_io_regions(struct ahd_softc *ahd, resource_size_t *base,
resource_size_t *base2)
{
*base = pci_resource_start(ahd->dev_softc, 0);
/*
* This is really the 3rd bar and should be at index 2,
* but the Linux PCI code doesn't know how to "count" 64bit
* bars.
*/
*base2 = pci_resource_start(ahd->dev_softc, 3);
if (*base == 0 || *base2 == 0)
return (ENOMEM);
if (!request_region(*base, 256, "aic79xx"))
return (ENOMEM);
if (!request_region(*base2, 256, "aic79xx")) {
release_region(*base, 256);
return (ENOMEM);
}
return (0);
}
static int
ahd_linux_pci_reserve_mem_region(struct ahd_softc *ahd,
resource_size_t *bus_addr,
uint8_t __iomem **maddr)
{
resource_size_t start;
resource_size_t base_page;
u_long base_offset;
int error = 0;
if (aic79xx_allow_memio == 0)
return (ENOMEM);
if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) != 0)
return (ENOMEM);
start = pci_resource_start(ahd->dev_softc, 1);
base_page = start & PAGE_MASK;
base_offset = start - base_page;
if (start != 0) {
*bus_addr = start;
if (!request_mem_region(start, 0x1000, "aic79xx"))
error = ENOMEM;
if (!error) {
*maddr = ioremap_nocache(base_page, base_offset + 512);
if (*maddr == NULL) {
error = ENOMEM;
release_mem_region(start, 0x1000);
} else
*maddr += base_offset;
}
} else
error = ENOMEM;
return (error);
}
int
ahd_pci_map_registers(struct ahd_softc *ahd)
{
uint32_t command;
resource_size_t base;
uint8_t __iomem *maddr;
int error;
/*
* If its allowed, we prefer memory mapped access.
*/
command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, 4);
command &= ~(PCIM_CMD_PORTEN|PCIM_CMD_MEMEN);
base = 0;
maddr = NULL;
error = ahd_linux_pci_reserve_mem_region(ahd, &base, &maddr);
if (error == 0) {
ahd->platform_data->mem_busaddr = base;
ahd->tags[0] = BUS_SPACE_MEMIO;
ahd->bshs[0].maddr = maddr;
ahd->tags[1] = BUS_SPACE_MEMIO;
ahd->bshs[1].maddr = maddr + 0x100;
ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
command | PCIM_CMD_MEMEN, 4);
if (ahd_pci_test_register_access(ahd) != 0) {
printk("aic79xx: PCI Device %d:%d:%d "
"failed memory mapped test. Using PIO.\n",
ahd_get_pci_bus(ahd->dev_softc),
ahd_get_pci_slot(ahd->dev_softc),
ahd_get_pci_function(ahd->dev_softc));
iounmap(maddr);
release_mem_region(ahd->platform_data->mem_busaddr,
0x1000);
ahd->bshs[0].maddr = NULL;
maddr = NULL;
} else
command |= PCIM_CMD_MEMEN;
} else if (bootverbose) {
printk("aic79xx: PCI%d:%d:%d MEM region 0x%llx "
"unavailable. Cannot memory map device.\n",
ahd_get_pci_bus(ahd->dev_softc),
ahd_get_pci_slot(ahd->dev_softc),
ahd_get_pci_function(ahd->dev_softc),
(unsigned long long)base);
}
if (maddr == NULL) {
resource_size_t base2;
error = ahd_linux_pci_reserve_io_regions(ahd, &base, &base2);
if (error == 0) {
ahd->tags[0] = BUS_SPACE_PIO;
ahd->tags[1] = BUS_SPACE_PIO;
ahd->bshs[0].ioport = (u_long)base;
ahd->bshs[1].ioport = (u_long)base2;
command |= PCIM_CMD_PORTEN;
} else {
printk("aic79xx: PCI%d:%d:%d IO regions 0x%llx and "
"0x%llx unavailable. Cannot map device.\n",
ahd_get_pci_bus(ahd->dev_softc),
ahd_get_pci_slot(ahd->dev_softc),
ahd_get_pci_function(ahd->dev_softc),
(unsigned long long)base,
(unsigned long long)base2);
}
}
ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, 4);
return (error);
}
int
ahd_pci_map_int(struct ahd_softc *ahd)
{
int error;
error = request_irq(ahd->dev_softc->irq, ahd_linux_isr,
IRQF_SHARED, "aic79xx", ahd);
if (!error)
ahd->platform_data->irq = ahd->dev_softc->irq;
return (-error);
}
void
ahd_power_state_change(struct ahd_softc *ahd, ahd_power_state new_state)
{
pci_set_power_state(ahd->dev_softc, new_state);
}

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drivers/scsi/aic7xxx/aic79xx_pci.c Normal file
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/*
* Adaptec AIC79xx device driver for Linux.
*
* Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id$
*
*/
#ifndef _AIC79XX_PCI_H_
#define _AIC79XX_PCI_H_
#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
#define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull
#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
#define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
#define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull
#define ID_AIC7901 0x800F9005FFFF9005ull
#define ID_AHA_29320A 0x8000900500609005ull
#define ID_AHA_29320ALP 0x8017900500449005ull
#define ID_AHA_29320LPE 0x8017900500459005ull
#define ID_AIC7901A 0x801E9005FFFF9005ull
#define ID_AHA_29320LP 0x8014900500449005ull
#define ID_AIC7902 0x801F9005FFFF9005ull
#define ID_AIC7902_B 0x801D9005FFFF9005ull
#define ID_AHA_39320 0x8010900500409005ull
#define ID_AHA_29320 0x8012900500429005ull
#define ID_AHA_29320B 0x8013900500439005ull
#define ID_AHA_39320_B 0x8015900500409005ull
#define ID_AHA_39320_B_DELL 0x8015900501681028ull
#define ID_AHA_39320A 0x8016900500409005ull
#define ID_AHA_39320D 0x8011900500419005ull
#define ID_AHA_39320D_B 0x801C900500419005ull
#define ID_AHA_39320D_HP 0x8011900500AC0E11ull
#define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull
#endif /* _AIC79XX_PCI_H_ */

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/*
* Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* String handling code courtesy of Gerard Roudier's <groudier@club-internet.fr>
* sym driver.
*
* $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic79xx_proc.c#19 $
*/
#include "aic79xx_osm.h"
#include "aic79xx_inline.h"
static void ahd_dump_target_state(struct ahd_softc *ahd,
struct seq_file *m,
u_int our_id, char channel,
u_int target_id);
static void ahd_dump_device_state(struct seq_file *m,
struct scsi_device *sdev);
/*
* Table of syncrates that don't follow the "divisible by 4"
* rule. This table will be expanded in future SCSI specs.
*/
static const struct {
u_int period_factor;
u_int period; /* in 100ths of ns */
} scsi_syncrates[] = {
{ 0x08, 625 }, /* FAST-160 */
{ 0x09, 1250 }, /* FAST-80 */
{ 0x0a, 2500 }, /* FAST-40 40MHz */
{ 0x0b, 3030 }, /* FAST-40 33MHz */
{ 0x0c, 5000 } /* FAST-20 */
};
/*
* Return the frequency in kHz corresponding to the given
* sync period factor.
*/
static u_int
ahd_calc_syncsrate(u_int period_factor)
{
int i;
/* See if the period is in the "exception" table */
for (i = 0; i < ARRAY_SIZE(scsi_syncrates); i++) {
if (period_factor == scsi_syncrates[i].period_factor) {
/* Period in kHz */
return (100000000 / scsi_syncrates[i].period);
}
}
/*
* Wasn't in the table, so use the standard
* 4 times conversion.
*/
return (10000000 / (period_factor * 4 * 10));
}
static void
ahd_format_transinfo(struct seq_file *m, struct ahd_transinfo *tinfo)
{
u_int speed;
u_int freq;
u_int mb;
if (tinfo->period == AHD_PERIOD_UNKNOWN) {
seq_printf(m, "Renegotiation Pending\n");
return;
}
speed = 3300;
freq = 0;
if (tinfo->offset != 0) {
freq = ahd_calc_syncsrate(tinfo->period);
speed = freq;
}
speed *= (0x01 << tinfo->width);
mb = speed / 1000;
if (mb > 0)
seq_printf(m, "%d.%03dMB/s transfers", mb, speed % 1000);
else
seq_printf(m, "%dKB/s transfers", speed);
if (freq != 0) {
int printed_options;
printed_options = 0;
seq_printf(m, " (%d.%03dMHz", freq / 1000, freq % 1000);
if ((tinfo->ppr_options & MSG_EXT_PPR_RD_STRM) != 0) {
seq_printf(m, " RDSTRM");
printed_options++;
}
if ((tinfo->ppr_options & MSG_EXT_PPR_DT_REQ) != 0) {
seq_printf(m, "%s", printed_options ? "|DT" : " DT");
printed_options++;
}
if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) != 0) {
seq_printf(m, "%s", printed_options ? "|IU" : " IU");
printed_options++;
}
if ((tinfo->ppr_options & MSG_EXT_PPR_RTI) != 0) {
seq_printf(m, "%s",
printed_options ? "|RTI" : " RTI");
printed_options++;
}
if ((tinfo->ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) {
seq_printf(m, "%s",
printed_options ? "|QAS" : " QAS");
printed_options++;
}
}
if (tinfo->width > 0) {
if (freq != 0) {
seq_printf(m, ", ");
} else {
seq_printf(m, " (");
}
seq_printf(m, "%dbit)", 8 * (0x01 << tinfo->width));
} else if (freq != 0) {
seq_printf(m, ")");
}
seq_printf(m, "\n");
}
static void
ahd_dump_target_state(struct ahd_softc *ahd, struct seq_file *m,
u_int our_id, char channel, u_int target_id)
{
struct scsi_target *starget;
struct ahd_initiator_tinfo *tinfo;
struct ahd_tmode_tstate *tstate;
int lun;
tinfo = ahd_fetch_transinfo(ahd, channel, our_id,
target_id, &tstate);
seq_printf(m, "Target %d Negotiation Settings\n", target_id);
seq_printf(m, "\tUser: ");
ahd_format_transinfo(m, &tinfo->user);
starget = ahd->platform_data->starget[target_id];
if (starget == NULL)
return;
seq_printf(m, "\tGoal: ");
ahd_format_transinfo(m, &tinfo->goal);
seq_printf(m, "\tCurr: ");
ahd_format_transinfo(m, &tinfo->curr);
for (lun = 0; lun < AHD_NUM_LUNS; lun++) {
struct scsi_device *dev;
dev = scsi_device_lookup_by_target(starget, lun);
if (dev == NULL)
continue;
ahd_dump_device_state(m, dev);
}
}
static void
ahd_dump_device_state(struct seq_file *m, struct scsi_device *sdev)
{
struct ahd_linux_device *dev = scsi_transport_device_data(sdev);
seq_printf(m, "\tChannel %c Target %d Lun %d Settings\n",
sdev->sdev_target->channel + 'A',
sdev->sdev_target->id, (u8)sdev->lun);
seq_printf(m, "\t\tCommands Queued %ld\n", dev->commands_issued);
seq_printf(m, "\t\tCommands Active %d\n", dev->active);
seq_printf(m, "\t\tCommand Openings %d\n", dev->openings);
seq_printf(m, "\t\tMax Tagged Openings %d\n", dev->maxtags);
seq_printf(m, "\t\tDevice Queue Frozen Count %d\n", dev->qfrozen);
}
int
ahd_proc_write_seeprom(struct Scsi_Host *shost, char *buffer, int length)
{
struct ahd_softc *ahd = *(struct ahd_softc **)shost->hostdata;
ahd_mode_state saved_modes;
int have_seeprom;
u_long s;
int paused;
int written;
/* Default to failure. */
written = -EINVAL;
ahd_lock(ahd, &s);
paused = ahd_is_paused(ahd);
if (!paused)
ahd_pause(ahd);
saved_modes = ahd_save_modes(ahd);
ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
if (length != sizeof(struct seeprom_config)) {
printk("ahd_proc_write_seeprom: incorrect buffer size\n");
goto done;
}
have_seeprom = ahd_verify_cksum((struct seeprom_config*)buffer);
if (have_seeprom == 0) {
printk("ahd_proc_write_seeprom: cksum verification failed\n");
goto done;
}
have_seeprom = ahd_acquire_seeprom(ahd);
if (!have_seeprom) {
printk("ahd_proc_write_seeprom: No Serial EEPROM\n");
goto done;
} else {
u_int start_addr;
if (ahd->seep_config == NULL) {
ahd->seep_config = kmalloc(sizeof(*ahd->seep_config), GFP_ATOMIC);
if (ahd->seep_config == NULL) {
printk("aic79xx: Unable to allocate serial "
"eeprom buffer. Write failing\n");
goto done;
}
}
printk("aic79xx: Writing Serial EEPROM\n");
start_addr = 32 * (ahd->channel - 'A');
ahd_write_seeprom(ahd, (u_int16_t *)buffer, start_addr,
sizeof(struct seeprom_config)/2);
ahd_read_seeprom(ahd, (uint16_t *)ahd->seep_config,
start_addr, sizeof(struct seeprom_config)/2,
/*ByteStream*/FALSE);
ahd_release_seeprom(ahd);
written = length;
}
done:
ahd_restore_modes(ahd, saved_modes);
if (!paused)
ahd_unpause(ahd);
ahd_unlock(ahd, &s);
return (written);
}
/*
* Return information to handle /proc support for the driver.
*/
int
ahd_linux_show_info(struct seq_file *m, struct Scsi_Host *shost)
{
struct ahd_softc *ahd = *(struct ahd_softc **)shost->hostdata;
char ahd_info[256];
u_int max_targ;
u_int i;
seq_printf(m, "Adaptec AIC79xx driver version: %s\n",
AIC79XX_DRIVER_VERSION);
seq_printf(m, "%s\n", ahd->description);
ahd_controller_info(ahd, ahd_info);
seq_printf(m, "%s\n", ahd_info);
seq_printf(m, "Allocated SCBs: %d, SG List Length: %d\n\n",
ahd->scb_data.numscbs, AHD_NSEG);
max_targ = 16;
if (ahd->seep_config == NULL)
seq_printf(m, "No Serial EEPROM\n");
else {
seq_printf(m, "Serial EEPROM:\n");
for (i = 0; i < sizeof(*ahd->seep_config)/2; i++) {
if (((i % 8) == 0) && (i != 0)) {
seq_printf(m, "\n");
}
seq_printf(m, "0x%.4x ",
((uint16_t*)ahd->seep_config)[i]);
}
seq_printf(m, "\n");
}
seq_printf(m, "\n");
if ((ahd->features & AHD_WIDE) == 0)
max_targ = 8;
for (i = 0; i < max_targ; i++) {
ahd_dump_target_state(ahd, m, ahd->our_id, 'A',
/*target_id*/i);
}
return 0;
}

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/*
* DO NOT EDIT - This file is automatically generated
* from the following source files:
*
* $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#120 $
* $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $
*/
#include "aic79xx_osm.h"
static const ahd_reg_parse_entry_t INTSTAT_parse_table[] = {
{ "SPLTINT", 0x01, 0x01 },
{ "CMDCMPLT", 0x02, 0x02 },
{ "SEQINT", 0x04, 0x04 },
{ "SCSIINT", 0x08, 0x08 },
{ "PCIINT", 0x10, 0x10 },
{ "SWTMINT", 0x20, 0x20 },
{ "BRKADRINT", 0x40, 0x40 },
{ "HWERRINT", 0x80, 0x80 },
{ "INT_PEND", 0xff, 0xff }
};
int
ahd_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(INTSTAT_parse_table, 9, "INTSTAT",
0x01, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t HS_MAILBOX_parse_table[] = {
{ "ENINT_COALESCE", 0x40, 0x40 },
{ "HOST_TQINPOS", 0x80, 0x80 }
};
int
ahd_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(HS_MAILBOX_parse_table, 2, "HS_MAILBOX",
0x0b, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SEQINTSTAT_parse_table[] = {
{ "SEQ_SPLTINT", 0x01, 0x01 },
{ "SEQ_PCIINT", 0x02, 0x02 },
{ "SEQ_SCSIINT", 0x04, 0x04 },
{ "SEQ_SEQINT", 0x08, 0x08 },
{ "SEQ_SWTMRTO", 0x10, 0x10 }
};
int
ahd_seqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SEQINTSTAT_parse_table, 5, "SEQINTSTAT",
0x0c, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t INTCTL_parse_table[] = {
{ "SPLTINTEN", 0x01, 0x01 },
{ "SEQINTEN", 0x02, 0x02 },
{ "SCSIINTEN", 0x04, 0x04 },
{ "PCIINTEN", 0x08, 0x08 },
{ "AUTOCLRCMDINT", 0x10, 0x10 },
{ "SWTIMER_START", 0x20, 0x20 },
{ "SWTMINTEN", 0x40, 0x40 },
{ "SWTMINTMASK", 0x80, 0x80 }
};
int
ahd_intctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(INTCTL_parse_table, 8, "INTCTL",
0x18, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t DFCNTRL_parse_table[] = {
{ "DIRECTIONEN", 0x01, 0x01 },
{ "FIFOFLUSH", 0x02, 0x02 },
{ "FIFOFLUSHACK", 0x02, 0x02 },
{ "DIRECTION", 0x04, 0x04 },
{ "DIRECTIONACK", 0x04, 0x04 },
{ "HDMAEN", 0x08, 0x08 },
{ "HDMAENACK", 0x08, 0x08 },
{ "SCSIEN", 0x20, 0x20 },
{ "SCSIENACK", 0x20, 0x20 },
{ "SCSIENWRDIS", 0x40, 0x40 },
{ "PRELOADEN", 0x80, 0x80 }
};
int
ahd_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(DFCNTRL_parse_table, 11, "DFCNTRL",
0x19, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t DFSTATUS_parse_table[] = {
{ "FIFOEMP", 0x01, 0x01 },
{ "FIFOFULL", 0x02, 0x02 },
{ "DFTHRESH", 0x04, 0x04 },
{ "HDONE", 0x08, 0x08 },
{ "MREQPEND", 0x10, 0x10 },
{ "PKT_PRELOAD_AVAIL", 0x40, 0x40 },
{ "PRELOAD_AVAIL", 0x80, 0x80 }
};
int
ahd_dfstatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(DFSTATUS_parse_table, 7, "DFSTATUS",
0x1a, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = {
{ "LAST_SEG_DONE", 0x01, 0x01 },
{ "LAST_SEG", 0x02, 0x02 },
{ "ODD_SEG", 0x04, 0x04 },
{ "SG_ADDR_MASK", 0xf8, 0xf8 }
};
int
ahd_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SG_CACHE_SHADOW_parse_table, 4, "SG_CACHE_SHADOW",
0x1b, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SCSISEQ0_parse_table[] = {
{ "SCSIRSTO", 0x01, 0x01 },
{ "FORCEBUSFREE", 0x10, 0x10 },
{ "ENARBO", 0x20, 0x20 },
{ "ENSELO", 0x40, 0x40 },
{ "TEMODEO", 0x80, 0x80 }
};
int
ahd_scsiseq0_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SCSISEQ0_parse_table, 5, "SCSISEQ0",
0x3a, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SCSISEQ1_parse_table[] = {
{ "ALTSTIM", 0x01, 0x01 },
{ "ENAUTOATNP", 0x02, 0x02 },
{ "MANUALP", 0x0c, 0x0c },
{ "ENRSELI", 0x10, 0x10 },
{ "ENSELI", 0x20, 0x20 },
{ "MANUALCTL", 0x40, 0x40 }
};
int
ahd_scsiseq1_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SCSISEQ1_parse_table, 6, "SCSISEQ1",
0x3b, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t DFFSTAT_parse_table[] = {
{ "CURRFIFO_0", 0x00, 0x03 },
{ "CURRFIFO_1", 0x01, 0x03 },
{ "CURRFIFO_NONE", 0x03, 0x03 },
{ "FIFO0FREE", 0x10, 0x10 },
{ "FIFO1FREE", 0x20, 0x20 },
{ "CURRFIFO", 0x03, 0x03 }
};
int
ahd_dffstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(DFFSTAT_parse_table, 6, "DFFSTAT",
0x3f, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SCSISIGI_parse_table[] = {
{ "P_DATAOUT", 0x00, 0xe0 },
{ "P_DATAOUT_DT", 0x20, 0xe0 },
{ "P_DATAIN", 0x40, 0xe0 },
{ "P_DATAIN_DT", 0x60, 0xe0 },
{ "P_COMMAND", 0x80, 0xe0 },
{ "P_MESGOUT", 0xa0, 0xe0 },
{ "P_STATUS", 0xc0, 0xe0 },
{ "P_MESGIN", 0xe0, 0xe0 },
{ "ACKI", 0x01, 0x01 },
{ "REQI", 0x02, 0x02 },
{ "BSYI", 0x04, 0x04 },
{ "SELI", 0x08, 0x08 },
{ "ATNI", 0x10, 0x10 },
{ "MSGI", 0x20, 0x20 },
{ "IOI", 0x40, 0x40 },
{ "CDI", 0x80, 0x80 },
{ "PHASE_MASK", 0xe0, 0xe0 }
};
int
ahd_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SCSISIGI_parse_table, 17, "SCSISIGI",
0x41, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SCSIPHASE_parse_table[] = {
{ "DATA_OUT_PHASE", 0x01, 0x03 },
{ "DATA_IN_PHASE", 0x02, 0x03 },
{ "DATA_PHASE_MASK", 0x03, 0x03 },
{ "MSG_OUT_PHASE", 0x04, 0x04 },
{ "MSG_IN_PHASE", 0x08, 0x08 },
{ "COMMAND_PHASE", 0x10, 0x10 },
{ "STATUS_PHASE", 0x20, 0x20 }
};
int
ahd_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SCSIPHASE_parse_table, 7, "SCSIPHASE",
0x42, regvalue, cur_col, wrap));
}
int
ahd_scsibus_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(NULL, 0, "SCSIBUS",
0x46, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SELID_parse_table[] = {
{ "ONEBIT", 0x08, 0x08 },
{ "SELID_MASK", 0xf0, 0xf0 }
};
int
ahd_selid_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SELID_parse_table, 2, "SELID",
0x49, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SSTAT0_parse_table[] = {
{ "ARBDO", 0x01, 0x01 },
{ "SPIORDY", 0x02, 0x02 },
{ "OVERRUN", 0x04, 0x04 },
{ "IOERR", 0x08, 0x08 },
{ "SELINGO", 0x10, 0x10 },
{ "SELDI", 0x20, 0x20 },
{ "SELDO", 0x40, 0x40 },
{ "TARGET", 0x80, 0x80 }
};
int
ahd_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SSTAT0_parse_table, 8, "SSTAT0",
0x4b, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SIMODE0_parse_table[] = {
{ "ENARBDO", 0x01, 0x01 },
{ "ENSPIORDY", 0x02, 0x02 },
{ "ENOVERRUN", 0x04, 0x04 },
{ "ENIOERR", 0x08, 0x08 },
{ "ENSELINGO", 0x10, 0x10 },
{ "ENSELDI", 0x20, 0x20 },
{ "ENSELDO", 0x40, 0x40 }
};
int
ahd_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SIMODE0_parse_table, 7, "SIMODE0",
0x4b, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SSTAT1_parse_table[] = {
{ "REQINIT", 0x01, 0x01 },
{ "STRB2FAST", 0x02, 0x02 },
{ "SCSIPERR", 0x04, 0x04 },
{ "BUSFREE", 0x08, 0x08 },
{ "PHASEMIS", 0x10, 0x10 },
{ "SCSIRSTI", 0x20, 0x20 },
{ "ATNTARG", 0x40, 0x40 },
{ "SELTO", 0x80, 0x80 }
};
int
ahd_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SSTAT1_parse_table, 8, "SSTAT1",
0x4c, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SSTAT2_parse_table[] = {
{ "BUSFREE_LQO", 0x40, 0xc0 },
{ "BUSFREE_DFF0", 0x80, 0xc0 },
{ "BUSFREE_DFF1", 0xc0, 0xc0 },
{ "DMADONE", 0x01, 0x01 },
{ "SDONE", 0x02, 0x02 },
{ "WIDE_RES", 0x04, 0x04 },
{ "BSYX", 0x08, 0x08 },
{ "EXP_ACTIVE", 0x10, 0x10 },
{ "NONPACKREQ", 0x20, 0x20 },
{ "BUSFREETIME", 0xc0, 0xc0 }
};
int
ahd_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SSTAT2_parse_table, 10, "SSTAT2",
0x4d, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t PERRDIAG_parse_table[] = {
{ "DTERR", 0x01, 0x01 },
{ "DGFORMERR", 0x02, 0x02 },
{ "CRCERR", 0x04, 0x04 },
{ "AIPERR", 0x08, 0x08 },
{ "PARITYERR", 0x10, 0x10 },
{ "PREVPHASE", 0x20, 0x20 },
{ "HIPERR", 0x40, 0x40 },
{ "HIZERO", 0x80, 0x80 }
};
int
ahd_perrdiag_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(PERRDIAG_parse_table, 8, "PERRDIAG",
0x4e, regvalue, cur_col, wrap));
}
int
ahd_soffcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(NULL, 0, "SOFFCNT",
0x4f, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t LQISTAT0_parse_table[] = {
{ "LQIATNCMD", 0x01, 0x01 },
{ "LQIATNLQ", 0x02, 0x02 },
{ "LQIBADLQT", 0x04, 0x04 },
{ "LQICRCT2", 0x08, 0x08 },
{ "LQICRCT1", 0x10, 0x10 },
{ "LQIATNQAS", 0x20, 0x20 }
};
int
ahd_lqistat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(LQISTAT0_parse_table, 6, "LQISTAT0",
0x50, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t LQISTAT1_parse_table[] = {
{ "LQIOVERI_NLQ", 0x01, 0x01 },
{ "LQIOVERI_LQ", 0x02, 0x02 },
{ "LQIBADLQI", 0x04, 0x04 },
{ "LQICRCI_NLQ", 0x08, 0x08 },
{ "LQICRCI_LQ", 0x10, 0x10 },
{ "LQIABORT", 0x20, 0x20 },
{ "LQIPHASE_NLQ", 0x40, 0x40 },
{ "LQIPHASE_LQ", 0x80, 0x80 }
};
int
ahd_lqistat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(LQISTAT1_parse_table, 8, "LQISTAT1",
0x51, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t LQISTAT2_parse_table[] = {
{ "LQIGSAVAIL", 0x01, 0x01 },
{ "LQISTOPCMD", 0x02, 0x02 },
{ "LQISTOPLQ", 0x04, 0x04 },
{ "LQISTOPPKT", 0x08, 0x08 },
{ "LQIWAITFIFO", 0x10, 0x10 },
{ "LQIWORKONLQ", 0x20, 0x20 },
{ "LQIPHASE_OUTPKT", 0x40, 0x40 },
{ "PACKETIZED", 0x80, 0x80 }
};
int
ahd_lqistat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(LQISTAT2_parse_table, 8, "LQISTAT2",
0x52, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SSTAT3_parse_table[] = {
{ "OSRAMPERR", 0x01, 0x01 },
{ "NTRAMPERR", 0x02, 0x02 }
};
int
ahd_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SSTAT3_parse_table, 2, "SSTAT3",
0x53, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = {
{ "LQOTCRC", 0x01, 0x01 },
{ "LQOATNPKT", 0x02, 0x02 },
{ "LQOATNLQ", 0x04, 0x04 },
{ "LQOSTOPT2", 0x08, 0x08 },
{ "LQOTARGSCBPERR", 0x10, 0x10 }
};
int
ahd_lqostat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(LQOSTAT0_parse_table, 5, "LQOSTAT0",
0x54, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = {
{ "LQOPHACHGINPKT", 0x01, 0x01 },
{ "LQOBUSFREE", 0x02, 0x02 },
{ "LQOBADQAS", 0x04, 0x04 },
{ "LQOSTOPI2", 0x08, 0x08 },
{ "LQOINITSCBPERR", 0x10, 0x10 }
};
int
ahd_lqostat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(LQOSTAT1_parse_table, 5, "LQOSTAT1",
0x55, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = {
{ "LQOSTOP0", 0x01, 0x01 },
{ "LQOPHACHGOUTPKT", 0x02, 0x02 },
{ "LQOWAITFIFO", 0x10, 0x10 },
{ "LQOPKT", 0xe0, 0xe0 }
};
int
ahd_lqostat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(LQOSTAT2_parse_table, 4, "LQOSTAT2",
0x56, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SIMODE1_parse_table[] = {
{ "ENREQINIT", 0x01, 0x01 },
{ "ENSTRB2FAST", 0x02, 0x02 },
{ "ENSCSIPERR", 0x04, 0x04 },
{ "ENBUSFREE", 0x08, 0x08 },
{ "ENPHASEMIS", 0x10, 0x10 },
{ "ENSCSIRST", 0x20, 0x20 },
{ "ENATNTARG", 0x40, 0x40 },
{ "ENSELTIMO", 0x80, 0x80 }
};
int
ahd_simode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SIMODE1_parse_table, 8, "SIMODE1",
0x57, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t DFFSXFRCTL_parse_table[] = {
{ "RSTCHN", 0x01, 0x01 },
{ "CLRCHN", 0x02, 0x02 },
{ "CLRSHCNT", 0x04, 0x04 },
{ "DFFBITBUCKET", 0x08, 0x08 }
};
int
ahd_dffsxfrctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(DFFSXFRCTL_parse_table, 4, "DFFSXFRCTL",
0x5a, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SEQINTSRC_parse_table[] = {
{ "CFG4TCMD", 0x01, 0x01 },
{ "CFG4ICMD", 0x02, 0x02 },
{ "CFG4TSTAT", 0x04, 0x04 },
{ "CFG4ISTAT", 0x08, 0x08 },
{ "CFG4DATA", 0x10, 0x10 },
{ "SAVEPTRS", 0x20, 0x20 },
{ "CTXTDONE", 0x40, 0x40 }
};
int
ahd_seqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SEQINTSRC_parse_table, 7, "SEQINTSRC",
0x5b, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SEQIMODE_parse_table[] = {
{ "ENCFG4TCMD", 0x01, 0x01 },
{ "ENCFG4ICMD", 0x02, 0x02 },
{ "ENCFG4TSTAT", 0x04, 0x04 },
{ "ENCFG4ISTAT", 0x08, 0x08 },
{ "ENCFG4DATA", 0x10, 0x10 },
{ "ENSAVEPTRS", 0x20, 0x20 },
{ "ENCTXTDONE", 0x40, 0x40 }
};
int
ahd_seqimode_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SEQIMODE_parse_table, 7, "SEQIMODE",
0x5c, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t MDFFSTAT_parse_table[] = {
{ "FIFOFREE", 0x01, 0x01 },
{ "DATAINFIFO", 0x02, 0x02 },
{ "DLZERO", 0x04, 0x04 },
{ "SHVALID", 0x08, 0x08 },
{ "LASTSDONE", 0x10, 0x10 },
{ "SHCNTMINUS1", 0x20, 0x20 },
{ "SHCNTNEGATIVE", 0x40, 0x40 }
};
int
ahd_mdffstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(MDFFSTAT_parse_table, 7, "MDFFSTAT",
0x5d, regvalue, cur_col, wrap));
}
int
ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(NULL, 0, "SELOID",
0x6b, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SG_STATE_parse_table[] = {
{ "SEGS_AVAIL", 0x01, 0x01 },
{ "LOADING_NEEDED", 0x02, 0x02 },
{ "FETCH_INPROG", 0x04, 0x04 }
};
int
ahd_sg_state_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SG_STATE_parse_table, 3, "SG_STATE",
0xa6, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = {
{ "CCSCBRESET", 0x01, 0x01 },
{ "CCSCBDIR", 0x04, 0x04 },
{ "CCSCBEN", 0x08, 0x08 },
{ "CCARREN", 0x10, 0x10 },
{ "ARRDONE", 0x40, 0x40 },
{ "CCSCBDONE", 0x80, 0x80 }
};
int
ahd_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(CCSCBCTL_parse_table, 6, "CCSCBCTL",
0xad, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t CCSGCTL_parse_table[] = {
{ "CCSGRESET", 0x01, 0x01 },
{ "SG_FETCH_REQ", 0x02, 0x02 },
{ "CCSGENACK", 0x08, 0x08 },
{ "SG_CACHE_AVAIL", 0x10, 0x10 },
{ "CCSGDONE", 0x80, 0x80 },
{ "CCSGEN", 0x0c, 0x0c }
};
int
ahd_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(CCSGCTL_parse_table, 6, "CCSGCTL",
0xad, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SEQCTL0_parse_table[] = {
{ "LOADRAM", 0x01, 0x01 },
{ "SEQRESET", 0x02, 0x02 },
{ "STEP", 0x04, 0x04 },
{ "BRKADRINTEN", 0x08, 0x08 },
{ "FASTMODE", 0x10, 0x10 },
{ "FAILDIS", 0x20, 0x20 },
{ "PAUSEDIS", 0x40, 0x40 },
{ "PERRORDIS", 0x80, 0x80 }
};
int
ahd_seqctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SEQCTL0_parse_table, 8, "SEQCTL0",
0xd6, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SEQINTCTL_parse_table[] = {
{ "IRET", 0x01, 0x01 },
{ "INTMASK1", 0x02, 0x02 },
{ "INTMASK2", 0x04, 0x04 },
{ "SCS_SEQ_INT1M0", 0x08, 0x08 },
{ "SCS_SEQ_INT1M1", 0x10, 0x10 },
{ "INT1_CONTEXT", 0x20, 0x20 },
{ "INTVEC1DSL", 0x80, 0x80 }
};
int
ahd_seqintctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SEQINTCTL_parse_table, 7, "SEQINTCTL",
0xd9, regvalue, cur_col, wrap));
}
int
ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(NULL, 0, "SRAM_BASE",
0x100, regvalue, cur_col, wrap));
}
int
ahd_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(NULL, 0, "QFREEZE_COUNT",
0x132, regvalue, cur_col, wrap));
}
int
ahd_kernel_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT",
0x134, regvalue, cur_col, wrap));
}
int
ahd_saved_mode_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(NULL, 0, "SAVED_MODE",
0x136, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
{ "NO_DISCONNECT", 0x01, 0x01 },
{ "SPHASE_PENDING", 0x02, 0x02 },
{ "DPHASE_PENDING", 0x04, 0x04 },
{ "CMDPHASE_PENDING", 0x08, 0x08 },
{ "TARG_CMD_PENDING", 0x10, 0x10 },
{ "DPHASE", 0x20, 0x20 },
{ "NO_CDB_SENT", 0x40, 0x40 },
{ "TARGET_CMD_IS_TAGGED",0x40, 0x40 },
{ "NOT_IDENTIFIED", 0x80, 0x80 }
};
int
ahd_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SEQ_FLAGS_parse_table, 9, "SEQ_FLAGS",
0x139, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t LASTPHASE_parse_table[] = {
{ "P_DATAOUT", 0x00, 0xe0 },
{ "P_DATAOUT_DT", 0x20, 0xe0 },
{ "P_DATAIN", 0x40, 0xe0 },
{ "P_DATAIN_DT", 0x60, 0xe0 },
{ "P_COMMAND", 0x80, 0xe0 },
{ "P_MESGOUT", 0xa0, 0xe0 },
{ "P_STATUS", 0xc0, 0xe0 },
{ "P_MESGIN", 0xe0, 0xe0 },
{ "P_BUSFREE", 0x01, 0x01 },
{ "MSGI", 0x20, 0x20 },
{ "IOI", 0x40, 0x40 },
{ "CDI", 0x80, 0x80 },
{ "PHASE_MASK", 0xe0, 0xe0 }
};
int
ahd_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(LASTPHASE_parse_table, 13, "LASTPHASE",
0x13c, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = {
{ "PENDING_MK_MESSAGE", 0x01, 0x01 },
{ "TARGET_MSG_PENDING", 0x02, 0x02 },
{ "SELECTOUT_QFROZEN", 0x04, 0x04 }
};
int
ahd_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SEQ_FLAGS2_parse_table, 3, "SEQ_FLAGS2",
0x14d, regvalue, cur_col, wrap));
}
int
ahd_mk_message_scb_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCB",
0x160, regvalue, cur_col, wrap));
}
int
ahd_mk_message_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID",
0x162, regvalue, cur_col, wrap));
}
int
ahd_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(NULL, 0, "SCB_BASE",
0x180, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SCB_CONTROL_parse_table[] = {
{ "SCB_TAG_TYPE", 0x03, 0x03 },
{ "DISCONNECTED", 0x04, 0x04 },
{ "STATUS_RCVD", 0x08, 0x08 },
{ "MK_MESSAGE", 0x10, 0x10 },
{ "TAG_ENB", 0x20, 0x20 },
{ "DISCENB", 0x40, 0x40 },
{ "TARGET_SCB", 0x80, 0x80 }
};
int
ahd_scb_control_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SCB_CONTROL_parse_table, 7, "SCB_CONTROL",
0x192, regvalue, cur_col, wrap));
}
static const ahd_reg_parse_entry_t SCB_SCSIID_parse_table[] = {
{ "OID", 0x0f, 0x0f },
{ "TID", 0xf0, 0xf0 }
};
int
ahd_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahd_print_register(SCB_SCSIID_parse_table, 2, "SCB_SCSIID",
0x193, regvalue, cur_col, wrap));
}

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/*
* Interface for the 93C66/56/46/26/06 serial eeprom parts.
*
* Copyright (c) 1995, 1996 Daniel M. Eischen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL").
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: //depot/aic7xxx/aic7xxx/aic7xxx_93cx6.c#19 $
*/
/*
* The instruction set of the 93C66/56/46/26/06 chips are as follows:
*
* Start OP *
* Function Bit Code Address** Data Description
* -------------------------------------------------------------------
* READ 1 10 A5 - A0 Reads data stored in memory,
* starting at specified address
* EWEN 1 00 11XXXX Write enable must precede
* all programming modes
* ERASE 1 11 A5 - A0 Erase register A5A4A3A2A1A0
* WRITE 1 01 A5 - A0 D15 - D0 Writes register
* ERAL 1 00 10XXXX Erase all registers
* WRAL 1 00 01XXXX D15 - D0 Writes to all registers
* EWDS 1 00 00XXXX Disables all programming
* instructions
* *Note: A value of X for address is a don't care condition.
* **Note: There are 8 address bits for the 93C56/66 chips unlike
* the 93C46/26/06 chips which have 6 address bits.
*
* The 93C46 has a four wire interface: clock, chip select, data in, and
* data out. In order to perform one of the above functions, you need
* to enable the chip select for a clock period (typically a minimum of
* 1 usec, with the clock high and low a minimum of 750 and 250 nsec
* respectively). While the chip select remains high, you can clock in
* the instructions (above) starting with the start bit, followed by the
* OP code, Address, and Data (if needed). For the READ instruction, the
* requested 16-bit register contents is read from the data out line but
* is preceded by an initial zero (leading 0, followed by 16-bits, MSB
* first). The clock cycling from low to high initiates the next data
* bit to be sent from the chip.
*/
#ifdef __linux__
#include "aic7xxx_osm.h"
#include "aic7xxx_inline.h"
#include "aic7xxx_93cx6.h"
#else
#include <dev/aic7xxx/aic7xxx_osm.h>
#include <dev/aic7xxx/aic7xxx_inline.h>
#include <dev/aic7xxx/aic7xxx_93cx6.h>
#endif
/*
* Right now, we only have to read the SEEPROM. But we make it easier to
* add other 93Cx6 functions.
*/
struct seeprom_cmd {
uint8_t len;
uint8_t bits[11];
};
/* Short opcodes for the c46 */
static const struct seeprom_cmd seeprom_ewen = {9, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
static const struct seeprom_cmd seeprom_ewds = {9, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
/* Long opcodes for the C56/C66 */
static const struct seeprom_cmd seeprom_long_ewen = {11, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
static const struct seeprom_cmd seeprom_long_ewds = {11, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
/* Common opcodes */
static const struct seeprom_cmd seeprom_write = {3, {1, 0, 1}};
static const struct seeprom_cmd seeprom_read = {3, {1, 1, 0}};
/*
* Wait for the SEERDY to go high; about 800 ns.
*/
#define CLOCK_PULSE(sd, rdy) \
while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) { \
; /* Do nothing */ \
} \
(void)SEEPROM_INB(sd); /* Clear clock */
/*
* Send a START condition and the given command
*/
static void
send_seeprom_cmd(struct seeprom_descriptor *sd, const struct seeprom_cmd *cmd)
{
uint8_t temp;
int i = 0;
/* Send chip select for one clock cycle. */
temp = sd->sd_MS ^ sd->sd_CS;
SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
CLOCK_PULSE(sd, sd->sd_RDY);
for (i = 0; i < cmd->len; i++) {
if (cmd->bits[i] != 0)
temp ^= sd->sd_DO;
SEEPROM_OUTB(sd, temp);
CLOCK_PULSE(sd, sd->sd_RDY);
SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
CLOCK_PULSE(sd, sd->sd_RDY);
if (cmd->bits[i] != 0)
temp ^= sd->sd_DO;
}
}
/*
* Clear CS put the chip in the reset state, where it can wait for new commands.
*/
static void
reset_seeprom(struct seeprom_descriptor *sd)
{
uint8_t temp;
temp = sd->sd_MS;
SEEPROM_OUTB(sd, temp);
CLOCK_PULSE(sd, sd->sd_RDY);
SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
CLOCK_PULSE(sd, sd->sd_RDY);
SEEPROM_OUTB(sd, temp);
CLOCK_PULSE(sd, sd->sd_RDY);
}
/*
* Read the serial EEPROM and returns 1 if successful and 0 if
* not successful.
*/
int
ahc_read_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
u_int start_addr, u_int count)
{
int i = 0;
u_int k = 0;
uint16_t v;
uint8_t temp;
/*
* Read the requested registers of the seeprom. The loop
* will range from 0 to count-1.
*/
for (k = start_addr; k < count + start_addr; k++) {
/*
* Now we're ready to send the read command followed by the
* address of the 16-bit register we want to read.
*/
send_seeprom_cmd(sd, &seeprom_read);
/* Send the 6 or 8 bit address (MSB first, LSB last). */
temp = sd->sd_MS ^ sd->sd_CS;
for (i = (sd->sd_chip - 1); i >= 0; i--) {
if ((k & (1 << i)) != 0)
temp ^= sd->sd_DO;
SEEPROM_OUTB(sd, temp);
CLOCK_PULSE(sd, sd->sd_RDY);
SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
CLOCK_PULSE(sd, sd->sd_RDY);
if ((k & (1 << i)) != 0)
temp ^= sd->sd_DO;
}
/*
* Now read the 16 bit register. An initial 0 precedes the
* register contents which begins with bit 15 (MSB) and ends
* with bit 0 (LSB). The initial 0 will be shifted off the
* top of our word as we let the loop run from 0 to 16.
*/
v = 0;
for (i = 16; i >= 0; i--) {
SEEPROM_OUTB(sd, temp);
CLOCK_PULSE(sd, sd->sd_RDY);
v <<= 1;
if (SEEPROM_DATA_INB(sd) & sd->sd_DI)
v |= 1;
SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
CLOCK_PULSE(sd, sd->sd_RDY);
}
buf[k - start_addr] = v;
/* Reset the chip select for the next command cycle. */
reset_seeprom(sd);
}
#ifdef AHC_DUMP_EEPROM
printk("\nSerial EEPROM:\n\t");
for (k = 0; k < count; k = k + 1) {
if (((k % 8) == 0) && (k != 0)) {
printk(KERN_CONT "\n\t");
}
printk(KERN_CONT " 0x%x", buf[k]);
}
printk(KERN_CONT "\n");
#endif
return (1);
}
/*
* Write the serial EEPROM and return 1 if successful and 0 if
* not successful.
*/
int
ahc_write_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
u_int start_addr, u_int count)
{
const struct seeprom_cmd *ewen, *ewds;
uint16_t v;
uint8_t temp;
int i, k;
/* Place the chip into write-enable mode */
if (sd->sd_chip == C46) {
ewen = &seeprom_ewen;
ewds = &seeprom_ewds;
} else if (sd->sd_chip == C56_66) {
ewen = &seeprom_long_ewen;
ewds = &seeprom_long_ewds;
} else {
printk("ahc_write_seeprom: unsupported seeprom type %d\n",
sd->sd_chip);
return (0);
}
send_seeprom_cmd(sd, ewen);
reset_seeprom(sd);
/* Write all requested data out to the seeprom. */
temp = sd->sd_MS ^ sd->sd_CS;
for (k = start_addr; k < count + start_addr; k++) {
/* Send the write command */
send_seeprom_cmd(sd, &seeprom_write);
/* Send the 6 or 8 bit address (MSB first). */
for (i = (sd->sd_chip - 1); i >= 0; i--) {
if ((k & (1 << i)) != 0)
temp ^= sd->sd_DO;
SEEPROM_OUTB(sd, temp);
CLOCK_PULSE(sd, sd->sd_RDY);
SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
CLOCK_PULSE(sd, sd->sd_RDY);
if ((k & (1 << i)) != 0)
temp ^= sd->sd_DO;
}
/* Write the 16 bit value, MSB first */
v = buf[k - start_addr];
for (i = 15; i >= 0; i--) {
if ((v & (1 << i)) != 0)
temp ^= sd->sd_DO;
SEEPROM_OUTB(sd, temp);
CLOCK_PULSE(sd, sd->sd_RDY);
SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
CLOCK_PULSE(sd, sd->sd_RDY);
if ((v & (1 << i)) != 0)
temp ^= sd->sd_DO;
}
/* Wait for the chip to complete the write */
temp = sd->sd_MS;
SEEPROM_OUTB(sd, temp);
CLOCK_PULSE(sd, sd->sd_RDY);
temp = sd->sd_MS ^ sd->sd_CS;
do {
SEEPROM_OUTB(sd, temp);
CLOCK_PULSE(sd, sd->sd_RDY);
SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
CLOCK_PULSE(sd, sd->sd_RDY);
} while ((SEEPROM_DATA_INB(sd) & sd->sd_DI) == 0);
reset_seeprom(sd);
}
/* Put the chip back into write-protect mode */
send_seeprom_cmd(sd, ewds);
reset_seeprom(sd);
return (1);
}
int
ahc_verify_cksum(struct seeprom_config *sc)
{
int i;
int maxaddr;
uint32_t checksum;
uint16_t *scarray;
maxaddr = (sizeof(*sc)/2) - 1;
checksum = 0;
scarray = (uint16_t *)sc;
for (i = 0; i < maxaddr; i++)
checksum = checksum + scarray[i];
if (checksum == 0
|| (checksum & 0xFFFF) != sc->checksum) {
return (0);
} else {
return(1);
}
}

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/*
* Interface to the 93C46/56 serial EEPROM that is used to store BIOS
* settings for the aic7xxx based adaptec SCSI controllers. It can
* also be used for 93C26 and 93C06 serial EEPROMS.
*
* Copyright (c) 1994, 1995, 2000 Justin T. Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aic7xxx_93cx6.h#12 $
*
* $FreeBSD$
*/
#ifndef _AIC7XXX_93CX6_H_
#define _AIC7XXX_93CX6_H_
typedef enum {
C46 = 6,
C56_66 = 8
} seeprom_chip_t;
struct seeprom_descriptor {
struct ahc_softc *sd_ahc;
u_int sd_control_offset;
u_int sd_status_offset;
u_int sd_dataout_offset;
seeprom_chip_t sd_chip;
uint16_t sd_MS;
uint16_t sd_RDY;
uint16_t sd_CS;
uint16_t sd_CK;
uint16_t sd_DO;
uint16_t sd_DI;
};
/*
* This function will read count 16-bit words from the serial EEPROM and
* return their value in buf. The port address of the aic7xxx serial EEPROM
* control register is passed in as offset. The following parameters are
* also passed in:
*
* CS - Chip select
* CK - Clock
* DO - Data out
* DI - Data in
* RDY - SEEPROM ready
* MS - Memory port mode select
*
* A failed read attempt returns 0, and a successful read returns 1.
*/
#define SEEPROM_INB(sd) \
ahc_inb(sd->sd_ahc, sd->sd_control_offset)
#define SEEPROM_OUTB(sd, value) \
do { \
ahc_outb(sd->sd_ahc, sd->sd_control_offset, value); \
ahc_flush_device_writes(sd->sd_ahc); \
} while(0)
#define SEEPROM_STATUS_INB(sd) \
ahc_inb(sd->sd_ahc, sd->sd_status_offset)
#define SEEPROM_DATA_INB(sd) \
ahc_inb(sd->sd_ahc, sd->sd_dataout_offset)
int ahc_read_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
u_int start_addr, u_int count);
int ahc_write_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
u_int start_addr, u_int count);
int ahc_verify_cksum(struct seeprom_config *sc);
#endif /* _AIC7XXX_93CX6_H_ */

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/*
* Inline routines shareable across OS platforms.
*
* Copyright (c) 1994-2001 Justin T. Gibbs.
* Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aic7xxx_inline.h#43 $
*
* $FreeBSD$
*/
#ifndef _AIC7XXX_INLINE_H_
#define _AIC7XXX_INLINE_H_
/************************* Sequencer Execution Control ************************/
int ahc_is_paused(struct ahc_softc *ahc);
void ahc_pause(struct ahc_softc *ahc);
void ahc_unpause(struct ahc_softc *ahc);
/************************** Memory mapping routines ***************************/
void ahc_sync_sglist(struct ahc_softc *ahc,
struct scb *scb, int op);
/******************************** Debugging ***********************************/
static inline char *ahc_name(struct ahc_softc *ahc);
static inline char *ahc_name(struct ahc_softc *ahc)
{
return (ahc->name);
}
/*********************** Miscellaneous Support Functions ***********************/
struct ahc_initiator_tinfo *
ahc_fetch_transinfo(struct ahc_softc *ahc,
char channel, u_int our_id,
u_int remote_id,
struct ahc_tmode_tstate **tstate);
uint16_t
ahc_inw(struct ahc_softc *ahc, u_int port);
void ahc_outw(struct ahc_softc *ahc, u_int port,
u_int value);
uint32_t
ahc_inl(struct ahc_softc *ahc, u_int port);
void ahc_outl(struct ahc_softc *ahc, u_int port,
uint32_t value);
uint64_t
ahc_inq(struct ahc_softc *ahc, u_int port);
void ahc_outq(struct ahc_softc *ahc, u_int port,
uint64_t value);
struct scb*
ahc_get_scb(struct ahc_softc *ahc);
void ahc_free_scb(struct ahc_softc *ahc, struct scb *scb);
struct scb *
ahc_lookup_scb(struct ahc_softc *ahc, u_int tag);
void ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb);
struct scsi_sense_data *
ahc_get_sense_buf(struct ahc_softc *ahc,
struct scb *scb);
/************************** Interrupt Processing ******************************/
int ahc_intr(struct ahc_softc *ahc);
#endif /* _AIC7XXX_INLINE_H_ */

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/*
* Adaptec AIC7xxx device driver for Linux.
*
* Copyright (c) 1994 John Aycock
* The University of Calgary Department of Computer Science.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Copyright (c) 2000-2003 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic7xxx_osm.h#151 $
*
*/
#ifndef _AIC7XXX_LINUX_H_
#define _AIC7XXX_LINUX_H_
#include <linux/types.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <scsi/scsi.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_eh.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_tcq.h>
#include <scsi/scsi_transport.h>
#include <scsi/scsi_transport_spi.h>
/* Core SCSI definitions */
#define AIC_LIB_PREFIX ahc
/* Name space conflict with BSD queue macros */
#ifdef LIST_HEAD
#undef LIST_HEAD
#endif
#include "cam.h"
#include "queue.h"
#include "scsi_message.h"
#include "aiclib.h"
/*********************************** Debugging ********************************/
#ifdef CONFIG_AIC7XXX_DEBUG_ENABLE
#ifdef CONFIG_AIC7XXX_DEBUG_MASK
#define AHC_DEBUG 1
#define AHC_DEBUG_OPTS CONFIG_AIC7XXX_DEBUG_MASK
#else
/*
* Compile in debugging code, but do not enable any printfs.
*/
#define AHC_DEBUG 1
#endif
/* No debugging code. */
#endif
/************************* Forward Declarations *******************************/
struct ahc_softc;
typedef struct pci_dev *ahc_dev_softc_t;
typedef struct scsi_cmnd *ahc_io_ctx_t;
/******************************* Byte Order ***********************************/
#define ahc_htobe16(x) cpu_to_be16(x)
#define ahc_htobe32(x) cpu_to_be32(x)
#define ahc_htobe64(x) cpu_to_be64(x)
#define ahc_htole16(x) cpu_to_le16(x)
#define ahc_htole32(x) cpu_to_le32(x)
#define ahc_htole64(x) cpu_to_le64(x)
#define ahc_be16toh(x) be16_to_cpu(x)
#define ahc_be32toh(x) be32_to_cpu(x)
#define ahc_be64toh(x) be64_to_cpu(x)
#define ahc_le16toh(x) le16_to_cpu(x)
#define ahc_le32toh(x) le32_to_cpu(x)
#define ahc_le64toh(x) le64_to_cpu(x)
/************************* Configuration Data *********************************/
extern u_int aic7xxx_no_probe;
extern u_int aic7xxx_allow_memio;
extern struct scsi_host_template aic7xxx_driver_template;
/***************************** Bus Space/DMA **********************************/
typedef uint32_t bus_size_t;
typedef enum {
BUS_SPACE_MEMIO,
BUS_SPACE_PIO
} bus_space_tag_t;
typedef union {
u_long ioport;
volatile uint8_t __iomem *maddr;
} bus_space_handle_t;
typedef struct bus_dma_segment
{
dma_addr_t ds_addr;
bus_size_t ds_len;
} bus_dma_segment_t;
struct ahc_linux_dma_tag
{
bus_size_t alignment;
bus_size_t boundary;
bus_size_t maxsize;
};
typedef struct ahc_linux_dma_tag* bus_dma_tag_t;
typedef dma_addr_t bus_dmamap_t;
typedef int bus_dma_filter_t(void*, dma_addr_t);
typedef void bus_dmamap_callback_t(void *, bus_dma_segment_t *, int, int);
#define BUS_DMA_WAITOK 0x0
#define BUS_DMA_NOWAIT 0x1
#define BUS_DMA_ALLOCNOW 0x2
#define BUS_DMA_LOAD_SEGS 0x4 /*
* Argument is an S/G list not
* a single buffer.
*/
#define BUS_SPACE_MAXADDR 0xFFFFFFFF
#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF
#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF
int ahc_dma_tag_create(struct ahc_softc *, bus_dma_tag_t /*parent*/,
bus_size_t /*alignment*/, bus_size_t /*boundary*/,
dma_addr_t /*lowaddr*/, dma_addr_t /*highaddr*/,
bus_dma_filter_t*/*filter*/, void */*filterarg*/,
bus_size_t /*maxsize*/, int /*nsegments*/,
bus_size_t /*maxsegsz*/, int /*flags*/,
bus_dma_tag_t */*dma_tagp*/);
void ahc_dma_tag_destroy(struct ahc_softc *, bus_dma_tag_t /*tag*/);
int ahc_dmamem_alloc(struct ahc_softc *, bus_dma_tag_t /*dmat*/,
void** /*vaddr*/, int /*flags*/,
bus_dmamap_t* /*mapp*/);
void ahc_dmamem_free(struct ahc_softc *, bus_dma_tag_t /*dmat*/,
void* /*vaddr*/, bus_dmamap_t /*map*/);
void ahc_dmamap_destroy(struct ahc_softc *, bus_dma_tag_t /*tag*/,
bus_dmamap_t /*map*/);
int ahc_dmamap_load(struct ahc_softc *ahc, bus_dma_tag_t /*dmat*/,
bus_dmamap_t /*map*/, void * /*buf*/,
bus_size_t /*buflen*/, bus_dmamap_callback_t *,
void */*callback_arg*/, int /*flags*/);
int ahc_dmamap_unload(struct ahc_softc *, bus_dma_tag_t, bus_dmamap_t);
/*
* Operations performed by ahc_dmamap_sync().
*/
#define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
#define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
#define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
#define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
/*
* XXX
* ahc_dmamap_sync is only used on buffers allocated with
* the pci_alloc_consistent() API. Although I'm not sure how
* this works on architectures with a write buffer, Linux does
* not have an API to sync "coherent" memory. Perhaps we need
* to do an mb()?
*/
#define ahc_dmamap_sync(ahc, dma_tag, dmamap, offset, len, op)
/********************************** Includes **********************************/
#ifdef CONFIG_AIC7XXX_REG_PRETTY_PRINT
#define AIC_DEBUG_REGISTERS 1
#else
#define AIC_DEBUG_REGISTERS 0
#endif
#include "aic7xxx.h"
/***************************** Timer Facilities *******************************/
static inline void
ahc_scb_timer_reset(struct scb *scb, u_int usec)
{
}
/***************************** SMP support ************************************/
#include <linux/spinlock.h>
#define AIC7XXX_DRIVER_VERSION "7.0"
/*************************** Device Data Structures ***************************/
/*
* A per probed device structure used to deal with some error recovery
* scenarios that the Linux mid-layer code just doesn't know how to
* handle. The structure allocated for a device only becomes persistent
* after a successfully completed inquiry command to the target when
* that inquiry data indicates a lun is present.
*/
typedef enum {
AHC_DEV_FREEZE_TIL_EMPTY = 0x02, /* Freeze queue until active == 0 */
AHC_DEV_Q_BASIC = 0x10, /* Allow basic device queuing */
AHC_DEV_Q_TAGGED = 0x20, /* Allow full SCSI2 command queueing */
AHC_DEV_PERIODIC_OTAG = 0x40, /* Send OTAG to prevent starvation */
} ahc_linux_dev_flags;
struct ahc_linux_device {
/*
* The number of transactions currently
* queued to the device.
*/
int active;
/*
* The currently allowed number of
* transactions that can be queued to
* the device. Must be signed for
* conversion from tagged to untagged
* mode where the device may have more
* than one outstanding active transaction.
*/
int openings;
/*
* A positive count indicates that this
* device's queue is halted.
*/
u_int qfrozen;
/*
* Cumulative command counter.
*/
u_long commands_issued;
/*
* The number of tagged transactions when
* running at our current opening level
* that have been successfully received by
* this device since the last QUEUE FULL.
*/
u_int tag_success_count;
#define AHC_TAG_SUCCESS_INTERVAL 50
ahc_linux_dev_flags flags;
/*
* The high limit for the tags variable.
*/
u_int maxtags;
/*
* The computed number of tags outstanding
* at the time of the last QUEUE FULL event.
*/
u_int tags_on_last_queuefull;
/*
* How many times we have seen a queue full
* with the same number of tags. This is used
* to stop our adaptive queue depth algorithm
* on devices with a fixed number of tags.
*/
u_int last_queuefull_same_count;
#define AHC_LOCK_TAGS_COUNT 50
/*
* How many transactions have been queued
* without the device going idle. We use
* this statistic to determine when to issue
* an ordered tag to prevent transaction
* starvation. This statistic is only updated
* if the AHC_DEV_PERIODIC_OTAG flag is set
* on this device.
*/
u_int commands_since_idle_or_otag;
#define AHC_OTAG_THRESH 500
};
/********************* Definitions Required by the Core ***********************/
/*
* Number of SG segments we require. So long as the S/G segments for
* a particular transaction are allocated in a physically contiguous
* manner and are allocated below 4GB, the number of S/G segments is
* unrestricted.
*/
#define AHC_NSEG 128
/*
* Per-SCB OSM storage.
*/
struct scb_platform_data {
struct ahc_linux_device *dev;
dma_addr_t buf_busaddr;
uint32_t xfer_len;
uint32_t sense_resid; /* Auto-Sense residual */
};
/*
* Define a structure used for each host adapter. All members are
* aligned on a boundary >= the size of the member to honor the
* alignment restrictions of the various platforms supported by
* this driver.
*/
struct ahc_platform_data {
/*
* Fields accessed from interrupt context.
*/
struct scsi_target *starget[AHC_NUM_TARGETS];
spinlock_t spin_lock;
u_int qfrozen;
struct completion *eh_done;
struct Scsi_Host *host; /* pointer to scsi host */
#define AHC_LINUX_NOIRQ ((uint32_t)~0)
uint32_t irq; /* IRQ for this adapter */
uint32_t bios_address;
resource_size_t mem_busaddr; /* Mem Base Addr */
};
void ahc_delay(long);
/***************************** Low Level I/O **********************************/
uint8_t ahc_inb(struct ahc_softc * ahc, long port);
void ahc_outb(struct ahc_softc * ahc, long port, uint8_t val);
void ahc_outsb(struct ahc_softc * ahc, long port,
uint8_t *, int count);
void ahc_insb(struct ahc_softc * ahc, long port,
uint8_t *, int count);
/**************************** Initialization **********************************/
int ahc_linux_register_host(struct ahc_softc *,
struct scsi_host_template *);
/******************************** Locking *************************************/
/* Lock protecting internal data structures */
static inline void
ahc_lockinit(struct ahc_softc *ahc)
{
spin_lock_init(&ahc->platform_data->spin_lock);
}
static inline void
ahc_lock(struct ahc_softc *ahc, unsigned long *flags)
{
spin_lock_irqsave(&ahc->platform_data->spin_lock, *flags);
}
static inline void
ahc_unlock(struct ahc_softc *ahc, unsigned long *flags)
{
spin_unlock_irqrestore(&ahc->platform_data->spin_lock, *flags);
}
/******************************* PCI Definitions ******************************/
/*
* PCIM_xxx: mask to locate subfield in register
* PCIR_xxx: config register offset
* PCIC_xxx: device class
* PCIS_xxx: device subclass
* PCIP_xxx: device programming interface
* PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
* PCID_xxx: device ID
*/
#define PCIR_DEVVENDOR 0x00
#define PCIR_VENDOR 0x00
#define PCIR_DEVICE 0x02
#define PCIR_COMMAND 0x04
#define PCIM_CMD_PORTEN 0x0001
#define PCIM_CMD_MEMEN 0x0002
#define PCIM_CMD_BUSMASTEREN 0x0004
#define PCIM_CMD_MWRICEN 0x0010
#define PCIM_CMD_PERRESPEN 0x0040
#define PCIM_CMD_SERRESPEN 0x0100
#define PCIR_STATUS 0x06
#define PCIR_REVID 0x08
#define PCIR_PROGIF 0x09
#define PCIR_SUBCLASS 0x0a
#define PCIR_CLASS 0x0b
#define PCIR_CACHELNSZ 0x0c
#define PCIR_LATTIMER 0x0d
#define PCIR_HEADERTYPE 0x0e
#define PCIM_MFDEV 0x80
#define PCIR_BIST 0x0f
#define PCIR_CAP_PTR 0x34
/* config registers for header type 0 devices */
#define PCIR_MAPS 0x10
#define PCIR_SUBVEND_0 0x2c
#define PCIR_SUBDEV_0 0x2e
typedef enum
{
AHC_POWER_STATE_D0,
AHC_POWER_STATE_D1,
AHC_POWER_STATE_D2,
AHC_POWER_STATE_D3
} ahc_power_state;
/**************************** VL/EISA Routines ********************************/
#ifdef CONFIG_EISA
int ahc_linux_eisa_init(void);
void ahc_linux_eisa_exit(void);
int aic7770_map_registers(struct ahc_softc *ahc,
u_int port);
int aic7770_map_int(struct ahc_softc *ahc, u_int irq);
#else
static inline int ahc_linux_eisa_init(void) {
return -ENODEV;
}
static inline void ahc_linux_eisa_exit(void) {
}
#endif
/******************************* PCI Routines *********************************/
#ifdef CONFIG_PCI
int ahc_linux_pci_init(void);
void ahc_linux_pci_exit(void);
int ahc_pci_map_registers(struct ahc_softc *ahc);
int ahc_pci_map_int(struct ahc_softc *ahc);
uint32_t ahc_pci_read_config(ahc_dev_softc_t pci,
int reg, int width);
void ahc_pci_write_config(ahc_dev_softc_t pci,
int reg, uint32_t value,
int width);
static inline int ahc_get_pci_function(ahc_dev_softc_t);
static inline int
ahc_get_pci_function(ahc_dev_softc_t pci)
{
return (PCI_FUNC(pci->devfn));
}
static inline int ahc_get_pci_slot(ahc_dev_softc_t);
static inline int
ahc_get_pci_slot(ahc_dev_softc_t pci)
{
return (PCI_SLOT(pci->devfn));
}
static inline int ahc_get_pci_bus(ahc_dev_softc_t);
static inline int
ahc_get_pci_bus(ahc_dev_softc_t pci)
{
return (pci->bus->number);
}
#else
static inline int ahc_linux_pci_init(void) {
return 0;
}
static inline void ahc_linux_pci_exit(void) {
}
#endif
static inline void ahc_flush_device_writes(struct ahc_softc *);
static inline void
ahc_flush_device_writes(struct ahc_softc *ahc)
{
/* XXX Is this sufficient for all architectures??? */
ahc_inb(ahc, INTSTAT);
}
/**************************** Proc FS Support *********************************/
int ahc_proc_write_seeprom(struct Scsi_Host *, char *, int);
int ahc_linux_show_info(struct seq_file *, struct Scsi_Host *);
/*************************** Domain Validation ********************************/
/*********************** Transaction Access Wrappers *************************/
static inline void ahc_cmd_set_transaction_status(struct scsi_cmnd *, uint32_t);
static inline void ahc_set_transaction_status(struct scb *, uint32_t);
static inline void ahc_cmd_set_scsi_status(struct scsi_cmnd *, uint32_t);
static inline void ahc_set_scsi_status(struct scb *, uint32_t);
static inline uint32_t ahc_cmd_get_transaction_status(struct scsi_cmnd *cmd);
static inline uint32_t ahc_get_transaction_status(struct scb *);
static inline uint32_t ahc_cmd_get_scsi_status(struct scsi_cmnd *cmd);
static inline uint32_t ahc_get_scsi_status(struct scb *);
static inline void ahc_set_transaction_tag(struct scb *, int, u_int);
static inline u_long ahc_get_transfer_length(struct scb *);
static inline int ahc_get_transfer_dir(struct scb *);
static inline void ahc_set_residual(struct scb *, u_long);
static inline void ahc_set_sense_residual(struct scb *scb, u_long resid);
static inline u_long ahc_get_residual(struct scb *);
static inline u_long ahc_get_sense_residual(struct scb *);
static inline int ahc_perform_autosense(struct scb *);
static inline uint32_t ahc_get_sense_bufsize(struct ahc_softc *,
struct scb *);
static inline void ahc_notify_xfer_settings_change(struct ahc_softc *,
struct ahc_devinfo *);
static inline void ahc_platform_scb_free(struct ahc_softc *ahc,
struct scb *scb);
static inline void ahc_freeze_scb(struct scb *scb);
static inline
void ahc_cmd_set_transaction_status(struct scsi_cmnd *cmd, uint32_t status)
{
cmd->result &= ~(CAM_STATUS_MASK << 16);
cmd->result |= status << 16;
}
static inline
void ahc_set_transaction_status(struct scb *scb, uint32_t status)
{
ahc_cmd_set_transaction_status(scb->io_ctx,status);
}
static inline
void ahc_cmd_set_scsi_status(struct scsi_cmnd *cmd, uint32_t status)
{
cmd->result &= ~0xFFFF;
cmd->result |= status;
}
static inline
void ahc_set_scsi_status(struct scb *scb, uint32_t status)
{
ahc_cmd_set_scsi_status(scb->io_ctx, status);
}
static inline
uint32_t ahc_cmd_get_transaction_status(struct scsi_cmnd *cmd)
{
return ((cmd->result >> 16) & CAM_STATUS_MASK);
}
static inline
uint32_t ahc_get_transaction_status(struct scb *scb)
{
return (ahc_cmd_get_transaction_status(scb->io_ctx));
}
static inline
uint32_t ahc_cmd_get_scsi_status(struct scsi_cmnd *cmd)
{
return (cmd->result & 0xFFFF);
}
static inline
uint32_t ahc_get_scsi_status(struct scb *scb)
{
return (ahc_cmd_get_scsi_status(scb->io_ctx));
}
static inline
void ahc_set_transaction_tag(struct scb *scb, int enabled, u_int type)
{
/*
* Nothing to do for linux as the incoming transaction
* has no concept of tag/non tagged, etc.
*/
}
static inline
u_long ahc_get_transfer_length(struct scb *scb)
{
return (scb->platform_data->xfer_len);
}
static inline
int ahc_get_transfer_dir(struct scb *scb)
{
return (scb->io_ctx->sc_data_direction);
}
static inline
void ahc_set_residual(struct scb *scb, u_long resid)
{
scsi_set_resid(scb->io_ctx, resid);
}
static inline
void ahc_set_sense_residual(struct scb *scb, u_long resid)
{
scb->platform_data->sense_resid = resid;
}
static inline
u_long ahc_get_residual(struct scb *scb)
{
return scsi_get_resid(scb->io_ctx);
}
static inline
u_long ahc_get_sense_residual(struct scb *scb)
{
return (scb->platform_data->sense_resid);
}
static inline
int ahc_perform_autosense(struct scb *scb)
{
/*
* We always perform autosense in Linux.
* On other platforms this is set on a
* per-transaction basis.
*/
return (1);
}
static inline uint32_t
ahc_get_sense_bufsize(struct ahc_softc *ahc, struct scb *scb)
{
return (sizeof(struct scsi_sense_data));
}
static inline void
ahc_notify_xfer_settings_change(struct ahc_softc *ahc,
struct ahc_devinfo *devinfo)
{
/* Nothing to do here for linux */
}
static inline void
ahc_platform_scb_free(struct ahc_softc *ahc, struct scb *scb)
{
}
int ahc_platform_alloc(struct ahc_softc *ahc, void *platform_arg);
void ahc_platform_free(struct ahc_softc *ahc);
void ahc_platform_freeze_devq(struct ahc_softc *ahc, struct scb *scb);
static inline void
ahc_freeze_scb(struct scb *scb)
{
if ((scb->io_ctx->result & (CAM_DEV_QFRZN << 16)) == 0) {
scb->io_ctx->result |= CAM_DEV_QFRZN << 16;
scb->platform_data->dev->qfrozen++;
}
}
void ahc_platform_set_tags(struct ahc_softc *ahc, struct scsi_device *sdev,
struct ahc_devinfo *devinfo, ahc_queue_alg);
int ahc_platform_abort_scbs(struct ahc_softc *ahc, int target,
char channel, int lun, u_int tag,
role_t role, uint32_t status);
irqreturn_t
ahc_linux_isr(int irq, void *dev_id);
void ahc_platform_flushwork(struct ahc_softc *ahc);
void ahc_done(struct ahc_softc*, struct scb*);
void ahc_send_async(struct ahc_softc *, char channel,
u_int target, u_int lun, ac_code);
void ahc_print_path(struct ahc_softc *, struct scb *);
void ahc_platform_dump_card_state(struct ahc_softc *ahc);
#ifdef CONFIG_PCI
#define AHC_PCI_CONFIG 1
#else
#define AHC_PCI_CONFIG 0
#endif
#define bootverbose aic7xxx_verbose
extern u_int aic7xxx_verbose;
#endif /* _AIC7XXX_LINUX_H_ */

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/*
* Linux driver attachment glue for PCI based controllers.
*
* Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic7xxx_osm_pci.c#47 $
*/
#include "aic7xxx_osm.h"
#include "aic7xxx_pci.h"
/* Define the macro locally since it's different for different class of chips.
*/
#define ID(x) ID_C(x, PCI_CLASS_STORAGE_SCSI)
static const struct pci_device_id ahc_linux_pci_id_table[] = {
/* aic7850 based controllers */
ID(ID_AHA_2902_04_10_15_20C_30C),
/* aic7860 based controllers */
ID(ID_AHA_2930CU),
ID(ID_AHA_1480A & ID_DEV_VENDOR_MASK),
ID(ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK),
ID(ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK),
ID(ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK),
/* aic7870 based controllers */
ID(ID_AHA_2940),
ID(ID_AHA_3940),
ID(ID_AHA_398X),
ID(ID_AHA_2944),
ID(ID_AHA_3944),
ID(ID_AHA_4944),
/* aic7880 based controllers */
ID(ID_AHA_2940U & ID_DEV_VENDOR_MASK),
ID(ID_AHA_3940U & ID_DEV_VENDOR_MASK),
ID(ID_AHA_2944U & ID_DEV_VENDOR_MASK),
ID(ID_AHA_3944U & ID_DEV_VENDOR_MASK),
ID(ID_AHA_398XU & ID_DEV_VENDOR_MASK),
ID(ID_AHA_4944U & ID_DEV_VENDOR_MASK),
ID(ID_AHA_2930U & ID_DEV_VENDOR_MASK),
ID(ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK),
ID(ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK),
/* aic7890 based controllers */
ID(ID_AHA_2930U2),
ID(ID_AHA_2940U2B),
ID(ID_AHA_2940U2_OEM),
ID(ID_AHA_2940U2),
ID(ID_AHA_2950U2B),
ID16(ID_AIC7890_ARO & ID_AIC7895_ARO_MASK),
ID(ID_AAA_131U2),
/* aic7890 based controllers */
ID(ID_AHA_29160),
ID(ID_AHA_29160_CPQ),
ID(ID_AHA_29160N),
ID(ID_AHA_29160C),
ID(ID_AHA_29160B),
ID(ID_AHA_19160B),
ID(ID_AIC7892_ARO),
/* aic7892 based controllers */
ID(ID_AHA_2940U_DUAL),
ID(ID_AHA_3940AU),
ID(ID_AHA_3944AU),
ID(ID_AIC7895_ARO),
ID(ID_AHA_3950U2B_0),
ID(ID_AHA_3950U2B_1),
ID(ID_AHA_3950U2D_0),
ID(ID_AHA_3950U2D_1),
ID(ID_AIC7896_ARO),
/* aic7899 based controllers */
ID(ID_AHA_3960D),
ID(ID_AHA_3960D_CPQ),
ID(ID_AIC7899_ARO),
/* Generic chip probes for devices we don't know exactly. */
ID(ID_AIC7850 & ID_DEV_VENDOR_MASK),
ID(ID_AIC7855 & ID_DEV_VENDOR_MASK),
ID(ID_AIC7859 & ID_DEV_VENDOR_MASK),
ID(ID_AIC7860 & ID_DEV_VENDOR_MASK),
ID(ID_AIC7870 & ID_DEV_VENDOR_MASK),
ID(ID_AIC7880 & ID_DEV_VENDOR_MASK),
ID16(ID_AIC7890 & ID_9005_GENERIC_MASK),
ID16(ID_AIC7892 & ID_9005_GENERIC_MASK),
ID(ID_AIC7895 & ID_DEV_VENDOR_MASK),
ID16(ID_AIC7896 & ID_9005_GENERIC_MASK),
ID16(ID_AIC7899 & ID_9005_GENERIC_MASK),
ID(ID_AIC7810 & ID_DEV_VENDOR_MASK),
ID(ID_AIC7815 & ID_DEV_VENDOR_MASK),
{ 0 }
};
MODULE_DEVICE_TABLE(pci, ahc_linux_pci_id_table);
#ifdef CONFIG_PM
static int
ahc_linux_pci_dev_suspend(struct pci_dev *pdev, pm_message_t mesg)
{
struct ahc_softc *ahc = pci_get_drvdata(pdev);
int rc;
if ((rc = ahc_suspend(ahc)))
return rc;
pci_save_state(pdev);
pci_disable_device(pdev);
if (mesg.event & PM_EVENT_SLEEP)
pci_set_power_state(pdev, PCI_D3hot);
return rc;
}
static int
ahc_linux_pci_dev_resume(struct pci_dev *pdev)
{
struct ahc_softc *ahc = pci_get_drvdata(pdev);
int rc;
pci_set_power_state(pdev, PCI_D0);
pci_restore_state(pdev);
if ((rc = pci_enable_device(pdev))) {
dev_printk(KERN_ERR, &pdev->dev,
"failed to enable device after resume (%d)\n", rc);
return rc;
}
pci_set_master(pdev);
ahc_pci_resume(ahc);
return (ahc_resume(ahc));
}
#endif
static void
ahc_linux_pci_dev_remove(struct pci_dev *pdev)
{
struct ahc_softc *ahc = pci_get_drvdata(pdev);
u_long s;
if (ahc->platform_data && ahc->platform_data->host)
scsi_remove_host(ahc->platform_data->host);
ahc_lock(ahc, &s);
ahc_intr_enable(ahc, FALSE);
ahc_unlock(ahc, &s);
ahc_free(ahc);
}
static void
ahc_linux_pci_inherit_flags(struct ahc_softc *ahc)
{
struct pci_dev *pdev = ahc->dev_softc, *master_pdev;
unsigned int master_devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
master_pdev = pci_get_slot(pdev->bus, master_devfn);
if (master_pdev) {
struct ahc_softc *master = pci_get_drvdata(master_pdev);
if (master) {
ahc->flags &= ~AHC_BIOS_ENABLED;
ahc->flags |= master->flags & AHC_BIOS_ENABLED;
ahc->flags &= ~AHC_PRIMARY_CHANNEL;
ahc->flags |= master->flags & AHC_PRIMARY_CHANNEL;
} else
printk(KERN_ERR "aic7xxx: no multichannel peer found!\n");
pci_dev_put(master_pdev);
}
}
static int
ahc_linux_pci_dev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
char buf[80];
const uint64_t mask_39bit = 0x7FFFFFFFFFULL;
struct ahc_softc *ahc;
ahc_dev_softc_t pci;
const struct ahc_pci_identity *entry;
char *name;
int error;
struct device *dev = &pdev->dev;
pci = pdev;
entry = ahc_find_pci_device(pci);
if (entry == NULL)
return (-ENODEV);
/*
* Allocate a softc for this card and
* set it up for attachment by our
* common detect routine.
*/
sprintf(buf, "ahc_pci:%d:%d:%d",
ahc_get_pci_bus(pci),
ahc_get_pci_slot(pci),
ahc_get_pci_function(pci));
name = kstrdup(buf, GFP_ATOMIC);
if (name == NULL)
return (-ENOMEM);
ahc = ahc_alloc(NULL, name);
if (ahc == NULL)
return (-ENOMEM);
if (pci_enable_device(pdev)) {
ahc_free(ahc);
return (-ENODEV);
}
pci_set_master(pdev);
if (sizeof(dma_addr_t) > 4
&& ahc->features & AHC_LARGE_SCBS
&& dma_set_mask(dev, mask_39bit) == 0
&& dma_get_required_mask(dev) > DMA_BIT_MASK(32)) {
ahc->flags |= AHC_39BIT_ADDRESSING;
} else {
if (dma_set_mask(dev, DMA_BIT_MASK(32))) {
ahc_free(ahc);
printk(KERN_WARNING "aic7xxx: No suitable DMA available.\n");
return (-ENODEV);
}
}
ahc->dev_softc = pci;
error = ahc_pci_config(ahc, entry);
if (error != 0) {
ahc_free(ahc);
return (-error);
}
/*
* Second Function PCI devices need to inherit some
* settings from function 0.
*/
if ((ahc->features & AHC_MULTI_FUNC) && PCI_FUNC(pdev->devfn) != 0)
ahc_linux_pci_inherit_flags(ahc);
pci_set_drvdata(pdev, ahc);
ahc_linux_register_host(ahc, &aic7xxx_driver_template);
return (0);
}
/******************************* PCI Routines *********************************/
uint32_t
ahc_pci_read_config(ahc_dev_softc_t pci, int reg, int width)
{
switch (width) {
case 1:
{
uint8_t retval;
pci_read_config_byte(pci, reg, &retval);
return (retval);
}
case 2:
{
uint16_t retval;
pci_read_config_word(pci, reg, &retval);
return (retval);
}
case 4:
{
uint32_t retval;
pci_read_config_dword(pci, reg, &retval);
return (retval);
}
default:
panic("ahc_pci_read_config: Read size too big");
/* NOTREACHED */
return (0);
}
}
void
ahc_pci_write_config(ahc_dev_softc_t pci, int reg, uint32_t value, int width)
{
switch (width) {
case 1:
pci_write_config_byte(pci, reg, value);
break;
case 2:
pci_write_config_word(pci, reg, value);
break;
case 4:
pci_write_config_dword(pci, reg, value);
break;
default:
panic("ahc_pci_write_config: Write size too big");
/* NOTREACHED */
}
}
static struct pci_driver aic7xxx_pci_driver = {
.name = "aic7xxx",
.probe = ahc_linux_pci_dev_probe,
#ifdef CONFIG_PM
.suspend = ahc_linux_pci_dev_suspend,
.resume = ahc_linux_pci_dev_resume,
#endif
.remove = ahc_linux_pci_dev_remove,
.id_table = ahc_linux_pci_id_table
};
int
ahc_linux_pci_init(void)
{
return pci_register_driver(&aic7xxx_pci_driver);
}
void
ahc_linux_pci_exit(void)
{
pci_unregister_driver(&aic7xxx_pci_driver);
}
static int
ahc_linux_pci_reserve_io_region(struct ahc_softc *ahc, resource_size_t *base)
{
if (aic7xxx_allow_memio == 0)
return (ENOMEM);
*base = pci_resource_start(ahc->dev_softc, 0);
if (*base == 0)
return (ENOMEM);
if (!request_region(*base, 256, "aic7xxx"))
return (ENOMEM);
return (0);
}
static int
ahc_linux_pci_reserve_mem_region(struct ahc_softc *ahc,
resource_size_t *bus_addr,
uint8_t __iomem **maddr)
{
resource_size_t start;
int error;
error = 0;
start = pci_resource_start(ahc->dev_softc, 1);
if (start != 0) {
*bus_addr = start;
if (!request_mem_region(start, 0x1000, "aic7xxx"))
error = ENOMEM;
if (error == 0) {
*maddr = ioremap_nocache(start, 256);
if (*maddr == NULL) {
error = ENOMEM;
release_mem_region(start, 0x1000);
}
}
} else
error = ENOMEM;
return (error);
}
int
ahc_pci_map_registers(struct ahc_softc *ahc)
{
uint32_t command;
resource_size_t base;
uint8_t __iomem *maddr;
int error;
/*
* If its allowed, we prefer memory mapped access.
*/
command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, 4);
command &= ~(PCIM_CMD_PORTEN|PCIM_CMD_MEMEN);
base = 0;
maddr = NULL;
error = ahc_linux_pci_reserve_mem_region(ahc, &base, &maddr);
if (error == 0) {
ahc->platform_data->mem_busaddr = base;
ahc->tag = BUS_SPACE_MEMIO;
ahc->bsh.maddr = maddr;
ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
command | PCIM_CMD_MEMEN, 4);
/*
* Do a quick test to see if memory mapped
* I/O is functioning correctly.
*/
if (ahc_pci_test_register_access(ahc) != 0) {
printk("aic7xxx: PCI Device %d:%d:%d "
"failed memory mapped test. Using PIO.\n",
ahc_get_pci_bus(ahc->dev_softc),
ahc_get_pci_slot(ahc->dev_softc),
ahc_get_pci_function(ahc->dev_softc));
iounmap(maddr);
release_mem_region(ahc->platform_data->mem_busaddr,
0x1000);
ahc->bsh.maddr = NULL;
maddr = NULL;
} else
command |= PCIM_CMD_MEMEN;
} else {
printk("aic7xxx: PCI%d:%d:%d MEM region 0x%llx "
"unavailable. Cannot memory map device.\n",
ahc_get_pci_bus(ahc->dev_softc),
ahc_get_pci_slot(ahc->dev_softc),
ahc_get_pci_function(ahc->dev_softc),
(unsigned long long)base);
}
/*
* We always prefer memory mapped access.
*/
if (maddr == NULL) {
error = ahc_linux_pci_reserve_io_region(ahc, &base);
if (error == 0) {
ahc->tag = BUS_SPACE_PIO;
ahc->bsh.ioport = (u_long)base;
command |= PCIM_CMD_PORTEN;
} else {
printk("aic7xxx: PCI%d:%d:%d IO region 0x%llx[0..255] "
"unavailable. Cannot map device.\n",
ahc_get_pci_bus(ahc->dev_softc),
ahc_get_pci_slot(ahc->dev_softc),
ahc_get_pci_function(ahc->dev_softc),
(unsigned long long)base);
}
}
ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, 4);
return (error);
}
int
ahc_pci_map_int(struct ahc_softc *ahc)
{
int error;
error = request_irq(ahc->dev_softc->irq, ahc_linux_isr,
IRQF_SHARED, "aic7xxx", ahc);
if (error == 0)
ahc->platform_data->irq = ahc->dev_softc->irq;
return (-error);
}

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/*
* Adaptec AIC7xxx device driver for Linux.
*
* Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id$
*
*/
#ifndef _AIC7XXX_PCI_H_
#define _AIC7XXX_PCI_H_
#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
#define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
#define ID_9005_SISL_MASK 0x000FFFFF00000000ull
#define ID_9005_SISL_ID 0x0005900500000000ull
#define ID_AIC7850 0x5078900400000000ull
#define ID_AHA_2902_04_10_15_20C_30C 0x5078900478509004ull
#define ID_AIC7855 0x5578900400000000ull
#define ID_AIC7859 0x3860900400000000ull
#define ID_AHA_2930CU 0x3860900438699004ull
#define ID_AIC7860 0x6078900400000000ull
#define ID_AIC7860C 0x6078900478609004ull
#define ID_AHA_1480A 0x6075900400000000ull
#define ID_AHA_2940AU_0 0x6178900400000000ull
#define ID_AHA_2940AU_1 0x6178900478619004ull
#define ID_AHA_2940AU_CN 0x2178900478219004ull
#define ID_AHA_2930C_VAR 0x6038900438689004ull
#define ID_AIC7870 0x7078900400000000ull
#define ID_AHA_2940 0x7178900400000000ull
#define ID_AHA_3940 0x7278900400000000ull
#define ID_AHA_398X 0x7378900400000000ull
#define ID_AHA_2944 0x7478900400000000ull
#define ID_AHA_3944 0x7578900400000000ull
#define ID_AHA_4944 0x7678900400000000ull
#define ID_AIC7880 0x8078900400000000ull
#define ID_AIC7880_B 0x8078900478809004ull
#define ID_AHA_2940U 0x8178900400000000ull
#define ID_AHA_3940U 0x8278900400000000ull
#define ID_AHA_2944U 0x8478900400000000ull
#define ID_AHA_3944U 0x8578900400000000ull
#define ID_AHA_398XU 0x8378900400000000ull
#define ID_AHA_4944U 0x8678900400000000ull
#define ID_AHA_2940UB 0x8178900478819004ull
#define ID_AHA_2930U 0x8878900478889004ull
#define ID_AHA_2940U_PRO 0x8778900478879004ull
#define ID_AHA_2940U_CN 0x0078900478009004ull
#define ID_AIC7895 0x7895900478959004ull
#define ID_AIC7895_ARO 0x7890900478939004ull
#define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull
#define ID_AHA_2940U_DUAL 0x7895900478919004ull
#define ID_AHA_3940AU 0x7895900478929004ull
#define ID_AHA_3944AU 0x7895900478949004ull
#define ID_AIC7890 0x001F9005000F9005ull
#define ID_AIC7890_ARO 0x00139005000F9005ull
#define ID_AAA_131U2 0x0013900500039005ull
#define ID_AHA_2930U2 0x0011900501819005ull
#define ID_AHA_2940U2B 0x00109005A1009005ull
#define ID_AHA_2940U2_OEM 0x0010900521809005ull
#define ID_AHA_2940U2 0x00109005A1809005ull
#define ID_AHA_2950U2B 0x00109005E1009005ull
#define ID_AIC7892 0x008F9005FFFF9005ull
#define ID_AIC7892_ARO 0x00839005FFFF9005ull
#define ID_AHA_29160 0x00809005E2A09005ull
#define ID_AHA_29160_CPQ 0x00809005E2A00E11ull
#define ID_AHA_29160N 0x0080900562A09005ull
#define ID_AHA_29160C 0x0080900562209005ull
#define ID_AHA_29160B 0x00809005E2209005ull
#define ID_AHA_19160B 0x0081900562A19005ull
#define ID_AHA_2915_30LP 0x0082900502109005ull
#define ID_AIC7896 0x005F9005FFFF9005ull
#define ID_AIC7896_ARO 0x00539005FFFF9005ull
#define ID_AHA_3950U2B_0 0x00509005FFFF9005ull
#define ID_AHA_3950U2B_1 0x00509005F5009005ull
#define ID_AHA_3950U2D_0 0x00519005FFFF9005ull
#define ID_AHA_3950U2D_1 0x00519005B5009005ull
#define ID_AIC7899 0x00CF9005FFFF9005ull
#define ID_AIC7899_ARO 0x00C39005FFFF9005ull
#define ID_AHA_3960D 0x00C09005F6209005ull
#define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull
#define ID_AIC7810 0x1078900400000000ull
#define ID_AIC7815 0x7815900400000000ull
#endif /* _AIC7XXX_PCI_H_ */

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/*
* Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* String handling code courtesy of Gerard Roudier's <groudier@club-internet.fr>
* sym driver.
*
* $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic7xxx_proc.c#29 $
*/
#include "aic7xxx_osm.h"
#include "aic7xxx_inline.h"
#include "aic7xxx_93cx6.h"
static void ahc_dump_target_state(struct ahc_softc *ahc,
struct seq_file *m,
u_int our_id, char channel,
u_int target_id, u_int target_offset);
static void ahc_dump_device_state(struct seq_file *m,
struct scsi_device *dev);
/*
* Table of syncrates that don't follow the "divisible by 4"
* rule. This table will be expanded in future SCSI specs.
*/
static const struct {
u_int period_factor;
u_int period; /* in 100ths of ns */
} scsi_syncrates[] = {
{ 0x08, 625 }, /* FAST-160 */
{ 0x09, 1250 }, /* FAST-80 */
{ 0x0a, 2500 }, /* FAST-40 40MHz */
{ 0x0b, 3030 }, /* FAST-40 33MHz */
{ 0x0c, 5000 } /* FAST-20 */
};
/*
* Return the frequency in kHz corresponding to the given
* sync period factor.
*/
static u_int
ahc_calc_syncsrate(u_int period_factor)
{
int i;
/* See if the period is in the "exception" table */
for (i = 0; i < ARRAY_SIZE(scsi_syncrates); i++) {
if (period_factor == scsi_syncrates[i].period_factor) {
/* Period in kHz */
return (100000000 / scsi_syncrates[i].period);
}
}
/*
* Wasn't in the table, so use the standard
* 4 times conversion.
*/
return (10000000 / (period_factor * 4 * 10));
}
static void
ahc_format_transinfo(struct seq_file *m, struct ahc_transinfo *tinfo)
{
u_int speed;
u_int freq;
u_int mb;
speed = 3300;
freq = 0;
if (tinfo->offset != 0) {
freq = ahc_calc_syncsrate(tinfo->period);
speed = freq;
}
speed *= (0x01 << tinfo->width);
mb = speed / 1000;
if (mb > 0)
seq_printf(m, "%d.%03dMB/s transfers", mb, speed % 1000);
else
seq_printf(m, "%dKB/s transfers", speed);
if (freq != 0) {
seq_printf(m, " (%d.%03dMHz%s, offset %d",
freq / 1000, freq % 1000,
(tinfo->ppr_options & MSG_EXT_PPR_DT_REQ) != 0
? " DT" : "", tinfo->offset);
}
if (tinfo->width > 0) {
if (freq != 0) {
seq_printf(m, ", ");
} else {
seq_printf(m, " (");
}
seq_printf(m, "%dbit)", 8 * (0x01 << tinfo->width));
} else if (freq != 0) {
seq_printf(m, ")");
}
seq_printf(m, "\n");
}
static void
ahc_dump_target_state(struct ahc_softc *ahc, struct seq_file *m,
u_int our_id, char channel, u_int target_id,
u_int target_offset)
{
struct scsi_target *starget;
struct ahc_initiator_tinfo *tinfo;
struct ahc_tmode_tstate *tstate;
int lun;
tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
target_id, &tstate);
if ((ahc->features & AHC_TWIN) != 0)
seq_printf(m, "Channel %c ", channel);
seq_printf(m, "Target %d Negotiation Settings\n", target_id);
seq_printf(m, "\tUser: ");
ahc_format_transinfo(m, &tinfo->user);
starget = ahc->platform_data->starget[target_offset];
if (!starget)
return;
seq_printf(m, "\tGoal: ");
ahc_format_transinfo(m, &tinfo->goal);
seq_printf(m, "\tCurr: ");
ahc_format_transinfo(m, &tinfo->curr);
for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
struct scsi_device *sdev;
sdev = scsi_device_lookup_by_target(starget, lun);
if (sdev == NULL)
continue;
ahc_dump_device_state(m, sdev);
}
}
static void
ahc_dump_device_state(struct seq_file *m, struct scsi_device *sdev)
{
struct ahc_linux_device *dev = scsi_transport_device_data(sdev);
seq_printf(m, "\tChannel %c Target %d Lun %d Settings\n",
sdev->sdev_target->channel + 'A',
sdev->sdev_target->id, (u8)sdev->lun);
seq_printf(m, "\t\tCommands Queued %ld\n", dev->commands_issued);
seq_printf(m, "\t\tCommands Active %d\n", dev->active);
seq_printf(m, "\t\tCommand Openings %d\n", dev->openings);
seq_printf(m, "\t\tMax Tagged Openings %d\n", dev->maxtags);
seq_printf(m, "\t\tDevice Queue Frozen Count %d\n", dev->qfrozen);
}
int
ahc_proc_write_seeprom(struct Scsi_Host *shost, char *buffer, int length)
{
struct ahc_softc *ahc = *(struct ahc_softc **)shost->hostdata;
struct seeprom_descriptor sd;
int have_seeprom;
u_long s;
int paused;
int written;
/* Default to failure. */
written = -EINVAL;
ahc_lock(ahc, &s);
paused = ahc_is_paused(ahc);
if (!paused)
ahc_pause(ahc);
if (length != sizeof(struct seeprom_config)) {
printk("ahc_proc_write_seeprom: incorrect buffer size\n");
goto done;
}
have_seeprom = ahc_verify_cksum((struct seeprom_config*)buffer);
if (have_seeprom == 0) {
printk("ahc_proc_write_seeprom: cksum verification failed\n");
goto done;
}
sd.sd_ahc = ahc;
#if AHC_PCI_CONFIG > 0
if ((ahc->chip & AHC_PCI) != 0) {
sd.sd_control_offset = SEECTL;
sd.sd_status_offset = SEECTL;
sd.sd_dataout_offset = SEECTL;
if (ahc->flags & AHC_LARGE_SEEPROM)
sd.sd_chip = C56_66;
else
sd.sd_chip = C46;
sd.sd_MS = SEEMS;
sd.sd_RDY = SEERDY;
sd.sd_CS = SEECS;
sd.sd_CK = SEECK;
sd.sd_DO = SEEDO;
sd.sd_DI = SEEDI;
have_seeprom = ahc_acquire_seeprom(ahc, &sd);
} else
#endif
if ((ahc->chip & AHC_VL) != 0) {
sd.sd_control_offset = SEECTL_2840;
sd.sd_status_offset = STATUS_2840;
sd.sd_dataout_offset = STATUS_2840;
sd.sd_chip = C46;
sd.sd_MS = 0;
sd.sd_RDY = EEPROM_TF;
sd.sd_CS = CS_2840;
sd.sd_CK = CK_2840;
sd.sd_DO = DO_2840;
sd.sd_DI = DI_2840;
have_seeprom = TRUE;
} else {
printk("ahc_proc_write_seeprom: unsupported adapter type\n");
goto done;
}
if (!have_seeprom) {
printk("ahc_proc_write_seeprom: No Serial EEPROM\n");
goto done;
} else {
u_int start_addr;
if (ahc->seep_config == NULL) {
ahc->seep_config = kmalloc(sizeof(*ahc->seep_config), GFP_ATOMIC);
if (ahc->seep_config == NULL) {
printk("aic7xxx: Unable to allocate serial "
"eeprom buffer. Write failing\n");
goto done;
}
}
printk("aic7xxx: Writing Serial EEPROM\n");
start_addr = 32 * (ahc->channel - 'A');
ahc_write_seeprom(&sd, (u_int16_t *)buffer, start_addr,
sizeof(struct seeprom_config)/2);
ahc_read_seeprom(&sd, (uint16_t *)ahc->seep_config,
start_addr, sizeof(struct seeprom_config)/2);
#if AHC_PCI_CONFIG > 0
if ((ahc->chip & AHC_VL) == 0)
ahc_release_seeprom(&sd);
#endif
written = length;
}
done:
if (!paused)
ahc_unpause(ahc);
ahc_unlock(ahc, &s);
return (written);
}
/*
* Return information to handle /proc support for the driver.
*/
int
ahc_linux_show_info(struct seq_file *m, struct Scsi_Host *shost)
{
struct ahc_softc *ahc = *(struct ahc_softc **)shost->hostdata;
char ahc_info[256];
u_int max_targ;
u_int i;
seq_printf(m, "Adaptec AIC7xxx driver version: %s\n",
AIC7XXX_DRIVER_VERSION);
seq_printf(m, "%s\n", ahc->description);
ahc_controller_info(ahc, ahc_info);
seq_printf(m, "%s\n", ahc_info);
seq_printf(m, "Allocated SCBs: %d, SG List Length: %d\n\n",
ahc->scb_data->numscbs, AHC_NSEG);
if (ahc->seep_config == NULL)
seq_printf(m, "No Serial EEPROM\n");
else {
seq_printf(m, "Serial EEPROM:\n");
for (i = 0; i < sizeof(*ahc->seep_config)/2; i++) {
if (((i % 8) == 0) && (i != 0)) {
seq_printf(m, "\n");
}
seq_printf(m, "0x%.4x ",
((uint16_t*)ahc->seep_config)[i]);
}
seq_printf(m, "\n");
}
seq_printf(m, "\n");
max_targ = 16;
if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
max_targ = 8;
for (i = 0; i < max_targ; i++) {
u_int our_id;
u_int target_id;
char channel;
channel = 'A';
our_id = ahc->our_id;
target_id = i;
if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
channel = 'B';
our_id = ahc->our_id_b;
target_id = i % 8;
}
ahc_dump_target_state(ahc, m, our_id,
channel, target_id, i);
}
return 0;
}

912
drivers/scsi/aic7xxx/aic7xxx_reg.h_shipped Normal file
View file

@ -0,0 +1,912 @@
/*
* DO NOT EDIT - This file is automatically generated
* from the following source files:
*
* $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $
* $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $
*/
typedef int (ahc_reg_print_t)(u_int, u_int *, u_int);
typedef struct ahc_reg_parse_entry {
char *name;
uint8_t value;
uint8_t mask;
} ahc_reg_parse_entry_t;
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_scsiseq_print;
#else
#define ahc_scsiseq_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SCSISEQ", 0x00, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_sxfrctl0_print;
#else
#define ahc_sxfrctl0_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SXFRCTL0", 0x01, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_scsisigi_print;
#else
#define ahc_scsisigi_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SCSISIGI", 0x03, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_scsirate_print;
#else
#define ahc_scsirate_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SCSIRATE", 0x04, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_sstat0_print;
#else
#define ahc_sstat0_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SSTAT0", 0x0b, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_sstat1_print;
#else
#define ahc_sstat1_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SSTAT1", 0x0c, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_sstat2_print;
#else
#define ahc_sstat2_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SSTAT2", 0x0d, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_sstat3_print;
#else
#define ahc_sstat3_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SSTAT3", 0x0e, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_simode0_print;
#else
#define ahc_simode0_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SIMODE0", 0x10, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_simode1_print;
#else
#define ahc_simode1_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SIMODE1", 0x11, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_scsibusl_print;
#else
#define ahc_scsibusl_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SCSIBUSL", 0x12, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_sblkctl_print;
#else
#define ahc_sblkctl_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SBLKCTL", 0x1f, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_seq_flags_print;
#else
#define ahc_seq_flags_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SEQ_FLAGS", 0x3c, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_lastphase_print;
#else
#define ahc_lastphase_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "LASTPHASE", 0x3f, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_seqctl_print;
#else
#define ahc_seqctl_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SEQCTL", 0x60, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_sram_base_print;
#else
#define ahc_sram_base_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SRAM_BASE", 0x70, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_error_print;
#else
#define ahc_error_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "ERROR", 0x92, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_dfcntrl_print;
#else
#define ahc_dfcntrl_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "DFCNTRL", 0x93, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_dfstatus_print;
#else
#define ahc_dfstatus_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "DFSTATUS", 0x94, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_scsiphase_print;
#else
#define ahc_scsiphase_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SCSIPHASE", 0x9e, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_scb_base_print;
#else
#define ahc_scb_base_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SCB_BASE", 0xa0, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_scb_control_print;
#else
#define ahc_scb_control_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SCB_CONTROL", 0xb8, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_scb_scsiid_print;
#else
#define ahc_scb_scsiid_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SCB_SCSIID", 0xb9, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_scb_lun_print;
#else
#define ahc_scb_lun_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SCB_LUN", 0xba, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_scb_tag_print;
#else
#define ahc_scb_tag_print(regvalue, cur_col, wrap) \
ahc_print_register(NULL, 0, "SCB_TAG", 0xbb, regvalue, cur_col, wrap)
#endif
#define SCSISEQ 0x00
#define TEMODE 0x80
#define SCSIRSTO 0x01
#define SXFRCTL0 0x01
#define DFON 0x80
#define DFPEXP 0x40
#define FAST20 0x20
#define CLRSTCNT 0x10
#define SPIOEN 0x08
#define SCAMEN 0x04
#define CLRCHN 0x02
#define SXFRCTL1 0x02
#define STIMESEL 0x18
#define BITBUCKET 0x80
#define SWRAPEN 0x40
#define ENSTIMER 0x04
#define ACTNEGEN 0x02
#define STPWEN 0x01
#define SCSISIGO 0x03
#define CDO 0x80
#define IOO 0x40
#define MSGO 0x20
#define ATNO 0x10
#define SELO 0x08
#define BSYO 0x04
#define REQO 0x02
#define ACKO 0x01
#define SCSISIGI 0x03
#define P_DATAIN_DT 0x60
#define P_DATAOUT_DT 0x20
#define ATNI 0x10
#define SELI 0x08
#define BSYI 0x04
#define REQI 0x02
#define ACKI 0x01
#define SCSIRATE 0x04
#define SXFR 0x70
#define SOFS 0x0f
#define SXFR_ULTRA2 0x0f
#define WIDEXFER 0x80
#define ENABLE_CRC 0x40
#define SINGLE_EDGE 0x10
#define SCSIID 0x05
#define SCSIOFFSET 0x05
#define SOFS_ULTRA2 0x7f
#define SCSIDATL 0x06
#define SCSIDATH 0x07
#define STCNT 0x08
#define OPTIONMODE 0x08
#define OPTIONMODE_DEFAULTS 0x03
#define AUTORATEEN 0x80
#define AUTOACKEN 0x40
#define ATNMGMNTEN 0x20
#define BUSFREEREV 0x10
#define EXPPHASEDIS 0x08
#define SCSIDATL_IMGEN 0x04
#define AUTO_MSGOUT_DE 0x02
#define DIS_MSGIN_DUALEDGE 0x01
#define TARGCRCCNT 0x0a
#define CLRSINT0 0x0b
#define CLRSELDO 0x40
#define CLRSELDI 0x20
#define CLRSELINGO 0x10
#define CLRIOERR 0x08
#define CLRSWRAP 0x08
#define CLRSPIORDY 0x02
#define SSTAT0 0x0b
#define TARGET 0x80
#define SELDO 0x40
#define SELDI 0x20
#define SELINGO 0x10
#define SWRAP 0x08
#define IOERR 0x08
#define SDONE 0x04
#define SPIORDY 0x02
#define DMADONE 0x01
#define CLRSINT1 0x0c
#define CLRSELTIMEO 0x80
#define CLRATNO 0x40
#define CLRSCSIRSTI 0x20
#define CLRBUSFREE 0x08
#define CLRSCSIPERR 0x04
#define CLRPHASECHG 0x02
#define CLRREQINIT 0x01
#define SSTAT1 0x0c
#define SELTO 0x80
#define ATNTARG 0x40
#define SCSIRSTI 0x20
#define PHASEMIS 0x10
#define BUSFREE 0x08
#define SCSIPERR 0x04
#define PHASECHG 0x02
#define REQINIT 0x01
#define SSTAT2 0x0d
#define SFCNT 0x1f
#define OVERRUN 0x80
#define SHVALID 0x40
#define EXP_ACTIVE 0x10
#define CRCVALERR 0x08
#define CRCENDERR 0x04
#define CRCREQERR 0x02
#define DUAL_EDGE_ERR 0x01
#define SSTAT3 0x0e
#define SCSICNT 0xf0
#define U2OFFCNT 0x7f
#define OFFCNT 0x0f
#define SCSIID_ULTRA2 0x0f
#define SIMODE0 0x10
#define ENSELDO 0x40
#define ENSELDI 0x20
#define ENSELINGO 0x10
#define ENIOERR 0x08
#define ENSWRAP 0x08
#define ENSDONE 0x04
#define ENSPIORDY 0x02
#define ENDMADONE 0x01
#define SIMODE1 0x11
#define ENSELTIMO 0x80
#define ENATNTARG 0x40
#define ENSCSIRST 0x20
#define ENPHASEMIS 0x10
#define ENBUSFREE 0x08
#define ENSCSIPERR 0x04
#define ENPHASECHG 0x02
#define ENREQINIT 0x01
#define SCSIBUSL 0x12
#define SCSIBUSH 0x13
#define SXFRCTL2 0x13
#define ASYNC_SETUP 0x07
#define AUTORSTDIS 0x10
#define CMDDMAEN 0x08
#define SHADDR 0x14
#define SELTIMER 0x18
#define TARGIDIN 0x18
#define STAGE6 0x20
#define STAGE5 0x10
#define STAGE4 0x08
#define STAGE3 0x04
#define STAGE2 0x02
#define STAGE1 0x01
#define SELID 0x19
#define SELID_MASK 0xf0
#define ONEBIT 0x08
#define SCAMCTL 0x1a
#define SCAMLVL 0x03
#define ENSCAMSELO 0x80
#define CLRSCAMSELID 0x40
#define ALTSTIM 0x20
#define DFLTTID 0x10
#define TARGID 0x1b
#define SPIOCAP 0x1b
#define SOFT1 0x80
#define SOFT0 0x40
#define SOFTCMDEN 0x20
#define EXT_BRDCTL 0x10
#define SEEPROM 0x08
#define EEPROM 0x04
#define ROM 0x02
#define SSPIOCPS 0x01
#define BRDCTL 0x1d
#define BRDDAT7 0x80
#define BRDDAT6 0x40
#define BRDDAT5 0x20
#define BRDDAT4 0x10
#define BRDSTB 0x10
#define BRDDAT3 0x08
#define BRDCS 0x08
#define BRDDAT2 0x04
#define BRDRW 0x04
#define BRDRW_ULTRA2 0x02
#define BRDCTL1 0x02
#define BRDCTL0 0x01
#define BRDSTB_ULTRA2 0x01
#define SEECTL 0x1e
#define EXTARBACK 0x80
#define EXTARBREQ 0x40
#define SEEMS 0x20
#define SEERDY 0x10
#define SEECS 0x08
#define SEECK 0x04
#define SEEDO 0x02
#define SEEDI 0x01
#define SBLKCTL 0x1f
#define DIAGLEDEN 0x80
#define DIAGLEDON 0x40
#define AUTOFLUSHDIS 0x20
#define ENAB40 0x08
#define SELBUSB 0x08
#define ENAB20 0x04
#define SELWIDE 0x02
#define XCVR 0x01
#define BUSY_TARGETS 0x20
#define TARG_SCSIRATE 0x20
#define ULTRA_ENB 0x30
#define CMDSIZE_TABLE 0x30
#define DISC_DSB 0x32
#define CMDSIZE_TABLE_TAIL 0x34
#define MWI_RESIDUAL 0x38
#define NEXT_QUEUED_SCB 0x39
#define MSG_OUT 0x3a
#define DMAPARAMS 0x3b
#define PRELOADEN 0x80
#define WIDEODD 0x40
#define SCSIEN 0x20
#define SDMAEN 0x10
#define SDMAENACK 0x10
#define HDMAEN 0x08
#define HDMAENACK 0x08
#define DIRECTION 0x04
#define FIFOFLUSH 0x02
#define FIFORESET 0x01
#define SEQ_FLAGS 0x3c
#define NOT_IDENTIFIED 0x80
#define NO_CDB_SENT 0x40
#define TARGET_CMD_IS_TAGGED 0x40
#define DPHASE 0x20
#define TARG_CMD_PENDING 0x10
#define CMDPHASE_PENDING 0x08
#define DPHASE_PENDING 0x04
#define SPHASE_PENDING 0x02
#define NO_DISCONNECT 0x01
#define SAVED_SCSIID 0x3d
#define SAVED_LUN 0x3e
#define LASTPHASE 0x3f
#define P_MESGIN 0xe0
#define PHASE_MASK 0xe0
#define P_STATUS 0xc0
#define P_MESGOUT 0xa0
#define P_COMMAND 0x80
#define P_DATAIN 0x40
#define P_BUSFREE 0x01
#define P_DATAOUT 0x00
#define CDI 0x80
#define IOI 0x40
#define MSGI 0x20
#define WAITING_SCBH 0x40
#define DISCONNECTED_SCBH 0x41
#define FREE_SCBH 0x42
#define COMPLETE_SCBH 0x43
#define HSCB_ADDR 0x44
#define SHARED_DATA_ADDR 0x48
#define KERNEL_QINPOS 0x4c
#define QINPOS 0x4d
#define QOUTPOS 0x4e
#define KERNEL_TQINPOS 0x4f
#define TQINPOS 0x50
#define ARG_1 0x51
#define RETURN_1 0x51
#define SEND_MSG 0x80
#define SEND_SENSE 0x40
#define SEND_REJ 0x20
#define MSGOUT_PHASEMIS 0x10
#define EXIT_MSG_LOOP 0x08
#define CONT_MSG_LOOP 0x04
#define CONT_TARG_SESSION 0x02
#define ARG_2 0x52
#define RETURN_2 0x52
#define LAST_MSG 0x53
#define TARG_IMMEDIATE_SCB 0x53
#define SCSISEQ_TEMPLATE 0x54
#define ENSELO 0x40
#define ENSELI 0x20
#define ENRSELI 0x10
#define ENAUTOATNO 0x08
#define ENAUTOATNI 0x04
#define ENAUTOATNP 0x02
#define HA_274_BIOSGLOBAL 0x56
#define INITIATOR_TAG 0x56
#define HA_274_EXTENDED_TRANS 0x01
#define SEQ_FLAGS2 0x57
#define TARGET_MSG_PENDING 0x02
#define SCB_DMA 0x01
#define SCSICONF 0x5a
#define HWSCSIID 0x0f
#define HSCSIID 0x07
#define TERM_ENB 0x80
#define RESET_SCSI 0x40
#define ENSPCHK 0x20
#define INTDEF 0x5c
#define VECTOR 0x0f
#define EDGE_TRIG 0x80
#define HOSTCONF 0x5d
#define HA_274_BIOSCTRL 0x5f
#define BIOSDISABLED 0x30
#define BIOSMODE 0x30
#define CHANNEL_B_PRIMARY 0x08
#define SEQCTL 0x60
#define PERRORDIS 0x80
#define PAUSEDIS 0x40
#define FAILDIS 0x20
#define FASTMODE 0x10
#define BRKADRINTEN 0x08
#define STEP 0x04
#define SEQRESET 0x02
#define LOADRAM 0x01
#define SEQRAM 0x61
#define SEQADDR0 0x62
#define SEQADDR1 0x63
#define SEQADDR1_MASK 0x01
#define ACCUM 0x64
#define SINDEX 0x65
#define DINDEX 0x66
#define ALLONES 0x69
#define ALLZEROS 0x6a
#define NONE 0x6a
#define FLAGS 0x6b
#define ZERO 0x02
#define CARRY 0x01
#define SINDIR 0x6c
#define DINDIR 0x6d
#define FUNCTION1 0x6e
#define STACK 0x6f
#define TARG_OFFSET 0x70
#define SRAM_BASE 0x70
#define BCTL 0x84
#define ACE 0x08
#define ENABLE 0x01
#define DSCOMMAND0 0x84
#define CACHETHEN 0x80
#define DPARCKEN 0x40
#define MPARCKEN 0x20
#define EXTREQLCK 0x10
#define INTSCBRAMSEL 0x08
#define RAMPS 0x04
#define USCBSIZE32 0x02
#define CIOPARCKEN 0x01
#define BUSTIME 0x85
#define BOFF 0xf0
#define BON 0x0f
#define DSCOMMAND1 0x85
#define DSLATT 0xfc
#define HADDLDSEL1 0x02
#define HADDLDSEL0 0x01
#define BUSSPD 0x86
#define DFTHRSH 0xc0
#define DFTHRSH_75 0x80
#define STBOFF 0x38
#define STBON 0x07
#define HS_MAILBOX 0x86
#define HOST_MAILBOX 0xf0
#define HOST_TQINPOS 0x80
#define SEQ_MAILBOX 0x0f
#define DSPCISTATUS 0x86
#define DFTHRSH_100 0xc0
#define HCNTRL 0x87
#define POWRDN 0x40
#define SWINT 0x10
#define IRQMS 0x08
#define PAUSE 0x04
#define INTEN 0x02
#define CHIPRST 0x01
#define CHIPRSTACK 0x01
#define HADDR 0x88
#define HCNT 0x8c
#define SCBPTR 0x90
#define INTSTAT 0x91
#define SEQINT_MASK 0xf1
#define OUT_OF_RANGE 0xe1
#define NO_FREE_SCB 0xd1
#define SCB_MISMATCH 0xc1
#define MISSED_BUSFREE 0xb1
#define MKMSG_FAILED 0xa1
#define DATA_OVERRUN 0x91
#define PERR_DETECTED 0x81
#define BAD_STATUS 0x71
#define HOST_MSG_LOOP 0x61
#define PDATA_REINIT 0x51
#define IGN_WIDE_RES 0x41
#define NO_MATCH 0x31
#define PROTO_VIOLATION 0x21
#define SEND_REJECT 0x11
#define INT_PEND 0x0f
#define BAD_PHASE 0x01
#define BRKADRINT 0x08
#define SCSIINT 0x04
#define CMDCMPLT 0x02
#define SEQINT 0x01
#define CLRINT 0x92
#define CLRPARERR 0x10
#define CLRBRKADRINT 0x08
#define CLRSCSIINT 0x04
#define CLRCMDINT 0x02
#define CLRSEQINT 0x01
#define ERROR 0x92
#define CIOPARERR 0x80
#define PCIERRSTAT 0x40
#define MPARERR 0x20
#define DPARERR 0x10
#define SQPARERR 0x08
#define ILLOPCODE 0x04
#define ILLSADDR 0x02
#define ILLHADDR 0x01
#define DFCNTRL 0x93
#define DFSTATUS 0x94
#define PRELOAD_AVAIL 0x80
#define DFCACHETH 0x40
#define FIFOQWDEMP 0x20
#define MREQPEND 0x10
#define HDONE 0x08
#define DFTHRESH 0x04
#define FIFOFULL 0x02
#define FIFOEMP 0x01
#define DFWADDR 0x95
#define DFRADDR 0x97
#define DFDAT 0x99
#define SCBCNT 0x9a
#define SCBCNT_MASK 0x1f
#define SCBAUTO 0x80
#define QINFIFO 0x9b
#define QINCNT 0x9c
#define QOUTFIFO 0x9d
#define CRCCONTROL1 0x9d
#define CRCONSEEN 0x80
#define CRCVALCHKEN 0x40
#define CRCENDCHKEN 0x20
#define CRCREQCHKEN 0x10
#define TARGCRCENDEN 0x08
#define TARGCRCCNTEN 0x04
#define QOUTCNT 0x9e
#define SCSIPHASE 0x9e
#define DATA_PHASE_MASK 0x03
#define STATUS_PHASE 0x20
#define COMMAND_PHASE 0x10
#define MSG_IN_PHASE 0x08
#define MSG_OUT_PHASE 0x04
#define DATA_IN_PHASE 0x02
#define DATA_OUT_PHASE 0x01
#define SFUNCT 0x9f
#define ALT_MODE 0x80
#define SCB_BASE 0xa0
#define SCB_CDB_PTR 0xa0
#define SCB_RESIDUAL_DATACNT 0xa0
#define SCB_CDB_STORE 0xa0
#define SCB_RESIDUAL_SGPTR 0xa4
#define SCB_SCSI_STATUS 0xa8
#define SCB_TARGET_PHASES 0xa9
#define SCB_TARGET_DATA_DIR 0xaa
#define SCB_TARGET_ITAG 0xab
#define SCB_DATAPTR 0xac
#define SCB_DATACNT 0xb0
#define SG_HIGH_ADDR_BITS 0x7f
#define SG_LAST_SEG 0x80
#define SCB_SGPTR 0xb4
#define SG_RESID_VALID 0x04
#define SG_FULL_RESID 0x02
#define SG_LIST_NULL 0x01
#define SCB_CONTROL 0xb8
#define SCB_TAG_TYPE 0x03
#define STATUS_RCVD 0x80
#define TARGET_SCB 0x80
#define DISCENB 0x40
#define TAG_ENB 0x20
#define MK_MESSAGE 0x10
#define ULTRAENB 0x08
#define DISCONNECTED 0x04
#define SCB_SCSIID 0xb9
#define TID 0xf0
#define TWIN_TID 0x70
#define OID 0x0f
#define TWIN_CHNLB 0x80
#define SCB_LUN 0xba
#define LID 0x3f
#define SCB_XFERLEN_ODD 0x80
#define SCB_TAG 0xbb
#define SCB_CDB_LEN 0xbc
#define SCB_SCSIRATE 0xbd
#define SCB_SCSIOFFSET 0xbe
#define SCB_NEXT 0xbf
#define SCB_64_SPARE 0xc0
#define SEECTL_2840 0xc0
#define CS_2840 0x04
#define CK_2840 0x02
#define DO_2840 0x01
#define STATUS_2840 0xc1
#define BIOS_SEL 0x60
#define ADSEL 0x1e
#define EEPROM_TF 0x80
#define DI_2840 0x01
#define SCB_64_BTT 0xd0
#define CCHADDR 0xe0
#define CCHCNT 0xe8
#define CCSGRAM 0xe9
#define CCSGADDR 0xea
#define CCSGCTL 0xeb
#define CCSGDONE 0x80
#define CCSGEN 0x08
#define SG_FETCH_NEEDED 0x02
#define CCSGRESET 0x01
#define CCSCBRAM 0xec
#define CCSCBADDR 0xed
#define CCSCBCTL 0xee
#define CCSCBDONE 0x80
#define ARRDONE 0x40
#define CCARREN 0x10
#define CCSCBEN 0x08
#define CCSCBDIR 0x04
#define CCSCBRESET 0x01
#define CCSCBCNT 0xef
#define SCBBADDR 0xf0
#define CCSCBPTR 0xf1
#define HNSCB_QOFF 0xf4
#define SNSCB_QOFF 0xf6
#define SDSCB_QOFF 0xf8
#define QOFF_CTLSTA 0xfa
#define SCB_QSIZE 0x07
#define SCB_QSIZE_256 0x06
#define SCB_AVAIL 0x40
#define SNSCB_ROLLOVER 0x20
#define SDSCB_ROLLOVER 0x10
#define DFF_THRSH 0xfb
#define WR_DFTHRSH 0x70
#define WR_DFTHRSH_MAX 0x70
#define WR_DFTHRSH_90 0x60
#define WR_DFTHRSH_85 0x50
#define WR_DFTHRSH_75 0x40
#define WR_DFTHRSH_63 0x30
#define WR_DFTHRSH_50 0x20
#define WR_DFTHRSH_25 0x10
#define RD_DFTHRSH 0x07
#define RD_DFTHRSH_MAX 0x07
#define RD_DFTHRSH_90 0x06
#define RD_DFTHRSH_85 0x05
#define RD_DFTHRSH_75 0x04
#define RD_DFTHRSH_63 0x03
#define RD_DFTHRSH_50 0x02
#define RD_DFTHRSH_25 0x01
#define RD_DFTHRSH_MIN 0x00
#define WR_DFTHRSH_MIN 0x00
#define SG_CACHE_SHADOW 0xfc
#define SG_ADDR_MASK 0xf8
#define LAST_SEG 0x02
#define LAST_SEG_DONE 0x01
#define SG_CACHE_PRE 0xfc
#define MAX_OFFSET_ULTRA2 0x7f
#define MAX_OFFSET_16BIT 0x08
#define BUS_8_BIT 0x00
#define TARGET_CMD_CMPLT 0xfe
#define STATUS_QUEUE_FULL 0x28
#define STATUS_BUSY 0x08
#define MAX_OFFSET_8BIT 0x0f
#define BUS_32_BIT 0x02
#define CCSGADDR_MAX 0x80
#define TID_SHIFT 0x04
#define SCB_DOWNLOAD_SIZE_64 0x30
#define HOST_MAILBOX_SHIFT 0x04
#define CMD_GROUP_CODE_SHIFT 0x05
#define CCSGRAM_MAXSEGS 0x10
#define SCB_LIST_NULL 0xff
#define SG_SIZEOF 0x08
#define SCB_DOWNLOAD_SIZE 0x20
#define SEQ_MAILBOX_SHIFT 0x00
#define TARGET_DATA_IN 0x01
#define HOST_MSG 0xff
#define MAX_OFFSET 0x7f
#define BUS_16_BIT 0x01
#define SCB_UPLOAD_SIZE 0x20
#define STACK_SIZE 0x04
/* Downloaded Constant Definitions */
#define INVERTED_CACHESIZE_MASK 0x03
#define SG_PREFETCH_ADDR_MASK 0x06
#define SG_PREFETCH_ALIGN_MASK 0x05
#define QOUTFIFO_OFFSET 0x00
#define SG_PREFETCH_CNT 0x04
#define CACHESIZE_MASK 0x02
#define QINFIFO_OFFSET 0x01
#define DOWNLOAD_CONST_COUNT 0x07
/* Exported Labels */

413
drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped Normal file
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/*
* DO NOT EDIT - This file is automatically generated
* from the following source files:
*
* $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $
* $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $
*/
#include "aic7xxx_osm.h"
static const ahc_reg_parse_entry_t SCSISEQ_parse_table[] = {
{ "SCSIRSTO", 0x01, 0x01 },
{ "ENAUTOATNP", 0x02, 0x02 },
{ "ENAUTOATNI", 0x04, 0x04 },
{ "ENAUTOATNO", 0x08, 0x08 },
{ "ENRSELI", 0x10, 0x10 },
{ "ENSELI", 0x20, 0x20 },
{ "ENSELO", 0x40, 0x40 },
{ "TEMODE", 0x80, 0x80 }
};
int
ahc_scsiseq_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SCSISEQ_parse_table, 8, "SCSISEQ",
0x00, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t SXFRCTL0_parse_table[] = {
{ "CLRCHN", 0x02, 0x02 },
{ "SCAMEN", 0x04, 0x04 },
{ "SPIOEN", 0x08, 0x08 },
{ "CLRSTCNT", 0x10, 0x10 },
{ "FAST20", 0x20, 0x20 },
{ "DFPEXP", 0x40, 0x40 },
{ "DFON", 0x80, 0x80 }
};
int
ahc_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SXFRCTL0_parse_table, 7, "SXFRCTL0",
0x01, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t SCSISIGI_parse_table[] = {
{ "ACKI", 0x01, 0x01 },
{ "REQI", 0x02, 0x02 },
{ "BSYI", 0x04, 0x04 },
{ "SELI", 0x08, 0x08 },
{ "ATNI", 0x10, 0x10 },
{ "MSGI", 0x20, 0x20 },
{ "IOI", 0x40, 0x40 },
{ "CDI", 0x80, 0x80 },
{ "P_DATAOUT", 0x00, 0x00 },
{ "P_DATAOUT_DT", 0x20, 0x20 },
{ "P_DATAIN", 0x40, 0x40 },
{ "P_DATAIN_DT", 0x60, 0x60 },
{ "P_COMMAND", 0x80, 0x80 },
{ "P_MESGOUT", 0xa0, 0xa0 },
{ "P_STATUS", 0xc0, 0xc0 },
{ "PHASE_MASK", 0xe0, 0xe0 },
{ "P_MESGIN", 0xe0, 0xe0 }
};
int
ahc_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SCSISIGI_parse_table, 17, "SCSISIGI",
0x03, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t SCSIRATE_parse_table[] = {
{ "SINGLE_EDGE", 0x10, 0x10 },
{ "ENABLE_CRC", 0x40, 0x40 },
{ "WIDEXFER", 0x80, 0x80 },
{ "SXFR_ULTRA2", 0x0f, 0x0f },
{ "SOFS", 0x0f, 0x0f },
{ "SXFR", 0x70, 0x70 }
};
int
ahc_scsirate_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SCSIRATE_parse_table, 6, "SCSIRATE",
0x04, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t SSTAT0_parse_table[] = {
{ "DMADONE", 0x01, 0x01 },
{ "SPIORDY", 0x02, 0x02 },
{ "SDONE", 0x04, 0x04 },
{ "SWRAP", 0x08, 0x08 },
{ "IOERR", 0x08, 0x08 },
{ "SELINGO", 0x10, 0x10 },
{ "SELDI", 0x20, 0x20 },
{ "SELDO", 0x40, 0x40 },
{ "TARGET", 0x80, 0x80 }
};
int
ahc_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SSTAT0_parse_table, 9, "SSTAT0",
0x0b, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t SSTAT1_parse_table[] = {
{ "REQINIT", 0x01, 0x01 },
{ "PHASECHG", 0x02, 0x02 },
{ "SCSIPERR", 0x04, 0x04 },
{ "BUSFREE", 0x08, 0x08 },
{ "PHASEMIS", 0x10, 0x10 },
{ "SCSIRSTI", 0x20, 0x20 },
{ "ATNTARG", 0x40, 0x40 },
{ "SELTO", 0x80, 0x80 }
};
int
ahc_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SSTAT1_parse_table, 8, "SSTAT1",
0x0c, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t SSTAT2_parse_table[] = {
{ "DUAL_EDGE_ERR", 0x01, 0x01 },
{ "CRCREQERR", 0x02, 0x02 },
{ "CRCENDERR", 0x04, 0x04 },
{ "CRCVALERR", 0x08, 0x08 },
{ "EXP_ACTIVE", 0x10, 0x10 },
{ "SHVALID", 0x40, 0x40 },
{ "OVERRUN", 0x80, 0x80 },
{ "SFCNT", 0x1f, 0x1f }
};
int
ahc_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SSTAT2_parse_table, 8, "SSTAT2",
0x0d, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t SSTAT3_parse_table[] = {
{ "OFFCNT", 0x0f, 0x0f },
{ "U2OFFCNT", 0x7f, 0x7f },
{ "SCSICNT", 0xf0, 0xf0 }
};
int
ahc_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SSTAT3_parse_table, 3, "SSTAT3",
0x0e, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t SIMODE0_parse_table[] = {
{ "ENDMADONE", 0x01, 0x01 },
{ "ENSPIORDY", 0x02, 0x02 },
{ "ENSDONE", 0x04, 0x04 },
{ "ENSWRAP", 0x08, 0x08 },
{ "ENIOERR", 0x08, 0x08 },
{ "ENSELINGO", 0x10, 0x10 },
{ "ENSELDI", 0x20, 0x20 },
{ "ENSELDO", 0x40, 0x40 }
};
int
ahc_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SIMODE0_parse_table, 8, "SIMODE0",
0x10, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t SIMODE1_parse_table[] = {
{ "ENREQINIT", 0x01, 0x01 },
{ "ENPHASECHG", 0x02, 0x02 },
{ "ENSCSIPERR", 0x04, 0x04 },
{ "ENBUSFREE", 0x08, 0x08 },
{ "ENPHASEMIS", 0x10, 0x10 },
{ "ENSCSIRST", 0x20, 0x20 },
{ "ENATNTARG", 0x40, 0x40 },
{ "ENSELTIMO", 0x80, 0x80 }
};
int
ahc_simode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SIMODE1_parse_table, 8, "SIMODE1",
0x11, regvalue, cur_col, wrap));
}
int
ahc_scsibusl_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(NULL, 0, "SCSIBUSL",
0x12, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t SBLKCTL_parse_table[] = {
{ "XCVR", 0x01, 0x01 },
{ "SELWIDE", 0x02, 0x02 },
{ "ENAB20", 0x04, 0x04 },
{ "SELBUSB", 0x08, 0x08 },
{ "ENAB40", 0x08, 0x08 },
{ "AUTOFLUSHDIS", 0x20, 0x20 },
{ "DIAGLEDON", 0x40, 0x40 },
{ "DIAGLEDEN", 0x80, 0x80 }
};
int
ahc_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SBLKCTL_parse_table, 8, "SBLKCTL",
0x1f, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
{ "NO_DISCONNECT", 0x01, 0x01 },
{ "SPHASE_PENDING", 0x02, 0x02 },
{ "DPHASE_PENDING", 0x04, 0x04 },
{ "CMDPHASE_PENDING", 0x08, 0x08 },
{ "TARG_CMD_PENDING", 0x10, 0x10 },
{ "DPHASE", 0x20, 0x20 },
{ "NO_CDB_SENT", 0x40, 0x40 },
{ "TARGET_CMD_IS_TAGGED",0x40, 0x40 },
{ "NOT_IDENTIFIED", 0x80, 0x80 }
};
int
ahc_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SEQ_FLAGS_parse_table, 9, "SEQ_FLAGS",
0x3c, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t LASTPHASE_parse_table[] = {
{ "MSGI", 0x20, 0x20 },
{ "IOI", 0x40, 0x40 },
{ "CDI", 0x80, 0x80 },
{ "P_DATAOUT", 0x00, 0x00 },
{ "P_BUSFREE", 0x01, 0x01 },
{ "P_DATAIN", 0x40, 0x40 },
{ "P_COMMAND", 0x80, 0x80 },
{ "P_MESGOUT", 0xa0, 0xa0 },
{ "P_STATUS", 0xc0, 0xc0 },
{ "PHASE_MASK", 0xe0, 0xe0 },
{ "P_MESGIN", 0xe0, 0xe0 }
};
int
ahc_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(LASTPHASE_parse_table, 11, "LASTPHASE",
0x3f, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t SEQCTL_parse_table[] = {
{ "LOADRAM", 0x01, 0x01 },
{ "SEQRESET", 0x02, 0x02 },
{ "STEP", 0x04, 0x04 },
{ "BRKADRINTEN", 0x08, 0x08 },
{ "FASTMODE", 0x10, 0x10 },
{ "FAILDIS", 0x20, 0x20 },
{ "PAUSEDIS", 0x40, 0x40 },
{ "PERRORDIS", 0x80, 0x80 }
};
int
ahc_seqctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SEQCTL_parse_table, 8, "SEQCTL",
0x60, regvalue, cur_col, wrap));
}
int
ahc_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(NULL, 0, "SRAM_BASE",
0x70, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t ERROR_parse_table[] = {
{ "ILLHADDR", 0x01, 0x01 },
{ "ILLSADDR", 0x02, 0x02 },
{ "ILLOPCODE", 0x04, 0x04 },
{ "SQPARERR", 0x08, 0x08 },
{ "DPARERR", 0x10, 0x10 },
{ "MPARERR", 0x20, 0x20 },
{ "PCIERRSTAT", 0x40, 0x40 },
{ "CIOPARERR", 0x80, 0x80 }
};
int
ahc_error_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(ERROR_parse_table, 8, "ERROR",
0x92, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t DFCNTRL_parse_table[] = {
{ "FIFORESET", 0x01, 0x01 },
{ "FIFOFLUSH", 0x02, 0x02 },
{ "DIRECTION", 0x04, 0x04 },
{ "HDMAEN", 0x08, 0x08 },
{ "HDMAENACK", 0x08, 0x08 },
{ "SDMAEN", 0x10, 0x10 },
{ "SDMAENACK", 0x10, 0x10 },
{ "SCSIEN", 0x20, 0x20 },
{ "WIDEODD", 0x40, 0x40 },
{ "PRELOADEN", 0x80, 0x80 }
};
int
ahc_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(DFCNTRL_parse_table, 10, "DFCNTRL",
0x93, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t DFSTATUS_parse_table[] = {
{ "FIFOEMP", 0x01, 0x01 },
{ "FIFOFULL", 0x02, 0x02 },
{ "DFTHRESH", 0x04, 0x04 },
{ "HDONE", 0x08, 0x08 },
{ "MREQPEND", 0x10, 0x10 },
{ "FIFOQWDEMP", 0x20, 0x20 },
{ "DFCACHETH", 0x40, 0x40 },
{ "PRELOAD_AVAIL", 0x80, 0x80 }
};
int
ahc_dfstatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(DFSTATUS_parse_table, 8, "DFSTATUS",
0x94, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t SCSIPHASE_parse_table[] = {
{ "DATA_OUT_PHASE", 0x01, 0x01 },
{ "DATA_IN_PHASE", 0x02, 0x02 },
{ "MSG_OUT_PHASE", 0x04, 0x04 },
{ "MSG_IN_PHASE", 0x08, 0x08 },
{ "COMMAND_PHASE", 0x10, 0x10 },
{ "STATUS_PHASE", 0x20, 0x20 },
{ "DATA_PHASE_MASK", 0x03, 0x03 }
};
int
ahc_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SCSIPHASE_parse_table, 7, "SCSIPHASE",
0x9e, regvalue, cur_col, wrap));
}
int
ahc_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(NULL, 0, "SCB_BASE",
0xa0, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t SCB_CONTROL_parse_table[] = {
{ "DISCONNECTED", 0x04, 0x04 },
{ "ULTRAENB", 0x08, 0x08 },
{ "MK_MESSAGE", 0x10, 0x10 },
{ "TAG_ENB", 0x20, 0x20 },
{ "DISCENB", 0x40, 0x40 },
{ "TARGET_SCB", 0x80, 0x80 },
{ "STATUS_RCVD", 0x80, 0x80 },
{ "SCB_TAG_TYPE", 0x03, 0x03 }
};
int
ahc_scb_control_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SCB_CONTROL_parse_table, 8, "SCB_CONTROL",
0xb8, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t SCB_SCSIID_parse_table[] = {
{ "TWIN_CHNLB", 0x80, 0x80 },
{ "OID", 0x0f, 0x0f },
{ "TWIN_TID", 0x70, 0x70 },
{ "TID", 0xf0, 0xf0 }
};
int
ahc_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SCB_SCSIID_parse_table, 4, "SCB_SCSIID",
0xb9, regvalue, cur_col, wrap));
}
static const ahc_reg_parse_entry_t SCB_LUN_parse_table[] = {
{ "SCB_XFERLEN_ODD", 0x80, 0x80 },
{ "LID", 0x3f, 0x3f }
};
int
ahc_scb_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(SCB_LUN_parse_table, 2, "SCB_LUN",
0xba, regvalue, cur_col, wrap));
}
int
ahc_scb_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
{
return (ahc_print_register(NULL, 0, "SCB_TAG",
0xbb, regvalue, cur_col, wrap));
}

1308
drivers/scsi/aic7xxx/aic7xxx_seq.h_shipped Normal file
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80
drivers/scsi/aic7xxx/aicasm/Makefile Normal file
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@ -0,0 +1,80 @@
PROG= aicasm
.SUFFIXES= .l .y .c .h
CSRCS= aicasm.c aicasm_symbol.c
YSRCS= aicasm_gram.y aicasm_macro_gram.y
LSRCS= aicasm_scan.l aicasm_macro_scan.l
GENHDRS= aicdb.h $(YSRCS:.y=.h)
GENSRCS= $(YSRCS:.y=.c) $(LSRCS:.l=.c)
SRCS= ${CSRCS} ${GENSRCS}
LIBS= -ldb
clean-files:= ${GENSRCS} ${GENHDRS} $(YSRCS:.y=.output) $(PROG)
# Override default kernel CFLAGS. This is a userland app.
AICASM_CFLAGS:= -I/usr/include -I.
LEX= flex
YACC= bison
YFLAGS= -d
NOMAN= noman
ifneq ($(HOSTCC),)
AICASM_CC= $(HOSTCC)
else
AICASM_CC= $(CC)
endif
ifdef DEBUG
CFLAGS+= -DDEBUG -g
YFLAGS+= -t -v
LFLAGS= -d
endif
$(PROG): ${GENHDRS} $(SRCS)
$(AICASM_CC) $(AICASM_CFLAGS) $(SRCS) -o $(PROG) $(LIBS)
aicdb.h:
@if [ -e "/usr/include/db4/db_185.h" ]; then \
echo "#include <db4/db_185.h>" > aicdb.h; \
elif [ -e "/usr/include/db3/db_185.h" ]; then \
echo "#include <db3/db_185.h>" > aicdb.h; \
elif [ -e "/usr/include/db2/db_185.h" ]; then \
echo "#include <db2/db_185.h>" > aicdb.h; \
elif [ -e "/usr/include/db1/db_185.h" ]; then \
echo "#include <db1/db_185.h>" > aicdb.h; \
elif [ -e "/usr/include/db/db_185.h" ]; then \
echo "#include <db/db_185.h>" > aicdb.h; \
elif [ -e "/usr/include/db_185.h" ]; then \
echo "#include <db_185.h>" > aicdb.h; \
else \
echo "*** Install db development libraries"; \
fi
clean:
rm -f $(clean-files)
# Create a dependency chain in generated files
# to avoid concurrent invocations of the single
# rule that builds them all.
aicasm_gram.c: aicasm_gram.h
aicasm_gram.c aicasm_gram.h: aicasm_gram.y
$(YACC) $(YFLAGS) -b $(<:.y=) $<
mv $(<:.y=).tab.c $(<:.y=.c)
mv $(<:.y=).tab.h $(<:.y=.h)
# Create a dependency chain in generated files
# to avoid concurrent invocations of the single
# rule that builds them all.
aicasm_macro_gram.c: aicasm_macro_gram.h
aicasm_macro_gram.c aicasm_macro_gram.h: aicasm_macro_gram.y
$(YACC) $(YFLAGS) -b $(<:.y=) -p mm $<
mv $(<:.y=).tab.c $(<:.y=.c)
mv $(<:.y=).tab.h $(<:.y=.h)
aicasm_scan.c: aicasm_scan.l
$(LEX) $(LFLAGS) -o$@ $<
aicasm_macro_scan.c: aicasm_macro_scan.l
$(LEX) $(LFLAGS) -Pmm -o$@ $<

844
drivers/scsi/aic7xxx/aicasm/aicasm.c Normal file
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@ -0,0 +1,844 @@
/*
* Aic7xxx SCSI host adapter firmware assembler
*
* Copyright (c) 1997, 1998, 2000, 2001 Justin T. Gibbs.
* Copyright (c) 2001, 2002 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm.c#23 $
*
* $FreeBSD$
*/
#include <sys/types.h>
#include <sys/mman.h>
#include <ctype.h>
#include <inttypes.h>
#include <regex.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sysexits.h>
#include <unistd.h>
#if linux
#include <endian.h>
#else
#include <machine/endian.h>
#endif
#include "aicasm.h"
#include "aicasm_symbol.h"
#include "aicasm_insformat.h"
typedef struct patch {
STAILQ_ENTRY(patch) links;
int patch_func;
u_int begin;
u_int skip_instr;
u_int skip_patch;
} patch_t;
STAILQ_HEAD(patch_list, patch) patches;
static void usage(void);
static void back_patch(void);
static void output_code(void);
static void output_listing(char *ifilename);
static void dump_scope(scope_t *scope);
static void emit_patch(scope_t *scope, int patch);
static int check_patch(patch_t **start_patch, int start_instr,
int *skip_addr, int *func_vals);
struct path_list search_path;
int includes_search_curdir;
char *appname;
char *stock_include_file;
FILE *ofile;
char *ofilename;
char *regfilename;
FILE *regfile;
char *listfilename;
FILE *listfile;
char *regdiagfilename;
FILE *regdiagfile;
int src_mode;
int dst_mode;
static STAILQ_HEAD(,instruction) seq_program;
struct cs_tailq cs_tailq;
struct scope_list scope_stack;
symlist_t patch_functions;
#if DEBUG
extern int yy_flex_debug;
extern int mm_flex_debug;
extern int yydebug;
extern int mmdebug;
#endif
extern FILE *yyin;
extern int yyparse(void);
int main(int argc, char *argv[]);
int
main(int argc, char *argv[])
{
extern char *optarg;
extern int optind;
int ch;
int retval;
char *inputfilename;
scope_t *sentinal;
STAILQ_INIT(&patches);
SLIST_INIT(&search_path);
STAILQ_INIT(&seq_program);
TAILQ_INIT(&cs_tailq);
SLIST_INIT(&scope_stack);
/* Set Sentinal scope node */
sentinal = scope_alloc();
sentinal->type = SCOPE_ROOT;
includes_search_curdir = 1;
appname = *argv;
regfile = NULL;
listfile = NULL;
#if DEBUG
yy_flex_debug = 0;
mm_flex_debug = 0;
yydebug = 0;
mmdebug = 0;
#endif
while ((ch = getopt(argc, argv, "d:i:l:n:o:p:r:I:")) != -1) {
switch(ch) {
case 'd':
#if DEBUG
if (strcmp(optarg, "s") == 0) {
yy_flex_debug = 1;
mm_flex_debug = 1;
} else if (strcmp(optarg, "p") == 0) {
yydebug = 1;
mmdebug = 1;
} else {
fprintf(stderr, "%s: -d Requires either an "
"'s' or 'p' argument\n", appname);
usage();
}
#else
stop("-d: Assembler not built with debugging "
"information", EX_SOFTWARE);
#endif
break;
case 'i':
stock_include_file = optarg;
break;
case 'l':
/* Create a program listing */
if ((listfile = fopen(optarg, "w")) == NULL) {
perror(optarg);
stop(NULL, EX_CANTCREAT);
}
listfilename = optarg;
break;
case 'n':
/* Don't complain about the -nostdinc directrive */
if (strcmp(optarg, "ostdinc")) {
fprintf(stderr, "%s: Unknown option -%c%s\n",
appname, ch, optarg);
usage();
/* NOTREACHED */
}
break;
case 'o':
if ((ofile = fopen(optarg, "w")) == NULL) {
perror(optarg);
stop(NULL, EX_CANTCREAT);
}
ofilename = optarg;
break;
case 'p':
/* Create Register Diagnostic "printing" Functions */
if ((regdiagfile = fopen(optarg, "w")) == NULL) {
perror(optarg);
stop(NULL, EX_CANTCREAT);
}
regdiagfilename = optarg;
break;
case 'r':
if ((regfile = fopen(optarg, "w")) == NULL) {
perror(optarg);
stop(NULL, EX_CANTCREAT);
}
regfilename = optarg;
break;
case 'I':
{
path_entry_t include_dir;
if (strcmp(optarg, "-") == 0) {
if (includes_search_curdir == 0) {
fprintf(stderr, "%s: Warning - '-I-' "
"specified multiple "
"times\n", appname);
}
includes_search_curdir = 0;
for (include_dir = SLIST_FIRST(&search_path);
include_dir != NULL;
include_dir = SLIST_NEXT(include_dir,
links))
/*
* All entries before a '-I-' only
* apply to includes specified with
* quotes instead of "<>".
*/
include_dir->quoted_includes_only = 1;
} else {
include_dir =
(path_entry_t)malloc(sizeof(*include_dir));
if (include_dir == NULL) {
perror(optarg);
stop(NULL, EX_OSERR);
}
include_dir->directory = strdup(optarg);
if (include_dir->directory == NULL) {
perror(optarg);
stop(NULL, EX_OSERR);
}
include_dir->quoted_includes_only = 0;
SLIST_INSERT_HEAD(&search_path, include_dir,
links);
}
break;
}
case '?':
default:
usage();
/* NOTREACHED */
}
}
argc -= optind;
argv += optind;
if (argc != 1) {
fprintf(stderr, "%s: No input file specifiled\n", appname);
usage();
/* NOTREACHED */
}
if (regdiagfile != NULL
&& (regfile == NULL || stock_include_file == NULL)) {
fprintf(stderr,
"%s: The -p option requires the -r and -i options.\n",
appname);
usage();
/* NOTREACHED */
}
symtable_open();
inputfilename = *argv;
include_file(*argv, SOURCE_FILE);
retval = yyparse();
if (retval == 0) {
if (SLIST_FIRST(&scope_stack) == NULL
|| SLIST_FIRST(&scope_stack)->type != SCOPE_ROOT) {
stop("Unterminated conditional expression", EX_DATAERR);
/* NOTREACHED */
}
/* Process outmost scope */
process_scope(SLIST_FIRST(&scope_stack));
/*
* Decend the tree of scopes and insert/emit
* patches as appropriate. We perform a depth first
* tranversal, recursively handling each scope.
*/
/* start at the root scope */
dump_scope(SLIST_FIRST(&scope_stack));
/* Patch up forward jump addresses */
back_patch();
if (ofile != NULL)
output_code();
if (regfile != NULL)
symtable_dump(regfile, regdiagfile);
if (listfile != NULL)
output_listing(inputfilename);
}
stop(NULL, 0);
/* NOTREACHED */
return (0);
}
static void
usage()
{
(void)fprintf(stderr,
"usage: %-16s [-nostdinc] [-I-] [-I directory] [-o output_file]\n"
" [-r register_output_file [-p register_diag_file -i includefile]]\n"
" [-l program_list_file]\n"
" input_file\n", appname);
exit(EX_USAGE);
}
static void
back_patch()
{
struct instruction *cur_instr;
for (cur_instr = STAILQ_FIRST(&seq_program);
cur_instr != NULL;
cur_instr = STAILQ_NEXT(cur_instr, links)) {
if (cur_instr->patch_label != NULL) {
struct ins_format3 *f3_instr;
u_int address;
if (cur_instr->patch_label->type != LABEL) {
char buf[255];
snprintf(buf, sizeof(buf),
"Undefined label %s",
cur_instr->patch_label->name);
stop(buf, EX_DATAERR);
/* NOTREACHED */
}
f3_instr = &cur_instr->format.format3;
address = f3_instr->address;
address += cur_instr->patch_label->info.linfo->address;
f3_instr->address = address;
}
}
}
static void
output_code()
{
struct instruction *cur_instr;
patch_t *cur_patch;
critical_section_t *cs;
symbol_node_t *cur_node;
int instrcount;
instrcount = 0;
fprintf(ofile,
"/*\n"
" * DO NOT EDIT - This file is automatically generated\n"
" * from the following source files:\n"
" *\n"
"%s */\n", versions);
fprintf(ofile, "static const uint8_t seqprog[] = {\n");
for (cur_instr = STAILQ_FIRST(&seq_program);
cur_instr != NULL;
cur_instr = STAILQ_NEXT(cur_instr, links)) {
fprintf(ofile, "%s\t0x%02x, 0x%02x, 0x%02x, 0x%02x",
cur_instr == STAILQ_FIRST(&seq_program) ? "" : ",\n",
#ifdef __LITTLE_ENDIAN
cur_instr->format.bytes[0],
cur_instr->format.bytes[1],
cur_instr->format.bytes[2],
cur_instr->format.bytes[3]);
#else
cur_instr->format.bytes[3],
cur_instr->format.bytes[2],
cur_instr->format.bytes[1],
cur_instr->format.bytes[0]);
#endif
instrcount++;
}
fprintf(ofile, "\n};\n\n");
if (patch_arg_list == NULL)
stop("Patch argument list not defined",
EX_DATAERR);
/*
* Output patch information. Patch functions first.
*/
fprintf(ofile,
"typedef int %spatch_func_t (%s);\n", prefix, patch_arg_list);
for (cur_node = SLIST_FIRST(&patch_functions);
cur_node != NULL;
cur_node = SLIST_NEXT(cur_node,links)) {
fprintf(ofile,
"static %spatch_func_t %spatch%d_func;\n"
"\n"
"static int\n"
"%spatch%d_func(%s)\n"
"{\n"
" return (%s);\n"
"}\n\n",
prefix,
prefix,
cur_node->symbol->info.condinfo->func_num,
prefix,
cur_node->symbol->info.condinfo->func_num,
patch_arg_list,
cur_node->symbol->name);
}
fprintf(ofile,
"static const struct patch {\n"
" %spatch_func_t *patch_func;\n"
" uint32_t begin :10,\n"
" skip_instr :10,\n"
" skip_patch :12;\n"
"} patches[] = {\n", prefix);
for (cur_patch = STAILQ_FIRST(&patches);
cur_patch != NULL;
cur_patch = STAILQ_NEXT(cur_patch,links)) {
fprintf(ofile, "%s\t{ %spatch%d_func, %d, %d, %d }",
cur_patch == STAILQ_FIRST(&patches) ? "" : ",\n",
prefix,
cur_patch->patch_func, cur_patch->begin,
cur_patch->skip_instr, cur_patch->skip_patch);
}
fprintf(ofile, "\n};\n\n");
fprintf(ofile,
"static const struct cs {\n"
" uint16_t begin;\n"
" uint16_t end;\n"
"} critical_sections[] = {\n");
for (cs = TAILQ_FIRST(&cs_tailq);
cs != NULL;
cs = TAILQ_NEXT(cs, links)) {
fprintf(ofile, "%s\t{ %d, %d }",
cs == TAILQ_FIRST(&cs_tailq) ? "" : ",\n",
cs->begin_addr, cs->end_addr);
}
fprintf(ofile, "\n};\n\n");
fprintf(ofile,
"static const int num_critical_sections = sizeof(critical_sections)\n"
" / sizeof(*critical_sections);\n");
fprintf(stderr, "%s: %d instructions used\n", appname, instrcount);
}
static void
dump_scope(scope_t *scope)
{
scope_t *cur_scope;
/*
* Emit the first patch for this scope
*/
emit_patch(scope, 0);
/*
* Dump each scope within this one.
*/
cur_scope = TAILQ_FIRST(&scope->inner_scope);
while (cur_scope != NULL) {
dump_scope(cur_scope);
cur_scope = TAILQ_NEXT(cur_scope, scope_links);
}
/*
* Emit the second, closing, patch for this scope
*/
emit_patch(scope, 1);
}
void
emit_patch(scope_t *scope, int patch)
{
patch_info_t *pinfo;
patch_t *new_patch;
pinfo = &scope->patches[patch];
if (pinfo->skip_instr == 0)
/* No-Op patch */
return;
new_patch = (patch_t *)malloc(sizeof(*new_patch));
if (new_patch == NULL)
stop("Could not malloc patch structure", EX_OSERR);
memset(new_patch, 0, sizeof(*new_patch));
if (patch == 0) {
new_patch->patch_func = scope->func_num;
new_patch->begin = scope->begin_addr;
} else {
new_patch->patch_func = 0;
new_patch->begin = scope->end_addr;
}
new_patch->skip_instr = pinfo->skip_instr;
new_patch->skip_patch = pinfo->skip_patch;
STAILQ_INSERT_TAIL(&patches, new_patch, links);
}
void
output_listing(char *ifilename)
{
char buf[1024];
FILE *ifile;
struct instruction *cur_instr;
patch_t *cur_patch;
symbol_node_t *cur_func;
int *func_values;
int instrcount;
int instrptr;
int line;
int func_count;
int skip_addr;
instrcount = 0;
instrptr = 0;
line = 1;
skip_addr = 0;
if ((ifile = fopen(ifilename, "r")) == NULL) {
perror(ifilename);
stop(NULL, EX_DATAERR);
}
/*
* Determine which options to apply to this listing.
*/
for (func_count = 0, cur_func = SLIST_FIRST(&patch_functions);
cur_func != NULL;
cur_func = SLIST_NEXT(cur_func, links))
func_count++;
func_values = NULL;
if (func_count != 0) {
func_values = (int *)malloc(func_count * sizeof(int));
if (func_values == NULL)
stop("Could not malloc", EX_OSERR);
func_values[0] = 0; /* FALSE func */
func_count--;
/*
* Ask the user to fill in the return values for
* the rest of the functions.
*/
for (cur_func = SLIST_FIRST(&patch_functions);
cur_func != NULL && SLIST_NEXT(cur_func, links) != NULL;
cur_func = SLIST_NEXT(cur_func, links), func_count--) {
int input;
fprintf(stdout, "\n(%s)\n", cur_func->symbol->name);
fprintf(stdout,
"Enter the return value for "
"this expression[T/F]:");
while (1) {
input = getchar();
input = toupper(input);
if (input == 'T') {
func_values[func_count] = 1;
break;
} else if (input == 'F') {
func_values[func_count] = 0;
break;
}
}
if (isatty(fileno(stdin)) == 0)
putchar(input);
}
fprintf(stdout, "\nThanks!\n");
}
/* Now output the listing */
cur_patch = STAILQ_FIRST(&patches);
for (cur_instr = STAILQ_FIRST(&seq_program);
cur_instr != NULL;
cur_instr = STAILQ_NEXT(cur_instr, links), instrcount++) {
if (check_patch(&cur_patch, instrcount,
&skip_addr, func_values) == 0) {
/* Don't count this instruction as it is in a patch
* that was removed.
*/
continue;
}
while (line < cur_instr->srcline) {
fgets(buf, sizeof(buf), ifile);
fprintf(listfile, " \t%s", buf);
line++;
}
fprintf(listfile, "%04x %02x%02x%02x%02x", instrptr,
#ifdef __LITTLE_ENDIAN
cur_instr->format.bytes[0],
cur_instr->format.bytes[1],
cur_instr->format.bytes[2],
cur_instr->format.bytes[3]);
#else
cur_instr->format.bytes[3],
cur_instr->format.bytes[2],
cur_instr->format.bytes[1],
cur_instr->format.bytes[0]);
#endif
/*
* Macro expansions can cause several instructions
* to be output for a single source line. Only
* advance the line once in these cases.
*/
if (line == cur_instr->srcline) {
fgets(buf, sizeof(buf), ifile);
fprintf(listfile, "\t%s", buf);
line++;
} else {
fprintf(listfile, "\n");
}
instrptr++;
}
/* Dump the remainder of the file */
while(fgets(buf, sizeof(buf), ifile) != NULL)
fprintf(listfile, " %s", buf);
fclose(ifile);
}
static int
check_patch(patch_t **start_patch, int start_instr,
int *skip_addr, int *func_vals)
{
patch_t *cur_patch;
cur_patch = *start_patch;
while (cur_patch != NULL && start_instr == cur_patch->begin) {
if (func_vals[cur_patch->patch_func] == 0) {
int skip;
/* Start rejecting code */
*skip_addr = start_instr + cur_patch->skip_instr;
for (skip = cur_patch->skip_patch;
skip > 0 && cur_patch != NULL;
skip--)
cur_patch = STAILQ_NEXT(cur_patch, links);
} else {
/* Accepted this patch. Advance to the next
* one and wait for our intruction pointer to
* hit this point.
*/
cur_patch = STAILQ_NEXT(cur_patch, links);
}
}
*start_patch = cur_patch;
if (start_instr < *skip_addr)
/* Still skipping */
return (0);
return (1);
}
/*
* Print out error information if appropriate, and clean up before
* terminating the program.
*/
void
stop(const char *string, int err_code)
{
if (string != NULL) {
fprintf(stderr, "%s: ", appname);
if (yyfilename != NULL) {
fprintf(stderr, "Stopped at file %s, line %d - ",
yyfilename, yylineno);
}
fprintf(stderr, "%s\n", string);
}
if (ofile != NULL) {
fclose(ofile);
if (err_code != 0) {
fprintf(stderr, "%s: Removing %s due to error\n",
appname, ofilename);
unlink(ofilename);
}
}
if (regfile != NULL) {
fclose(regfile);
if (err_code != 0) {
fprintf(stderr, "%s: Removing %s due to error\n",
appname, regfilename);
unlink(regfilename);
}
}
if (listfile != NULL) {
fclose(listfile);
if (err_code != 0) {
fprintf(stderr, "%s: Removing %s due to error\n",
appname, listfilename);
unlink(listfilename);
}
}
symlist_free(&patch_functions);
symtable_close();
exit(err_code);
}
struct instruction *
seq_alloc()
{
struct instruction *new_instr;
new_instr = (struct instruction *)malloc(sizeof(struct instruction));
if (new_instr == NULL)
stop("Unable to malloc instruction object", EX_SOFTWARE);
memset(new_instr, 0, sizeof(*new_instr));
STAILQ_INSERT_TAIL(&seq_program, new_instr, links);
new_instr->srcline = yylineno;
return new_instr;
}
critical_section_t *
cs_alloc()
{
critical_section_t *new_cs;
new_cs= (critical_section_t *)malloc(sizeof(critical_section_t));
if (new_cs == NULL)
stop("Unable to malloc critical_section object", EX_SOFTWARE);
memset(new_cs, 0, sizeof(*new_cs));
TAILQ_INSERT_TAIL(&cs_tailq, new_cs, links);
return new_cs;
}
scope_t *
scope_alloc()
{
scope_t *new_scope;
new_scope = (scope_t *)malloc(sizeof(scope_t));
if (new_scope == NULL)
stop("Unable to malloc scope object", EX_SOFTWARE);
memset(new_scope, 0, sizeof(*new_scope));
TAILQ_INIT(&new_scope->inner_scope);
if (SLIST_FIRST(&scope_stack) != NULL) {
TAILQ_INSERT_TAIL(&SLIST_FIRST(&scope_stack)->inner_scope,
new_scope, scope_links);
}
/* This patch is now the current scope */
SLIST_INSERT_HEAD(&scope_stack, new_scope, scope_stack_links);
return new_scope;
}
void
process_scope(scope_t *scope)
{
/*
* We are "leaving" this scope. We should now have
* enough information to process the lists of scopes
* we encapsulate.
*/
scope_t *cur_scope;
u_int skip_patch_count;
u_int skip_instr_count;
cur_scope = TAILQ_LAST(&scope->inner_scope, scope_tailq);
skip_patch_count = 0;
skip_instr_count = 0;
while (cur_scope != NULL) {
u_int patch0_patch_skip;
patch0_patch_skip = 0;
switch (cur_scope->type) {
case SCOPE_IF:
case SCOPE_ELSE_IF:
if (skip_instr_count != 0) {
/* Create a tail patch */
patch0_patch_skip++;
cur_scope->patches[1].skip_patch =
skip_patch_count + 1;
cur_scope->patches[1].skip_instr =
skip_instr_count;
}
/* Count Head patch */
patch0_patch_skip++;
/* Count any patches contained in our inner scope */
patch0_patch_skip += cur_scope->inner_scope_patches;
cur_scope->patches[0].skip_patch = patch0_patch_skip;
cur_scope->patches[0].skip_instr =
cur_scope->end_addr - cur_scope->begin_addr;
skip_instr_count += cur_scope->patches[0].skip_instr;
skip_patch_count += patch0_patch_skip;
if (cur_scope->type == SCOPE_IF) {
scope->inner_scope_patches += skip_patch_count;
skip_patch_count = 0;
skip_instr_count = 0;
}
break;
case SCOPE_ELSE:
/* Count any patches contained in our innter scope */
skip_patch_count += cur_scope->inner_scope_patches;
skip_instr_count += cur_scope->end_addr
- cur_scope->begin_addr;
break;
case SCOPE_ROOT:
stop("Unexpected scope type encountered", EX_SOFTWARE);
/* NOTREACHED */
}
cur_scope = TAILQ_PREV(cur_scope, scope_tailq, scope_links);
}
}

95
drivers/scsi/aic7xxx/aicasm/aicasm.h Normal file
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@ -0,0 +1,95 @@
/*
* Assembler for the sequencer program downloaded to Aic7xxx SCSI host adapters
*
* Copyright (c) 1997 Justin T. Gibbs.
* Copyright (c) 2001, 2002 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm.h#14 $
*
* $FreeBSD$
*/
#ifdef __linux__
#include "../queue.h"
#else
#include <sys/queue.h>
#endif
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
typedef struct path_entry {
char *directory;
int quoted_includes_only;
SLIST_ENTRY(path_entry) links;
} *path_entry_t;
typedef enum {
QUOTED_INCLUDE,
BRACKETED_INCLUDE,
SOURCE_FILE
} include_type;
SLIST_HEAD(path_list, path_entry);
extern struct path_list search_path;
extern struct cs_tailq cs_tailq;
extern struct scope_list scope_stack;
extern struct symlist patch_functions;
extern int includes_search_curdir; /* False if we've seen -I- */
extern char *appname;
extern char *stock_include_file;
extern int yylineno;
extern char *yyfilename;
extern char *prefix;
extern char *patch_arg_list;
extern char *versions;
extern int src_mode;
extern int dst_mode;
struct symbol;
void stop(const char *errstring, int err_code);
void include_file(char *file_name, include_type type);
void expand_macro(struct symbol *macro_symbol);
struct instruction *seq_alloc(void);
struct critical_section *cs_alloc(void);
struct scope *scope_alloc(void);
void process_scope(struct scope *);

2004
drivers/scsi/aic7xxx/aicasm/aicasm_gram.y Normal file
View file

File diff suppressed because it is too large Load diff

218
drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h Normal file
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@ -0,0 +1,218 @@
/*
* Instruction formats for the sequencer program downloaded to
* Aic7xxx SCSI host adapters
*
* Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_insformat.h#12 $
*
* $FreeBSD$
*/
#include <asm/byteorder.h>
/* 8bit ALU logic operations */
struct ins_format1 {
#ifdef __LITTLE_ENDIAN
uint32_t immediate : 8,
source : 9,
destination : 9,
ret : 1,
opcode : 4,
parity : 1;
#else
uint32_t parity : 1,
opcode : 4,
ret : 1,
destination : 9,
source : 9,
immediate : 8;
#endif
};
/* 8bit ALU shift/rotate operations */
struct ins_format2 {
#ifdef __LITTLE_ENDIAN
uint32_t shift_control : 8,
source : 9,
destination : 9,
ret : 1,
opcode : 4,
parity : 1;
#else
uint32_t parity : 1,
opcode : 4,
ret : 1,
destination : 9,
source : 9,
shift_control : 8;
#endif
};
/* 8bit branch control operations */
struct ins_format3 {
#ifdef __LITTLE_ENDIAN
uint32_t immediate : 8,
source : 9,
address : 10,
opcode : 4,
parity : 1;
#else
uint32_t parity : 1,
opcode : 4,
address : 10,
source : 9,
immediate : 8;
#endif
};
/* 16bit ALU logic operations */
struct ins_format4 {
#ifdef __LITTLE_ENDIAN
uint32_t opcode_ext : 8,
source : 9,
destination : 9,
ret : 1,
opcode : 4,
parity : 1;
#else
uint32_t parity : 1,
opcode : 4,
ret : 1,
destination : 9,
source : 9,
opcode_ext : 8;
#endif
};
/* 16bit branch control operations */
struct ins_format5 {
#ifdef __LITTLE_ENDIAN
uint32_t opcode_ext : 8,
source : 9,
address : 10,
opcode : 4,
parity : 1;
#else
uint32_t parity : 1,
opcode : 4,
address : 10,
source : 9,
opcode_ext : 8;
#endif
};
/* Far branch operations */
struct ins_format6 {
#ifdef __LITTLE_ENDIAN
uint32_t page : 3,
opcode_ext : 5,
source : 9,
address : 10,
opcode : 4,
parity : 1;
#else
uint32_t parity : 1,
opcode : 4,
address : 10,
source : 9,
opcode_ext : 5,
page : 3;
#endif
};
union ins_formats {
struct ins_format1 format1;
struct ins_format2 format2;
struct ins_format3 format3;
struct ins_format4 format4;
struct ins_format5 format5;
struct ins_format6 format6;
uint8_t bytes[4];
uint32_t integer;
};
struct instruction {
union ins_formats format;
u_int srcline;
struct symbol *patch_label;
STAILQ_ENTRY(instruction) links;
};
#define AIC_OP_OR 0x0
#define AIC_OP_AND 0x1
#define AIC_OP_XOR 0x2
#define AIC_OP_ADD 0x3
#define AIC_OP_ADC 0x4
#define AIC_OP_ROL 0x5
#define AIC_OP_BMOV 0x6
#define AIC_OP_MVI16 0x7
#define AIC_OP_JMP 0x8
#define AIC_OP_JC 0x9
#define AIC_OP_JNC 0xa
#define AIC_OP_CALL 0xb
#define AIC_OP_JNE 0xc
#define AIC_OP_JNZ 0xd
#define AIC_OP_JE 0xe
#define AIC_OP_JZ 0xf
/* Pseudo Ops */
#define AIC_OP_SHL 0x10
#define AIC_OP_SHR 0x20
#define AIC_OP_ROR 0x30
/* 16bit Ops. Low byte main opcode. High byte extended opcode. */
#define AIC_OP_OR16 0x8005
#define AIC_OP_AND16 0x8105
#define AIC_OP_XOR16 0x8205
#define AIC_OP_ADD16 0x8305
#define AIC_OP_ADC16 0x8405
#define AIC_OP_JNE16 0x8805
#define AIC_OP_JNZ16 0x8905
#define AIC_OP_JE16 0x8C05
#define AIC_OP_JZ16 0x8B05
#define AIC_OP_JMP16 0x9005
#define AIC_OP_JC16 0x9105
#define AIC_OP_JNC16 0x9205
#define AIC_OP_CALL16 0x9305
/* Page extension is low three bits of second opcode byte. */
#define AIC_OP_JMPF 0xA005
#define AIC_OP_CALLF 0xB005
#define AIC_OP_JCF 0xC005
#define AIC_OP_JNCF 0xD005
#define AIC_OP_CMPXCHG 0xE005

165
drivers/scsi/aic7xxx/aicasm/aicasm_macro_gram.y Normal file
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@ -0,0 +1,165 @@
%{
/*
* Sub-parser for macro invocation in the Aic7xxx SCSI
* Host adapter sequencer assembler.
*
* Copyright (c) 2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_macro_gram.y#5 $
*
* $FreeBSD$
*/
#include <sys/types.h>
#include <inttypes.h>
#include <regex.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sysexits.h>
#ifdef __linux__
#include "../queue.h"
#else
#include <sys/queue.h>
#endif
#include "aicasm.h"
#include "aicasm_symbol.h"
#include "aicasm_insformat.h"
static symbol_t *macro_symbol;
static void add_macro_arg(const char *argtext, int position);
void mmerror(const char *string);
%}
%union {
int value;
char *str;
symbol_t *sym;
}
%token <str> T_ARG
%token <sym> T_SYMBOL
%type <value> macro_arglist
%%
macrocall:
T_SYMBOL '('
{
macro_symbol = $1;
}
macro_arglist ')'
{
if (macro_symbol->info.macroinfo->narg != $4) {
printf("Narg == %d", macro_symbol->info.macroinfo->narg);
stop("Too few arguments for macro invocation",
EX_DATAERR);
/* NOTREACHED */
}
macro_symbol = NULL;
YYACCEPT;
}
;
macro_arglist:
{
/* Macros can take 0 arguments */
$$ = 0;
}
| T_ARG
{
$$ = 1;
add_macro_arg($1, 1);
}
| macro_arglist ',' T_ARG
{
if ($1 == 0) {
stop("Comma without preceding argument in arg list",
EX_DATAERR);
/* NOTREACHED */
}
$$ = $1 + 1;
add_macro_arg($3, $$);
}
;
%%
static void
add_macro_arg(const char *argtext, int argnum)
{
struct macro_arg *marg;
int i;
if (macro_symbol == NULL || macro_symbol->type != MACRO) {
stop("Invalid current symbol for adding macro arg",
EX_SOFTWARE);
/* NOTREACHED */
}
/*
* Macro Invocation. Find the appropriate argument and fill
* in the replace ment text for this call.
*/
i = 0;
STAILQ_FOREACH(marg, &macro_symbol->info.macroinfo->args, links) {
i++;
if (i == argnum)
break;
}
if (marg == NULL) {
stop("Too many arguments for macro invocation", EX_DATAERR);
/* NOTREACHED */
}
marg->replacement_text = strdup(argtext);
if (marg->replacement_text == NULL) {
stop("Unable to replicate replacement text", EX_SOFTWARE);
/* NOTREACHED */
}
}
void
mmerror(const char *string)
{
stop(string, EX_DATAERR);
}

157
drivers/scsi/aic7xxx/aicasm/aicasm_macro_scan.l Normal file
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@ -0,0 +1,157 @@
%{
/*
* Sub-Lexical Analyzer for macro invokation in
* the Aic7xxx SCSI Host adapter sequencer assembler.
*
* Copyright (c) 2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_macro_scan.l#8 $
*
* $FreeBSD$
*/
#include <sys/types.h>
#include <inttypes.h>
#include <limits.h>
#include <regex.h>
#include <stdio.h>
#include <string.h>
#include <sysexits.h>
#ifdef __linux__
#include "../queue.h"
#else
#include <sys/queue.h>
#endif
#include "aicasm.h"
#include "aicasm_symbol.h"
#include "aicasm_macro_gram.h"
#define MAX_STR_CONST 4096
static char string_buf[MAX_STR_CONST];
static char *string_buf_ptr;
static int parren_count;
static char buf[255];
int mmlineno;
%}
WORD [A-Za-z_][-A-Za-z_0-9]*
SPACE [ \t]+
MCARG [^(), \t]+
%x ARGLIST
%%
\n {
++mmlineno;
}
\r ;
<ARGLIST>{SPACE} ;
<ARGLIST>\( {
parren_count++;
if (parren_count == 1) {
string_buf_ptr = string_buf;
return ('(');
}
*string_buf_ptr++ = '(';
}
<ARGLIST>\) {
if (parren_count == 1) {
if (string_buf_ptr != string_buf) {
/*
* Return an argument and
* rescan this parren so we
* can return it as well.
*/
*string_buf_ptr = '\0';
mmlval.str = string_buf;
string_buf_ptr = string_buf;
unput(')');
return T_ARG;
}
BEGIN INITIAL;
return (')');
}
parren_count--;
*string_buf_ptr++ = ')';
}
<ARGLIST>{MCARG} {
char *yptr;
yptr = mmtext;
while (*yptr)
*string_buf_ptr++ = *yptr++;
}
<ARGLIST>\, {
if (string_buf_ptr != string_buf) {
/*
* Return an argument and
* rescan this comma so we
* can return it as well.
*/
*string_buf_ptr = '\0';
mmlval.str = string_buf;
string_buf_ptr = string_buf;
unput(',');
return T_ARG;
}
return ',';
}
{WORD}[(] {
/* May be a symbol or a macro invocation. */
mmlval.sym = symtable_get(mmtext);
if (mmlval.sym->type != MACRO) {
stop("Expecting Macro Name",
EX_DATAERR);
}
unput('(');
parren_count = 0;
BEGIN ARGLIST;
return T_SYMBOL;
}
. {
snprintf(buf, sizeof(buf), "Invalid character "
"'%c'", mmtext[0]);
stop(buf, EX_DATAERR);
}
%%
int
mmwrap()
{
stop("EOF encountered in macro call", EX_DATAERR);
}

622
drivers/scsi/aic7xxx/aicasm/aicasm_scan.l Normal file
View file

@ -0,0 +1,622 @@
%{
/*
* Lexical Analyzer for the Aic7xxx SCSI Host adapter sequencer assembler.
*
* Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
* Copyright (c) 2001, 2002 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_scan.l#20 $
*
* $FreeBSD$
*/
#include <sys/types.h>
#include <inttypes.h>
#include <limits.h>
#include <regex.h>
#include <stdio.h>
#include <string.h>
#include <sysexits.h>
#ifdef __linux__
#include "../queue.h"
#else
#include <sys/queue.h>
#endif
#include "aicasm.h"
#include "aicasm_symbol.h"
#include "aicasm_gram.h"
/* This is used for macro body capture too, so err on the large size. */
#define MAX_STR_CONST 4096
static char string_buf[MAX_STR_CONST];
static char *string_buf_ptr;
static int parren_count;
static int quote_count;
static char buf[255];
%}
PATH ([/]*[-A-Za-z0-9_.])+
WORD [A-Za-z_][-A-Za-z_0-9]*
SPACE [ \t]+
MCARG [^(), \t]+
MBODY ((\\[^\n])*[^\n\\]*)+
%x COMMENT
%x CEXPR
%x INCLUDE
%x STRING
%x MACRODEF
%x MACROARGLIST
%x MACROCALLARGS
%x MACROBODY
%%
\n { ++yylineno; }
\r ;
"/*" { BEGIN COMMENT; /* Enter comment eating state */ }
<COMMENT>"/*" { fprintf(stderr, "Warning! Comment within comment."); }
<COMMENT>\n { ++yylineno; }
<COMMENT>[^*/\n]* ;
<COMMENT>"*"+[^*/\n]* ;
<COMMENT>"/"+[^*/\n]* ;
<COMMENT>"*"+"/" { BEGIN INITIAL; }
if[ \t]*\( {
string_buf_ptr = string_buf;
parren_count = 1;
BEGIN CEXPR;
return T_IF;
}
<CEXPR>\( { *string_buf_ptr++ = '('; parren_count++; }
<CEXPR>\) {
parren_count--;
if (parren_count == 0) {
/* All done */
BEGIN INITIAL;
*string_buf_ptr = '\0';
yylval.sym = symtable_get(string_buf);
return T_CEXPR;
} else {
*string_buf_ptr++ = ')';
}
}
<CEXPR>\n { ++yylineno; }
<CEXPR>\r ;
<CEXPR>[^()\n]+ {
char *yptr;
yptr = yytext;
while (*yptr != '\0') {
/* Remove duplicate spaces */
if (*yptr == '\t')
*yptr = ' ';
if (*yptr == ' '
&& string_buf_ptr != string_buf
&& string_buf_ptr[-1] == ' ')
yptr++;
else
*string_buf_ptr++ = *yptr++;
}
}
else { return T_ELSE; }
VERSION { return T_VERSION; }
PREFIX { return T_PREFIX; }
PATCH_ARG_LIST { return T_PATCH_ARG_LIST; }
\" {
string_buf_ptr = string_buf;
BEGIN STRING;
}
<STRING>[^"]+ {
char *yptr;
yptr = yytext;
while (*yptr)
*string_buf_ptr++ = *yptr++;
}
<STRING>\" {
/* All done */
BEGIN INITIAL;
*string_buf_ptr = '\0';
yylval.str = string_buf;
return T_STRING;
}
{SPACE} ;
/* Register/SCB/SRAM definition keywords */
export { return T_EXPORT; }
register { return T_REGISTER; }
const { yylval.value = FALSE; return T_CONST; }
download { return T_DOWNLOAD; }
address { return T_ADDRESS; }
count { return T_COUNT; }
access_mode { return T_ACCESS_MODE; }
dont_generate_debug_code { return T_DONT_GENERATE_DEBUG_CODE; }
modes { return T_MODES; }
RW|RO|WO {
if (strcmp(yytext, "RW") == 0)
yylval.value = RW;
else if (strcmp(yytext, "RO") == 0)
yylval.value = RO;
else
yylval.value = WO;
return T_MODE;
}
field { return T_FIELD; }
enum { return T_ENUM; }
mask { return T_MASK; }
alias { return T_ALIAS; }
size { return T_SIZE; }
scb { return T_SCB; }
scratch_ram { return T_SRAM; }
accumulator { return T_ACCUM; }
mode_pointer { return T_MODE_PTR; }
allones { return T_ALLONES; }
allzeros { return T_ALLZEROS; }
none { return T_NONE; }
sindex { return T_SINDEX; }
A { return T_A; }
/* Instruction Formatting */
PAD_PAGE { return T_PAD_PAGE; }
BEGIN_CRITICAL { return T_BEGIN_CS; }
END_CRITICAL { return T_END_CS; }
SET_SRC_MODE { return T_SET_SRC_MODE; }
SET_DST_MODE { return T_SET_DST_MODE; }
/* Opcodes */
shl { return T_SHL; }
shr { return T_SHR; }
ror { return T_ROR; }
rol { return T_ROL; }
mvi { return T_MVI; }
mov { return T_MOV; }
clr { return T_CLR; }
jmp { return T_JMP; }
jc { return T_JC; }
jnc { return T_JNC; }
je { return T_JE; }
jne { return T_JNE; }
jz { return T_JZ; }
jnz { return T_JNZ; }
call { return T_CALL; }
add { return T_ADD; }
adc { return T_ADC; }
bmov { return T_BMOV; }
inc { return T_INC; }
dec { return T_DEC; }
stc { return T_STC; }
clc { return T_CLC; }
cmp { return T_CMP; }
not { return T_NOT; }
xor { return T_XOR; }
test { return T_TEST;}
and { return T_AND; }
or { return T_OR; }
ret { return T_RET; }
nop { return T_NOP; }
/* ARP2 16bit extensions */
/* or16 { return T_OR16; } */
/* and16 { return T_AND16; }*/
/* xor16 { return T_XOR16; }*/
/* add16 { return T_ADD16; }*/
/* adc16 { return T_ADC16; }*/
/* mvi16 { return T_MVI16; }*/
/* test16 { return T_TEST16; }*/
/* cmp16 { return T_CMP16; }*/
/* cmpxchg { return T_CMPXCHG; }*/
/* Allowed Symbols */
\<\< { return T_EXPR_LSHIFT; }
\>\> { return T_EXPR_RSHIFT; }
[-+,:()~|&."{};<>[\]/*!=] { return yytext[0]; }
/* Number processing */
0[0-7]* {
yylval.value = strtol(yytext, NULL, 8);
return T_NUMBER;
}
0[xX][0-9a-fA-F]+ {
yylval.value = strtoul(yytext + 2, NULL, 16);
return T_NUMBER;
}
[1-9][0-9]* {
yylval.value = strtol(yytext, NULL, 10);
return T_NUMBER;
}
/* Include Files */
#include{SPACE} {
BEGIN INCLUDE;
quote_count = 0;
return T_INCLUDE;
}
<INCLUDE>[<] { return yytext[0]; }
<INCLUDE>[>] { BEGIN INITIAL; return yytext[0]; }
<INCLUDE>[\"] {
if (quote_count != 0)
BEGIN INITIAL;
quote_count++;
return yytext[0];
}
<INCLUDE>{PATH} {
char *yptr;
yptr = yytext;
string_buf_ptr = string_buf;
while (*yptr)
*string_buf_ptr++ = *yptr++;
yylval.str = string_buf;
*string_buf_ptr = '\0';
return T_PATH;
}
<INCLUDE>. { stop("Invalid include line", EX_DATAERR); }
#define{SPACE} {
BEGIN MACRODEF;
return T_DEFINE;
}
<MACRODEF>{WORD}{SPACE} {
char *yptr;
/* Strip space and return as a normal symbol */
yptr = yytext;
while (*yptr != ' ' && *yptr != '\t')
yptr++;
*yptr = '\0';
yylval.sym = symtable_get(yytext);
string_buf_ptr = string_buf;
BEGIN MACROBODY;
return T_SYMBOL;
}
<MACRODEF>{WORD}\( {
/*
* We store the symbol with its opening
* parren so we can differentiate macros
* that take args from macros with the
* same name that do not take args as
* is allowed in C.
*/
BEGIN MACROARGLIST;
yylval.sym = symtable_get(yytext);
unput('(');
return T_SYMBOL;
}
<MACROARGLIST>{WORD} {
yylval.str = yytext;
return T_ARG;
}
<MACROARGLIST>{SPACE} ;
<MACROARGLIST>[(,] {
return yytext[0];
}
<MACROARGLIST>[)] {
string_buf_ptr = string_buf;
BEGIN MACROBODY;
return ')';
}
<MACROARGLIST>. {
snprintf(buf, sizeof(buf), "Invalid character "
"'%c' in macro argument list",
yytext[0]);
stop(buf, EX_DATAERR);
}
<MACROCALLARGS>{SPACE} ;
<MACROCALLARGS>\( {
parren_count++;
if (parren_count == 1)
return ('(');
*string_buf_ptr++ = '(';
}
<MACROCALLARGS>\) {
parren_count--;
if (parren_count == 0) {
BEGIN INITIAL;
return (')');
}
*string_buf_ptr++ = ')';
}
<MACROCALLARGS>{MCARG} {
char *yptr;
yptr = yytext;
while (*yptr)
*string_buf_ptr++ = *yptr++;
}
<MACROCALLARGS>\, {
if (string_buf_ptr != string_buf) {
/*
* Return an argument and
* rescan this comma so we
* can return it as well.
*/
*string_buf_ptr = '\0';
yylval.str = string_buf;
string_buf_ptr = string_buf;
unput(',');
return T_ARG;
}
return ',';
}
<MACROBODY>\\\n {
/* Eat escaped newlines. */
++yylineno;
}
<MACROBODY>\r ;
<MACROBODY>\n {
/* Macros end on the first unescaped newline. */
BEGIN INITIAL;
*string_buf_ptr = '\0';
yylval.str = string_buf;
++yylineno;
return T_MACROBODY;
}
<MACROBODY>{MBODY} {
char *yptr;
char c;
yptr = yytext;
while (c = *yptr++) {
/*
* Strip carriage returns.
*/
if (c == '\r')
continue;
*string_buf_ptr++ = c;
}
}
{WORD}\( {
char *yptr;
char *ycopy;
/* May be a symbol or a macro invocation. */
yylval.sym = symtable_get(yytext);
if (yylval.sym->type == MACRO) {
YY_BUFFER_STATE old_state;
YY_BUFFER_STATE temp_state;
ycopy = strdup(yytext);
yptr = ycopy + yyleng;
while (yptr > ycopy)
unput(*--yptr);
old_state = YY_CURRENT_BUFFER;
temp_state =
yy_create_buffer(stdin,
YY_BUF_SIZE);
yy_switch_to_buffer(temp_state);
mm_switch_to_buffer(old_state);
mmparse();
mm_switch_to_buffer(temp_state);
yy_switch_to_buffer(old_state);
mm_delete_buffer(temp_state);
expand_macro(yylval.sym);
} else {
if (yylval.sym->type == UNINITIALIZED) {
/* Try without the '(' */
symbol_delete(yylval.sym);
yytext[yyleng-1] = '\0';
yylval.sym =
symtable_get(yytext);
}
unput('(');
return T_SYMBOL;
}
}
{WORD} {
yylval.sym = symtable_get(yytext);
if (yylval.sym->type == MACRO) {
expand_macro(yylval.sym);
} else {
return T_SYMBOL;
}
}
. {
snprintf(buf, sizeof(buf), "Invalid character "
"'%c'", yytext[0]);
stop(buf, EX_DATAERR);
}
%%
typedef struct include {
YY_BUFFER_STATE buffer;
int lineno;
char *filename;
SLIST_ENTRY(include) links;
}include_t;
SLIST_HEAD(, include) include_stack;
void
include_file(char *file_name, include_type type)
{
FILE *newfile;
include_t *include;
newfile = NULL;
/* Try the current directory first */
if (includes_search_curdir != 0 || type == SOURCE_FILE)
newfile = fopen(file_name, "r");
if (newfile == NULL && type != SOURCE_FILE) {
path_entry_t include_dir;
for (include_dir = search_path.slh_first;
include_dir != NULL;
include_dir = include_dir->links.sle_next) {
char fullname[PATH_MAX];
if ((include_dir->quoted_includes_only == TRUE)
&& (type != QUOTED_INCLUDE))
continue;
snprintf(fullname, sizeof(fullname),
"%s/%s", include_dir->directory, file_name);
if ((newfile = fopen(fullname, "r")) != NULL)
break;
}
}
if (newfile == NULL) {
perror(file_name);
stop("Unable to open input file", EX_SOFTWARE);
/* NOTREACHED */
}
if (type != SOURCE_FILE) {
include = (include_t *)malloc(sizeof(include_t));
if (include == NULL) {
stop("Unable to allocate include stack entry",
EX_SOFTWARE);
/* NOTREACHED */
}
include->buffer = YY_CURRENT_BUFFER;
include->lineno = yylineno;
include->filename = yyfilename;
SLIST_INSERT_HEAD(&include_stack, include, links);
}
yy_switch_to_buffer(yy_create_buffer(newfile, YY_BUF_SIZE));
yylineno = 1;
yyfilename = strdup(file_name);
}
static void next_substitution(struct symbol *mac_symbol, const char *body_pos,
const char **next_match,
struct macro_arg **match_marg, regmatch_t *match);
void
expand_macro(struct symbol *macro_symbol)
{
struct macro_arg *marg;
struct macro_arg *match_marg;
const char *body_head;
const char *body_pos;
const char *next_match;
/*
* Due to the nature of unput, we must work
* backwards through the macro body performing
* any expansions.
*/
body_head = macro_symbol->info.macroinfo->body;
body_pos = body_head + strlen(body_head);
while (body_pos > body_head) {
regmatch_t match;
next_match = body_head;
match_marg = NULL;
next_substitution(macro_symbol, body_pos, &next_match,
&match_marg, &match);
/* Put back everything up until the replacement. */
while (body_pos > next_match)
unput(*--body_pos);
/* Perform the replacement. */
if (match_marg != NULL) {
const char *strp;
next_match = match_marg->replacement_text;
strp = next_match + strlen(next_match);
while (strp > next_match)
unput(*--strp);
/* Skip past the unexpanded macro arg. */
body_pos -= match.rm_eo - match.rm_so;
}
}
/* Cleanup replacement text. */
STAILQ_FOREACH(marg, &macro_symbol->info.macroinfo->args, links) {
free(marg->replacement_text);
}
}
/*
* Find the next substitution in the macro working backwards from
* body_pos until the beginning of the macro buffer. next_match
* should be initialized to the beginning of the macro buffer prior
* to calling this routine.
*/
static void
next_substitution(struct symbol *mac_symbol, const char *body_pos,
const char **next_match, struct macro_arg **match_marg,
regmatch_t *match)
{
regmatch_t matches[2];
struct macro_arg *marg;
const char *search_pos;
int retval;
do {
search_pos = *next_match;
STAILQ_FOREACH(marg, &mac_symbol->info.macroinfo->args, links) {
retval = regexec(&marg->arg_regex, search_pos, 2,
matches, 0);
if (retval == 0
&& (matches[1].rm_eo + search_pos) <= body_pos
&& (matches[1].rm_eo + search_pos) > *next_match) {
*match = matches[1];
*next_match = match->rm_eo + search_pos;
*match_marg = marg;
}
}
} while (search_pos != *next_match);
}
int
yywrap()
{
include_t *include;
yy_delete_buffer(YY_CURRENT_BUFFER);
(void)fclose(yyin);
if (yyfilename != NULL)
free(yyfilename);
yyfilename = NULL;
include = include_stack.slh_first;
if (include != NULL) {
yy_switch_to_buffer(include->buffer);
yylineno = include->lineno;
yyfilename = include->filename;
SLIST_REMOVE_HEAD(&include_stack, links);
free(include);
return (0);
}
return (1);
}

693
drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c Normal file
View file

@ -0,0 +1,693 @@
/*
* Aic7xxx SCSI host adapter firmware assembler symbol table implementation
*
* Copyright (c) 1997 Justin T. Gibbs.
* Copyright (c) 2002 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_symbol.c#24 $
*
* $FreeBSD$
*/
#include <sys/types.h>
#ifdef __linux__
#include "aicdb.h"
#else
#include <db.h>
#endif
#include <fcntl.h>
#include <inttypes.h>
#include <regex.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sysexits.h>
#include "aicasm_symbol.h"
#include "aicasm.h"
static DB *symtable;
symbol_t *
symbol_create(char *name)
{
symbol_t *new_symbol;
new_symbol = (symbol_t *)malloc(sizeof(symbol_t));
if (new_symbol == NULL) {
perror("Unable to create new symbol");
exit(EX_SOFTWARE);
}
memset(new_symbol, 0, sizeof(*new_symbol));
new_symbol->name = strdup(name);
if (new_symbol->name == NULL)
stop("Unable to strdup symbol name", EX_SOFTWARE);
new_symbol->type = UNINITIALIZED;
new_symbol->count = 1;
return (new_symbol);
}
void
symbol_delete(symbol_t *symbol)
{
if (symtable != NULL) {
DBT key;
key.data = symbol->name;
key.size = strlen(symbol->name);
symtable->del(symtable, &key, /*flags*/0);
}
switch(symbol->type) {
case SCBLOC:
case SRAMLOC:
case REGISTER:
if (symbol->info.rinfo != NULL)
free(symbol->info.rinfo);
break;
case ALIAS:
if (symbol->info.ainfo != NULL)
free(symbol->info.ainfo);
break;
case MASK:
case FIELD:
case ENUM:
case ENUM_ENTRY:
if (symbol->info.finfo != NULL) {
symlist_free(&symbol->info.finfo->symrefs);
free(symbol->info.finfo);
}
break;
case DOWNLOAD_CONST:
case CONST:
if (symbol->info.cinfo != NULL)
free(symbol->info.cinfo);
break;
case LABEL:
if (symbol->info.linfo != NULL)
free(symbol->info.linfo);
break;
case UNINITIALIZED:
default:
break;
}
free(symbol->name);
free(symbol);
}
void
symtable_open()
{
symtable = dbopen(/*filename*/NULL,
O_CREAT | O_NONBLOCK | O_RDWR, /*mode*/0, DB_HASH,
/*openinfo*/NULL);
if (symtable == NULL) {
perror("Symbol table creation failed");
exit(EX_SOFTWARE);
/* NOTREACHED */
}
}
void
symtable_close()
{
if (symtable != NULL) {
DBT key;
DBT data;
while (symtable->seq(symtable, &key, &data, R_FIRST) == 0) {
symbol_t *stored_ptr;
memcpy(&stored_ptr, data.data, sizeof(stored_ptr));
symbol_delete(stored_ptr);
}
symtable->close(symtable);
}
}
/*
* The semantics of get is to return an uninitialized symbol entry
* if a lookup fails.
*/
symbol_t *
symtable_get(char *name)
{
symbol_t *stored_ptr;
DBT key;
DBT data;
int retval;
key.data = (void *)name;
key.size = strlen(name);
if ((retval = symtable->get(symtable, &key, &data, /*flags*/0)) != 0) {
if (retval == -1) {
perror("Symbol table get operation failed");
exit(EX_SOFTWARE);
/* NOTREACHED */
} else if (retval == 1) {
/* Symbol wasn't found, so create a new one */
symbol_t *new_symbol;
new_symbol = symbol_create(name);
data.data = &new_symbol;
data.size = sizeof(new_symbol);
if (symtable->put(symtable, &key, &data,
/*flags*/0) !=0) {
perror("Symtable put failed");
exit(EX_SOFTWARE);
}
return (new_symbol);
} else {
perror("Unexpected return value from db get routine");
exit(EX_SOFTWARE);
/* NOTREACHED */
}
}
memcpy(&stored_ptr, data.data, sizeof(stored_ptr));
stored_ptr->count++;
data.data = &stored_ptr;
if (symtable->put(symtable, &key, &data, /*flags*/0) !=0) {
perror("Symtable put failed");
exit(EX_SOFTWARE);
}
return (stored_ptr);
}
symbol_node_t *
symlist_search(symlist_t *symlist, char *symname)
{
symbol_node_t *curnode;
curnode = SLIST_FIRST(symlist);
while(curnode != NULL) {
if (strcmp(symname, curnode->symbol->name) == 0)
break;
curnode = SLIST_NEXT(curnode, links);
}
return (curnode);
}
void
symlist_add(symlist_t *symlist, symbol_t *symbol, int how)
{
symbol_node_t *newnode;
newnode = (symbol_node_t *)malloc(sizeof(symbol_node_t));
if (newnode == NULL) {
stop("symlist_add: Unable to malloc symbol_node", EX_SOFTWARE);
/* NOTREACHED */
}
newnode->symbol = symbol;
if (how == SYMLIST_SORT) {
symbol_node_t *curnode;
int field;
field = FALSE;
switch(symbol->type) {
case REGISTER:
case SCBLOC:
case SRAMLOC:
break;
case FIELD:
case MASK:
case ENUM:
case ENUM_ENTRY:
field = TRUE;
break;
default:
stop("symlist_add: Invalid symbol type for sorting",
EX_SOFTWARE);
/* NOTREACHED */
}
curnode = SLIST_FIRST(symlist);
if (curnode == NULL
|| (field
&& (curnode->symbol->type > newnode->symbol->type
|| (curnode->symbol->type == newnode->symbol->type
&& (curnode->symbol->info.finfo->value >
newnode->symbol->info.finfo->value))))
|| (!field && (curnode->symbol->info.rinfo->address >
newnode->symbol->info.rinfo->address))) {
SLIST_INSERT_HEAD(symlist, newnode, links);
return;
}
while (1) {
if (SLIST_NEXT(curnode, links) == NULL) {
SLIST_INSERT_AFTER(curnode, newnode,
links);
break;
} else {
symbol_t *cursymbol;
cursymbol = SLIST_NEXT(curnode, links)->symbol;
if ((field
&& (cursymbol->type > symbol->type
|| (cursymbol->type == symbol->type
&& (cursymbol->info.finfo->value >
symbol->info.finfo->value))))
|| (!field
&& (cursymbol->info.rinfo->address >
symbol->info.rinfo->address))) {
SLIST_INSERT_AFTER(curnode, newnode,
links);
break;
}
}
curnode = SLIST_NEXT(curnode, links);
}
} else {
SLIST_INSERT_HEAD(symlist, newnode, links);
}
}
void
symlist_free(symlist_t *symlist)
{
symbol_node_t *node1, *node2;
node1 = SLIST_FIRST(symlist);
while (node1 != NULL) {
node2 = SLIST_NEXT(node1, links);
free(node1);
node1 = node2;
}
SLIST_INIT(symlist);
}
void
symlist_merge(symlist_t *symlist_dest, symlist_t *symlist_src1,
symlist_t *symlist_src2)
{
symbol_node_t *node;
*symlist_dest = *symlist_src1;
while((node = SLIST_FIRST(symlist_src2)) != NULL) {
SLIST_REMOVE_HEAD(symlist_src2, links);
SLIST_INSERT_HEAD(symlist_dest, node, links);
}
/* These are now empty */
SLIST_INIT(symlist_src1);
SLIST_INIT(symlist_src2);
}
void
aic_print_file_prologue(FILE *ofile)
{
if (ofile == NULL)
return;
fprintf(ofile,
"/*\n"
" * DO NOT EDIT - This file is automatically generated\n"
" * from the following source files:\n"
" *\n"
"%s */\n",
versions);
}
void
aic_print_include(FILE *dfile, char *include_file)
{
if (dfile == NULL)
return;
fprintf(dfile, "\n#include \"%s\"\n\n", include_file);
}
void
aic_print_reg_dump_types(FILE *ofile)
{
if (ofile == NULL)
return;
fprintf(ofile,
"typedef int (%sreg_print_t)(u_int, u_int *, u_int);\n"
"typedef struct %sreg_parse_entry {\n"
" char *name;\n"
" uint8_t value;\n"
" uint8_t mask;\n"
"} %sreg_parse_entry_t;\n"
"\n",
prefix, prefix, prefix);
}
static void
aic_print_reg_dump_start(FILE *dfile, symbol_node_t *regnode)
{
if (dfile == NULL)
return;
fprintf(dfile,
"static const %sreg_parse_entry_t %s_parse_table[] = {\n",
prefix,
regnode->symbol->name);
}
static void
aic_print_reg_dump_end(FILE *ofile, FILE *dfile,
symbol_node_t *regnode, u_int num_entries)
{
char *lower_name;
char *letter;
lower_name = strdup(regnode->symbol->name);
if (lower_name == NULL)
stop("Unable to strdup symbol name", EX_SOFTWARE);
for (letter = lower_name; *letter != '\0'; letter++)
*letter = tolower(*letter);
if (dfile != NULL) {
if (num_entries != 0)
fprintf(dfile,
"\n"
"};\n"
"\n");
fprintf(dfile,
"int\n"
"%s%s_print(u_int regvalue, u_int *cur_col, u_int wrap)\n"
"{\n"
" return (%sprint_register(%s%s, %d, \"%s\",\n"
" 0x%02x, regvalue, cur_col, wrap));\n"
"}\n"
"\n",
prefix,
lower_name,
prefix,
num_entries != 0 ? regnode->symbol->name : "NULL",
num_entries != 0 ? "_parse_table" : "",
num_entries,
regnode->symbol->name,
regnode->symbol->info.rinfo->address);
}
fprintf(ofile,
"#if AIC_DEBUG_REGISTERS\n"
"%sreg_print_t %s%s_print;\n"
"#else\n"
"#define %s%s_print(regvalue, cur_col, wrap) \\\n"
" %sprint_register(NULL, 0, \"%s\", 0x%02x, regvalue, cur_col, wrap)\n"
"#endif\n"
"\n",
prefix,
prefix,
lower_name,
prefix,
lower_name,
prefix,
regnode->symbol->name,
regnode->symbol->info.rinfo->address);
}
static void
aic_print_reg_dump_entry(FILE *dfile, symbol_node_t *curnode)
{
int num_tabs;
if (dfile == NULL)
return;
fprintf(dfile,
" { \"%s\",",
curnode->symbol->name);
num_tabs = 3 - (strlen(curnode->symbol->name) + 5) / 8;
while (num_tabs-- > 0)
fputc('\t', dfile);
fprintf(dfile, "0x%02x, 0x%02x }",
curnode->symbol->info.finfo->value,
curnode->symbol->info.finfo->mask);
}
void
symtable_dump(FILE *ofile, FILE *dfile)
{
/*
* Sort the registers by address with a simple insertion sort.
* Put bitmasks next to the first register that defines them.
* Put constants at the end.
*/
symlist_t registers;
symlist_t masks;
symlist_t constants;
symlist_t download_constants;
symlist_t aliases;
symlist_t exported_labels;
symbol_node_t *curnode;
symbol_node_t *regnode;
DBT key;
DBT data;
int flag;
int reg_count = 0, reg_used = 0;
u_int i;
if (symtable == NULL)
return;
SLIST_INIT(&registers);
SLIST_INIT(&masks);
SLIST_INIT(&constants);
SLIST_INIT(&download_constants);
SLIST_INIT(&aliases);
SLIST_INIT(&exported_labels);
flag = R_FIRST;
while (symtable->seq(symtable, &key, &data, flag) == 0) {
symbol_t *cursym;
memcpy(&cursym, data.data, sizeof(cursym));
switch(cursym->type) {
case REGISTER:
case SCBLOC:
case SRAMLOC:
symlist_add(&registers, cursym, SYMLIST_SORT);
break;
case MASK:
case FIELD:
case ENUM:
case ENUM_ENTRY:
symlist_add(&masks, cursym, SYMLIST_SORT);
break;
case CONST:
symlist_add(&constants, cursym,
SYMLIST_INSERT_HEAD);
break;
case DOWNLOAD_CONST:
symlist_add(&download_constants, cursym,
SYMLIST_INSERT_HEAD);
break;
case ALIAS:
symlist_add(&aliases, cursym,
SYMLIST_INSERT_HEAD);
break;
case LABEL:
if (cursym->info.linfo->exported == 0)
break;
symlist_add(&exported_labels, cursym,
SYMLIST_INSERT_HEAD);
break;
default:
break;
}
flag = R_NEXT;
}
/* Register dianostic functions/declarations first. */
aic_print_file_prologue(ofile);
aic_print_reg_dump_types(ofile);
aic_print_file_prologue(dfile);
aic_print_include(dfile, stock_include_file);
SLIST_FOREACH(curnode, &registers, links) {
if (curnode->symbol->dont_generate_debug_code)
continue;
switch(curnode->symbol->type) {
case REGISTER:
case SCBLOC:
case SRAMLOC:
{
symlist_t *fields;
symbol_node_t *fieldnode;
int num_entries;
num_entries = 0;
reg_count++;
if (curnode->symbol->count == 1)
break;
fields = &curnode->symbol->info.rinfo->fields;
SLIST_FOREACH(fieldnode, fields, links) {
if (num_entries == 0)
aic_print_reg_dump_start(dfile,
curnode);
else if (dfile != NULL)
fputs(",\n", dfile);
num_entries++;
aic_print_reg_dump_entry(dfile, fieldnode);
}
aic_print_reg_dump_end(ofile, dfile,
curnode, num_entries);
reg_used++;
}
default:
break;
}
}
fprintf(stderr, "%s: %d of %d register definitions used\n", appname,
reg_used, reg_count);
/* Fold in the masks and bits */
while (SLIST_FIRST(&masks) != NULL) {
char *regname;
curnode = SLIST_FIRST(&masks);
SLIST_REMOVE_HEAD(&masks, links);
regnode = SLIST_FIRST(&curnode->symbol->info.finfo->symrefs);
regname = regnode->symbol->name;
regnode = symlist_search(&registers, regname);
SLIST_INSERT_AFTER(regnode, curnode, links);
}
/* Add the aliases */
while (SLIST_FIRST(&aliases) != NULL) {
char *regname;
curnode = SLIST_FIRST(&aliases);
SLIST_REMOVE_HEAD(&aliases, links);
regname = curnode->symbol->info.ainfo->parent->name;
regnode = symlist_search(&registers, regname);
SLIST_INSERT_AFTER(regnode, curnode, links);
}
/* Output generated #defines. */
while (SLIST_FIRST(&registers) != NULL) {
symbol_node_t *curnode;
u_int value;
char *tab_str;
char *tab_str2;
curnode = SLIST_FIRST(&registers);
SLIST_REMOVE_HEAD(&registers, links);
switch(curnode->symbol->type) {
case REGISTER:
case SCBLOC:
case SRAMLOC:
fprintf(ofile, "\n");
value = curnode->symbol->info.rinfo->address;
tab_str = "\t";
tab_str2 = "\t\t";
break;
case ALIAS:
{
symbol_t *parent;
parent = curnode->symbol->info.ainfo->parent;
value = parent->info.rinfo->address;
tab_str = "\t";
tab_str2 = "\t\t";
break;
}
case MASK:
case FIELD:
case ENUM:
case ENUM_ENTRY:
value = curnode->symbol->info.finfo->value;
tab_str = "\t\t";
tab_str2 = "\t";
break;
default:
value = 0; /* Quiet compiler */
tab_str = NULL;
tab_str2 = NULL;
stop("symtable_dump: Invalid symbol type "
"encountered", EX_SOFTWARE);
break;
}
fprintf(ofile, "#define%s%-16s%s0x%02x\n",
tab_str, curnode->symbol->name, tab_str2,
value);
free(curnode);
}
fprintf(ofile, "\n\n");
while (SLIST_FIRST(&constants) != NULL) {
symbol_node_t *curnode;
curnode = SLIST_FIRST(&constants);
SLIST_REMOVE_HEAD(&constants, links);
fprintf(ofile, "#define\t%-8s\t0x%02x\n",
curnode->symbol->name,
curnode->symbol->info.cinfo->value);
free(curnode);
}
fprintf(ofile, "\n\n/* Downloaded Constant Definitions */\n");
for (i = 0; SLIST_FIRST(&download_constants) != NULL; i++) {
symbol_node_t *curnode;
curnode = SLIST_FIRST(&download_constants);
SLIST_REMOVE_HEAD(&download_constants, links);
fprintf(ofile, "#define\t%-8s\t0x%02x\n",
curnode->symbol->name,
curnode->symbol->info.cinfo->value);
free(curnode);
}
fprintf(ofile, "#define\tDOWNLOAD_CONST_COUNT\t0x%02x\n", i);
fprintf(ofile, "\n\n/* Exported Labels */\n");
while (SLIST_FIRST(&exported_labels) != NULL) {
symbol_node_t *curnode;
curnode = SLIST_FIRST(&exported_labels);
SLIST_REMOVE_HEAD(&exported_labels, links);
fprintf(ofile, "#define\tLABEL_%-8s\t0x%02x\n",
curnode->symbol->name,
curnode->symbol->info.linfo->address);
free(curnode);
}
}

209
drivers/scsi/aic7xxx/aicasm/aicasm_symbol.h Normal file
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@ -0,0 +1,209 @@
/*
* Aic7xxx SCSI host adapter firmware assembler symbol table definitions
*
* Copyright (c) 1997 Justin T. Gibbs.
* Copyright (c) 2002 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_symbol.h#17 $
*
* $FreeBSD$
*/
#ifdef __linux__
#include "../queue.h"
#else
#include <sys/queue.h>
#endif
typedef enum {
UNINITIALIZED,
REGISTER,
ALIAS,
SCBLOC,
SRAMLOC,
ENUM_ENTRY,
FIELD,
MASK,
ENUM,
CONST,
DOWNLOAD_CONST,
LABEL,
CONDITIONAL,
MACRO
} symtype;
typedef enum {
RO = 0x01,
WO = 0x02,
RW = 0x03
}amode_t;
typedef SLIST_HEAD(symlist, symbol_node) symlist_t;
struct reg_info {
u_int address;
int size;
amode_t mode;
symlist_t fields;
uint8_t valid_bitmask;
uint8_t modes;
int typecheck_masks;
};
struct field_info {
symlist_t symrefs;
uint8_t value;
uint8_t mask;
};
struct const_info {
u_int value;
int define;
};
struct alias_info {
struct symbol *parent;
};
struct label_info {
int address;
int exported;
};
struct cond_info {
int func_num;
};
struct macro_arg {
STAILQ_ENTRY(macro_arg) links;
regex_t arg_regex;
char *replacement_text;
};
STAILQ_HEAD(macro_arg_list, macro_arg) args;
struct macro_info {
struct macro_arg_list args;
int narg;
const char* body;
};
typedef struct expression_info {
symlist_t referenced_syms;
int value;
} expression_t;
typedef struct symbol {
char *name;
symtype type;
int count;
union {
struct reg_info *rinfo;
struct field_info *finfo;
struct const_info *cinfo;
struct alias_info *ainfo;
struct label_info *linfo;
struct cond_info *condinfo;
struct macro_info *macroinfo;
} info;
int dont_generate_debug_code;
} symbol_t;
typedef struct symbol_ref {
symbol_t *symbol;
int offset;
} symbol_ref_t;
typedef struct symbol_node {
SLIST_ENTRY(symbol_node) links;
symbol_t *symbol;
} symbol_node_t;
typedef struct critical_section {
TAILQ_ENTRY(critical_section) links;
int begin_addr;
int end_addr;
} critical_section_t;
typedef enum {
SCOPE_ROOT,
SCOPE_IF,
SCOPE_ELSE_IF,
SCOPE_ELSE
} scope_type;
typedef struct patch_info {
int skip_patch;
int skip_instr;
} patch_info_t;
typedef struct scope {
SLIST_ENTRY(scope) scope_stack_links;
TAILQ_ENTRY(scope) scope_links;
TAILQ_HEAD(, scope) inner_scope;
scope_type type;
int inner_scope_patches;
int begin_addr;
int end_addr;
patch_info_t patches[2];
int func_num;
} scope_t;
TAILQ_HEAD(cs_tailq, critical_section);
SLIST_HEAD(scope_list, scope);
TAILQ_HEAD(scope_tailq, scope);
void symbol_delete(symbol_t *symbol);
void symtable_open(void);
void symtable_close(void);
symbol_t *
symtable_get(char *name);
symbol_node_t *
symlist_search(symlist_t *symlist, char *symname);
void
symlist_add(symlist_t *symlist, symbol_t *symbol, int how);
#define SYMLIST_INSERT_HEAD 0x00
#define SYMLIST_SORT 0x01
void symlist_free(symlist_t *symlist);
void symlist_merge(symlist_t *symlist_dest, symlist_t *symlist_src1,
symlist_t *symlist_src2);
void symtable_dump(FILE *ofile, FILE *dfile);

34
drivers/scsi/aic7xxx/aiclib.c Normal file
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@ -0,0 +1,34 @@
/*
* Implementation of Utility functions for all SCSI device types.
*
* Copyright (c) 1997, 1998, 1999 Justin T. Gibbs.
* Copyright (c) 1997, 1998 Kenneth D. Merry.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: src/sys/cam/scsi/scsi_all.c,v 1.38 2002/09/23 04:56:35 mjacob Exp $
* $Id$
*/
#include "aiclib.h"

195
drivers/scsi/aic7xxx/aiclib.h Normal file
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@ -0,0 +1,195 @@
/*
* Largely written by Julian Elischer (julian@tfs.com)
* for TRW Financial Systems.
*
* TRW Financial Systems, in accordance with their agreement with Carnegie
* Mellon University, makes this software available to CMU to distribute
* or use in any manner that they see fit as long as this message is kept with
* the software. For this reason TFS also grants any other persons or
* organisations permission to use or modify this software.
*
* TFS supplies this software to be publicly redistributed
* on the understanding that TFS is not responsible for the correct
* functioning of this software in any circumstances.
*
* Ported to run under 386BSD by Julian Elischer (julian@tfs.com) Sept 1992
*
* $FreeBSD: src/sys/cam/scsi/scsi_all.h,v 1.21 2002/10/08 17:12:44 ken Exp $
*
* Copyright (c) 2003 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id$
*/
#ifndef _AICLIB_H
#define _AICLIB_H
struct scsi_sense
{
uint8_t opcode;
uint8_t byte2;
uint8_t unused[2];
uint8_t length;
uint8_t control;
};
#define SCSI_REV_0 0
#define SCSI_REV_CCS 1
#define SCSI_REV_2 2
#define SCSI_REV_SPC 3
#define SCSI_REV_SPC2 4
struct scsi_sense_data
{
uint8_t error_code;
#define SSD_ERRCODE 0x7F
#define SSD_CURRENT_ERROR 0x70
#define SSD_DEFERRED_ERROR 0x71
#define SSD_ERRCODE_VALID 0x80
uint8_t segment;
uint8_t flags;
#define SSD_KEY 0x0F
#define SSD_KEY_NO_SENSE 0x00
#define SSD_KEY_RECOVERED_ERROR 0x01
#define SSD_KEY_NOT_READY 0x02
#define SSD_KEY_MEDIUM_ERROR 0x03
#define SSD_KEY_HARDWARE_ERROR 0x04
#define SSD_KEY_ILLEGAL_REQUEST 0x05
#define SSD_KEY_UNIT_ATTENTION 0x06
#define SSD_KEY_DATA_PROTECT 0x07
#define SSD_KEY_BLANK_CHECK 0x08
#define SSD_KEY_Vendor_Specific 0x09
#define SSD_KEY_COPY_ABORTED 0x0a
#define SSD_KEY_ABORTED_COMMAND 0x0b
#define SSD_KEY_EQUAL 0x0c
#define SSD_KEY_VOLUME_OVERFLOW 0x0d
#define SSD_KEY_MISCOMPARE 0x0e
#define SSD_KEY_RESERVED 0x0f
#define SSD_ILI 0x20
#define SSD_EOM 0x40
#define SSD_FILEMARK 0x80
uint8_t info[4];
uint8_t extra_len;
uint8_t cmd_spec_info[4];
uint8_t add_sense_code;
uint8_t add_sense_code_qual;
uint8_t fru;
uint8_t sense_key_spec[3];
#define SSD_SCS_VALID 0x80
#define SSD_FIELDPTR_CMD 0x40
#define SSD_BITPTR_VALID 0x08
#define SSD_BITPTR_VALUE 0x07
#define SSD_MIN_SIZE 18
uint8_t extra_bytes[14];
#define SSD_FULL_SIZE sizeof(struct scsi_sense_data)
};
/*
* Status Byte
*/
#define SCSI_STATUS_OK 0x00
#define SCSI_STATUS_CHECK_COND 0x02
#define SCSI_STATUS_COND_MET 0x04
#define SCSI_STATUS_BUSY 0x08
#define SCSI_STATUS_INTERMED 0x10
#define SCSI_STATUS_INTERMED_COND_MET 0x14
#define SCSI_STATUS_RESERV_CONFLICT 0x18
#define SCSI_STATUS_CMD_TERMINATED 0x22 /* Obsolete in SAM-2 */
#define SCSI_STATUS_QUEUE_FULL 0x28
#define SCSI_STATUS_ACA_ACTIVE 0x30
#define SCSI_STATUS_TASK_ABORTED 0x40
/************************* Large Disk Handling ********************************/
static inline int
aic_sector_div(sector_t capacity, int heads, int sectors)
{
/* ugly, ugly sector_div calling convention.. */
sector_div(capacity, (heads * sectors));
return (int)capacity;
}
static inline uint32_t
scsi_4btoul(uint8_t *bytes)
{
uint32_t rv;
rv = (bytes[0] << 24) |
(bytes[1] << 16) |
(bytes[2] << 8) |
bytes[3];
return (rv);
}
/* Macros for generating the elements of the PCI ID tables. */
#define GETID(v, s) (unsigned)(((v) >> (s)) & 0xFFFF ?: PCI_ANY_ID)
#define ID_C(x, c) \
{ \
GETID(x,32), GETID(x,48), GETID(x,0), GETID(x,16), \
(c) << 8, 0xFFFF00, 0 \
}
#define ID2C(x) \
ID_C(x, PCI_CLASS_STORAGE_SCSI), \
ID_C(x, PCI_CLASS_STORAGE_RAID)
#define IDIROC(x) ((x) | ~ID_ALL_IROC_MASK)
/* Generate IDs for all 16 possibilites.
* The argument has already masked out
* the 4 least significant bits of the device id.
* (e.g., mask: ID_9005_GENERIC_MASK).
*/
#define ID16(x) \
ID(x), \
ID((x) | 0x0001000000000000ull), \
ID((x) | 0x0002000000000000ull), \
ID((x) | 0x0003000000000000ull), \
ID((x) | 0x0004000000000000ull), \
ID((x) | 0x0005000000000000ull), \
ID((x) | 0x0006000000000000ull), \
ID((x) | 0x0007000000000000ull), \
ID((x) | 0x0008000000000000ull), \
ID((x) | 0x0009000000000000ull), \
ID((x) | 0x000A000000000000ull), \
ID((x) | 0x000B000000000000ull), \
ID((x) | 0x000C000000000000ull), \
ID((x) | 0x000D000000000000ull), \
ID((x) | 0x000E000000000000ull), \
ID((x) | 0x000F000000000000ull)
#endif /*_AICLIB_H */

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drivers/scsi/aic7xxx/cam.h Normal file
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/*
* Data structures and definitions for the CAM system.
*
* Copyright (c) 1997 Justin T. Gibbs.
* Copyright (c) 2000 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL").
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/cam.h#15 $
*/
#ifndef _AIC7XXX_CAM_H
#define _AIC7XXX_CAM_H 1
#include <linux/types.h>
#define CAM_BUS_WILDCARD ((u_int)~0)
#define CAM_TARGET_WILDCARD ((u_int)~0)
#define CAM_LUN_WILDCARD ((u_int)~0)
/* CAM Status field values */
typedef enum {
CAM_REQ_INPROG, /* CCB request is in progress */
CAM_REQ_CMP, /* CCB request completed without error */
CAM_REQ_ABORTED, /* CCB request aborted by the host */
CAM_UA_ABORT, /* Unable to abort CCB request */
CAM_REQ_CMP_ERR, /* CCB request completed with an error */
CAM_BUSY, /* CAM subsystem is busy */
CAM_REQ_INVALID, /* CCB request was invalid */
CAM_PATH_INVALID, /* Supplied Path ID is invalid */
CAM_SEL_TIMEOUT, /* Target Selection Timeout */
CAM_CMD_TIMEOUT, /* Command timeout */
CAM_SCSI_STATUS_ERROR, /* SCSI error, look at error code in CCB */
CAM_SCSI_BUS_RESET, /* SCSI Bus Reset Sent/Received */
CAM_UNCOR_PARITY, /* Uncorrectable parity error occurred */
CAM_AUTOSENSE_FAIL, /* Autosense: request sense cmd fail */
CAM_NO_HBA, /* No HBA Detected Error */
CAM_DATA_RUN_ERR, /* Data Overrun error */
CAM_UNEXP_BUSFREE, /* Unexpected Bus Free */
CAM_SEQUENCE_FAIL, /* Protocol Violation */
CAM_CCB_LEN_ERR, /* CCB length supplied is inadequate */
CAM_PROVIDE_FAIL, /* Unable to provide requested capability */
CAM_BDR_SENT, /* A SCSI BDR msg was sent to target */
CAM_REQ_TERMIO, /* CCB request terminated by the host */
CAM_UNREC_HBA_ERROR, /* Unrecoverable Host Bus Adapter Error */
CAM_REQ_TOO_BIG, /* The request was too large for this host */
CAM_UA_TERMIO, /* Unable to terminate I/O CCB request */
CAM_MSG_REJECT_REC, /* Message Reject Received */
CAM_DEV_NOT_THERE, /* SCSI Device Not Installed/there */
CAM_RESRC_UNAVAIL, /* Resource Unavailable */
/*
* This request should be requeued to preserve
* transaction ordering. This typically occurs
* when the SIM recognizes an error that should
* freeze the queue and must place additional
* requests for the target at the sim level
* back into the XPT queue.
*/
CAM_REQUEUE_REQ,
CAM_DEV_QFRZN = 0x40,
CAM_STATUS_MASK = 0x3F
} cam_status;
/*
* Definitions for the asynchronous callback CCB fields.
*/
typedef enum {
AC_GETDEV_CHANGED = 0x800,/* Getdev info might have changed */
AC_INQ_CHANGED = 0x400,/* Inquiry info might have changed */
AC_TRANSFER_NEG = 0x200,/* New transfer settings in effect */
AC_LOST_DEVICE = 0x100,/* A device went away */
AC_FOUND_DEVICE = 0x080,/* A new device was found */
AC_PATH_DEREGISTERED = 0x040,/* A path has de-registered */
AC_PATH_REGISTERED = 0x020,/* A new path has been registered */
AC_SENT_BDR = 0x010,/* A BDR message was sent to target */
AC_SCSI_AEN = 0x008,/* A SCSI AEN has been received */
AC_UNSOL_RESEL = 0x002,/* Unsolicited reselection occurred */
AC_BUS_RESET = 0x001 /* A SCSI bus reset occurred */
} ac_code;
typedef enum {
CAM_DIR_IN = DMA_FROM_DEVICE,
CAM_DIR_OUT = DMA_TO_DEVICE,
CAM_DIR_NONE = DMA_NONE,
} ccb_flags;
#endif /* _AIC7XXX_CAM_H */

501
drivers/scsi/aic7xxx/queue.h Normal file
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/*
* Copyright (c) 1991, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)queue.h 8.5 (Berkeley) 8/20/94
* $FreeBSD: src/sys/sys/queue.h,v 1.38 2000/05/26 02:06:56 jake Exp $
*/
#ifndef _SYS_QUEUE_H_
#define _SYS_QUEUE_H_
/*
* This file defines five types of data structures: singly-linked lists,
* singly-linked tail queues, lists, tail queues, and circular queues.
*
* A singly-linked list is headed by a single forward pointer. The elements
* are singly linked for minimum space and pointer manipulation overhead at
* the expense of O(n) removal for arbitrary elements. New elements can be
* added to the list after an existing element or at the head of the list.
* Elements being removed from the head of the list should use the explicit
* macro for this purpose for optimum efficiency. A singly-linked list may
* only be traversed in the forward direction. Singly-linked lists are ideal
* for applications with large datasets and few or no removals or for
* implementing a LIFO queue.
*
* A singly-linked tail queue is headed by a pair of pointers, one to the
* head of the list and the other to the tail of the list. The elements are
* singly linked for minimum space and pointer manipulation overhead at the
* expense of O(n) removal for arbitrary elements. New elements can be added
* to the list after an existing element, at the head of the list, or at the
* end of the list. Elements being removed from the head of the tail queue
* should use the explicit macro for this purpose for optimum efficiency.
* A singly-linked tail queue may only be traversed in the forward direction.
* Singly-linked tail queues are ideal for applications with large datasets
* and few or no removals or for implementing a FIFO queue.
*
* A list is headed by a single forward pointer (or an array of forward
* pointers for a hash table header). The elements are doubly linked
* so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before
* or after an existing element or at the head of the list. A list
* may only be traversed in the forward direction.
*
* A tail queue is headed by a pair of pointers, one to the head of the
* list and the other to the tail of the list. The elements are doubly
* linked so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before or
* after an existing element, at the head of the list, or at the end of
* the list. A tail queue may be traversed in either direction.
*
* A circle queue is headed by a pair of pointers, one to the head of the
* list and the other to the tail of the list. The elements are doubly
* linked so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before or after
* an existing element, at the head of the list, or at the end of the list.
* A circle queue may be traversed in either direction, but has a more
* complex end of list detection.
*
* For details on the use of these macros, see the queue(3) manual page.
*
*
* SLIST LIST STAILQ TAILQ CIRCLEQ
* _HEAD + + + + +
* _HEAD_INITIALIZER + + + + +
* _ENTRY + + + + +
* _INIT + + + + +
* _EMPTY + + + + +
* _FIRST + + + + +
* _NEXT + + + + +
* _PREV - - - + +
* _LAST - - + + +
* _FOREACH + + + + +
* _FOREACH_REVERSE - - - + +
* _INSERT_HEAD + + + + +
* _INSERT_BEFORE - + - + +
* _INSERT_AFTER + + + + +
* _INSERT_TAIL - - + + +
* _REMOVE_HEAD + - + - -
* _REMOVE + + + + +
*
*/
/*
* Singly-linked List declarations.
*/
#define SLIST_HEAD(name, type) \
struct name { \
struct type *slh_first; /* first element */ \
}
#define SLIST_HEAD_INITIALIZER(head) \
{ NULL }
#define SLIST_ENTRY(type) \
struct { \
struct type *sle_next; /* next element */ \
}
/*
* Singly-linked List functions.
*/
#define SLIST_EMPTY(head) ((head)->slh_first == NULL)
#define SLIST_FIRST(head) ((head)->slh_first)
#define SLIST_FOREACH(var, head, field) \
for ((var) = SLIST_FIRST((head)); \
(var); \
(var) = SLIST_NEXT((var), field))
#define SLIST_INIT(head) do { \
SLIST_FIRST((head)) = NULL; \
} while (0)
#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \
SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field); \
SLIST_NEXT((slistelm), field) = (elm); \
} while (0)
#define SLIST_INSERT_HEAD(head, elm, field) do { \
SLIST_NEXT((elm), field) = SLIST_FIRST((head)); \
SLIST_FIRST((head)) = (elm); \
} while (0)
#define SLIST_NEXT(elm, field) ((elm)->field.sle_next)
#define SLIST_REMOVE(head, elm, type, field) do { \
if (SLIST_FIRST((head)) == (elm)) { \
SLIST_REMOVE_HEAD((head), field); \
} \
else { \
struct type *curelm = SLIST_FIRST((head)); \
while (SLIST_NEXT(curelm, field) != (elm)) \
curelm = SLIST_NEXT(curelm, field); \
SLIST_NEXT(curelm, field) = \
SLIST_NEXT(SLIST_NEXT(curelm, field), field); \
} \
} while (0)
#define SLIST_REMOVE_HEAD(head, field) do { \
SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field); \
} while (0)
/*
* Singly-linked Tail queue declarations.
*/
#define STAILQ_HEAD(name, type) \
struct name { \
struct type *stqh_first;/* first element */ \
struct type **stqh_last;/* addr of last next element */ \
}
#define STAILQ_HEAD_INITIALIZER(head) \
{ NULL, &(head).stqh_first }
#define STAILQ_ENTRY(type) \
struct { \
struct type *stqe_next; /* next element */ \
}
/*
* Singly-linked Tail queue functions.
*/
#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL)
#define STAILQ_FIRST(head) ((head)->stqh_first)
#define STAILQ_FOREACH(var, head, field) \
for((var) = STAILQ_FIRST((head)); \
(var); \
(var) = STAILQ_NEXT((var), field))
#define STAILQ_INIT(head) do { \
STAILQ_FIRST((head)) = NULL; \
(head)->stqh_last = &STAILQ_FIRST((head)); \
} while (0)
#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \
if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
STAILQ_NEXT((tqelm), field) = (elm); \
} while (0)
#define STAILQ_INSERT_HEAD(head, elm, field) do { \
if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL) \
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
STAILQ_FIRST((head)) = (elm); \
} while (0)
#define STAILQ_INSERT_TAIL(head, elm, field) do { \
STAILQ_NEXT((elm), field) = NULL; \
STAILQ_LAST((head)) = (elm); \
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
} while (0)
#define STAILQ_LAST(head) (*(head)->stqh_last)
#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next)
#define STAILQ_REMOVE(head, elm, type, field) do { \
if (STAILQ_FIRST((head)) == (elm)) { \
STAILQ_REMOVE_HEAD(head, field); \
} \
else { \
struct type *curelm = STAILQ_FIRST((head)); \
while (STAILQ_NEXT(curelm, field) != (elm)) \
curelm = STAILQ_NEXT(curelm, field); \
if ((STAILQ_NEXT(curelm, field) = \
STAILQ_NEXT(STAILQ_NEXT(curelm, field), field)) == NULL)\
(head)->stqh_last = &STAILQ_NEXT((curelm), field);\
} \
} while (0)
#define STAILQ_REMOVE_HEAD(head, field) do { \
if ((STAILQ_FIRST((head)) = \
STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL) \
(head)->stqh_last = &STAILQ_FIRST((head)); \
} while (0)
#define STAILQ_REMOVE_HEAD_UNTIL(head, elm, field) do { \
if ((STAILQ_FIRST((head)) = STAILQ_NEXT((elm), field)) == NULL) \
(head)->stqh_last = &STAILQ_FIRST((head)); \
} while (0)
/*
* List declarations.
*/
#define LIST_HEAD(name, type) \
struct name { \
struct type *lh_first; /* first element */ \
}
#define LIST_HEAD_INITIALIZER(head) \
{ NULL }
#define LIST_ENTRY(type) \
struct { \
struct type *le_next; /* next element */ \
struct type **le_prev; /* address of previous next element */ \
}
/*
* List functions.
*/
#define LIST_EMPTY(head) ((head)->lh_first == NULL)
#define LIST_FIRST(head) ((head)->lh_first)
#define LIST_FOREACH(var, head, field) \
for ((var) = LIST_FIRST((head)); \
(var); \
(var) = LIST_NEXT((var), field))
#define LIST_INIT(head) do { \
LIST_FIRST((head)) = NULL; \
} while (0)
#define LIST_INSERT_AFTER(listelm, elm, field) do { \
if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\
LIST_NEXT((listelm), field)->field.le_prev = \
&LIST_NEXT((elm), field); \
LIST_NEXT((listelm), field) = (elm); \
(elm)->field.le_prev = &LIST_NEXT((listelm), field); \
} while (0)
#define LIST_INSERT_BEFORE(listelm, elm, field) do { \
(elm)->field.le_prev = (listelm)->field.le_prev; \
LIST_NEXT((elm), field) = (listelm); \
*(listelm)->field.le_prev = (elm); \
(listelm)->field.le_prev = &LIST_NEXT((elm), field); \
} while (0)
#define LIST_INSERT_HEAD(head, elm, field) do { \
if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL) \
LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\
LIST_FIRST((head)) = (elm); \
(elm)->field.le_prev = &LIST_FIRST((head)); \
} while (0)
#define LIST_NEXT(elm, field) ((elm)->field.le_next)
#define LIST_REMOVE(elm, field) do { \
if (LIST_NEXT((elm), field) != NULL) \
LIST_NEXT((elm), field)->field.le_prev = \
(elm)->field.le_prev; \
*(elm)->field.le_prev = LIST_NEXT((elm), field); \
} while (0)
/*
* Tail queue declarations.
*/
#define TAILQ_HEAD(name, type) \
struct name { \
struct type *tqh_first; /* first element */ \
struct type **tqh_last; /* addr of last next element */ \
}
#define TAILQ_HEAD_INITIALIZER(head) \
{ NULL, &(head).tqh_first }
#define TAILQ_ENTRY(type) \
struct { \
struct type *tqe_next; /* next element */ \
struct type **tqe_prev; /* address of previous next element */ \
}
/*
* Tail queue functions.
*/
#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL)
#define TAILQ_FIRST(head) ((head)->tqh_first)
#define TAILQ_FOREACH(var, head, field) \
for ((var) = TAILQ_FIRST((head)); \
(var); \
(var) = TAILQ_NEXT((var), field))
#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \
for ((var) = TAILQ_LAST((head), headname); \
(var); \
(var) = TAILQ_PREV((var), headname, field))
#define TAILQ_INIT(head) do { \
TAILQ_FIRST((head)) = NULL; \
(head)->tqh_last = &TAILQ_FIRST((head)); \
} while (0)
#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\
TAILQ_NEXT((elm), field)->field.tqe_prev = \
&TAILQ_NEXT((elm), field); \
else \
(head)->tqh_last = &TAILQ_NEXT((elm), field); \
TAILQ_NEXT((listelm), field) = (elm); \
(elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \
} while (0)
#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
(elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
TAILQ_NEXT((elm), field) = (listelm); \
*(listelm)->field.tqe_prev = (elm); \
(listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \
} while (0)
#define TAILQ_INSERT_HEAD(head, elm, field) do { \
if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \
TAILQ_FIRST((head))->field.tqe_prev = \
&TAILQ_NEXT((elm), field); \
else \
(head)->tqh_last = &TAILQ_NEXT((elm), field); \
TAILQ_FIRST((head)) = (elm); \
(elm)->field.tqe_prev = &TAILQ_FIRST((head)); \
} while (0)
#define TAILQ_INSERT_TAIL(head, elm, field) do { \
TAILQ_NEXT((elm), field) = NULL; \
(elm)->field.tqe_prev = (head)->tqh_last; \
*(head)->tqh_last = (elm); \
(head)->tqh_last = &TAILQ_NEXT((elm), field); \
} while (0)
#define TAILQ_LAST(head, headname) \
(*(((struct headname *)((head)->tqh_last))->tqh_last))
#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
#define TAILQ_PREV(elm, headname, field) \
(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
#define TAILQ_REMOVE(head, elm, field) do { \
if ((TAILQ_NEXT((elm), field)) != NULL) \
TAILQ_NEXT((elm), field)->field.tqe_prev = \
(elm)->field.tqe_prev; \
else \
(head)->tqh_last = (elm)->field.tqe_prev; \
*(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \
} while (0)
/*
* Circular queue declarations.
*/
#define CIRCLEQ_HEAD(name, type) \
struct name { \
struct type *cqh_first; /* first element */ \
struct type *cqh_last; /* last element */ \
}
#define CIRCLEQ_HEAD_INITIALIZER(head) \
{ (void *)&(head), (void *)&(head) }
#define CIRCLEQ_ENTRY(type) \
struct { \
struct type *cqe_next; /* next element */ \
struct type *cqe_prev; /* previous element */ \
}
/*
* Circular queue functions.
*/
#define CIRCLEQ_EMPTY(head) ((head)->cqh_first == (void *)(head))
#define CIRCLEQ_FIRST(head) ((head)->cqh_first)
#define CIRCLEQ_FOREACH(var, head, field) \
for ((var) = CIRCLEQ_FIRST((head)); \
(var) != (void *)(head); \
(var) = CIRCLEQ_NEXT((var), field))
#define CIRCLEQ_FOREACH_REVERSE(var, head, field) \
for ((var) = CIRCLEQ_LAST((head)); \
(var) != (void *)(head); \
(var) = CIRCLEQ_PREV((var), field))
#define CIRCLEQ_INIT(head) do { \
CIRCLEQ_FIRST((head)) = (void *)(head); \
CIRCLEQ_LAST((head)) = (void *)(head); \
} while (0)
#define CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
CIRCLEQ_NEXT((elm), field) = CIRCLEQ_NEXT((listelm), field); \
CIRCLEQ_PREV((elm), field) = (listelm); \
if (CIRCLEQ_NEXT((listelm), field) == (void *)(head)) \
CIRCLEQ_LAST((head)) = (elm); \
else \
CIRCLEQ_PREV(CIRCLEQ_NEXT((listelm), field), field) = (elm);\
CIRCLEQ_NEXT((listelm), field) = (elm); \
} while (0)
#define CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \
CIRCLEQ_NEXT((elm), field) = (listelm); \
CIRCLEQ_PREV((elm), field) = CIRCLEQ_PREV((listelm), field); \
if (CIRCLEQ_PREV((listelm), field) == (void *)(head)) \
CIRCLEQ_FIRST((head)) = (elm); \
else \
CIRCLEQ_NEXT(CIRCLEQ_PREV((listelm), field), field) = (elm);\
CIRCLEQ_PREV((listelm), field) = (elm); \
} while (0)
#define CIRCLEQ_INSERT_HEAD(head, elm, field) do { \
CIRCLEQ_NEXT((elm), field) = CIRCLEQ_FIRST((head)); \
CIRCLEQ_PREV((elm), field) = (void *)(head); \
if (CIRCLEQ_LAST((head)) == (void *)(head)) \
CIRCLEQ_LAST((head)) = (elm); \
else \
CIRCLEQ_PREV(CIRCLEQ_FIRST((head)), field) = (elm); \
CIRCLEQ_FIRST((head)) = (elm); \
} while (0)
#define CIRCLEQ_INSERT_TAIL(head, elm, field) do { \
CIRCLEQ_NEXT((elm), field) = (void *)(head); \
CIRCLEQ_PREV((elm), field) = CIRCLEQ_LAST((head)); \
if (CIRCLEQ_FIRST((head)) == (void *)(head)) \
CIRCLEQ_FIRST((head)) = (elm); \
else \
CIRCLEQ_NEXT(CIRCLEQ_LAST((head)), field) = (elm); \
CIRCLEQ_LAST((head)) = (elm); \
} while (0)
#define CIRCLEQ_LAST(head) ((head)->cqh_last)
#define CIRCLEQ_NEXT(elm,field) ((elm)->field.cqe_next)
#define CIRCLEQ_PREV(elm,field) ((elm)->field.cqe_prev)
#define CIRCLEQ_REMOVE(head, elm, field) do { \
if (CIRCLEQ_NEXT((elm), field) == (void *)(head)) \
CIRCLEQ_LAST((head)) = CIRCLEQ_PREV((elm), field); \
else \
CIRCLEQ_PREV(CIRCLEQ_NEXT((elm), field), field) = \
CIRCLEQ_PREV((elm), field); \
if (CIRCLEQ_PREV((elm), field) == (void *)(head)) \
CIRCLEQ_FIRST((head)) = CIRCLEQ_NEXT((elm), field); \
else \
CIRCLEQ_NEXT(CIRCLEQ_PREV((elm), field), field) = \
CIRCLEQ_NEXT((elm), field); \
} while (0)
#endif /* !_SYS_QUEUE_H_ */

39
drivers/scsi/aic7xxx/scsi_iu.h Normal file
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/*
* This file is in the public domain.
*/
#ifndef _SCSI_SCSI_IU_H
#define _SCSI_SCSI_IU_H 1
struct scsi_status_iu_header
{
u_int8_t reserved[2];
u_int8_t flags;
#define SIU_SNSVALID 0x2
#define SIU_RSPVALID 0x1
u_int8_t status;
u_int8_t sense_length[4];
u_int8_t pkt_failures_length[4];
u_int8_t pkt_failures[1];
};
#define SIU_PKTFAIL_OFFSET(siu) 12
#define SIU_PKTFAIL_CODE(siu) (scsi_4btoul((siu)->pkt_failures) & 0xFF)
#define SIU_PFC_NONE 0
#define SIU_PFC_CIU_FIELDS_INVALID 2
#define SIU_PFC_TMF_NOT_SUPPORTED 4
#define SIU_PFC_TMF_FAILED 5
#define SIU_PFC_INVALID_TYPE_CODE 6
#define SIU_PFC_ILLEGAL_REQUEST 7
#define SIU_SENSE_OFFSET(siu) \
(12 + (((siu)->flags & SIU_RSPVALID) \
? scsi_4btoul((siu)->pkt_failures_length) \
: 0))
#define SIU_TASKMGMT_NONE 0x00
#define SIU_TASKMGMT_ABORT_TASK 0x01
#define SIU_TASKMGMT_ABORT_TASK_SET 0x02
#define SIU_TASKMGMT_CLEAR_TASK_SET 0x04
#define SIU_TASKMGMT_LUN_RESET 0x08
#define SIU_TASKMGMT_TARGET_RESET 0x20
#define SIU_TASKMGMT_CLEAR_ACA 0x40
#endif /*_SCSI_SCSI_IU_H*/

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