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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 17:02:46 -04:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
324
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
Normal file
324
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
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@ -0,0 +1,324 @@
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/*
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* Interface for the 93C66/56/46/26/06 serial eeprom parts.
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*
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* Copyright (c) 1995, 1996 Daniel M. Eischen
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL").
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: //depot/aic7xxx/aic7xxx/aic7xxx_93cx6.c#19 $
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*/
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/*
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* The instruction set of the 93C66/56/46/26/06 chips are as follows:
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*
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* Start OP *
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* Function Bit Code Address** Data Description
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* -------------------------------------------------------------------
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* READ 1 10 A5 - A0 Reads data stored in memory,
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* starting at specified address
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* EWEN 1 00 11XXXX Write enable must precede
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* all programming modes
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* ERASE 1 11 A5 - A0 Erase register A5A4A3A2A1A0
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* WRITE 1 01 A5 - A0 D15 - D0 Writes register
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* ERAL 1 00 10XXXX Erase all registers
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* WRAL 1 00 01XXXX D15 - D0 Writes to all registers
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* EWDS 1 00 00XXXX Disables all programming
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* instructions
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* *Note: A value of X for address is a don't care condition.
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* **Note: There are 8 address bits for the 93C56/66 chips unlike
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* the 93C46/26/06 chips which have 6 address bits.
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*
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* The 93C46 has a four wire interface: clock, chip select, data in, and
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* data out. In order to perform one of the above functions, you need
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* to enable the chip select for a clock period (typically a minimum of
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* 1 usec, with the clock high and low a minimum of 750 and 250 nsec
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* respectively). While the chip select remains high, you can clock in
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* the instructions (above) starting with the start bit, followed by the
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* OP code, Address, and Data (if needed). For the READ instruction, the
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* requested 16-bit register contents is read from the data out line but
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* is preceded by an initial zero (leading 0, followed by 16-bits, MSB
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* first). The clock cycling from low to high initiates the next data
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* bit to be sent from the chip.
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*/
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#ifdef __linux__
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#include "aic7xxx_osm.h"
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#include "aic7xxx_inline.h"
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#include "aic7xxx_93cx6.h"
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#else
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#include <dev/aic7xxx/aic7xxx_osm.h>
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#include <dev/aic7xxx/aic7xxx_inline.h>
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#include <dev/aic7xxx/aic7xxx_93cx6.h>
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#endif
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/*
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* Right now, we only have to read the SEEPROM. But we make it easier to
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* add other 93Cx6 functions.
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*/
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struct seeprom_cmd {
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uint8_t len;
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uint8_t bits[11];
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};
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/* Short opcodes for the c46 */
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static const struct seeprom_cmd seeprom_ewen = {9, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
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static const struct seeprom_cmd seeprom_ewds = {9, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
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/* Long opcodes for the C56/C66 */
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static const struct seeprom_cmd seeprom_long_ewen = {11, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
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static const struct seeprom_cmd seeprom_long_ewds = {11, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
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/* Common opcodes */
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static const struct seeprom_cmd seeprom_write = {3, {1, 0, 1}};
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static const struct seeprom_cmd seeprom_read = {3, {1, 1, 0}};
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/*
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* Wait for the SEERDY to go high; about 800 ns.
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*/
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#define CLOCK_PULSE(sd, rdy) \
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while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) { \
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; /* Do nothing */ \
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} \
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(void)SEEPROM_INB(sd); /* Clear clock */
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/*
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* Send a START condition and the given command
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*/
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static void
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send_seeprom_cmd(struct seeprom_descriptor *sd, const struct seeprom_cmd *cmd)
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{
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uint8_t temp;
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int i = 0;
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/* Send chip select for one clock cycle. */
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temp = sd->sd_MS ^ sd->sd_CS;
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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for (i = 0; i < cmd->len; i++) {
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if (cmd->bits[i] != 0)
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temp ^= sd->sd_DO;
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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if (cmd->bits[i] != 0)
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temp ^= sd->sd_DO;
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}
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}
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/*
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* Clear CS put the chip in the reset state, where it can wait for new commands.
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*/
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static void
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reset_seeprom(struct seeprom_descriptor *sd)
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{
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uint8_t temp;
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temp = sd->sd_MS;
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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}
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/*
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* Read the serial EEPROM and returns 1 if successful and 0 if
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* not successful.
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*/
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int
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ahc_read_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
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u_int start_addr, u_int count)
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{
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int i = 0;
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u_int k = 0;
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uint16_t v;
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uint8_t temp;
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/*
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* Read the requested registers of the seeprom. The loop
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* will range from 0 to count-1.
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*/
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for (k = start_addr; k < count + start_addr; k++) {
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/*
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* Now we're ready to send the read command followed by the
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* address of the 16-bit register we want to read.
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*/
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send_seeprom_cmd(sd, &seeprom_read);
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/* Send the 6 or 8 bit address (MSB first, LSB last). */
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temp = sd->sd_MS ^ sd->sd_CS;
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for (i = (sd->sd_chip - 1); i >= 0; i--) {
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if ((k & (1 << i)) != 0)
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temp ^= sd->sd_DO;
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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if ((k & (1 << i)) != 0)
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temp ^= sd->sd_DO;
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}
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/*
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* Now read the 16 bit register. An initial 0 precedes the
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* register contents which begins with bit 15 (MSB) and ends
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* with bit 0 (LSB). The initial 0 will be shifted off the
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* top of our word as we let the loop run from 0 to 16.
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*/
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v = 0;
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for (i = 16; i >= 0; i--) {
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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v <<= 1;
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if (SEEPROM_DATA_INB(sd) & sd->sd_DI)
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v |= 1;
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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}
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buf[k - start_addr] = v;
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/* Reset the chip select for the next command cycle. */
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reset_seeprom(sd);
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}
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#ifdef AHC_DUMP_EEPROM
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printk("\nSerial EEPROM:\n\t");
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for (k = 0; k < count; k = k + 1) {
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if (((k % 8) == 0) && (k != 0)) {
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printk(KERN_CONT "\n\t");
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}
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printk(KERN_CONT " 0x%x", buf[k]);
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}
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printk(KERN_CONT "\n");
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#endif
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return (1);
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}
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/*
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* Write the serial EEPROM and return 1 if successful and 0 if
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* not successful.
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*/
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int
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ahc_write_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
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u_int start_addr, u_int count)
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{
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const struct seeprom_cmd *ewen, *ewds;
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uint16_t v;
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uint8_t temp;
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int i, k;
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/* Place the chip into write-enable mode */
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if (sd->sd_chip == C46) {
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ewen = &seeprom_ewen;
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ewds = &seeprom_ewds;
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} else if (sd->sd_chip == C56_66) {
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ewen = &seeprom_long_ewen;
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ewds = &seeprom_long_ewds;
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} else {
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printk("ahc_write_seeprom: unsupported seeprom type %d\n",
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sd->sd_chip);
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return (0);
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}
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send_seeprom_cmd(sd, ewen);
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reset_seeprom(sd);
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/* Write all requested data out to the seeprom. */
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temp = sd->sd_MS ^ sd->sd_CS;
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for (k = start_addr; k < count + start_addr; k++) {
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/* Send the write command */
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send_seeprom_cmd(sd, &seeprom_write);
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/* Send the 6 or 8 bit address (MSB first). */
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for (i = (sd->sd_chip - 1); i >= 0; i--) {
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if ((k & (1 << i)) != 0)
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temp ^= sd->sd_DO;
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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if ((k & (1 << i)) != 0)
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temp ^= sd->sd_DO;
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}
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/* Write the 16 bit value, MSB first */
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v = buf[k - start_addr];
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for (i = 15; i >= 0; i--) {
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if ((v & (1 << i)) != 0)
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temp ^= sd->sd_DO;
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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if ((v & (1 << i)) != 0)
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temp ^= sd->sd_DO;
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}
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/* Wait for the chip to complete the write */
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temp = sd->sd_MS;
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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temp = sd->sd_MS ^ sd->sd_CS;
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do {
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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} while ((SEEPROM_DATA_INB(sd) & sd->sd_DI) == 0);
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reset_seeprom(sd);
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}
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/* Put the chip back into write-protect mode */
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send_seeprom_cmd(sd, ewds);
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reset_seeprom(sd);
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return (1);
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}
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int
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ahc_verify_cksum(struct seeprom_config *sc)
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{
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int i;
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int maxaddr;
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uint32_t checksum;
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uint16_t *scarray;
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maxaddr = (sizeof(*sc)/2) - 1;
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checksum = 0;
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scarray = (uint16_t *)sc;
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for (i = 0; i < maxaddr; i++)
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checksum = checksum + scarray[i];
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if (checksum == 0
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|| (checksum & 0xFFFF) != sc->checksum) {
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return (0);
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} else {
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return(1);
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}
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}
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