mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
50
drivers/scsi/mvsas/Kconfig
Normal file
50
drivers/scsi/mvsas/Kconfig
Normal file
|
|
@ -0,0 +1,50 @@
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|||
#
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# Kernel configuration file for 88SE64XX/88SE94XX SAS/SATA driver.
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#
|
||||
# Copyright 2007 Red Hat, Inc.
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# Copyright 2008 Marvell. <kewei@marvell.com>
|
||||
# Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
|
||||
#
|
||||
# This file is licensed under GPLv2.
|
||||
#
|
||||
# This file is part of the 88SE64XX/88SE94XX driver.
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||||
#
|
||||
# The 88SE64XX/88SE94XX driver is free software; you can redistribute
|
||||
# it and/or modify it under the terms of the GNU General Public License
|
||||
# as published by the Free Software Foundation; version 2 of the
|
||||
# License.
|
||||
#
|
||||
# The 88SE64XX/88SE94XX driver is distributed in the hope that it will be
|
||||
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
# General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with 88SE64XX/88SE94XX Driver; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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||||
#
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config SCSI_MVSAS
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tristate "Marvell 88SE64XX/88SE94XX SAS/SATA support"
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depends on PCI
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select SCSI_SAS_LIBSAS
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select FW_LOADER
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help
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||||
This driver supports Marvell's SAS/SATA 3Gb/s PCI-E 88SE64XX and 6Gb/s
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PCI-E 88SE94XX chip based host adapters.
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config SCSI_MVSAS_DEBUG
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bool "Compile in debug mode"
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default y
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depends on SCSI_MVSAS
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help
|
||||
Compiles the 88SE64XX/88SE94XX driver in debug mode. In debug mode,
|
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the driver prints some messages to the console.
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config SCSI_MVSAS_TASKLET
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bool "Support for interrupt tasklet"
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default n
|
||||
depends on SCSI_MVSAS
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||||
help
|
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Compiles the 88SE64xx/88SE94xx driver in interrupt tasklet mode.In this mode,
|
||||
the interrupt will schedule a tasklet.
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31
drivers/scsi/mvsas/Makefile
Normal file
31
drivers/scsi/mvsas/Makefile
Normal file
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|
@ -0,0 +1,31 @@
|
|||
#
|
||||
# Makefile for Marvell 88SE64xx/88SE84xx SAS/SATA driver.
|
||||
#
|
||||
# Copyright 2007 Red Hat, Inc.
|
||||
# Copyright 2008 Marvell. <kewei@marvell.com>
|
||||
# Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
|
||||
#
|
||||
# This file is licensed under GPLv2.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; version 2 of the
|
||||
# License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
# General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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# USA
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||||
|
||||
ccflags-$(CONFIG_SCSI_MVSAS_DEBUG) := -DMV_DEBUG
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obj-$(CONFIG_SCSI_MVSAS) += mvsas.o
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mvsas-y += mv_init.o \
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mv_sas.o \
|
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mv_64xx.o \
|
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mv_94xx.o
|
||||
828
drivers/scsi/mvsas/mv_64xx.c
Normal file
828
drivers/scsi/mvsas/mv_64xx.c
Normal file
|
|
@ -0,0 +1,828 @@
|
|||
/*
|
||||
* Marvell 88SE64xx hardware specific
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||||
*
|
||||
* Copyright 2007 Red Hat, Inc.
|
||||
* Copyright 2008 Marvell. <kewei@marvell.com>
|
||||
* Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
|
||||
*
|
||||
* This file is licensed under GPLv2.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the
|
||||
* License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
#include "mv_sas.h"
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#include "mv_64xx.h"
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#include "mv_chips.h"
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||||
|
||||
static void mvs_64xx_detect_porttype(struct mvs_info *mvi, int i)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
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u32 reg;
|
||||
struct mvs_phy *phy = &mvi->phy[i];
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reg = mr32(MVS_GBL_PORT_TYPE);
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phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
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if (reg & MODE_SAS_SATA & (1 << i))
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phy->phy_type |= PORT_TYPE_SAS;
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else
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phy->phy_type |= PORT_TYPE_SATA;
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||||
}
|
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|
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static void mvs_64xx_enable_xmt(struct mvs_info *mvi, int phy_id)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
u32 tmp;
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||||
|
||||
tmp = mr32(MVS_PCS);
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if (mvi->chip->n_phy <= MVS_SOC_PORTS)
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tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT);
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else
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tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2);
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mw32(MVS_PCS, tmp);
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}
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static void mvs_64xx_phy_hacks(struct mvs_info *mvi)
|
||||
{
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void __iomem *regs = mvi->regs;
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int i;
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mvs_phy_hacks(mvi);
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|
||||
if (!(mvi->flags & MVF_FLAG_SOC)) {
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for (i = 0; i < MVS_SOC_PORTS; i++) {
|
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mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE8);
|
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mvs_write_port_vsr_data(mvi, i, 0x2F0);
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}
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} else {
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/* disable auto port detection */
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mw32(MVS_GBL_PORT_TYPE, 0);
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for (i = 0; i < mvi->chip->n_phy; i++) {
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mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE7);
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||||
mvs_write_port_vsr_data(mvi, i, 0x90000000);
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mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE9);
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mvs_write_port_vsr_data(mvi, i, 0x50f2);
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mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE11);
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mvs_write_port_vsr_data(mvi, i, 0x0e);
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}
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}
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}
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static void mvs_64xx_stp_reset(struct mvs_info *mvi, u32 phy_id)
|
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{
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void __iomem *regs = mvi->regs;
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u32 reg, tmp;
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if (!(mvi->flags & MVF_FLAG_SOC)) {
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if (phy_id < MVS_SOC_PORTS)
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pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, ®);
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else
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pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, ®);
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|
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} else
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reg = mr32(MVS_PHY_CTL);
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|
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tmp = reg;
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if (phy_id < MVS_SOC_PORTS)
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tmp |= (1U << phy_id) << PCTL_LINK_OFFS;
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else
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tmp |= (1U << (phy_id - MVS_SOC_PORTS)) << PCTL_LINK_OFFS;
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|
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if (!(mvi->flags & MVF_FLAG_SOC)) {
|
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if (phy_id < MVS_SOC_PORTS) {
|
||||
pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
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mdelay(10);
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pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, reg);
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} else {
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pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
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mdelay(10);
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pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, reg);
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}
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} else {
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mw32(MVS_PHY_CTL, tmp);
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mdelay(10);
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mw32(MVS_PHY_CTL, reg);
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}
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}
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static void mvs_64xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)
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{
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u32 tmp;
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tmp = mvs_read_port_irq_stat(mvi, phy_id);
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tmp &= ~PHYEV_RDY_CH;
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mvs_write_port_irq_stat(mvi, phy_id, tmp);
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tmp = mvs_read_phy_ctl(mvi, phy_id);
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if (hard == MVS_HARD_RESET)
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tmp |= PHY_RST_HARD;
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else if (hard == MVS_SOFT_RESET)
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tmp |= PHY_RST;
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mvs_write_phy_ctl(mvi, phy_id, tmp);
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if (hard) {
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do {
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tmp = mvs_read_phy_ctl(mvi, phy_id);
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} while (tmp & PHY_RST_HARD);
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}
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}
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void mvs_64xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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if (clear_all) {
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tmp = mr32(MVS_INT_STAT_SRS_0);
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if (tmp) {
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printk(KERN_DEBUG "check SRS 0 %08X.\n", tmp);
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mw32(MVS_INT_STAT_SRS_0, tmp);
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}
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} else {
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tmp = mr32(MVS_INT_STAT_SRS_0);
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if (tmp & (1 << (reg_set % 32))) {
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printk(KERN_DEBUG "register set 0x%x was stopped.\n",
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reg_set);
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mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32));
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}
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}
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}
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static int mvs_64xx_chip_reset(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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int i;
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/* make sure interrupts are masked immediately (paranoia) */
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mw32(MVS_GBL_CTL, 0);
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tmp = mr32(MVS_GBL_CTL);
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/* Reset Controller */
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if (!(tmp & HBA_RST)) {
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if (mvi->flags & MVF_PHY_PWR_FIX) {
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pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
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tmp &= ~PCTL_PWR_OFF;
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tmp |= PCTL_PHY_DSBL;
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pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
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pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
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tmp &= ~PCTL_PWR_OFF;
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tmp |= PCTL_PHY_DSBL;
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pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
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}
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}
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/* make sure interrupts are masked immediately (paranoia) */
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mw32(MVS_GBL_CTL, 0);
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tmp = mr32(MVS_GBL_CTL);
|
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|
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/* Reset Controller */
|
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if (!(tmp & HBA_RST)) {
|
||||
/* global reset, incl. COMRESET/H_RESET_N (self-clearing) */
|
||||
mw32_f(MVS_GBL_CTL, HBA_RST);
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}
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|
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/* wait for reset to finish; timeout is just a guess */
|
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i = 1000;
|
||||
while (i-- > 0) {
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msleep(10);
|
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|
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if (!(mr32(MVS_GBL_CTL) & HBA_RST))
|
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break;
|
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}
|
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if (mr32(MVS_GBL_CTL) & HBA_RST) {
|
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dev_printk(KERN_ERR, mvi->dev, "HBA reset failed\n");
|
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return -EBUSY;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mvs_64xx_phy_disable(struct mvs_info *mvi, u32 phy_id)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
u32 tmp;
|
||||
if (!(mvi->flags & MVF_FLAG_SOC)) {
|
||||
u32 offs;
|
||||
if (phy_id < 4)
|
||||
offs = PCR_PHY_CTL;
|
||||
else {
|
||||
offs = PCR_PHY_CTL2;
|
||||
phy_id -= 4;
|
||||
}
|
||||
pci_read_config_dword(mvi->pdev, offs, &tmp);
|
||||
tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id);
|
||||
pci_write_config_dword(mvi->pdev, offs, tmp);
|
||||
} else {
|
||||
tmp = mr32(MVS_PHY_CTL);
|
||||
tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id);
|
||||
mw32(MVS_PHY_CTL, tmp);
|
||||
}
|
||||
}
|
||||
|
||||
static void mvs_64xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
u32 tmp;
|
||||
if (!(mvi->flags & MVF_FLAG_SOC)) {
|
||||
u32 offs;
|
||||
if (phy_id < 4)
|
||||
offs = PCR_PHY_CTL;
|
||||
else {
|
||||
offs = PCR_PHY_CTL2;
|
||||
phy_id -= 4;
|
||||
}
|
||||
pci_read_config_dword(mvi->pdev, offs, &tmp);
|
||||
tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id));
|
||||
pci_write_config_dword(mvi->pdev, offs, tmp);
|
||||
} else {
|
||||
tmp = mr32(MVS_PHY_CTL);
|
||||
tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id));
|
||||
mw32(MVS_PHY_CTL, tmp);
|
||||
}
|
||||
}
|
||||
|
||||
static int mvs_64xx_init(struct mvs_info *mvi)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
int i;
|
||||
u32 tmp, cctl;
|
||||
|
||||
if (mvi->pdev && mvi->pdev->revision == 0)
|
||||
mvi->flags |= MVF_PHY_PWR_FIX;
|
||||
if (!(mvi->flags & MVF_FLAG_SOC)) {
|
||||
mvs_show_pcie_usage(mvi);
|
||||
tmp = mvs_64xx_chip_reset(mvi);
|
||||
if (tmp)
|
||||
return tmp;
|
||||
} else {
|
||||
tmp = mr32(MVS_PHY_CTL);
|
||||
tmp &= ~PCTL_PWR_OFF;
|
||||
tmp |= PCTL_PHY_DSBL;
|
||||
mw32(MVS_PHY_CTL, tmp);
|
||||
}
|
||||
|
||||
/* Init Chip */
|
||||
/* make sure RST is set; HBA_RST /should/ have done that for us */
|
||||
cctl = mr32(MVS_CTL) & 0xFFFF;
|
||||
if (cctl & CCTL_RST)
|
||||
cctl &= ~CCTL_RST;
|
||||
else
|
||||
mw32_f(MVS_CTL, cctl | CCTL_RST);
|
||||
|
||||
if (!(mvi->flags & MVF_FLAG_SOC)) {
|
||||
/* write to device control _AND_ device status register */
|
||||
pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp);
|
||||
tmp &= ~PRD_REQ_MASK;
|
||||
tmp |= PRD_REQ_SIZE;
|
||||
pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp);
|
||||
|
||||
pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
|
||||
tmp &= ~PCTL_PWR_OFF;
|
||||
tmp &= ~PCTL_PHY_DSBL;
|
||||
pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
|
||||
|
||||
pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
|
||||
tmp &= PCTL_PWR_OFF;
|
||||
tmp &= ~PCTL_PHY_DSBL;
|
||||
pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
|
||||
} else {
|
||||
tmp = mr32(MVS_PHY_CTL);
|
||||
tmp &= ~PCTL_PWR_OFF;
|
||||
tmp |= PCTL_COM_ON;
|
||||
tmp &= ~PCTL_PHY_DSBL;
|
||||
tmp |= PCTL_LINK_RST;
|
||||
mw32(MVS_PHY_CTL, tmp);
|
||||
msleep(100);
|
||||
tmp &= ~PCTL_LINK_RST;
|
||||
mw32(MVS_PHY_CTL, tmp);
|
||||
msleep(100);
|
||||
}
|
||||
|
||||
/* reset control */
|
||||
mw32(MVS_PCS, 0); /* MVS_PCS */
|
||||
/* init phys */
|
||||
mvs_64xx_phy_hacks(mvi);
|
||||
|
||||
tmp = mvs_cr32(mvi, CMD_PHY_MODE_21);
|
||||
tmp &= 0x0000ffff;
|
||||
tmp |= 0x00fa0000;
|
||||
mvs_cw32(mvi, CMD_PHY_MODE_21, tmp);
|
||||
|
||||
/* enable auto port detection */
|
||||
mw32(MVS_GBL_PORT_TYPE, MODE_AUTO_DET_EN);
|
||||
|
||||
mw32(MVS_CMD_LIST_LO, mvi->slot_dma);
|
||||
mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
|
||||
|
||||
mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);
|
||||
mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
|
||||
|
||||
mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ);
|
||||
mw32(MVS_TX_LO, mvi->tx_dma);
|
||||
mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);
|
||||
|
||||
mw32(MVS_RX_CFG, MVS_RX_RING_SZ);
|
||||
mw32(MVS_RX_LO, mvi->rx_dma);
|
||||
mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);
|
||||
|
||||
for (i = 0; i < mvi->chip->n_phy; i++) {
|
||||
/* set phy local SAS address */
|
||||
/* should set little endian SAS address to 64xx chip */
|
||||
mvs_set_sas_addr(mvi, i, PHYR_ADDR_LO, PHYR_ADDR_HI,
|
||||
cpu_to_be64(mvi->phy[i].dev_sas_addr));
|
||||
|
||||
mvs_64xx_enable_xmt(mvi, i);
|
||||
|
||||
mvs_64xx_phy_reset(mvi, i, MVS_HARD_RESET);
|
||||
msleep(500);
|
||||
mvs_64xx_detect_porttype(mvi, i);
|
||||
}
|
||||
if (mvi->flags & MVF_FLAG_SOC) {
|
||||
/* set select registers */
|
||||
writel(0x0E008000, regs + 0x000);
|
||||
writel(0x59000008, regs + 0x004);
|
||||
writel(0x20, regs + 0x008);
|
||||
writel(0x20, regs + 0x00c);
|
||||
writel(0x20, regs + 0x010);
|
||||
writel(0x20, regs + 0x014);
|
||||
writel(0x20, regs + 0x018);
|
||||
writel(0x20, regs + 0x01c);
|
||||
}
|
||||
for (i = 0; i < mvi->chip->n_phy; i++) {
|
||||
/* clear phy int status */
|
||||
tmp = mvs_read_port_irq_stat(mvi, i);
|
||||
tmp &= ~PHYEV_SIG_FIS;
|
||||
mvs_write_port_irq_stat(mvi, i, tmp);
|
||||
|
||||
/* set phy int mask */
|
||||
tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | PHYEV_UNASSOC_FIS |
|
||||
PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR |
|
||||
PHYEV_DEC_ERR;
|
||||
mvs_write_port_irq_mask(mvi, i, tmp);
|
||||
|
||||
msleep(100);
|
||||
mvs_update_phyinfo(mvi, i, 1);
|
||||
}
|
||||
|
||||
/* little endian for open address and command table, etc. */
|
||||
cctl = mr32(MVS_CTL);
|
||||
cctl |= CCTL_ENDIAN_CMD;
|
||||
cctl |= CCTL_ENDIAN_DATA;
|
||||
cctl &= ~CCTL_ENDIAN_OPEN;
|
||||
cctl |= CCTL_ENDIAN_RSP;
|
||||
mw32_f(MVS_CTL, cctl);
|
||||
|
||||
/* reset CMD queue */
|
||||
tmp = mr32(MVS_PCS);
|
||||
tmp |= PCS_CMD_RST;
|
||||
tmp &= ~PCS_SELF_CLEAR;
|
||||
mw32(MVS_PCS, tmp);
|
||||
/*
|
||||
* the max count is 0x1ff, while our max slot is 0x200,
|
||||
* it will make count 0.
|
||||
*/
|
||||
tmp = 0;
|
||||
if (MVS_CHIP_SLOT_SZ > 0x1ff)
|
||||
mw32(MVS_INT_COAL, 0x1ff | COAL_EN);
|
||||
else
|
||||
mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ | COAL_EN);
|
||||
|
||||
tmp = 0x10000 | interrupt_coalescing;
|
||||
mw32(MVS_INT_COAL_TMOUT, tmp);
|
||||
|
||||
/* ladies and gentlemen, start your engines */
|
||||
mw32(MVS_TX_CFG, 0);
|
||||
mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);
|
||||
mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN);
|
||||
/* enable CMD/CMPL_Q/RESP mode */
|
||||
mw32(MVS_PCS, PCS_SATA_RETRY | PCS_FIS_RX_EN |
|
||||
PCS_CMD_EN | PCS_CMD_STOP_ERR);
|
||||
|
||||
/* enable completion queue interrupt */
|
||||
tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP |
|
||||
CINT_DMA_PCIE);
|
||||
|
||||
mw32(MVS_INT_MASK, tmp);
|
||||
|
||||
/* Enable SRS interrupt */
|
||||
mw32(MVS_INT_MASK_SRS_0, 0xFFFF);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mvs_64xx_ioremap(struct mvs_info *mvi)
|
||||
{
|
||||
if (!mvs_ioremap(mvi, 4, 2))
|
||||
return 0;
|
||||
return -1;
|
||||
}
|
||||
|
||||
static void mvs_64xx_iounmap(struct mvs_info *mvi)
|
||||
{
|
||||
mvs_iounmap(mvi->regs);
|
||||
mvs_iounmap(mvi->regs_ex);
|
||||
}
|
||||
|
||||
static void mvs_64xx_interrupt_enable(struct mvs_info *mvi)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
u32 tmp;
|
||||
|
||||
tmp = mr32(MVS_GBL_CTL);
|
||||
mw32(MVS_GBL_CTL, tmp | INT_EN);
|
||||
}
|
||||
|
||||
static void mvs_64xx_interrupt_disable(struct mvs_info *mvi)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
u32 tmp;
|
||||
|
||||
tmp = mr32(MVS_GBL_CTL);
|
||||
mw32(MVS_GBL_CTL, tmp & ~INT_EN);
|
||||
}
|
||||
|
||||
static u32 mvs_64xx_isr_status(struct mvs_info *mvi, int irq)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
u32 stat;
|
||||
|
||||
if (!(mvi->flags & MVF_FLAG_SOC)) {
|
||||
stat = mr32(MVS_GBL_INT_STAT);
|
||||
|
||||
if (stat == 0 || stat == 0xffffffff)
|
||||
return 0;
|
||||
} else
|
||||
stat = 1;
|
||||
return stat;
|
||||
}
|
||||
|
||||
static irqreturn_t mvs_64xx_isr(struct mvs_info *mvi, int irq, u32 stat)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
|
||||
/* clear CMD_CMPLT ASAP */
|
||||
mw32_f(MVS_INT_STAT, CINT_DONE);
|
||||
|
||||
spin_lock(&mvi->lock);
|
||||
mvs_int_full(mvi);
|
||||
spin_unlock(&mvi->lock);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void mvs_64xx_command_active(struct mvs_info *mvi, u32 slot_idx)
|
||||
{
|
||||
u32 tmp;
|
||||
mvs_cw32(mvi, 0x40 + (slot_idx >> 3), 1 << (slot_idx % 32));
|
||||
mvs_cw32(mvi, 0x00 + (slot_idx >> 3), 1 << (slot_idx % 32));
|
||||
do {
|
||||
tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3));
|
||||
} while (tmp & 1 << (slot_idx % 32));
|
||||
do {
|
||||
tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3));
|
||||
} while (tmp & 1 << (slot_idx % 32));
|
||||
}
|
||||
|
||||
static void mvs_64xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,
|
||||
u32 tfs)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
u32 tmp;
|
||||
|
||||
if (type == PORT_TYPE_SATA) {
|
||||
tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs);
|
||||
mw32(MVS_INT_STAT_SRS_0, tmp);
|
||||
}
|
||||
mw32(MVS_INT_STAT, CINT_CI_STOP);
|
||||
tmp = mr32(MVS_PCS) | 0xFF00;
|
||||
mw32(MVS_PCS, tmp);
|
||||
}
|
||||
|
||||
static void mvs_64xx_free_reg_set(struct mvs_info *mvi, u8 *tfs)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
u32 tmp, offs;
|
||||
|
||||
if (*tfs == MVS_ID_NOT_MAPPED)
|
||||
return;
|
||||
|
||||
offs = 1U << ((*tfs & 0x0f) + PCS_EN_SATA_REG_SHIFT);
|
||||
if (*tfs < 16) {
|
||||
tmp = mr32(MVS_PCS);
|
||||
mw32(MVS_PCS, tmp & ~offs);
|
||||
} else {
|
||||
tmp = mr32(MVS_CTL);
|
||||
mw32(MVS_CTL, tmp & ~offs);
|
||||
}
|
||||
|
||||
tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << *tfs);
|
||||
if (tmp)
|
||||
mw32(MVS_INT_STAT_SRS_0, tmp);
|
||||
|
||||
*tfs = MVS_ID_NOT_MAPPED;
|
||||
return;
|
||||
}
|
||||
|
||||
static u8 mvs_64xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)
|
||||
{
|
||||
int i;
|
||||
u32 tmp, offs;
|
||||
void __iomem *regs = mvi->regs;
|
||||
|
||||
if (*tfs != MVS_ID_NOT_MAPPED)
|
||||
return 0;
|
||||
|
||||
tmp = mr32(MVS_PCS);
|
||||
|
||||
for (i = 0; i < mvi->chip->srs_sz; i++) {
|
||||
if (i == 16)
|
||||
tmp = mr32(MVS_CTL);
|
||||
offs = 1U << ((i & 0x0f) + PCS_EN_SATA_REG_SHIFT);
|
||||
if (!(tmp & offs)) {
|
||||
*tfs = i;
|
||||
|
||||
if (i < 16)
|
||||
mw32(MVS_PCS, tmp | offs);
|
||||
else
|
||||
mw32(MVS_CTL, tmp | offs);
|
||||
tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << i);
|
||||
if (tmp)
|
||||
mw32(MVS_INT_STAT_SRS_0, tmp);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
return MVS_ID_NOT_MAPPED;
|
||||
}
|
||||
|
||||
void mvs_64xx_make_prd(struct scatterlist *scatter, int nr, void *prd)
|
||||
{
|
||||
int i;
|
||||
struct scatterlist *sg;
|
||||
struct mvs_prd *buf_prd = prd;
|
||||
for_each_sg(scatter, sg, nr, i) {
|
||||
buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
|
||||
buf_prd->len = cpu_to_le32(sg_dma_len(sg));
|
||||
buf_prd++;
|
||||
}
|
||||
}
|
||||
|
||||
static int mvs_64xx_oob_done(struct mvs_info *mvi, int i)
|
||||
{
|
||||
u32 phy_st;
|
||||
mvs_write_port_cfg_addr(mvi, i,
|
||||
PHYR_PHY_STAT);
|
||||
phy_st = mvs_read_port_cfg_data(mvi, i);
|
||||
if (phy_st & PHY_OOB_DTCTD)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mvs_64xx_fix_phy_info(struct mvs_info *mvi, int i,
|
||||
struct sas_identify_frame *id)
|
||||
|
||||
{
|
||||
struct mvs_phy *phy = &mvi->phy[i];
|
||||
struct asd_sas_phy *sas_phy = &phy->sas_phy;
|
||||
|
||||
sas_phy->linkrate =
|
||||
(phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
|
||||
PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET;
|
||||
|
||||
phy->minimum_linkrate =
|
||||
(phy->phy_status &
|
||||
PHY_MIN_SPP_PHYS_LINK_RATE_MASK) >> 8;
|
||||
phy->maximum_linkrate =
|
||||
(phy->phy_status &
|
||||
PHY_MAX_SPP_PHYS_LINK_RATE_MASK) >> 12;
|
||||
|
||||
mvs_write_port_cfg_addr(mvi, i, PHYR_IDENTIFY);
|
||||
phy->dev_info = mvs_read_port_cfg_data(mvi, i);
|
||||
|
||||
mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_DEV_INFO);
|
||||
phy->att_dev_info = mvs_read_port_cfg_data(mvi, i);
|
||||
|
||||
mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_HI);
|
||||
phy->att_dev_sas_addr =
|
||||
(u64) mvs_read_port_cfg_data(mvi, i) << 32;
|
||||
mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_LO);
|
||||
phy->att_dev_sas_addr |= mvs_read_port_cfg_data(mvi, i);
|
||||
phy->att_dev_sas_addr = SAS_ADDR(&phy->att_dev_sas_addr);
|
||||
}
|
||||
|
||||
static void mvs_64xx_phy_work_around(struct mvs_info *mvi, int i)
|
||||
{
|
||||
u32 tmp;
|
||||
struct mvs_phy *phy = &mvi->phy[i];
|
||||
mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE6);
|
||||
tmp = mvs_read_port_vsr_data(mvi, i);
|
||||
if (((phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
|
||||
PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET) ==
|
||||
SAS_LINK_RATE_1_5_GBPS)
|
||||
tmp &= ~PHY_MODE6_LATECLK;
|
||||
else
|
||||
tmp |= PHY_MODE6_LATECLK;
|
||||
mvs_write_port_vsr_data(mvi, i, tmp);
|
||||
}
|
||||
|
||||
void mvs_64xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
|
||||
struct sas_phy_linkrates *rates)
|
||||
{
|
||||
u32 lrmin = 0, lrmax = 0;
|
||||
u32 tmp;
|
||||
|
||||
tmp = mvs_read_phy_ctl(mvi, phy_id);
|
||||
lrmin = (rates->minimum_linkrate << 8);
|
||||
lrmax = (rates->maximum_linkrate << 12);
|
||||
|
||||
if (lrmin) {
|
||||
tmp &= ~(0xf << 8);
|
||||
tmp |= lrmin;
|
||||
}
|
||||
if (lrmax) {
|
||||
tmp &= ~(0xf << 12);
|
||||
tmp |= lrmax;
|
||||
}
|
||||
mvs_write_phy_ctl(mvi, phy_id, tmp);
|
||||
mvs_64xx_phy_reset(mvi, phy_id, MVS_HARD_RESET);
|
||||
}
|
||||
|
||||
static void mvs_64xx_clear_active_cmds(struct mvs_info *mvi)
|
||||
{
|
||||
u32 tmp;
|
||||
void __iomem *regs = mvi->regs;
|
||||
tmp = mr32(MVS_PCS);
|
||||
mw32(MVS_PCS, tmp & 0xFFFF);
|
||||
mw32(MVS_PCS, tmp);
|
||||
tmp = mr32(MVS_CTL);
|
||||
mw32(MVS_CTL, tmp & 0xFFFF);
|
||||
mw32(MVS_CTL, tmp);
|
||||
}
|
||||
|
||||
|
||||
u32 mvs_64xx_spi_read_data(struct mvs_info *mvi)
|
||||
{
|
||||
void __iomem *regs = mvi->regs_ex;
|
||||
return ior32(SPI_DATA_REG_64XX);
|
||||
}
|
||||
|
||||
void mvs_64xx_spi_write_data(struct mvs_info *mvi, u32 data)
|
||||
{
|
||||
void __iomem *regs = mvi->regs_ex;
|
||||
iow32(SPI_DATA_REG_64XX, data);
|
||||
}
|
||||
|
||||
|
||||
int mvs_64xx_spi_buildcmd(struct mvs_info *mvi,
|
||||
u32 *dwCmd,
|
||||
u8 cmd,
|
||||
u8 read,
|
||||
u8 length,
|
||||
u32 addr
|
||||
)
|
||||
{
|
||||
u32 dwTmp;
|
||||
|
||||
dwTmp = ((u32)cmd << 24) | ((u32)length << 19);
|
||||
if (read)
|
||||
dwTmp |= 1U<<23;
|
||||
|
||||
if (addr != MV_MAX_U32) {
|
||||
dwTmp |= 1U<<22;
|
||||
dwTmp |= (addr & 0x0003FFFF);
|
||||
}
|
||||
|
||||
*dwCmd = dwTmp;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int mvs_64xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
|
||||
{
|
||||
void __iomem *regs = mvi->regs_ex;
|
||||
int retry;
|
||||
|
||||
for (retry = 0; retry < 1; retry++) {
|
||||
iow32(SPI_CTRL_REG_64XX, SPI_CTRL_VENDOR_ENABLE);
|
||||
iow32(SPI_CMD_REG_64XX, cmd);
|
||||
iow32(SPI_CTRL_REG_64XX,
|
||||
SPI_CTRL_VENDOR_ENABLE | SPI_CTRL_SPISTART);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mvs_64xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
|
||||
{
|
||||
void __iomem *regs = mvi->regs_ex;
|
||||
u32 i, dwTmp;
|
||||
|
||||
for (i = 0; i < timeout; i++) {
|
||||
dwTmp = ior32(SPI_CTRL_REG_64XX);
|
||||
if (!(dwTmp & SPI_CTRL_SPISTART))
|
||||
return 0;
|
||||
msleep(10);
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
void mvs_64xx_fix_dma(struct mvs_info *mvi, u32 phy_mask,
|
||||
int buf_len, int from, void *prd)
|
||||
{
|
||||
int i;
|
||||
struct mvs_prd *buf_prd = prd;
|
||||
dma_addr_t buf_dma = mvi->bulk_buffer_dma;
|
||||
|
||||
buf_prd += from;
|
||||
for (i = 0; i < MAX_SG_ENTRY - from; i++) {
|
||||
buf_prd->addr = cpu_to_le64(buf_dma);
|
||||
buf_prd->len = cpu_to_le32(buf_len);
|
||||
++buf_prd;
|
||||
}
|
||||
}
|
||||
|
||||
static void mvs_64xx_tune_interrupt(struct mvs_info *mvi, u32 time)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
u32 tmp = 0;
|
||||
/*
|
||||
* the max count is 0x1ff, while our max slot is 0x200,
|
||||
* it will make count 0.
|
||||
*/
|
||||
if (time == 0) {
|
||||
mw32(MVS_INT_COAL, 0);
|
||||
mw32(MVS_INT_COAL_TMOUT, 0x10000);
|
||||
} else {
|
||||
if (MVS_CHIP_SLOT_SZ > 0x1ff)
|
||||
mw32(MVS_INT_COAL, 0x1ff|COAL_EN);
|
||||
else
|
||||
mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ|COAL_EN);
|
||||
|
||||
tmp = 0x10000 | time;
|
||||
mw32(MVS_INT_COAL_TMOUT, tmp);
|
||||
}
|
||||
}
|
||||
|
||||
const struct mvs_dispatch mvs_64xx_dispatch = {
|
||||
"mv64xx",
|
||||
mvs_64xx_init,
|
||||
NULL,
|
||||
mvs_64xx_ioremap,
|
||||
mvs_64xx_iounmap,
|
||||
mvs_64xx_isr,
|
||||
mvs_64xx_isr_status,
|
||||
mvs_64xx_interrupt_enable,
|
||||
mvs_64xx_interrupt_disable,
|
||||
mvs_read_phy_ctl,
|
||||
mvs_write_phy_ctl,
|
||||
mvs_read_port_cfg_data,
|
||||
mvs_write_port_cfg_data,
|
||||
mvs_write_port_cfg_addr,
|
||||
mvs_read_port_vsr_data,
|
||||
mvs_write_port_vsr_data,
|
||||
mvs_write_port_vsr_addr,
|
||||
mvs_read_port_irq_stat,
|
||||
mvs_write_port_irq_stat,
|
||||
mvs_read_port_irq_mask,
|
||||
mvs_write_port_irq_mask,
|
||||
mvs_64xx_command_active,
|
||||
mvs_64xx_clear_srs_irq,
|
||||
mvs_64xx_issue_stop,
|
||||
mvs_start_delivery,
|
||||
mvs_rx_update,
|
||||
mvs_int_full,
|
||||
mvs_64xx_assign_reg_set,
|
||||
mvs_64xx_free_reg_set,
|
||||
mvs_get_prd_size,
|
||||
mvs_get_prd_count,
|
||||
mvs_64xx_make_prd,
|
||||
mvs_64xx_detect_porttype,
|
||||
mvs_64xx_oob_done,
|
||||
mvs_64xx_fix_phy_info,
|
||||
mvs_64xx_phy_work_around,
|
||||
mvs_64xx_phy_set_link_rate,
|
||||
mvs_hw_max_link_rate,
|
||||
mvs_64xx_phy_disable,
|
||||
mvs_64xx_phy_enable,
|
||||
mvs_64xx_phy_reset,
|
||||
mvs_64xx_stp_reset,
|
||||
mvs_64xx_clear_active_cmds,
|
||||
mvs_64xx_spi_read_data,
|
||||
mvs_64xx_spi_write_data,
|
||||
mvs_64xx_spi_buildcmd,
|
||||
mvs_64xx_spi_issuecmd,
|
||||
mvs_64xx_spi_waitdataready,
|
||||
mvs_64xx_fix_dma,
|
||||
mvs_64xx_tune_interrupt,
|
||||
NULL,
|
||||
};
|
||||
|
||||
152
drivers/scsi/mvsas/mv_64xx.h
Normal file
152
drivers/scsi/mvsas/mv_64xx.h
Normal file
|
|
@ -0,0 +1,152 @@
|
|||
/*
|
||||
* Marvell 88SE64xx hardware specific head file
|
||||
*
|
||||
* Copyright 2007 Red Hat, Inc.
|
||||
* Copyright 2008 Marvell. <kewei@marvell.com>
|
||||
* Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
|
||||
*
|
||||
* This file is licensed under GPLv2.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the
|
||||
* License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
#ifndef _MVS64XX_REG_H_
|
||||
#define _MVS64XX_REG_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#define MAX_LINK_RATE SAS_LINK_RATE_3_0_GBPS
|
||||
|
||||
/* enhanced mode registers (BAR4) */
|
||||
enum hw_registers {
|
||||
MVS_GBL_CTL = 0x04, /* global control */
|
||||
MVS_GBL_INT_STAT = 0x08, /* global irq status */
|
||||
MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
|
||||
|
||||
MVS_PHY_CTL = 0x40, /* SOC PHY Control */
|
||||
MVS_PORTS_IMP = 0x9C, /* SOC Port Implemented */
|
||||
|
||||
MVS_GBL_PORT_TYPE = 0xa0, /* port type */
|
||||
|
||||
MVS_CTL = 0x100, /* SAS/SATA port configuration */
|
||||
MVS_PCS = 0x104, /* SAS/SATA port control/status */
|
||||
MVS_CMD_LIST_LO = 0x108, /* cmd list addr */
|
||||
MVS_CMD_LIST_HI = 0x10C,
|
||||
MVS_RX_FIS_LO = 0x110, /* RX FIS list addr */
|
||||
MVS_RX_FIS_HI = 0x114,
|
||||
|
||||
MVS_TX_CFG = 0x120, /* TX configuration */
|
||||
MVS_TX_LO = 0x124, /* TX (delivery) ring addr */
|
||||
MVS_TX_HI = 0x128,
|
||||
|
||||
MVS_TX_PROD_IDX = 0x12C, /* TX producer pointer */
|
||||
MVS_TX_CONS_IDX = 0x130, /* TX consumer pointer (RO) */
|
||||
MVS_RX_CFG = 0x134, /* RX configuration */
|
||||
MVS_RX_LO = 0x138, /* RX (completion) ring addr */
|
||||
MVS_RX_HI = 0x13C,
|
||||
MVS_RX_CONS_IDX = 0x140, /* RX consumer pointer (RO) */
|
||||
|
||||
MVS_INT_COAL = 0x148, /* Int coalescing config */
|
||||
MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */
|
||||
MVS_INT_STAT = 0x150, /* Central int status */
|
||||
MVS_INT_MASK = 0x154, /* Central int enable */
|
||||
MVS_INT_STAT_SRS_0 = 0x158, /* SATA register set status */
|
||||
MVS_INT_MASK_SRS_0 = 0x15C,
|
||||
|
||||
/* ports 1-3 follow after this */
|
||||
MVS_P0_INT_STAT = 0x160, /* port0 interrupt status */
|
||||
MVS_P0_INT_MASK = 0x164, /* port0 interrupt mask */
|
||||
/* ports 5-7 follow after this */
|
||||
MVS_P4_INT_STAT = 0x200, /* Port4 interrupt status */
|
||||
MVS_P4_INT_MASK = 0x204, /* Port4 interrupt enable mask */
|
||||
|
||||
/* ports 1-3 follow after this */
|
||||
MVS_P0_SER_CTLSTAT = 0x180, /* port0 serial control/status */
|
||||
/* ports 5-7 follow after this */
|
||||
MVS_P4_SER_CTLSTAT = 0x220, /* port4 serial control/status */
|
||||
|
||||
MVS_CMD_ADDR = 0x1B8, /* Command register port (addr) */
|
||||
MVS_CMD_DATA = 0x1BC, /* Command register port (data) */
|
||||
|
||||
/* ports 1-3 follow after this */
|
||||
MVS_P0_CFG_ADDR = 0x1C0, /* port0 phy register address */
|
||||
MVS_P0_CFG_DATA = 0x1C4, /* port0 phy register data */
|
||||
/* ports 5-7 follow after this */
|
||||
MVS_P4_CFG_ADDR = 0x230, /* Port4 config address */
|
||||
MVS_P4_CFG_DATA = 0x234, /* Port4 config data */
|
||||
|
||||
/* ports 1-3 follow after this */
|
||||
MVS_P0_VSR_ADDR = 0x1E0, /* port0 VSR address */
|
||||
MVS_P0_VSR_DATA = 0x1E4, /* port0 VSR data */
|
||||
/* ports 5-7 follow after this */
|
||||
MVS_P4_VSR_ADDR = 0x250, /* port4 VSR addr */
|
||||
MVS_P4_VSR_DATA = 0x254, /* port4 VSR data */
|
||||
};
|
||||
|
||||
enum pci_cfg_registers {
|
||||
PCR_PHY_CTL = 0x40,
|
||||
PCR_PHY_CTL2 = 0x90,
|
||||
PCR_DEV_CTRL = 0xE8,
|
||||
PCR_LINK_STAT = 0xF2,
|
||||
};
|
||||
|
||||
/* SAS/SATA Vendor Specific Port Registers */
|
||||
enum sas_sata_vsp_regs {
|
||||
VSR_PHY_STAT = 0x00, /* Phy Status */
|
||||
VSR_PHY_MODE1 = 0x01, /* phy tx */
|
||||
VSR_PHY_MODE2 = 0x02, /* tx scc */
|
||||
VSR_PHY_MODE3 = 0x03, /* pll */
|
||||
VSR_PHY_MODE4 = 0x04, /* VCO */
|
||||
VSR_PHY_MODE5 = 0x05, /* Rx */
|
||||
VSR_PHY_MODE6 = 0x06, /* CDR */
|
||||
VSR_PHY_MODE7 = 0x07, /* Impedance */
|
||||
VSR_PHY_MODE8 = 0x08, /* Voltage */
|
||||
VSR_PHY_MODE9 = 0x09, /* Test */
|
||||
VSR_PHY_MODE10 = 0x0A, /* Power */
|
||||
VSR_PHY_MODE11 = 0x0B, /* Phy Mode */
|
||||
VSR_PHY_VS0 = 0x0C, /* Vednor Specific 0 */
|
||||
VSR_PHY_VS1 = 0x0D, /* Vednor Specific 1 */
|
||||
};
|
||||
|
||||
enum chip_register_bits {
|
||||
PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0xF << 8),
|
||||
PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0xF << 12),
|
||||
PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
|
||||
PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
|
||||
(0xF << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
|
||||
};
|
||||
|
||||
#define MAX_SG_ENTRY 64
|
||||
|
||||
struct mvs_prd {
|
||||
__le64 addr; /* 64-bit buffer address */
|
||||
__le32 reserved;
|
||||
__le32 len; /* 16-bit length */
|
||||
};
|
||||
|
||||
#define SPI_CTRL_REG 0xc0
|
||||
#define SPI_CTRL_VENDOR_ENABLE (1U<<29)
|
||||
#define SPI_CTRL_SPIRDY (1U<<22)
|
||||
#define SPI_CTRL_SPISTART (1U<<20)
|
||||
|
||||
#define SPI_CMD_REG 0xc4
|
||||
#define SPI_DATA_REG 0xc8
|
||||
|
||||
#define SPI_CTRL_REG_64XX 0x10
|
||||
#define SPI_CMD_REG_64XX 0x14
|
||||
#define SPI_DATA_REG_64XX 0x18
|
||||
|
||||
#endif
|
||||
1061
drivers/scsi/mvsas/mv_94xx.c
Normal file
1061
drivers/scsi/mvsas/mv_94xx.c
Normal file
File diff suppressed because it is too large
Load diff
278
drivers/scsi/mvsas/mv_94xx.h
Normal file
278
drivers/scsi/mvsas/mv_94xx.h
Normal file
|
|
@ -0,0 +1,278 @@
|
|||
/*
|
||||
* Marvell 88SE94xx hardware specific head file
|
||||
*
|
||||
* Copyright 2007 Red Hat, Inc.
|
||||
* Copyright 2008 Marvell. <kewei@marvell.com>
|
||||
* Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
|
||||
*
|
||||
* This file is licensed under GPLv2.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the
|
||||
* License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
#ifndef _MVS94XX_REG_H_
|
||||
#define _MVS94XX_REG_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#define MAX_LINK_RATE SAS_LINK_RATE_6_0_GBPS
|
||||
|
||||
enum VANIR_REVISION_ID {
|
||||
VANIR_A0_REV = 0xA0,
|
||||
VANIR_B0_REV = 0x01,
|
||||
VANIR_C0_REV = 0x02,
|
||||
VANIR_C1_REV = 0x03,
|
||||
VANIR_C2_REV = 0xC2,
|
||||
};
|
||||
|
||||
enum hw_registers {
|
||||
MVS_GBL_CTL = 0x04, /* global control */
|
||||
MVS_GBL_INT_STAT = 0x00, /* global irq status */
|
||||
MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
|
||||
|
||||
MVS_PHY_CTL = 0x40, /* SOC PHY Control */
|
||||
MVS_PORTS_IMP = 0x9C, /* SOC Port Implemented */
|
||||
|
||||
MVS_GBL_PORT_TYPE = 0xa0, /* port type */
|
||||
|
||||
MVS_CTL = 0x100, /* SAS/SATA port configuration */
|
||||
MVS_PCS = 0x104, /* SAS/SATA port control/status */
|
||||
MVS_CMD_LIST_LO = 0x108, /* cmd list addr */
|
||||
MVS_CMD_LIST_HI = 0x10C,
|
||||
MVS_RX_FIS_LO = 0x110, /* RX FIS list addr */
|
||||
MVS_RX_FIS_HI = 0x114,
|
||||
MVS_STP_REG_SET_0 = 0x118, /* STP/SATA Register Set Enable */
|
||||
MVS_STP_REG_SET_1 = 0x11C,
|
||||
MVS_TX_CFG = 0x120, /* TX configuration */
|
||||
MVS_TX_LO = 0x124, /* TX (delivery) ring addr */
|
||||
MVS_TX_HI = 0x128,
|
||||
|
||||
MVS_TX_PROD_IDX = 0x12C, /* TX producer pointer */
|
||||
MVS_TX_CONS_IDX = 0x130, /* TX consumer pointer (RO) */
|
||||
MVS_RX_CFG = 0x134, /* RX configuration */
|
||||
MVS_RX_LO = 0x138, /* RX (completion) ring addr */
|
||||
MVS_RX_HI = 0x13C,
|
||||
MVS_RX_CONS_IDX = 0x140, /* RX consumer pointer (RO) */
|
||||
|
||||
MVS_INT_COAL = 0x148, /* Int coalescing config */
|
||||
MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */
|
||||
MVS_INT_STAT = 0x150, /* Central int status */
|
||||
MVS_INT_MASK = 0x154, /* Central int enable */
|
||||
MVS_INT_STAT_SRS_0 = 0x158, /* SATA register set status */
|
||||
MVS_INT_MASK_SRS_0 = 0x15C,
|
||||
MVS_INT_STAT_SRS_1 = 0x160,
|
||||
MVS_INT_MASK_SRS_1 = 0x164,
|
||||
MVS_NON_NCQ_ERR_0 = 0x168, /* SRS Non-specific NCQ Error */
|
||||
MVS_NON_NCQ_ERR_1 = 0x16C,
|
||||
MVS_CMD_ADDR = 0x170, /* Command register port (addr) */
|
||||
MVS_CMD_DATA = 0x174, /* Command register port (data) */
|
||||
MVS_MEM_PARITY_ERR = 0x178, /* Memory parity error */
|
||||
|
||||
/* ports 1-3 follow after this */
|
||||
MVS_P0_INT_STAT = 0x180, /* port0 interrupt status */
|
||||
MVS_P0_INT_MASK = 0x184, /* port0 interrupt mask */
|
||||
/* ports 5-7 follow after this */
|
||||
MVS_P4_INT_STAT = 0x1A0, /* Port4 interrupt status */
|
||||
MVS_P4_INT_MASK = 0x1A4, /* Port4 interrupt enable mask */
|
||||
|
||||
/* ports 1-3 follow after this */
|
||||
MVS_P0_SER_CTLSTAT = 0x1D0, /* port0 serial control/status */
|
||||
/* ports 5-7 follow after this */
|
||||
MVS_P4_SER_CTLSTAT = 0x1E0, /* port4 serial control/status */
|
||||
|
||||
/* ports 1-3 follow after this */
|
||||
MVS_P0_CFG_ADDR = 0x200, /* port0 phy register address */
|
||||
MVS_P0_CFG_DATA = 0x204, /* port0 phy register data */
|
||||
/* ports 5-7 follow after this */
|
||||
MVS_P4_CFG_ADDR = 0x220, /* Port4 config address */
|
||||
MVS_P4_CFG_DATA = 0x224, /* Port4 config data */
|
||||
|
||||
/* phys 1-3 follow after this */
|
||||
MVS_P0_VSR_ADDR = 0x250, /* phy0 VSR address */
|
||||
MVS_P0_VSR_DATA = 0x254, /* phy0 VSR data */
|
||||
/* phys 1-3 follow after this */
|
||||
/* multiplexing */
|
||||
MVS_P4_VSR_ADDR = 0x250, /* phy4 VSR address */
|
||||
MVS_P4_VSR_DATA = 0x254, /* phy4 VSR data */
|
||||
MVS_PA_VSR_ADDR = 0x290, /* All port VSR addr */
|
||||
MVS_PA_VSR_PORT = 0x294, /* All port VSR data */
|
||||
MVS_COMMAND_ACTIVE = 0x300,
|
||||
};
|
||||
|
||||
enum pci_cfg_registers {
|
||||
PCR_PHY_CTL = 0x40,
|
||||
PCR_PHY_CTL2 = 0x90,
|
||||
PCR_DEV_CTRL = 0x78,
|
||||
PCR_LINK_STAT = 0x82,
|
||||
};
|
||||
|
||||
/* SAS/SATA Vendor Specific Port Registers */
|
||||
enum sas_sata_vsp_regs {
|
||||
VSR_PHY_STAT = 0x00 * 4, /* Phy Interrupt Status */
|
||||
VSR_PHY_MODE1 = 0x01 * 4, /* phy Interrupt Enable */
|
||||
VSR_PHY_MODE2 = 0x02 * 4, /* Phy Configuration */
|
||||
VSR_PHY_MODE3 = 0x03 * 4, /* Phy Status */
|
||||
VSR_PHY_MODE4 = 0x04 * 4, /* Phy Counter 0 */
|
||||
VSR_PHY_MODE5 = 0x05 * 4, /* Phy Counter 1 */
|
||||
VSR_PHY_MODE6 = 0x06 * 4, /* Event Counter Control */
|
||||
VSR_PHY_MODE7 = 0x07 * 4, /* Event Counter Select */
|
||||
VSR_PHY_MODE8 = 0x08 * 4, /* Event Counter 0 */
|
||||
VSR_PHY_MODE9 = 0x09 * 4, /* Event Counter 1 */
|
||||
VSR_PHY_MODE10 = 0x0A * 4, /* Event Counter 2 */
|
||||
VSR_PHY_MODE11 = 0x0B * 4, /* Event Counter 3 */
|
||||
VSR_PHY_ACT_LED = 0x0C * 4, /* Activity LED control */
|
||||
|
||||
VSR_PHY_FFE_CONTROL = 0x10C,
|
||||
VSR_PHY_DFE_UPDATE_CRTL = 0x110,
|
||||
VSR_REF_CLOCK_CRTL = 0x1A0,
|
||||
};
|
||||
|
||||
enum chip_register_bits {
|
||||
PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0x7 << 8),
|
||||
PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0x7 << 12),
|
||||
PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
|
||||
PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
|
||||
(0x3 << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
|
||||
};
|
||||
|
||||
enum pci_interrupt_cause {
|
||||
/* MAIN_IRQ_CAUSE (R10200) Bits*/
|
||||
MVS_IRQ_COM_IN_I2O_IOP0 = (1 << 0),
|
||||
MVS_IRQ_COM_IN_I2O_IOP1 = (1 << 1),
|
||||
MVS_IRQ_COM_IN_I2O_IOP2 = (1 << 2),
|
||||
MVS_IRQ_COM_IN_I2O_IOP3 = (1 << 3),
|
||||
MVS_IRQ_COM_OUT_I2O_HOS0 = (1 << 4),
|
||||
MVS_IRQ_COM_OUT_I2O_HOS1 = (1 << 5),
|
||||
MVS_IRQ_COM_OUT_I2O_HOS2 = (1 << 6),
|
||||
MVS_IRQ_COM_OUT_I2O_HOS3 = (1 << 7),
|
||||
MVS_IRQ_PCIF_TO_CPU_DRBL0 = (1 << 8),
|
||||
MVS_IRQ_PCIF_TO_CPU_DRBL1 = (1 << 9),
|
||||
MVS_IRQ_PCIF_TO_CPU_DRBL2 = (1 << 10),
|
||||
MVS_IRQ_PCIF_TO_CPU_DRBL3 = (1 << 11),
|
||||
MVS_IRQ_PCIF_DRBL0 = (1 << 12),
|
||||
MVS_IRQ_PCIF_DRBL1 = (1 << 13),
|
||||
MVS_IRQ_PCIF_DRBL2 = (1 << 14),
|
||||
MVS_IRQ_PCIF_DRBL3 = (1 << 15),
|
||||
MVS_IRQ_XOR_A = (1 << 16),
|
||||
MVS_IRQ_XOR_B = (1 << 17),
|
||||
MVS_IRQ_SAS_A = (1 << 18),
|
||||
MVS_IRQ_SAS_B = (1 << 19),
|
||||
MVS_IRQ_CPU_CNTRL = (1 << 20),
|
||||
MVS_IRQ_GPIO = (1 << 21),
|
||||
MVS_IRQ_UART = (1 << 22),
|
||||
MVS_IRQ_SPI = (1 << 23),
|
||||
MVS_IRQ_I2C = (1 << 24),
|
||||
MVS_IRQ_SGPIO = (1 << 25),
|
||||
MVS_IRQ_COM_ERR = (1 << 29),
|
||||
MVS_IRQ_I2O_ERR = (1 << 30),
|
||||
MVS_IRQ_PCIE_ERR = (1 << 31),
|
||||
};
|
||||
|
||||
union reg_phy_cfg {
|
||||
u32 v;
|
||||
struct {
|
||||
u32 phy_reset:1;
|
||||
u32 sas_support:1;
|
||||
u32 sata_support:1;
|
||||
u32 sata_host_mode:1;
|
||||
/*
|
||||
* bit 2: 6Gbps support
|
||||
* bit 1: 3Gbps support
|
||||
* bit 0: 1.5Gbps support
|
||||
*/
|
||||
u32 speed_support:3;
|
||||
u32 snw_3_support:1;
|
||||
u32 tx_lnk_parity:1;
|
||||
/*
|
||||
* bit 5: G1 (1.5Gbps) Without SSC
|
||||
* bit 4: G1 (1.5Gbps) with SSC
|
||||
* bit 3: G2 (3.0Gbps) Without SSC
|
||||
* bit 2: G2 (3.0Gbps) with SSC
|
||||
* bit 1: G3 (6.0Gbps) without SSC
|
||||
* bit 0: G3 (6.0Gbps) with SSC
|
||||
*/
|
||||
u32 tx_spt_phs_lnk_rate:6;
|
||||
/* 8h: 1.5Gbps 9h: 3Gbps Ah: 6Gbps */
|
||||
u32 tx_lgcl_lnk_rate:4;
|
||||
u32 tx_ssc_type:1;
|
||||
u32 sata_spin_up_spt:1;
|
||||
u32 sata_spin_up_en:1;
|
||||
u32 bypass_oob:1;
|
||||
u32 disable_phy:1;
|
||||
u32 rsvd:8;
|
||||
} u;
|
||||
};
|
||||
|
||||
#define MAX_SG_ENTRY 255
|
||||
|
||||
struct mvs_prd_imt {
|
||||
#ifndef __BIG_ENDIAN
|
||||
__le32 len:22;
|
||||
u8 _r_a:2;
|
||||
u8 misc_ctl:4;
|
||||
u8 inter_sel:4;
|
||||
#else
|
||||
u32 inter_sel:4;
|
||||
u32 misc_ctl:4;
|
||||
u32 _r_a:2;
|
||||
u32 len:22;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct mvs_prd {
|
||||
/* 64-bit buffer address */
|
||||
__le64 addr;
|
||||
/* 22-bit length */
|
||||
__le32 im_len;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/*
|
||||
* these registers are accessed through port vendor
|
||||
* specific address/data registers
|
||||
*/
|
||||
enum sas_sata_phy_regs {
|
||||
GENERATION_1_SETTING = 0x118,
|
||||
GENERATION_1_2_SETTING = 0x11C,
|
||||
GENERATION_2_3_SETTING = 0x120,
|
||||
GENERATION_3_4_SETTING = 0x124,
|
||||
};
|
||||
|
||||
#define SPI_CTRL_REG_94XX 0xc800
|
||||
#define SPI_ADDR_REG_94XX 0xc804
|
||||
#define SPI_WR_DATA_REG_94XX 0xc808
|
||||
#define SPI_RD_DATA_REG_94XX 0xc80c
|
||||
#define SPI_CTRL_READ_94XX (1U << 2)
|
||||
#define SPI_ADDR_VLD_94XX (1U << 1)
|
||||
#define SPI_CTRL_SpiStart_94XX (1U << 0)
|
||||
|
||||
static inline int
|
||||
mv_ffc64(u64 v)
|
||||
{
|
||||
u64 x = ~v;
|
||||
return x ? __ffs64(x) : -1;
|
||||
}
|
||||
|
||||
#define r_reg_set_enable(i) \
|
||||
(((i) > 31) ? mr32(MVS_STP_REG_SET_1) : \
|
||||
mr32(MVS_STP_REG_SET_0))
|
||||
|
||||
#define w_reg_set_enable(i, tmp) \
|
||||
(((i) > 31) ? mw32(MVS_STP_REG_SET_1, tmp) : \
|
||||
mw32(MVS_STP_REG_SET_0, tmp))
|
||||
|
||||
extern const struct mvs_dispatch mvs_94xx_dispatch;
|
||||
#endif
|
||||
|
||||
270
drivers/scsi/mvsas/mv_chips.h
Normal file
270
drivers/scsi/mvsas/mv_chips.h
Normal file
|
|
@ -0,0 +1,270 @@
|
|||
/*
|
||||
* Marvell 88SE64xx/88SE94xx register IO interface
|
||||
*
|
||||
* Copyright 2007 Red Hat, Inc.
|
||||
* Copyright 2008 Marvell. <kewei@marvell.com>
|
||||
* Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
|
||||
*
|
||||
* This file is licensed under GPLv2.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the
|
||||
* License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MV_CHIPS_H_
|
||||
#define _MV_CHIPS_H_
|
||||
|
||||
#define mr32(reg) readl(regs + reg)
|
||||
#define mw32(reg, val) writel((val), regs + reg)
|
||||
#define mw32_f(reg, val) do { \
|
||||
mw32(reg, val); \
|
||||
mr32(reg); \
|
||||
} while (0)
|
||||
|
||||
#define iow32(reg, val) outl(val, (unsigned long)(regs + reg))
|
||||
#define ior32(reg) inl((unsigned long)(regs + reg))
|
||||
#define iow16(reg, val) outw((unsigned long)(val, regs + reg))
|
||||
#define ior16(reg) inw((unsigned long)(regs + reg))
|
||||
#define iow8(reg, val) outb((unsigned long)(val, regs + reg))
|
||||
#define ior8(reg) inb((unsigned long)(regs + reg))
|
||||
|
||||
static inline u32 mvs_cr32(struct mvs_info *mvi, u32 addr)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
mw32(MVS_CMD_ADDR, addr);
|
||||
return mr32(MVS_CMD_DATA);
|
||||
}
|
||||
|
||||
static inline void mvs_cw32(struct mvs_info *mvi, u32 addr, u32 val)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
mw32(MVS_CMD_ADDR, addr);
|
||||
mw32(MVS_CMD_DATA, val);
|
||||
}
|
||||
|
||||
static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
return (port < 4) ? mr32(MVS_P0_SER_CTLSTAT + port * 4) :
|
||||
mr32(MVS_P4_SER_CTLSTAT + (port - 4) * 4);
|
||||
}
|
||||
|
||||
static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
if (port < 4)
|
||||
mw32(MVS_P0_SER_CTLSTAT + port * 4, val);
|
||||
else
|
||||
mw32(MVS_P4_SER_CTLSTAT + (port - 4) * 4, val);
|
||||
}
|
||||
|
||||
static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off,
|
||||
u32 off2, u32 port)
|
||||
{
|
||||
void __iomem *regs = mvi->regs + off;
|
||||
void __iomem *regs2 = mvi->regs + off2;
|
||||
return (port < 4) ? readl(regs + port * 8) :
|
||||
readl(regs2 + (port - 4) * 8);
|
||||
}
|
||||
|
||||
static inline void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2,
|
||||
u32 port, u32 val)
|
||||
{
|
||||
void __iomem *regs = mvi->regs + off;
|
||||
void __iomem *regs2 = mvi->regs + off2;
|
||||
if (port < 4)
|
||||
writel(val, regs + port * 8);
|
||||
else
|
||||
writel(val, regs2 + (port - 4) * 8);
|
||||
}
|
||||
|
||||
static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
|
||||
{
|
||||
return mvs_read_port(mvi, MVS_P0_CFG_DATA,
|
||||
MVS_P4_CFG_DATA, port);
|
||||
}
|
||||
|
||||
static inline void mvs_write_port_cfg_data(struct mvs_info *mvi,
|
||||
u32 port, u32 val)
|
||||
{
|
||||
mvs_write_port(mvi, MVS_P0_CFG_DATA,
|
||||
MVS_P4_CFG_DATA, port, val);
|
||||
}
|
||||
|
||||
static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi,
|
||||
u32 port, u32 addr)
|
||||
{
|
||||
mvs_write_port(mvi, MVS_P0_CFG_ADDR,
|
||||
MVS_P4_CFG_ADDR, port, addr);
|
||||
mdelay(10);
|
||||
}
|
||||
|
||||
static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
|
||||
{
|
||||
return mvs_read_port(mvi, MVS_P0_VSR_DATA,
|
||||
MVS_P4_VSR_DATA, port);
|
||||
}
|
||||
|
||||
static inline void mvs_write_port_vsr_data(struct mvs_info *mvi,
|
||||
u32 port, u32 val)
|
||||
{
|
||||
mvs_write_port(mvi, MVS_P0_VSR_DATA,
|
||||
MVS_P4_VSR_DATA, port, val);
|
||||
}
|
||||
|
||||
static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi,
|
||||
u32 port, u32 addr)
|
||||
{
|
||||
mvs_write_port(mvi, MVS_P0_VSR_ADDR,
|
||||
MVS_P4_VSR_ADDR, port, addr);
|
||||
mdelay(10);
|
||||
}
|
||||
|
||||
static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
|
||||
{
|
||||
return mvs_read_port(mvi, MVS_P0_INT_STAT,
|
||||
MVS_P4_INT_STAT, port);
|
||||
}
|
||||
|
||||
static inline void mvs_write_port_irq_stat(struct mvs_info *mvi,
|
||||
u32 port, u32 val)
|
||||
{
|
||||
mvs_write_port(mvi, MVS_P0_INT_STAT,
|
||||
MVS_P4_INT_STAT, port, val);
|
||||
}
|
||||
|
||||
static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
|
||||
{
|
||||
return mvs_read_port(mvi, MVS_P0_INT_MASK,
|
||||
MVS_P4_INT_MASK, port);
|
||||
|
||||
}
|
||||
|
||||
static inline void mvs_write_port_irq_mask(struct mvs_info *mvi,
|
||||
u32 port, u32 val)
|
||||
{
|
||||
mvs_write_port(mvi, MVS_P0_INT_MASK,
|
||||
MVS_P4_INT_MASK, port, val);
|
||||
}
|
||||
|
||||
static inline void mvs_phy_hacks(struct mvs_info *mvi)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
tmp = mvs_cr32(mvi, CMD_PHY_TIMER);
|
||||
tmp &= ~(1 << 9);
|
||||
tmp |= (1 << 10);
|
||||
mvs_cw32(mvi, CMD_PHY_TIMER, tmp);
|
||||
|
||||
/* enable retry 127 times */
|
||||
mvs_cw32(mvi, CMD_SAS_CTL1, 0x7f7f);
|
||||
|
||||
/* extend open frame timeout to max */
|
||||
tmp = mvs_cr32(mvi, CMD_SAS_CTL0);
|
||||
tmp &= ~0xffff;
|
||||
tmp |= 0x3fff;
|
||||
mvs_cw32(mvi, CMD_SAS_CTL0, tmp);
|
||||
|
||||
mvs_cw32(mvi, CMD_WD_TIMER, 0x7a0000);
|
||||
|
||||
/* not to halt for different port op during wideport link change */
|
||||
mvs_cw32(mvi, CMD_APP_ERR_CONFIG, 0xffefbf7d);
|
||||
}
|
||||
|
||||
static inline void mvs_int_sata(struct mvs_info *mvi)
|
||||
{
|
||||
u32 tmp;
|
||||
void __iomem *regs = mvi->regs;
|
||||
tmp = mr32(MVS_INT_STAT_SRS_0);
|
||||
if (tmp)
|
||||
mw32(MVS_INT_STAT_SRS_0, tmp);
|
||||
MVS_CHIP_DISP->clear_active_cmds(mvi);
|
||||
}
|
||||
|
||||
static inline void mvs_int_full(struct mvs_info *mvi)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
u32 tmp, stat;
|
||||
int i;
|
||||
|
||||
stat = mr32(MVS_INT_STAT);
|
||||
mvs_int_rx(mvi, false);
|
||||
|
||||
for (i = 0; i < mvi->chip->n_phy; i++) {
|
||||
tmp = (stat >> i) & (CINT_PORT | CINT_PORT_STOPPED);
|
||||
if (tmp)
|
||||
mvs_int_port(mvi, i, tmp);
|
||||
}
|
||||
|
||||
if (stat & CINT_NON_SPEC_NCQ_ERROR)
|
||||
MVS_CHIP_DISP->non_spec_ncq_error(mvi);
|
||||
|
||||
if (stat & CINT_SRS)
|
||||
mvs_int_sata(mvi);
|
||||
|
||||
mw32(MVS_INT_STAT, stat);
|
||||
}
|
||||
|
||||
static inline void mvs_start_delivery(struct mvs_info *mvi, u32 tx)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
mw32(MVS_TX_PROD_IDX, tx);
|
||||
}
|
||||
|
||||
static inline u32 mvs_rx_update(struct mvs_info *mvi)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
return mr32(MVS_RX_CONS_IDX);
|
||||
}
|
||||
|
||||
static inline u32 mvs_get_prd_size(void)
|
||||
{
|
||||
return sizeof(struct mvs_prd);
|
||||
}
|
||||
|
||||
static inline u32 mvs_get_prd_count(void)
|
||||
{
|
||||
return MAX_SG_ENTRY;
|
||||
}
|
||||
|
||||
static inline void mvs_show_pcie_usage(struct mvs_info *mvi)
|
||||
{
|
||||
u16 link_stat, link_spd;
|
||||
const char *spd[] = {
|
||||
"UnKnown",
|
||||
"2.5",
|
||||
"5.0",
|
||||
};
|
||||
if (mvi->flags & MVF_FLAG_SOC || mvi->id > 0)
|
||||
return;
|
||||
|
||||
pci_read_config_word(mvi->pdev, PCR_LINK_STAT, &link_stat);
|
||||
link_spd = (link_stat & PLS_LINK_SPD) >> PLS_LINK_SPD_OFFS;
|
||||
if (link_spd >= 3)
|
||||
link_spd = 0;
|
||||
dev_printk(KERN_INFO, mvi->dev,
|
||||
"mvsas: PCI-E x%u, Bandwidth Usage: %s Gbps\n",
|
||||
(link_stat & PLS_NEG_LINK_WD) >> PLS_NEG_LINK_WD_OFFS,
|
||||
spd[link_spd]);
|
||||
}
|
||||
|
||||
static inline u32 mvs_hw_max_link_rate(void)
|
||||
{
|
||||
return MAX_LINK_RATE;
|
||||
}
|
||||
|
||||
#endif /* _MV_CHIPS_H_ */
|
||||
|
||||
510
drivers/scsi/mvsas/mv_defs.h
Normal file
510
drivers/scsi/mvsas/mv_defs.h
Normal file
|
|
@ -0,0 +1,510 @@
|
|||
/*
|
||||
* Marvell 88SE64xx/88SE94xx const head file
|
||||
*
|
||||
* Copyright 2007 Red Hat, Inc.
|
||||
* Copyright 2008 Marvell. <kewei@marvell.com>
|
||||
* Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
|
||||
*
|
||||
* This file is licensed under GPLv2.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the
|
||||
* License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
#ifndef _MV_DEFS_H_
|
||||
#define _MV_DEFS_H_
|
||||
|
||||
#define PCI_DEVICE_ID_ARECA_1300 0x1300
|
||||
#define PCI_DEVICE_ID_ARECA_1320 0x1320
|
||||
|
||||
enum chip_flavors {
|
||||
chip_6320,
|
||||
chip_6440,
|
||||
chip_6485,
|
||||
chip_9480,
|
||||
chip_9180,
|
||||
chip_9445,
|
||||
chip_9485,
|
||||
chip_1300,
|
||||
chip_1320
|
||||
};
|
||||
|
||||
/* driver compile-time configuration */
|
||||
enum driver_configuration {
|
||||
MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
|
||||
MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
|
||||
/* software requires power-of-2
|
||||
ring size */
|
||||
MVS_SOC_SLOTS = 64,
|
||||
MVS_SOC_TX_RING_SZ = MVS_SOC_SLOTS * 2,
|
||||
MVS_SOC_RX_RING_SZ = MVS_SOC_SLOTS * 2,
|
||||
|
||||
MVS_SLOT_BUF_SZ = 8192, /* cmd tbl + IU + status + PRD */
|
||||
MVS_SSP_CMD_SZ = 64, /* SSP command table buffer size */
|
||||
MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
|
||||
MVS_OAF_SZ = 64, /* Open address frame buffer size */
|
||||
MVS_QUEUE_SIZE = 64, /* Support Queue depth */
|
||||
MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
|
||||
};
|
||||
|
||||
/* unchangeable hardware details */
|
||||
enum hardware_details {
|
||||
MVS_MAX_PHYS = 8, /* max. possible phys */
|
||||
MVS_MAX_PORTS = 8, /* max. possible ports */
|
||||
MVS_SOC_PHYS = 4, /* soc phys */
|
||||
MVS_SOC_PORTS = 4, /* soc phys */
|
||||
MVS_MAX_DEVICES = 1024, /* max supported device */
|
||||
};
|
||||
|
||||
/* peripheral registers (BAR2) */
|
||||
enum peripheral_registers {
|
||||
SPI_CTL = 0x10, /* EEPROM control */
|
||||
SPI_CMD = 0x14, /* EEPROM command */
|
||||
SPI_DATA = 0x18, /* EEPROM data */
|
||||
};
|
||||
|
||||
enum peripheral_register_bits {
|
||||
TWSI_RDY = (1U << 7), /* EEPROM interface ready */
|
||||
TWSI_RD = (1U << 4), /* EEPROM read access */
|
||||
|
||||
SPI_ADDR_MASK = 0x3ffff, /* bits 17:0 */
|
||||
};
|
||||
|
||||
enum hw_register_bits {
|
||||
/* MVS_GBL_CTL */
|
||||
INT_EN = (1U << 1), /* Global int enable */
|
||||
HBA_RST = (1U << 0), /* HBA reset */
|
||||
|
||||
/* MVS_GBL_INT_STAT */
|
||||
INT_XOR = (1U << 4), /* XOR engine event */
|
||||
INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
|
||||
|
||||
/* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
|
||||
SATA_TARGET = (1U << 16), /* port0 SATA target enable */
|
||||
MODE_AUTO_DET_PORT7 = (1U << 15), /* port0 SAS/SATA autodetect */
|
||||
MODE_AUTO_DET_PORT6 = (1U << 14),
|
||||
MODE_AUTO_DET_PORT5 = (1U << 13),
|
||||
MODE_AUTO_DET_PORT4 = (1U << 12),
|
||||
MODE_AUTO_DET_PORT3 = (1U << 11),
|
||||
MODE_AUTO_DET_PORT2 = (1U << 10),
|
||||
MODE_AUTO_DET_PORT1 = (1U << 9),
|
||||
MODE_AUTO_DET_PORT0 = (1U << 8),
|
||||
MODE_AUTO_DET_EN = MODE_AUTO_DET_PORT0 | MODE_AUTO_DET_PORT1 |
|
||||
MODE_AUTO_DET_PORT2 | MODE_AUTO_DET_PORT3 |
|
||||
MODE_AUTO_DET_PORT4 | MODE_AUTO_DET_PORT5 |
|
||||
MODE_AUTO_DET_PORT6 | MODE_AUTO_DET_PORT7,
|
||||
MODE_SAS_PORT7_MASK = (1U << 7), /* port0 SAS(1), SATA(0) mode */
|
||||
MODE_SAS_PORT6_MASK = (1U << 6),
|
||||
MODE_SAS_PORT5_MASK = (1U << 5),
|
||||
MODE_SAS_PORT4_MASK = (1U << 4),
|
||||
MODE_SAS_PORT3_MASK = (1U << 3),
|
||||
MODE_SAS_PORT2_MASK = (1U << 2),
|
||||
MODE_SAS_PORT1_MASK = (1U << 1),
|
||||
MODE_SAS_PORT0_MASK = (1U << 0),
|
||||
MODE_SAS_SATA = MODE_SAS_PORT0_MASK | MODE_SAS_PORT1_MASK |
|
||||
MODE_SAS_PORT2_MASK | MODE_SAS_PORT3_MASK |
|
||||
MODE_SAS_PORT4_MASK | MODE_SAS_PORT5_MASK |
|
||||
MODE_SAS_PORT6_MASK | MODE_SAS_PORT7_MASK,
|
||||
|
||||
/* SAS_MODE value may be
|
||||
* dictated (in hw) by values
|
||||
* of SATA_TARGET & AUTO_DET
|
||||
*/
|
||||
|
||||
/* MVS_TX_CFG */
|
||||
TX_EN = (1U << 16), /* Enable TX */
|
||||
TX_RING_SZ_MASK = 0xfff, /* TX ring size, bits 11:0 */
|
||||
|
||||
/* MVS_RX_CFG */
|
||||
RX_EN = (1U << 16), /* Enable RX */
|
||||
RX_RING_SZ_MASK = 0xfff, /* RX ring size, bits 11:0 */
|
||||
|
||||
/* MVS_INT_COAL */
|
||||
COAL_EN = (1U << 16), /* Enable int coalescing */
|
||||
|
||||
/* MVS_INT_STAT, MVS_INT_MASK */
|
||||
CINT_I2C = (1U << 31), /* I2C event */
|
||||
CINT_SW0 = (1U << 30), /* software event 0 */
|
||||
CINT_SW1 = (1U << 29), /* software event 1 */
|
||||
CINT_PRD_BC = (1U << 28), /* PRD BC err for read cmd */
|
||||
CINT_DMA_PCIE = (1U << 27), /* DMA to PCIE timeout */
|
||||
CINT_MEM = (1U << 26), /* int mem parity err */
|
||||
CINT_I2C_SLAVE = (1U << 25), /* slave I2C event */
|
||||
CINT_NON_SPEC_NCQ_ERROR = (1U << 25), /* Non specific NCQ error */
|
||||
CINT_SRS = (1U << 3), /* SRS event */
|
||||
CINT_CI_STOP = (1U << 1), /* cmd issue stopped */
|
||||
CINT_DONE = (1U << 0), /* cmd completion */
|
||||
|
||||
/* shl for ports 1-3 */
|
||||
CINT_PORT_STOPPED = (1U << 16), /* port0 stopped */
|
||||
CINT_PORT = (1U << 8), /* port0 event */
|
||||
CINT_PORT_MASK_OFFSET = 8,
|
||||
CINT_PORT_MASK = (0xFF << CINT_PORT_MASK_OFFSET),
|
||||
CINT_PHY_MASK_OFFSET = 4,
|
||||
CINT_PHY_MASK = (0x0F << CINT_PHY_MASK_OFFSET),
|
||||
|
||||
/* TX (delivery) ring bits */
|
||||
TXQ_CMD_SHIFT = 29,
|
||||
TXQ_CMD_SSP = 1, /* SSP protocol */
|
||||
TXQ_CMD_SMP = 2, /* SMP protocol */
|
||||
TXQ_CMD_STP = 3, /* STP/SATA protocol */
|
||||
TXQ_CMD_SSP_FREE_LIST = 4, /* add to SSP target free list */
|
||||
TXQ_CMD_SLOT_RESET = 7, /* reset command slot */
|
||||
TXQ_MODE_I = (1U << 28), /* mode: 0=target,1=initiator */
|
||||
TXQ_MODE_TARGET = 0,
|
||||
TXQ_MODE_INITIATOR = 1,
|
||||
TXQ_PRIO_HI = (1U << 27), /* priority: 0=normal, 1=high */
|
||||
TXQ_PRI_NORMAL = 0,
|
||||
TXQ_PRI_HIGH = 1,
|
||||
TXQ_SRS_SHIFT = 20, /* SATA register set */
|
||||
TXQ_SRS_MASK = 0x7f,
|
||||
TXQ_PHY_SHIFT = 12, /* PHY bitmap */
|
||||
TXQ_PHY_MASK = 0xff,
|
||||
TXQ_SLOT_MASK = 0xfff, /* slot number */
|
||||
|
||||
/* RX (completion) ring bits */
|
||||
RXQ_GOOD = (1U << 23), /* Response good */
|
||||
RXQ_SLOT_RESET = (1U << 21), /* Slot reset complete */
|
||||
RXQ_CMD_RX = (1U << 20), /* target cmd received */
|
||||
RXQ_ATTN = (1U << 19), /* attention */
|
||||
RXQ_RSP = (1U << 18), /* response frame xfer'd */
|
||||
RXQ_ERR = (1U << 17), /* err info rec xfer'd */
|
||||
RXQ_DONE = (1U << 16), /* cmd complete */
|
||||
RXQ_SLOT_MASK = 0xfff, /* slot number */
|
||||
|
||||
/* mvs_cmd_hdr bits */
|
||||
MCH_PRD_LEN_SHIFT = 16, /* 16-bit PRD table len */
|
||||
MCH_SSP_FR_TYPE_SHIFT = 13, /* SSP frame type */
|
||||
|
||||
/* SSP initiator only */
|
||||
MCH_SSP_FR_CMD = 0x0, /* COMMAND frame */
|
||||
|
||||
/* SSP initiator or target */
|
||||
MCH_SSP_FR_TASK = 0x1, /* TASK frame */
|
||||
|
||||
/* SSP target only */
|
||||
MCH_SSP_FR_XFER_RDY = 0x4, /* XFER_RDY frame */
|
||||
MCH_SSP_FR_RESP = 0x5, /* RESPONSE frame */
|
||||
MCH_SSP_FR_READ = 0x6, /* Read DATA frame(s) */
|
||||
MCH_SSP_FR_READ_RESP = 0x7, /* ditto, plus RESPONSE */
|
||||
|
||||
MCH_SSP_MODE_PASSTHRU = 1,
|
||||
MCH_SSP_MODE_NORMAL = 0,
|
||||
MCH_PASSTHRU = (1U << 12), /* pass-through (SSP) */
|
||||
MCH_FBURST = (1U << 11), /* first burst (SSP) */
|
||||
MCH_CHK_LEN = (1U << 10), /* chk xfer len (SSP) */
|
||||
MCH_RETRY = (1U << 9), /* tport layer retry (SSP) */
|
||||
MCH_PROTECTION = (1U << 8), /* protection info rec (SSP) */
|
||||
MCH_RESET = (1U << 7), /* Reset (STP/SATA) */
|
||||
MCH_FPDMA = (1U << 6), /* First party DMA (STP/SATA) */
|
||||
MCH_ATAPI = (1U << 5), /* ATAPI (STP/SATA) */
|
||||
MCH_BIST = (1U << 4), /* BIST activate (STP/SATA) */
|
||||
MCH_PMP_MASK = 0xf, /* PMP from cmd FIS (STP/SATA)*/
|
||||
|
||||
CCTL_RST = (1U << 5), /* port logic reset */
|
||||
|
||||
/* 0(LSB first), 1(MSB first) */
|
||||
CCTL_ENDIAN_DATA = (1U << 3), /* PRD data */
|
||||
CCTL_ENDIAN_RSP = (1U << 2), /* response frame */
|
||||
CCTL_ENDIAN_OPEN = (1U << 1), /* open address frame */
|
||||
CCTL_ENDIAN_CMD = (1U << 0), /* command table */
|
||||
|
||||
/* MVS_Px_SER_CTLSTAT (per-phy control) */
|
||||
PHY_SSP_RST = (1U << 3), /* reset SSP link layer */
|
||||
PHY_BCAST_CHG = (1U << 2), /* broadcast(change) notif */
|
||||
PHY_RST_HARD = (1U << 1), /* hard reset + phy reset */
|
||||
PHY_RST = (1U << 0), /* phy reset */
|
||||
PHY_READY_MASK = (1U << 20),
|
||||
|
||||
/* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */
|
||||
PHYEV_DEC_ERR = (1U << 24), /* Phy Decoding Error */
|
||||
PHYEV_DCDR_ERR = (1U << 23), /* STP Deocder Error */
|
||||
PHYEV_CRC_ERR = (1U << 22), /* STP CRC Error */
|
||||
PHYEV_UNASSOC_FIS = (1U << 19), /* unassociated FIS rx'd */
|
||||
PHYEV_AN = (1U << 18), /* SATA async notification */
|
||||
PHYEV_BIST_ACT = (1U << 17), /* BIST activate FIS */
|
||||
PHYEV_SIG_FIS = (1U << 16), /* signature FIS */
|
||||
PHYEV_POOF = (1U << 12), /* phy ready from 1 -> 0 */
|
||||
PHYEV_IU_BIG = (1U << 11), /* IU too long err */
|
||||
PHYEV_IU_SMALL = (1U << 10), /* IU too short err */
|
||||
PHYEV_UNK_TAG = (1U << 9), /* unknown tag */
|
||||
PHYEV_BROAD_CH = (1U << 8), /* broadcast(CHANGE) */
|
||||
PHYEV_COMWAKE = (1U << 7), /* COMWAKE rx'd */
|
||||
PHYEV_PORT_SEL = (1U << 6), /* port selector present */
|
||||
PHYEV_HARD_RST = (1U << 5), /* hard reset rx'd */
|
||||
PHYEV_ID_TMOUT = (1U << 4), /* identify timeout */
|
||||
PHYEV_ID_FAIL = (1U << 3), /* identify failed */
|
||||
PHYEV_ID_DONE = (1U << 2), /* identify done */
|
||||
PHYEV_HARD_RST_DONE = (1U << 1), /* hard reset done */
|
||||
PHYEV_RDY_CH = (1U << 0), /* phy ready changed state */
|
||||
|
||||
/* MVS_PCS */
|
||||
PCS_EN_SATA_REG_SHIFT = (16), /* Enable SATA Register Set */
|
||||
PCS_EN_PORT_XMT_SHIFT = (12), /* Enable Port Transmit */
|
||||
PCS_EN_PORT_XMT_SHIFT2 = (8), /* For 6485 */
|
||||
PCS_SATA_RETRY = (1U << 8), /* retry ctl FIS on R_ERR */
|
||||
PCS_RSP_RX_EN = (1U << 7), /* raw response rx */
|
||||
PCS_SATA_RETRY_2 = (1U << 6), /* For 9180 */
|
||||
PCS_SELF_CLEAR = (1U << 5), /* self-clearing int mode */
|
||||
PCS_FIS_RX_EN = (1U << 4), /* FIS rx enable */
|
||||
PCS_CMD_STOP_ERR = (1U << 3), /* cmd stop-on-err enable */
|
||||
PCS_CMD_RST = (1U << 1), /* reset cmd issue */
|
||||
PCS_CMD_EN = (1U << 0), /* enable cmd issue */
|
||||
|
||||
/* Port n Attached Device Info */
|
||||
PORT_DEV_SSP_TRGT = (1U << 19),
|
||||
PORT_DEV_SMP_TRGT = (1U << 18),
|
||||
PORT_DEV_STP_TRGT = (1U << 17),
|
||||
PORT_DEV_SSP_INIT = (1U << 11),
|
||||
PORT_DEV_SMP_INIT = (1U << 10),
|
||||
PORT_DEV_STP_INIT = (1U << 9),
|
||||
PORT_PHY_ID_MASK = (0xFFU << 24),
|
||||
PORT_SSP_TRGT_MASK = (0x1U << 19),
|
||||
PORT_SSP_INIT_MASK = (0x1U << 11),
|
||||
PORT_DEV_TRGT_MASK = (0x7U << 17),
|
||||
PORT_DEV_INIT_MASK = (0x7U << 9),
|
||||
PORT_DEV_TYPE_MASK = (0x7U << 0),
|
||||
|
||||
/* Port n PHY Status */
|
||||
PHY_RDY = (1U << 2),
|
||||
PHY_DW_SYNC = (1U << 1),
|
||||
PHY_OOB_DTCTD = (1U << 0),
|
||||
|
||||
/* VSR */
|
||||
/* PHYMODE 6 (CDB) */
|
||||
PHY_MODE6_LATECLK = (1U << 29), /* Lock Clock */
|
||||
PHY_MODE6_DTL_SPEED = (1U << 27), /* Digital Loop Speed */
|
||||
PHY_MODE6_FC_ORDER = (1U << 26), /* Fibre Channel Mode Order*/
|
||||
PHY_MODE6_MUCNT_EN = (1U << 24), /* u Count Enable */
|
||||
PHY_MODE6_SEL_MUCNT_LEN = (1U << 22), /* Training Length Select */
|
||||
PHY_MODE6_SELMUPI = (1U << 20), /* Phase Multi Select (init) */
|
||||
PHY_MODE6_SELMUPF = (1U << 18), /* Phase Multi Select (final) */
|
||||
PHY_MODE6_SELMUFF = (1U << 16), /* Freq Loop Multi Sel(final) */
|
||||
PHY_MODE6_SELMUFI = (1U << 14), /* Freq Loop Multi Sel(init) */
|
||||
PHY_MODE6_FREEZE_LOOP = (1U << 12), /* Freeze Rx CDR Loop */
|
||||
PHY_MODE6_INT_RXFOFFS = (1U << 3), /* Rx CDR Freq Loop Enable */
|
||||
PHY_MODE6_FRC_RXFOFFS = (1U << 2), /* Initial Rx CDR Offset */
|
||||
PHY_MODE6_STAU_0D8 = (1U << 1), /* Rx CDR Freq Loop Saturate */
|
||||
PHY_MODE6_RXSAT_DIS = (1U << 0), /* Saturate Ctl */
|
||||
};
|
||||
|
||||
/* SAS/SATA configuration port registers, aka phy registers */
|
||||
enum sas_sata_config_port_regs {
|
||||
PHYR_IDENTIFY = 0x00, /* info for IDENTIFY frame */
|
||||
PHYR_ADDR_LO = 0x04, /* my SAS address (low) */
|
||||
PHYR_ADDR_HI = 0x08, /* my SAS address (high) */
|
||||
PHYR_ATT_DEV_INFO = 0x0C, /* attached device info */
|
||||
PHYR_ATT_ADDR_LO = 0x10, /* attached dev SAS addr (low) */
|
||||
PHYR_ATT_ADDR_HI = 0x14, /* attached dev SAS addr (high) */
|
||||
PHYR_SATA_CTL = 0x18, /* SATA control */
|
||||
PHYR_PHY_STAT = 0x1C, /* PHY status */
|
||||
PHYR_SATA_SIG0 = 0x20, /*port SATA signature FIS(Byte 0-3) */
|
||||
PHYR_SATA_SIG1 = 0x24, /*port SATA signature FIS(Byte 4-7) */
|
||||
PHYR_SATA_SIG2 = 0x28, /*port SATA signature FIS(Byte 8-11) */
|
||||
PHYR_SATA_SIG3 = 0x2c, /*port SATA signature FIS(Byte 12-15) */
|
||||
PHYR_R_ERR_COUNT = 0x30, /* port R_ERR count register */
|
||||
PHYR_CRC_ERR_COUNT = 0x34, /* port CRC error count register */
|
||||
PHYR_WIDE_PORT = 0x38, /* wide port participating */
|
||||
PHYR_CURRENT0 = 0x80, /* current connection info 0 */
|
||||
PHYR_CURRENT1 = 0x84, /* current connection info 1 */
|
||||
PHYR_CURRENT2 = 0x88, /* current connection info 2 */
|
||||
CONFIG_ID_FRAME0 = 0x100, /* Port device ID frame register 0 */
|
||||
CONFIG_ID_FRAME1 = 0x104, /* Port device ID frame register 1 */
|
||||
CONFIG_ID_FRAME2 = 0x108, /* Port device ID frame register 2 */
|
||||
CONFIG_ID_FRAME3 = 0x10c, /* Port device ID frame register 3 */
|
||||
CONFIG_ID_FRAME4 = 0x110, /* Port device ID frame register 4 */
|
||||
CONFIG_ID_FRAME5 = 0x114, /* Port device ID frame register 5 */
|
||||
CONFIG_ID_FRAME6 = 0x118, /* Port device ID frame register 6 */
|
||||
CONFIG_ATT_ID_FRAME0 = 0x11c, /* attached ID frame register 0 */
|
||||
CONFIG_ATT_ID_FRAME1 = 0x120, /* attached ID frame register 1 */
|
||||
CONFIG_ATT_ID_FRAME2 = 0x124, /* attached ID frame register 2 */
|
||||
CONFIG_ATT_ID_FRAME3 = 0x128, /* attached ID frame register 3 */
|
||||
CONFIG_ATT_ID_FRAME4 = 0x12c, /* attached ID frame register 4 */
|
||||
CONFIG_ATT_ID_FRAME5 = 0x130, /* attached ID frame register 5 */
|
||||
CONFIG_ATT_ID_FRAME6 = 0x134, /* attached ID frame register 6 */
|
||||
};
|
||||
|
||||
enum sas_cmd_port_registers {
|
||||
CMD_CMRST_OOB_DET = 0x100, /* COMRESET OOB detect register */
|
||||
CMD_CMWK_OOB_DET = 0x104, /* COMWAKE OOB detect register */
|
||||
CMD_CMSAS_OOB_DET = 0x108, /* COMSAS OOB detect register */
|
||||
CMD_BRST_OOB_DET = 0x10c, /* burst OOB detect register */
|
||||
CMD_OOB_SPACE = 0x110, /* OOB space control register */
|
||||
CMD_OOB_BURST = 0x114, /* OOB burst control register */
|
||||
CMD_PHY_TIMER = 0x118, /* PHY timer control register */
|
||||
CMD_PHY_CONFIG0 = 0x11c, /* PHY config register 0 */
|
||||
CMD_PHY_CONFIG1 = 0x120, /* PHY config register 1 */
|
||||
CMD_SAS_CTL0 = 0x124, /* SAS control register 0 */
|
||||
CMD_SAS_CTL1 = 0x128, /* SAS control register 1 */
|
||||
CMD_SAS_CTL2 = 0x12c, /* SAS control register 2 */
|
||||
CMD_SAS_CTL3 = 0x130, /* SAS control register 3 */
|
||||
CMD_ID_TEST = 0x134, /* ID test register */
|
||||
CMD_PL_TIMER = 0x138, /* PL timer register */
|
||||
CMD_WD_TIMER = 0x13c, /* WD timer register */
|
||||
CMD_PORT_SEL_COUNT = 0x140, /* port selector count register */
|
||||
CMD_APP_MEM_CTL = 0x144, /* Application Memory Control */
|
||||
CMD_XOR_MEM_CTL = 0x148, /* XOR Block Memory Control */
|
||||
CMD_DMA_MEM_CTL = 0x14c, /* DMA Block Memory Control */
|
||||
CMD_PORT_MEM_CTL0 = 0x150, /* Port Memory Control 0 */
|
||||
CMD_PORT_MEM_CTL1 = 0x154, /* Port Memory Control 1 */
|
||||
CMD_SATA_PORT_MEM_CTL0 = 0x158, /* SATA Port Memory Control 0 */
|
||||
CMD_SATA_PORT_MEM_CTL1 = 0x15c, /* SATA Port Memory Control 1 */
|
||||
CMD_XOR_MEM_BIST_CTL = 0x160, /* XOR Memory BIST Control */
|
||||
CMD_XOR_MEM_BIST_STAT = 0x164, /* XOR Memroy BIST Status */
|
||||
CMD_DMA_MEM_BIST_CTL = 0x168, /* DMA Memory BIST Control */
|
||||
CMD_DMA_MEM_BIST_STAT = 0x16c, /* DMA Memory BIST Status */
|
||||
CMD_PORT_MEM_BIST_CTL = 0x170, /* Port Memory BIST Control */
|
||||
CMD_PORT_MEM_BIST_STAT0 = 0x174, /* Port Memory BIST Status 0 */
|
||||
CMD_PORT_MEM_BIST_STAT1 = 0x178, /* Port Memory BIST Status 1 */
|
||||
CMD_STP_MEM_BIST_CTL = 0x17c, /* STP Memory BIST Control */
|
||||
CMD_STP_MEM_BIST_STAT0 = 0x180, /* STP Memory BIST Status 0 */
|
||||
CMD_STP_MEM_BIST_STAT1 = 0x184, /* STP Memory BIST Status 1 */
|
||||
CMD_RESET_COUNT = 0x188, /* Reset Count */
|
||||
CMD_MONTR_DATA_SEL = 0x18C, /* Monitor Data/Select */
|
||||
CMD_PLL_PHY_CONFIG = 0x190, /* PLL/PHY Configuration */
|
||||
CMD_PHY_CTL = 0x194, /* PHY Control and Status */
|
||||
CMD_PHY_TEST_COUNT0 = 0x198, /* Phy Test Count 0 */
|
||||
CMD_PHY_TEST_COUNT1 = 0x19C, /* Phy Test Count 1 */
|
||||
CMD_PHY_TEST_COUNT2 = 0x1A0, /* Phy Test Count 2 */
|
||||
CMD_APP_ERR_CONFIG = 0x1A4, /* Application Error Configuration */
|
||||
CMD_PND_FIFO_CTL0 = 0x1A8, /* Pending FIFO Control 0 */
|
||||
CMD_HOST_CTL = 0x1AC, /* Host Control Status */
|
||||
CMD_HOST_WR_DATA = 0x1B0, /* Host Write Data */
|
||||
CMD_HOST_RD_DATA = 0x1B4, /* Host Read Data */
|
||||
CMD_PHY_MODE_21 = 0x1B8, /* Phy Mode 21 */
|
||||
CMD_SL_MODE0 = 0x1BC, /* SL Mode 0 */
|
||||
CMD_SL_MODE1 = 0x1C0, /* SL Mode 1 */
|
||||
CMD_PND_FIFO_CTL1 = 0x1C4, /* Pending FIFO Control 1 */
|
||||
CMD_PORT_LAYER_TIMER1 = 0x1E0, /* Port Layer Timer 1 */
|
||||
CMD_LINK_TIMER = 0x1E4, /* Link Timer */
|
||||
};
|
||||
|
||||
enum mvs_info_flags {
|
||||
MVF_PHY_PWR_FIX = (1U << 1), /* bug workaround */
|
||||
MVF_FLAG_SOC = (1U << 2), /* SoC integrated controllers */
|
||||
};
|
||||
|
||||
enum mvs_event_flags {
|
||||
PHY_PLUG_EVENT = (3U),
|
||||
PHY_PLUG_IN = (1U << 0), /* phy plug in */
|
||||
PHY_PLUG_OUT = (1U << 1), /* phy plug out */
|
||||
EXP_BRCT_CHG = (1U << 2), /* broadcast change */
|
||||
};
|
||||
|
||||
enum mvs_port_type {
|
||||
PORT_TGT_MASK = (1U << 5),
|
||||
PORT_INIT_PORT = (1U << 4),
|
||||
PORT_TGT_PORT = (1U << 3),
|
||||
PORT_INIT_TGT_PORT = (PORT_INIT_PORT | PORT_TGT_PORT),
|
||||
PORT_TYPE_SAS = (1U << 1),
|
||||
PORT_TYPE_SATA = (1U << 0),
|
||||
};
|
||||
|
||||
/* Command Table Format */
|
||||
enum ct_format {
|
||||
/* SSP */
|
||||
SSP_F_H = 0x00,
|
||||
SSP_F_IU = 0x18,
|
||||
SSP_F_MAX = 0x4D,
|
||||
/* STP */
|
||||
STP_CMD_FIS = 0x00,
|
||||
STP_ATAPI_CMD = 0x40,
|
||||
STP_F_MAX = 0x10,
|
||||
/* SMP */
|
||||
SMP_F_T = 0x00,
|
||||
SMP_F_DEP = 0x01,
|
||||
SMP_F_MAX = 0x101,
|
||||
};
|
||||
|
||||
enum status_buffer {
|
||||
SB_EIR_OFF = 0x00, /* Error Information Record */
|
||||
SB_RFB_OFF = 0x08, /* Response Frame Buffer */
|
||||
SB_RFB_MAX = 0x400, /* RFB size*/
|
||||
};
|
||||
|
||||
enum error_info_rec {
|
||||
CMD_ISS_STPD = (1U << 31), /* Cmd Issue Stopped */
|
||||
CMD_PI_ERR = (1U << 30), /* Protection info error. see flags2 */
|
||||
RSP_OVER = (1U << 29), /* rsp buffer overflow */
|
||||
RETRY_LIM = (1U << 28), /* FIS/frame retry limit exceeded */
|
||||
UNK_FIS = (1U << 27), /* unknown FIS */
|
||||
DMA_TERM = (1U << 26), /* DMA terminate primitive rx'd */
|
||||
SYNC_ERR = (1U << 25), /* SYNC rx'd during frame xmit */
|
||||
TFILE_ERR = (1U << 24), /* SATA taskfile Error bit set */
|
||||
R_ERR = (1U << 23), /* SATA returned R_ERR prim */
|
||||
RD_OFS = (1U << 20), /* Read DATA frame invalid offset */
|
||||
XFER_RDY_OFS = (1U << 19), /* XFER_RDY offset error */
|
||||
UNEXP_XFER_RDY = (1U << 18), /* unexpected XFER_RDY error */
|
||||
DATA_OVER_UNDER = (1U << 16), /* data overflow/underflow */
|
||||
INTERLOCK = (1U << 15), /* interlock error */
|
||||
NAK = (1U << 14), /* NAK rx'd */
|
||||
ACK_NAK_TO = (1U << 13), /* ACK/NAK timeout */
|
||||
CXN_CLOSED = (1U << 12), /* cxn closed w/out ack/nak */
|
||||
OPEN_TO = (1U << 11), /* I_T nexus lost, open cxn timeout */
|
||||
PATH_BLOCKED = (1U << 10), /* I_T nexus lost, pathway blocked */
|
||||
NO_DEST = (1U << 9), /* I_T nexus lost, no destination */
|
||||
STP_RES_BSY = (1U << 8), /* STP resources busy */
|
||||
BREAK = (1U << 7), /* break received */
|
||||
BAD_DEST = (1U << 6), /* bad destination */
|
||||
BAD_PROTO = (1U << 5), /* protocol not supported */
|
||||
BAD_RATE = (1U << 4), /* cxn rate not supported */
|
||||
WRONG_DEST = (1U << 3), /* wrong destination error */
|
||||
CREDIT_TO = (1U << 2), /* credit timeout */
|
||||
WDOG_TO = (1U << 1), /* watchdog timeout */
|
||||
BUF_PAR = (1U << 0), /* buffer parity error */
|
||||
};
|
||||
|
||||
enum error_info_rec_2 {
|
||||
SLOT_BSY_ERR = (1U << 31), /* Slot Busy Error */
|
||||
GRD_CHK_ERR = (1U << 14), /* Guard Check Error */
|
||||
APP_CHK_ERR = (1U << 13), /* Application Check error */
|
||||
REF_CHK_ERR = (1U << 12), /* Reference Check Error */
|
||||
USR_BLK_NM = (1U << 0), /* User Block Number */
|
||||
};
|
||||
|
||||
enum pci_cfg_register_bits {
|
||||
PCTL_PWR_OFF = (0xFU << 24),
|
||||
PCTL_COM_ON = (0xFU << 20),
|
||||
PCTL_LINK_RST = (0xFU << 16),
|
||||
PCTL_LINK_OFFS = (16),
|
||||
PCTL_PHY_DSBL = (0xFU << 12),
|
||||
PCTL_PHY_DSBL_OFFS = (12),
|
||||
PRD_REQ_SIZE = (0x4000),
|
||||
PRD_REQ_MASK = (0x00007000),
|
||||
PLS_NEG_LINK_WD = (0x3FU << 4),
|
||||
PLS_NEG_LINK_WD_OFFS = 4,
|
||||
PLS_LINK_SPD = (0x0FU << 0),
|
||||
PLS_LINK_SPD_OFFS = 0,
|
||||
};
|
||||
|
||||
enum open_frame_protocol {
|
||||
PROTOCOL_SMP = 0x0,
|
||||
PROTOCOL_SSP = 0x1,
|
||||
PROTOCOL_STP = 0x2,
|
||||
};
|
||||
|
||||
/* define for response frame datapres field */
|
||||
enum datapres_field {
|
||||
NO_DATA = 0,
|
||||
RESPONSE_DATA = 1,
|
||||
SENSE_DATA = 2,
|
||||
};
|
||||
|
||||
/* define task management IU */
|
||||
struct mvs_tmf_task{
|
||||
u8 tmf;
|
||||
u16 tag_of_task_to_be_managed;
|
||||
};
|
||||
#endif
|
||||
876
drivers/scsi/mvsas/mv_init.c
Normal file
876
drivers/scsi/mvsas/mv_init.c
Normal file
|
|
@ -0,0 +1,876 @@
|
|||
/*
|
||||
* Marvell 88SE64xx/88SE94xx pci init
|
||||
*
|
||||
* Copyright 2007 Red Hat, Inc.
|
||||
* Copyright 2008 Marvell. <kewei@marvell.com>
|
||||
* Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
|
||||
*
|
||||
* This file is licensed under GPLv2.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the
|
||||
* License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
|
||||
#include "mv_sas.h"
|
||||
|
||||
static int lldd_max_execute_num = 1;
|
||||
module_param_named(collector, lldd_max_execute_num, int, S_IRUGO);
|
||||
MODULE_PARM_DESC(collector, "\n"
|
||||
"\tIf greater than one, tells the SAS Layer to run in Task Collector\n"
|
||||
"\tMode. If 1 or 0, tells the SAS Layer to run in Direct Mode.\n"
|
||||
"\tThe mvsas SAS LLDD supports both modes.\n"
|
||||
"\tDefault: 1 (Direct Mode).\n");
|
||||
|
||||
int interrupt_coalescing = 0x80;
|
||||
|
||||
static struct scsi_transport_template *mvs_stt;
|
||||
struct kmem_cache *mvs_task_list_cache;
|
||||
static const struct mvs_chip_info mvs_chips[] = {
|
||||
[chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
|
||||
[chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
|
||||
[chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },
|
||||
[chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
|
||||
[chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
|
||||
[chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
|
||||
[chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
|
||||
[chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
|
||||
[chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
|
||||
};
|
||||
|
||||
struct device_attribute *mvst_host_attrs[];
|
||||
|
||||
#define SOC_SAS_NUM 2
|
||||
|
||||
static struct scsi_host_template mvs_sht = {
|
||||
.module = THIS_MODULE,
|
||||
.name = DRV_NAME,
|
||||
.queuecommand = sas_queuecommand,
|
||||
.target_alloc = sas_target_alloc,
|
||||
.slave_configure = sas_slave_configure,
|
||||
.scan_finished = mvs_scan_finished,
|
||||
.scan_start = mvs_scan_start,
|
||||
.change_queue_depth = sas_change_queue_depth,
|
||||
.change_queue_type = sas_change_queue_type,
|
||||
.bios_param = sas_bios_param,
|
||||
.can_queue = 1,
|
||||
.cmd_per_lun = 1,
|
||||
.this_id = -1,
|
||||
.sg_tablesize = SG_ALL,
|
||||
.max_sectors = SCSI_DEFAULT_MAX_SECTORS,
|
||||
.use_clustering = ENABLE_CLUSTERING,
|
||||
.eh_device_reset_handler = sas_eh_device_reset_handler,
|
||||
.eh_bus_reset_handler = sas_eh_bus_reset_handler,
|
||||
.target_destroy = sas_target_destroy,
|
||||
.ioctl = sas_ioctl,
|
||||
.shost_attrs = mvst_host_attrs,
|
||||
};
|
||||
|
||||
static struct sas_domain_function_template mvs_transport_ops = {
|
||||
.lldd_dev_found = mvs_dev_found,
|
||||
.lldd_dev_gone = mvs_dev_gone,
|
||||
.lldd_execute_task = mvs_queue_command,
|
||||
.lldd_control_phy = mvs_phy_control,
|
||||
|
||||
.lldd_abort_task = mvs_abort_task,
|
||||
.lldd_abort_task_set = mvs_abort_task_set,
|
||||
.lldd_clear_aca = mvs_clear_aca,
|
||||
.lldd_clear_task_set = mvs_clear_task_set,
|
||||
.lldd_I_T_nexus_reset = mvs_I_T_nexus_reset,
|
||||
.lldd_lu_reset = mvs_lu_reset,
|
||||
.lldd_query_task = mvs_query_task,
|
||||
.lldd_port_formed = mvs_port_formed,
|
||||
.lldd_port_deformed = mvs_port_deformed,
|
||||
|
||||
};
|
||||
|
||||
static void mvs_phy_init(struct mvs_info *mvi, int phy_id)
|
||||
{
|
||||
struct mvs_phy *phy = &mvi->phy[phy_id];
|
||||
struct asd_sas_phy *sas_phy = &phy->sas_phy;
|
||||
|
||||
phy->mvi = mvi;
|
||||
phy->port = NULL;
|
||||
init_timer(&phy->timer);
|
||||
sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
|
||||
sas_phy->class = SAS;
|
||||
sas_phy->iproto = SAS_PROTOCOL_ALL;
|
||||
sas_phy->tproto = 0;
|
||||
sas_phy->type = PHY_TYPE_PHYSICAL;
|
||||
sas_phy->role = PHY_ROLE_INITIATOR;
|
||||
sas_phy->oob_mode = OOB_NOT_CONNECTED;
|
||||
sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
|
||||
|
||||
sas_phy->id = phy_id;
|
||||
sas_phy->sas_addr = &mvi->sas_addr[0];
|
||||
sas_phy->frame_rcvd = &phy->frame_rcvd[0];
|
||||
sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
|
||||
sas_phy->lldd_phy = phy;
|
||||
}
|
||||
|
||||
static void mvs_free(struct mvs_info *mvi)
|
||||
{
|
||||
struct mvs_wq *mwq;
|
||||
int slot_nr;
|
||||
|
||||
if (!mvi)
|
||||
return;
|
||||
|
||||
if (mvi->flags & MVF_FLAG_SOC)
|
||||
slot_nr = MVS_SOC_SLOTS;
|
||||
else
|
||||
slot_nr = MVS_CHIP_SLOT_SZ;
|
||||
|
||||
if (mvi->dma_pool)
|
||||
pci_pool_destroy(mvi->dma_pool);
|
||||
|
||||
if (mvi->tx)
|
||||
dma_free_coherent(mvi->dev,
|
||||
sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
|
||||
mvi->tx, mvi->tx_dma);
|
||||
if (mvi->rx_fis)
|
||||
dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
|
||||
mvi->rx_fis, mvi->rx_fis_dma);
|
||||
if (mvi->rx)
|
||||
dma_free_coherent(mvi->dev,
|
||||
sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
|
||||
mvi->rx, mvi->rx_dma);
|
||||
if (mvi->slot)
|
||||
dma_free_coherent(mvi->dev,
|
||||
sizeof(*mvi->slot) * slot_nr,
|
||||
mvi->slot, mvi->slot_dma);
|
||||
|
||||
if (mvi->bulk_buffer)
|
||||
dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
|
||||
mvi->bulk_buffer, mvi->bulk_buffer_dma);
|
||||
if (mvi->bulk_buffer1)
|
||||
dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
|
||||
mvi->bulk_buffer1, mvi->bulk_buffer_dma1);
|
||||
|
||||
MVS_CHIP_DISP->chip_iounmap(mvi);
|
||||
if (mvi->shost)
|
||||
scsi_host_put(mvi->shost);
|
||||
list_for_each_entry(mwq, &mvi->wq_list, entry)
|
||||
cancel_delayed_work(&mwq->work_q);
|
||||
kfree(mvi->tags);
|
||||
kfree(mvi);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SCSI_MVSAS_TASKLET
|
||||
static void mvs_tasklet(unsigned long opaque)
|
||||
{
|
||||
u32 stat;
|
||||
u16 core_nr, i = 0;
|
||||
|
||||
struct mvs_info *mvi;
|
||||
struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
|
||||
|
||||
core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
|
||||
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
|
||||
|
||||
if (unlikely(!mvi))
|
||||
BUG_ON(1);
|
||||
|
||||
stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq);
|
||||
if (!stat)
|
||||
goto out;
|
||||
|
||||
for (i = 0; i < core_nr; i++) {
|
||||
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
|
||||
MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat);
|
||||
}
|
||||
out:
|
||||
MVS_CHIP_DISP->interrupt_enable(mvi);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
static irqreturn_t mvs_interrupt(int irq, void *opaque)
|
||||
{
|
||||
u32 core_nr;
|
||||
u32 stat;
|
||||
struct mvs_info *mvi;
|
||||
struct sas_ha_struct *sha = opaque;
|
||||
#ifndef CONFIG_SCSI_MVSAS_TASKLET
|
||||
u32 i;
|
||||
#endif
|
||||
|
||||
core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
|
||||
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
|
||||
|
||||
if (unlikely(!mvi))
|
||||
return IRQ_NONE;
|
||||
#ifdef CONFIG_SCSI_MVSAS_TASKLET
|
||||
MVS_CHIP_DISP->interrupt_disable(mvi);
|
||||
#endif
|
||||
|
||||
stat = MVS_CHIP_DISP->isr_status(mvi, irq);
|
||||
if (!stat) {
|
||||
#ifdef CONFIG_SCSI_MVSAS_TASKLET
|
||||
MVS_CHIP_DISP->interrupt_enable(mvi);
|
||||
#endif
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SCSI_MVSAS_TASKLET
|
||||
tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
|
||||
#else
|
||||
for (i = 0; i < core_nr; i++) {
|
||||
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
|
||||
MVS_CHIP_DISP->isr(mvi, irq, stat);
|
||||
}
|
||||
#endif
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
|
||||
{
|
||||
int i = 0, slot_nr;
|
||||
char pool_name[32];
|
||||
|
||||
if (mvi->flags & MVF_FLAG_SOC)
|
||||
slot_nr = MVS_SOC_SLOTS;
|
||||
else
|
||||
slot_nr = MVS_CHIP_SLOT_SZ;
|
||||
|
||||
spin_lock_init(&mvi->lock);
|
||||
for (i = 0; i < mvi->chip->n_phy; i++) {
|
||||
mvs_phy_init(mvi, i);
|
||||
mvi->port[i].wide_port_phymap = 0;
|
||||
mvi->port[i].port_attached = 0;
|
||||
INIT_LIST_HEAD(&mvi->port[i].list);
|
||||
}
|
||||
for (i = 0; i < MVS_MAX_DEVICES; i++) {
|
||||
mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
|
||||
mvi->devices[i].dev_type = SAS_PHY_UNUSED;
|
||||
mvi->devices[i].device_id = i;
|
||||
mvi->devices[i].dev_status = MVS_DEV_NORMAL;
|
||||
init_timer(&mvi->devices[i].timer);
|
||||
}
|
||||
|
||||
/*
|
||||
* alloc and init our DMA areas
|
||||
*/
|
||||
mvi->tx = dma_alloc_coherent(mvi->dev,
|
||||
sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
|
||||
&mvi->tx_dma, GFP_KERNEL);
|
||||
if (!mvi->tx)
|
||||
goto err_out;
|
||||
memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
|
||||
mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
|
||||
&mvi->rx_fis_dma, GFP_KERNEL);
|
||||
if (!mvi->rx_fis)
|
||||
goto err_out;
|
||||
memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
|
||||
|
||||
mvi->rx = dma_alloc_coherent(mvi->dev,
|
||||
sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
|
||||
&mvi->rx_dma, GFP_KERNEL);
|
||||
if (!mvi->rx)
|
||||
goto err_out;
|
||||
memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1));
|
||||
mvi->rx[0] = cpu_to_le32(0xfff);
|
||||
mvi->rx_cons = 0xfff;
|
||||
|
||||
mvi->slot = dma_alloc_coherent(mvi->dev,
|
||||
sizeof(*mvi->slot) * slot_nr,
|
||||
&mvi->slot_dma, GFP_KERNEL);
|
||||
if (!mvi->slot)
|
||||
goto err_out;
|
||||
memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr);
|
||||
|
||||
mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
|
||||
TRASH_BUCKET_SIZE,
|
||||
&mvi->bulk_buffer_dma, GFP_KERNEL);
|
||||
if (!mvi->bulk_buffer)
|
||||
goto err_out;
|
||||
|
||||
mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev,
|
||||
TRASH_BUCKET_SIZE,
|
||||
&mvi->bulk_buffer_dma1, GFP_KERNEL);
|
||||
if (!mvi->bulk_buffer1)
|
||||
goto err_out;
|
||||
|
||||
sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);
|
||||
mvi->dma_pool = pci_pool_create(pool_name, mvi->pdev, MVS_SLOT_BUF_SZ, 16, 0);
|
||||
if (!mvi->dma_pool) {
|
||||
printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);
|
||||
goto err_out;
|
||||
}
|
||||
mvi->tags_num = slot_nr;
|
||||
|
||||
/* Initialize tags */
|
||||
mvs_tag_init(mvi);
|
||||
return 0;
|
||||
err_out:
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
|
||||
{
|
||||
unsigned long res_start, res_len, res_flag, res_flag_ex = 0;
|
||||
struct pci_dev *pdev = mvi->pdev;
|
||||
if (bar_ex != -1) {
|
||||
/*
|
||||
* ioremap main and peripheral registers
|
||||
*/
|
||||
res_start = pci_resource_start(pdev, bar_ex);
|
||||
res_len = pci_resource_len(pdev, bar_ex);
|
||||
if (!res_start || !res_len)
|
||||
goto err_out;
|
||||
|
||||
res_flag_ex = pci_resource_flags(pdev, bar_ex);
|
||||
if (res_flag_ex & IORESOURCE_MEM) {
|
||||
if (res_flag_ex & IORESOURCE_CACHEABLE)
|
||||
mvi->regs_ex = ioremap(res_start, res_len);
|
||||
else
|
||||
mvi->regs_ex = ioremap_nocache(res_start,
|
||||
res_len);
|
||||
} else
|
||||
mvi->regs_ex = (void *)res_start;
|
||||
if (!mvi->regs_ex)
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
res_start = pci_resource_start(pdev, bar);
|
||||
res_len = pci_resource_len(pdev, bar);
|
||||
if (!res_start || !res_len)
|
||||
goto err_out;
|
||||
|
||||
res_flag = pci_resource_flags(pdev, bar);
|
||||
if (res_flag & IORESOURCE_CACHEABLE)
|
||||
mvi->regs = ioremap(res_start, res_len);
|
||||
else
|
||||
mvi->regs = ioremap_nocache(res_start, res_len);
|
||||
|
||||
if (!mvi->regs) {
|
||||
if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
|
||||
iounmap(mvi->regs_ex);
|
||||
mvi->regs_ex = NULL;
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
return 0;
|
||||
err_out:
|
||||
return -1;
|
||||
}
|
||||
|
||||
void mvs_iounmap(void __iomem *regs)
|
||||
{
|
||||
iounmap(regs);
|
||||
}
|
||||
|
||||
static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev,
|
||||
const struct pci_device_id *ent,
|
||||
struct Scsi_Host *shost, unsigned int id)
|
||||
{
|
||||
struct mvs_info *mvi = NULL;
|
||||
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
|
||||
|
||||
mvi = kzalloc(sizeof(*mvi) +
|
||||
(1L << mvs_chips[ent->driver_data].slot_width) *
|
||||
sizeof(struct mvs_slot_info), GFP_KERNEL);
|
||||
if (!mvi)
|
||||
return NULL;
|
||||
|
||||
mvi->pdev = pdev;
|
||||
mvi->dev = &pdev->dev;
|
||||
mvi->chip_id = ent->driver_data;
|
||||
mvi->chip = &mvs_chips[mvi->chip_id];
|
||||
INIT_LIST_HEAD(&mvi->wq_list);
|
||||
|
||||
((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
|
||||
((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
|
||||
|
||||
mvi->id = id;
|
||||
mvi->sas = sha;
|
||||
mvi->shost = shost;
|
||||
|
||||
mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL);
|
||||
if (!mvi->tags)
|
||||
goto err_out;
|
||||
|
||||
if (MVS_CHIP_DISP->chip_ioremap(mvi))
|
||||
goto err_out;
|
||||
if (!mvs_alloc(mvi, shost))
|
||||
return mvi;
|
||||
err_out:
|
||||
mvs_free(mvi);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int pci_go_64(struct pci_dev *pdev)
|
||||
{
|
||||
int rc;
|
||||
|
||||
if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
|
||||
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
|
||||
if (rc) {
|
||||
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
|
||||
if (rc) {
|
||||
dev_printk(KERN_ERR, &pdev->dev,
|
||||
"64-bit DMA enable failed\n");
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
|
||||
if (rc) {
|
||||
dev_printk(KERN_ERR, &pdev->dev,
|
||||
"32-bit DMA enable failed\n");
|
||||
return rc;
|
||||
}
|
||||
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
|
||||
if (rc) {
|
||||
dev_printk(KERN_ERR, &pdev->dev,
|
||||
"32-bit consistent DMA enable failed\n");
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int mvs_prep_sas_ha_init(struct Scsi_Host *shost,
|
||||
const struct mvs_chip_info *chip_info)
|
||||
{
|
||||
int phy_nr, port_nr; unsigned short core_nr;
|
||||
struct asd_sas_phy **arr_phy;
|
||||
struct asd_sas_port **arr_port;
|
||||
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
|
||||
|
||||
core_nr = chip_info->n_host;
|
||||
phy_nr = core_nr * chip_info->n_phy;
|
||||
port_nr = phy_nr;
|
||||
|
||||
memset(sha, 0x00, sizeof(struct sas_ha_struct));
|
||||
arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
|
||||
arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
|
||||
if (!arr_phy || !arr_port)
|
||||
goto exit_free;
|
||||
|
||||
sha->sas_phy = arr_phy;
|
||||
sha->sas_port = arr_port;
|
||||
sha->core.shost = shost;
|
||||
|
||||
sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
|
||||
if (!sha->lldd_ha)
|
||||
goto exit_free;
|
||||
|
||||
((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
|
||||
|
||||
shost->transportt = mvs_stt;
|
||||
shost->max_id = MVS_MAX_DEVICES;
|
||||
shost->max_lun = ~0;
|
||||
shost->max_channel = 1;
|
||||
shost->max_cmd_len = 16;
|
||||
|
||||
return 0;
|
||||
exit_free:
|
||||
kfree(arr_phy);
|
||||
kfree(arr_port);
|
||||
return -1;
|
||||
|
||||
}
|
||||
|
||||
static void mvs_post_sas_ha_init(struct Scsi_Host *shost,
|
||||
const struct mvs_chip_info *chip_info)
|
||||
{
|
||||
int can_queue, i = 0, j = 0;
|
||||
struct mvs_info *mvi = NULL;
|
||||
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
|
||||
unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
|
||||
|
||||
for (j = 0; j < nr_core; j++) {
|
||||
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
|
||||
for (i = 0; i < chip_info->n_phy; i++) {
|
||||
sha->sas_phy[j * chip_info->n_phy + i] =
|
||||
&mvi->phy[i].sas_phy;
|
||||
sha->sas_port[j * chip_info->n_phy + i] =
|
||||
&mvi->port[i].sas_port;
|
||||
}
|
||||
}
|
||||
|
||||
sha->sas_ha_name = DRV_NAME;
|
||||
sha->dev = mvi->dev;
|
||||
sha->lldd_module = THIS_MODULE;
|
||||
sha->sas_addr = &mvi->sas_addr[0];
|
||||
|
||||
sha->num_phys = nr_core * chip_info->n_phy;
|
||||
|
||||
sha->lldd_max_execute_num = lldd_max_execute_num;
|
||||
|
||||
if (mvi->flags & MVF_FLAG_SOC)
|
||||
can_queue = MVS_SOC_CAN_QUEUE;
|
||||
else
|
||||
can_queue = MVS_CHIP_SLOT_SZ;
|
||||
|
||||
sha->lldd_queue_size = can_queue;
|
||||
shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);
|
||||
shost->can_queue = can_queue;
|
||||
mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;
|
||||
sha->core.shost = mvi->shost;
|
||||
}
|
||||
|
||||
static void mvs_init_sas_add(struct mvs_info *mvi)
|
||||
{
|
||||
u8 i;
|
||||
for (i = 0; i < mvi->chip->n_phy; i++) {
|
||||
mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
|
||||
mvi->phy[i].dev_sas_addr =
|
||||
cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
|
||||
}
|
||||
|
||||
memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
|
||||
}
|
||||
|
||||
static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
unsigned int rc, nhost = 0;
|
||||
struct mvs_info *mvi;
|
||||
struct mvs_prv_info *mpi;
|
||||
irq_handler_t irq_handler = mvs_interrupt;
|
||||
struct Scsi_Host *shost = NULL;
|
||||
const struct mvs_chip_info *chip;
|
||||
|
||||
dev_printk(KERN_INFO, &pdev->dev,
|
||||
"mvsas: driver version %s\n", DRV_VERSION);
|
||||
rc = pci_enable_device(pdev);
|
||||
if (rc)
|
||||
goto err_out_enable;
|
||||
|
||||
pci_set_master(pdev);
|
||||
|
||||
rc = pci_request_regions(pdev, DRV_NAME);
|
||||
if (rc)
|
||||
goto err_out_disable;
|
||||
|
||||
rc = pci_go_64(pdev);
|
||||
if (rc)
|
||||
goto err_out_regions;
|
||||
|
||||
shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
|
||||
if (!shost) {
|
||||
rc = -ENOMEM;
|
||||
goto err_out_regions;
|
||||
}
|
||||
|
||||
chip = &mvs_chips[ent->driver_data];
|
||||
SHOST_TO_SAS_HA(shost) =
|
||||
kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
|
||||
if (!SHOST_TO_SAS_HA(shost)) {
|
||||
kfree(shost);
|
||||
rc = -ENOMEM;
|
||||
goto err_out_regions;
|
||||
}
|
||||
|
||||
rc = mvs_prep_sas_ha_init(shost, chip);
|
||||
if (rc) {
|
||||
kfree(shost);
|
||||
rc = -ENOMEM;
|
||||
goto err_out_regions;
|
||||
}
|
||||
|
||||
pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
|
||||
|
||||
do {
|
||||
mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
|
||||
if (!mvi) {
|
||||
rc = -ENOMEM;
|
||||
goto err_out_regions;
|
||||
}
|
||||
|
||||
memset(&mvi->hba_info_param, 0xFF,
|
||||
sizeof(struct hba_info_page));
|
||||
|
||||
mvs_init_sas_add(mvi);
|
||||
|
||||
mvi->instance = nhost;
|
||||
rc = MVS_CHIP_DISP->chip_init(mvi);
|
||||
if (rc) {
|
||||
mvs_free(mvi);
|
||||
goto err_out_regions;
|
||||
}
|
||||
nhost++;
|
||||
} while (nhost < chip->n_host);
|
||||
mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha);
|
||||
#ifdef CONFIG_SCSI_MVSAS_TASKLET
|
||||
tasklet_init(&(mpi->mv_tasklet), mvs_tasklet,
|
||||
(unsigned long)SHOST_TO_SAS_HA(shost));
|
||||
#endif
|
||||
|
||||
mvs_post_sas_ha_init(shost, chip);
|
||||
|
||||
rc = scsi_add_host(shost, &pdev->dev);
|
||||
if (rc)
|
||||
goto err_out_shost;
|
||||
|
||||
rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
|
||||
if (rc)
|
||||
goto err_out_shost;
|
||||
rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
|
||||
DRV_NAME, SHOST_TO_SAS_HA(shost));
|
||||
if (rc)
|
||||
goto err_not_sas;
|
||||
|
||||
MVS_CHIP_DISP->interrupt_enable(mvi);
|
||||
|
||||
scsi_scan_host(mvi->shost);
|
||||
|
||||
return 0;
|
||||
|
||||
err_not_sas:
|
||||
sas_unregister_ha(SHOST_TO_SAS_HA(shost));
|
||||
err_out_shost:
|
||||
scsi_remove_host(mvi->shost);
|
||||
err_out_regions:
|
||||
pci_release_regions(pdev);
|
||||
err_out_disable:
|
||||
pci_disable_device(pdev);
|
||||
err_out_enable:
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void mvs_pci_remove(struct pci_dev *pdev)
|
||||
{
|
||||
unsigned short core_nr, i = 0;
|
||||
struct sas_ha_struct *sha = pci_get_drvdata(pdev);
|
||||
struct mvs_info *mvi = NULL;
|
||||
|
||||
core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
|
||||
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
|
||||
|
||||
#ifdef CONFIG_SCSI_MVSAS_TASKLET
|
||||
tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
|
||||
#endif
|
||||
|
||||
sas_unregister_ha(sha);
|
||||
sas_remove_host(mvi->shost);
|
||||
scsi_remove_host(mvi->shost);
|
||||
|
||||
MVS_CHIP_DISP->interrupt_disable(mvi);
|
||||
free_irq(mvi->pdev->irq, sha);
|
||||
for (i = 0; i < core_nr; i++) {
|
||||
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
|
||||
mvs_free(mvi);
|
||||
}
|
||||
kfree(sha->sas_phy);
|
||||
kfree(sha->sas_port);
|
||||
kfree(sha);
|
||||
pci_release_regions(pdev);
|
||||
pci_disable_device(pdev);
|
||||
return;
|
||||
}
|
||||
|
||||
static struct pci_device_id mvs_pci_table[] = {
|
||||
{ PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
|
||||
{ PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_MARVELL,
|
||||
.device = 0x6440,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = 0x6480,
|
||||
.class = 0,
|
||||
.class_mask = 0,
|
||||
.driver_data = chip_6485,
|
||||
},
|
||||
{ PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
|
||||
{ PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
|
||||
{ PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
|
||||
{ PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
|
||||
{ PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },
|
||||
{ PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },
|
||||
{ PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },
|
||||
{ PCI_VDEVICE(TTI, 0x2710), chip_9480 },
|
||||
{ PCI_VDEVICE(TTI, 0x2720), chip_9480 },
|
||||
{ PCI_VDEVICE(TTI, 0x2721), chip_9480 },
|
||||
{ PCI_VDEVICE(TTI, 0x2722), chip_9480 },
|
||||
{ PCI_VDEVICE(TTI, 0x2740), chip_9480 },
|
||||
{ PCI_VDEVICE(TTI, 0x2744), chip_9480 },
|
||||
{ PCI_VDEVICE(TTI, 0x2760), chip_9480 },
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_MARVELL_EXT,
|
||||
.device = 0x9480,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = 0x9480,
|
||||
.class = 0,
|
||||
.class_mask = 0,
|
||||
.driver_data = chip_9480,
|
||||
},
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_MARVELL_EXT,
|
||||
.device = 0x9445,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = 0x9480,
|
||||
.class = 0,
|
||||
.class_mask = 0,
|
||||
.driver_data = chip_9445,
|
||||
},
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_MARVELL_EXT,
|
||||
.device = 0x9485,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = 0x9480,
|
||||
.class = 0,
|
||||
.class_mask = 0,
|
||||
.driver_data = chip_9485,
|
||||
},
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_MARVELL_EXT,
|
||||
.device = 0x9485,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = 0x9485,
|
||||
.class = 0,
|
||||
.class_mask = 0,
|
||||
.driver_data = chip_9485,
|
||||
},
|
||||
{ PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */
|
||||
{ PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
||||
{ PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
||||
{ PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
||||
{ PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
||||
{ PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
||||
{ PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
||||
{ PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
||||
{ PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
||||
{ PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
||||
|
||||
{ } /* terminate list */
|
||||
};
|
||||
|
||||
static struct pci_driver mvs_pci_driver = {
|
||||
.name = DRV_NAME,
|
||||
.id_table = mvs_pci_table,
|
||||
.probe = mvs_pci_init,
|
||||
.remove = mvs_pci_remove,
|
||||
};
|
||||
|
||||
static ssize_t
|
||||
mvs_show_driver_version(struct device *cdev,
|
||||
struct device_attribute *attr, char *buffer)
|
||||
{
|
||||
return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION);
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(driver_version,
|
||||
S_IRUGO,
|
||||
mvs_show_driver_version,
|
||||
NULL);
|
||||
|
||||
static ssize_t
|
||||
mvs_store_interrupt_coalescing(struct device *cdev,
|
||||
struct device_attribute *attr,
|
||||
const char *buffer, size_t size)
|
||||
{
|
||||
int val = 0;
|
||||
struct mvs_info *mvi = NULL;
|
||||
struct Scsi_Host *shost = class_to_shost(cdev);
|
||||
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
|
||||
u8 i, core_nr;
|
||||
if (buffer == NULL)
|
||||
return size;
|
||||
|
||||
if (sscanf(buffer, "%d", &val) != 1)
|
||||
return -EINVAL;
|
||||
|
||||
if (val >= 0x10000) {
|
||||
mv_dprintk("interrupt coalescing timer %d us is"
|
||||
"too long\n", val);
|
||||
return strlen(buffer);
|
||||
}
|
||||
|
||||
interrupt_coalescing = val;
|
||||
|
||||
core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
|
||||
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
|
||||
|
||||
if (unlikely(!mvi))
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < core_nr; i++) {
|
||||
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
|
||||
if (MVS_CHIP_DISP->tune_interrupt)
|
||||
MVS_CHIP_DISP->tune_interrupt(mvi,
|
||||
interrupt_coalescing);
|
||||
}
|
||||
mv_dprintk("set interrupt coalescing time to %d us\n",
|
||||
interrupt_coalescing);
|
||||
return strlen(buffer);
|
||||
}
|
||||
|
||||
static ssize_t mvs_show_interrupt_coalescing(struct device *cdev,
|
||||
struct device_attribute *attr, char *buffer)
|
||||
{
|
||||
return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing);
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(interrupt_coalescing,
|
||||
S_IRUGO|S_IWUSR,
|
||||
mvs_show_interrupt_coalescing,
|
||||
mvs_store_interrupt_coalescing);
|
||||
|
||||
/* task handler */
|
||||
struct task_struct *mvs_th;
|
||||
static int __init mvs_init(void)
|
||||
{
|
||||
int rc;
|
||||
mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
|
||||
if (!mvs_stt)
|
||||
return -ENOMEM;
|
||||
|
||||
mvs_task_list_cache = kmem_cache_create("mvs_task_list", sizeof(struct mvs_task_list),
|
||||
0, SLAB_HWCACHE_ALIGN, NULL);
|
||||
if (!mvs_task_list_cache) {
|
||||
rc = -ENOMEM;
|
||||
mv_printk("%s: mvs_task_list_cache alloc failed! \n", __func__);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
rc = pci_register_driver(&mvs_pci_driver);
|
||||
|
||||
if (rc)
|
||||
goto err_out;
|
||||
|
||||
return 0;
|
||||
|
||||
err_out:
|
||||
sas_release_transport(mvs_stt);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void __exit mvs_exit(void)
|
||||
{
|
||||
pci_unregister_driver(&mvs_pci_driver);
|
||||
sas_release_transport(mvs_stt);
|
||||
kmem_cache_destroy(mvs_task_list_cache);
|
||||
}
|
||||
|
||||
struct device_attribute *mvst_host_attrs[] = {
|
||||
&dev_attr_driver_version,
|
||||
&dev_attr_interrupt_coalescing,
|
||||
NULL,
|
||||
};
|
||||
|
||||
module_init(mvs_init);
|
||||
module_exit(mvs_exit);
|
||||
|
||||
MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
|
||||
MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
|
||||
MODULE_VERSION(DRV_VERSION);
|
||||
MODULE_LICENSE("GPL");
|
||||
#ifdef CONFIG_PCI
|
||||
MODULE_DEVICE_TABLE(pci, mvs_pci_table);
|
||||
#endif
|
||||
2206
drivers/scsi/mvsas/mv_sas.c
Normal file
2206
drivers/scsi/mvsas/mv_sas.c
Normal file
File diff suppressed because it is too large
Load diff
488
drivers/scsi/mvsas/mv_sas.h
Normal file
488
drivers/scsi/mvsas/mv_sas.h
Normal file
|
|
@ -0,0 +1,488 @@
|
|||
/*
|
||||
* Marvell 88SE64xx/88SE94xx main function head file
|
||||
*
|
||||
* Copyright 2007 Red Hat, Inc.
|
||||
* Copyright 2008 Marvell. <kewei@marvell.com>
|
||||
* Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
|
||||
*
|
||||
* This file is licensed under GPLv2.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the
|
||||
* License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
#ifndef _MV_SAS_H_
|
||||
#define _MV_SAS_H_
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <asm/unaligned.h>
|
||||
#include <scsi/libsas.h>
|
||||
#include <scsi/scsi.h>
|
||||
#include <scsi/scsi_tcq.h>
|
||||
#include <scsi/sas_ata.h>
|
||||
#include "mv_defs.h"
|
||||
|
||||
#define DRV_NAME "mvsas"
|
||||
#define DRV_VERSION "0.8.16"
|
||||
#define MVS_ID_NOT_MAPPED 0x7f
|
||||
#define WIDE_PORT_MAX_PHY 4
|
||||
#define mv_printk(fmt, arg ...) \
|
||||
printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg)
|
||||
#ifdef MV_DEBUG
|
||||
#define mv_dprintk(format, arg...) \
|
||||
printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg)
|
||||
#else
|
||||
#define mv_dprintk(format, arg...)
|
||||
#endif
|
||||
#define MV_MAX_U32 0xffffffff
|
||||
|
||||
extern int interrupt_coalescing;
|
||||
extern struct mvs_tgt_initiator mvs_tgt;
|
||||
extern struct mvs_info *tgt_mvi;
|
||||
extern const struct mvs_dispatch mvs_64xx_dispatch;
|
||||
extern const struct mvs_dispatch mvs_94xx_dispatch;
|
||||
extern struct kmem_cache *mvs_task_list_cache;
|
||||
|
||||
#define DEV_IS_EXPANDER(type) \
|
||||
((type == SAS_EDGE_EXPANDER_DEVICE) || (type == SAS_FANOUT_EXPANDER_DEVICE))
|
||||
|
||||
#define bit(n) ((u64)1 << n)
|
||||
|
||||
#define for_each_phy(__lseq_mask, __mc, __lseq) \
|
||||
for ((__mc) = (__lseq_mask), (__lseq) = 0; \
|
||||
(__mc) != 0 ; \
|
||||
(++__lseq), (__mc) >>= 1)
|
||||
|
||||
#define MVS_PHY_ID (1U << sas_phy->id)
|
||||
#define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f)
|
||||
#define UNASSOC_D2H_FIS(id) \
|
||||
((void *) mvi->rx_fis + 0x100 * id)
|
||||
#define SATA_RECEIVED_FIS_LIST(reg_set) \
|
||||
((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
|
||||
#define SATA_RECEIVED_SDB_FIS(reg_set) \
|
||||
(SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
|
||||
#define SATA_RECEIVED_D2H_FIS(reg_set) \
|
||||
(SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
|
||||
#define SATA_RECEIVED_PIO_FIS(reg_set) \
|
||||
(SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
|
||||
#define SATA_RECEIVED_DMA_FIS(reg_set) \
|
||||
(SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)
|
||||
|
||||
enum dev_status {
|
||||
MVS_DEV_NORMAL = 0x0,
|
||||
MVS_DEV_EH = 0x1,
|
||||
};
|
||||
|
||||
enum dev_reset {
|
||||
MVS_SOFT_RESET = 0,
|
||||
MVS_HARD_RESET = 1,
|
||||
MVS_PHY_TUNE = 2,
|
||||
};
|
||||
|
||||
struct mvs_info;
|
||||
|
||||
struct mvs_dispatch {
|
||||
char *name;
|
||||
int (*chip_init)(struct mvs_info *mvi);
|
||||
int (*spi_init)(struct mvs_info *mvi);
|
||||
int (*chip_ioremap)(struct mvs_info *mvi);
|
||||
void (*chip_iounmap)(struct mvs_info *mvi);
|
||||
irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat);
|
||||
u32 (*isr_status)(struct mvs_info *mvi, int irq);
|
||||
void (*interrupt_enable)(struct mvs_info *mvi);
|
||||
void (*interrupt_disable)(struct mvs_info *mvi);
|
||||
|
||||
u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port);
|
||||
void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val);
|
||||
|
||||
u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port);
|
||||
void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val);
|
||||
void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr);
|
||||
|
||||
u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port);
|
||||
void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val);
|
||||
void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr);
|
||||
|
||||
u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port);
|
||||
void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val);
|
||||
|
||||
u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port);
|
||||
void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val);
|
||||
|
||||
void (*command_active)(struct mvs_info *mvi, u32 slot_idx);
|
||||
void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all);
|
||||
void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type,
|
||||
u32 tfs);
|
||||
void (*start_delivery)(struct mvs_info *mvi, u32 tx);
|
||||
u32 (*rx_update)(struct mvs_info *mvi);
|
||||
void (*int_full)(struct mvs_info *mvi);
|
||||
u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs);
|
||||
void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs);
|
||||
u32 (*prd_size)(void);
|
||||
u32 (*prd_count)(void);
|
||||
void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
|
||||
void (*detect_porttype)(struct mvs_info *mvi, int i);
|
||||
int (*oob_done)(struct mvs_info *mvi, int i);
|
||||
void (*fix_phy_info)(struct mvs_info *mvi, int i,
|
||||
struct sas_identify_frame *id);
|
||||
void (*phy_work_around)(struct mvs_info *mvi, int i);
|
||||
void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id,
|
||||
struct sas_phy_linkrates *rates);
|
||||
u32 (*phy_max_link_rate)(void);
|
||||
void (*phy_disable)(struct mvs_info *mvi, u32 phy_id);
|
||||
void (*phy_enable)(struct mvs_info *mvi, u32 phy_id);
|
||||
void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard);
|
||||
void (*stp_reset)(struct mvs_info *mvi, u32 phy_id);
|
||||
void (*clear_active_cmds)(struct mvs_info *mvi);
|
||||
u32 (*spi_read_data)(struct mvs_info *mvi);
|
||||
void (*spi_write_data)(struct mvs_info *mvi, u32 data);
|
||||
int (*spi_buildcmd)(struct mvs_info *mvi,
|
||||
u32 *dwCmd,
|
||||
u8 cmd,
|
||||
u8 read,
|
||||
u8 length,
|
||||
u32 addr
|
||||
);
|
||||
int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd);
|
||||
int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout);
|
||||
void (*dma_fix)(struct mvs_info *mvi, u32 phy_mask,
|
||||
int buf_len, int from, void *prd);
|
||||
void (*tune_interrupt)(struct mvs_info *mvi, u32 time);
|
||||
void (*non_spec_ncq_error)(struct mvs_info *mvi);
|
||||
|
||||
};
|
||||
|
||||
struct mvs_chip_info {
|
||||
u32 n_host;
|
||||
u32 n_phy;
|
||||
u32 fis_offs;
|
||||
u32 fis_count;
|
||||
u32 srs_sz;
|
||||
u32 sg_width;
|
||||
u32 slot_width;
|
||||
const struct mvs_dispatch *dispatch;
|
||||
};
|
||||
#define MVS_MAX_SG (1U << mvi->chip->sg_width)
|
||||
#define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
|
||||
#define MVS_RX_FISL_SZ \
|
||||
(mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100))
|
||||
#define MVS_CHIP_DISP (mvi->chip->dispatch)
|
||||
|
||||
struct mvs_err_info {
|
||||
__le32 flags;
|
||||
__le32 flags2;
|
||||
};
|
||||
|
||||
struct mvs_cmd_hdr {
|
||||
__le32 flags; /* PRD tbl len; SAS, SATA ctl */
|
||||
__le32 lens; /* cmd, max resp frame len */
|
||||
__le32 tags; /* targ port xfer tag; tag */
|
||||
__le32 data_len; /* data xfer len */
|
||||
__le64 cmd_tbl; /* command table address */
|
||||
__le64 open_frame; /* open addr frame address */
|
||||
__le64 status_buf; /* status buffer address */
|
||||
__le64 prd_tbl; /* PRD tbl address */
|
||||
__le32 reserved[4];
|
||||
};
|
||||
|
||||
struct mvs_port {
|
||||
struct asd_sas_port sas_port;
|
||||
u8 port_attached;
|
||||
u8 wide_port_phymap;
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
struct mvs_phy {
|
||||
struct mvs_info *mvi;
|
||||
struct mvs_port *port;
|
||||
struct asd_sas_phy sas_phy;
|
||||
struct sas_identify identify;
|
||||
struct scsi_device *sdev;
|
||||
struct timer_list timer;
|
||||
u64 dev_sas_addr;
|
||||
u64 att_dev_sas_addr;
|
||||
u32 att_dev_info;
|
||||
u32 dev_info;
|
||||
u32 phy_type;
|
||||
u32 phy_status;
|
||||
u32 irq_status;
|
||||
u32 frame_rcvd_size;
|
||||
u8 frame_rcvd[32];
|
||||
u8 phy_attached;
|
||||
u8 phy_mode;
|
||||
u8 reserved[2];
|
||||
u32 phy_event;
|
||||
enum sas_linkrate minimum_linkrate;
|
||||
enum sas_linkrate maximum_linkrate;
|
||||
};
|
||||
|
||||
struct mvs_device {
|
||||
struct list_head dev_entry;
|
||||
enum sas_device_type dev_type;
|
||||
struct mvs_info *mvi_info;
|
||||
struct domain_device *sas_device;
|
||||
struct timer_list timer;
|
||||
u32 attached_phy;
|
||||
u32 device_id;
|
||||
u32 running_req;
|
||||
u8 taskfileset;
|
||||
u8 dev_status;
|
||||
u16 reserved;
|
||||
};
|
||||
|
||||
/* Generate PHY tunning parameters */
|
||||
struct phy_tuning {
|
||||
/* 1 bit, transmitter emphasis enable */
|
||||
u8 trans_emp_en:1;
|
||||
/* 4 bits, transmitter emphasis amplitude */
|
||||
u8 trans_emp_amp:4;
|
||||
/* 3 bits, reserved space */
|
||||
u8 Reserved_2bit_1:3;
|
||||
/* 5 bits, transmitter amplitude */
|
||||
u8 trans_amp:5;
|
||||
/* 2 bits, transmitter amplitude adjust */
|
||||
u8 trans_amp_adj:2;
|
||||
/* 1 bit, reserved space */
|
||||
u8 resv_2bit_2:1;
|
||||
/* 2 bytes, reserved space */
|
||||
u8 reserved[2];
|
||||
};
|
||||
|
||||
struct ffe_control {
|
||||
/* 4 bits, FFE Capacitor Select (value range 0~F) */
|
||||
u8 ffe_cap_sel:4;
|
||||
/* 3 bits, FFE Resistor Select (value range 0~7) */
|
||||
u8 ffe_rss_sel:3;
|
||||
/* 1 bit reserve*/
|
||||
u8 reserved:1;
|
||||
};
|
||||
|
||||
/*
|
||||
* HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes.
|
||||
* The data area is valid only Signature="MRVL".
|
||||
* If any member fills with 0xFF, the member is invalid.
|
||||
*/
|
||||
struct hba_info_page {
|
||||
/* Dword 0 */
|
||||
/* 4 bytes, structure signature,should be "MRVL" at first initial */
|
||||
u8 signature[4];
|
||||
|
||||
/* Dword 1-13 */
|
||||
u32 reserved1[13];
|
||||
|
||||
/* Dword 14-29 */
|
||||
/* 64 bytes, SAS address for each port */
|
||||
u64 sas_addr[8];
|
||||
|
||||
/* Dword 30-31 */
|
||||
/* 8 bytes for vanir 8 port PHY FFE seeting
|
||||
* BIT 0~3 : FFE Capacitor select(value range 0~F)
|
||||
* BIT 4~6 : FFE Resistor select(value range 0~7)
|
||||
* BIT 7: reserve.
|
||||
*/
|
||||
|
||||
struct ffe_control ffe_ctl[8];
|
||||
/* Dword 32 -43 */
|
||||
u32 reserved2[12];
|
||||
|
||||
/* Dword 44-45 */
|
||||
/* 8 bytes, 0: 1.5G, 1: 3.0G, should be 0x01 at first initial */
|
||||
u8 phy_rate[8];
|
||||
|
||||
/* Dword 46-53 */
|
||||
/* 32 bytes, PHY tuning parameters for each PHY*/
|
||||
struct phy_tuning phy_tuning[8];
|
||||
|
||||
/* Dword 54-63 */
|
||||
u32 reserved3[10];
|
||||
}; /* total 256 bytes */
|
||||
|
||||
struct mvs_slot_info {
|
||||
struct list_head entry;
|
||||
union {
|
||||
struct sas_task *task;
|
||||
void *tdata;
|
||||
};
|
||||
u32 n_elem;
|
||||
u32 tx;
|
||||
u32 slot_tag;
|
||||
|
||||
/* DMA buffer for storing cmd tbl, open addr frame, status buffer,
|
||||
* and PRD table
|
||||
*/
|
||||
void *buf;
|
||||
dma_addr_t buf_dma;
|
||||
void *response;
|
||||
struct mvs_port *port;
|
||||
struct mvs_device *device;
|
||||
void *open_frame;
|
||||
};
|
||||
|
||||
struct mvs_info {
|
||||
unsigned long flags;
|
||||
|
||||
/* host-wide lock */
|
||||
spinlock_t lock;
|
||||
|
||||
/* our device */
|
||||
struct pci_dev *pdev;
|
||||
struct device *dev;
|
||||
|
||||
/* enhanced mode registers */
|
||||
void __iomem *regs;
|
||||
|
||||
/* peripheral or soc registers */
|
||||
void __iomem *regs_ex;
|
||||
u8 sas_addr[SAS_ADDR_SIZE];
|
||||
|
||||
/* SCSI/SAS glue */
|
||||
struct sas_ha_struct *sas;
|
||||
struct Scsi_Host *shost;
|
||||
|
||||
/* TX (delivery) DMA ring */
|
||||
__le32 *tx;
|
||||
dma_addr_t tx_dma;
|
||||
|
||||
/* cached next-producer idx */
|
||||
u32 tx_prod;
|
||||
|
||||
/* RX (completion) DMA ring */
|
||||
__le32 *rx;
|
||||
dma_addr_t rx_dma;
|
||||
|
||||
/* RX consumer idx */
|
||||
u32 rx_cons;
|
||||
|
||||
/* RX'd FIS area */
|
||||
__le32 *rx_fis;
|
||||
dma_addr_t rx_fis_dma;
|
||||
|
||||
/* DMA command header slots */
|
||||
struct mvs_cmd_hdr *slot;
|
||||
dma_addr_t slot_dma;
|
||||
|
||||
u32 chip_id;
|
||||
const struct mvs_chip_info *chip;
|
||||
|
||||
int tags_num;
|
||||
unsigned long *tags;
|
||||
/* further per-slot information */
|
||||
struct mvs_phy phy[MVS_MAX_PHYS];
|
||||
struct mvs_port port[MVS_MAX_PHYS];
|
||||
u32 id;
|
||||
u64 sata_reg_set;
|
||||
struct list_head *hba_list;
|
||||
struct list_head soc_entry;
|
||||
struct list_head wq_list;
|
||||
unsigned long instance;
|
||||
u16 flashid;
|
||||
u32 flashsize;
|
||||
u32 flashsectSize;
|
||||
|
||||
void *addon;
|
||||
struct hba_info_page hba_info_param;
|
||||
struct mvs_device devices[MVS_MAX_DEVICES];
|
||||
void *bulk_buffer;
|
||||
dma_addr_t bulk_buffer_dma;
|
||||
void *bulk_buffer1;
|
||||
dma_addr_t bulk_buffer_dma1;
|
||||
#define TRASH_BUCKET_SIZE 0x20000
|
||||
void *dma_pool;
|
||||
struct mvs_slot_info slot_info[0];
|
||||
};
|
||||
|
||||
struct mvs_prv_info{
|
||||
u8 n_host;
|
||||
u8 n_phy;
|
||||
u8 scan_finished;
|
||||
u8 reserve;
|
||||
struct mvs_info *mvi[2];
|
||||
struct tasklet_struct mv_tasklet;
|
||||
};
|
||||
|
||||
struct mvs_wq {
|
||||
struct delayed_work work_q;
|
||||
struct mvs_info *mvi;
|
||||
void *data;
|
||||
int handler;
|
||||
struct list_head entry;
|
||||
};
|
||||
|
||||
struct mvs_task_exec_info {
|
||||
struct sas_task *task;
|
||||
struct mvs_cmd_hdr *hdr;
|
||||
struct mvs_port *port;
|
||||
u32 tag;
|
||||
int n_elem;
|
||||
};
|
||||
|
||||
struct mvs_task_list {
|
||||
struct sas_task *task;
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
|
||||
/******************** function prototype *********************/
|
||||
void mvs_get_sas_addr(void *buf, u32 buflen);
|
||||
void mvs_tag_clear(struct mvs_info *mvi, u32 tag);
|
||||
void mvs_tag_free(struct mvs_info *mvi, u32 tag);
|
||||
void mvs_tag_set(struct mvs_info *mvi, unsigned int tag);
|
||||
int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out);
|
||||
void mvs_tag_init(struct mvs_info *mvi);
|
||||
void mvs_iounmap(void __iomem *regs);
|
||||
int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex);
|
||||
void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard);
|
||||
int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
|
||||
void *funcdata);
|
||||
void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
|
||||
u32 off_hi, u64 sas_addr);
|
||||
void mvs_scan_start(struct Scsi_Host *shost);
|
||||
int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
|
||||
int mvs_queue_command(struct sas_task *task, const int num,
|
||||
gfp_t gfp_flags);
|
||||
int mvs_abort_task(struct sas_task *task);
|
||||
int mvs_abort_task_set(struct domain_device *dev, u8 *lun);
|
||||
int mvs_clear_aca(struct domain_device *dev, u8 *lun);
|
||||
int mvs_clear_task_set(struct domain_device *dev, u8 * lun);
|
||||
void mvs_port_formed(struct asd_sas_phy *sas_phy);
|
||||
void mvs_port_deformed(struct asd_sas_phy *sas_phy);
|
||||
int mvs_dev_found(struct domain_device *dev);
|
||||
void mvs_dev_gone(struct domain_device *dev);
|
||||
int mvs_lu_reset(struct domain_device *dev, u8 *lun);
|
||||
int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags);
|
||||
int mvs_I_T_nexus_reset(struct domain_device *dev);
|
||||
int mvs_query_task(struct sas_task *task);
|
||||
void mvs_release_task(struct mvs_info *mvi,
|
||||
struct domain_device *dev);
|
||||
void mvs_do_release_task(struct mvs_info *mvi, int phy_no,
|
||||
struct domain_device *dev);
|
||||
void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events);
|
||||
void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
|
||||
int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
|
||||
struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set);
|
||||
#endif
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue