mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
38
drivers/scsi/qla2xxx/Kconfig
Normal file
38
drivers/scsi/qla2xxx/Kconfig
Normal file
|
|
@ -0,0 +1,38 @@
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config SCSI_QLA_FC
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tristate "QLogic QLA2XXX Fibre Channel Support"
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depends on PCI && SCSI
|
||||
depends on SCSI_FC_ATTRS
|
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select FW_LOADER
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---help---
|
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This qla2xxx driver supports all QLogic Fibre Channel
|
||||
PCI and PCIe host adapters.
|
||||
|
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By default, firmware for the ISP parts will be loaded
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via the Firmware Loader interface.
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|
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ISP Firmware Filename
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---------- -----------------
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21xx ql2100_fw.bin
|
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22xx ql2200_fw.bin
|
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2300, 2312, 6312 ql2300_fw.bin
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2322, 6322 ql2322_fw.bin
|
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24xx, 54xx ql2400_fw.bin
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25xx ql2500_fw.bin
|
||||
|
||||
Upon request, the driver caches the firmware image until
|
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the driver is unloaded.
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|
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Firmware images can be retrieved from:
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http://ldriver.qlogic.com/firmware/
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They are also included in the linux-firmware tree as well.
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|
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config TCM_QLA2XXX
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tristate "TCM_QLA2XXX fabric module for Qlogic 2xxx series target mode HBAs"
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depends on SCSI_QLA_FC && TARGET_CORE
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depends on LIBFC
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select BTREE
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default n
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---help---
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Say Y here to enable the TCM_QLA2XXX fabric module for Qlogic 2xxx series target mode HBAs
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6
drivers/scsi/qla2xxx/Makefile
Normal file
6
drivers/scsi/qla2xxx/Makefile
Normal file
|
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@ -0,0 +1,6 @@
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qla2xxx-y := qla_os.o qla_init.o qla_mbx.o qla_iocb.o qla_isr.o qla_gs.o \
|
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qla_dbg.o qla_sup.o qla_attr.o qla_mid.o qla_dfs.o qla_bsg.o \
|
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qla_nx.o qla_mr.o qla_nx2.o qla_target.o qla_tmpl.o
|
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|
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obj-$(CONFIG_SCSI_QLA_FC) += qla2xxx.o
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obj-$(CONFIG_TCM_QLA2XXX) += tcm_qla2xxx.o
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2323
drivers/scsi/qla2xxx/qla_attr.c
Normal file
2323
drivers/scsi/qla2xxx/qla_attr.c
Normal file
File diff suppressed because it is too large
Load diff
2279
drivers/scsi/qla2xxx/qla_bsg.c
Normal file
2279
drivers/scsi/qla2xxx/qla_bsg.c
Normal file
File diff suppressed because it is too large
Load diff
235
drivers/scsi/qla2xxx/qla_bsg.h
Normal file
235
drivers/scsi/qla2xxx/qla_bsg.h
Normal file
|
|
@ -0,0 +1,235 @@
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|||
/*
|
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* QLogic Fibre Channel HBA Driver
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* Copyright (c) 2003-2014 QLogic Corporation
|
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*
|
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* See LICENSE.qla2xxx for copyright and licensing details.
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*/
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#ifndef __QLA_BSG_H
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#define __QLA_BSG_H
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|
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/* BSG Vendor specific commands */
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#define QL_VND_LOOPBACK 0x01
|
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#define QL_VND_A84_RESET 0x02
|
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#define QL_VND_A84_UPDATE_FW 0x03
|
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#define QL_VND_A84_MGMT_CMD 0x04
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#define QL_VND_IIDMA 0x05
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#define QL_VND_FCP_PRIO_CFG_CMD 0x06
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#define QL_VND_READ_FLASH 0x07
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#define QL_VND_UPDATE_FLASH 0x08
|
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#define QL_VND_SET_FRU_VERSION 0x0B
|
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#define QL_VND_READ_FRU_STATUS 0x0C
|
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#define QL_VND_WRITE_FRU_STATUS 0x0D
|
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#define QL_VND_DIAG_IO_CMD 0x0A
|
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#define QL_VND_WRITE_I2C 0x10
|
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#define QL_VND_READ_I2C 0x11
|
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#define QL_VND_FX00_MGMT_CMD 0x12
|
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#define QL_VND_SERDES_OP 0x13
|
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#define QL_VND_SERDES_OP_EX 0x14
|
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|
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/* BSG Vendor specific subcode returns */
|
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#define EXT_STATUS_OK 0
|
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#define EXT_STATUS_ERR 1
|
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#define EXT_STATUS_BUSY 2
|
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#define EXT_STATUS_INVALID_PARAM 6
|
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#define EXT_STATUS_DATA_OVERRUN 7
|
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#define EXT_STATUS_DATA_UNDERRUN 8
|
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#define EXT_STATUS_MAILBOX 11
|
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#define EXT_STATUS_NO_MEMORY 17
|
||||
#define EXT_STATUS_DEVICE_OFFLINE 22
|
||||
|
||||
/*
|
||||
* To support bidirectional iocb
|
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* BSG Vendor specific returns
|
||||
*/
|
||||
#define EXT_STATUS_NOT_SUPPORTED 27
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#define EXT_STATUS_INVALID_CFG 28
|
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#define EXT_STATUS_DMA_ERR 29
|
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#define EXT_STATUS_TIMEOUT 30
|
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#define EXT_STATUS_THREAD_FAILED 31
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#define EXT_STATUS_DATA_CMP_FAILED 32
|
||||
|
||||
/* BSG definations for interpreting CommandSent field */
|
||||
#define INT_DEF_LB_LOOPBACK_CMD 0
|
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#define INT_DEF_LB_ECHO_CMD 1
|
||||
|
||||
/* Loopback related definations */
|
||||
#define INTERNAL_LOOPBACK 0xF1
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#define EXTERNAL_LOOPBACK 0xF2
|
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#define ENABLE_INTERNAL_LOOPBACK 0x02
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#define ENABLE_EXTERNAL_LOOPBACK 0x04
|
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#define INTERNAL_LOOPBACK_MASK 0x000E
|
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#define MAX_ELS_FRAME_PAYLOAD 252
|
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#define ELS_OPCODE_BYTE 0x10
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||||
|
||||
/* BSG Vendor specific definations */
|
||||
#define A84_ISSUE_WRITE_TYPE_CMD 0
|
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#define A84_ISSUE_READ_TYPE_CMD 1
|
||||
#define A84_CLEANUP_CMD 2
|
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#define A84_ISSUE_RESET_OP_FW 3
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||||
#define A84_ISSUE_RESET_DIAG_FW 4
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#define A84_ISSUE_UPDATE_OPFW_CMD 5
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#define A84_ISSUE_UPDATE_DIAGFW_CMD 6
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|
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struct qla84_mgmt_param {
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union {
|
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struct {
|
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uint32_t start_addr;
|
||||
} mem; /* for QLA84_MGMT_READ/WRITE_MEM */
|
||||
struct {
|
||||
uint32_t id;
|
||||
#define QLA84_MGMT_CONFIG_ID_UIF 1
|
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#define QLA84_MGMT_CONFIG_ID_FCOE_COS 2
|
||||
#define QLA84_MGMT_CONFIG_ID_PAUSE 3
|
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#define QLA84_MGMT_CONFIG_ID_TIMEOUTS 4
|
||||
|
||||
uint32_t param0;
|
||||
uint32_t param1;
|
||||
} config; /* for QLA84_MGMT_CHNG_CONFIG */
|
||||
|
||||
struct {
|
||||
uint32_t type;
|
||||
#define QLA84_MGMT_INFO_CONFIG_LOG_DATA 1 /* Get Config Log Data */
|
||||
#define QLA84_MGMT_INFO_LOG_DATA 2 /* Get Log Data */
|
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#define QLA84_MGMT_INFO_PORT_STAT 3 /* Get Port Statistics */
|
||||
#define QLA84_MGMT_INFO_LIF_STAT 4 /* Get LIF Statistics */
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||||
#define QLA84_MGMT_INFO_ASIC_STAT 5 /* Get ASIC Statistics */
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#define QLA84_MGMT_INFO_CONFIG_PARAMS 6 /* Get Config Parameters */
|
||||
#define QLA84_MGMT_INFO_PANIC_LOG 7 /* Get Panic Log */
|
||||
|
||||
uint32_t context;
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/*
|
||||
* context definitions for QLA84_MGMT_INFO_CONFIG_LOG_DATA
|
||||
*/
|
||||
#define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0
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#define IC_LOG_DATA_LOG_ID_LEARN_LOG 1
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||||
#define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2
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||||
#define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3
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#define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4
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#define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5
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||||
#define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6
|
||||
#define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7
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||||
#define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8
|
||||
#define IC_LOG_DATA_LOG_ID_DCX_LOG 9
|
||||
|
||||
/*
|
||||
* context definitions for QLA84_MGMT_INFO_PORT_STAT
|
||||
*/
|
||||
#define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0
|
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#define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1
|
||||
#define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2
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||||
#define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3
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||||
#define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4
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||||
#define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5
|
||||
|
||||
|
||||
/*
|
||||
* context definitions for QLA84_MGMT_INFO_LIF_STAT
|
||||
*/
|
||||
#define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0
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||||
#define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1
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#define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2
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||||
#define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3
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#define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6
|
||||
|
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} info; /* for QLA84_MGMT_GET_INFO */
|
||||
} u;
|
||||
};
|
||||
|
||||
struct qla84_msg_mgmt {
|
||||
uint16_t cmd;
|
||||
#define QLA84_MGMT_READ_MEM 0x00
|
||||
#define QLA84_MGMT_WRITE_MEM 0x01
|
||||
#define QLA84_MGMT_CHNG_CONFIG 0x02
|
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#define QLA84_MGMT_GET_INFO 0x03
|
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uint16_t rsrvd;
|
||||
struct qla84_mgmt_param mgmtp;/* parameters for cmd */
|
||||
uint32_t len; /* bytes in payload following this struct */
|
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uint8_t payload[0]; /* payload for cmd */
|
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};
|
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|
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struct qla_bsg_a84_mgmt {
|
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struct qla84_msg_mgmt mgmt;
|
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} __attribute__ ((packed));
|
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|
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struct qla_scsi_addr {
|
||||
uint16_t bus;
|
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uint16_t target;
|
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} __attribute__ ((packed));
|
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|
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struct qla_ext_dest_addr {
|
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union {
|
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uint8_t wwnn[8];
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uint8_t wwpn[8];
|
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uint8_t id[4];
|
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struct qla_scsi_addr scsi_addr;
|
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} dest_addr;
|
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uint16_t dest_type;
|
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#define EXT_DEF_TYPE_WWPN 2
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uint16_t lun;
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uint16_t padding[2];
|
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} __attribute__ ((packed));
|
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|
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struct qla_port_param {
|
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struct qla_ext_dest_addr fc_scsi_addr;
|
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uint16_t mode;
|
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uint16_t speed;
|
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} __attribute__ ((packed));
|
||||
|
||||
|
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/* FRU VPD */
|
||||
|
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#define MAX_FRU_SIZE 36
|
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|
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struct qla_field_address {
|
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uint16_t offset;
|
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uint16_t device;
|
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uint16_t option;
|
||||
} __packed;
|
||||
|
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struct qla_field_info {
|
||||
uint8_t version[MAX_FRU_SIZE];
|
||||
} __packed;
|
||||
|
||||
struct qla_image_version {
|
||||
struct qla_field_address field_address;
|
||||
struct qla_field_info field_info;
|
||||
} __packed;
|
||||
|
||||
struct qla_image_version_list {
|
||||
uint32_t count;
|
||||
struct qla_image_version version[0];
|
||||
} __packed;
|
||||
|
||||
struct qla_status_reg {
|
||||
struct qla_field_address field_address;
|
||||
uint8_t status_reg;
|
||||
uint8_t reserved[7];
|
||||
} __packed;
|
||||
|
||||
struct qla_i2c_access {
|
||||
uint16_t device;
|
||||
uint16_t offset;
|
||||
uint16_t option;
|
||||
uint16_t length;
|
||||
uint8_t buffer[0x40];
|
||||
} __packed;
|
||||
|
||||
/* 26xx serdes register interface */
|
||||
|
||||
/* serdes reg commands */
|
||||
#define INT_SC_SERDES_READ_REG 1
|
||||
#define INT_SC_SERDES_WRITE_REG 2
|
||||
|
||||
struct qla_serdes_reg {
|
||||
uint16_t cmd;
|
||||
uint16_t addr;
|
||||
uint16_t val;
|
||||
} __packed;
|
||||
|
||||
struct qla_serdes_reg_ex {
|
||||
uint16_t cmd;
|
||||
uint32_t addr;
|
||||
uint32_t val;
|
||||
} __packed;
|
||||
|
||||
#endif
|
||||
2696
drivers/scsi/qla2xxx/qla_dbg.c
Normal file
2696
drivers/scsi/qla2xxx/qla_dbg.c
Normal file
File diff suppressed because it is too large
Load diff
358
drivers/scsi/qla2xxx/qla_dbg.h
Normal file
358
drivers/scsi/qla2xxx/qla_dbg.h
Normal file
|
|
@ -0,0 +1,358 @@
|
|||
/*
|
||||
* QLogic Fibre Channel HBA Driver
|
||||
* Copyright (c) 2003-2014 QLogic Corporation
|
||||
*
|
||||
* See LICENSE.qla2xxx for copyright and licensing details.
|
||||
*/
|
||||
|
||||
#include "qla_def.h"
|
||||
|
||||
/*
|
||||
* Firmware Dump structure definition
|
||||
*/
|
||||
|
||||
struct qla2300_fw_dump {
|
||||
uint16_t hccr;
|
||||
uint16_t pbiu_reg[8];
|
||||
uint16_t risc_host_reg[8];
|
||||
uint16_t mailbox_reg[32];
|
||||
uint16_t resp_dma_reg[32];
|
||||
uint16_t dma_reg[48];
|
||||
uint16_t risc_hdw_reg[16];
|
||||
uint16_t risc_gp0_reg[16];
|
||||
uint16_t risc_gp1_reg[16];
|
||||
uint16_t risc_gp2_reg[16];
|
||||
uint16_t risc_gp3_reg[16];
|
||||
uint16_t risc_gp4_reg[16];
|
||||
uint16_t risc_gp5_reg[16];
|
||||
uint16_t risc_gp6_reg[16];
|
||||
uint16_t risc_gp7_reg[16];
|
||||
uint16_t frame_buf_hdw_reg[64];
|
||||
uint16_t fpm_b0_reg[64];
|
||||
uint16_t fpm_b1_reg[64];
|
||||
uint16_t risc_ram[0xf800];
|
||||
uint16_t stack_ram[0x1000];
|
||||
uint16_t data_ram[1];
|
||||
};
|
||||
|
||||
struct qla2100_fw_dump {
|
||||
uint16_t hccr;
|
||||
uint16_t pbiu_reg[8];
|
||||
uint16_t mailbox_reg[32];
|
||||
uint16_t dma_reg[48];
|
||||
uint16_t risc_hdw_reg[16];
|
||||
uint16_t risc_gp0_reg[16];
|
||||
uint16_t risc_gp1_reg[16];
|
||||
uint16_t risc_gp2_reg[16];
|
||||
uint16_t risc_gp3_reg[16];
|
||||
uint16_t risc_gp4_reg[16];
|
||||
uint16_t risc_gp5_reg[16];
|
||||
uint16_t risc_gp6_reg[16];
|
||||
uint16_t risc_gp7_reg[16];
|
||||
uint16_t frame_buf_hdw_reg[16];
|
||||
uint16_t fpm_b0_reg[64];
|
||||
uint16_t fpm_b1_reg[64];
|
||||
uint16_t risc_ram[0xf000];
|
||||
};
|
||||
|
||||
struct qla24xx_fw_dump {
|
||||
uint32_t host_status;
|
||||
uint32_t host_reg[32];
|
||||
uint32_t shadow_reg[7];
|
||||
uint16_t mailbox_reg[32];
|
||||
uint32_t xseq_gp_reg[128];
|
||||
uint32_t xseq_0_reg[16];
|
||||
uint32_t xseq_1_reg[16];
|
||||
uint32_t rseq_gp_reg[128];
|
||||
uint32_t rseq_0_reg[16];
|
||||
uint32_t rseq_1_reg[16];
|
||||
uint32_t rseq_2_reg[16];
|
||||
uint32_t cmd_dma_reg[16];
|
||||
uint32_t req0_dma_reg[15];
|
||||
uint32_t resp0_dma_reg[15];
|
||||
uint32_t req1_dma_reg[15];
|
||||
uint32_t xmt0_dma_reg[32];
|
||||
uint32_t xmt1_dma_reg[32];
|
||||
uint32_t xmt2_dma_reg[32];
|
||||
uint32_t xmt3_dma_reg[32];
|
||||
uint32_t xmt4_dma_reg[32];
|
||||
uint32_t xmt_data_dma_reg[16];
|
||||
uint32_t rcvt0_data_dma_reg[32];
|
||||
uint32_t rcvt1_data_dma_reg[32];
|
||||
uint32_t risc_gp_reg[128];
|
||||
uint32_t lmc_reg[112];
|
||||
uint32_t fpm_hdw_reg[192];
|
||||
uint32_t fb_hdw_reg[176];
|
||||
uint32_t code_ram[0x2000];
|
||||
uint32_t ext_mem[1];
|
||||
};
|
||||
|
||||
struct qla25xx_fw_dump {
|
||||
uint32_t host_status;
|
||||
uint32_t host_risc_reg[32];
|
||||
uint32_t pcie_regs[4];
|
||||
uint32_t host_reg[32];
|
||||
uint32_t shadow_reg[11];
|
||||
uint32_t risc_io_reg;
|
||||
uint16_t mailbox_reg[32];
|
||||
uint32_t xseq_gp_reg[128];
|
||||
uint32_t xseq_0_reg[48];
|
||||
uint32_t xseq_1_reg[16];
|
||||
uint32_t rseq_gp_reg[128];
|
||||
uint32_t rseq_0_reg[32];
|
||||
uint32_t rseq_1_reg[16];
|
||||
uint32_t rseq_2_reg[16];
|
||||
uint32_t aseq_gp_reg[128];
|
||||
uint32_t aseq_0_reg[32];
|
||||
uint32_t aseq_1_reg[16];
|
||||
uint32_t aseq_2_reg[16];
|
||||
uint32_t cmd_dma_reg[16];
|
||||
uint32_t req0_dma_reg[15];
|
||||
uint32_t resp0_dma_reg[15];
|
||||
uint32_t req1_dma_reg[15];
|
||||
uint32_t xmt0_dma_reg[32];
|
||||
uint32_t xmt1_dma_reg[32];
|
||||
uint32_t xmt2_dma_reg[32];
|
||||
uint32_t xmt3_dma_reg[32];
|
||||
uint32_t xmt4_dma_reg[32];
|
||||
uint32_t xmt_data_dma_reg[16];
|
||||
uint32_t rcvt0_data_dma_reg[32];
|
||||
uint32_t rcvt1_data_dma_reg[32];
|
||||
uint32_t risc_gp_reg[128];
|
||||
uint32_t lmc_reg[128];
|
||||
uint32_t fpm_hdw_reg[192];
|
||||
uint32_t fb_hdw_reg[192];
|
||||
uint32_t code_ram[0x2000];
|
||||
uint32_t ext_mem[1];
|
||||
};
|
||||
|
||||
struct qla81xx_fw_dump {
|
||||
uint32_t host_status;
|
||||
uint32_t host_risc_reg[32];
|
||||
uint32_t pcie_regs[4];
|
||||
uint32_t host_reg[32];
|
||||
uint32_t shadow_reg[11];
|
||||
uint32_t risc_io_reg;
|
||||
uint16_t mailbox_reg[32];
|
||||
uint32_t xseq_gp_reg[128];
|
||||
uint32_t xseq_0_reg[48];
|
||||
uint32_t xseq_1_reg[16];
|
||||
uint32_t rseq_gp_reg[128];
|
||||
uint32_t rseq_0_reg[32];
|
||||
uint32_t rseq_1_reg[16];
|
||||
uint32_t rseq_2_reg[16];
|
||||
uint32_t aseq_gp_reg[128];
|
||||
uint32_t aseq_0_reg[32];
|
||||
uint32_t aseq_1_reg[16];
|
||||
uint32_t aseq_2_reg[16];
|
||||
uint32_t cmd_dma_reg[16];
|
||||
uint32_t req0_dma_reg[15];
|
||||
uint32_t resp0_dma_reg[15];
|
||||
uint32_t req1_dma_reg[15];
|
||||
uint32_t xmt0_dma_reg[32];
|
||||
uint32_t xmt1_dma_reg[32];
|
||||
uint32_t xmt2_dma_reg[32];
|
||||
uint32_t xmt3_dma_reg[32];
|
||||
uint32_t xmt4_dma_reg[32];
|
||||
uint32_t xmt_data_dma_reg[16];
|
||||
uint32_t rcvt0_data_dma_reg[32];
|
||||
uint32_t rcvt1_data_dma_reg[32];
|
||||
uint32_t risc_gp_reg[128];
|
||||
uint32_t lmc_reg[128];
|
||||
uint32_t fpm_hdw_reg[224];
|
||||
uint32_t fb_hdw_reg[208];
|
||||
uint32_t code_ram[0x2000];
|
||||
uint32_t ext_mem[1];
|
||||
};
|
||||
|
||||
struct qla83xx_fw_dump {
|
||||
uint32_t host_status;
|
||||
uint32_t host_risc_reg[48];
|
||||
uint32_t pcie_regs[4];
|
||||
uint32_t host_reg[32];
|
||||
uint32_t shadow_reg[11];
|
||||
uint32_t risc_io_reg;
|
||||
uint16_t mailbox_reg[32];
|
||||
uint32_t xseq_gp_reg[256];
|
||||
uint32_t xseq_0_reg[48];
|
||||
uint32_t xseq_1_reg[16];
|
||||
uint32_t xseq_2_reg[16];
|
||||
uint32_t rseq_gp_reg[256];
|
||||
uint32_t rseq_0_reg[32];
|
||||
uint32_t rseq_1_reg[16];
|
||||
uint32_t rseq_2_reg[16];
|
||||
uint32_t rseq_3_reg[16];
|
||||
uint32_t aseq_gp_reg[256];
|
||||
uint32_t aseq_0_reg[32];
|
||||
uint32_t aseq_1_reg[16];
|
||||
uint32_t aseq_2_reg[16];
|
||||
uint32_t aseq_3_reg[16];
|
||||
uint32_t cmd_dma_reg[64];
|
||||
uint32_t req0_dma_reg[15];
|
||||
uint32_t resp0_dma_reg[15];
|
||||
uint32_t req1_dma_reg[15];
|
||||
uint32_t xmt0_dma_reg[32];
|
||||
uint32_t xmt1_dma_reg[32];
|
||||
uint32_t xmt2_dma_reg[32];
|
||||
uint32_t xmt3_dma_reg[32];
|
||||
uint32_t xmt4_dma_reg[32];
|
||||
uint32_t xmt_data_dma_reg[16];
|
||||
uint32_t rcvt0_data_dma_reg[32];
|
||||
uint32_t rcvt1_data_dma_reg[32];
|
||||
uint32_t risc_gp_reg[128];
|
||||
uint32_t lmc_reg[128];
|
||||
uint32_t fpm_hdw_reg[256];
|
||||
uint32_t rq0_array_reg[256];
|
||||
uint32_t rq1_array_reg[256];
|
||||
uint32_t rp0_array_reg[256];
|
||||
uint32_t rp1_array_reg[256];
|
||||
uint32_t queue_control_reg[16];
|
||||
uint32_t fb_hdw_reg[432];
|
||||
uint32_t at0_array_reg[128];
|
||||
uint32_t code_ram[0x2400];
|
||||
uint32_t ext_mem[1];
|
||||
};
|
||||
|
||||
#define EFT_NUM_BUFFERS 4
|
||||
#define EFT_BYTES_PER_BUFFER 0x4000
|
||||
#define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
|
||||
|
||||
#define FCE_NUM_BUFFERS 64
|
||||
#define FCE_BYTES_PER_BUFFER 0x400
|
||||
#define FCE_SIZE ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS))
|
||||
#define fce_calc_size(b) ((FCE_BYTES_PER_BUFFER) * (b))
|
||||
|
||||
struct qla2xxx_fce_chain {
|
||||
uint32_t type;
|
||||
uint32_t chain_size;
|
||||
|
||||
uint32_t size;
|
||||
uint32_t addr_l;
|
||||
uint32_t addr_h;
|
||||
uint32_t eregs[8];
|
||||
};
|
||||
|
||||
struct qla2xxx_mq_chain {
|
||||
uint32_t type;
|
||||
uint32_t chain_size;
|
||||
|
||||
uint32_t count;
|
||||
uint32_t qregs[4 * QLA_MQ_SIZE];
|
||||
};
|
||||
|
||||
struct qla2xxx_mqueue_header {
|
||||
uint32_t queue;
|
||||
#define TYPE_REQUEST_QUEUE 0x1
|
||||
#define TYPE_RESPONSE_QUEUE 0x2
|
||||
#define TYPE_ATIO_QUEUE 0x3
|
||||
uint32_t number;
|
||||
uint32_t size;
|
||||
};
|
||||
|
||||
struct qla2xxx_mqueue_chain {
|
||||
uint32_t type;
|
||||
uint32_t chain_size;
|
||||
};
|
||||
|
||||
#define DUMP_CHAIN_VARIANT 0x80000000
|
||||
#define DUMP_CHAIN_FCE 0x7FFFFAF0
|
||||
#define DUMP_CHAIN_MQ 0x7FFFFAF1
|
||||
#define DUMP_CHAIN_QUEUE 0x7FFFFAF2
|
||||
#define DUMP_CHAIN_LAST 0x80000000
|
||||
|
||||
struct qla2xxx_fw_dump {
|
||||
uint8_t signature[4];
|
||||
uint32_t version;
|
||||
|
||||
uint32_t fw_major_version;
|
||||
uint32_t fw_minor_version;
|
||||
uint32_t fw_subminor_version;
|
||||
uint32_t fw_attributes;
|
||||
|
||||
uint32_t vendor;
|
||||
uint32_t device;
|
||||
uint32_t subsystem_vendor;
|
||||
uint32_t subsystem_device;
|
||||
|
||||
uint32_t fixed_size;
|
||||
uint32_t mem_size;
|
||||
uint32_t req_q_size;
|
||||
uint32_t rsp_q_size;
|
||||
|
||||
uint32_t eft_size;
|
||||
uint32_t eft_addr_l;
|
||||
uint32_t eft_addr_h;
|
||||
|
||||
uint32_t header_size;
|
||||
|
||||
union {
|
||||
struct qla2100_fw_dump isp21;
|
||||
struct qla2300_fw_dump isp23;
|
||||
struct qla24xx_fw_dump isp24;
|
||||
struct qla25xx_fw_dump isp25;
|
||||
struct qla81xx_fw_dump isp81;
|
||||
struct qla83xx_fw_dump isp83;
|
||||
} isp;
|
||||
};
|
||||
|
||||
#define QL_MSGHDR "qla2xxx"
|
||||
#define QL_DBG_DEFAULT1_MASK 0x1e400000
|
||||
|
||||
#define ql_log_fatal 0 /* display fatal errors */
|
||||
#define ql_log_warn 1 /* display critical errors */
|
||||
#define ql_log_info 2 /* display all recovered errors */
|
||||
#define ql_log_all 3 /* This value is only used by ql_errlev.
|
||||
* No messages will use this value.
|
||||
* This should be always highest value
|
||||
* as compared to other log levels.
|
||||
*/
|
||||
|
||||
extern int ql_errlev;
|
||||
|
||||
void __attribute__((format (printf, 4, 5)))
|
||||
ql_dbg(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
|
||||
void __attribute__((format (printf, 4, 5)))
|
||||
ql_dbg_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
|
||||
|
||||
void __attribute__((format (printf, 4, 5)))
|
||||
ql_log(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
|
||||
void __attribute__((format (printf, 4, 5)))
|
||||
ql_log_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
|
||||
|
||||
/* Debug Levels */
|
||||
/* The 0x40000000 is the max value any debug level can have
|
||||
* as ql2xextended_error_logging is of type signed int
|
||||
*/
|
||||
#define ql_dbg_init 0x40000000 /* Init Debug */
|
||||
#define ql_dbg_mbx 0x20000000 /* MBX Debug */
|
||||
#define ql_dbg_disc 0x10000000 /* Device Discovery Debug */
|
||||
#define ql_dbg_io 0x08000000 /* IO Tracing Debug */
|
||||
#define ql_dbg_dpc 0x04000000 /* DPC Thead Debug */
|
||||
#define ql_dbg_async 0x02000000 /* Async events Debug */
|
||||
#define ql_dbg_timer 0x01000000 /* Timer Debug */
|
||||
#define ql_dbg_user 0x00800000 /* User Space Interations Debug */
|
||||
#define ql_dbg_taskm 0x00400000 /* Task Management Debug */
|
||||
#define ql_dbg_aer 0x00200000 /* AER/EEH Debug */
|
||||
#define ql_dbg_multiq 0x00100000 /* MultiQ Debug */
|
||||
#define ql_dbg_p3p 0x00080000 /* P3P specific Debug */
|
||||
#define ql_dbg_vport 0x00040000 /* Virtual Port Debug */
|
||||
#define ql_dbg_buffer 0x00020000 /* For dumping the buffer/regs */
|
||||
#define ql_dbg_misc 0x00010000 /* For dumping everything that is not
|
||||
* not covered by upper categories
|
||||
*/
|
||||
#define ql_dbg_verbose 0x00008000 /* More verbosity for each level
|
||||
* This is to be used with other levels where
|
||||
* more verbosity is required. It might not
|
||||
* be applicable to all the levels.
|
||||
*/
|
||||
#define ql_dbg_tgt 0x00004000 /* Target mode */
|
||||
#define ql_dbg_tgt_mgt 0x00002000 /* Target mode management */
|
||||
#define ql_dbg_tgt_tmr 0x00001000 /* Target mode task management */
|
||||
|
||||
extern int qla27xx_dump_mpi_ram(struct qla_hw_data *, uint32_t, uint32_t *,
|
||||
uint32_t, void **);
|
||||
extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, uint32_t *,
|
||||
uint32_t, void **);
|
||||
extern void qla24xx_pause_risc(struct device_reg_24xx __iomem *,
|
||||
struct qla_hw_data *);
|
||||
extern int qla24xx_soft_reset(struct qla_hw_data *);
|
||||
3709
drivers/scsi/qla2xxx/qla_def.h
Normal file
3709
drivers/scsi/qla2xxx/qla_def.h
Normal file
File diff suppressed because it is too large
Load diff
99
drivers/scsi/qla2xxx/qla_devtbl.h
Normal file
99
drivers/scsi/qla2xxx/qla_devtbl.h
Normal file
|
|
@ -0,0 +1,99 @@
|
|||
#define QLA_MODEL_NAMES 0x5C
|
||||
|
||||
/*
|
||||
* Adapter model names and descriptions.
|
||||
*/
|
||||
static char *qla2x00_model_name[QLA_MODEL_NAMES*2] = {
|
||||
"QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
|
||||
"QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
|
||||
"QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
|
||||
"QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
|
||||
"QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
|
||||
"QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
|
||||
"QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
|
||||
"QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
|
||||
"QCP2332", "Sun cPCI to 2Gb FC, Dual Channel", /* 0x108 */
|
||||
"QCP2340", "cPCI to 2Gb FC, Single Channel", /* 0x109 */
|
||||
"QLA2342", "Sun 133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10a */
|
||||
"QCP2342", "Sun - cPCI to 2Gb FC, Dual Channel", /* 0x10b */
|
||||
"QLA2350", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x10c */
|
||||
"QLA2352", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10d */
|
||||
"QLA2352", "Sun 133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10e */
|
||||
" ", " ", /* 0x10f */
|
||||
" ", " ", /* 0x110 */
|
||||
" ", " ", /* 0x111 */
|
||||
" ", " ", /* 0x112 */
|
||||
" ", " ", /* 0x113 */
|
||||
" ", " ", /* 0x114 */
|
||||
"QLA2360", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x115 */
|
||||
"QLA2362", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x116 */
|
||||
"QLE2360", "PCI-Express to 2Gb FC, Single Channel", /* 0x117 */
|
||||
"QLE2362", "PCI-Express to 2Gb FC, Dual Channel", /* 0x118 */
|
||||
"QLA200", "133MHz PCI-X to 2Gb FC Optical", /* 0x119 */
|
||||
" ", " ", /* 0x11a */
|
||||
" ", " ", /* 0x11b */
|
||||
"QLA200P", "133MHz PCI-X to 2Gb FC SFP", /* 0x11c */
|
||||
" ", " ", /* 0x11d */
|
||||
" ", " ", /* 0x11e */
|
||||
" ", " ", /* 0x11f */
|
||||
" ", " ", /* 0x120 */
|
||||
" ", " ", /* 0x121 */
|
||||
" ", " ", /* 0x122 */
|
||||
" ", " ", /* 0x123 */
|
||||
" ", " ", /* 0x124 */
|
||||
" ", " ", /* 0x125 */
|
||||
" ", " ", /* 0x126 */
|
||||
" ", " ", /* 0x127 */
|
||||
" ", " ", /* 0x128 */
|
||||
" ", " ", /* 0x129 */
|
||||
" ", " ", /* 0x12a */
|
||||
" ", " ", /* 0x12b */
|
||||
" ", " ", /* 0x12c */
|
||||
" ", " ", /* 0x12d */
|
||||
" ", " ", /* 0x12e */
|
||||
"QLA210", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x12f */
|
||||
"EMC 250", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x130 */
|
||||
"HP A7538A", "HP 1p2g PCI-X to 2Gb FC, Single Channel", /* 0x131 */
|
||||
"QLA210", "Sun 133MHz PCI-X to 2Gb FC, Single Channel", /* 0x132 */
|
||||
"QLA2460", "PCI-X 2.0 to 4Gb FC, Single Channel", /* 0x133 */
|
||||
"QLA2462", "PCI-X 2.0 to 4Gb FC, Dual Channel", /* 0x134 */
|
||||
"QMC2462", "IBM eServer BC 4Gb FC Expansion Card", /* 0x135 */
|
||||
"QMC2462S", "IBM eServer BC 4Gb FC Expansion Card SFF", /* 0x136 */
|
||||
"QLE2460", "PCI-Express to 4Gb FC, Single Channel", /* 0x137 */
|
||||
"QLE2462", "PCI-Express to 4Gb FC, Dual Channel", /* 0x138 */
|
||||
"QME2462", "Dell BS PCI-Express to 4Gb FC, Dual Channel", /* 0x139 */
|
||||
" ", " ", /* 0x13a */
|
||||
" ", " ", /* 0x13b */
|
||||
" ", " ", /* 0x13c */
|
||||
"QEM2462", "Sun Server I/O Module 4Gb FC, Dual Channel", /* 0x13d */
|
||||
"QLE210", "PCI-Express to 2Gb FC, Single Channel", /* 0x13e */
|
||||
"QLE220", "PCI-Express to 4Gb FC, Single Channel", /* 0x13f */
|
||||
"QLA2460", "Sun PCI-X 2.0 to 4Gb FC, Single Channel", /* 0x140 */
|
||||
"QLA2462", "Sun PCI-X 2.0 to 4Gb FC, Dual Channel", /* 0x141 */
|
||||
"QLE2460", "Sun PCI-Express to 2Gb FC, Single Channel", /* 0x142 */
|
||||
"QLE2462", "Sun PCI-Express to 4Gb FC, Single Channel", /* 0x143 */
|
||||
"QEM2462", "Server I/O Module 4Gb FC, Dual Channel", /* 0x144 */
|
||||
"QLE2440", "PCI-Express to 4Gb FC, Single Channel", /* 0x145 */
|
||||
"QLE2464", "PCI-Express to 4Gb FC, Quad Channel", /* 0x146 */
|
||||
"QLA2440", "PCI-X 2.0 to 4Gb FC, Single Channel", /* 0x147 */
|
||||
"HP AE369A", "PCI-X 2.0 to 4Gb FC, Dual Channel", /* 0x148 */
|
||||
"QLA2340", "Sun 133MHz PCI-X to 2Gb FC, Single Channel", /* 0x149 */
|
||||
" ", " ", /* 0x14a */
|
||||
" ", " ", /* 0x14b */
|
||||
"QMC2432M", "IBM eServer BC 4Gb FC Expansion Card CFFE", /* 0x14c */
|
||||
"QMC2422M", "IBM eServer BC 4Gb FC Expansion Card CFFX", /* 0x14d */
|
||||
"QLE220", "Sun PCI-Express to 4Gb FC, Single Channel", /* 0x14e */
|
||||
" ", " ", /* 0x14f */
|
||||
" ", " ", /* 0x150 */
|
||||
" ", " ", /* 0x151 */
|
||||
"QME2462", "PCI-Express to 4Gb FC, Dual Channel Mezz HBA", /* 0x152 */
|
||||
"QMH2462", "PCI-Express to 4Gb FC, Dual Channel Mezz HBA", /* 0x153 */
|
||||
" ", " ", /* 0x154 */
|
||||
"QLE220", "PCI-Express to 4Gb FC, Single Channel", /* 0x155 */
|
||||
"QLE220", "PCI-Express to 4Gb FC, Single Channel", /* 0x156 */
|
||||
" ", " ", /* 0x157 */
|
||||
" ", " ", /* 0x158 */
|
||||
" ", " ", /* 0x159 */
|
||||
" ", " ", /* 0x15a */
|
||||
"QME2472", "Dell BS PCI-Express to 4Gb FC, Dual Channel", /* 0x15b */
|
||||
};
|
||||
182
drivers/scsi/qla2xxx/qla_dfs.c
Normal file
182
drivers/scsi/qla2xxx/qla_dfs.c
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
/*
|
||||
* QLogic Fibre Channel HBA Driver
|
||||
* Copyright (c) 2003-2014 QLogic Corporation
|
||||
*
|
||||
* See LICENSE.qla2xxx for copyright and licensing details.
|
||||
*/
|
||||
#include "qla_def.h"
|
||||
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/seq_file.h>
|
||||
|
||||
static struct dentry *qla2x00_dfs_root;
|
||||
static atomic_t qla2x00_dfs_root_count;
|
||||
|
||||
static int
|
||||
qla2x00_dfs_fce_show(struct seq_file *s, void *unused)
|
||||
{
|
||||
scsi_qla_host_t *vha = s->private;
|
||||
uint32_t cnt;
|
||||
uint32_t *fce;
|
||||
uint64_t fce_start;
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
|
||||
mutex_lock(&ha->fce_mutex);
|
||||
|
||||
seq_printf(s, "FCE Trace Buffer\n");
|
||||
seq_printf(s, "In Pointer = %llx\n\n", (unsigned long long)ha->fce_wr);
|
||||
seq_printf(s, "Base = %llx\n\n", (unsigned long long) ha->fce_dma);
|
||||
seq_printf(s, "FCE Enable Registers\n");
|
||||
seq_printf(s, "%08x %08x %08x %08x %08x %08x\n",
|
||||
ha->fce_mb[0], ha->fce_mb[2], ha->fce_mb[3], ha->fce_mb[4],
|
||||
ha->fce_mb[5], ha->fce_mb[6]);
|
||||
|
||||
fce = (uint32_t *) ha->fce;
|
||||
fce_start = (unsigned long long) ha->fce_dma;
|
||||
for (cnt = 0; cnt < fce_calc_size(ha->fce_bufs) / 4; cnt++) {
|
||||
if (cnt % 8 == 0)
|
||||
seq_printf(s, "\n%llx: ",
|
||||
(unsigned long long)((cnt * 4) + fce_start));
|
||||
else
|
||||
seq_printf(s, " ");
|
||||
seq_printf(s, "%08x", *fce++);
|
||||
}
|
||||
|
||||
seq_printf(s, "\nEnd\n");
|
||||
|
||||
mutex_unlock(&ha->fce_mutex);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
qla2x00_dfs_fce_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
scsi_qla_host_t *vha = inode->i_private;
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
int rval;
|
||||
|
||||
if (!ha->flags.fce_enabled)
|
||||
goto out;
|
||||
|
||||
mutex_lock(&ha->fce_mutex);
|
||||
|
||||
/* Pause tracing to flush FCE buffers. */
|
||||
rval = qla2x00_disable_fce_trace(vha, &ha->fce_wr, &ha->fce_rd);
|
||||
if (rval)
|
||||
ql_dbg(ql_dbg_user, vha, 0x705c,
|
||||
"DebugFS: Unable to disable FCE (%d).\n", rval);
|
||||
|
||||
ha->flags.fce_enabled = 0;
|
||||
|
||||
mutex_unlock(&ha->fce_mutex);
|
||||
out:
|
||||
return single_open(file, qla2x00_dfs_fce_show, vha);
|
||||
}
|
||||
|
||||
static int
|
||||
qla2x00_dfs_fce_release(struct inode *inode, struct file *file)
|
||||
{
|
||||
scsi_qla_host_t *vha = inode->i_private;
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
int rval;
|
||||
|
||||
if (ha->flags.fce_enabled)
|
||||
goto out;
|
||||
|
||||
mutex_lock(&ha->fce_mutex);
|
||||
|
||||
/* Re-enable FCE tracing. */
|
||||
ha->flags.fce_enabled = 1;
|
||||
memset(ha->fce, 0, fce_calc_size(ha->fce_bufs));
|
||||
rval = qla2x00_enable_fce_trace(vha, ha->fce_dma, ha->fce_bufs,
|
||||
ha->fce_mb, &ha->fce_bufs);
|
||||
if (rval) {
|
||||
ql_dbg(ql_dbg_user, vha, 0x700d,
|
||||
"DebugFS: Unable to reinitialize FCE (%d).\n", rval);
|
||||
ha->flags.fce_enabled = 0;
|
||||
}
|
||||
|
||||
mutex_unlock(&ha->fce_mutex);
|
||||
out:
|
||||
return single_release(inode, file);
|
||||
}
|
||||
|
||||
static const struct file_operations dfs_fce_ops = {
|
||||
.open = qla2x00_dfs_fce_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = qla2x00_dfs_fce_release,
|
||||
};
|
||||
|
||||
int
|
||||
qla2x00_dfs_setup(scsi_qla_host_t *vha)
|
||||
{
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
|
||||
if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
|
||||
!IS_QLA27XX(ha))
|
||||
goto out;
|
||||
if (!ha->fce)
|
||||
goto out;
|
||||
|
||||
if (qla2x00_dfs_root)
|
||||
goto create_dir;
|
||||
|
||||
atomic_set(&qla2x00_dfs_root_count, 0);
|
||||
qla2x00_dfs_root = debugfs_create_dir(QLA2XXX_DRIVER_NAME, NULL);
|
||||
if (!qla2x00_dfs_root) {
|
||||
ql_log(ql_log_warn, vha, 0x00f7,
|
||||
"Unable to create debugfs root directory.\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
create_dir:
|
||||
if (ha->dfs_dir)
|
||||
goto create_nodes;
|
||||
|
||||
mutex_init(&ha->fce_mutex);
|
||||
ha->dfs_dir = debugfs_create_dir(vha->host_str, qla2x00_dfs_root);
|
||||
if (!ha->dfs_dir) {
|
||||
ql_log(ql_log_warn, vha, 0x00f8,
|
||||
"Unable to create debugfs ha directory.\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
atomic_inc(&qla2x00_dfs_root_count);
|
||||
|
||||
create_nodes:
|
||||
ha->dfs_fce = debugfs_create_file("fce", S_IRUSR, ha->dfs_dir, vha,
|
||||
&dfs_fce_ops);
|
||||
if (!ha->dfs_fce) {
|
||||
ql_log(ql_log_warn, vha, 0x00f9,
|
||||
"Unable to create debugfs fce node.\n");
|
||||
goto out;
|
||||
}
|
||||
out:
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
qla2x00_dfs_remove(scsi_qla_host_t *vha)
|
||||
{
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
if (ha->dfs_fce) {
|
||||
debugfs_remove(ha->dfs_fce);
|
||||
ha->dfs_fce = NULL;
|
||||
}
|
||||
|
||||
if (ha->dfs_dir) {
|
||||
debugfs_remove(ha->dfs_dir);
|
||||
ha->dfs_dir = NULL;
|
||||
atomic_dec(&qla2x00_dfs_root_count);
|
||||
}
|
||||
|
||||
if (atomic_read(&qla2x00_dfs_root_count) == 0 &&
|
||||
qla2x00_dfs_root) {
|
||||
debugfs_remove(qla2x00_dfs_root);
|
||||
qla2x00_dfs_root = NULL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
1954
drivers/scsi/qla2xxx/qla_fw.h
Normal file
1954
drivers/scsi/qla2xxx/qla_fw.h
Normal file
File diff suppressed because it is too large
Load diff
771
drivers/scsi/qla2xxx/qla_gbl.h
Normal file
771
drivers/scsi/qla2xxx/qla_gbl.h
Normal file
|
|
@ -0,0 +1,771 @@
|
|||
/*
|
||||
* QLogic Fibre Channel HBA Driver
|
||||
* Copyright (c) 2003-2014 QLogic Corporation
|
||||
*
|
||||
* See LICENSE.qla2xxx for copyright and licensing details.
|
||||
*/
|
||||
#ifndef __QLA_GBL_H
|
||||
#define __QLA_GBL_H
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
/*
|
||||
* Global Function Prototypes in qla_init.c source file.
|
||||
*/
|
||||
extern int qla2x00_initialize_adapter(scsi_qla_host_t *);
|
||||
|
||||
extern int qla2100_pci_config(struct scsi_qla_host *);
|
||||
extern int qla2300_pci_config(struct scsi_qla_host *);
|
||||
extern int qla24xx_pci_config(scsi_qla_host_t *);
|
||||
extern int qla25xx_pci_config(scsi_qla_host_t *);
|
||||
extern void qla2x00_reset_chip(struct scsi_qla_host *);
|
||||
extern void qla24xx_reset_chip(struct scsi_qla_host *);
|
||||
extern int qla2x00_chip_diag(struct scsi_qla_host *);
|
||||
extern int qla24xx_chip_diag(struct scsi_qla_host *);
|
||||
extern void qla2x00_config_rings(struct scsi_qla_host *);
|
||||
extern void qla24xx_config_rings(struct scsi_qla_host *);
|
||||
extern void qla2x00_reset_adapter(struct scsi_qla_host *);
|
||||
extern void qla24xx_reset_adapter(struct scsi_qla_host *);
|
||||
extern int qla2x00_nvram_config(struct scsi_qla_host *);
|
||||
extern int qla24xx_nvram_config(struct scsi_qla_host *);
|
||||
extern int qla81xx_nvram_config(struct scsi_qla_host *);
|
||||
extern void qla2x00_update_fw_options(struct scsi_qla_host *);
|
||||
extern void qla24xx_update_fw_options(scsi_qla_host_t *);
|
||||
extern void qla81xx_update_fw_options(scsi_qla_host_t *);
|
||||
extern int qla2x00_load_risc(struct scsi_qla_host *, uint32_t *);
|
||||
extern int qla24xx_load_risc(scsi_qla_host_t *, uint32_t *);
|
||||
extern int qla81xx_load_risc(scsi_qla_host_t *, uint32_t *);
|
||||
|
||||
extern int qla2x00_perform_loop_resync(scsi_qla_host_t *);
|
||||
extern int qla2x00_loop_resync(scsi_qla_host_t *);
|
||||
|
||||
extern int qla2x00_find_new_loop_id(scsi_qla_host_t *, fc_port_t *);
|
||||
|
||||
extern int qla2x00_fabric_login(scsi_qla_host_t *, fc_port_t *, uint16_t *);
|
||||
extern int qla2x00_local_device_login(scsi_qla_host_t *, fc_port_t *);
|
||||
|
||||
extern void qla2x00_update_fcports(scsi_qla_host_t *);
|
||||
|
||||
extern int qla2x00_abort_isp(scsi_qla_host_t *);
|
||||
extern void qla2x00_abort_isp_cleanup(scsi_qla_host_t *);
|
||||
extern void qla2x00_quiesce_io(scsi_qla_host_t *);
|
||||
|
||||
extern void qla2x00_update_fcport(scsi_qla_host_t *, fc_port_t *);
|
||||
|
||||
extern void qla2x00_alloc_fw_dump(scsi_qla_host_t *);
|
||||
extern void qla2x00_try_to_stop_firmware(scsi_qla_host_t *);
|
||||
|
||||
extern int qla2x00_get_thermal_temp(scsi_qla_host_t *, uint16_t *);
|
||||
|
||||
extern void qla84xx_put_chip(struct scsi_qla_host *);
|
||||
|
||||
extern int qla2x00_async_login(struct scsi_qla_host *, fc_port_t *,
|
||||
uint16_t *);
|
||||
extern int qla2x00_async_logout(struct scsi_qla_host *, fc_port_t *);
|
||||
extern int qla2x00_async_adisc(struct scsi_qla_host *, fc_port_t *,
|
||||
uint16_t *);
|
||||
extern int qla2x00_async_tm_cmd(fc_port_t *, uint32_t, uint32_t, uint32_t);
|
||||
extern void qla2x00_async_login_done(struct scsi_qla_host *, fc_port_t *,
|
||||
uint16_t *);
|
||||
extern void qla2x00_async_logout_done(struct scsi_qla_host *, fc_port_t *,
|
||||
uint16_t *);
|
||||
extern void qla2x00_async_adisc_done(struct scsi_qla_host *, fc_port_t *,
|
||||
uint16_t *);
|
||||
extern void *qla2x00_alloc_iocbs(struct scsi_qla_host *, srb_t *);
|
||||
extern void *qla2x00_alloc_iocbs_ready(struct scsi_qla_host *, srb_t *);
|
||||
extern int qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *, fc_port_t *);
|
||||
|
||||
extern fc_port_t *
|
||||
qla2x00_alloc_fcport(scsi_qla_host_t *, gfp_t );
|
||||
|
||||
extern int __qla83xx_set_idc_control(scsi_qla_host_t *, uint32_t);
|
||||
extern int __qla83xx_get_idc_control(scsi_qla_host_t *, uint32_t *);
|
||||
extern void qla83xx_idc_audit(scsi_qla_host_t *, int);
|
||||
extern int qla83xx_nic_core_reset(scsi_qla_host_t *);
|
||||
extern void qla83xx_reset_ownership(scsi_qla_host_t *);
|
||||
extern int qla2xxx_mctp_dump(scsi_qla_host_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_alloc_outstanding_cmds(struct qla_hw_data *, struct req_que *);
|
||||
extern int qla2x00_init_rings(scsi_qla_host_t *);
|
||||
|
||||
/*
|
||||
* Global Data in qla_os.c source file.
|
||||
*/
|
||||
extern char qla2x00_version_str[];
|
||||
|
||||
extern int ql2xlogintimeout;
|
||||
extern int qlport_down_retry;
|
||||
extern int ql2xplogiabsentdevice;
|
||||
extern int ql2xloginretrycount;
|
||||
extern int ql2xfdmienable;
|
||||
extern int ql2xallocfwdump;
|
||||
extern int ql2xextended_error_logging;
|
||||
extern int ql2xiidmaenable;
|
||||
extern int ql2xmaxqueues;
|
||||
extern int ql2xmultique_tag;
|
||||
extern int ql2xfwloadbin;
|
||||
extern int ql2xetsenable;
|
||||
extern int ql2xshiftctondsd;
|
||||
extern int ql2xdbwr;
|
||||
extern int ql2xasynctmfenable;
|
||||
extern int ql2xgffidenable;
|
||||
extern int ql2xenabledif;
|
||||
extern int ql2xenablehba_err_chk;
|
||||
extern int ql2xtargetreset;
|
||||
extern int ql2xdontresethba;
|
||||
extern uint64_t ql2xmaxlun;
|
||||
extern int ql2xmdcapmask;
|
||||
extern int ql2xmdenable;
|
||||
|
||||
extern int qla2x00_loop_reset(scsi_qla_host_t *);
|
||||
extern void qla2x00_abort_all_cmds(scsi_qla_host_t *, int);
|
||||
extern int qla2x00_post_aen_work(struct scsi_qla_host *, enum
|
||||
fc_host_event_code, u32);
|
||||
extern int qla2x00_post_idc_ack_work(struct scsi_qla_host *, uint16_t *);
|
||||
extern int qla2x00_post_async_login_work(struct scsi_qla_host *, fc_port_t *,
|
||||
uint16_t *);
|
||||
extern int qla2x00_post_async_login_done_work(struct scsi_qla_host *,
|
||||
fc_port_t *, uint16_t *);
|
||||
extern int qla2x00_post_async_logout_work(struct scsi_qla_host *, fc_port_t *,
|
||||
uint16_t *);
|
||||
extern int qla2x00_post_async_logout_done_work(struct scsi_qla_host *,
|
||||
fc_port_t *, uint16_t *);
|
||||
extern int qla2x00_post_async_adisc_work(struct scsi_qla_host *, fc_port_t *,
|
||||
uint16_t *);
|
||||
extern int qla2x00_post_async_adisc_done_work(struct scsi_qla_host *,
|
||||
fc_port_t *, uint16_t *);
|
||||
|
||||
extern int qla81xx_restart_mpi_firmware(scsi_qla_host_t *);
|
||||
|
||||
extern struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *,
|
||||
struct qla_hw_data *);
|
||||
extern void qla2x00_free_host(struct scsi_qla_host *);
|
||||
extern void qla2x00_relogin(struct scsi_qla_host *);
|
||||
extern void qla2x00_do_work(struct scsi_qla_host *);
|
||||
extern void qla2x00_free_fcports(struct scsi_qla_host *);
|
||||
|
||||
extern void qla83xx_schedule_work(scsi_qla_host_t *, int);
|
||||
extern void qla83xx_service_idc_aen(struct work_struct *);
|
||||
extern void qla83xx_nic_core_unrecoverable_work(struct work_struct *);
|
||||
extern void qla83xx_idc_state_handler_work(struct work_struct *);
|
||||
extern void qla83xx_nic_core_reset_work(struct work_struct *);
|
||||
|
||||
extern void qla83xx_idc_lock(scsi_qla_host_t *, uint16_t);
|
||||
extern void qla83xx_idc_unlock(scsi_qla_host_t *, uint16_t);
|
||||
extern int qla83xx_idc_state_handler(scsi_qla_host_t *);
|
||||
extern int qla83xx_set_drv_presence(scsi_qla_host_t *vha);
|
||||
extern int __qla83xx_set_drv_presence(scsi_qla_host_t *vha);
|
||||
extern int qla83xx_clear_drv_presence(scsi_qla_host_t *vha);
|
||||
extern int __qla83xx_clear_drv_presence(scsi_qla_host_t *vha);
|
||||
extern int qla2x00_post_uevent_work(struct scsi_qla_host *, u32);
|
||||
|
||||
extern int qla2x00_post_uevent_work(struct scsi_qla_host *, u32);
|
||||
extern void qla2x00_disable_board_on_pci_error(struct work_struct *);
|
||||
|
||||
/*
|
||||
* Global Functions in qla_mid.c source file.
|
||||
*/
|
||||
extern struct scsi_host_template qla2xxx_driver_template;
|
||||
extern struct scsi_transport_template *qla2xxx_transport_vport_template;
|
||||
extern void qla2x00_timer(scsi_qla_host_t *);
|
||||
extern void qla2x00_start_timer(scsi_qla_host_t *, void *, unsigned long);
|
||||
extern void qla24xx_deallocate_vp_id(scsi_qla_host_t *);
|
||||
extern int qla24xx_disable_vp (scsi_qla_host_t *);
|
||||
extern int qla24xx_enable_vp (scsi_qla_host_t *);
|
||||
extern int qla24xx_control_vp(scsi_qla_host_t *, int );
|
||||
extern int qla24xx_modify_vp_config(scsi_qla_host_t *);
|
||||
extern int qla2x00_send_change_request(scsi_qla_host_t *, uint16_t, uint16_t);
|
||||
extern void qla2x00_vp_stop_timer(scsi_qla_host_t *);
|
||||
extern int qla24xx_configure_vhba (scsi_qla_host_t *);
|
||||
extern void qla24xx_report_id_acquisition(scsi_qla_host_t *,
|
||||
struct vp_rpt_id_entry_24xx *);
|
||||
extern void qla2x00_do_dpc_all_vps(scsi_qla_host_t *);
|
||||
extern int qla24xx_vport_create_req_sanity_check(struct fc_vport *);
|
||||
extern scsi_qla_host_t * qla24xx_create_vhost(struct fc_vport *);
|
||||
|
||||
extern void qla2x00_sp_free_dma(void *, void *);
|
||||
extern char *qla2x00_get_fw_version_str(struct scsi_qla_host *, char *);
|
||||
|
||||
extern void qla2x00_mark_device_lost(scsi_qla_host_t *, fc_port_t *, int, int);
|
||||
extern void qla2x00_mark_all_devices_lost(scsi_qla_host_t *, int);
|
||||
|
||||
extern struct fw_blob *qla2x00_request_firmware(scsi_qla_host_t *);
|
||||
|
||||
extern int qla2x00_wait_for_hba_online(scsi_qla_host_t *);
|
||||
extern int qla2x00_wait_for_chip_reset(scsi_qla_host_t *);
|
||||
extern int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *);
|
||||
|
||||
extern void qla2xxx_wake_dpc(struct scsi_qla_host *);
|
||||
extern void qla2x00_alert_all_vps(struct rsp_que *, uint16_t *);
|
||||
extern void qla2x00_async_event(scsi_qla_host_t *, struct rsp_que *,
|
||||
uint16_t *);
|
||||
extern int qla2x00_vp_abort_isp(scsi_qla_host_t *);
|
||||
|
||||
/*
|
||||
* Global Function Prototypes in qla_iocb.c source file.
|
||||
*/
|
||||
|
||||
extern uint16_t qla2x00_calc_iocbs_32(uint16_t);
|
||||
extern uint16_t qla2x00_calc_iocbs_64(uint16_t);
|
||||
extern void qla2x00_build_scsi_iocbs_32(srb_t *, cmd_entry_t *, uint16_t);
|
||||
extern void qla2x00_build_scsi_iocbs_64(srb_t *, cmd_entry_t *, uint16_t);
|
||||
extern int qla2x00_start_scsi(srb_t *sp);
|
||||
extern int qla24xx_start_scsi(srb_t *sp);
|
||||
int qla2x00_marker(struct scsi_qla_host *, struct req_que *, struct rsp_que *,
|
||||
uint16_t, uint64_t, uint8_t);
|
||||
extern int qla2x00_start_sp(srb_t *);
|
||||
extern int qla24xx_dif_start_scsi(srb_t *);
|
||||
extern int qla2x00_start_bidir(srb_t *, struct scsi_qla_host *, uint32_t);
|
||||
extern unsigned long qla2x00_get_async_timeout(struct scsi_qla_host *);
|
||||
|
||||
extern void *qla2x00_alloc_iocbs(scsi_qla_host_t *, srb_t *);
|
||||
extern int qla2x00_issue_marker(scsi_qla_host_t *, int);
|
||||
extern int qla24xx_walk_and_build_sglist_no_difb(struct qla_hw_data *, srb_t *,
|
||||
uint32_t *, uint16_t, struct qla_tgt_cmd *);
|
||||
extern int qla24xx_walk_and_build_sglist(struct qla_hw_data *, srb_t *,
|
||||
uint32_t *, uint16_t, struct qla_tgt_cmd *);
|
||||
extern int qla24xx_walk_and_build_prot_sglist(struct qla_hw_data *, srb_t *,
|
||||
uint32_t *, uint16_t, struct qla_tgt_cmd *);
|
||||
|
||||
|
||||
/*
|
||||
* Global Function Prototypes in qla_mbx.c source file.
|
||||
*/
|
||||
extern int
|
||||
qla2x00_load_ram(scsi_qla_host_t *, dma_addr_t, uint32_t, uint32_t);
|
||||
|
||||
extern int
|
||||
qla2x00_dump_ram(scsi_qla_host_t *, dma_addr_t, uint32_t, uint32_t);
|
||||
|
||||
extern int
|
||||
qla2x00_execute_fw(scsi_qla_host_t *, uint32_t);
|
||||
|
||||
extern int
|
||||
qla2x00_get_fw_version(scsi_qla_host_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_get_fw_options(scsi_qla_host_t *, uint16_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_set_fw_options(scsi_qla_host_t *, uint16_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_mbx_reg_test(scsi_qla_host_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_verify_checksum(scsi_qla_host_t *, uint32_t);
|
||||
|
||||
extern int
|
||||
qla2x00_issue_iocb(scsi_qla_host_t *, void *, dma_addr_t, size_t);
|
||||
|
||||
extern int
|
||||
qla2x00_abort_command(srb_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_abort_target(struct fc_port *, uint64_t, int);
|
||||
|
||||
extern int
|
||||
qla2x00_lun_reset(struct fc_port *, uint64_t, int);
|
||||
|
||||
extern int
|
||||
qla2x00_get_adapter_id(scsi_qla_host_t *, uint16_t *, uint8_t *, uint8_t *,
|
||||
uint8_t *, uint16_t *, uint16_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_get_retry_cnt(scsi_qla_host_t *, uint8_t *, uint8_t *, uint16_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_init_firmware(scsi_qla_host_t *, uint16_t);
|
||||
|
||||
extern int
|
||||
qla2x00_get_node_name_list(scsi_qla_host_t *, void **, int *);
|
||||
|
||||
extern int
|
||||
qla2x00_get_port_database(scsi_qla_host_t *, fc_port_t *, uint8_t);
|
||||
|
||||
extern int
|
||||
qla2x00_get_firmware_state(scsi_qla_host_t *, uint16_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_get_port_name(scsi_qla_host_t *, uint16_t, uint8_t *, uint8_t);
|
||||
|
||||
extern int
|
||||
qla24xx_link_initialize(scsi_qla_host_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_lip_reset(scsi_qla_host_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_send_sns(scsi_qla_host_t *, dma_addr_t, uint16_t, size_t);
|
||||
|
||||
extern int
|
||||
qla2x00_login_fabric(scsi_qla_host_t *, uint16_t, uint8_t, uint8_t, uint8_t,
|
||||
uint16_t *, uint8_t);
|
||||
extern int
|
||||
qla24xx_login_fabric(scsi_qla_host_t *, uint16_t, uint8_t, uint8_t, uint8_t,
|
||||
uint16_t *, uint8_t);
|
||||
|
||||
extern int
|
||||
qla2x00_login_local_device(scsi_qla_host_t *, fc_port_t *, uint16_t *,
|
||||
uint8_t);
|
||||
|
||||
extern int
|
||||
qla2x00_fabric_logout(scsi_qla_host_t *, uint16_t, uint8_t, uint8_t, uint8_t);
|
||||
|
||||
extern int
|
||||
qla24xx_fabric_logout(scsi_qla_host_t *, uint16_t, uint8_t, uint8_t, uint8_t);
|
||||
|
||||
extern int
|
||||
qla2x00_full_login_lip(scsi_qla_host_t *ha);
|
||||
|
||||
extern int
|
||||
qla2x00_get_id_list(scsi_qla_host_t *, void *, dma_addr_t, uint16_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_get_resource_cnts(scsi_qla_host_t *, uint16_t *, uint16_t *,
|
||||
uint16_t *, uint16_t *, uint16_t *, uint16_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_get_fcal_position_map(scsi_qla_host_t *ha, char *pos_map);
|
||||
|
||||
extern int
|
||||
qla2x00_get_link_status(scsi_qla_host_t *, uint16_t, struct link_statistics *,
|
||||
dma_addr_t);
|
||||
|
||||
extern int
|
||||
qla24xx_get_isp_stats(scsi_qla_host_t *, struct link_statistics *,
|
||||
dma_addr_t);
|
||||
|
||||
extern int qla24xx_abort_command(srb_t *);
|
||||
extern int qla24xx_async_abort_command(srb_t *);
|
||||
extern int
|
||||
qla24xx_abort_target(struct fc_port *, uint64_t, int);
|
||||
extern int
|
||||
qla24xx_lun_reset(struct fc_port *, uint64_t, int);
|
||||
extern int
|
||||
qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *, unsigned int,
|
||||
uint64_t, enum nexus_wait_type);
|
||||
extern int
|
||||
qla2x00_system_error(scsi_qla_host_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_write_serdes_word(scsi_qla_host_t *, uint16_t, uint16_t);
|
||||
extern int
|
||||
qla2x00_read_serdes_word(scsi_qla_host_t *, uint16_t, uint16_t *);
|
||||
|
||||
extern int
|
||||
qla8044_write_serdes_word(scsi_qla_host_t *, uint32_t, uint32_t);
|
||||
extern int
|
||||
qla8044_read_serdes_word(scsi_qla_host_t *, uint32_t, uint32_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_set_serdes_params(scsi_qla_host_t *, uint16_t, uint16_t, uint16_t);
|
||||
|
||||
extern int
|
||||
qla2x00_stop_firmware(scsi_qla_host_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_enable_eft_trace(scsi_qla_host_t *, dma_addr_t, uint16_t);
|
||||
extern int
|
||||
qla2x00_disable_eft_trace(scsi_qla_host_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_enable_fce_trace(scsi_qla_host_t *, dma_addr_t, uint16_t , uint16_t *,
|
||||
uint32_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_disable_fce_trace(scsi_qla_host_t *, uint64_t *, uint64_t *);
|
||||
|
||||
extern int
|
||||
qla82xx_set_driver_version(scsi_qla_host_t *, char *);
|
||||
|
||||
extern int
|
||||
qla25xx_set_driver_version(scsi_qla_host_t *, char *);
|
||||
|
||||
extern int
|
||||
qla2x00_read_sfp(scsi_qla_host_t *, dma_addr_t, uint8_t *,
|
||||
uint16_t, uint16_t, uint16_t, uint16_t);
|
||||
|
||||
extern int
|
||||
qla2x00_write_sfp(scsi_qla_host_t *, dma_addr_t, uint8_t *,
|
||||
uint16_t, uint16_t, uint16_t, uint16_t);
|
||||
|
||||
extern int
|
||||
qla2x00_set_idma_speed(scsi_qla_host_t *, uint16_t, uint16_t, uint16_t *);
|
||||
|
||||
extern int qla84xx_verify_chip(struct scsi_qla_host *, uint16_t *);
|
||||
|
||||
extern int qla81xx_idc_ack(scsi_qla_host_t *, uint16_t *);
|
||||
|
||||
extern int
|
||||
qla81xx_fac_get_sector_size(scsi_qla_host_t *, uint32_t *);
|
||||
|
||||
extern int
|
||||
qla81xx_fac_do_write_enable(scsi_qla_host_t *, int);
|
||||
|
||||
extern int
|
||||
qla81xx_fac_erase_sector(scsi_qla_host_t *, uint32_t, uint32_t);
|
||||
|
||||
extern int
|
||||
qla2x00_get_xgmac_stats(scsi_qla_host_t *, dma_addr_t, uint16_t, uint16_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_get_dcbx_params(scsi_qla_host_t *, dma_addr_t, uint16_t);
|
||||
|
||||
extern int
|
||||
qla2x00_read_ram_word(scsi_qla_host_t *, uint32_t, uint32_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_write_ram_word(scsi_qla_host_t *, uint32_t, uint32_t);
|
||||
|
||||
extern int
|
||||
qla81xx_write_mpi_register(scsi_qla_host_t *, uint16_t *);
|
||||
extern int qla2x00_get_data_rate(scsi_qla_host_t *);
|
||||
extern int qla24xx_set_fcp_prio(scsi_qla_host_t *, uint16_t, uint16_t,
|
||||
uint16_t *);
|
||||
extern int
|
||||
qla81xx_get_port_config(scsi_qla_host_t *, uint16_t *);
|
||||
|
||||
extern int
|
||||
qla81xx_set_port_config(scsi_qla_host_t *, uint16_t *);
|
||||
|
||||
extern int
|
||||
qla2x00_port_logout(scsi_qla_host_t *, struct fc_port *);
|
||||
|
||||
extern int
|
||||
qla2x00_dump_mctp_data(scsi_qla_host_t *, dma_addr_t, uint32_t, uint32_t);
|
||||
|
||||
/*
|
||||
* Global Function Prototypes in qla_isr.c source file.
|
||||
*/
|
||||
extern irqreturn_t qla2100_intr_handler(int, void *);
|
||||
extern irqreturn_t qla2300_intr_handler(int, void *);
|
||||
extern irqreturn_t qla24xx_intr_handler(int, void *);
|
||||
extern void qla2x00_process_response_queue(struct rsp_que *);
|
||||
extern void
|
||||
qla24xx_process_response_queue(struct scsi_qla_host *, struct rsp_que *);
|
||||
extern int qla2x00_request_irqs(struct qla_hw_data *, struct rsp_que *);
|
||||
extern void qla2x00_free_irqs(scsi_qla_host_t *);
|
||||
|
||||
extern int qla2x00_get_data_rate(scsi_qla_host_t *);
|
||||
extern const char *qla2x00_get_link_speed_str(struct qla_hw_data *, uint16_t);
|
||||
extern srb_t *
|
||||
qla2x00_get_sp_from_handle(scsi_qla_host_t *, const char *, struct req_que *,
|
||||
void *);
|
||||
extern void
|
||||
qla2x00_process_completed_request(struct scsi_qla_host *, struct req_que *,
|
||||
uint32_t);
|
||||
|
||||
/*
|
||||
* Global Function Prototypes in qla_sup.c source file.
|
||||
*/
|
||||
extern void qla2x00_release_nvram_protection(scsi_qla_host_t *);
|
||||
extern uint32_t *qla24xx_read_flash_data(scsi_qla_host_t *, uint32_t *,
|
||||
uint32_t, uint32_t);
|
||||
extern uint8_t *qla2x00_read_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
|
||||
uint32_t);
|
||||
extern uint8_t *qla24xx_read_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
|
||||
uint32_t);
|
||||
extern int qla2x00_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
|
||||
uint32_t);
|
||||
extern int qla24xx_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
|
||||
uint32_t);
|
||||
extern uint8_t *qla25xx_read_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
|
||||
uint32_t);
|
||||
extern int qla25xx_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
|
||||
uint32_t);
|
||||
extern int qla2x00_is_a_vp_did(scsi_qla_host_t *, uint32_t);
|
||||
bool qla2x00_check_reg32_for_disconnect(scsi_qla_host_t *, uint32_t);
|
||||
bool qla2x00_check_reg16_for_disconnect(scsi_qla_host_t *, uint16_t);
|
||||
|
||||
extern int qla2x00_beacon_on(struct scsi_qla_host *);
|
||||
extern int qla2x00_beacon_off(struct scsi_qla_host *);
|
||||
extern void qla2x00_beacon_blink(struct scsi_qla_host *);
|
||||
extern int qla24xx_beacon_on(struct scsi_qla_host *);
|
||||
extern int qla24xx_beacon_off(struct scsi_qla_host *);
|
||||
extern void qla24xx_beacon_blink(struct scsi_qla_host *);
|
||||
extern void qla83xx_beacon_blink(struct scsi_qla_host *);
|
||||
extern int qla82xx_beacon_on(struct scsi_qla_host *);
|
||||
extern int qla82xx_beacon_off(struct scsi_qla_host *);
|
||||
extern int qla83xx_wr_reg(scsi_qla_host_t *, uint32_t, uint32_t);
|
||||
extern int qla83xx_rd_reg(scsi_qla_host_t *, uint32_t, uint32_t *);
|
||||
extern int qla83xx_restart_nic_firmware(scsi_qla_host_t *);
|
||||
extern int qla83xx_access_control(scsi_qla_host_t *, uint16_t, uint32_t,
|
||||
uint32_t, uint16_t *);
|
||||
|
||||
extern uint8_t *qla2x00_read_optrom_data(struct scsi_qla_host *, uint8_t *,
|
||||
uint32_t, uint32_t);
|
||||
extern int qla2x00_write_optrom_data(struct scsi_qla_host *, uint8_t *,
|
||||
uint32_t, uint32_t);
|
||||
extern uint8_t *qla24xx_read_optrom_data(struct scsi_qla_host *, uint8_t *,
|
||||
uint32_t, uint32_t);
|
||||
extern int qla24xx_write_optrom_data(struct scsi_qla_host *, uint8_t *,
|
||||
uint32_t, uint32_t);
|
||||
extern uint8_t *qla25xx_read_optrom_data(struct scsi_qla_host *, uint8_t *,
|
||||
uint32_t, uint32_t);
|
||||
extern uint8_t *qla8044_read_optrom_data(struct scsi_qla_host *,
|
||||
uint8_t *, uint32_t, uint32_t);
|
||||
extern void qla8044_watchdog(struct scsi_qla_host *vha);
|
||||
|
||||
extern int qla2x00_get_flash_version(scsi_qla_host_t *, void *);
|
||||
extern int qla24xx_get_flash_version(scsi_qla_host_t *, void *);
|
||||
extern int qla82xx_get_flash_version(scsi_qla_host_t *, void *);
|
||||
|
||||
extern int qla2xxx_get_flash_info(scsi_qla_host_t *);
|
||||
extern int qla2xxx_get_vpd_field(scsi_qla_host_t *, char *, char *, size_t);
|
||||
|
||||
extern void qla2xxx_flash_npiv_conf(scsi_qla_host_t *);
|
||||
extern int qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *);
|
||||
|
||||
/*
|
||||
* Global Function Prototypes in qla_dbg.c source file.
|
||||
*/
|
||||
extern void qla2100_fw_dump(scsi_qla_host_t *, int);
|
||||
extern void qla2300_fw_dump(scsi_qla_host_t *, int);
|
||||
extern void qla24xx_fw_dump(scsi_qla_host_t *, int);
|
||||
extern void qla25xx_fw_dump(scsi_qla_host_t *, int);
|
||||
extern void qla81xx_fw_dump(scsi_qla_host_t *, int);
|
||||
extern void qla82xx_fw_dump(scsi_qla_host_t *, int);
|
||||
extern void qla8044_fw_dump(scsi_qla_host_t *, int);
|
||||
|
||||
extern void qla27xx_fwdump(scsi_qla_host_t *, int);
|
||||
extern ulong qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *);
|
||||
extern int qla27xx_fwdt_template_valid(void *);
|
||||
extern ulong qla27xx_fwdt_template_size(void *);
|
||||
extern const void *qla27xx_fwdt_template_default(void);
|
||||
extern ulong qla27xx_fwdt_template_default_size(void);
|
||||
|
||||
extern void qla2x00_dump_regs(scsi_qla_host_t *);
|
||||
extern void qla2x00_dump_buffer(uint8_t *, uint32_t);
|
||||
extern void qla2x00_dump_buffer_zipped(uint8_t *, uint32_t);
|
||||
extern void ql_dump_regs(uint32_t, scsi_qla_host_t *, int32_t);
|
||||
extern void ql_dump_buffer(uint32_t, scsi_qla_host_t *, int32_t,
|
||||
uint8_t *, uint32_t);
|
||||
extern void qla2xxx_dump_post_process(scsi_qla_host_t *, int);
|
||||
|
||||
/*
|
||||
* Global Function Prototypes in qla_gs.c source file.
|
||||
*/
|
||||
extern void *qla2x00_prep_ms_iocb(scsi_qla_host_t *, uint32_t, uint32_t);
|
||||
extern void *qla24xx_prep_ms_iocb(scsi_qla_host_t *, uint32_t, uint32_t);
|
||||
extern int qla2x00_ga_nxt(scsi_qla_host_t *, fc_port_t *);
|
||||
extern int qla2x00_gid_pt(scsi_qla_host_t *, sw_info_t *);
|
||||
extern int qla2x00_gpn_id(scsi_qla_host_t *, sw_info_t *);
|
||||
extern int qla2x00_gnn_id(scsi_qla_host_t *, sw_info_t *);
|
||||
extern void qla2x00_gff_id(scsi_qla_host_t *, sw_info_t *);
|
||||
extern int qla2x00_rft_id(scsi_qla_host_t *);
|
||||
extern int qla2x00_rff_id(scsi_qla_host_t *);
|
||||
extern int qla2x00_rnn_id(scsi_qla_host_t *);
|
||||
extern int qla2x00_rsnn_nn(scsi_qla_host_t *);
|
||||
extern void *qla2x00_prep_ms_fdmi_iocb(scsi_qla_host_t *, uint32_t, uint32_t);
|
||||
extern void *qla24xx_prep_ms_fdmi_iocb(scsi_qla_host_t *, uint32_t, uint32_t);
|
||||
extern int qla2x00_fdmi_register(scsi_qla_host_t *);
|
||||
extern int qla2x00_gfpn_id(scsi_qla_host_t *, sw_info_t *);
|
||||
extern int qla2x00_gpsc(scsi_qla_host_t *, sw_info_t *);
|
||||
extern void qla2x00_get_sym_node_name(scsi_qla_host_t *, uint8_t *, size_t);
|
||||
|
||||
/*
|
||||
* Global Function Prototypes in qla_attr.c source file.
|
||||
*/
|
||||
struct device_attribute;
|
||||
extern struct device_attribute *qla2x00_host_attrs[];
|
||||
struct fc_function_template;
|
||||
extern struct fc_function_template qla2xxx_transport_functions;
|
||||
extern struct fc_function_template qla2xxx_transport_vport_functions;
|
||||
extern void qla2x00_alloc_sysfs_attr(scsi_qla_host_t *);
|
||||
extern void qla2x00_free_sysfs_attr(scsi_qla_host_t *, bool);
|
||||
extern void qla2x00_init_host_attr(scsi_qla_host_t *);
|
||||
extern void qla2x00_alloc_sysfs_attr(scsi_qla_host_t *);
|
||||
extern int qla2x00_loopback_test(scsi_qla_host_t *, struct msg_echo_lb *, uint16_t *);
|
||||
extern int qla2x00_echo_test(scsi_qla_host_t *,
|
||||
struct msg_echo_lb *, uint16_t *);
|
||||
extern int qla24xx_update_all_fcp_prio(scsi_qla_host_t *);
|
||||
extern int qla24xx_fcp_prio_cfg_valid(scsi_qla_host_t *,
|
||||
struct qla_fcp_prio_cfg *, uint8_t);
|
||||
|
||||
/*
|
||||
* Global Function Prototypes in qla_dfs.c source file.
|
||||
*/
|
||||
extern int qla2x00_dfs_setup(scsi_qla_host_t *);
|
||||
extern int qla2x00_dfs_remove(scsi_qla_host_t *);
|
||||
|
||||
/* Globa function prototypes for multi-q */
|
||||
extern int qla25xx_request_irq(struct rsp_que *);
|
||||
extern int qla25xx_init_req_que(struct scsi_qla_host *, struct req_que *);
|
||||
extern int qla25xx_init_rsp_que(struct scsi_qla_host *, struct rsp_que *);
|
||||
extern int qla25xx_create_req_que(struct qla_hw_data *, uint16_t, uint8_t,
|
||||
uint16_t, int, uint8_t);
|
||||
extern int qla25xx_create_rsp_que(struct qla_hw_data *, uint16_t, uint8_t,
|
||||
uint16_t, int);
|
||||
extern void qla2x00_init_response_q_entries(struct rsp_que *);
|
||||
extern int qla25xx_delete_req_que(struct scsi_qla_host *, struct req_que *);
|
||||
extern int qla25xx_delete_queues(struct scsi_qla_host *);
|
||||
extern uint16_t qla24xx_rd_req_reg(struct qla_hw_data *, uint16_t);
|
||||
extern uint16_t qla25xx_rd_req_reg(struct qla_hw_data *, uint16_t);
|
||||
extern void qla24xx_wrt_req_reg(struct qla_hw_data *, uint16_t, uint16_t);
|
||||
extern void qla25xx_wrt_req_reg(struct qla_hw_data *, uint16_t, uint16_t);
|
||||
extern void qla25xx_wrt_rsp_reg(struct qla_hw_data *, uint16_t, uint16_t);
|
||||
extern void qla24xx_wrt_rsp_reg(struct qla_hw_data *, uint16_t, uint16_t);
|
||||
|
||||
/* qlafx00 related functions */
|
||||
extern int qlafx00_pci_config(struct scsi_qla_host *);
|
||||
extern int qlafx00_initialize_adapter(struct scsi_qla_host *);
|
||||
extern void qlafx00_soft_reset(scsi_qla_host_t *);
|
||||
extern int qlafx00_chip_diag(scsi_qla_host_t *);
|
||||
extern void qlafx00_config_rings(struct scsi_qla_host *);
|
||||
extern char *qlafx00_pci_info_str(struct scsi_qla_host *, char *);
|
||||
extern char *qlafx00_fw_version_str(struct scsi_qla_host *, char *, size_t);
|
||||
extern irqreturn_t qlafx00_intr_handler(int, void *);
|
||||
extern void qlafx00_enable_intrs(struct qla_hw_data *);
|
||||
extern void qlafx00_disable_intrs(struct qla_hw_data *);
|
||||
extern int qlafx00_abort_target(fc_port_t *, uint64_t, int);
|
||||
extern int qlafx00_lun_reset(fc_port_t *, uint64_t, int);
|
||||
extern int qlafx00_start_scsi(srb_t *);
|
||||
extern int qlafx00_abort_isp(scsi_qla_host_t *);
|
||||
extern int qlafx00_iospace_config(struct qla_hw_data *);
|
||||
extern int qlafx00_init_firmware(scsi_qla_host_t *, uint16_t);
|
||||
extern int qlafx00_driver_shutdown(scsi_qla_host_t *, int);
|
||||
extern int qlafx00_fw_ready(scsi_qla_host_t *);
|
||||
extern int qlafx00_configure_devices(scsi_qla_host_t *);
|
||||
extern int qlafx00_reset_initialize(scsi_qla_host_t *);
|
||||
extern int qlafx00_fx_disc(scsi_qla_host_t *, fc_port_t *, uint16_t);
|
||||
extern int qlafx00_process_aen(struct scsi_qla_host *, struct qla_work_evt *);
|
||||
extern int qlafx00_post_aenfx_work(struct scsi_qla_host *, uint32_t,
|
||||
uint32_t *, int);
|
||||
extern uint32_t qlafx00_fw_state_show(struct device *,
|
||||
struct device_attribute *, char *);
|
||||
extern void qlafx00_get_host_speed(struct Scsi_Host *);
|
||||
extern void qlafx00_init_response_q_entries(struct rsp_que *);
|
||||
|
||||
extern void qlafx00_tm_iocb(srb_t *, struct tsk_mgmt_entry_fx00 *);
|
||||
extern void qlafx00_abort_iocb(srb_t *, struct abort_iocb_entry_fx00 *);
|
||||
extern void qlafx00_fxdisc_iocb(srb_t *, struct fxdisc_entry_fx00 *);
|
||||
extern void qlafx00_timer_routine(scsi_qla_host_t *);
|
||||
extern int qlafx00_rescan_isp(scsi_qla_host_t *);
|
||||
extern int qlafx00_loop_reset(scsi_qla_host_t *vha);
|
||||
|
||||
/* qla82xx related functions */
|
||||
|
||||
/* PCI related functions */
|
||||
extern int qla82xx_pci_config(struct scsi_qla_host *);
|
||||
extern int qla82xx_pci_mem_read_2M(struct qla_hw_data *, u64, void *, int);
|
||||
extern int qla82xx_pci_region_offset(struct pci_dev *, int);
|
||||
extern int qla82xx_iospace_config(struct qla_hw_data *);
|
||||
|
||||
/* Initialization related functions */
|
||||
extern void qla82xx_reset_chip(struct scsi_qla_host *);
|
||||
extern void qla82xx_config_rings(struct scsi_qla_host *);
|
||||
extern void qla82xx_watchdog(scsi_qla_host_t *);
|
||||
extern int qla82xx_start_firmware(scsi_qla_host_t *);
|
||||
|
||||
/* Firmware and flash related functions */
|
||||
extern int qla82xx_load_risc(scsi_qla_host_t *, uint32_t *);
|
||||
extern uint8_t *qla82xx_read_optrom_data(struct scsi_qla_host *, uint8_t *,
|
||||
uint32_t, uint32_t);
|
||||
extern int qla82xx_write_optrom_data(struct scsi_qla_host *, uint8_t *,
|
||||
uint32_t, uint32_t);
|
||||
|
||||
/* Mailbox related functions */
|
||||
extern int qla82xx_abort_isp(scsi_qla_host_t *);
|
||||
extern int qla82xx_restart_isp(scsi_qla_host_t *);
|
||||
|
||||
/* IOCB related functions */
|
||||
extern int qla82xx_start_scsi(srb_t *);
|
||||
extern void qla2x00_sp_free(void *, void *);
|
||||
extern void qla2x00_sp_timeout(unsigned long);
|
||||
extern void qla2x00_bsg_job_done(void *, void *, int);
|
||||
extern void qla2x00_bsg_sp_free(void *, void *);
|
||||
extern void qla2x00_start_iocbs(struct scsi_qla_host *, struct req_que *);
|
||||
|
||||
/* Interrupt related */
|
||||
extern irqreturn_t qla82xx_intr_handler(int, void *);
|
||||
extern irqreturn_t qla82xx_msi_handler(int, void *);
|
||||
extern irqreturn_t qla82xx_msix_default(int, void *);
|
||||
extern irqreturn_t qla82xx_msix_rsp_q(int, void *);
|
||||
extern void qla82xx_enable_intrs(struct qla_hw_data *);
|
||||
extern void qla82xx_disable_intrs(struct qla_hw_data *);
|
||||
extern void qla82xx_poll(int, void *);
|
||||
extern void qla82xx_init_flags(struct qla_hw_data *);
|
||||
|
||||
/* ISP 8021 hardware related */
|
||||
extern void qla82xx_set_drv_active(scsi_qla_host_t *);
|
||||
extern int qla82xx_wr_32(struct qla_hw_data *, ulong, u32);
|
||||
extern int qla82xx_rd_32(struct qla_hw_data *, ulong);
|
||||
extern int qla82xx_rdmem(struct qla_hw_data *, u64, void *, int);
|
||||
extern int qla82xx_wrmem(struct qla_hw_data *, u64, void *, int);
|
||||
|
||||
/* ISP 8021 IDC */
|
||||
extern void qla82xx_clear_drv_active(struct qla_hw_data *);
|
||||
extern uint32_t qla82xx_wait_for_state_change(scsi_qla_host_t *, uint32_t);
|
||||
extern int qla82xx_idc_lock(struct qla_hw_data *);
|
||||
extern void qla82xx_idc_unlock(struct qla_hw_data *);
|
||||
extern int qla82xx_device_state_handler(scsi_qla_host_t *);
|
||||
extern void qla8xxx_dev_failed_handler(scsi_qla_host_t *);
|
||||
extern void qla82xx_clear_qsnt_ready(scsi_qla_host_t *);
|
||||
|
||||
extern void qla2x00_set_model_info(scsi_qla_host_t *, uint8_t *,
|
||||
size_t, char *);
|
||||
extern int qla82xx_mbx_intr_enable(scsi_qla_host_t *);
|
||||
extern int qla82xx_mbx_intr_disable(scsi_qla_host_t *);
|
||||
extern void qla82xx_start_iocbs(scsi_qla_host_t *);
|
||||
extern int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *);
|
||||
extern int qla82xx_check_md_needed(scsi_qla_host_t *);
|
||||
extern void qla82xx_chip_reset_cleanup(scsi_qla_host_t *);
|
||||
extern int qla81xx_set_led_config(scsi_qla_host_t *, uint16_t *);
|
||||
extern int qla81xx_get_led_config(scsi_qla_host_t *, uint16_t *);
|
||||
extern int qla82xx_mbx_beacon_ctl(scsi_qla_host_t *, int);
|
||||
extern char *qdev_state(uint32_t);
|
||||
extern void qla82xx_clear_pending_mbx(scsi_qla_host_t *);
|
||||
extern int qla82xx_read_temperature(scsi_qla_host_t *);
|
||||
extern int qla8044_read_temperature(scsi_qla_host_t *);
|
||||
|
||||
/* BSG related functions */
|
||||
extern int qla24xx_bsg_request(struct fc_bsg_job *);
|
||||
extern int qla24xx_bsg_timeout(struct fc_bsg_job *);
|
||||
extern int qla84xx_reset_chip(scsi_qla_host_t *, uint16_t);
|
||||
extern int qla2x00_issue_iocb_timeout(scsi_qla_host_t *, void *,
|
||||
dma_addr_t, size_t, uint32_t);
|
||||
extern int qla2x00_get_idma_speed(scsi_qla_host_t *, uint16_t,
|
||||
uint16_t *, uint16_t *);
|
||||
|
||||
/* 83xx related functions */
|
||||
extern void qla83xx_fw_dump(scsi_qla_host_t *, int);
|
||||
|
||||
/* Minidump related functions */
|
||||
extern int qla82xx_md_get_template_size(scsi_qla_host_t *);
|
||||
extern int qla82xx_md_get_template(scsi_qla_host_t *);
|
||||
extern int qla82xx_md_alloc(scsi_qla_host_t *);
|
||||
extern void qla82xx_md_free(scsi_qla_host_t *);
|
||||
extern int qla82xx_md_collect(scsi_qla_host_t *);
|
||||
extern void qla82xx_md_prep(scsi_qla_host_t *);
|
||||
extern void qla82xx_set_reset_owner(scsi_qla_host_t *);
|
||||
extern int qla82xx_validate_template_chksum(scsi_qla_host_t *vha);
|
||||
|
||||
/* Function declarations for ISP8044 */
|
||||
extern int qla8044_idc_lock(struct qla_hw_data *ha);
|
||||
extern void qla8044_idc_unlock(struct qla_hw_data *ha);
|
||||
extern uint32_t qla8044_rd_reg(struct qla_hw_data *ha, ulong addr);
|
||||
extern void qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val);
|
||||
extern void qla8044_read_reset_template(struct scsi_qla_host *ha);
|
||||
extern void qla8044_set_idc_dontreset(struct scsi_qla_host *ha);
|
||||
extern int qla8044_rd_direct(struct scsi_qla_host *vha, const uint32_t crb_reg);
|
||||
extern void qla8044_wr_direct(struct scsi_qla_host *vha,
|
||||
const uint32_t crb_reg, const uint32_t value);
|
||||
extern inline void qla8044_set_qsnt_ready(struct scsi_qla_host *vha);
|
||||
extern inline void qla8044_need_reset_handler(struct scsi_qla_host *vha);
|
||||
extern int qla8044_device_state_handler(struct scsi_qla_host *vha);
|
||||
extern void qla8044_clear_qsnt_ready(struct scsi_qla_host *vha);
|
||||
extern void qla8044_clear_drv_active(struct qla_hw_data *);
|
||||
void qla8044_get_minidump(struct scsi_qla_host *vha);
|
||||
int qla8044_collect_md_data(struct scsi_qla_host *vha);
|
||||
extern int qla8044_md_get_template(scsi_qla_host_t *);
|
||||
extern int qla8044_write_optrom_data(struct scsi_qla_host *, uint8_t *,
|
||||
uint32_t, uint32_t);
|
||||
extern irqreturn_t qla8044_intr_handler(int, void *);
|
||||
extern void qla82xx_mbx_completion(scsi_qla_host_t *, uint16_t);
|
||||
extern int qla8044_abort_isp(scsi_qla_host_t *);
|
||||
extern int qla8044_check_fw_alive(struct scsi_qla_host *);
|
||||
|
||||
extern void qlt_host_reset_handler(struct qla_hw_data *ha);
|
||||
#endif /* _QLA_GBL_H */
|
||||
2694
drivers/scsi/qla2xxx/qla_gs.c
Normal file
2694
drivers/scsi/qla2xxx/qla_gs.c
Normal file
File diff suppressed because it is too large
Load diff
6424
drivers/scsi/qla2xxx/qla_init.c
Normal file
6424
drivers/scsi/qla2xxx/qla_init.c
Normal file
File diff suppressed because it is too large
Load diff
289
drivers/scsi/qla2xxx/qla_inline.h
Normal file
289
drivers/scsi/qla2xxx/qla_inline.h
Normal file
|
|
@ -0,0 +1,289 @@
|
|||
/*
|
||||
* QLogic Fibre Channel HBA Driver
|
||||
* Copyright (c) 2003-2014 QLogic Corporation
|
||||
*
|
||||
* See LICENSE.qla2xxx for copyright and licensing details.
|
||||
*/
|
||||
|
||||
#include "qla_target.h"
|
||||
/**
|
||||
* qla24xx_calc_iocbs() - Determine number of Command Type 3 and
|
||||
* Continuation Type 1 IOCBs to allocate.
|
||||
*
|
||||
* @dsds: number of data segment decriptors needed
|
||||
*
|
||||
* Returns the number of IOCB entries needed to store @dsds.
|
||||
*/
|
||||
static inline uint16_t
|
||||
qla24xx_calc_iocbs(scsi_qla_host_t *vha, uint16_t dsds)
|
||||
{
|
||||
uint16_t iocbs;
|
||||
|
||||
iocbs = 1;
|
||||
if (dsds > 1) {
|
||||
iocbs += (dsds - 1) / 5;
|
||||
if ((dsds - 1) % 5)
|
||||
iocbs++;
|
||||
}
|
||||
return iocbs;
|
||||
}
|
||||
|
||||
/*
|
||||
* qla2x00_debounce_register
|
||||
* Debounce register.
|
||||
*
|
||||
* Input:
|
||||
* port = register address.
|
||||
*
|
||||
* Returns:
|
||||
* register value.
|
||||
*/
|
||||
static __inline__ uint16_t
|
||||
qla2x00_debounce_register(volatile uint16_t __iomem *addr)
|
||||
{
|
||||
volatile uint16_t first;
|
||||
volatile uint16_t second;
|
||||
|
||||
do {
|
||||
first = RD_REG_WORD(addr);
|
||||
barrier();
|
||||
cpu_relax();
|
||||
second = RD_REG_WORD(addr);
|
||||
} while (first != second);
|
||||
|
||||
return (first);
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla2x00_poll(struct rsp_que *rsp)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct qla_hw_data *ha = rsp->hw;
|
||||
local_irq_save(flags);
|
||||
if (IS_P3P_TYPE(ha))
|
||||
qla82xx_poll(0, rsp);
|
||||
else
|
||||
ha->isp_ops->intr_handler(0, rsp);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static inline uint8_t *
|
||||
host_to_fcp_swap(uint8_t *fcp, uint32_t bsize)
|
||||
{
|
||||
uint32_t *ifcp = (uint32_t *) fcp;
|
||||
uint32_t *ofcp = (uint32_t *) fcp;
|
||||
uint32_t iter = bsize >> 2;
|
||||
|
||||
for (; iter ; iter--)
|
||||
*ofcp++ = swab32(*ifcp++);
|
||||
|
||||
return fcp;
|
||||
}
|
||||
|
||||
static inline void
|
||||
host_to_adap(uint8_t *src, uint8_t *dst, uint32_t bsize)
|
||||
{
|
||||
uint32_t *isrc = (uint32_t *) src;
|
||||
__le32 *odest = (__le32 *) dst;
|
||||
uint32_t iter = bsize >> 2;
|
||||
|
||||
for (; iter ; iter--)
|
||||
*odest++ = cpu_to_le32(*isrc++);
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (IS_FWI2_CAPABLE(ha))
|
||||
return;
|
||||
|
||||
for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
|
||||
set_bit(i, ha->loop_id_map);
|
||||
set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
|
||||
set_bit(BROADCAST, ha->loop_id_map);
|
||||
}
|
||||
|
||||
static inline int
|
||||
qla2x00_is_reserved_id(scsi_qla_host_t *vha, uint16_t loop_id)
|
||||
{
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
if (IS_FWI2_CAPABLE(ha))
|
||||
return (loop_id > NPH_LAST_HANDLE);
|
||||
|
||||
return ((loop_id > ha->max_loop_id && loop_id < SNS_FIRST_LOOP_ID) ||
|
||||
loop_id == MANAGEMENT_SERVER || loop_id == BROADCAST);
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla2x00_clear_loop_id(fc_port_t *fcport) {
|
||||
struct qla_hw_data *ha = fcport->vha->hw;
|
||||
|
||||
if (fcport->loop_id == FC_NO_LOOP_ID ||
|
||||
qla2x00_is_reserved_id(fcport->vha, fcport->loop_id))
|
||||
return;
|
||||
|
||||
clear_bit(fcport->loop_id, ha->loop_id_map);
|
||||
fcport->loop_id = FC_NO_LOOP_ID;
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla2x00_clean_dsd_pool(struct qla_hw_data *ha, srb_t *sp,
|
||||
struct qla_tgt_cmd *tc)
|
||||
{
|
||||
struct dsd_dma *dsd_ptr, *tdsd_ptr;
|
||||
struct crc_context *ctx;
|
||||
|
||||
if (sp)
|
||||
ctx = (struct crc_context *)GET_CMD_CTX_SP(sp);
|
||||
else if (tc)
|
||||
ctx = (struct crc_context *)tc->ctx;
|
||||
else {
|
||||
BUG();
|
||||
return;
|
||||
}
|
||||
|
||||
/* clean up allocated prev pool */
|
||||
list_for_each_entry_safe(dsd_ptr, tdsd_ptr,
|
||||
&ctx->dsd_list, list) {
|
||||
dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr,
|
||||
dsd_ptr->dsd_list_dma);
|
||||
list_del(&dsd_ptr->list);
|
||||
kfree(dsd_ptr);
|
||||
}
|
||||
INIT_LIST_HEAD(&ctx->dsd_list);
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla2x00_set_fcport_state(fc_port_t *fcport, int state)
|
||||
{
|
||||
int old_state;
|
||||
|
||||
old_state = atomic_read(&fcport->state);
|
||||
atomic_set(&fcport->state, state);
|
||||
|
||||
/* Don't print state transitions during initial allocation of fcport */
|
||||
if (old_state && old_state != state) {
|
||||
ql_dbg(ql_dbg_disc, fcport->vha, 0x207d,
|
||||
"FCPort state transitioned from %s to %s - "
|
||||
"portid=%02x%02x%02x.\n",
|
||||
port_state_str[old_state], port_state_str[state],
|
||||
fcport->d_id.b.domain, fcport->d_id.b.area,
|
||||
fcport->d_id.b.al_pa);
|
||||
}
|
||||
}
|
||||
|
||||
static inline int
|
||||
qla2x00_hba_err_chk_enabled(srb_t *sp)
|
||||
{
|
||||
/*
|
||||
* Uncomment when corresponding SCSI changes are done.
|
||||
*
|
||||
if (!sp->cmd->prot_chk)
|
||||
return 0;
|
||||
*
|
||||
*/
|
||||
switch (scsi_get_prot_op(GET_CMD_SP(sp))) {
|
||||
case SCSI_PROT_READ_STRIP:
|
||||
case SCSI_PROT_WRITE_INSERT:
|
||||
if (ql2xenablehba_err_chk >= 1)
|
||||
return 1;
|
||||
break;
|
||||
case SCSI_PROT_READ_PASS:
|
||||
case SCSI_PROT_WRITE_PASS:
|
||||
if (ql2xenablehba_err_chk >= 2)
|
||||
return 1;
|
||||
break;
|
||||
case SCSI_PROT_READ_INSERT:
|
||||
case SCSI_PROT_WRITE_STRIP:
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
qla2x00_reset_active(scsi_qla_host_t *vha)
|
||||
{
|
||||
scsi_qla_host_t *base_vha = pci_get_drvdata(vha->hw->pdev);
|
||||
|
||||
/* Test appropriate base-vha and vha flags. */
|
||||
return test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) ||
|
||||
test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
|
||||
test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
|
||||
test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
|
||||
test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
|
||||
}
|
||||
|
||||
static inline srb_t *
|
||||
qla2x00_get_sp(scsi_qla_host_t *vha, fc_port_t *fcport, gfp_t flag)
|
||||
{
|
||||
srb_t *sp = NULL;
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
uint8_t bail;
|
||||
|
||||
QLA_VHA_MARK_BUSY(vha, bail);
|
||||
if (unlikely(bail))
|
||||
return NULL;
|
||||
|
||||
sp = mempool_alloc(ha->srb_mempool, flag);
|
||||
if (!sp)
|
||||
goto done;
|
||||
|
||||
memset(sp, 0, sizeof(*sp));
|
||||
sp->fcport = fcport;
|
||||
sp->iocbs = 1;
|
||||
done:
|
||||
if (!sp)
|
||||
QLA_VHA_MARK_NOT_BUSY(vha);
|
||||
return sp;
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla2x00_rel_sp(scsi_qla_host_t *vha, srb_t *sp)
|
||||
{
|
||||
mempool_free(sp, vha->hw->srb_mempool);
|
||||
QLA_VHA_MARK_NOT_BUSY(vha);
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla2x00_init_timer(srb_t *sp, unsigned long tmo)
|
||||
{
|
||||
init_timer(&sp->u.iocb_cmd.timer);
|
||||
sp->u.iocb_cmd.timer.expires = jiffies + tmo * HZ;
|
||||
sp->u.iocb_cmd.timer.data = (unsigned long)sp;
|
||||
sp->u.iocb_cmd.timer.function = qla2x00_sp_timeout;
|
||||
add_timer(&sp->u.iocb_cmd.timer);
|
||||
sp->free = qla2x00_sp_free;
|
||||
if ((IS_QLAFX00(sp->fcport->vha->hw)) &&
|
||||
(sp->type == SRB_FXIOCB_DCMD))
|
||||
init_completion(&sp->u.iocb_cmd.u.fxiocb.fxiocb_comp);
|
||||
}
|
||||
|
||||
static inline int
|
||||
qla2x00_gid_list_size(struct qla_hw_data *ha)
|
||||
{
|
||||
if (IS_QLAFX00(ha))
|
||||
return sizeof(uint32_t) * 32;
|
||||
else
|
||||
return sizeof(struct gid_list_info) * ha->max_fibre_devices;
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla2x00_handle_mbx_completion(struct qla_hw_data *ha, int status)
|
||||
{
|
||||
if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
|
||||
(status & MBX_INTERRUPT) && ha->flags.mbox_int) {
|
||||
set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
|
||||
clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
|
||||
complete(&ha->mbx_intr_comp);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla2x00_set_retry_delay_timestamp(fc_port_t *fcport, uint16_t retry_delay)
|
||||
{
|
||||
if (retry_delay)
|
||||
fcport->retry_delay_timestamp = jiffies +
|
||||
(retry_delay * HZ / 10);
|
||||
}
|
||||
2943
drivers/scsi/qla2xxx/qla_iocb.c
Normal file
2943
drivers/scsi/qla2xxx/qla_iocb.c
Normal file
File diff suppressed because it is too large
Load diff
3199
drivers/scsi/qla2xxx/qla_isr.c
Normal file
3199
drivers/scsi/qla2xxx/qla_isr.c
Normal file
File diff suppressed because it is too large
Load diff
5450
drivers/scsi/qla2xxx/qla_mbx.c
Normal file
5450
drivers/scsi/qla2xxx/qla_mbx.c
Normal file
File diff suppressed because it is too large
Load diff
853
drivers/scsi/qla2xxx/qla_mid.c
Normal file
853
drivers/scsi/qla2xxx/qla_mid.c
Normal file
|
|
@ -0,0 +1,853 @@
|
|||
/*
|
||||
* QLogic Fibre Channel HBA Driver
|
||||
* Copyright (c) 2003-2014 QLogic Corporation
|
||||
*
|
||||
* See LICENSE.qla2xxx for copyright and licensing details.
|
||||
*/
|
||||
#include "qla_def.h"
|
||||
#include "qla_gbl.h"
|
||||
#include "qla_target.h"
|
||||
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
#include <scsi/scsi_tcq.h>
|
||||
#include <scsi/scsicam.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
void
|
||||
qla2x00_vp_stop_timer(scsi_qla_host_t *vha)
|
||||
{
|
||||
if (vha->vp_idx && vha->timer_active) {
|
||||
del_timer_sync(&vha->timer);
|
||||
vha->timer_active = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
qla24xx_allocate_vp_id(scsi_qla_host_t *vha)
|
||||
{
|
||||
uint32_t vp_id;
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
unsigned long flags;
|
||||
|
||||
/* Find an empty slot and assign an vp_id */
|
||||
mutex_lock(&ha->vport_lock);
|
||||
vp_id = find_first_zero_bit(ha->vp_idx_map, ha->max_npiv_vports + 1);
|
||||
if (vp_id > ha->max_npiv_vports) {
|
||||
ql_dbg(ql_dbg_vport, vha, 0xa000,
|
||||
"vp_id %d is bigger than max-supported %d.\n",
|
||||
vp_id, ha->max_npiv_vports);
|
||||
mutex_unlock(&ha->vport_lock);
|
||||
return vp_id;
|
||||
}
|
||||
|
||||
set_bit(vp_id, ha->vp_idx_map);
|
||||
ha->num_vhosts++;
|
||||
vha->vp_idx = vp_id;
|
||||
|
||||
spin_lock_irqsave(&ha->vport_slock, flags);
|
||||
list_add_tail(&vha->list, &ha->vp_list);
|
||||
|
||||
qlt_update_vp_map(vha, SET_VP_IDX);
|
||||
|
||||
spin_unlock_irqrestore(&ha->vport_slock, flags);
|
||||
|
||||
mutex_unlock(&ha->vport_lock);
|
||||
return vp_id;
|
||||
}
|
||||
|
||||
void
|
||||
qla24xx_deallocate_vp_id(scsi_qla_host_t *vha)
|
||||
{
|
||||
uint16_t vp_id;
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
unsigned long flags = 0;
|
||||
|
||||
mutex_lock(&ha->vport_lock);
|
||||
/*
|
||||
* Wait for all pending activities to finish before removing vport from
|
||||
* the list.
|
||||
* Lock needs to be held for safe removal from the list (it
|
||||
* ensures no active vp_list traversal while the vport is removed
|
||||
* from the queue)
|
||||
*/
|
||||
spin_lock_irqsave(&ha->vport_slock, flags);
|
||||
while (atomic_read(&vha->vref_count)) {
|
||||
spin_unlock_irqrestore(&ha->vport_slock, flags);
|
||||
|
||||
msleep(500);
|
||||
|
||||
spin_lock_irqsave(&ha->vport_slock, flags);
|
||||
}
|
||||
list_del(&vha->list);
|
||||
qlt_update_vp_map(vha, RESET_VP_IDX);
|
||||
spin_unlock_irqrestore(&ha->vport_slock, flags);
|
||||
|
||||
vp_id = vha->vp_idx;
|
||||
ha->num_vhosts--;
|
||||
clear_bit(vp_id, ha->vp_idx_map);
|
||||
|
||||
mutex_unlock(&ha->vport_lock);
|
||||
}
|
||||
|
||||
static scsi_qla_host_t *
|
||||
qla24xx_find_vhost_by_name(struct qla_hw_data *ha, uint8_t *port_name)
|
||||
{
|
||||
scsi_qla_host_t *vha;
|
||||
struct scsi_qla_host *tvha;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&ha->vport_slock, flags);
|
||||
/* Locate matching device in database. */
|
||||
list_for_each_entry_safe(vha, tvha, &ha->vp_list, list) {
|
||||
if (!memcmp(port_name, vha->port_name, WWN_SIZE)) {
|
||||
spin_unlock_irqrestore(&ha->vport_slock, flags);
|
||||
return vha;
|
||||
}
|
||||
}
|
||||
spin_unlock_irqrestore(&ha->vport_slock, flags);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* qla2x00_mark_vp_devices_dead
|
||||
* Updates fcport state when device goes offline.
|
||||
*
|
||||
* Input:
|
||||
* ha = adapter block pointer.
|
||||
* fcport = port structure pointer.
|
||||
*
|
||||
* Return:
|
||||
* None.
|
||||
*
|
||||
* Context:
|
||||
*/
|
||||
static void
|
||||
qla2x00_mark_vp_devices_dead(scsi_qla_host_t *vha)
|
||||
{
|
||||
/*
|
||||
* !!! NOTE !!!
|
||||
* This function, if called in contexts other than vp create, disable
|
||||
* or delete, please make sure this is synchronized with the
|
||||
* delete thread.
|
||||
*/
|
||||
fc_port_t *fcport;
|
||||
|
||||
list_for_each_entry(fcport, &vha->vp_fcports, list) {
|
||||
ql_dbg(ql_dbg_vport, vha, 0xa001,
|
||||
"Marking port dead, loop_id=0x%04x : %x.\n",
|
||||
fcport->loop_id, fcport->vha->vp_idx);
|
||||
|
||||
qla2x00_mark_device_lost(vha, fcport, 0, 0);
|
||||
qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
qla24xx_disable_vp(scsi_qla_host_t *vha)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
ret = qla24xx_control_vp(vha, VCE_COMMAND_DISABLE_VPS_LOGO_ALL);
|
||||
atomic_set(&vha->loop_state, LOOP_DOWN);
|
||||
atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
|
||||
|
||||
/* Remove port id from vp target map */
|
||||
spin_lock_irqsave(&vha->hw->vport_slock, flags);
|
||||
qlt_update_vp_map(vha, RESET_AL_PA);
|
||||
spin_unlock_irqrestore(&vha->hw->vport_slock, flags);
|
||||
|
||||
qla2x00_mark_vp_devices_dead(vha);
|
||||
atomic_set(&vha->vp_state, VP_FAILED);
|
||||
vha->flags.management_server_logged_in = 0;
|
||||
if (ret == QLA_SUCCESS) {
|
||||
fc_vport_set_state(vha->fc_vport, FC_VPORT_DISABLED);
|
||||
} else {
|
||||
fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
qla24xx_enable_vp(scsi_qla_host_t *vha)
|
||||
{
|
||||
int ret;
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
|
||||
|
||||
/* Check if physical ha port is Up */
|
||||
if (atomic_read(&base_vha->loop_state) == LOOP_DOWN ||
|
||||
atomic_read(&base_vha->loop_state) == LOOP_DEAD ||
|
||||
!(ha->current_topology & ISP_CFG_F)) {
|
||||
vha->vp_err_state = VP_ERR_PORTDWN;
|
||||
fc_vport_set_state(vha->fc_vport, FC_VPORT_LINKDOWN);
|
||||
goto enable_failed;
|
||||
}
|
||||
|
||||
/* Initialize the new vport unless it is a persistent port */
|
||||
mutex_lock(&ha->vport_lock);
|
||||
ret = qla24xx_modify_vp_config(vha);
|
||||
mutex_unlock(&ha->vport_lock);
|
||||
|
||||
if (ret != QLA_SUCCESS) {
|
||||
fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
|
||||
goto enable_failed;
|
||||
}
|
||||
|
||||
ql_dbg(ql_dbg_taskm, vha, 0x801a,
|
||||
"Virtual port with id: %d - Enabled.\n", vha->vp_idx);
|
||||
return 0;
|
||||
|
||||
enable_failed:
|
||||
ql_dbg(ql_dbg_taskm, vha, 0x801b,
|
||||
"Virtual port with id: %d - Disabled.\n", vha->vp_idx);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void
|
||||
qla24xx_configure_vp(scsi_qla_host_t *vha)
|
||||
{
|
||||
struct fc_vport *fc_vport;
|
||||
int ret;
|
||||
|
||||
fc_vport = vha->fc_vport;
|
||||
|
||||
ql_dbg(ql_dbg_vport, vha, 0xa002,
|
||||
"%s: change request #3.\n", __func__);
|
||||
ret = qla2x00_send_change_request(vha, 0x3, vha->vp_idx);
|
||||
if (ret != QLA_SUCCESS) {
|
||||
ql_dbg(ql_dbg_vport, vha, 0xa003, "Failed to enable "
|
||||
"receiving of RSCN requests: 0x%x.\n", ret);
|
||||
return;
|
||||
} else {
|
||||
/* Corresponds to SCR enabled */
|
||||
clear_bit(VP_SCR_NEEDED, &vha->vp_flags);
|
||||
}
|
||||
|
||||
vha->flags.online = 1;
|
||||
if (qla24xx_configure_vhba(vha))
|
||||
return;
|
||||
|
||||
atomic_set(&vha->vp_state, VP_ACTIVE);
|
||||
fc_vport_set_state(fc_vport, FC_VPORT_ACTIVE);
|
||||
}
|
||||
|
||||
void
|
||||
qla2x00_alert_all_vps(struct rsp_que *rsp, uint16_t *mb)
|
||||
{
|
||||
scsi_qla_host_t *vha;
|
||||
struct qla_hw_data *ha = rsp->hw;
|
||||
int i = 0;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&ha->vport_slock, flags);
|
||||
list_for_each_entry(vha, &ha->vp_list, list) {
|
||||
if (vha->vp_idx) {
|
||||
atomic_inc(&vha->vref_count);
|
||||
spin_unlock_irqrestore(&ha->vport_slock, flags);
|
||||
|
||||
switch (mb[0]) {
|
||||
case MBA_LIP_OCCURRED:
|
||||
case MBA_LOOP_UP:
|
||||
case MBA_LOOP_DOWN:
|
||||
case MBA_LIP_RESET:
|
||||
case MBA_POINT_TO_POINT:
|
||||
case MBA_CHG_IN_CONNECTION:
|
||||
case MBA_PORT_UPDATE:
|
||||
case MBA_RSCN_UPDATE:
|
||||
ql_dbg(ql_dbg_async, vha, 0x5024,
|
||||
"Async_event for VP[%d], mb=0x%x vha=%p.\n",
|
||||
i, *mb, vha);
|
||||
qla2x00_async_event(vha, rsp, mb);
|
||||
break;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&ha->vport_slock, flags);
|
||||
atomic_dec(&vha->vref_count);
|
||||
}
|
||||
i++;
|
||||
}
|
||||
spin_unlock_irqrestore(&ha->vport_slock, flags);
|
||||
}
|
||||
|
||||
int
|
||||
qla2x00_vp_abort_isp(scsi_qla_host_t *vha)
|
||||
{
|
||||
/*
|
||||
* Physical port will do most of the abort and recovery work. We can
|
||||
* just treat it as a loop down
|
||||
*/
|
||||
if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
|
||||
atomic_set(&vha->loop_state, LOOP_DOWN);
|
||||
qla2x00_mark_all_devices_lost(vha, 0);
|
||||
} else {
|
||||
if (!atomic_read(&vha->loop_down_timer))
|
||||
atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
|
||||
}
|
||||
|
||||
/*
|
||||
* To exclusively reset vport, we need to log it out first. Note: this
|
||||
* control_vp can fail if ISP reset is already issued, this is
|
||||
* expected, as the vp would be already logged out due to ISP reset.
|
||||
*/
|
||||
if (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
|
||||
qla24xx_control_vp(vha, VCE_COMMAND_DISABLE_VPS_LOGO_ALL);
|
||||
|
||||
ql_dbg(ql_dbg_taskm, vha, 0x801d,
|
||||
"Scheduling enable of Vport %d.\n", vha->vp_idx);
|
||||
return qla24xx_enable_vp(vha);
|
||||
}
|
||||
|
||||
static int
|
||||
qla2x00_do_dpc_vp(scsi_qla_host_t *vha)
|
||||
{
|
||||
ql_dbg(ql_dbg_dpc + ql_dbg_verbose, vha, 0x4012,
|
||||
"Entering %s vp_flags: 0x%lx.\n", __func__, vha->vp_flags);
|
||||
|
||||
qla2x00_do_work(vha);
|
||||
|
||||
if (test_and_clear_bit(VP_IDX_ACQUIRED, &vha->vp_flags)) {
|
||||
/* VP acquired. complete port configuration */
|
||||
ql_dbg(ql_dbg_dpc, vha, 0x4014,
|
||||
"Configure VP scheduled.\n");
|
||||
qla24xx_configure_vp(vha);
|
||||
ql_dbg(ql_dbg_dpc, vha, 0x4015,
|
||||
"Configure VP end.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags)) {
|
||||
ql_dbg(ql_dbg_dpc, vha, 0x4016,
|
||||
"FCPort update scheduled.\n");
|
||||
qla2x00_update_fcports(vha);
|
||||
clear_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags);
|
||||
ql_dbg(ql_dbg_dpc, vha, 0x4017,
|
||||
"FCPort update end.\n");
|
||||
}
|
||||
|
||||
if ((test_and_clear_bit(RELOGIN_NEEDED, &vha->dpc_flags)) &&
|
||||
!test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) &&
|
||||
atomic_read(&vha->loop_state) != LOOP_DOWN) {
|
||||
|
||||
ql_dbg(ql_dbg_dpc, vha, 0x4018,
|
||||
"Relogin needed scheduled.\n");
|
||||
qla2x00_relogin(vha);
|
||||
ql_dbg(ql_dbg_dpc, vha, 0x4019,
|
||||
"Relogin needed end.\n");
|
||||
}
|
||||
|
||||
if (test_and_clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) &&
|
||||
(!(test_and_set_bit(RESET_ACTIVE, &vha->dpc_flags)))) {
|
||||
clear_bit(RESET_ACTIVE, &vha->dpc_flags);
|
||||
}
|
||||
|
||||
if (test_and_clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
|
||||
if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))) {
|
||||
ql_dbg(ql_dbg_dpc, vha, 0x401a,
|
||||
"Loop resync scheduled.\n");
|
||||
qla2x00_loop_resync(vha);
|
||||
clear_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags);
|
||||
ql_dbg(ql_dbg_dpc, vha, 0x401b,
|
||||
"Loop resync end.\n");
|
||||
}
|
||||
}
|
||||
|
||||
ql_dbg(ql_dbg_dpc + ql_dbg_verbose, vha, 0x401c,
|
||||
"Exiting %s.\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
qla2x00_do_dpc_all_vps(scsi_qla_host_t *vha)
|
||||
{
|
||||
int ret;
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
scsi_qla_host_t *vp;
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (vha->vp_idx)
|
||||
return;
|
||||
if (list_empty(&ha->vp_list))
|
||||
return;
|
||||
|
||||
clear_bit(VP_DPC_NEEDED, &vha->dpc_flags);
|
||||
|
||||
if (!(ha->current_topology & ISP_CFG_F))
|
||||
return;
|
||||
|
||||
spin_lock_irqsave(&ha->vport_slock, flags);
|
||||
list_for_each_entry(vp, &ha->vp_list, list) {
|
||||
if (vp->vp_idx) {
|
||||
atomic_inc(&vp->vref_count);
|
||||
spin_unlock_irqrestore(&ha->vport_slock, flags);
|
||||
|
||||
ret = qla2x00_do_dpc_vp(vp);
|
||||
|
||||
spin_lock_irqsave(&ha->vport_slock, flags);
|
||||
atomic_dec(&vp->vref_count);
|
||||
}
|
||||
}
|
||||
spin_unlock_irqrestore(&ha->vport_slock, flags);
|
||||
}
|
||||
|
||||
int
|
||||
qla24xx_vport_create_req_sanity_check(struct fc_vport *fc_vport)
|
||||
{
|
||||
scsi_qla_host_t *base_vha = shost_priv(fc_vport->shost);
|
||||
struct qla_hw_data *ha = base_vha->hw;
|
||||
scsi_qla_host_t *vha;
|
||||
uint8_t port_name[WWN_SIZE];
|
||||
|
||||
if (fc_vport->roles != FC_PORT_ROLE_FCP_INITIATOR)
|
||||
return VPCERR_UNSUPPORTED;
|
||||
|
||||
/* Check up the F/W and H/W support NPIV */
|
||||
if (!ha->flags.npiv_supported)
|
||||
return VPCERR_UNSUPPORTED;
|
||||
|
||||
/* Check up whether npiv supported switch presented */
|
||||
if (!(ha->switch_cap & FLOGI_MID_SUPPORT))
|
||||
return VPCERR_NO_FABRIC_SUPP;
|
||||
|
||||
/* Check up unique WWPN */
|
||||
u64_to_wwn(fc_vport->port_name, port_name);
|
||||
if (!memcmp(port_name, base_vha->port_name, WWN_SIZE))
|
||||
return VPCERR_BAD_WWN;
|
||||
vha = qla24xx_find_vhost_by_name(ha, port_name);
|
||||
if (vha)
|
||||
return VPCERR_BAD_WWN;
|
||||
|
||||
/* Check up max-npiv-supports */
|
||||
if (ha->num_vhosts > ha->max_npiv_vports) {
|
||||
ql_dbg(ql_dbg_vport, vha, 0xa004,
|
||||
"num_vhosts %ud is bigger "
|
||||
"than max_npiv_vports %ud.\n",
|
||||
ha->num_vhosts, ha->max_npiv_vports);
|
||||
return VPCERR_UNSUPPORTED;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
scsi_qla_host_t *
|
||||
qla24xx_create_vhost(struct fc_vport *fc_vport)
|
||||
{
|
||||
scsi_qla_host_t *base_vha = shost_priv(fc_vport->shost);
|
||||
struct qla_hw_data *ha = base_vha->hw;
|
||||
scsi_qla_host_t *vha;
|
||||
struct scsi_host_template *sht = &qla2xxx_driver_template;
|
||||
struct Scsi_Host *host;
|
||||
|
||||
vha = qla2x00_create_host(sht, ha);
|
||||
if (!vha) {
|
||||
ql_log(ql_log_warn, vha, 0xa005,
|
||||
"scsi_host_alloc() failed for vport.\n");
|
||||
return(NULL);
|
||||
}
|
||||
|
||||
host = vha->host;
|
||||
fc_vport->dd_data = vha;
|
||||
/* New host info */
|
||||
u64_to_wwn(fc_vport->node_name, vha->node_name);
|
||||
u64_to_wwn(fc_vport->port_name, vha->port_name);
|
||||
|
||||
vha->fc_vport = fc_vport;
|
||||
vha->device_flags = 0;
|
||||
vha->vp_idx = qla24xx_allocate_vp_id(vha);
|
||||
if (vha->vp_idx > ha->max_npiv_vports) {
|
||||
ql_dbg(ql_dbg_vport, vha, 0xa006,
|
||||
"Couldn't allocate vp_id.\n");
|
||||
goto create_vhost_failed;
|
||||
}
|
||||
vha->mgmt_svr_loop_id = 10 + vha->vp_idx;
|
||||
|
||||
vha->dpc_flags = 0L;
|
||||
|
||||
/*
|
||||
* To fix the issue of processing a parent's RSCN for the vport before
|
||||
* its SCR is complete.
|
||||
*/
|
||||
set_bit(VP_SCR_NEEDED, &vha->vp_flags);
|
||||
atomic_set(&vha->loop_state, LOOP_DOWN);
|
||||
atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
|
||||
|
||||
qla2x00_start_timer(vha, qla2x00_timer, WATCH_INTERVAL);
|
||||
|
||||
vha->req = base_vha->req;
|
||||
host->can_queue = base_vha->req->length + 128;
|
||||
host->cmd_per_lun = 3;
|
||||
if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
|
||||
host->max_cmd_len = 32;
|
||||
else
|
||||
host->max_cmd_len = MAX_CMDSZ;
|
||||
host->max_channel = MAX_BUSES - 1;
|
||||
host->max_lun = ql2xmaxlun;
|
||||
host->unique_id = host->host_no;
|
||||
host->max_id = ha->max_fibre_devices;
|
||||
host->transportt = qla2xxx_transport_vport_template;
|
||||
|
||||
ql_dbg(ql_dbg_vport, vha, 0xa007,
|
||||
"Detect vport hba %ld at address = %p.\n",
|
||||
vha->host_no, vha);
|
||||
|
||||
vha->flags.init_done = 1;
|
||||
|
||||
mutex_lock(&ha->vport_lock);
|
||||
set_bit(vha->vp_idx, ha->vp_idx_map);
|
||||
ha->cur_vport_count++;
|
||||
mutex_unlock(&ha->vport_lock);
|
||||
|
||||
return vha;
|
||||
|
||||
create_vhost_failed:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void
|
||||
qla25xx_free_req_que(struct scsi_qla_host *vha, struct req_que *req)
|
||||
{
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
uint16_t que_id = req->id;
|
||||
|
||||
dma_free_coherent(&ha->pdev->dev, (req->length + 1) *
|
||||
sizeof(request_t), req->ring, req->dma);
|
||||
req->ring = NULL;
|
||||
req->dma = 0;
|
||||
if (que_id) {
|
||||
ha->req_q_map[que_id] = NULL;
|
||||
mutex_lock(&ha->vport_lock);
|
||||
clear_bit(que_id, ha->req_qid_map);
|
||||
mutex_unlock(&ha->vport_lock);
|
||||
}
|
||||
kfree(req->outstanding_cmds);
|
||||
kfree(req);
|
||||
req = NULL;
|
||||
}
|
||||
|
||||
static void
|
||||
qla25xx_free_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
|
||||
{
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
uint16_t que_id = rsp->id;
|
||||
|
||||
if (rsp->msix && rsp->msix->have_irq) {
|
||||
free_irq(rsp->msix->vector, rsp);
|
||||
rsp->msix->have_irq = 0;
|
||||
rsp->msix->rsp = NULL;
|
||||
}
|
||||
dma_free_coherent(&ha->pdev->dev, (rsp->length + 1) *
|
||||
sizeof(response_t), rsp->ring, rsp->dma);
|
||||
rsp->ring = NULL;
|
||||
rsp->dma = 0;
|
||||
if (que_id) {
|
||||
ha->rsp_q_map[que_id] = NULL;
|
||||
mutex_lock(&ha->vport_lock);
|
||||
clear_bit(que_id, ha->rsp_qid_map);
|
||||
mutex_unlock(&ha->vport_lock);
|
||||
}
|
||||
kfree(rsp);
|
||||
rsp = NULL;
|
||||
}
|
||||
|
||||
int
|
||||
qla25xx_delete_req_que(struct scsi_qla_host *vha, struct req_que *req)
|
||||
{
|
||||
int ret = -1;
|
||||
|
||||
if (req) {
|
||||
req->options |= BIT_0;
|
||||
ret = qla25xx_init_req_que(vha, req);
|
||||
}
|
||||
if (ret == QLA_SUCCESS)
|
||||
qla25xx_free_req_que(vha, req);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
qla25xx_delete_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
|
||||
{
|
||||
int ret = -1;
|
||||
|
||||
if (rsp) {
|
||||
rsp->options |= BIT_0;
|
||||
ret = qla25xx_init_rsp_que(vha, rsp);
|
||||
}
|
||||
if (ret == QLA_SUCCESS)
|
||||
qla25xx_free_rsp_que(vha, rsp);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Delete all queues for a given vhost */
|
||||
int
|
||||
qla25xx_delete_queues(struct scsi_qla_host *vha)
|
||||
{
|
||||
int cnt, ret = 0;
|
||||
struct req_que *req = NULL;
|
||||
struct rsp_que *rsp = NULL;
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
|
||||
/* Delete request queues */
|
||||
for (cnt = 1; cnt < ha->max_req_queues; cnt++) {
|
||||
req = ha->req_q_map[cnt];
|
||||
if (req) {
|
||||
ret = qla25xx_delete_req_que(vha, req);
|
||||
if (ret != QLA_SUCCESS) {
|
||||
ql_log(ql_log_warn, vha, 0x00ea,
|
||||
"Couldn't delete req que %d.\n",
|
||||
req->id);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Delete response queues */
|
||||
for (cnt = 1; cnt < ha->max_rsp_queues; cnt++) {
|
||||
rsp = ha->rsp_q_map[cnt];
|
||||
if (rsp) {
|
||||
ret = qla25xx_delete_rsp_que(vha, rsp);
|
||||
if (ret != QLA_SUCCESS) {
|
||||
ql_log(ql_log_warn, vha, 0x00eb,
|
||||
"Couldn't delete rsp que %d.\n",
|
||||
rsp->id);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
qla25xx_create_req_que(struct qla_hw_data *ha, uint16_t options,
|
||||
uint8_t vp_idx, uint16_t rid, int rsp_que, uint8_t qos)
|
||||
{
|
||||
int ret = 0;
|
||||
struct req_que *req = NULL;
|
||||
struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
|
||||
uint16_t que_id = 0;
|
||||
device_reg_t *reg;
|
||||
uint32_t cnt;
|
||||
|
||||
req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
|
||||
if (req == NULL) {
|
||||
ql_log(ql_log_fatal, base_vha, 0x00d9,
|
||||
"Failed to allocate memory for request queue.\n");
|
||||
goto failed;
|
||||
}
|
||||
|
||||
req->length = REQUEST_ENTRY_CNT_24XX;
|
||||
req->ring = dma_alloc_coherent(&ha->pdev->dev,
|
||||
(req->length + 1) * sizeof(request_t),
|
||||
&req->dma, GFP_KERNEL);
|
||||
if (req->ring == NULL) {
|
||||
ql_log(ql_log_fatal, base_vha, 0x00da,
|
||||
"Failed to allocate memory for request_ring.\n");
|
||||
goto que_failed;
|
||||
}
|
||||
|
||||
ret = qla2x00_alloc_outstanding_cmds(ha, req);
|
||||
if (ret != QLA_SUCCESS)
|
||||
goto que_failed;
|
||||
|
||||
mutex_lock(&ha->vport_lock);
|
||||
que_id = find_first_zero_bit(ha->req_qid_map, ha->max_req_queues);
|
||||
if (que_id >= ha->max_req_queues) {
|
||||
mutex_unlock(&ha->vport_lock);
|
||||
ql_log(ql_log_warn, base_vha, 0x00db,
|
||||
"No resources to create additional request queue.\n");
|
||||
goto que_failed;
|
||||
}
|
||||
set_bit(que_id, ha->req_qid_map);
|
||||
ha->req_q_map[que_id] = req;
|
||||
req->rid = rid;
|
||||
req->vp_idx = vp_idx;
|
||||
req->qos = qos;
|
||||
|
||||
ql_dbg(ql_dbg_multiq, base_vha, 0xc002,
|
||||
"queue_id=%d rid=%d vp_idx=%d qos=%d.\n",
|
||||
que_id, req->rid, req->vp_idx, req->qos);
|
||||
ql_dbg(ql_dbg_init, base_vha, 0x00dc,
|
||||
"queue_id=%d rid=%d vp_idx=%d qos=%d.\n",
|
||||
que_id, req->rid, req->vp_idx, req->qos);
|
||||
if (rsp_que < 0)
|
||||
req->rsp = NULL;
|
||||
else
|
||||
req->rsp = ha->rsp_q_map[rsp_que];
|
||||
/* Use alternate PCI bus number */
|
||||
if (MSB(req->rid))
|
||||
options |= BIT_4;
|
||||
/* Use alternate PCI devfn */
|
||||
if (LSB(req->rid))
|
||||
options |= BIT_5;
|
||||
req->options = options;
|
||||
|
||||
ql_dbg(ql_dbg_multiq, base_vha, 0xc003,
|
||||
"options=0x%x.\n", req->options);
|
||||
ql_dbg(ql_dbg_init, base_vha, 0x00dd,
|
||||
"options=0x%x.\n", req->options);
|
||||
for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
|
||||
req->outstanding_cmds[cnt] = NULL;
|
||||
req->current_outstanding_cmd = 1;
|
||||
|
||||
req->ring_ptr = req->ring;
|
||||
req->ring_index = 0;
|
||||
req->cnt = req->length;
|
||||
req->id = que_id;
|
||||
reg = ISP_QUE_REG(ha, que_id);
|
||||
req->req_q_in = ®->isp25mq.req_q_in;
|
||||
req->req_q_out = ®->isp25mq.req_q_out;
|
||||
req->max_q_depth = ha->req_q_map[0]->max_q_depth;
|
||||
req->out_ptr = (void *)(req->ring + req->length);
|
||||
mutex_unlock(&ha->vport_lock);
|
||||
ql_dbg(ql_dbg_multiq, base_vha, 0xc004,
|
||||
"ring_ptr=%p ring_index=%d, "
|
||||
"cnt=%d id=%d max_q_depth=%d.\n",
|
||||
req->ring_ptr, req->ring_index,
|
||||
req->cnt, req->id, req->max_q_depth);
|
||||
ql_dbg(ql_dbg_init, base_vha, 0x00de,
|
||||
"ring_ptr=%p ring_index=%d, "
|
||||
"cnt=%d id=%d max_q_depth=%d.\n",
|
||||
req->ring_ptr, req->ring_index, req->cnt,
|
||||
req->id, req->max_q_depth);
|
||||
|
||||
ret = qla25xx_init_req_que(base_vha, req);
|
||||
if (ret != QLA_SUCCESS) {
|
||||
ql_log(ql_log_fatal, base_vha, 0x00df,
|
||||
"%s failed.\n", __func__);
|
||||
mutex_lock(&ha->vport_lock);
|
||||
clear_bit(que_id, ha->req_qid_map);
|
||||
mutex_unlock(&ha->vport_lock);
|
||||
goto que_failed;
|
||||
}
|
||||
|
||||
return req->id;
|
||||
|
||||
que_failed:
|
||||
qla25xx_free_req_que(base_vha, req);
|
||||
failed:
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void qla_do_work(struct work_struct *work)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct rsp_que *rsp = container_of(work, struct rsp_que, q_work);
|
||||
struct scsi_qla_host *vha;
|
||||
struct qla_hw_data *ha = rsp->hw;
|
||||
|
||||
spin_lock_irqsave(&rsp->hw->hardware_lock, flags);
|
||||
vha = pci_get_drvdata(ha->pdev);
|
||||
qla24xx_process_response_queue(vha, rsp);
|
||||
spin_unlock_irqrestore(&rsp->hw->hardware_lock, flags);
|
||||
}
|
||||
|
||||
/* create response queue */
|
||||
int
|
||||
qla25xx_create_rsp_que(struct qla_hw_data *ha, uint16_t options,
|
||||
uint8_t vp_idx, uint16_t rid, int req)
|
||||
{
|
||||
int ret = 0;
|
||||
struct rsp_que *rsp = NULL;
|
||||
struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
|
||||
uint16_t que_id = 0;
|
||||
device_reg_t *reg;
|
||||
|
||||
rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
|
||||
if (rsp == NULL) {
|
||||
ql_log(ql_log_warn, base_vha, 0x0066,
|
||||
"Failed to allocate memory for response queue.\n");
|
||||
goto failed;
|
||||
}
|
||||
|
||||
rsp->length = RESPONSE_ENTRY_CNT_MQ;
|
||||
rsp->ring = dma_alloc_coherent(&ha->pdev->dev,
|
||||
(rsp->length + 1) * sizeof(response_t),
|
||||
&rsp->dma, GFP_KERNEL);
|
||||
if (rsp->ring == NULL) {
|
||||
ql_log(ql_log_warn, base_vha, 0x00e1,
|
||||
"Failed to allocate memory for response ring.\n");
|
||||
goto que_failed;
|
||||
}
|
||||
|
||||
mutex_lock(&ha->vport_lock);
|
||||
que_id = find_first_zero_bit(ha->rsp_qid_map, ha->max_rsp_queues);
|
||||
if (que_id >= ha->max_rsp_queues) {
|
||||
mutex_unlock(&ha->vport_lock);
|
||||
ql_log(ql_log_warn, base_vha, 0x00e2,
|
||||
"No resources to create additional request queue.\n");
|
||||
goto que_failed;
|
||||
}
|
||||
set_bit(que_id, ha->rsp_qid_map);
|
||||
|
||||
if (ha->flags.msix_enabled)
|
||||
rsp->msix = &ha->msix_entries[que_id + 1];
|
||||
else
|
||||
ql_log(ql_log_warn, base_vha, 0x00e3,
|
||||
"MSIX not enalbled.\n");
|
||||
|
||||
ha->rsp_q_map[que_id] = rsp;
|
||||
rsp->rid = rid;
|
||||
rsp->vp_idx = vp_idx;
|
||||
rsp->hw = ha;
|
||||
ql_dbg(ql_dbg_init, base_vha, 0x00e4,
|
||||
"queue_id=%d rid=%d vp_idx=%d hw=%p.\n",
|
||||
que_id, rsp->rid, rsp->vp_idx, rsp->hw);
|
||||
/* Use alternate PCI bus number */
|
||||
if (MSB(rsp->rid))
|
||||
options |= BIT_4;
|
||||
/* Use alternate PCI devfn */
|
||||
if (LSB(rsp->rid))
|
||||
options |= BIT_5;
|
||||
/* Enable MSIX handshake mode on for uncapable adapters */
|
||||
if (!IS_MSIX_NACK_CAPABLE(ha))
|
||||
options |= BIT_6;
|
||||
|
||||
rsp->options = options;
|
||||
rsp->id = que_id;
|
||||
reg = ISP_QUE_REG(ha, que_id);
|
||||
rsp->rsp_q_in = ®->isp25mq.rsp_q_in;
|
||||
rsp->rsp_q_out = ®->isp25mq.rsp_q_out;
|
||||
rsp->in_ptr = (void *)(rsp->ring + rsp->length);
|
||||
mutex_unlock(&ha->vport_lock);
|
||||
ql_dbg(ql_dbg_multiq, base_vha, 0xc00b,
|
||||
"options=%x id=%d rsp_q_in=%p rsp_q_out=%p",
|
||||
rsp->options, rsp->id, rsp->rsp_q_in,
|
||||
rsp->rsp_q_out);
|
||||
ql_dbg(ql_dbg_init, base_vha, 0x00e5,
|
||||
"options=%x id=%d rsp_q_in=%p rsp_q_out=%p",
|
||||
rsp->options, rsp->id, rsp->rsp_q_in,
|
||||
rsp->rsp_q_out);
|
||||
|
||||
ret = qla25xx_request_irq(rsp);
|
||||
if (ret)
|
||||
goto que_failed;
|
||||
|
||||
ret = qla25xx_init_rsp_que(base_vha, rsp);
|
||||
if (ret != QLA_SUCCESS) {
|
||||
ql_log(ql_log_fatal, base_vha, 0x00e7,
|
||||
"%s failed.\n", __func__);
|
||||
mutex_lock(&ha->vport_lock);
|
||||
clear_bit(que_id, ha->rsp_qid_map);
|
||||
mutex_unlock(&ha->vport_lock);
|
||||
goto que_failed;
|
||||
}
|
||||
if (req >= 0)
|
||||
rsp->req = ha->req_q_map[req];
|
||||
else
|
||||
rsp->req = NULL;
|
||||
|
||||
qla2x00_init_response_q_entries(rsp);
|
||||
if (rsp->hw->wq)
|
||||
INIT_WORK(&rsp->q_work, qla_do_work);
|
||||
return rsp->id;
|
||||
|
||||
que_failed:
|
||||
qla25xx_free_rsp_que(base_vha, rsp);
|
||||
failed:
|
||||
return 0;
|
||||
}
|
||||
3474
drivers/scsi/qla2xxx/qla_mr.c
Normal file
3474
drivers/scsi/qla2xxx/qla_mr.c
Normal file
File diff suppressed because it is too large
Load diff
527
drivers/scsi/qla2xxx/qla_mr.h
Normal file
527
drivers/scsi/qla2xxx/qla_mr.h
Normal file
|
|
@ -0,0 +1,527 @@
|
|||
/*
|
||||
* QLogic Fibre Channel HBA Driver
|
||||
* Copyright (c) 2003-2014 QLogic Corporation
|
||||
*
|
||||
* See LICENSE.qla2xxx for copyright and licensing details.
|
||||
*/
|
||||
#ifndef __QLA_MR_H
|
||||
#define __QLA_MR_H
|
||||
|
||||
/*
|
||||
* The PCI VendorID and DeviceID for our board.
|
||||
*/
|
||||
#define PCI_DEVICE_ID_QLOGIC_ISPF001 0xF001
|
||||
|
||||
/* FX00 specific definitions */
|
||||
|
||||
#define FX00_COMMAND_TYPE_7 0x07 /* Command Type 7 entry for 7XXX */
|
||||
struct cmd_type_7_fx00 {
|
||||
uint8_t entry_type; /* Entry type. */
|
||||
uint8_t entry_count; /* Entry count. */
|
||||
uint8_t sys_define; /* System defined. */
|
||||
uint8_t entry_status; /* Entry Status. */
|
||||
|
||||
uint32_t handle; /* System handle. */
|
||||
uint8_t reserved_0;
|
||||
uint8_t port_path_ctrl;
|
||||
uint16_t reserved_1;
|
||||
|
||||
__le16 tgt_idx; /* Target Idx. */
|
||||
uint16_t timeout; /* Command timeout. */
|
||||
|
||||
__le16 dseg_count; /* Data segment count. */
|
||||
uint8_t scsi_rsp_dsd_len;
|
||||
uint8_t reserved_2;
|
||||
|
||||
struct scsi_lun lun; /* LUN (LE). */
|
||||
|
||||
uint8_t cntrl_flags;
|
||||
|
||||
uint8_t task_mgmt_flags; /* Task management flags. */
|
||||
|
||||
uint8_t task;
|
||||
|
||||
uint8_t crn;
|
||||
|
||||
uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */
|
||||
__le32 byte_count; /* Total byte count. */
|
||||
|
||||
uint32_t dseg_0_address[2]; /* Data segment 0 address. */
|
||||
uint32_t dseg_0_len; /* Data segment 0 length. */
|
||||
};
|
||||
|
||||
#define STATUS_TYPE_FX00 0x01 /* Status entry. */
|
||||
struct sts_entry_fx00 {
|
||||
uint8_t entry_type; /* Entry type. */
|
||||
uint8_t entry_count; /* Entry count. */
|
||||
uint8_t sys_define; /* System defined. */
|
||||
uint8_t entry_status; /* Entry Status. */
|
||||
|
||||
uint32_t handle; /* System handle. */
|
||||
uint32_t reserved_3; /* System handle. */
|
||||
|
||||
__le16 comp_status; /* Completion status. */
|
||||
uint16_t reserved_0; /* OX_ID used by the firmware. */
|
||||
|
||||
__le32 residual_len; /* FW calc residual transfer length. */
|
||||
|
||||
uint16_t reserved_1;
|
||||
uint16_t state_flags; /* State flags. */
|
||||
|
||||
uint16_t reserved_2;
|
||||
__le16 scsi_status; /* SCSI status. */
|
||||
|
||||
uint32_t sense_len; /* FCP SENSE length. */
|
||||
uint8_t data[32]; /* FCP response/sense information. */
|
||||
};
|
||||
|
||||
|
||||
#define MAX_HANDLE_COUNT 15
|
||||
#define MULTI_STATUS_TYPE_FX00 0x0D
|
||||
|
||||
struct multi_sts_entry_fx00 {
|
||||
uint8_t entry_type; /* Entry type. */
|
||||
uint8_t entry_count; /* Entry count. */
|
||||
uint8_t handle_count;
|
||||
uint8_t entry_status;
|
||||
|
||||
__le32 handles[MAX_HANDLE_COUNT];
|
||||
};
|
||||
|
||||
#define TSK_MGMT_IOCB_TYPE_FX00 0x05
|
||||
struct tsk_mgmt_entry_fx00 {
|
||||
uint8_t entry_type; /* Entry type. */
|
||||
uint8_t entry_count; /* Entry count. */
|
||||
uint8_t sys_define;
|
||||
uint8_t entry_status; /* Entry Status. */
|
||||
|
||||
__le32 handle; /* System handle. */
|
||||
|
||||
uint32_t reserved_0;
|
||||
|
||||
__le16 tgt_id; /* Target Idx. */
|
||||
|
||||
uint16_t reserved_1;
|
||||
uint16_t reserved_3;
|
||||
uint16_t reserved_4;
|
||||
|
||||
struct scsi_lun lun; /* LUN (LE). */
|
||||
|
||||
__le32 control_flags; /* Control Flags. */
|
||||
|
||||
uint8_t reserved_2[32];
|
||||
};
|
||||
|
||||
|
||||
#define ABORT_IOCB_TYPE_FX00 0x08 /* Abort IOCB status. */
|
||||
struct abort_iocb_entry_fx00 {
|
||||
uint8_t entry_type; /* Entry type. */
|
||||
uint8_t entry_count; /* Entry count. */
|
||||
uint8_t sys_define; /* System defined. */
|
||||
uint8_t entry_status; /* Entry Status. */
|
||||
|
||||
__le32 handle; /* System handle. */
|
||||
__le32 reserved_0;
|
||||
|
||||
__le16 tgt_id_sts; /* Completion status. */
|
||||
__le16 options;
|
||||
|
||||
__le32 abort_handle; /* System handle. */
|
||||
__le32 reserved_2;
|
||||
|
||||
__le16 req_que_no;
|
||||
uint8_t reserved_1[38];
|
||||
};
|
||||
|
||||
#define IOCTL_IOSB_TYPE_FX00 0x0C
|
||||
struct ioctl_iocb_entry_fx00 {
|
||||
uint8_t entry_type; /* Entry type. */
|
||||
uint8_t entry_count; /* Entry count. */
|
||||
uint8_t sys_define; /* System defined. */
|
||||
uint8_t entry_status; /* Entry Status. */
|
||||
|
||||
uint32_t handle; /* System handle. */
|
||||
uint32_t reserved_0; /* System handle. */
|
||||
|
||||
uint16_t comp_func_num;
|
||||
__le16 fw_iotcl_flags;
|
||||
|
||||
__le32 dataword_r; /* Data word returned */
|
||||
uint32_t adapid; /* Adapter ID */
|
||||
uint32_t dataword_r_extra;
|
||||
|
||||
__le32 seq_no;
|
||||
uint8_t reserved_2[20];
|
||||
uint32_t residuallen;
|
||||
__le32 status;
|
||||
};
|
||||
|
||||
#define STATUS_CONT_TYPE_FX00 0x04
|
||||
|
||||
#define FX00_IOCB_TYPE 0x0B
|
||||
struct fxdisc_entry_fx00 {
|
||||
uint8_t entry_type; /* Entry type. */
|
||||
uint8_t entry_count; /* Entry count. */
|
||||
uint8_t sys_define; /* System Defined. */
|
||||
uint8_t entry_status; /* Entry Status. */
|
||||
|
||||
__le32 handle; /* System handle. */
|
||||
__le32 reserved_0; /* System handle. */
|
||||
|
||||
__le16 func_num;
|
||||
__le16 req_xfrcnt;
|
||||
__le16 req_dsdcnt;
|
||||
__le16 rsp_xfrcnt;
|
||||
__le16 rsp_dsdcnt;
|
||||
uint8_t flags;
|
||||
uint8_t reserved_1;
|
||||
|
||||
__le32 dseg_rq_address[2]; /* Data segment 0 address. */
|
||||
__le32 dseg_rq_len; /* Data segment 0 length. */
|
||||
__le32 dseg_rsp_address[2]; /* Data segment 1 address. */
|
||||
__le32 dseg_rsp_len; /* Data segment 1 length. */
|
||||
|
||||
__le32 dataword;
|
||||
__le32 adapid;
|
||||
__le32 adapid_hi;
|
||||
__le32 dataword_extra;
|
||||
};
|
||||
|
||||
struct qlafx00_tgt_node_info {
|
||||
uint8_t tgt_node_wwpn[WWN_SIZE];
|
||||
uint8_t tgt_node_wwnn[WWN_SIZE];
|
||||
uint32_t tgt_node_state;
|
||||
uint8_t reserved[128];
|
||||
uint32_t reserved_1[8];
|
||||
uint64_t reserved_2[4];
|
||||
} __packed;
|
||||
|
||||
#define QLAFX00_TGT_NODE_INFO sizeof(struct qlafx00_tgt_node_info)
|
||||
|
||||
#define QLAFX00_LINK_STATUS_DOWN 0x10
|
||||
#define QLAFX00_LINK_STATUS_UP 0x11
|
||||
|
||||
#define QLAFX00_PORT_SPEED_2G 0x2
|
||||
#define QLAFX00_PORT_SPEED_4G 0x4
|
||||
#define QLAFX00_PORT_SPEED_8G 0x8
|
||||
#define QLAFX00_PORT_SPEED_10G 0xa
|
||||
struct port_info_data {
|
||||
uint8_t port_state;
|
||||
uint8_t port_type;
|
||||
uint16_t port_identifier;
|
||||
uint32_t up_port_state;
|
||||
uint8_t fw_ver_num[32];
|
||||
uint8_t portal_attrib;
|
||||
uint16_t host_option;
|
||||
uint8_t reset_delay;
|
||||
uint8_t pdwn_retry_cnt;
|
||||
uint16_t max_luns2tgt;
|
||||
uint8_t risc_ver;
|
||||
uint8_t pconn_option;
|
||||
uint16_t risc_option;
|
||||
uint16_t max_frame_len;
|
||||
uint16_t max_iocb_alloc;
|
||||
uint16_t exec_throttle;
|
||||
uint8_t retry_cnt;
|
||||
uint8_t retry_delay;
|
||||
uint8_t port_name[8];
|
||||
uint8_t port_id[3];
|
||||
uint8_t link_status;
|
||||
uint8_t plink_rate;
|
||||
uint32_t link_config;
|
||||
uint16_t adap_haddr;
|
||||
uint8_t tgt_disc;
|
||||
uint8_t log_tout;
|
||||
uint8_t node_name[8];
|
||||
uint16_t erisc_opt1;
|
||||
uint8_t resp_acc_tmr;
|
||||
uint8_t intr_del_tmr;
|
||||
uint8_t erisc_opt2;
|
||||
uint8_t alt_port_name[8];
|
||||
uint8_t alt_node_name[8];
|
||||
uint8_t link_down_tout;
|
||||
uint8_t conn_type;
|
||||
uint8_t fc_fw_mode;
|
||||
uint32_t uiReserved[48];
|
||||
} __packed;
|
||||
|
||||
/* OS Type Designations */
|
||||
#define OS_TYPE_UNKNOWN 0
|
||||
#define OS_TYPE_LINUX 2
|
||||
|
||||
/* Linux Info */
|
||||
#define SYSNAME_LENGTH 128
|
||||
#define NODENAME_LENGTH 64
|
||||
#define RELEASE_LENGTH 64
|
||||
#define VERSION_LENGTH 64
|
||||
#define MACHINE_LENGTH 64
|
||||
#define DOMNAME_LENGTH 64
|
||||
|
||||
struct host_system_info {
|
||||
uint32_t os_type;
|
||||
char sysname[SYSNAME_LENGTH];
|
||||
char nodename[NODENAME_LENGTH];
|
||||
char release[RELEASE_LENGTH];
|
||||
char version[VERSION_LENGTH];
|
||||
char machine[MACHINE_LENGTH];
|
||||
char domainname[DOMNAME_LENGTH];
|
||||
char hostdriver[VERSION_LENGTH];
|
||||
uint32_t reserved[64];
|
||||
} __packed;
|
||||
|
||||
struct register_host_info {
|
||||
struct host_system_info hsi; /* host system info */
|
||||
uint64_t utc; /* UTC (system time) */
|
||||
uint32_t reserved[64]; /* future additions */
|
||||
} __packed;
|
||||
|
||||
|
||||
#define QLAFX00_PORT_DATA_INFO (sizeof(struct port_info_data))
|
||||
#define QLAFX00_TGT_NODE_LIST_SIZE (sizeof(uint32_t) * 32)
|
||||
|
||||
struct config_info_data {
|
||||
uint8_t model_num[16];
|
||||
uint8_t model_description[80];
|
||||
uint8_t reserved0[160];
|
||||
uint8_t symbolic_name[64];
|
||||
uint8_t serial_num[32];
|
||||
uint8_t hw_version[16];
|
||||
uint8_t fw_version[16];
|
||||
uint8_t uboot_version[16];
|
||||
uint8_t fru_serial_num[32];
|
||||
|
||||
uint8_t fc_port_count;
|
||||
uint8_t iscsi_port_count;
|
||||
uint8_t reserved1[2];
|
||||
|
||||
uint8_t mode;
|
||||
uint8_t log_level;
|
||||
uint8_t reserved2[2];
|
||||
|
||||
uint32_t log_size;
|
||||
|
||||
uint8_t tgt_pres_mode;
|
||||
uint8_t iqn_flags;
|
||||
uint8_t lun_mapping;
|
||||
|
||||
uint64_t adapter_id;
|
||||
|
||||
uint32_t cluster_key_len;
|
||||
uint8_t cluster_key[16];
|
||||
|
||||
uint64_t cluster_master_id;
|
||||
uint64_t cluster_slave_id;
|
||||
uint8_t cluster_flags;
|
||||
uint32_t enabled_capabilities;
|
||||
uint32_t nominal_temp_value;
|
||||
} __packed;
|
||||
|
||||
#define FXDISC_GET_CONFIG_INFO 0x01
|
||||
#define FXDISC_GET_PORT_INFO 0x02
|
||||
#define FXDISC_GET_TGT_NODE_INFO 0x80
|
||||
#define FXDISC_GET_TGT_NODE_LIST 0x81
|
||||
#define FXDISC_REG_HOST_INFO 0x99
|
||||
#define FXDISC_ABORT_IOCTL 0xff
|
||||
|
||||
#define QLAFX00_HBA_ICNTRL_REG 0x20B08
|
||||
#define QLAFX00_ICR_ENB_MASK 0x80000000
|
||||
#define QLAFX00_ICR_DIS_MASK 0x7fffffff
|
||||
#define QLAFX00_HST_RST_REG 0x18264
|
||||
#define QLAFX00_SOC_TEMP_REG 0x184C4
|
||||
#define QLAFX00_HST_TO_HBA_REG 0x20A04
|
||||
#define QLAFX00_HBA_TO_HOST_REG 0x21B70
|
||||
#define QLAFX00_HST_INT_STS_BITS 0x7
|
||||
#define QLAFX00_BAR1_BASE_ADDR_REG 0x40018
|
||||
#define QLAFX00_PEX0_WIN0_BASE_ADDR_REG 0x41824
|
||||
|
||||
#define QLAFX00_INTR_MB_CMPLT 0x1
|
||||
#define QLAFX00_INTR_RSP_CMPLT 0x2
|
||||
#define QLAFX00_INTR_ASYNC_CMPLT 0x4
|
||||
|
||||
#define QLAFX00_MBA_SYSTEM_ERR 0x8002
|
||||
#define QLAFX00_MBA_TEMP_OVER 0x8005
|
||||
#define QLAFX00_MBA_TEMP_NORM 0x8006
|
||||
#define QLAFX00_MBA_TEMP_CRIT 0x8007
|
||||
#define QLAFX00_MBA_LINK_UP 0x8011
|
||||
#define QLAFX00_MBA_LINK_DOWN 0x8012
|
||||
#define QLAFX00_MBA_PORT_UPDATE 0x8014
|
||||
#define QLAFX00_MBA_SHUTDOWN_RQSTD 0x8062
|
||||
|
||||
#define SOC_SW_RST_CONTROL_REG_CORE0 0x0020800
|
||||
#define SOC_FABRIC_RST_CONTROL_REG 0x0020840
|
||||
#define SOC_FABRIC_CONTROL_REG 0x0020200
|
||||
#define SOC_FABRIC_CONFIG_REG 0x0020204
|
||||
#define SOC_PWR_MANAGEMENT_PWR_DOWN_REG 0x001820C
|
||||
|
||||
#define SOC_INTERRUPT_SOURCE_I_CONTROL_REG 0x0020B00
|
||||
#define SOC_CORE_TIMER_REG 0x0021850
|
||||
#define SOC_IRQ_ACK_REG 0x00218b4
|
||||
|
||||
#define CONTINUE_A64_TYPE_FX00 0x03 /* Continuation entry. */
|
||||
|
||||
#define QLAFX00_SET_HST_INTR(ha, value) \
|
||||
WRT_REG_DWORD((ha)->cregbase + QLAFX00_HST_TO_HBA_REG, \
|
||||
value)
|
||||
|
||||
#define QLAFX00_CLR_HST_INTR(ha, value) \
|
||||
WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
|
||||
~value)
|
||||
|
||||
#define QLAFX00_RD_INTR_REG(ha) \
|
||||
RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)
|
||||
|
||||
#define QLAFX00_CLR_INTR_REG(ha, value) \
|
||||
WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
|
||||
~value)
|
||||
|
||||
#define QLAFX00_SET_HBA_SOC_REG(ha, off, val)\
|
||||
WRT_REG_DWORD((ha)->cregbase + off, val)
|
||||
|
||||
#define QLAFX00_GET_HBA_SOC_REG(ha, off)\
|
||||
RD_REG_DWORD((ha)->cregbase + off)
|
||||
|
||||
#define QLAFX00_HBA_RST_REG(ha, val)\
|
||||
WRT_REG_DWORD((ha)->cregbase + QLAFX00_HST_RST_REG, val)
|
||||
|
||||
#define QLAFX00_RD_ICNTRL_REG(ha) \
|
||||
RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)
|
||||
|
||||
#define QLAFX00_ENABLE_ICNTRL_REG(ha) \
|
||||
WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
|
||||
(QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) | \
|
||||
QLAFX00_ICR_ENB_MASK))
|
||||
|
||||
#define QLAFX00_DISABLE_ICNTRL_REG(ha) \
|
||||
WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
|
||||
(QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) & \
|
||||
QLAFX00_ICR_DIS_MASK))
|
||||
|
||||
#define QLAFX00_RD_REG(ha, off) \
|
||||
RD_REG_DWORD((ha)->cregbase + off)
|
||||
|
||||
#define QLAFX00_WR_REG(ha, off, val) \
|
||||
WRT_REG_DWORD((ha)->cregbase + off, val)
|
||||
|
||||
struct qla_mt_iocb_rqst_fx00 {
|
||||
__le32 reserved_0;
|
||||
|
||||
__le16 func_type;
|
||||
uint8_t flags;
|
||||
uint8_t reserved_1;
|
||||
|
||||
__le32 dataword;
|
||||
|
||||
__le32 adapid;
|
||||
__le32 adapid_hi;
|
||||
|
||||
__le32 dataword_extra;
|
||||
|
||||
__le16 req_len;
|
||||
__le16 reserved_2;
|
||||
|
||||
__le16 rsp_len;
|
||||
__le16 reserved_3;
|
||||
};
|
||||
|
||||
struct qla_mt_iocb_rsp_fx00 {
|
||||
uint32_t reserved_1;
|
||||
|
||||
uint16_t func_type;
|
||||
__le16 ioctl_flags;
|
||||
|
||||
__le32 ioctl_data;
|
||||
|
||||
uint32_t adapid;
|
||||
uint32_t adapid_hi;
|
||||
|
||||
uint32_t reserved_2;
|
||||
__le32 seq_number;
|
||||
|
||||
uint8_t reserved_3[20];
|
||||
|
||||
int32_t res_count;
|
||||
|
||||
__le32 status;
|
||||
};
|
||||
|
||||
|
||||
#define MAILBOX_REGISTER_COUNT_FX00 16
|
||||
#define AEN_MAILBOX_REGISTER_COUNT_FX00 8
|
||||
#define MAX_FIBRE_DEVICES_FX00 512
|
||||
#define MAX_LUNS_FX00 0x1024
|
||||
#define MAX_TARGETS_FX00 MAX_ISA_DEVICES
|
||||
#define REQUEST_ENTRY_CNT_FX00 512 /* Number of request entries. */
|
||||
#define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
|
||||
|
||||
/*
|
||||
* Firmware state codes for QLAFX00 adapters
|
||||
*/
|
||||
#define FSTATE_FX00_CONFIG_WAIT 0x0000 /* Waiting for driver to issue
|
||||
* Initialize FW Mbox cmd
|
||||
*/
|
||||
#define FSTATE_FX00_INITIALIZED 0x1000 /* FW has been initialized by
|
||||
* the driver
|
||||
*/
|
||||
|
||||
#define FX00_DEF_RATOV 10
|
||||
|
||||
struct mr_data_fx00 {
|
||||
uint8_t symbolic_name[64];
|
||||
uint8_t serial_num[32];
|
||||
uint8_t hw_version[16];
|
||||
uint8_t fw_version[16];
|
||||
uint8_t uboot_version[16];
|
||||
uint8_t fru_serial_num[32];
|
||||
fc_port_t fcport; /* fcport used for requests
|
||||
* that are not linked
|
||||
* to a particular target
|
||||
*/
|
||||
uint8_t fw_hbt_en;
|
||||
uint8_t fw_hbt_cnt;
|
||||
uint8_t fw_hbt_miss_cnt;
|
||||
uint32_t old_fw_hbt_cnt;
|
||||
uint16_t fw_reset_timer_tick;
|
||||
uint8_t fw_reset_timer_exp;
|
||||
uint16_t fw_critemp_timer_tick;
|
||||
uint32_t old_aenmbx0_state;
|
||||
uint32_t critical_temperature;
|
||||
bool extended_io_enabled;
|
||||
bool host_info_resend;
|
||||
uint8_t hinfo_resend_timer_tick;
|
||||
};
|
||||
|
||||
#define QLAFX00_EXTENDED_IO_EN_MASK 0x20
|
||||
|
||||
/*
|
||||
* SoC Junction Temperature is stored in
|
||||
* bits 9:1 of SoC Junction Temperature Register
|
||||
* in a firmware specific format format.
|
||||
* To get the temperature in Celsius degrees
|
||||
* the value from this bitfiled should be converted
|
||||
* using this formula:
|
||||
* Temperature (degrees C) = ((3,153,000 - (10,000 * X)) / 13,825)
|
||||
* where X is the bit field value
|
||||
* this macro reads the register, extracts the bitfield value,
|
||||
* performs the calcualtions and returns temperature in Celsius
|
||||
*/
|
||||
#define QLAFX00_GET_TEMPERATURE(ha) ((3153000 - (10000 * \
|
||||
((QLAFX00_RD_REG(ha, QLAFX00_SOC_TEMP_REG) & 0x3FE) >> 1))) / 13825)
|
||||
|
||||
|
||||
#define QLAFX00_LOOP_DOWN_TIME 615 /* 600 */
|
||||
#define QLAFX00_HEARTBEAT_INTERVAL 6 /* number of seconds */
|
||||
#define QLAFX00_HEARTBEAT_MISS_CNT 3 /* number of miss */
|
||||
#define QLAFX00_RESET_INTERVAL 120 /* number of seconds */
|
||||
#define QLAFX00_MAX_RESET_INTERVAL 600 /* number of seconds */
|
||||
#define QLAFX00_CRITEMP_INTERVAL 60 /* number of seconds */
|
||||
#define QLAFX00_HINFO_RESEND_INTERVAL 60 /* number of seconds */
|
||||
|
||||
#define QLAFX00_CRITEMP_THRSHLD 80 /* Celsius degrees */
|
||||
|
||||
/* Max conncurrent IOs that can be queued */
|
||||
#define QLAFX00_MAX_CANQUEUE 1024
|
||||
|
||||
/* IOCTL IOCB abort success */
|
||||
#define QLAFX00_IOCTL_ICOB_ABORT_SUCCESS 0x68
|
||||
|
||||
#endif
|
||||
4518
drivers/scsi/qla2xxx/qla_nx.c
Normal file
4518
drivers/scsi/qla2xxx/qla_nx.c
Normal file
File diff suppressed because it is too large
Load diff
1202
drivers/scsi/qla2xxx/qla_nx.h
Normal file
1202
drivers/scsi/qla2xxx/qla_nx.h
Normal file
File diff suppressed because it is too large
Load diff
4079
drivers/scsi/qla2xxx/qla_nx2.c
Normal file
4079
drivers/scsi/qla2xxx/qla_nx2.c
Normal file
File diff suppressed because it is too large
Load diff
599
drivers/scsi/qla2xxx/qla_nx2.h
Normal file
599
drivers/scsi/qla2xxx/qla_nx2.h
Normal file
|
|
@ -0,0 +1,599 @@
|
|||
/*
|
||||
* QLogic Fibre Channel HBA Driver
|
||||
* Copyright (c) 2003-2014 QLogic Corporation
|
||||
*
|
||||
* See LICENSE.qla2xxx for copyright and licensing details.
|
||||
*/
|
||||
|
||||
#ifndef __QLA_NX2_H
|
||||
#define __QLA_NX2_H
|
||||
|
||||
#define QSNT_ACK_TOV 30
|
||||
#define INTENT_TO_RECOVER 0x01
|
||||
#define PROCEED_TO_RECOVER 0x02
|
||||
#define IDC_LOCK_RECOVERY_OWNER_MASK 0x3C
|
||||
#define IDC_LOCK_RECOVERY_STATE_MASK 0x3
|
||||
#define IDC_LOCK_RECOVERY_STATE_SHIFT_BITS 2
|
||||
|
||||
#define QLA8044_DRV_LOCK_MSLEEP 200
|
||||
#define QLA8044_ADDR_DDR_NET (0x0000000000000000ULL)
|
||||
#define QLA8044_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
|
||||
|
||||
#define MD_MIU_TEST_AGT_WRDATA_LO 0x410000A0
|
||||
#define MD_MIU_TEST_AGT_WRDATA_HI 0x410000A4
|
||||
#define MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B0
|
||||
#define MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B4
|
||||
#define MD_MIU_TEST_AGT_RDDATA_LO 0x410000A8
|
||||
#define MD_MIU_TEST_AGT_RDDATA_HI 0x410000AC
|
||||
#define MD_MIU_TEST_AGT_RDDATA_ULO 0x410000B8
|
||||
#define MD_MIU_TEST_AGT_RDDATA_UHI 0x410000BC
|
||||
|
||||
/* MIU_TEST_AGT_CTRL flags. work for SIU as well */
|
||||
#define MIU_TA_CTL_WRITE_ENABLE (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE)
|
||||
#define MIU_TA_CTL_WRITE_START (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE | \
|
||||
MIU_TA_CTL_START)
|
||||
#define MIU_TA_CTL_START_ENABLE (MIU_TA_CTL_START | MIU_TA_CTL_ENABLE)
|
||||
|
||||
/* Imbus address bit used to indicate a host address. This bit is
|
||||
* eliminated by the pcie bar and bar select before presentation
|
||||
* over pcie. */
|
||||
/* host memory via IMBUS */
|
||||
#define QLA8044_P2_ADDR_PCIE (0x0000000800000000ULL)
|
||||
#define QLA8044_P3_ADDR_PCIE (0x0000008000000000ULL)
|
||||
#define QLA8044_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
|
||||
#define QLA8044_ADDR_OCM0 (0x0000000200000000ULL)
|
||||
#define QLA8044_ADDR_OCM0_MAX (0x00000002000fffffULL)
|
||||
#define QLA8044_ADDR_OCM1 (0x0000000200400000ULL)
|
||||
#define QLA8044_ADDR_OCM1_MAX (0x00000002004fffffULL)
|
||||
#define QLA8044_ADDR_QDR_NET (0x0000000300000000ULL)
|
||||
#define QLA8044_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
|
||||
#define QLA8044_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
|
||||
#define QLA8044_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
|
||||
#define QLA8044_PCI_CRBSPACE ((unsigned long)0x06000000)
|
||||
#define QLA8044_PCI_DIRECT_CRB ((unsigned long)0x04400000)
|
||||
#define QLA8044_PCI_CAMQM ((unsigned long)0x04800000)
|
||||
#define QLA8044_PCI_CAMQM_MAX ((unsigned long)0x04ffffff)
|
||||
#define QLA8044_PCI_DDR_NET ((unsigned long)0x00000000)
|
||||
#define QLA8044_PCI_QDR_NET ((unsigned long)0x04000000)
|
||||
#define QLA8044_PCI_QDR_NET_MAX ((unsigned long)0x043fffff)
|
||||
|
||||
/* PCI Windowing for DDR regions. */
|
||||
#define QLA8044_ADDR_IN_RANGE(addr, low, high) \
|
||||
(((addr) <= (high)) && ((addr) >= (low)))
|
||||
|
||||
/* Indirectly Mapped Registers */
|
||||
#define QLA8044_FLASH_SPI_STATUS 0x2808E010
|
||||
#define QLA8044_FLASH_SPI_CONTROL 0x2808E014
|
||||
#define QLA8044_FLASH_STATUS 0x42100004
|
||||
#define QLA8044_FLASH_CONTROL 0x42110004
|
||||
#define QLA8044_FLASH_ADDR 0x42110008
|
||||
#define QLA8044_FLASH_WRDATA 0x4211000C
|
||||
#define QLA8044_FLASH_RDDATA 0x42110018
|
||||
#define QLA8044_FLASH_DIRECT_WINDOW 0x42110030
|
||||
#define QLA8044_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
|
||||
|
||||
/* Flash access regs */
|
||||
#define QLA8044_FLASH_LOCK 0x3850
|
||||
#define QLA8044_FLASH_UNLOCK 0x3854
|
||||
#define QLA8044_FLASH_LOCK_ID 0x3500
|
||||
|
||||
/* Driver Lock regs */
|
||||
#define QLA8044_DRV_LOCK 0x3868
|
||||
#define QLA8044_DRV_UNLOCK 0x386C
|
||||
#define QLA8044_DRV_LOCK_ID 0x3504
|
||||
#define QLA8044_DRV_LOCKRECOVERY 0x379C
|
||||
|
||||
/* IDC version */
|
||||
#define QLA8044_IDC_VER_MAJ_VALUE 0x1
|
||||
#define QLA8044_IDC_VER_MIN_VALUE 0x0
|
||||
|
||||
/* IDC Registers : Driver Coexistence Defines */
|
||||
#define QLA8044_CRB_IDC_VER_MAJOR 0x3780
|
||||
#define QLA8044_CRB_IDC_VER_MINOR 0x3798
|
||||
#define QLA8044_IDC_DRV_AUDIT 0x3794
|
||||
#define QLA8044_SRE_SHIM_CONTROL 0x0D200284
|
||||
#define QLA8044_PORT0_RXB_PAUSE_THRS 0x0B2003A4
|
||||
#define QLA8044_PORT1_RXB_PAUSE_THRS 0x0B2013A4
|
||||
#define QLA8044_PORT0_RXB_TC_MAX_CELL 0x0B200388
|
||||
#define QLA8044_PORT1_RXB_TC_MAX_CELL 0x0B201388
|
||||
#define QLA8044_PORT0_RXB_TC_STATS 0x0B20039C
|
||||
#define QLA8044_PORT1_RXB_TC_STATS 0x0B20139C
|
||||
#define QLA8044_PORT2_IFB_PAUSE_THRS 0x0B200704
|
||||
#define QLA8044_PORT3_IFB_PAUSE_THRS 0x0B201704
|
||||
|
||||
/* set value to pause threshold value */
|
||||
#define QLA8044_SET_PAUSE_VAL 0x0
|
||||
#define QLA8044_SET_TC_MAX_CELL_VAL 0x03FF03FF
|
||||
#define QLA8044_PEG_HALT_STATUS1 0x34A8
|
||||
#define QLA8044_PEG_HALT_STATUS2 0x34AC
|
||||
#define QLA8044_PEG_ALIVE_COUNTER 0x34B0 /* FW_HEARTBEAT */
|
||||
#define QLA8044_FW_CAPABILITIES 0x3528
|
||||
#define QLA8044_CRB_DRV_ACTIVE 0x3788 /* IDC_DRV_PRESENCE */
|
||||
#define QLA8044_CRB_DEV_STATE 0x3784 /* IDC_DEV_STATE */
|
||||
#define QLA8044_CRB_DRV_STATE 0x378C /* IDC_DRV_ACK */
|
||||
#define QLA8044_CRB_DRV_SCRATCH 0x3548
|
||||
#define QLA8044_CRB_DEV_PART_INFO1 0x37E0
|
||||
#define QLA8044_CRB_DEV_PART_INFO2 0x37E4
|
||||
#define QLA8044_FW_VER_MAJOR 0x3550
|
||||
#define QLA8044_FW_VER_MINOR 0x3554
|
||||
#define QLA8044_FW_VER_SUB 0x3558
|
||||
#define QLA8044_NPAR_STATE 0x359C
|
||||
#define QLA8044_FW_IMAGE_VALID 0x35FC
|
||||
#define QLA8044_CMDPEG_STATE 0x3650
|
||||
#define QLA8044_ASIC_TEMP 0x37B4
|
||||
#define QLA8044_FW_API 0x356C
|
||||
#define QLA8044_DRV_OP_MODE 0x3570
|
||||
#define QLA8044_CRB_WIN_BASE 0x3800
|
||||
#define QLA8044_CRB_WIN_FUNC(f) (QLA8044_CRB_WIN_BASE+((f)*4))
|
||||
#define QLA8044_SEM_LOCK_BASE 0x3840
|
||||
#define QLA8044_SEM_UNLOCK_BASE 0x3844
|
||||
#define QLA8044_SEM_LOCK_FUNC(f) (QLA8044_SEM_LOCK_BASE+((f)*8))
|
||||
#define QLA8044_SEM_UNLOCK_FUNC(f) (QLA8044_SEM_UNLOCK_BASE+((f)*8))
|
||||
#define QLA8044_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
|
||||
#define QLA8044_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
|
||||
#define QLA8044_MAX_LINK_SPEED(f) (0x36F0+(((f) / 4) * 4))
|
||||
#define QLA8044_LINK_SPEED_FACTOR 10
|
||||
#define QLA8044_FUN7_ACTIVE_INDEX 0x80
|
||||
|
||||
/* FLASH API Defines */
|
||||
#define QLA8044_FLASH_MAX_WAIT_USEC 100
|
||||
#define QLA8044_FLASH_LOCK_TIMEOUT 10000
|
||||
#define QLA8044_FLASH_SECTOR_SIZE 65536
|
||||
#define QLA8044_DRV_LOCK_TIMEOUT 2000
|
||||
#define QLA8044_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
|
||||
#define QLA8044_FLASH_WRITE_CMD 0xdacdacda
|
||||
#define QLA8044_FLASH_BUFFER_WRITE_CMD 0xcadcadca
|
||||
#define QLA8044_FLASH_READ_RETRY_COUNT 2000
|
||||
#define QLA8044_FLASH_STATUS_READY 0x6
|
||||
#define QLA8044_FLASH_BUFFER_WRITE_MIN 2
|
||||
#define QLA8044_FLASH_BUFFER_WRITE_MAX 64
|
||||
#define QLA8044_FLASH_STATUS_REG_POLL_DELAY 1
|
||||
#define QLA8044_ERASE_MODE 1
|
||||
#define QLA8044_WRITE_MODE 2
|
||||
#define QLA8044_DWORD_WRITE_MODE 3
|
||||
#define QLA8044_GLOBAL_RESET 0x38CC
|
||||
#define QLA8044_WILDCARD 0x38F0
|
||||
#define QLA8044_INFORMANT 0x38FC
|
||||
#define QLA8044_HOST_MBX_CTRL 0x3038
|
||||
#define QLA8044_FW_MBX_CTRL 0x303C
|
||||
#define QLA8044_BOOTLOADER_ADDR 0x355C
|
||||
#define QLA8044_BOOTLOADER_SIZE 0x3560
|
||||
#define QLA8044_FW_IMAGE_ADDR 0x3564
|
||||
#define QLA8044_MBX_INTR_ENABLE 0x1000
|
||||
#define QLA8044_MBX_INTR_MASK 0x1200
|
||||
|
||||
/* IDC Control Register bit defines */
|
||||
#define DONTRESET_BIT0 0x1
|
||||
#define GRACEFUL_RESET_BIT1 0x2
|
||||
|
||||
/* ISP8044 PEG_HALT_STATUS1 bits */
|
||||
#define QLA8044_HALT_STATUS_INFORMATIONAL (0x1 << 29)
|
||||
#define QLA8044_HALT_STATUS_FW_RESET (0x2 << 29)
|
||||
#define QLA8044_HALT_STATUS_UNRECOVERABLE (0x4 << 29)
|
||||
|
||||
/* Firmware image definitions */
|
||||
#define QLA8044_BOOTLOADER_FLASH_ADDR 0x10000
|
||||
#define QLA8044_BOOT_FROM_FLASH 0
|
||||
#define QLA8044_IDC_PARAM_ADDR 0x3e8020
|
||||
|
||||
/* FLASH related definitions */
|
||||
#define QLA8044_OPTROM_BURST_SIZE 0x100
|
||||
#define QLA8044_MAX_OPTROM_BURST_DWORDS (QLA8044_OPTROM_BURST_SIZE / 4)
|
||||
#define QLA8044_MIN_OPTROM_BURST_DWORDS 2
|
||||
#define QLA8044_SECTOR_SIZE (64 * 1024)
|
||||
|
||||
#define QLA8044_FLASH_SPI_CTL 0x4
|
||||
#define QLA8044_FLASH_FIRST_TEMP_VAL 0x00800000
|
||||
#define QLA8044_FLASH_SECOND_TEMP_VAL 0x00800001
|
||||
#define QLA8044_FLASH_FIRST_MS_PATTERN 0x43
|
||||
#define QLA8044_FLASH_SECOND_MS_PATTERN 0x7F
|
||||
#define QLA8044_FLASH_LAST_MS_PATTERN 0x7D
|
||||
#define QLA8044_FLASH_STATUS_WRITE_DEF_SIG 0xFD0100
|
||||
#define QLA8044_FLASH_SECOND_ERASE_MS_VAL 0x5
|
||||
#define QLA8044_FLASH_ERASE_SIG 0xFD0300
|
||||
#define QLA8044_FLASH_LAST_ERASE_MS_VAL 0x3D
|
||||
|
||||
/* Reset template definitions */
|
||||
#define QLA8044_MAX_RESET_SEQ_ENTRIES 16
|
||||
#define QLA8044_RESTART_TEMPLATE_SIZE 0x2000
|
||||
#define QLA8044_RESET_TEMPLATE_ADDR 0x4F0000
|
||||
#define QLA8044_RESET_SEQ_VERSION 0x0101
|
||||
|
||||
/* Reset template entry opcodes */
|
||||
#define OPCODE_NOP 0x0000
|
||||
#define OPCODE_WRITE_LIST 0x0001
|
||||
#define OPCODE_READ_WRITE_LIST 0x0002
|
||||
#define OPCODE_POLL_LIST 0x0004
|
||||
#define OPCODE_POLL_WRITE_LIST 0x0008
|
||||
#define OPCODE_READ_MODIFY_WRITE 0x0010
|
||||
#define OPCODE_SEQ_PAUSE 0x0020
|
||||
#define OPCODE_SEQ_END 0x0040
|
||||
#define OPCODE_TMPL_END 0x0080
|
||||
#define OPCODE_POLL_READ_LIST 0x0100
|
||||
|
||||
/* Template Header */
|
||||
#define RESET_TMPLT_HDR_SIGNATURE 0xCAFE
|
||||
#define QLA8044_IDC_DRV_CTRL 0x3790
|
||||
#define AF_8044_NO_FW_DUMP 27 /* 0x08000000 */
|
||||
|
||||
#define MINIDUMP_SIZE_36K 36864
|
||||
|
||||
struct qla8044_reset_template_hdr {
|
||||
uint16_t version;
|
||||
uint16_t signature;
|
||||
uint16_t size;
|
||||
uint16_t entries;
|
||||
uint16_t hdr_size;
|
||||
uint16_t checksum;
|
||||
uint16_t init_seq_offset;
|
||||
uint16_t start_seq_offset;
|
||||
} __packed;
|
||||
|
||||
/* Common Entry Header. */
|
||||
struct qla8044_reset_entry_hdr {
|
||||
uint16_t cmd;
|
||||
uint16_t size;
|
||||
uint16_t count;
|
||||
uint16_t delay;
|
||||
} __packed;
|
||||
|
||||
/* Generic poll entry type. */
|
||||
struct qla8044_poll {
|
||||
uint32_t test_mask;
|
||||
uint32_t test_value;
|
||||
} __packed;
|
||||
|
||||
/* Read modify write entry type. */
|
||||
struct qla8044_rmw {
|
||||
uint32_t test_mask;
|
||||
uint32_t xor_value;
|
||||
uint32_t or_value;
|
||||
uint8_t shl;
|
||||
uint8_t shr;
|
||||
uint8_t index_a;
|
||||
uint8_t rsvd;
|
||||
} __packed;
|
||||
|
||||
/* Generic Entry Item with 2 DWords. */
|
||||
struct qla8044_entry {
|
||||
uint32_t arg1;
|
||||
uint32_t arg2;
|
||||
} __packed;
|
||||
|
||||
/* Generic Entry Item with 4 DWords.*/
|
||||
struct qla8044_quad_entry {
|
||||
uint32_t dr_addr;
|
||||
uint32_t dr_value;
|
||||
uint32_t ar_addr;
|
||||
uint32_t ar_value;
|
||||
} __packed;
|
||||
|
||||
struct qla8044_reset_template {
|
||||
int seq_index;
|
||||
int seq_error;
|
||||
int array_index;
|
||||
uint32_t array[QLA8044_MAX_RESET_SEQ_ENTRIES];
|
||||
uint8_t *buff;
|
||||
uint8_t *stop_offset;
|
||||
uint8_t *start_offset;
|
||||
uint8_t *init_offset;
|
||||
struct qla8044_reset_template_hdr *hdr;
|
||||
uint8_t seq_end;
|
||||
uint8_t template_end;
|
||||
};
|
||||
|
||||
/* Driver_code is for driver to write some info about the entry
|
||||
* currently not used.
|
||||
*/
|
||||
struct qla8044_minidump_entry_hdr {
|
||||
uint32_t entry_type;
|
||||
uint32_t entry_size;
|
||||
uint32_t entry_capture_size;
|
||||
struct {
|
||||
uint8_t entry_capture_mask;
|
||||
uint8_t entry_code;
|
||||
uint8_t driver_code;
|
||||
uint8_t driver_flags;
|
||||
} d_ctrl;
|
||||
} __packed;
|
||||
|
||||
/* Read CRB entry header */
|
||||
struct qla8044_minidump_entry_crb {
|
||||
struct qla8044_minidump_entry_hdr h;
|
||||
uint32_t addr;
|
||||
struct {
|
||||
uint8_t addr_stride;
|
||||
uint8_t state_index_a;
|
||||
uint16_t poll_timeout;
|
||||
} crb_strd;
|
||||
uint32_t data_size;
|
||||
uint32_t op_count;
|
||||
|
||||
struct {
|
||||
uint8_t opcode;
|
||||
uint8_t state_index_v;
|
||||
uint8_t shl;
|
||||
uint8_t shr;
|
||||
} crb_ctrl;
|
||||
|
||||
uint32_t value_1;
|
||||
uint32_t value_2;
|
||||
uint32_t value_3;
|
||||
} __packed;
|
||||
|
||||
struct qla8044_minidump_entry_cache {
|
||||
struct qla8044_minidump_entry_hdr h;
|
||||
uint32_t tag_reg_addr;
|
||||
struct {
|
||||
uint16_t tag_value_stride;
|
||||
uint16_t init_tag_value;
|
||||
} addr_ctrl;
|
||||
uint32_t data_size;
|
||||
uint32_t op_count;
|
||||
uint32_t control_addr;
|
||||
struct {
|
||||
uint16_t write_value;
|
||||
uint8_t poll_mask;
|
||||
uint8_t poll_wait;
|
||||
} cache_ctrl;
|
||||
uint32_t read_addr;
|
||||
struct {
|
||||
uint8_t read_addr_stride;
|
||||
uint8_t read_addr_cnt;
|
||||
uint16_t rsvd_1;
|
||||
} read_ctrl;
|
||||
} __packed;
|
||||
|
||||
/* Read OCM */
|
||||
struct qla8044_minidump_entry_rdocm {
|
||||
struct qla8044_minidump_entry_hdr h;
|
||||
uint32_t rsvd_0;
|
||||
uint32_t rsvd_1;
|
||||
uint32_t data_size;
|
||||
uint32_t op_count;
|
||||
uint32_t rsvd_2;
|
||||
uint32_t rsvd_3;
|
||||
uint32_t read_addr;
|
||||
uint32_t read_addr_stride;
|
||||
} __packed;
|
||||
|
||||
/* Read Memory */
|
||||
struct qla8044_minidump_entry_rdmem {
|
||||
struct qla8044_minidump_entry_hdr h;
|
||||
uint32_t rsvd[6];
|
||||
uint32_t read_addr;
|
||||
uint32_t read_data_size;
|
||||
};
|
||||
|
||||
/* Read Memory: For Pex-DMA */
|
||||
struct qla8044_minidump_entry_rdmem_pex_dma {
|
||||
struct qla8044_minidump_entry_hdr h;
|
||||
uint32_t desc_card_addr;
|
||||
uint16_t dma_desc_cmd;
|
||||
uint8_t rsvd[2];
|
||||
uint32_t start_dma_cmd;
|
||||
uint8_t rsvd2[12];
|
||||
uint32_t read_addr;
|
||||
uint32_t read_data_size;
|
||||
} __packed;
|
||||
|
||||
/* Read ROM */
|
||||
struct qla8044_minidump_entry_rdrom {
|
||||
struct qla8044_minidump_entry_hdr h;
|
||||
uint32_t rsvd[6];
|
||||
uint32_t read_addr;
|
||||
uint32_t read_data_size;
|
||||
} __packed;
|
||||
|
||||
/* Mux entry */
|
||||
struct qla8044_minidump_entry_mux {
|
||||
struct qla8044_minidump_entry_hdr h;
|
||||
uint32_t select_addr;
|
||||
uint32_t rsvd_0;
|
||||
uint32_t data_size;
|
||||
uint32_t op_count;
|
||||
uint32_t select_value;
|
||||
uint32_t select_value_stride;
|
||||
uint32_t read_addr;
|
||||
uint32_t rsvd_1;
|
||||
} __packed;
|
||||
|
||||
/* Queue entry */
|
||||
struct qla8044_minidump_entry_queue {
|
||||
struct qla8044_minidump_entry_hdr h;
|
||||
uint32_t select_addr;
|
||||
struct {
|
||||
uint16_t queue_id_stride;
|
||||
uint16_t rsvd_0;
|
||||
} q_strd;
|
||||
uint32_t data_size;
|
||||
uint32_t op_count;
|
||||
uint32_t rsvd_1;
|
||||
uint32_t rsvd_2;
|
||||
uint32_t read_addr;
|
||||
struct {
|
||||
uint8_t read_addr_stride;
|
||||
uint8_t read_addr_cnt;
|
||||
uint16_t rsvd_3;
|
||||
} rd_strd;
|
||||
} __packed;
|
||||
|
||||
/* POLLRD Entry */
|
||||
struct qla8044_minidump_entry_pollrd {
|
||||
struct qla8044_minidump_entry_hdr h;
|
||||
uint32_t select_addr;
|
||||
uint32_t read_addr;
|
||||
uint32_t select_value;
|
||||
uint16_t select_value_stride;
|
||||
uint16_t op_count;
|
||||
uint32_t poll_wait;
|
||||
uint32_t poll_mask;
|
||||
uint32_t data_size;
|
||||
uint32_t rsvd_1;
|
||||
} __packed;
|
||||
|
||||
struct qla8044_minidump_entry_rddfe {
|
||||
struct qla8044_minidump_entry_hdr h;
|
||||
uint32_t addr_1;
|
||||
uint32_t value;
|
||||
uint8_t stride;
|
||||
uint8_t stride2;
|
||||
uint16_t count;
|
||||
uint32_t poll;
|
||||
uint32_t mask;
|
||||
uint32_t modify_mask;
|
||||
uint32_t data_size;
|
||||
uint32_t rsvd;
|
||||
|
||||
} __packed;
|
||||
|
||||
struct qla8044_minidump_entry_rdmdio {
|
||||
struct qla8044_minidump_entry_hdr h;
|
||||
|
||||
uint32_t addr_1;
|
||||
uint32_t addr_2;
|
||||
uint32_t value_1;
|
||||
uint8_t stride_1;
|
||||
uint8_t stride_2;
|
||||
uint16_t count;
|
||||
uint32_t poll;
|
||||
uint32_t mask;
|
||||
uint32_t value_2;
|
||||
uint32_t data_size;
|
||||
|
||||
} __packed;
|
||||
|
||||
struct qla8044_minidump_entry_pollwr {
|
||||
struct qla8044_minidump_entry_hdr h;
|
||||
uint32_t addr_1;
|
||||
uint32_t addr_2;
|
||||
uint32_t value_1;
|
||||
uint32_t value_2;
|
||||
uint32_t poll;
|
||||
uint32_t mask;
|
||||
uint32_t data_size;
|
||||
uint32_t rsvd;
|
||||
|
||||
} __packed;
|
||||
|
||||
/* RDMUX2 Entry */
|
||||
struct qla8044_minidump_entry_rdmux2 {
|
||||
struct qla8044_minidump_entry_hdr h;
|
||||
uint32_t select_addr_1;
|
||||
uint32_t select_addr_2;
|
||||
uint32_t select_value_1;
|
||||
uint32_t select_value_2;
|
||||
uint32_t op_count;
|
||||
uint32_t select_value_mask;
|
||||
uint32_t read_addr;
|
||||
uint8_t select_value_stride;
|
||||
uint8_t data_size;
|
||||
uint8_t rsvd[2];
|
||||
} __packed;
|
||||
|
||||
/* POLLRDMWR Entry */
|
||||
struct qla8044_minidump_entry_pollrdmwr {
|
||||
struct qla8044_minidump_entry_hdr h;
|
||||
uint32_t addr_1;
|
||||
uint32_t addr_2;
|
||||
uint32_t value_1;
|
||||
uint32_t value_2;
|
||||
uint32_t poll_wait;
|
||||
uint32_t poll_mask;
|
||||
uint32_t modify_mask;
|
||||
uint32_t data_size;
|
||||
} __packed;
|
||||
|
||||
/* IDC additional information */
|
||||
struct qla8044_idc_information {
|
||||
uint32_t request_desc; /* IDC request descriptor */
|
||||
uint32_t info1; /* IDC additional info */
|
||||
uint32_t info2; /* IDC additional info */
|
||||
uint32_t info3; /* IDC additional info */
|
||||
} __packed;
|
||||
|
||||
enum qla_regs {
|
||||
QLA8044_PEG_HALT_STATUS1_INDEX = 0,
|
||||
QLA8044_PEG_HALT_STATUS2_INDEX,
|
||||
QLA8044_PEG_ALIVE_COUNTER_INDEX,
|
||||
QLA8044_CRB_DRV_ACTIVE_INDEX,
|
||||
QLA8044_CRB_DEV_STATE_INDEX,
|
||||
QLA8044_CRB_DRV_STATE_INDEX,
|
||||
QLA8044_CRB_DRV_SCRATCH_INDEX,
|
||||
QLA8044_CRB_DEV_PART_INFO_INDEX,
|
||||
QLA8044_CRB_DRV_IDC_VERSION_INDEX,
|
||||
QLA8044_FW_VERSION_MAJOR_INDEX,
|
||||
QLA8044_FW_VERSION_MINOR_INDEX,
|
||||
QLA8044_FW_VERSION_SUB_INDEX,
|
||||
QLA8044_CRB_CMDPEG_STATE_INDEX,
|
||||
QLA8044_CRB_TEMP_STATE_INDEX,
|
||||
} __packed;
|
||||
|
||||
#define CRB_REG_INDEX_MAX 14
|
||||
#define CRB_CMDPEG_CHECK_RETRY_COUNT 60
|
||||
#define CRB_CMDPEG_CHECK_DELAY 500
|
||||
|
||||
static const uint32_t qla8044_reg_tbl[] = {
|
||||
QLA8044_PEG_HALT_STATUS1,
|
||||
QLA8044_PEG_HALT_STATUS2,
|
||||
QLA8044_PEG_ALIVE_COUNTER,
|
||||
QLA8044_CRB_DRV_ACTIVE,
|
||||
QLA8044_CRB_DEV_STATE,
|
||||
QLA8044_CRB_DRV_STATE,
|
||||
QLA8044_CRB_DRV_SCRATCH,
|
||||
QLA8044_CRB_DEV_PART_INFO1,
|
||||
QLA8044_CRB_IDC_VER_MAJOR,
|
||||
QLA8044_FW_VER_MAJOR,
|
||||
QLA8044_FW_VER_MINOR,
|
||||
QLA8044_FW_VER_SUB,
|
||||
QLA8044_CMDPEG_STATE,
|
||||
QLA8044_ASIC_TEMP,
|
||||
};
|
||||
|
||||
/* MiniDump Structures */
|
||||
|
||||
/* Driver_code is for driver to write some info about the entry
|
||||
* currently not used.
|
||||
*/
|
||||
#define QLA8044_SS_OCM_WNDREG_INDEX 3
|
||||
#define QLA8044_DBG_STATE_ARRAY_LEN 16
|
||||
#define QLA8044_DBG_CAP_SIZE_ARRAY_LEN 8
|
||||
#define QLA8044_DBG_RSVD_ARRAY_LEN 8
|
||||
#define QLA8044_DBG_OCM_WNDREG_ARRAY_LEN 16
|
||||
#define QLA8044_SS_PCI_INDEX 0
|
||||
#define QLA8044_RDDFE 38
|
||||
#define QLA8044_RDMDIO 39
|
||||
#define QLA8044_POLLWR 40
|
||||
|
||||
struct qla8044_minidump_template_hdr {
|
||||
uint32_t entry_type;
|
||||
uint32_t first_entry_offset;
|
||||
uint32_t size_of_template;
|
||||
uint32_t capture_debug_level;
|
||||
uint32_t num_of_entries;
|
||||
uint32_t version;
|
||||
uint32_t driver_timestamp;
|
||||
uint32_t checksum;
|
||||
|
||||
uint32_t driver_capture_mask;
|
||||
uint32_t driver_info_word2;
|
||||
uint32_t driver_info_word3;
|
||||
uint32_t driver_info_word4;
|
||||
|
||||
uint32_t saved_state_array[QLA8044_DBG_STATE_ARRAY_LEN];
|
||||
uint32_t capture_size_array[QLA8044_DBG_CAP_SIZE_ARRAY_LEN];
|
||||
uint32_t ocm_window_reg[QLA8044_DBG_OCM_WNDREG_ARRAY_LEN];
|
||||
};
|
||||
|
||||
struct qla8044_pex_dma_descriptor {
|
||||
struct {
|
||||
uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */
|
||||
uint8_t rsvd[2];
|
||||
uint16_t dma_desc_cmd;
|
||||
} cmd;
|
||||
uint64_t src_addr;
|
||||
uint64_t dma_bus_addr; /*0-3: desc-cmd, 4-7: pci-func, 8-15: desc-cmd*/
|
||||
uint8_t rsvd[24];
|
||||
} __packed;
|
||||
|
||||
#endif
|
||||
5908
drivers/scsi/qla2xxx/qla_os.c
Normal file
5908
drivers/scsi/qla2xxx/qla_os.c
Normal file
File diff suppressed because it is too large
Load diff
12
drivers/scsi/qla2xxx/qla_settings.h
Normal file
12
drivers/scsi/qla2xxx/qla_settings.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* QLogic Fibre Channel HBA Driver
|
||||
* Copyright (c) 2003-2014 QLogic Corporation
|
||||
*
|
||||
* See LICENSE.qla2xxx for copyright and licensing details.
|
||||
*/
|
||||
#define MAX_RETRIES_OF_ISP_ABORT 5
|
||||
|
||||
/* Max time to wait for the loop to be in LOOP_READY state */
|
||||
#define MAX_LOOP_TIMEOUT (60 * 5)
|
||||
|
||||
#include "qla_version.h"
|
||||
3216
drivers/scsi/qla2xxx/qla_sup.c
Normal file
3216
drivers/scsi/qla2xxx/qla_sup.c
Normal file
File diff suppressed because it is too large
Load diff
5965
drivers/scsi/qla2xxx/qla_target.c
Normal file
5965
drivers/scsi/qla2xxx/qla_target.c
Normal file
File diff suppressed because it is too large
Load diff
1114
drivers/scsi/qla2xxx/qla_target.h
Normal file
1114
drivers/scsi/qla2xxx/qla_target.h
Normal file
File diff suppressed because it is too large
Load diff
946
drivers/scsi/qla2xxx/qla_tmpl.c
Normal file
946
drivers/scsi/qla2xxx/qla_tmpl.c
Normal file
|
|
@ -0,0 +1,946 @@
|
|||
/*
|
||||
* QLogic Fibre Channel HBA Driver
|
||||
* Copyright (c) 2003-2014 QLogic Corporation
|
||||
*
|
||||
* See LICENSE.qla2xxx for copyright and licensing details.
|
||||
*/
|
||||
#include "qla_def.h"
|
||||
#include "qla_tmpl.h"
|
||||
|
||||
/* note default template is in big endian */
|
||||
static const uint32_t ql27xx_fwdt_default_template[] = {
|
||||
0x63000000, 0xa4000000, 0x7c050000, 0x00000000,
|
||||
0x30000000, 0x01000000, 0x00000000, 0xc0406eb4,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x04010000, 0x14000000, 0x00000000,
|
||||
0x02000000, 0x44000000, 0x09010000, 0x10000000,
|
||||
0x00000000, 0x02000000, 0x01010000, 0x1c000000,
|
||||
0x00000000, 0x02000000, 0x00600000, 0x00000000,
|
||||
0xc0000000, 0x01010000, 0x1c000000, 0x00000000,
|
||||
0x02000000, 0x00600000, 0x00000000, 0xcc000000,
|
||||
0x01010000, 0x1c000000, 0x00000000, 0x02000000,
|
||||
0x10600000, 0x00000000, 0xd4000000, 0x01010000,
|
||||
0x1c000000, 0x00000000, 0x02000000, 0x700f0000,
|
||||
0x00000060, 0xf0000000, 0x00010000, 0x18000000,
|
||||
0x00000000, 0x02000000, 0x00700000, 0x041000c0,
|
||||
0x00010000, 0x18000000, 0x00000000, 0x02000000,
|
||||
0x10700000, 0x041000c0, 0x00010000, 0x18000000,
|
||||
0x00000000, 0x02000000, 0x40700000, 0x041000c0,
|
||||
0x01010000, 0x1c000000, 0x00000000, 0x02000000,
|
||||
0x007c0000, 0x01000000, 0xc0000000, 0x00010000,
|
||||
0x18000000, 0x00000000, 0x02000000, 0x007c0000,
|
||||
0x040300c4, 0x00010000, 0x18000000, 0x00000000,
|
||||
0x02000000, 0x007c0000, 0x040100c0, 0x01010000,
|
||||
0x1c000000, 0x00000000, 0x02000000, 0x007c0000,
|
||||
0x00000000, 0xc0000000, 0x00010000, 0x18000000,
|
||||
0x00000000, 0x02000000, 0x007c0000, 0x04200000,
|
||||
0x0b010000, 0x18000000, 0x00000000, 0x02000000,
|
||||
0x0c000000, 0x00000000, 0x02010000, 0x20000000,
|
||||
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
|
||||
0xf0000000, 0x000000b0, 0x02010000, 0x20000000,
|
||||
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
|
||||
0xf0000000, 0x000010b0, 0x02010000, 0x20000000,
|
||||
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
|
||||
0xf0000000, 0x000020b0, 0x02010000, 0x20000000,
|
||||
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
|
||||
0xf0000000, 0x000030b0, 0x02010000, 0x20000000,
|
||||
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
|
||||
0xf0000000, 0x000040b0, 0x02010000, 0x20000000,
|
||||
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
|
||||
0xf0000000, 0x000050b0, 0x02010000, 0x20000000,
|
||||
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
|
||||
0xf0000000, 0x000060b0, 0x02010000, 0x20000000,
|
||||
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
|
||||
0xf0000000, 0x000070b0, 0x02010000, 0x20000000,
|
||||
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
|
||||
0xf0000000, 0x000080b0, 0x02010000, 0x20000000,
|
||||
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
|
||||
0xf0000000, 0x000090b0, 0x02010000, 0x20000000,
|
||||
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
|
||||
0xf0000000, 0x0000a0b0, 0x00010000, 0x18000000,
|
||||
0x00000000, 0x02000000, 0x0a000000, 0x040100c0,
|
||||
0x00010000, 0x18000000, 0x00000000, 0x02000000,
|
||||
0x0a000000, 0x04200080, 0x00010000, 0x18000000,
|
||||
0x00000000, 0x02000000, 0x00be0000, 0x041000c0,
|
||||
0x00010000, 0x18000000, 0x00000000, 0x02000000,
|
||||
0x10be0000, 0x041000c0, 0x00010000, 0x18000000,
|
||||
0x00000000, 0x02000000, 0x20be0000, 0x041000c0,
|
||||
0x00010000, 0x18000000, 0x00000000, 0x02000000,
|
||||
0x30be0000, 0x041000c0, 0x00010000, 0x18000000,
|
||||
0x00000000, 0x02000000, 0x00b00000, 0x041000c0,
|
||||
0x00010000, 0x18000000, 0x00000000, 0x02000000,
|
||||
0x10b00000, 0x041000c0, 0x00010000, 0x18000000,
|
||||
0x00000000, 0x02000000, 0x20b00000, 0x041000c0,
|
||||
0x00010000, 0x18000000, 0x00000000, 0x02000000,
|
||||
0x30b00000, 0x041000c0, 0x00010000, 0x18000000,
|
||||
0x00000000, 0x02000000, 0x00300000, 0x041000c0,
|
||||
0x00010000, 0x18000000, 0x00000000, 0x02000000,
|
||||
0x10300000, 0x041000c0, 0x00010000, 0x18000000,
|
||||
0x00000000, 0x02000000, 0x20300000, 0x041000c0,
|
||||
0x00010000, 0x18000000, 0x00000000, 0x02000000,
|
||||
0x30300000, 0x041000c0, 0x0a010000, 0x10000000,
|
||||
0x00000000, 0x02000000, 0x06010000, 0x1c000000,
|
||||
0x00000000, 0x02000000, 0x01000000, 0x00000200,
|
||||
0xff230200, 0x06010000, 0x1c000000, 0x00000000,
|
||||
0x02000000, 0x02000000, 0x00001000, 0x00000000,
|
||||
0x07010000, 0x18000000, 0x00000000, 0x02000000,
|
||||
0x00000000, 0x01000000, 0x07010000, 0x18000000,
|
||||
0x00000000, 0x02000000, 0x00000000, 0x02000000,
|
||||
0x07010000, 0x18000000, 0x00000000, 0x02000000,
|
||||
0x00000000, 0x03000000, 0x0d010000, 0x14000000,
|
||||
0x00000000, 0x02000000, 0x00000000, 0xff000000,
|
||||
0x10000000, 0x00000000, 0x00000080,
|
||||
};
|
||||
|
||||
static inline void __iomem *
|
||||
qla27xx_isp_reg(struct scsi_qla_host *vha)
|
||||
{
|
||||
return &vha->hw->iobase->isp24;
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla27xx_insert16(uint16_t value, void *buf, ulong *len)
|
||||
{
|
||||
if (buf) {
|
||||
buf += *len;
|
||||
*(__le16 *)buf = cpu_to_le16(value);
|
||||
}
|
||||
*len += sizeof(value);
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla27xx_insert32(uint32_t value, void *buf, ulong *len)
|
||||
{
|
||||
if (buf) {
|
||||
buf += *len;
|
||||
*(__le32 *)buf = cpu_to_le32(value);
|
||||
}
|
||||
*len += sizeof(value);
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla27xx_insertbuf(void *mem, ulong size, void *buf, ulong *len)
|
||||
{
|
||||
|
||||
if (buf && mem && size) {
|
||||
buf += *len;
|
||||
memcpy(buf, mem, size);
|
||||
}
|
||||
*len += size;
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla27xx_read8(void *window, void *buf, ulong *len)
|
||||
{
|
||||
uint8_t value = ~0;
|
||||
|
||||
if (buf) {
|
||||
value = RD_REG_BYTE((__iomem void *)window);
|
||||
}
|
||||
qla27xx_insert32(value, buf, len);
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla27xx_read16(void *window, void *buf, ulong *len)
|
||||
{
|
||||
uint16_t value = ~0;
|
||||
|
||||
if (buf) {
|
||||
value = RD_REG_WORD((__iomem void *)window);
|
||||
}
|
||||
qla27xx_insert32(value, buf, len);
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla27xx_read32(void *window, void *buf, ulong *len)
|
||||
{
|
||||
uint32_t value = ~0;
|
||||
|
||||
if (buf) {
|
||||
value = RD_REG_DWORD((__iomem void *)window);
|
||||
}
|
||||
qla27xx_insert32(value, buf, len);
|
||||
}
|
||||
|
||||
static inline void (*qla27xx_read_vector(uint width))(void *, void *, ulong *)
|
||||
{
|
||||
return
|
||||
(width == 1) ? qla27xx_read8 :
|
||||
(width == 2) ? qla27xx_read16 :
|
||||
qla27xx_read32;
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla27xx_read_reg(__iomem struct device_reg_24xx *reg,
|
||||
uint offset, void *buf, ulong *len)
|
||||
{
|
||||
void *window = (void *)reg + offset;
|
||||
|
||||
qla27xx_read32(window, buf, len);
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla27xx_write_reg(__iomem struct device_reg_24xx *reg,
|
||||
uint offset, uint32_t data, void *buf)
|
||||
{
|
||||
__iomem void *window = reg + offset;
|
||||
|
||||
if (buf) {
|
||||
WRT_REG_DWORD(window, data);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla27xx_read_window(__iomem struct device_reg_24xx *reg,
|
||||
uint32_t addr, uint offset, uint count, uint width, void *buf,
|
||||
ulong *len)
|
||||
{
|
||||
void *window = (void *)reg + offset;
|
||||
void (*readn)(void *, void *, ulong *) = qla27xx_read_vector(width);
|
||||
|
||||
qla27xx_write_reg(reg, IOBASE_ADDR, addr, buf);
|
||||
while (count--) {
|
||||
qla27xx_insert32(addr, buf, len);
|
||||
readn(window, buf, len);
|
||||
window += width;
|
||||
addr++;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla27xx_skip_entry(struct qla27xx_fwdt_entry *ent, void *buf)
|
||||
{
|
||||
if (buf)
|
||||
ent->hdr.driver_flags |= DRIVER_FLAG_SKIP_ENTRY;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t0(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd100,
|
||||
"%s: nop [%lx]\n", __func__, *len);
|
||||
qla27xx_skip_entry(ent, buf);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t255(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd1ff,
|
||||
"%s: end [%lx]\n", __func__, *len);
|
||||
qla27xx_skip_entry(ent, buf);
|
||||
|
||||
/* terminate */
|
||||
return true;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t256(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd200,
|
||||
"%s: rdio t1 [%lx]\n", __func__, *len);
|
||||
qla27xx_read_window(reg, ent->t256.base_addr, ent->t256.pci_offset,
|
||||
ent->t256.reg_count, ent->t256.reg_width, buf, len);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t257(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd201,
|
||||
"%s: wrio t1 [%lx]\n", __func__, *len);
|
||||
qla27xx_write_reg(reg, IOBASE_ADDR, ent->t257.base_addr, buf);
|
||||
qla27xx_write_reg(reg, ent->t257.pci_offset, ent->t257.write_data, buf);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t258(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd202,
|
||||
"%s: rdio t2 [%lx]\n", __func__, *len);
|
||||
qla27xx_write_reg(reg, ent->t258.banksel_offset, ent->t258.bank, buf);
|
||||
qla27xx_read_window(reg, ent->t258.base_addr, ent->t258.pci_offset,
|
||||
ent->t258.reg_count, ent->t258.reg_width, buf, len);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t259(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd203,
|
||||
"%s: wrio t2 [%lx]\n", __func__, *len);
|
||||
qla27xx_write_reg(reg, IOBASE_ADDR, ent->t259.base_addr, buf);
|
||||
qla27xx_write_reg(reg, ent->t259.banksel_offset, ent->t259.bank, buf);
|
||||
qla27xx_write_reg(reg, ent->t259.pci_offset, ent->t259.write_data, buf);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t260(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd204,
|
||||
"%s: rdpci [%lx]\n", __func__, *len);
|
||||
qla27xx_insert32(ent->t260.pci_offset, buf, len);
|
||||
qla27xx_read_reg(reg, ent->t260.pci_offset, buf, len);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t261(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd205,
|
||||
"%s: wrpci [%lx]\n", __func__, *len);
|
||||
qla27xx_write_reg(reg, ent->t261.pci_offset, ent->t261.write_data, buf);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t262(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
ulong dwords;
|
||||
ulong start;
|
||||
ulong end;
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd206,
|
||||
"%s: rdram(%x) [%lx]\n", __func__, ent->t262.ram_area, *len);
|
||||
start = ent->t262.start_addr;
|
||||
end = ent->t262.end_addr;
|
||||
|
||||
if (ent->t262.ram_area == T262_RAM_AREA_CRITICAL_RAM) {
|
||||
;
|
||||
} else if (ent->t262.ram_area == T262_RAM_AREA_EXTERNAL_RAM) {
|
||||
end = vha->hw->fw_memory_size;
|
||||
if (buf)
|
||||
ent->t262.end_addr = end;
|
||||
} else if (ent->t262.ram_area == T262_RAM_AREA_SHARED_RAM) {
|
||||
start = vha->hw->fw_shared_ram_start;
|
||||
end = vha->hw->fw_shared_ram_end;
|
||||
if (buf) {
|
||||
ent->t262.start_addr = start;
|
||||
ent->t262.end_addr = end;
|
||||
}
|
||||
} else {
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd022,
|
||||
"%s: unknown area %x\n", __func__, ent->t262.ram_area);
|
||||
qla27xx_skip_entry(ent, buf);
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (end < start || end == 0) {
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd023,
|
||||
"%s: unusable range (start=%x end=%x)\n", __func__,
|
||||
ent->t262.end_addr, ent->t262.start_addr);
|
||||
qla27xx_skip_entry(ent, buf);
|
||||
goto done;
|
||||
}
|
||||
|
||||
dwords = end - start + 1;
|
||||
if (buf) {
|
||||
buf += *len;
|
||||
qla24xx_dump_ram(vha->hw, start, buf, dwords, &buf);
|
||||
}
|
||||
*len += dwords * sizeof(uint32_t);
|
||||
done:
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
uint count = 0;
|
||||
uint i;
|
||||
uint length;
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd207,
|
||||
"%s: getq(%x) [%lx]\n", __func__, ent->t263.queue_type, *len);
|
||||
if (ent->t263.queue_type == T263_QUEUE_TYPE_REQ) {
|
||||
for (i = 0; i < vha->hw->max_req_queues; i++) {
|
||||
struct req_que *req = vha->hw->req_q_map[i];
|
||||
if (req || !buf) {
|
||||
length = req ?
|
||||
req->length : REQUEST_ENTRY_CNT_24XX;
|
||||
qla27xx_insert16(i, buf, len);
|
||||
qla27xx_insert16(length, buf, len);
|
||||
qla27xx_insertbuf(req ? req->ring : NULL,
|
||||
length * sizeof(*req->ring), buf, len);
|
||||
count++;
|
||||
}
|
||||
}
|
||||
} else if (ent->t263.queue_type == T263_QUEUE_TYPE_RSP) {
|
||||
for (i = 0; i < vha->hw->max_rsp_queues; i++) {
|
||||
struct rsp_que *rsp = vha->hw->rsp_q_map[i];
|
||||
if (rsp || !buf) {
|
||||
length = rsp ?
|
||||
rsp->length : RESPONSE_ENTRY_CNT_MQ;
|
||||
qla27xx_insert16(i, buf, len);
|
||||
qla27xx_insert16(length, buf, len);
|
||||
qla27xx_insertbuf(rsp ? rsp->ring : NULL,
|
||||
length * sizeof(*rsp->ring), buf, len);
|
||||
count++;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd026,
|
||||
"%s: unknown queue %x\n", __func__, ent->t263.queue_type);
|
||||
qla27xx_skip_entry(ent, buf);
|
||||
}
|
||||
|
||||
if (buf)
|
||||
ent->t263.num_queues = count;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t264(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd208,
|
||||
"%s: getfce [%lx]\n", __func__, *len);
|
||||
if (vha->hw->fce) {
|
||||
if (buf) {
|
||||
ent->t264.fce_trace_size = FCE_SIZE;
|
||||
ent->t264.write_pointer = vha->hw->fce_wr;
|
||||
ent->t264.base_pointer = vha->hw->fce_dma;
|
||||
ent->t264.fce_enable_mb0 = vha->hw->fce_mb[0];
|
||||
ent->t264.fce_enable_mb2 = vha->hw->fce_mb[2];
|
||||
ent->t264.fce_enable_mb3 = vha->hw->fce_mb[3];
|
||||
ent->t264.fce_enable_mb4 = vha->hw->fce_mb[4];
|
||||
ent->t264.fce_enable_mb5 = vha->hw->fce_mb[5];
|
||||
ent->t264.fce_enable_mb6 = vha->hw->fce_mb[6];
|
||||
}
|
||||
qla27xx_insertbuf(vha->hw->fce, FCE_SIZE, buf, len);
|
||||
} else {
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd027,
|
||||
"%s: missing fce\n", __func__);
|
||||
qla27xx_skip_entry(ent, buf);
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t265(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd209,
|
||||
"%s: pause risc [%lx]\n", __func__, *len);
|
||||
if (buf)
|
||||
qla24xx_pause_risc(reg, vha->hw);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t266(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd20a,
|
||||
"%s: reset risc [%lx]\n", __func__, *len);
|
||||
if (buf)
|
||||
qla24xx_soft_reset(vha->hw);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t267(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd20b,
|
||||
"%s: dis intr [%lx]\n", __func__, *len);
|
||||
qla27xx_write_reg(reg, ent->t267.pci_offset, ent->t267.data, buf);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t268(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd20c,
|
||||
"%s: gethb(%x) [%lx]\n", __func__, ent->t268.buf_type, *len);
|
||||
if (ent->t268.buf_type == T268_BUF_TYPE_EXTD_TRACE) {
|
||||
if (vha->hw->eft) {
|
||||
if (buf) {
|
||||
ent->t268.buf_size = EFT_SIZE;
|
||||
ent->t268.start_addr = vha->hw->eft_dma;
|
||||
}
|
||||
qla27xx_insertbuf(vha->hw->eft, EFT_SIZE, buf, len);
|
||||
} else {
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd028,
|
||||
"%s: missing eft\n", __func__);
|
||||
qla27xx_skip_entry(ent, buf);
|
||||
}
|
||||
} else {
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd02b,
|
||||
"%s: unknown buffer %x\n", __func__, ent->t268.buf_type);
|
||||
qla27xx_skip_entry(ent, buf);
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t269(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd20d,
|
||||
"%s: scratch [%lx]\n", __func__, *len);
|
||||
qla27xx_insert32(0xaaaaaaaa, buf, len);
|
||||
qla27xx_insert32(0xbbbbbbbb, buf, len);
|
||||
qla27xx_insert32(0xcccccccc, buf, len);
|
||||
qla27xx_insert32(0xdddddddd, buf, len);
|
||||
qla27xx_insert32(*len + sizeof(uint32_t), buf, len);
|
||||
if (buf)
|
||||
ent->t269.scratch_size = 5 * sizeof(uint32_t);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t270(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
||||
ulong dwords = ent->t270.count;
|
||||
ulong addr = ent->t270.addr;
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd20e,
|
||||
"%s: rdremreg [%lx]\n", __func__, *len);
|
||||
qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf);
|
||||
while (dwords--) {
|
||||
qla27xx_write_reg(reg, 0xc0, addr|0x80000000, buf);
|
||||
qla27xx_insert32(addr, buf, len);
|
||||
qla27xx_read_reg(reg, 0xc4, buf, len);
|
||||
addr += sizeof(uint32_t);
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t271(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
||||
ulong addr = ent->t271.addr;
|
||||
ulong data = ent->t271.data;
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd20f,
|
||||
"%s: wrremreg [%lx]\n", __func__, *len);
|
||||
qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf);
|
||||
qla27xx_write_reg(reg, 0xc4, data, buf);
|
||||
qla27xx_write_reg(reg, 0xc0, addr, buf);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t272(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
ulong dwords = ent->t272.count;
|
||||
ulong start = ent->t272.addr;
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd210,
|
||||
"%s: rdremram [%lx]\n", __func__, *len);
|
||||
if (buf) {
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd02c,
|
||||
"%s: @%lx -> (%lx dwords)\n", __func__, start, dwords);
|
||||
buf += *len;
|
||||
qla27xx_dump_mpi_ram(vha->hw, start, buf, dwords, &buf);
|
||||
}
|
||||
*len += dwords * sizeof(uint32_t);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t273(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
ulong dwords = ent->t273.count;
|
||||
ulong addr = ent->t273.addr;
|
||||
uint32_t value;
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd211,
|
||||
"%s: pcicfg [%lx]\n", __func__, *len);
|
||||
while (dwords--) {
|
||||
value = ~0;
|
||||
if (pci_read_config_dword(vha->hw->pdev, addr, &value))
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd02d,
|
||||
"%s: failed pcicfg read at %lx\n", __func__, addr);
|
||||
qla27xx_insert32(addr, buf, len);
|
||||
qla27xx_insert32(value, buf, len);
|
||||
addr += sizeof(uint32_t);
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
uint count = 0;
|
||||
uint i;
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd212,
|
||||
"%s: getqsh(%x) [%lx]\n", __func__, ent->t274.queue_type, *len);
|
||||
if (ent->t274.queue_type == T274_QUEUE_TYPE_REQ_SHAD) {
|
||||
for (i = 0; i < vha->hw->max_req_queues; i++) {
|
||||
struct req_que *req = vha->hw->req_q_map[i];
|
||||
if (req || !buf) {
|
||||
qla27xx_insert16(i, buf, len);
|
||||
qla27xx_insert16(1, buf, len);
|
||||
qla27xx_insert32(req && req->out_ptr ?
|
||||
*req->out_ptr : 0, buf, len);
|
||||
count++;
|
||||
}
|
||||
}
|
||||
} else if (ent->t274.queue_type == T274_QUEUE_TYPE_RSP_SHAD) {
|
||||
for (i = 0; i < vha->hw->max_rsp_queues; i++) {
|
||||
struct rsp_que *rsp = vha->hw->rsp_q_map[i];
|
||||
if (rsp || !buf) {
|
||||
qla27xx_insert16(i, buf, len);
|
||||
qla27xx_insert16(1, buf, len);
|
||||
qla27xx_insert32(rsp && rsp->in_ptr ?
|
||||
*rsp->in_ptr : 0, buf, len);
|
||||
count++;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd02f,
|
||||
"%s: unknown queue %x\n", __func__, ent->t274.queue_type);
|
||||
qla27xx_skip_entry(ent, buf);
|
||||
}
|
||||
|
||||
if (buf)
|
||||
ent->t274.num_queues = count;
|
||||
|
||||
if (!count)
|
||||
qla27xx_skip_entry(ent, buf);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_t275(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
ulong offset = offsetof(typeof(*ent), t275.buffer);
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd213,
|
||||
"%s: buffer(%x) [%lx]\n", __func__, ent->t275.length, *len);
|
||||
if (!ent->t275.length) {
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd020,
|
||||
"%s: buffer zero length\n", __func__);
|
||||
qla27xx_skip_entry(ent, buf);
|
||||
goto done;
|
||||
}
|
||||
if (offset + ent->t275.length > ent->hdr.entry_size) {
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd030,
|
||||
"%s: buffer overflow\n", __func__);
|
||||
qla27xx_skip_entry(ent, buf);
|
||||
goto done;
|
||||
}
|
||||
|
||||
qla27xx_insertbuf(ent->t275.buffer, ent->t275.length, buf, len);
|
||||
done:
|
||||
return false;
|
||||
}
|
||||
|
||||
static int
|
||||
qla27xx_fwdt_entry_other(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
||||
{
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd2ff,
|
||||
"%s: type %x [%lx]\n", __func__, ent->hdr.entry_type, *len);
|
||||
qla27xx_skip_entry(ent, buf);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
struct qla27xx_fwdt_entry_call {
|
||||
uint type;
|
||||
int (*call)(
|
||||
struct scsi_qla_host *,
|
||||
struct qla27xx_fwdt_entry *,
|
||||
void *,
|
||||
ulong *);
|
||||
};
|
||||
|
||||
static struct qla27xx_fwdt_entry_call ql27xx_fwdt_entry_call_list[] = {
|
||||
{ ENTRY_TYPE_NOP , qla27xx_fwdt_entry_t0 } ,
|
||||
{ ENTRY_TYPE_TMP_END , qla27xx_fwdt_entry_t255 } ,
|
||||
{ ENTRY_TYPE_RD_IOB_T1 , qla27xx_fwdt_entry_t256 } ,
|
||||
{ ENTRY_TYPE_WR_IOB_T1 , qla27xx_fwdt_entry_t257 } ,
|
||||
{ ENTRY_TYPE_RD_IOB_T2 , qla27xx_fwdt_entry_t258 } ,
|
||||
{ ENTRY_TYPE_WR_IOB_T2 , qla27xx_fwdt_entry_t259 } ,
|
||||
{ ENTRY_TYPE_RD_PCI , qla27xx_fwdt_entry_t260 } ,
|
||||
{ ENTRY_TYPE_WR_PCI , qla27xx_fwdt_entry_t261 } ,
|
||||
{ ENTRY_TYPE_RD_RAM , qla27xx_fwdt_entry_t262 } ,
|
||||
{ ENTRY_TYPE_GET_QUEUE , qla27xx_fwdt_entry_t263 } ,
|
||||
{ ENTRY_TYPE_GET_FCE , qla27xx_fwdt_entry_t264 } ,
|
||||
{ ENTRY_TYPE_PSE_RISC , qla27xx_fwdt_entry_t265 } ,
|
||||
{ ENTRY_TYPE_RST_RISC , qla27xx_fwdt_entry_t266 } ,
|
||||
{ ENTRY_TYPE_DIS_INTR , qla27xx_fwdt_entry_t267 } ,
|
||||
{ ENTRY_TYPE_GET_HBUF , qla27xx_fwdt_entry_t268 } ,
|
||||
{ ENTRY_TYPE_SCRATCH , qla27xx_fwdt_entry_t269 } ,
|
||||
{ ENTRY_TYPE_RDREMREG , qla27xx_fwdt_entry_t270 } ,
|
||||
{ ENTRY_TYPE_WRREMREG , qla27xx_fwdt_entry_t271 } ,
|
||||
{ ENTRY_TYPE_RDREMRAM , qla27xx_fwdt_entry_t272 } ,
|
||||
{ ENTRY_TYPE_PCICFG , qla27xx_fwdt_entry_t273 } ,
|
||||
{ ENTRY_TYPE_GET_SHADOW , qla27xx_fwdt_entry_t274 } ,
|
||||
{ ENTRY_TYPE_WRITE_BUF , qla27xx_fwdt_entry_t275 } ,
|
||||
{ -1 , qla27xx_fwdt_entry_other }
|
||||
};
|
||||
|
||||
static inline int (*qla27xx_find_entry(uint type))
|
||||
(struct scsi_qla_host *, struct qla27xx_fwdt_entry *, void *, ulong *)
|
||||
{
|
||||
struct qla27xx_fwdt_entry_call *list = ql27xx_fwdt_entry_call_list;
|
||||
|
||||
while (list->type < type)
|
||||
list++;
|
||||
|
||||
if (list->type == type)
|
||||
return list->call;
|
||||
return qla27xx_fwdt_entry_other;
|
||||
}
|
||||
|
||||
static inline void *
|
||||
qla27xx_next_entry(void *p)
|
||||
{
|
||||
struct qla27xx_fwdt_entry *ent = p;
|
||||
|
||||
return p + ent->hdr.entry_size;
|
||||
}
|
||||
|
||||
static void
|
||||
qla27xx_walk_template(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_template *tmp, void *buf, ulong *len)
|
||||
{
|
||||
struct qla27xx_fwdt_entry *ent = (void *)tmp + tmp->entry_offset;
|
||||
ulong count = tmp->entry_count;
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd01a,
|
||||
"%s: entry count %lx\n", __func__, count);
|
||||
while (count--) {
|
||||
if (qla27xx_find_entry(ent->hdr.entry_type)(vha, ent, buf, len))
|
||||
break;
|
||||
ent = qla27xx_next_entry(ent);
|
||||
}
|
||||
|
||||
if (count)
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd018,
|
||||
"%s: residual count (%lx)\n", __func__, count);
|
||||
|
||||
if (ent->hdr.entry_type != ENTRY_TYPE_TMP_END)
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd019,
|
||||
"%s: missing end (%lx)\n", __func__, count);
|
||||
|
||||
ql_dbg(ql_dbg_misc, vha, 0xd01b,
|
||||
"%s: len=%lx\n", __func__, *len);
|
||||
}
|
||||
|
||||
static void
|
||||
qla27xx_time_stamp(struct qla27xx_fwdt_template *tmp)
|
||||
{
|
||||
tmp->capture_timestamp = jiffies;
|
||||
}
|
||||
|
||||
static void
|
||||
qla27xx_driver_info(struct qla27xx_fwdt_template *tmp)
|
||||
{
|
||||
uint8_t v[] = { 0, 0, 0, 0, 0, 0 };
|
||||
int rval = 0;
|
||||
|
||||
rval = sscanf(qla2x00_version_str, "%hhu.%hhu.%hhu.%hhu.%hhu.%hhu",
|
||||
v+0, v+1, v+2, v+3, v+4, v+5);
|
||||
|
||||
tmp->driver_info[0] = v[3] << 24 | v[2] << 16 | v[1] << 8 | v[0];
|
||||
tmp->driver_info[1] = v[5] << 8 | v[4];
|
||||
tmp->driver_info[2] = 0x12345678;
|
||||
}
|
||||
|
||||
static void
|
||||
qla27xx_firmware_info(struct qla27xx_fwdt_template *tmp,
|
||||
struct scsi_qla_host *vha)
|
||||
{
|
||||
tmp->firmware_version[0] = vha->hw->fw_major_version;
|
||||
tmp->firmware_version[1] = vha->hw->fw_minor_version;
|
||||
tmp->firmware_version[2] = vha->hw->fw_subminor_version;
|
||||
tmp->firmware_version[3] =
|
||||
vha->hw->fw_attributes_h << 16 | vha->hw->fw_attributes;
|
||||
tmp->firmware_version[4] =
|
||||
vha->hw->fw_attributes_ext[1] << 16 | vha->hw->fw_attributes_ext[0];
|
||||
}
|
||||
|
||||
static void
|
||||
ql27xx_edit_template(struct scsi_qla_host *vha,
|
||||
struct qla27xx_fwdt_template *tmp)
|
||||
{
|
||||
qla27xx_time_stamp(tmp);
|
||||
qla27xx_driver_info(tmp);
|
||||
qla27xx_firmware_info(tmp, vha);
|
||||
}
|
||||
|
||||
static inline uint32_t
|
||||
qla27xx_template_checksum(void *p, ulong size)
|
||||
{
|
||||
uint32_t *buf = p;
|
||||
uint64_t sum = 0;
|
||||
|
||||
size /= sizeof(*buf);
|
||||
|
||||
while (size--)
|
||||
sum += *buf++;
|
||||
|
||||
sum = (sum & 0xffffffff) + (sum >> 32);
|
||||
|
||||
return ~sum;
|
||||
}
|
||||
|
||||
static inline int
|
||||
qla27xx_verify_template_checksum(struct qla27xx_fwdt_template *tmp)
|
||||
{
|
||||
return qla27xx_template_checksum(tmp, tmp->template_size) == 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
qla27xx_verify_template_header(struct qla27xx_fwdt_template *tmp)
|
||||
{
|
||||
return tmp->template_type == TEMPLATE_TYPE_FWDUMP;
|
||||
}
|
||||
|
||||
static void
|
||||
qla27xx_execute_fwdt_template(struct scsi_qla_host *vha)
|
||||
{
|
||||
struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template;
|
||||
ulong len;
|
||||
|
||||
if (qla27xx_fwdt_template_valid(tmp)) {
|
||||
len = tmp->template_size;
|
||||
tmp = memcpy(vha->hw->fw_dump, tmp, len);
|
||||
ql27xx_edit_template(vha, tmp);
|
||||
qla27xx_walk_template(vha, tmp, tmp, &len);
|
||||
vha->hw->fw_dump_len = len;
|
||||
vha->hw->fw_dumped = 1;
|
||||
}
|
||||
}
|
||||
|
||||
ulong
|
||||
qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *vha)
|
||||
{
|
||||
struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template;
|
||||
ulong len = 0;
|
||||
|
||||
if (qla27xx_fwdt_template_valid(tmp)) {
|
||||
len = tmp->template_size;
|
||||
qla27xx_walk_template(vha, tmp, NULL, &len);
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
ulong
|
||||
qla27xx_fwdt_template_size(void *p)
|
||||
{
|
||||
struct qla27xx_fwdt_template *tmp = p;
|
||||
|
||||
return tmp->template_size;
|
||||
}
|
||||
|
||||
ulong
|
||||
qla27xx_fwdt_template_default_size(void)
|
||||
{
|
||||
return sizeof(ql27xx_fwdt_default_template);
|
||||
}
|
||||
|
||||
const void *
|
||||
qla27xx_fwdt_template_default(void)
|
||||
{
|
||||
return ql27xx_fwdt_default_template;
|
||||
}
|
||||
|
||||
int
|
||||
qla27xx_fwdt_template_valid(void *p)
|
||||
{
|
||||
struct qla27xx_fwdt_template *tmp = p;
|
||||
|
||||
if (!qla27xx_verify_template_header(tmp)) {
|
||||
ql_log(ql_log_warn, NULL, 0xd01c,
|
||||
"%s: template type %x\n", __func__, tmp->template_type);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!qla27xx_verify_template_checksum(tmp)) {
|
||||
ql_log(ql_log_warn, NULL, 0xd01d,
|
||||
"%s: failed template checksum\n", __func__);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void
|
||||
qla27xx_fwdump(scsi_qla_host_t *vha, int hardware_locked)
|
||||
{
|
||||
ulong flags = 0;
|
||||
|
||||
if (!hardware_locked)
|
||||
spin_lock_irqsave(&vha->hw->hardware_lock, flags);
|
||||
|
||||
if (!vha->hw->fw_dump)
|
||||
ql_log(ql_log_warn, vha, 0xd01e, "fwdump buffer missing.\n");
|
||||
else if (!vha->hw->fw_dump_template)
|
||||
ql_log(ql_log_warn, vha, 0xd01f, "fwdump template missing.\n");
|
||||
else
|
||||
qla27xx_execute_fwdt_template(vha);
|
||||
|
||||
if (!hardware_locked)
|
||||
spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
|
||||
}
|
||||
224
drivers/scsi/qla2xxx/qla_tmpl.h
Normal file
224
drivers/scsi/qla2xxx/qla_tmpl.h
Normal file
|
|
@ -0,0 +1,224 @@
|
|||
/*
|
||||
* QLogic Fibre Channel HBA Driver
|
||||
* Copyright (c) 2003-2014 QLogic Corporation
|
||||
*
|
||||
* See LICENSE.qla2xxx for copyright and licensing details.
|
||||
*/
|
||||
|
||||
#ifndef __QLA_DMP27_H__
|
||||
#define __QLA_DMP27_H__
|
||||
|
||||
#define IOBASE_ADDR offsetof(struct device_reg_24xx, iobase_addr)
|
||||
|
||||
struct __packed qla27xx_fwdt_template {
|
||||
uint32_t template_type;
|
||||
uint32_t entry_offset;
|
||||
uint32_t template_size;
|
||||
uint32_t reserved_1;
|
||||
|
||||
uint32_t entry_count;
|
||||
uint32_t template_version;
|
||||
uint32_t capture_timestamp;
|
||||
uint32_t template_checksum;
|
||||
|
||||
uint32_t reserved_2;
|
||||
uint32_t driver_info[3];
|
||||
|
||||
uint32_t saved_state[16];
|
||||
|
||||
uint32_t reserved_3[8];
|
||||
uint32_t firmware_version[5];
|
||||
};
|
||||
|
||||
#define TEMPLATE_TYPE_FWDUMP 99
|
||||
|
||||
#define ENTRY_TYPE_NOP 0
|
||||
#define ENTRY_TYPE_TMP_END 255
|
||||
#define ENTRY_TYPE_RD_IOB_T1 256
|
||||
#define ENTRY_TYPE_WR_IOB_T1 257
|
||||
#define ENTRY_TYPE_RD_IOB_T2 258
|
||||
#define ENTRY_TYPE_WR_IOB_T2 259
|
||||
#define ENTRY_TYPE_RD_PCI 260
|
||||
#define ENTRY_TYPE_WR_PCI 261
|
||||
#define ENTRY_TYPE_RD_RAM 262
|
||||
#define ENTRY_TYPE_GET_QUEUE 263
|
||||
#define ENTRY_TYPE_GET_FCE 264
|
||||
#define ENTRY_TYPE_PSE_RISC 265
|
||||
#define ENTRY_TYPE_RST_RISC 266
|
||||
#define ENTRY_TYPE_DIS_INTR 267
|
||||
#define ENTRY_TYPE_GET_HBUF 268
|
||||
#define ENTRY_TYPE_SCRATCH 269
|
||||
#define ENTRY_TYPE_RDREMREG 270
|
||||
#define ENTRY_TYPE_WRREMREG 271
|
||||
#define ENTRY_TYPE_RDREMRAM 272
|
||||
#define ENTRY_TYPE_PCICFG 273
|
||||
#define ENTRY_TYPE_GET_SHADOW 274
|
||||
#define ENTRY_TYPE_WRITE_BUF 275
|
||||
|
||||
#define CAPTURE_FLAG_PHYS_ONLY BIT_0
|
||||
#define CAPTURE_FLAG_PHYS_VIRT BIT_1
|
||||
|
||||
#define DRIVER_FLAG_SKIP_ENTRY BIT_7
|
||||
|
||||
struct __packed qla27xx_fwdt_entry {
|
||||
struct __packed {
|
||||
uint32_t entry_type;
|
||||
uint32_t entry_size;
|
||||
uint32_t reserved_1;
|
||||
|
||||
uint8_t capture_flags;
|
||||
uint8_t reserved_2[2];
|
||||
uint8_t driver_flags;
|
||||
} hdr;
|
||||
union __packed {
|
||||
struct __packed {
|
||||
} t0;
|
||||
|
||||
struct __packed {
|
||||
} t255;
|
||||
|
||||
struct __packed {
|
||||
uint32_t base_addr;
|
||||
uint8_t reg_width;
|
||||
uint16_t reg_count;
|
||||
uint8_t pci_offset;
|
||||
} t256;
|
||||
|
||||
struct __packed {
|
||||
uint32_t base_addr;
|
||||
uint32_t write_data;
|
||||
uint8_t pci_offset;
|
||||
uint8_t reserved[3];
|
||||
} t257;
|
||||
|
||||
struct __packed {
|
||||
uint32_t base_addr;
|
||||
uint8_t reg_width;
|
||||
uint16_t reg_count;
|
||||
uint8_t pci_offset;
|
||||
uint8_t banksel_offset;
|
||||
uint8_t reserved[3];
|
||||
uint32_t bank;
|
||||
} t258;
|
||||
|
||||
struct __packed {
|
||||
uint32_t base_addr;
|
||||
uint32_t write_data;
|
||||
uint8_t reserved[2];
|
||||
uint8_t pci_offset;
|
||||
uint8_t banksel_offset;
|
||||
uint32_t bank;
|
||||
} t259;
|
||||
|
||||
struct __packed {
|
||||
uint8_t pci_offset;
|
||||
uint8_t reserved[3];
|
||||
} t260;
|
||||
|
||||
struct __packed {
|
||||
uint8_t pci_offset;
|
||||
uint8_t reserved[3];
|
||||
uint32_t write_data;
|
||||
} t261;
|
||||
|
||||
struct __packed {
|
||||
uint8_t ram_area;
|
||||
uint8_t reserved[3];
|
||||
uint32_t start_addr;
|
||||
uint32_t end_addr;
|
||||
} t262;
|
||||
|
||||
struct __packed {
|
||||
uint32_t num_queues;
|
||||
uint8_t queue_type;
|
||||
uint8_t reserved[3];
|
||||
} t263;
|
||||
|
||||
struct __packed {
|
||||
uint32_t fce_trace_size;
|
||||
uint64_t write_pointer;
|
||||
uint64_t base_pointer;
|
||||
uint32_t fce_enable_mb0;
|
||||
uint32_t fce_enable_mb2;
|
||||
uint32_t fce_enable_mb3;
|
||||
uint32_t fce_enable_mb4;
|
||||
uint32_t fce_enable_mb5;
|
||||
uint32_t fce_enable_mb6;
|
||||
} t264;
|
||||
|
||||
struct __packed {
|
||||
} t265;
|
||||
|
||||
struct __packed {
|
||||
} t266;
|
||||
|
||||
struct __packed {
|
||||
uint8_t pci_offset;
|
||||
uint8_t reserved[3];
|
||||
uint32_t data;
|
||||
} t267;
|
||||
|
||||
struct __packed {
|
||||
uint8_t buf_type;
|
||||
uint8_t reserved[3];
|
||||
uint32_t buf_size;
|
||||
uint64_t start_addr;
|
||||
} t268;
|
||||
|
||||
struct __packed {
|
||||
uint32_t scratch_size;
|
||||
} t269;
|
||||
|
||||
struct __packed {
|
||||
uint32_t addr;
|
||||
uint32_t count;
|
||||
} t270;
|
||||
|
||||
struct __packed {
|
||||
uint32_t addr;
|
||||
uint32_t data;
|
||||
} t271;
|
||||
|
||||
struct __packed {
|
||||
uint32_t addr;
|
||||
uint32_t count;
|
||||
} t272;
|
||||
|
||||
struct __packed {
|
||||
uint32_t addr;
|
||||
uint32_t count;
|
||||
} t273;
|
||||
|
||||
struct __packed {
|
||||
uint32_t num_queues;
|
||||
uint8_t queue_type;
|
||||
uint8_t reserved[3];
|
||||
} t274;
|
||||
|
||||
struct __packed {
|
||||
uint32_t length;
|
||||
uint8_t buffer[];
|
||||
} t275;
|
||||
};
|
||||
};
|
||||
|
||||
#define T262_RAM_AREA_CRITICAL_RAM 1
|
||||
#define T262_RAM_AREA_EXTERNAL_RAM 2
|
||||
#define T262_RAM_AREA_SHARED_RAM 3
|
||||
#define T262_RAM_AREA_DDR_RAM 4
|
||||
|
||||
#define T263_QUEUE_TYPE_REQ 1
|
||||
#define T263_QUEUE_TYPE_RSP 2
|
||||
#define T263_QUEUE_TYPE_ATIO 3
|
||||
|
||||
#define T268_BUF_TYPE_EXTD_TRACE 1
|
||||
#define T268_BUF_TYPE_EXCH_BUFOFF 2
|
||||
#define T268_BUF_TYPE_EXTD_LOGIN 3
|
||||
#define T268_BUF_TYPE_REQ_MIRROR 4
|
||||
#define T268_BUF_TYPE_RSP_MIRROR 5
|
||||
|
||||
#define T274_QUEUE_TYPE_REQ_SHAD 1
|
||||
#define T274_QUEUE_TYPE_RSP_SHAD 2
|
||||
#define T274_QUEUE_TYPE_ATIO_SHAD 3
|
||||
|
||||
#endif
|
||||
15
drivers/scsi/qla2xxx/qla_version.h
Normal file
15
drivers/scsi/qla2xxx/qla_version.h
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* QLogic Fibre Channel HBA Driver
|
||||
* Copyright (c) 2003-2014 QLogic Corporation
|
||||
*
|
||||
* See LICENSE.qla2xxx for copyright and licensing details.
|
||||
*/
|
||||
/*
|
||||
* Driver version
|
||||
*/
|
||||
#define QLA2XXX_VERSION "8.07.00.16-k"
|
||||
|
||||
#define QLA_DRIVER_MAJOR_VER 8
|
||||
#define QLA_DRIVER_MINOR_VER 7
|
||||
#define QLA_DRIVER_PATCH_VER 0
|
||||
#define QLA_DRIVER_BETA_VER 0
|
||||
2184
drivers/scsi/qla2xxx/tcm_qla2xxx.c
Normal file
2184
drivers/scsi/qla2xxx/tcm_qla2xxx.c
Normal file
File diff suppressed because it is too large
Load diff
83
drivers/scsi/qla2xxx/tcm_qla2xxx.h
Normal file
83
drivers/scsi/qla2xxx/tcm_qla2xxx.h
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
#include <target/target_core_base.h>
|
||||
#include <linux/btree.h>
|
||||
|
||||
#define TCM_QLA2XXX_VERSION "v0.1"
|
||||
/* length of ASCII WWPNs including pad */
|
||||
#define TCM_QLA2XXX_NAMELEN 32
|
||||
/*
|
||||
* Number of pre-allocated per-session tags, based upon the worst-case
|
||||
* per port number of iocbs
|
||||
*/
|
||||
#define TCM_QLA2XXX_DEFAULT_TAGS 2088
|
||||
|
||||
#include "qla_target.h"
|
||||
|
||||
struct tcm_qla2xxx_nacl {
|
||||
/* From libfc struct fc_rport->port_id */
|
||||
u32 nport_id;
|
||||
/* Binary World Wide unique Node Name for remote FC Initiator Nport */
|
||||
u64 nport_wwnn;
|
||||
/* ASCII formatted WWPN for FC Initiator Nport */
|
||||
char nport_name[TCM_QLA2XXX_NAMELEN];
|
||||
/* Pointer to qla_tgt_sess */
|
||||
struct qla_tgt_sess *qla_tgt_sess;
|
||||
/* Pointer to TCM FC nexus */
|
||||
struct se_session *nport_nexus;
|
||||
/* Returned by tcm_qla2xxx_make_nodeacl() */
|
||||
struct se_node_acl se_node_acl;
|
||||
};
|
||||
|
||||
struct tcm_qla2xxx_tpg_attrib {
|
||||
int generate_node_acls;
|
||||
int cache_dynamic_acls;
|
||||
int demo_mode_write_protect;
|
||||
int prod_mode_write_protect;
|
||||
int demo_mode_login_only;
|
||||
};
|
||||
|
||||
struct tcm_qla2xxx_tpg {
|
||||
/* FC lport target portal group tag for TCM */
|
||||
u16 lport_tpgt;
|
||||
/* Atomic bit to determine TPG active status */
|
||||
atomic_t lport_tpg_enabled;
|
||||
/* Pointer back to tcm_qla2xxx_lport */
|
||||
struct tcm_qla2xxx_lport *lport;
|
||||
/* Used by tcm_qla2xxx_tpg_attrib_cit */
|
||||
struct tcm_qla2xxx_tpg_attrib tpg_attrib;
|
||||
/* Returned by tcm_qla2xxx_make_tpg() */
|
||||
struct se_portal_group se_tpg;
|
||||
/* Items for dealing with configfs_depend_item */
|
||||
struct completion tpg_base_comp;
|
||||
struct work_struct tpg_base_work;
|
||||
};
|
||||
|
||||
struct tcm_qla2xxx_fc_loopid {
|
||||
struct se_node_acl *se_nacl;
|
||||
};
|
||||
|
||||
struct tcm_qla2xxx_lport {
|
||||
/* SCSI protocol the lport is providing */
|
||||
u8 lport_proto_id;
|
||||
/* Binary World Wide unique Port Name for FC Target Lport */
|
||||
u64 lport_wwpn;
|
||||
/* Binary World Wide unique Port Name for FC NPIV Target Lport */
|
||||
u64 lport_npiv_wwpn;
|
||||
/* Binary World Wide unique Node Name for FC NPIV Target Lport */
|
||||
u64 lport_npiv_wwnn;
|
||||
/* ASCII formatted WWPN for FC Target Lport */
|
||||
char lport_name[TCM_QLA2XXX_NAMELEN];
|
||||
/* ASCII formatted naa WWPN for VPD page 83 etc */
|
||||
char lport_naa_name[TCM_QLA2XXX_NAMELEN];
|
||||
/* map for fc_port pointers in 24-bit FC Port ID space */
|
||||
struct btree_head32 lport_fcport_map;
|
||||
/* vmalloc-ed memory for fc_port pointers for 16-bit FC loop ID */
|
||||
struct tcm_qla2xxx_fc_loopid *lport_loopid_map;
|
||||
/* Pointer to struct scsi_qla_host from qla2xxx LLD */
|
||||
struct scsi_qla_host *qla_vha;
|
||||
/* Pointer to struct qla_tgt pointer */
|
||||
struct qla_tgt lport_qla_tgt;
|
||||
/* Pointer to TPG=1 for non NPIV mode */
|
||||
struct tcm_qla2xxx_tpg *tpg_1;
|
||||
/* Returned by tcm_qla2xxx_make_lport() */
|
||||
struct se_wwn lport_wwn;
|
||||
};
|
||||
Loading…
Add table
Add a link
Reference in a new issue