Fixed MTP to work with TWRP

drivers/soc/samsung/Kconfig

@@ -0,0 +1,104 @@
+#
+# EXYNOS Soc drivers
+#
+menuconfig SOC_SAMSUNG
+	bool "SAMSUNG SOC drivers support"
+
+if SOC_SAMSUNG
+config EXYNOS_CHIPID
+	bool "Exynos Chip ID Driver Support"
+	depends on ARCH_EXYNOS
+	select SOC_BUS
+config EXYNOS_REBOOT
+	bool "Exynos Chip Reboot Driver Support"
+	depends on ARCH_EXYNOS
+
+config SAMSUNG_DMADEV
+	bool
+	select ARM_AMBA
+	select DMADEVICES
+	select PL330_DMA if (ARCH_EXYNOS7 || ARCH_EXYNOS8)
+	help
+	  Use DMA device engine for PL330 DMAC.
+
+config SAMSUNG_CORE_TEST
+	bool "Show system-control registers"
+	depends on ARCH_EXYNOS
+	help
+	  Show system-control registers.
+
+config ECT
+	bool "Enable Exynos Characteristic Table File"
+	default n
+	depends on ARCH_EXYNOS
+
+config ECT_DUMP
+	bool "Enable Exynos Characteristic Table File Dump sysfs"
+	default n
+	depends on ECT
+
+config ECT_HEADER_IN_KERNEL
+	bool "Enable Exynos Characteristic Table File by using kernel header"
+	help
+	  This is an option only for emulator
+	default n
+	depends on ECT
+
+config EXYNOS_CONTENT_PATH_PROTECTION
+	bool "Exynos Content Path Protection"
+	default y
+	help
+	  Enable content path protection of EXYNOS.
+
+config EXYNOS_SEC_LOGGER
+	bool "Exynos Secure Logger Support"
+	default y
+	help
+	  Enable logging for secure drm fw.
+
+config EXYNOS_HOTPLUG_GOVERNOR
+	bool "Enable Exynos dynamic hotplug governor"
+	depends on HOTPLUG_CPU
+
+config EXYNOS_MCINFO
+	bool "Exynos memory controller information"
+	default n
+
+config MCINFO_SYSFS
+	bool "Exynos memory controller information sysfs"
+	depends on EXYNOS_MCINFO
+	default	y if SYSFS
+
+menuconfig EXYNOS_BCM
+	bool "EXYNOS_BCM driver support"
+	default y
+	help
+	  Enable exynos_bcm driver support
+
+config USI
+	bool "Enable Universal Serial Interface"
+	default n
+
+config EXYNOS_PD
+	bool "Exynos PM Domains Driver Support"
+	depends on PM_RUNTIME
+	help
+	  Exynos specific pm domain driver.
+
+config EXYNOS_RGT
+	bool "Exynos Regulator Debug Support"
+	depends on REGULATOR
+	depends on DEBUG_FS
+	depends on OF
+	help
+	  dummy device driver for debugging samsung PMIC
+
+source "drivers/soc/samsung/acpm/Kconfig"
+
+endif #SOC_SAMSUNG
+
+config SEC_INCELL
+	bool "Incell data & function for Samsung"
+	default n
+	help
+	  say y to enable incell data & function for Samsung.

drivers/soc/samsung/Makefile

@@ -0,0 +1,39 @@
+#
+# Exynos SoC Specific drivers
+#
+
+obj-$(CONFIG_ARCH_EXYNOS)	+= exynos-pm.o
+obj-$(CONFIG_ARCH_EXYNOS)	+= exynos-pmu.o
+obj-$(CONFIG_ARCH_EXYNOS)	+= exynos-powermode.o
+obj-$(CONFIG_ARCH_EXYNOS)	+= exynos-el3_mon.o
+obj-$(CONFIG_HOTPLUG_CPU)	+= exynos-cpu_hotplug.o
+obj-$(CONFIG_EXYNOS_MCINFO)	+= exynos-mcinfo.o
+obj-$(CONFIG_EXYNOS_PD)		+= exynos-pd.o exynos-pd-dbg.o
+obj-$(CONFIG_EXYNOS_RGT)	+= exynos-rgt.o
+
+obj-$(CONFIG_ARCH_EXYNOS)	+= secmem.o
+obj-$(CONFIG_ARCH_EXYNOS)	+= exynos-smc.o
+obj-$(CONFIG_EXYNOS_SEC_LOGGER) += secprint.o
+
+# CAL
+obj-$(CONFIG_PWRCAL)            += pwrcal/
+obj-$(CONFIG_EXYNOS_CHIPID)	+= exynos-chipid.o
+obj-$(CONFIG_EXYNOS_REBOOT)	+= exynos-reboot.o
+
+# CP
+obj-$(CONFIG_SEC_SIPC_MODEM_IF)	+= pmu-cp.o
+obj-$(CONFIG_SEC_MODEM_IF)	+= pmu-cp.o
+
+obj-$(CONFIG_ECT)		+= ect_parser.o
+
+obj-$(CONFIG_EXYNOS_HOTPLUG_GOVERNOR)	+= exynos-hotplug_governor.o
+
+obj-$(CONFIG_EXYNOS_BCM)		+= exynos-bcm.o
+
+# ACPM
+obj-$(CONFIG_EXYNOS_ACPM)    	+= acpm/
+
+# USI
+obj-$(CONFIG_USI) += usi.o
+
+obj-$(CONFIG_SEC_INCELL) += sec_incell.o

drivers/soc/samsung/acpm/Kconfig

@@ -0,0 +1,26 @@
+#
+# ACPM driver configuration
+#
+
+menuconfig EXYNOS_ACPM
+	bool "ACPM driver support"
+	default n
+	help
+	  Enable ACPM support
+
+if EXYNOS_ACPM
+
+config EXYNOS7570_ACPM
+	bool "EXYNOS7570_ACPM support"
+	default y
+	depends on SOC_EXYNOS7570
+	help
+	  Enable ACPM support
+
+config EXYNOS7270_ACPM
+	bool "EXYNOS7270_ACPM support"
+	default y
+	depends on SOC_EXYNOS7270
+	help
+	  Enable ACPM support
+endif

drivers/soc/samsung/acpm/Makefile

@@ -0,0 +1,5 @@
+#
+# Makefile for ACPM.
+#
+
+obj-$(CONFIG_EXYNOS_ACPM)    += acpm.o acpm_ipc.o

drivers/soc/samsung/acpm/acpm.c

@@ -0,0 +1,553 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/firmware.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/debugfs.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/exynos-ss.h>
+#include <linux/reboot.h>
+
+#include "acpm.h"
+#include "acpm_ipc.h"
+
+static struct workqueue_struct *debug_logging_wq;
+
+static int ipc_done;
+static unsigned long long ipc_time_start;
+static unsigned long long ipc_time_end;
+
+static struct acpm_debug_info *debug;
+static struct acpm_info *exynos_acpm;
+
+static int acpm_send_data(struct device_node *node, unsigned int check_id,
+		struct ipc_config *config);
+
+static void acpm_framework_handler(unsigned int *cmd, unsigned int size)
+{
+	unsigned int id = 0;
+
+	ipc_time_end = sched_clock();
+
+	if (cmd[0] & ACPM_IPC_PROTOCOL_DP_CMD) {
+		id = cmd[0] & ACPM_IPC_PROTOCOL_IDX;
+		id = id	>> ACPM_IPC_PROTOCOL_ID;
+		ipc_done = id;
+	} else if (cmd[0] & (1 << ACPM_IPC_PROTOCOL_STOP)) {
+
+		ipc_done = ACPM_IPC_PROTOCOL_STOP;
+	} else if (cmd[0] & (1 << ACPM_IPC_PROTOCOL_TEST)) {
+		id = cmd[0] & ACPM_IPC_PROTOCOL_IDX;
+		id = id	>> ACPM_IPC_PROTOCOL_ID;
+		ipc_done = id;
+	}
+}
+
+static int plugin_fw_connet(struct device_node *node, unsigned int id,
+		const char *p_name, unsigned int attach)
+{
+	struct ipc_config config;
+	int ret = 0;
+
+	config.cmd = kzalloc(SZ_16, GFP_KERNEL);
+	if (attach)
+		config.cmd[0] = (1 << ACPM_IPC_PROTOCOL_DP_A);
+	else
+		config.cmd[0] = (1 << ACPM_IPC_PROTOCOL_DP_D);
+
+	config.cmd[0] |= id << ACPM_IPC_PROTOCOL_ID;
+
+	config.responce = true;
+
+	ret = acpm_send_data(node, id, &config);
+
+	kfree(config.cmd);
+
+	if (!ret) {
+		if (attach)
+			pr_info("[ACPM] %s plugin attach done!\n", p_name);
+		else
+			pr_info("[ACPM] %s plugin detach done!\n", p_name);
+	}
+
+	return ret;
+}
+
+static void firmware_load(void *base, const char *firmware, int size)
+{
+	memcpy(base, firmware, size);
+}
+
+static int firmware_update(struct device *dev, struct acpm_plugins *plugin)
+{
+	const struct firmware *fw_entry = NULL;
+	int err;
+
+	dev_info(dev, "Loading %s firmware ... ", plugin->fw_name);
+	err = request_firmware(&fw_entry, plugin->fw_name, dev);
+	if (err) {
+		dev_err(dev, "firmware request FAIL \n");
+		return err;
+	}
+
+	if (fw_entry) {
+		firmware_load(plugin->fw_base, fw_entry->data, fw_entry->size);
+	} else {
+		dev_err(dev, "firmware loading FAIL \n");
+		return -ENODEV;
+	}
+
+	dev_info(dev, "OK \n");
+
+	release_firmware(fw_entry);
+
+	return 0;
+}
+
+static int plugins_init(struct device_node *node, struct acpm_info *acpm)
+{
+	struct device_node *child;
+	const __be32 *prop_0, *prop_1;
+	int ret = 0;
+	unsigned int len;
+	int i = 0;
+	unsigned int attach;
+
+	acpm->plugin_num = of_get_child_count(node);
+
+	acpm->plugin = devm_kzalloc(acpm->dev,
+			sizeof(struct acpm_plugins) * acpm->plugin_num, GFP_KERNEL);
+
+	for_each_child_of_node(node, child) {
+		acpm->plugin[i].np = child;
+
+		prop_0 = of_get_property(child, "attach", &len);
+		if (prop_0)
+			attach = be32_to_cpup(prop_0);
+		else
+			attach = 1;
+
+		prop_0 = of_get_property(child, "id", &len);
+		if (prop_0)
+			acpm->plugin[i].id = be32_to_cpup(prop_0);
+		else
+			acpm->plugin[i].id = i;
+
+		if (attach == 1) {
+			if (of_property_read_string(child, "fw_name", &acpm->plugin[i].fw_name))
+				return -ENODEV;
+
+			prop_0 = of_get_property(child, "fw_base", &len);
+			prop_1 = of_get_property(child, "fw_size", &len);
+			if (prop_0 && prop_1) {
+				acpm->plugin[i].fw_base = ioremap(be32_to_cpup(prop_0),
+						be32_to_cpup(prop_1));
+			} else {
+				dev_info(acpm->dev, "fw base ioremap fail!!\n");
+			}
+
+			if (acpm->plugin[i].fw_base) {
+				firmware_update(acpm->dev, &acpm->plugin[i]);
+				iounmap(acpm->plugin[i].fw_base);
+			}
+		}
+
+		if (attach != 2) {
+			ret = plugin_fw_connet(child, acpm->plugin[i].id, child->name, attach);
+			if (ret < 0)
+				dev_err(acpm->dev, "plugin attach/detach:%u fail! plugin_name:%s, ret:%d",
+						attach, child->name, ret);
+		}
+
+		i++;
+	}
+
+	return ret;
+}
+
+static int debug_ipc_loopback_test_get(void *data, unsigned long long *val)
+{
+	struct acpm_info *acpm = data;
+	struct ipc_config config;
+	int ret = 0;
+
+	config.cmd = kzalloc(SZ_16, GFP_KERNEL);
+	config.cmd[0] = (1 << ACPM_IPC_PROTOCOL_TEST);
+	config.cmd[0] |= 0x3 << ACPM_IPC_PROTOCOL_ID;
+
+	config.responce = true;
+
+	ret = acpm_send_data(acpm->plugin[0].np, 3, &config);
+
+	if (!ret)
+		*val = ipc_time_end - ipc_time_start;
+	else
+		*val = 0;
+
+	kfree(config.cmd);
+
+	return 0;
+}
+
+static int debug_ipc_loopback_test_set(void *data, unsigned long long val)
+{
+
+	return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(debug_ipc_loopback_test_fops,
+		debug_ipc_loopback_test_get, debug_ipc_loopback_test_set, "%llu\n");
+
+static void acpm_debugfs_init(struct acpm_info *acpm)
+{
+	struct dentry *den;
+
+	den = debugfs_create_dir("acpm_framework", NULL);
+	debugfs_create_file("ipc_loopback_test", 0644, den, acpm, &debug_ipc_loopback_test_fops);
+}
+
+void *memcpy_align_4(void *dest, const void *src, unsigned int n)
+{
+	unsigned int *dp = dest;
+	const unsigned int *sp = src;
+	int i;
+
+	if ((n % 4))
+		BUG();
+
+	n = n >> 2;
+
+	for (i = 0; i < n; i++)
+		*dp++ = *sp++;
+
+	return dest;
+}
+
+void timestamp_write(void)
+{
+	unsigned int tmp_index;
+
+	if (spin_trylock(&debug->lock)) {
+		tmp_index = __raw_readl(debug->time_index);
+
+		tmp_index++;
+
+		if (tmp_index == debug->time_len)
+			tmp_index = 0;
+
+		debug->timestamps[tmp_index] = sched_clock();
+
+		__raw_writel(tmp_index, debug->time_index);
+		spin_unlock(&debug->lock);
+	}
+}
+
+void acpm_log_print(void)
+{
+	unsigned int front;
+	unsigned int rear;
+	unsigned int id;
+	unsigned int index;
+	unsigned int count;
+	unsigned char str[9] = {0,};
+	unsigned int val;
+	unsigned int log_header;
+	unsigned long long time;
+
+	/* ACPM Log data dequeue & print */
+	front = __raw_readl(debug->log_buff_front);
+	rear = __raw_readl(debug->log_buff_rear);
+
+	while (rear != front) {
+		log_header = __raw_readl(debug->log_buff_base + debug->log_buff_size * rear);
+
+		/* log header information
+		 * id: [31:29]
+		 * index: [28:23]
+		 * apm systick count: [22:0]
+		 */
+		id = (log_header & (0x7 << LOG_ID_SHIFT)) >> LOG_ID_SHIFT;
+		index = (log_header & (0x3f << LOG_TIME_INDEX)) >> LOG_TIME_INDEX;
+		count = log_header & 0x7fffff;
+
+		/* string length: log_buff_size - header(4) - integer_data(4) */
+		memcpy_align_4(str, debug->log_buff_base + (debug->log_buff_size * rear) + 4,
+				debug->log_buff_size - 8);
+
+		val = __raw_readl(debug->log_buff_base + debug->log_buff_size * rear +
+				debug->log_buff_size - 4);
+
+		time = debug->timestamps[index];
+
+		/* systick period: 1 / 26MHz */
+		time += count * APM_SYSTICK_NS_PERIOD;
+
+		exynos_ss_acpm(time, str, val);
+		if (debug->debug_logging_level == 1)
+			pr_info("[ACPM_FW][%llu] id:%u, %s, %u\n", time, id, str, val);
+		else {
+			exynos_ss_printk("[ACPM_FW][%llu] id:%u, %s, %u\n", time, id, str, val);
+			trace_printk("[ACPM_FW][%llu] id:%u, %s, %u\n", time, id, str, val);
+		}
+
+		if (debug->log_buff_len == (rear + 1))
+			rear = 0;
+		else
+			rear++;
+
+		__raw_writel(rear, debug->log_buff_rear);
+		front = __raw_readl(debug->log_buff_front);
+	}
+
+	timestamp_write();
+}
+
+static void acpm_debug_logging(struct work_struct *work)
+{
+	acpm_log_print();
+
+	queue_delayed_work(debug_logging_wq, &debug->work,
+			msecs_to_jiffies(debug->period));
+}
+
+void exynos_apm_power_down(void)
+{
+	unsigned int reg;
+
+	reg = __raw_readl(exynos_acpm->mcore_base + EXYNOS_PMU_CORTEX_APM_CONFIGURATION);
+	reg &= APM_LOCAL_PWR_CFG_RESET;
+	__raw_writel(reg, exynos_acpm->mcore_base + EXYNOS_PMU_CORTEX_APM_CONFIGURATION);
+}
+
+void acpm_enter_wfi(void)
+{
+	struct ipc_config config;
+	int ret = 0;
+
+	config.cmd = kzalloc(SZ_16, GFP_KERNEL);
+	config.responce = true;
+	config.cmd[0] = 1 << ACPM_IPC_PROTOCOL_STOP;
+
+	ret = acpm_send_data(exynos_acpm->plugin[0].np, ACPM_IPC_PROTOCOL_STOP, &config);
+
+	kfree(config.cmd);
+
+	if (ret)
+		pr_err("[ACPM] acpm enter wfi fail!!\n");
+}
+
+void acpm_ramdump(void)
+{
+#ifdef CONFIG_EXYNOS_SNAPSHOT_ACPM
+	if (debug->dump_size)
+		memcpy(debug->dump_dram_base, debug->dump_base, debug->dump_size);
+#endif
+}
+
+static int exynos_acpm_reboot_notifier_call(struct notifier_block *this,
+				   unsigned long code, void *_cmd)
+{
+	acpm_enter_wfi();
+	exynos_apm_power_down();
+	acpm_log_print();
+	acpm_ramdump();
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block exynos_acpm_reboot_notifier = {
+	.notifier_call = exynos_acpm_reboot_notifier_call,
+	.priority = (INT_MIN + 1),
+};
+
+static void log_buffer_init(struct device *dev, struct device_node *node)
+{
+	const __be32 *prop;
+	unsigned int base = 0;
+	unsigned int time_len = 0;
+	unsigned int buff_size = 0;
+	unsigned int buff_len = 0;
+	unsigned int len = 0;
+	unsigned int dump_base = 0;
+	unsigned int dump_size = 0;
+
+	prop = of_get_property(node, "log_base", &len);
+	if (prop)
+		base = be32_to_cpup(prop);
+
+	prop = of_get_property(node, "time_len", &len);
+	if (prop)
+		time_len = be32_to_cpup(prop);
+
+	prop = of_get_property(node, "log_buff_size", &len);
+	if (prop)
+		buff_size = be32_to_cpup(prop);
+
+	prop = of_get_property(node, "log_buff_len", &len);
+	if (prop)
+		buff_len = be32_to_cpup(prop);
+
+	if (base && time_len && buff_size && buff_len) {
+		debug = devm_kzalloc(dev, sizeof(struct acpm_debug_info), GFP_KERNEL);
+
+		debug->time_index = ioremap(base,
+				(buff_len * buff_size) + SZ_16);
+		debug->time_len = time_len;
+		debug->timestamps = devm_kzalloc(dev,
+				sizeof(unsigned long long) * time_len, GFP_KERNEL);
+
+		debug->log_buff_rear = debug->time_index + SZ_8;
+		debug->log_buff_front = debug->log_buff_rear + SZ_4;
+		debug->log_buff_base = debug->log_buff_front + SZ_4;
+		debug->log_buff_len = buff_len;
+		debug->log_buff_size = buff_size;
+
+		prop = of_get_property(node, "debug_logging_level", &len);
+		if (prop)
+			debug->debug_logging_level = be32_to_cpup(prop);
+	}
+
+	prop = of_get_property(node, "dump_base", &len);
+	if (prop)
+		dump_base = be32_to_cpup(prop);
+
+	prop = of_get_property(node, "dump_size", &len);
+	if (prop)
+		dump_size = be32_to_cpup(prop);
+
+	if (debug && base && buff_size) {
+		debug->dump_base = ioremap(dump_base, dump_size);
+		debug->dump_size = dump_size;
+	}
+
+	prop = of_get_property(node, "logging_period", &len);
+	if (prop)
+		debug->period = be32_to_cpup(prop);
+
+#ifdef CONFIG_EXYNOS_SNAPSHOT_ACPM
+	debug->dump_dram_base = kzalloc(debug->dump_size, GFP_KERNEL);
+	exynos_ss_printk("[ACPM] acpm framework SRAM dump to dram base: 0x%x\n",
+			virt_to_phys(debug->dump_dram_base));
+#endif
+
+	spin_lock_init(&debug->lock);
+}
+
+static int acpm_send_data(struct device_node *node, unsigned int check_id,
+		struct ipc_config *config)
+{
+	unsigned int channel_num, size;
+	int ret = 0;
+	int timeout_flag;
+
+	if (!acpm_ipc_request_channel(node, acpm_framework_handler,
+				&channel_num, &size)) {
+		ipc_done = -1;
+
+		ipc_time_start = sched_clock();
+		ret = acpm_ipc_send_data(channel_num, config);
+
+		/* Responce interrupt waitting */
+		UNTIL_EQUAL(ipc_done, check_id, timeout_flag);
+
+		if (timeout_flag)
+			ret = -ETIMEDOUT;
+
+		acpm_ipc_release_channel(channel_num);
+	} else {
+		pr_err("%s ipc request_channel fail, id:%u, size:%u\n",
+				__func__, channel_num, size);
+		ret = -EBUSY;
+	}
+
+	return ret;
+}
+
+static int acpm_probe(struct platform_device *pdev)
+{
+	struct acpm_info *acpm;
+	struct device_node *node = pdev->dev.of_node;
+	struct resource *res;
+	int ret = 0;
+
+	dev_info(&pdev->dev, "acpm probe\n");
+
+	if (!node) {
+		dev_err(&pdev->dev, "driver doesnt support"
+				"non-dt devices\n");
+		return -ENODEV;
+	}
+
+	acpm = devm_kzalloc(&pdev->dev,
+			sizeof(struct acpm_info), GFP_KERNEL);
+	if (IS_ERR(acpm))
+		return PTR_ERR(acpm);
+
+	acpm->dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	acpm->mcore_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(acpm->mcore_base))
+		return PTR_ERR(acpm->mcore_base);
+
+	log_buffer_init(&pdev->dev, node);
+
+	node = of_get_child_by_name(node, "plugins");
+
+	if (node) {
+		ret = plugins_init(node, acpm);
+		acpm_debugfs_init(acpm);
+	};
+
+	if (debug->period) {
+		debug_logging_wq = create_freezable_workqueue("acpm_debug_logging");
+		INIT_DELAYED_WORK(&debug->work, acpm_debug_logging);
+
+		queue_delayed_work(debug_logging_wq, &debug->work,
+				msecs_to_jiffies(10000));
+	}
+
+	exynos_acpm = acpm;
+
+	register_reboot_notifier(&exynos_acpm_reboot_notifier);
+
+	return ret;
+}
+
+static int acpm_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static const struct of_device_id acpm_match[] = {
+	{ .compatible = "samsung,exynos-acpm" },
+	{},
+};
+
+static struct platform_driver samsung_acpm_driver = {
+	.probe	= acpm_probe,
+	.remove	= acpm_remove,
+	.driver	= {
+		.name = "exynos-acpm",
+		.owner	= THIS_MODULE,
+		.of_match_table	= acpm_match,
+	},
+};
+
+static int __init exynos_acpm_init(void)
+{
+	return platform_driver_register(&samsung_acpm_driver);
+}
+fs_initcall_sync(exynos_acpm_init);

drivers/soc/samsung/acpm/acpm.h

@@ -0,0 +1,52 @@
+#ifndef __ACPM_H__
+#define __ACPM_H__
+
+struct acpm_plugins {
+	unsigned int id;
+	const char *fw_name;
+	void __iomem *fw_base;
+	struct device_node *np;
+};
+
+struct acpm_info {
+	unsigned int plugin_num;
+	struct device *dev;
+	void __iomem *mcore_base;
+	struct acpm_plugins *plugin;
+};
+
+struct acpm_debug_info {
+	unsigned int period;
+	void __iomem *time_index;
+	unsigned int time_len;
+	unsigned long long *timestamps;
+
+	void __iomem *log_buff_rear;
+	void __iomem *log_buff_front;
+	void __iomem *log_buff_base;
+	unsigned int log_buff_len;
+	unsigned int log_buff_size;
+	void __iomem *dump_base;
+	unsigned int dump_size;
+	void __iomem *dump_dram_base;
+	unsigned int debug_logging_level;
+	struct delayed_work work;
+
+	spinlock_t lock;
+};
+
+extern void acpm_log_print(void);
+extern void timestamp_write(void);
+extern void *memcpy_align_4(void *dest, const void *src, unsigned int n);
+
+#define EXYNOS_PMU_CORTEX_APM_CONFIGURATION                           (0x0100)
+#define EXYNOS_PMU_CORTEX_APM_STATUS                                  (0x0104)
+#define EXYNOS_PMU_CORTEX_APM_OPTION                                  (0x0108)
+#define EXYNOS_PMU_CORTEX_APM_DURATION0                               (0x0110)
+#define EXYNOS_PMU_CORTEX_APM_DURATION1                               (0x0114)
+#define EXYNOS_PMU_CORTEX_APM_DURATION2                               (0x0118)
+#define EXYNOS_PMU_CORTEX_APM_DURATION3                               (0x011C)
+
+#define APM_LOCAL_PWR_CFG_RESET         (~(0x1 << 0))
+
+#endif

drivers/soc/samsung/acpm/acpm_ipc.c

@@ -0,0 +1,462 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/debugfs.h>
+#include <linux/interrupt.h>
+#include <linux/of_irq.h>
+#include <linux/workqueue.h>
+
+#include "acpm.h"
+#include "acpm_ipc.h"
+
+static struct acpm_ipc_info *acpm_ipc;
+
+unsigned int acpm_ipc_request_channel(struct device_node *np, ipc_callback handler,
+		unsigned int *id, unsigned int *size)
+{
+	struct device_node *node;
+	int i;
+
+	if (!np)
+		return -ENODEV;
+
+	node = of_parse_phandle(np, "acpm-ipc-channel", 0);
+
+	if (!node)
+		return -ENOENT;
+
+	for(i = 0; i < acpm_ipc->channel_num; i++) {
+		if (acpm_ipc->channel[i].ch_node == node) {
+			*id = acpm_ipc->channel[i].id;
+			*size = acpm_ipc->channel[i].buff_size;
+
+			if (handler)
+				acpm_ipc->channel[i].ipc_callback = handler;
+
+			return 0;
+		}
+	}
+
+	return -ENODEV;
+}
+
+unsigned int acpm_ipc_release_channel(unsigned int channel_id)
+{
+	struct acpm_ipc_ch *channel = &acpm_ipc->channel[channel_id];
+
+	channel->ipc_callback = NULL;
+
+	return 0;
+}
+
+static irqreturn_t acpm_ipc_handler(int irq, void *p)
+{
+	struct acpm_ipc_info *ipc = p;
+	unsigned int status;
+	unsigned int int_check = 0;
+	int i;
+
+	/* ACPM IPC INTERRUPT STATUS REGISTER */
+	status = __raw_readl(acpm_ipc->intr + INTSR1);
+
+	for (i = 0; i < acpm_ipc->channel_num; i++) {
+		if (status & (0x1 << ipc->channel[i].id)) {
+			tasklet_schedule(&ipc->channel[i].dequeue_task);
+			/* ACPM IPC INTERRUPT PENDING CLEAR */
+			__raw_writel(1 << ipc->channel[i].id, ipc->intr + INTCR1);
+		}
+		int_check |= 0x1 << ipc->channel[i].id;
+	}
+
+	if (status & ~int_check) {
+		pr_err("[ACPM] unknown interrupt, status:0x%x\n", status);
+		return IRQ_NONE;
+	}
+
+	return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_ACPM_IPC_PROFILE
+
+#define ACPM_IPC_ITERATION		(1000)
+#define ACPM_IPC_CH_NUM			(4)
+struct time_data {
+	unsigned long min;
+	unsigned long max;
+	unsigned int cnt;
+};
+
+struct time_data time_d[ACPM_IPC_CH_NUM];
+struct time_data en_time_d[ACPM_IPC_CH_NUM];
+#endif
+
+static void dequeue_policy(struct acpm_ipc_ch *channel)
+{
+	unsigned int front;
+	unsigned int rear;
+#ifdef CONFIG_ACPM_IPC_PROFILE
+	unsigned long after, before;
+
+	before = sched_clock();
+#endif
+	spin_lock_bh(&channel->rx_lock);
+
+	/* IPC command dequeue */
+	front = __raw_readl(channel->rx_front);
+	rear = __raw_readl(channel->rx_rear);
+
+	while (rear != front) {
+		memcpy_align_4(channel->cmd, channel->rx_base + channel->buff_size * rear,
+				channel->buff_size);
+
+		if (channel->ipc_callback)
+			channel->ipc_callback(channel->cmd, channel->buff_size);
+
+		if (channel->buff_len == (rear + 1))
+			rear = 0;
+		else
+			rear++;
+
+		__raw_writel(rear, channel->rx_rear);
+		front = __raw_readl(channel->rx_front);
+	}
+
+	acpm_log_print();
+	spin_unlock_bh(&channel->rx_lock);
+
+#ifdef CONFIG_ACPM_IPC_PROFILE
+	after = sched_clock();
+
+	if (time_d[channel->id].max < (after - before))
+		time_d[channel->id].max = after - before;
+	if (time_d[channel->id].min > (after - before))
+		time_d[channel->id].min = after - before;
+	time_d[channel->id].cnt += 1;
+	if (time_d[channel->id].cnt == ACPM_IPC_ITERATION) {
+		pr_err("[dequeue_ACPM][%u] chnnale:%u, min:%lu, max:%lu\n",
+				time_d[channel->id].cnt,
+				channel->id, time_d[channel->id].min,
+				time_d[channel->id].max);
+		time_d[channel->id].cnt = 0;
+		time_d[channel->id].min = ~0;
+		time_d[channel->id].max = 0;
+	}
+#endif
+}
+
+static void dequeue_tasklet(unsigned long data)
+{
+	struct acpm_ipc_ch *channel = (struct acpm_ipc_ch *)data;
+
+	dequeue_policy(channel);
+}
+
+static void apm_interrupt_gen(unsigned int id)
+{
+	/* APM NVIC INTERRUPT GENERATE */
+	__raw_writel((1 << id) << 16, acpm_ipc->intr + INTGR0);
+}
+
+int acpm_ipc_send_data(unsigned int channel_id, struct ipc_config *cfg)
+{
+	unsigned int front;
+	unsigned int rear;
+	unsigned int tmp_index;
+	struct acpm_ipc_ch *channel;
+	unsigned int buf;
+	bool timeout_flag = 0;
+#ifdef CONFIG_ACPM_IPC_PROFILE
+	unsigned long after, before;
+
+	before = sched_clock();
+#endif
+	if (channel_id >= acpm_ipc->channel_num)
+		return -EIO;
+
+	channel = &acpm_ipc->channel[channel_id];
+
+	spin_lock(&channel->tx_lock);
+
+	front = __raw_readl(channel->tx_front);
+	rear = __raw_readl(channel->tx_rear);
+
+	tmp_index = front + 1;
+
+	if (tmp_index >= channel->buff_len)
+		tmp_index = 0;
+
+	/* buffer full check */
+	UNTIL_EQUAL(true, tmp_index != __raw_readl(channel->tx_rear), timeout_flag);
+	if (timeout_flag) {
+		acpm_log_print();
+		spin_unlock(&channel->tx_lock);
+		return -ETIMEDOUT;
+	}
+
+	memcpy_align_4(channel->tx_base + channel->buff_size * front, cfg->cmd,
+			channel->buff_size);
+
+	if (cfg->cmd[0] & (1 << ACPM_IPC_PROTOCOL_INDIRECTION)) {
+		/* another indirection command check */
+		while (rear != front) {
+			buf = __raw_readl(channel->tx_base + channel->buff_size * rear);
+
+			if (buf & (1 << ACPM_IPC_PROTOCOL_INDIRECTION)) {
+
+				UNTIL_EQUAL(true, rear != __raw_readl(channel->tx_rear),
+						timeout_flag);
+
+				if (timeout_flag) {
+					acpm_log_print();
+					spin_unlock(&channel->tx_lock);
+					return -ETIMEDOUT;
+				} else {
+					rear = __raw_readl(channel->tx_rear);
+				}
+
+			} else {
+				if (channel->buff_len == (rear + 1))
+					rear = 0;
+				else
+					rear++;
+			}
+		}
+
+		if (cfg->indirection)
+			memcpy_align_4(channel->tx_direction, cfg->indirection,
+					cfg->indirection_size);
+		else
+			return -EINVAL;
+	}
+
+	__raw_writel(tmp_index, channel->tx_front);
+
+	timestamp_write();
+	apm_interrupt_gen(channel->id);
+
+	spin_unlock(&channel->tx_lock);
+
+#ifdef CONFIG_ACPM_IPC_PROFILE
+	after = sched_clock();
+	if (en_time_d[channel->id].max < (after - before))
+		en_time_d[channel->id].max = after - before;
+	if (en_time_d[channel->id].min > (after - before))
+		en_time_d[channel->id].min = after - before;
+	en_time_d[channel->id].cnt += 1;
+	if (en_time_d[channel->id].cnt == ACPM_IPC_ITERATION) {
+		pr_err("[enqueue_ACPM][%u] chnnale:%u, min:%lu, max:%lu\n",
+				en_time_d[channel->id].cnt,
+				channel->id, en_time_d[channel->id].min,
+				en_time_d[channel->id].max);
+		en_time_d[channel->id].cnt = 0;
+		en_time_d[channel->id].min = ~0;
+		en_time_d[channel->id].max = 0;
+	}
+#endif
+	if (channel->polling && cfg->responce) {
+		UNTIL_EQUAL(true, !!(__raw_readl(acpm_ipc->intr + INTSR1) & (1 << channel->id)),
+				timeout_flag);
+		if (timeout_flag) {
+			acpm_log_print();
+			return -ETIMEDOUT;
+		}
+
+		dequeue_policy(channel);
+
+		__raw_writel((1 << channel->id), acpm_ipc->intr + INTCR1);
+	}
+
+	return 0;
+}
+
+static int channel_init(struct device_node *node, struct acpm_ipc_info *acpm_ipc)
+{
+	struct device_node *child;
+	const __be32 *prop;
+	unsigned int len;
+	unsigned int max_buff_size;
+	int i = 0;
+	void __iomem *addr;
+	int polling = 0;
+
+	acpm_ipc->channel_num = of_get_child_count(node);
+
+	prop = of_get_property(node, "polling", &len);
+	if (prop)
+		polling = be32_to_cpup(prop);
+
+	if (polling)
+		disable_irq(acpm_ipc->irq);
+
+	acpm_ipc->channel = devm_kzalloc(acpm_ipc->dev,
+			sizeof(struct acpm_ipc_ch) * acpm_ipc->channel_num, GFP_KERNEL);
+
+	prop = of_get_property(node, "max_buff_size", &len);
+	if (prop)
+		max_buff_size = be32_to_cpup(prop);
+	else
+		max_buff_size = 0x300 * acpm_ipc->channel_num;
+
+	for_each_child_of_node(node, child) {
+		acpm_ipc->channel[i].ch_node = child;
+		acpm_ipc->channel[i].polling = polling;
+
+		prop = of_get_property(child, "channel_id", &len);
+		if (prop)
+			acpm_ipc->channel[i].id = be32_to_cpup(prop);
+		else
+			acpm_ipc->channel[i].id = i;
+
+		prop = of_get_property(child, "buff_size", &len);
+		if (prop)
+			acpm_ipc->channel[i].buff_size = be32_to_cpup(prop);
+		else
+			acpm_ipc->channel[i].buff_size = 12;
+
+		prop = of_get_property(child, "buff_len", &len);
+		if (prop)
+			acpm_ipc->channel[i].buff_len = be32_to_cpup(prop);
+		else
+			acpm_ipc->channel[i].buff_len = 8;
+
+		prop = of_get_property(child, "direction_buff", &len);
+		if (prop)
+			acpm_ipc->channel[i].d_buff_size = be32_to_cpup(prop);
+		else
+			acpm_ipc->channel[i].d_buff_size = 0;
+
+		if (max_buff_size < (acpm_ipc->channel[i].buff_size *
+					acpm_ipc->channel[i].buff_len * 2 +
+					acpm_ipc->channel[i].d_buff_size + 8)) {
+			dev_err(acpm_ipc->dev, "exceed the buff size-"
+					"max:%u, size:%u, len:%u, direction:%u\n",
+					max_buff_size,
+					acpm_ipc->channel[i].buff_size,
+					acpm_ipc->channel[i].buff_len,
+					acpm_ipc->channel[i].d_buff_size);
+			return -ENOMEM;
+		}
+
+		prop = of_get_property(child, "rx_buff", &len);
+		if (prop)
+			addr = ioremap(be32_to_cpup(prop), acpm_ipc->channel[i].buff_size *
+					acpm_ipc->channel[i].buff_len + 8);
+
+		acpm_ipc->channel[i].rx_rear = addr;
+		acpm_ipc->channel[i].rx_front = addr + 4;
+		acpm_ipc->channel[i].rx_base = addr + 8;
+
+		acpm_ipc->channel[i].cmd = devm_kzalloc(acpm_ipc->dev,
+				acpm_ipc->channel[i].buff_size, GFP_KERNEL);
+
+		prop = of_get_property(child, "tx_buff", &len);
+		if (prop)
+			addr = ioremap(be32_to_cpup(prop), acpm_ipc->channel[i].buff_size *
+					acpm_ipc->channel[i].buff_len +
+					acpm_ipc->channel[i].d_buff_size + 8);
+
+		/* acpm_ipc queue base address init */
+		acpm_ipc->channel[i].tx_rear = addr;
+		acpm_ipc->channel[i].tx_front = addr + 4;
+		acpm_ipc->channel[i].tx_base = addr + 8;
+		if (acpm_ipc->channel[i].d_buff_size)
+			acpm_ipc->channel[i].tx_direction = addr + 8 +
+				acpm_ipc->channel[i].buff_size *
+				acpm_ipc->channel[i].buff_len;
+
+		tasklet_init(&acpm_ipc->channel[i].dequeue_task, dequeue_tasklet,
+				(unsigned long)&acpm_ipc->channel[i]);
+
+		spin_lock_init(&acpm_ipc->channel[i].rx_lock);
+		spin_lock_init(&acpm_ipc->channel[i].tx_lock);
+		i++;
+	}
+
+	return 0;
+}
+
+static int acpm_ipc_probe(struct platform_device *pdev)
+{
+	struct device_node *node = pdev->dev.of_node;
+	struct resource *res;
+	int ret = 0;
+
+	if (!node) {
+		dev_err(&pdev->dev, "driver doesnt support"
+				"non-dt devices\n");
+		return -ENODEV;
+	}
+
+	dev_info(&pdev->dev, "acpm_ipc probe\n");
+
+	acpm_ipc = devm_kzalloc(&pdev->dev,
+			sizeof(struct acpm_ipc_info), GFP_KERNEL);
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	acpm_ipc->irq = res->start;
+	ret = devm_request_irq(&pdev->dev, acpm_ipc->irq,
+			acpm_ipc_handler, IRQF_SHARED,
+			dev_name(&pdev->dev), acpm_ipc);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register acpm_ipc interrupt:%d\n", ret);
+		return ret;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	acpm_ipc->intr = devm_ioremap_resource(&pdev->dev, res);
+
+	acpm_ipc->channel = devm_kzalloc(&pdev->dev,
+			sizeof(struct acpm_ipc_info), GFP_KERNEL);
+
+	if (IS_ERR(acpm_ipc))
+		return PTR_ERR(acpm_ipc);
+
+	acpm_ipc->dev = &pdev->dev;
+
+	node = of_get_child_by_name(node, "channels");
+
+	if (node) {
+		ret = channel_init(node, acpm_ipc);
+	}
+
+	return ret;
+}
+
+static int acpm_ipc_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static const struct of_device_id acpm_ipc_match[] = {
+	{ .compatible = "samsung,exynos-acpm-ipc" },
+	{},
+};
+
+static struct platform_driver samsung_acpm_ipc_driver = {
+	.probe	= acpm_ipc_probe,
+	.remove	= acpm_ipc_remove,
+	.driver	= {
+		.name = "exynos-acpm-ipc",
+		.owner	= THIS_MODULE,
+		.of_match_table	= acpm_ipc_match,
+	},
+};
+
+static int __init exynos_acpm_ipc_init(void)
+{
+
+	return platform_driver_register(&samsung_acpm_ipc_driver);
+}
+arch_initcall(exynos_acpm_ipc_init);

drivers/soc/samsung/acpm/acpm_ipc.h

@@ -0,0 +1,76 @@
+#ifndef __ACPM_IPC_H_
+#define __ACPM_IPC_H_
+
+#include <soc/samsung/acpm_ipc_ctrl.h>
+
+struct acpm_ipc_ch {
+	struct device_node *ch_node;
+	unsigned int id;
+	void __iomem *rx_rear;
+	void __iomem *rx_front;
+	void __iomem *rx_base;
+
+	void __iomem *tx_rear;
+	void __iomem *tx_front;
+	void __iomem *tx_base;
+	void __iomem *tx_direction;
+
+	unsigned int buff_size;
+	unsigned int buff_len;
+	unsigned int d_buff_size;
+	unsigned int *cmd;
+	struct tasklet_struct dequeue_task;
+	spinlock_t rx_lock;
+	spinlock_t tx_lock;
+	bool polling;
+
+	void (*ipc_callback) (unsigned int *cmd, unsigned int size);
+};
+
+struct acpm_ipc_info {
+	unsigned int channel_num;
+	struct device *dev;
+	struct acpm_ipc_ch *channel;
+	unsigned int irq;
+	void __iomem *intr;
+};
+
+#define LOG_ID_SHIFT				(29)
+#define LOG_TIME_INDEX				(23)
+
+#define INTGR0					0x0008
+#define INTCR0					0x000C
+#define INTMR0					0x0010
+#define INTSR0					0x0014
+#define INTMSR0					0x0018
+#define INTGR1					0x001C
+#define INTCR1					0x0020
+#define INTMR1					0x0024
+#define INTSR1					0x0028
+#define INTMSR1					0x002C
+#define SR0					0x0080
+#define SR1					0x0084
+#define SR2					0x0088
+#define SR3					0x008C
+
+#define IPC_TIMEOUT				(10000000)
+#define APM_SYSTICK_NS_PERIOD			(1000 / 26)
+
+#define UNTIL_EQUAL(arg0, arg1, flag)			\
+do {							\
+	u64 timeout = sched_clock() + IPC_TIMEOUT;	\
+	bool t_flag = true;				\
+	do {						\
+		if ((arg0) == (arg1)) {			\
+			t_flag = false;			\
+			break;				\
+		}					\
+	} while (timeout >= sched_clock());		\
+	if (t_flag) {					\
+		pr_err("%s %d Timeout error!\n",	\
+				__func__, __LINE__);	\
+	}						\
+	(flag) = t_flag;				\
+} while(0)
+
+#endif

drivers/soc/samsung/exynos-bcm.c

@@ -0,0 +1,672 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+#include <linux/syscalls.h>
+#include <linux/fcntl.h>
+#include <linux/file.h>
+#include <linux/exynos_ion.h>
+#include <linux/workqueue.h>
+#include <linux/clk.h>
+#include <asm/cacheflush.h>
+#include <soc/samsung/exynos-pd.h>
+#include "../../../drivers/soc/samsung/pwrcal/pwrcal.h"
+#include <linux/suspend.h>
+
+#include <soc/samsung/bcm.h>
+#include <linux/memblock.h>
+#include <asm/map.h>
+
+#define BCM_BDGGEN
+#ifdef BCM_BDGGEN
+#define BCM_BDG(x...) pr_info("bcm: " x)
+#else
+#define BCM_BDG(x...) do {} while (0)
+#endif
+
+#define BCM_MAX_DATA		4 * 1024 * 1024 / 32
+#define MAX_STR			4 * 1024
+
+enum outform {
+	OUT_FILE = 1,
+	OUT_LOG,
+};
+
+static size_t fd_virt_addr;
+struct bcm_info {
+	struct clk *clk;
+	char *clk_name;
+	char *pd_name;
+	int on;
+};
+
+struct fw_system_func {
+	int (*fw_show)(char *);
+	char * (*fw_cmd)(const char *);
+	struct output_data *(*fw_init)(const int *);
+	struct output_data *(*fw_stop)(u64, unsigned long (*func)(unsigned int),const int *);
+	int (*fw_periodic)(u64, unsigned long (*func)(unsigned int), const int *);
+	char *(*fw_getresult)(char *str);
+	int (*fw_exit)(void);
+	int (*pd_sync)(struct bcm_info *, int, u64);
+	struct bcm_info *(*get_pd)(void);
+	int (*get_outform)(void);
+} *fw_func;
+
+struct os_system_func {
+	struct output_data *fdata;
+	struct output_data *ldata;
+	void __iomem *(*remap)(phys_addr_t phys_addr, size_t size);
+	void (*unmap)(volatile void __iomem *addr);
+	int (*sprint)(char *buf, const char *fmt, ...);
+	int (*print)(const char *, ...);
+} os_func;
+
+struct bcm_monitor_data {
+	spinlock_t lock;
+	struct platform_device *pdev;
+	void __iomem *bin_base;
+	unsigned long bin_size;
+} *g_data;
+
+static struct hrtimer bcm_hrtimer;
+static struct workqueue_struct *bcm_wq;
+static struct bcm_work_struct {
+       struct work_struct work;
+	char *data;
+} *work_file_out;
+
+static void write_file(struct work_struct *work)
+{
+	char *result = kzalloc(sizeof(char) * MAX_STR, GFP_KERNEL);
+	char *filename;
+	unsigned long flags;
+	struct file *fp = NULL;
+	mm_segment_t old_fs = get_fs();
+
+	spin_lock_irqsave(&g_data->lock, flags);
+	if (fw_func)
+		filename = fw_func->fw_getresult(result);
+	spin_unlock_irqrestore(&g_data->lock, flags);
+	if (!fw_func || !filename) {
+		goto exit;
+	}
+
+	set_fs(KERNEL_DS);
+
+	fp = filp_open(filename, O_WRONLY|O_CREAT|O_APPEND, 0);
+	if (IS_ERR(fp)) {
+		BCM_BDG("filp_open fail!!");
+		goto exit;
+
+	}
+	do {
+		if (result)
+			vfs_write(fp, result, strlen(result), &fp->f_pos);
+		spin_lock_irqsave(&g_data->lock, flags);
+		filename = fw_func->fw_getresult(result);
+		spin_unlock_irqrestore(&g_data->lock, flags);
+	} while(filename);
+
+	filp_close(fp, NULL);
+exit:
+	set_fs(old_fs);
+	kfree(result);
+
+}
+
+static void bcm_file_out (char *data)
+{
+	work_file_out->data = data;
+
+	queue_work(bcm_wq, (struct work_struct *)work_file_out);
+}
+
+static u64 get_time(void)
+{
+	return sched_clock();
+}
+
+int bcm_pd_sync(struct bcm_info *bcm, bool on)
+{
+	int ret = -1;
+	unsigned long flags;
+	struct clk *clk = bcm->clk;
+
+	if (on ^ bcm->on) {
+		if (on && clk)
+			clk_enable(clk);
+		spin_lock_irqsave(&g_data->lock, flags);
+		ret = fw_func->pd_sync(bcm, on, get_time());
+		spin_unlock_irqrestore(&g_data->lock, flags);
+
+		if (!on && clk)
+			clk_disable(clk);
+	}
+	return ret;
+}
+EXPORT_SYMBOL(bcm_pd_sync);
+
+static enum hrtimer_restart monitor_fn(struct hrtimer *hrtimer)
+{
+	unsigned long flags;
+	int duration;
+	enum hrtimer_restart ret = HRTIMER_NORESTART;
+
+	spin_lock_irqsave(&g_data->lock, flags);
+	duration = fw_func->fw_periodic(get_time(),
+			cal_dfs_cached_get_rate, NULL);
+	spin_unlock_irqrestore(&g_data->lock, flags);
+
+	if (duration > 0) {
+		hrtimer_forward_now(hrtimer, ns_to_ktime(duration * 1000));
+		ret = HRTIMER_RESTART;
+	}
+	return ret;
+}
+
+struct output_data *bcm_start(const int *usr)
+{
+	unsigned long flags;
+	struct output_data *data = NULL;
+	int duration = 0;
+	if (fw_func) {
+		spin_lock_irqsave(&g_data->lock, flags);
+		data = fw_func->fw_init(usr);
+		if (data) {
+			duration = fw_func->fw_periodic(get_time(),
+					cal_dfs_cached_get_rate, usr);
+		}
+		spin_unlock_irqrestore(&g_data->lock, flags);
+		if (duration > 0) {
+			if (bcm_hrtimer.state)
+				hrtimer_try_to_cancel(&bcm_hrtimer);
+			if (!bcm_hrtimer.state)
+				hrtimer_start(&bcm_hrtimer,
+						ns_to_ktime(duration * 1000),
+						HRTIMER_MODE_REL);
+		}
+	}
+	return data;
+}
+EXPORT_SYMBOL(bcm_start);
+
+static void bcm_log(void)
+{
+	unsigned long flags;
+	char *str = kzalloc(sizeof(char) * MAX_STR, GFP_KERNEL);
+	spin_lock_irqsave(&g_data->lock, flags);
+	while (fw_func->fw_getresult(str)) {
+		spin_unlock_irqrestore(&g_data->lock, flags);
+		pr_info("%s", str);
+		spin_lock_irqsave(&g_data->lock, flags);
+	}
+	spin_unlock_irqrestore(&g_data->lock, flags);
+	kfree(str);
+}
+
+struct output_data *bcm_stop(const int *usr)
+{
+	unsigned long flags;
+	struct output_data *data = NULL;
+	if (fw_func) {
+		spin_lock_irqsave(&g_data->lock, flags);
+		data = fw_func->fw_stop(get_time(),
+				cal_dfs_cached_get_rate, usr);
+		spin_unlock_irqrestore(&g_data->lock, flags);
+		if (data) {
+			hrtimer_try_to_cancel(&bcm_hrtimer);
+			switch (fw_func->get_outform()) {
+			case OUT_FILE:
+				bcm_file_out(NULL);
+				break;
+			case OUT_LOG:
+				bcm_log();
+				break;
+			}
+		}
+	}
+	return data;
+}
+EXPORT_SYMBOL(bcm_stop);
+
+static void __iomem * bcm_ioremap(phys_addr_t phys_addr, size_t size)
+{
+	return ioremap(phys_addr, size);
+}
+
+typedef struct fw_system_func*(*start_up_func_t)(void **func);
+
+static void pd_init(void)
+{
+	struct exynos_pm_domain *exypd;
+	struct bcm_info *bcm;
+	while (bcm = fw_func->get_pd(), bcm) {
+		if (bcm->clk_name) {
+			bcm->clk = clk_get(NULL, bcm->clk_name);
+			if (IS_ERR(bcm->clk))
+				BCM_BDG("failed to get clk %s\n",
+						bcm->clk_name);
+			else
+				clk_prepare(bcm->clk);
+		}
+		bcm->on = false;
+		exypd = exynos_pd_lookup_name(bcm->pd_name);
+		if (exypd) {
+			mutex_lock(&exypd->access_lock);
+			exypd->bcm = bcm;
+			if (cal_pd_status(exypd->cal_pdid)) {
+				bcm_pd_sync(bcm, true);
+			}
+			mutex_unlock(&exypd->access_lock);
+		} else {
+			bcm_pd_sync(bcm, true);
+		}
+	}
+}
+
+static void load_bcm_bin(struct work_struct *work)
+{
+	int ret = 0;
+	struct file *fp = NULL;
+	long fsize, nread;
+	unsigned long flags;
+	u8 *buf = NULL;
+	char *lib_isp = NULL;
+	mm_segment_t old_fs;
+
+	os_func.print = printk;
+	os_func.sprint = sprintf;
+	os_func.remap = bcm_ioremap;
+	os_func.unmap = iounmap;
+
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+	fp = filp_open("/data/bcm.bin", O_RDONLY, 0);
+	if (IS_ERR(fp)) {
+		BCM_BDG("filp_open fail!!");
+		ret = -EIO;
+		goto exit1;
+	}
+
+	fsize = fp->f_path.dentry->d_inode->i_size;
+	BCM_BDG("start, file path %s, size %ld Bytes\n",
+		"/data/bcm.bin", fsize);
+	buf = vmalloc(fsize);
+	if (!buf) {
+		BCM_BDG("failed to allocate memory");
+		ret = -ENOMEM;
+		goto exit2;
+	}
+
+	nread = vfs_read(fp, (char __user *)buf, fsize, &fp->f_pos);
+	if (nread != fsize) {
+		BCM_BDG("failed to read firmware file, %ld Bytes", nread);
+		ret = -EIO;
+		goto exit3;
+	}
+
+	lib_isp = (char *)fd_virt_addr;
+	/* TODO: Must change below size of reserved memory */
+	memset((char *)fd_virt_addr, 0x0, SZ_64K);
+
+	spin_lock_irqsave(&g_data->lock, flags);
+	flush_icache_range((unsigned long)lib_isp,
+			   (unsigned long)lib_isp + SZ_64K);
+	memcpy((void *)lib_isp, (void *)buf, fsize);
+	flush_cache_all();
+
+	spin_unlock_irqrestore(&g_data->lock, flags);
+	fw_func = ((start_up_func_t)lib_isp)((void **)&os_func);
+	pd_init();
+
+exit3:
+	vfree((void *)buf);
+exit2:
+	filp_close(fp, NULL);
+exit1:
+	set_fs(old_fs);
+	return;
+}
+
+static void pd_exit(void)
+{
+	struct bcm_info *bcm;
+	struct exynos_pm_domain *exypd;
+	while (bcm = fw_func->get_pd(), bcm) {
+		exypd = exynos_pd_lookup_name(bcm->pd_name);
+		if (exypd) {
+			mutex_lock(&exypd->access_lock);
+			exypd->bcm = NULL;
+			bcm_pd_sync(bcm, false);
+			mutex_unlock(&exypd->access_lock);
+		} else {
+			bcm_pd_sync(bcm, false);
+		}
+		if (bcm->on)
+			clk_disable_unprepare(bcm->clk);
+		else
+			clk_unprepare(bcm->clk);
+	}
+}
+
+static ssize_t store_load_bcm_fw(struct device *dev,
+					struct device_attribute *attr,
+					const char *buf, size_t count)
+{
+	struct platform_device *pdev = container_of(dev,
+						    struct platform_device, dev);
+	struct bcm_monitor_data *data = platform_get_drvdata(pdev);
+	unsigned long flags;
+	int ret;
+	int value;
+
+	ret = sscanf(buf, "%d\n", &value);
+	if (ret != 1) {
+		dev_err(dev, "failed sscanf %d\n", ret);
+		return -EINVAL;
+	}
+
+	/* bcm stop and pd unprepare */
+	if (fw_func) {
+		pd_exit();
+		spin_lock_irqsave(&data->lock, flags);
+		if (fw_func->fw_stop(0, NULL, NULL))
+			hrtimer_try_to_cancel(&bcm_hrtimer);
+		fw_func->fw_cmd("0");
+		spin_unlock_irqrestore(&data->lock, flags);
+		fw_func->fw_exit();
+		fw_func = NULL;
+	}
+	if (value) {
+		if (!os_func.fdata) {
+			os_func.fdata = kzalloc(sizeof(struct output_data) *
+						BCM_MAX_DATA, GFP_KERNEL);
+			os_func.ldata = os_func.fdata + BCM_MAX_DATA;
+		} else {
+			memset((char *)os_func.fdata, 0x0,
+			       sizeof(struct output_data) * BCM_MAX_DATA);
+		}
+
+		/* load binary */
+		load_bcm_bin(NULL);
+	} else {
+		kfree(os_func.fdata);
+		os_func.fdata = NULL;
+		os_func.ldata = NULL;
+	}
+
+	return count;
+}
+
+static ssize_t show_load_bcm_fw(struct device *dev,
+					struct device_attribute *attr, char *buf)
+{
+	struct platform_device *pdev = container_of(dev,
+						    struct platform_device, dev);
+	struct bcm_monitor_data *data = platform_get_drvdata(pdev);
+	unsigned long flags;
+	ssize_t count = 0;
+
+	spin_lock_irqsave(&data->lock, flags);
+
+	if(fw_func ) {
+		count += snprintf(buf, PAGE_SIZE, "\n[PPMU_binary load]\n");
+		count += snprintf(buf, PAGE_SIZE, "\n %llx, %ld\n",
+				  (u64)data->bin_base, data->bin_size);
+	}
+
+	spin_unlock_irqrestore(&data->lock, flags);
+	return count;
+}
+
+#define BCM_START 1
+#define BCM_STOP 0
+
+static ssize_t store_cmd_bcm_fw(struct device *dev,
+					struct device_attribute *attr,
+					const char *buf, size_t count)
+{
+	struct platform_device *pdev = container_of(dev,
+						    struct platform_device, dev);
+	struct bcm_monitor_data *data = platform_get_drvdata(pdev);
+	char * info_str = NULL;
+	int cmd;
+	int option = 1;
+	int ret = 0;
+	unsigned long flags;
+
+	if (fw_func) {
+		ret = sscanf(buf, "%d %d", &cmd, &option);
+		switch (cmd) {
+		case BCM_STOP:
+			spin_lock_irqsave(&data->lock, flags);
+			if (fw_func->fw_stop(get_time(),
+					cal_dfs_cached_get_rate, NULL))
+				hrtimer_try_to_cancel(&bcm_hrtimer);
+			info_str = fw_func->fw_cmd(buf);
+			spin_unlock_irqrestore(&data->lock, flags);
+			switch (fw_func->get_outform()) {
+			case OUT_LOG:
+				bcm_log();
+				break;
+			default:
+				write_file(NULL);
+			}
+			break;
+		case BCM_START:
+			spin_lock_irqsave(&data->lock, flags);
+			info_str = fw_func->fw_cmd(buf);
+			spin_unlock_irqrestore(&data->lock, flags);
+			if (info_str && option)
+				bcm_start(NULL);
+			break;
+		default:
+			pd_exit();
+			spin_lock_irqsave(&data->lock, flags);
+			if (fw_func->fw_stop(get_time(),
+					cal_dfs_cached_get_rate, NULL))
+				hrtimer_try_to_cancel(&bcm_hrtimer);
+			info_str = fw_func->fw_cmd(buf);
+			spin_unlock_irqrestore(&data->lock, flags);
+			pd_init();
+			break;
+		}
+
+		if (info_str)
+			BCM_BDG ("command: %s\n", info_str);
+	} else {
+		BCM_BDG ("binary is not loaded!\n");
+	}
+
+	return count;
+}
+
+static ssize_t show_cmd_bcm_fw(struct device *dev,
+					struct device_attribute *attr, char *buf)
+{
+	struct platform_device *pdev = container_of(dev,
+						    struct platform_device, dev);
+	struct bcm_monitor_data *data = platform_get_drvdata(pdev);
+	ssize_t count = 0;
+	unsigned long flags;
+
+	if (fw_func) {
+		spin_lock_irqsave(&data->lock, flags);
+
+		if (fw_func->fw_show)
+			count += fw_func->fw_show(buf);
+
+		spin_unlock_irqrestore(&data->lock, flags);
+	} else {
+		BCM_BDG ("LDFW is not loaded!\n");
+	}
+	return count;
+}
+static DEVICE_ATTR(load_bin, 0640, show_load_bcm_fw, store_load_bcm_fw);
+static DEVICE_ATTR(command, 0640, show_cmd_bcm_fw, store_cmd_bcm_fw);
+
+static struct attribute *bcm_sysfs_entries[] = {
+	&dev_attr_load_bin.attr,
+	&dev_attr_command.attr,
+	NULL,
+};
+
+static struct attribute_group bcm_attr_group = {
+	.attrs	= bcm_sysfs_entries,
+};
+
+static void param_init(struct bcm_monitor_data *data)
+{
+	data->bin_base = (char *)fd_virt_addr;
+	data->bin_size = SZ_64K;
+}
+
+static int exynos_bcm_notifier_event(struct notifier_block *this,
+		unsigned long event,
+		void *ptr)
+{
+	unsigned long flags;
+
+	if (fw_func) {
+		switch ((unsigned int)event) {
+		case PM_POST_SUSPEND:
+			bcm_start(NULL);
+			return NOTIFY_OK;
+		case PM_SUSPEND_PREPARE:
+			spin_lock_irqsave(&g_data->lock, flags);
+			if (fw_func->fw_stop(get_time(),
+						cal_dfs_cached_get_rate, NULL))
+				hrtimer_try_to_cancel(&bcm_hrtimer);
+			fw_func->fw_cmd(NULL);
+			spin_unlock_irqrestore(&g_data->lock, flags);
+			return NOTIFY_OK;
+		}
+	}
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block exynos_bcm_notifier = {
+	.notifier_call = exynos_bcm_notifier_event,
+};
+
+static int bcm_probe(struct platform_device *pdev)
+{
+	int ret;
+
+	BCM_BDG("%s: bcm probe\n", __func__);
+
+	g_data = devm_kzalloc(&pdev->dev, sizeof(struct bcm_monitor_data),
+			GFP_KERNEL);
+	if (!g_data) {
+		dev_err(&pdev->dev, "failed to data resource alloc\n");
+		return -ENOMEM;
+	}
+	g_data->pdev = pdev;
+
+	platform_set_drvdata(pdev, g_data);
+	g_data = g_data;
+	spin_lock_init(&g_data->lock);
+
+	param_init(g_data);
+
+	ret = sysfs_create_group(&pdev->dev.kobj, &bcm_attr_group);
+	if (ret) {
+		dev_err(&pdev->dev, "failed create sysfs for sci debug data\n");
+		goto err_sysfs;
+	}
+
+	bcm_wq = create_freezable_workqueue("bcm_wq");
+	if (IS_ERR(bcm_wq)) {
+		pr_err("%s: couldn't create workqueue\n", __FILE__);
+		return PTR_ERR(bcm_wq);
+	}
+
+	work_file_out = (struct bcm_work_struct *)
+		devm_kzalloc(&pdev->dev, sizeof(struct bcm_work_struct),
+			     GFP_KERNEL);
+	INIT_WORK((struct work_struct *)work_file_out, write_file);
+
+	register_pm_notifier(&exynos_bcm_notifier);
+
+	hrtimer_init(&bcm_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+	bcm_hrtimer.function = &monitor_fn;
+
+err_sysfs:
+	return 0;
+}
+
+static int bcm_remove(struct platform_device *dev)
+{
+	return 0;
+}
+
+static const struct of_device_id bcm_dt_match[] = {
+	{
+		.compatible = "samsung,bcm",
+	},
+	{},
+};
+
+static struct platform_driver bcm_driver = {
+	.probe		= bcm_probe,
+	.remove		= bcm_remove,
+	.driver		= {
+		.name	= "bcm",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static struct platform_device bcm_device = {
+	.name	= "bcm",
+	.id	= -1,
+};
+
+static int __init bcm_setup(char *str)
+{
+	struct map_desc fd_table;
+	phys_addr_t fd_phys_addr;
+	if (kstrtoul(str, 0, (unsigned long *)&fd_virt_addr))
+		goto out;
+	fd_phys_addr = memblock_alloc(SZ_64K, SZ_4K);
+	fd_table.virtual = (ulong)fd_virt_addr;
+	fd_table.pfn = __phys_to_pfn(fd_phys_addr);
+	fd_table.length = SZ_64K;
+	fd_table.type = MT_MEMORY;
+
+	iotable_init_exec(&fd_table, 1);
+	return 0;
+out:
+	return -1;
+}
+__setup("bcm_setup=", bcm_setup);
+
+static int __init bcm_drv_register(void)
+{
+	int ret;
+	BCM_BDG("%s: bcm init\n", __func__);
+
+	if (!fd_virt_addr)
+		return -EINVAL;
+
+	ret = platform_device_register(&bcm_device );
+	if (ret)
+		return ret;
+
+	return platform_driver_register(&bcm_driver);
+}
+late_initcall(bcm_drv_register);
+
+MODULE_AUTHOR("Seokju Yoon <sukju.yoon@samsung.com>");
+MODULE_DESCRIPTION("Samsung BCM driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("interface:bcm");

drivers/soc/samsung/exynos-chipid.c

@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *	      http://www.samsung.com/
+ *
+ * EXYNOS - CHIP ID support
+ * Author: Pankaj Dubey <pankaj.dubey@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/sys_soc.h>
+#include <linux/soc/samsung/exynos-soc.h>
+
+#define EXYNOS_SUBREV_MASK	(0xF << 4)
+#define EXYNOS_MAINREV_MASK	(0xF << 0)
+#define EXYNOS_REV_MASK		(EXYNOS_SUBREV_MASK | EXYNOS_MAINREV_MASK)
+
+static void __iomem *exynos_chipid_base;
+
+struct exynos_chipid_info exynos_soc_info;
+EXPORT_SYMBOL(exynos_soc_info);
+
+static const char * __init product_id_to_name(unsigned int product_id)
+{
+	const char *soc_name;
+	unsigned int soc_id = product_id & EXYNOS_SOC_MASK;
+
+	switch (soc_id) {
+	case EXYNOS3250_SOC_ID:
+		soc_name = "EXYNOS3250";
+		break;
+	case EXYNOS4210_SOC_ID:
+		soc_name = "EXYNOS4210";
+		break;
+	case EXYNOS4212_SOC_ID:
+		soc_name = "EXYNOS4212";
+		break;
+	case EXYNOS4412_SOC_ID:
+		soc_name = "EXYNOS4412";
+		break;
+	case EXYNOS4415_SOC_ID:
+		soc_name = "EXYNOS4415";
+		break;
+	case EXYNOS5250_SOC_ID:
+		soc_name = "EXYNOS5250";
+		break;
+	case EXYNOS5260_SOC_ID:
+		soc_name = "EXYNOS5260";
+		break;
+	case EXYNOS5420_SOC_ID:
+		soc_name = "EXYNOS5420";
+		break;
+	case EXYNOS5440_SOC_ID:
+		soc_name = "EXYNOS5440";
+		break;
+	case EXYNOS5800_SOC_ID:
+		soc_name = "EXYNOS5800";
+		break;
+	case EXYNOS7570_SOC_ID:
+		soc_name = "EXYNOS7570";
+		break;
+	case EXYNOS7870_SOC_ID:
+		soc_name = "EXYNOS7870";
+		break;
+	case EXYNOS8890_SOC_ID:
+		soc_name = "EXYNOS8890";
+		break;
+	default:
+		soc_name = "UNKNOWN";
+	}
+	return soc_name;
+}
+
+static const struct of_device_id of_exynos_chipid_ids[] __initconst = {
+	{
+		.compatible	= "samsung,exynos4210-chipid",
+	},
+	{},
+};
+
+/**
+ *  exynos_chipid_early_init: Early chipid initialization
+ *  @dev: pointer to chipid device
+ */
+void __init exynos_chipid_early_init(struct device *dev)
+{
+	struct device_node *np;
+	const struct of_device_id *match;
+
+	if (exynos_chipid_base)
+		return;
+
+	if (!dev)
+		np = of_find_matching_node_and_match(NULL,
+			of_exynos_chipid_ids, &match);
+	else
+		np = dev->of_node;
+
+	if (!np)
+		panic("%s, failed to find chipid node\n", __func__);
+
+	exynos_chipid_base = of_iomap(np, 0);
+
+	if (!exynos_chipid_base)
+		panic("%s: failed to map registers\n", __func__);
+
+	exynos_soc_info.product_id  = __raw_readl(exynos_chipid_base);
+	exynos_soc_info.lot_id = __raw_readl(exynos_chipid_base + UNIQUE_ID1) & EXYNOS_LOTID_MASK;
+	exynos_soc_info.unique_id  = __raw_readl(exynos_chipid_base + UNIQUE_ID1);
+	exynos_soc_info.unique_id  |= (u64)__raw_readl(exynos_chipid_base + UNIQUE_ID2) << 32;
+	exynos_soc_info.revision = exynos_soc_info.product_id & EXYNOS_REV_MASK;
+}
+
+static int __init exynos_chipid_probe(struct platform_device *pdev)
+{
+	struct soc_device_attribute *soc_dev_attr;
+	struct soc_device *soc_dev;
+	struct device_node *root;
+	int ret;
+
+	exynos_chipid_early_init(&pdev->dev);
+
+	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+	if (!soc_dev_attr)
+		return -ENODEV;
+
+	soc_dev_attr->family = "Samsung Exynos";
+
+	root = of_find_node_by_path("/");
+	ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
+	of_node_put(root);
+	if (ret)
+		goto free_soc;
+
+	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d",
+					exynos_soc_info.revision);
+	if (!soc_dev_attr->revision)
+		goto free_soc;
+
+	soc_dev_attr->soc_id = product_id_to_name(exynos_soc_info.product_id);
+
+	soc_dev = soc_device_register(soc_dev_attr);
+	if (IS_ERR(soc_dev))
+		goto free_rev;
+
+	soc_device_to_device(soc_dev);
+
+	dev_info(&pdev->dev, "Exynos: CPU[%s] CPU_REV[0x%x] Detected\n",
+			product_id_to_name(exynos_soc_info.product_id),
+			exynos_soc_info.revision);
+	return 0;
+free_rev:
+	kfree(soc_dev_attr->revision);
+free_soc:
+	kfree(soc_dev_attr);
+	return -EINVAL;
+}
+
+static struct platform_driver exynos_chipid_driver __refdata = {
+	.driver = {
+		.name = "exynos-chipid",
+		.of_match_table = of_exynos_chipid_ids,
+	},
+	.probe = exynos_chipid_probe,
+};
+
+static int __init exynos_chipid_init(void)
+{
+	return platform_driver_register(&exynos_chipid_driver);
+}
+core_initcall(exynos_chipid_init);
+
+/*
+ *  sysfs implementation for exynos-snapshot
+ *  you can access the sysfs of exynos-snapshot to /sys/devices/system/chip-id
+ *  path.
+ */
+static struct bus_type chipid_subsys = {
+	.name = "chip-id",
+	.dev_name = "chip-id",
+};
+
+static ssize_t chipid_product_id_show(struct kobject *kobj,
+			         struct kobj_attribute *attr, char *buf)
+{
+	return snprintf(buf, 10, "%08X\n", exynos_soc_info.product_id);
+}
+
+static ssize_t chipid_lot_id_show(struct kobject *kobj,
+			         struct kobj_attribute *attr, char *buf)
+{
+	return snprintf(buf, 14, "%08X\n", exynos_soc_info.lot_id);
+}
+
+static ssize_t chipid_revision_show(struct kobject *kobj,
+			         struct kobj_attribute *attr, char *buf)
+{
+	return snprintf(buf, 14, "%08X\n", exynos_soc_info.revision);
+}
+
+static struct kobj_attribute chipid_product_id_attr =
+        __ATTR(product_id, 0644, chipid_product_id_show, NULL);
+
+static struct kobj_attribute chipid_lot_id_attr =
+        __ATTR(lot_id, 0644, chipid_lot_id_show, NULL);
+
+static struct kobj_attribute chipid_revision_attr =
+        __ATTR(revision, 0644, chipid_revision_show, NULL);
+
+static struct attribute *chipid_sysfs_attrs[] = {
+	&chipid_product_id_attr.attr,
+	&chipid_lot_id_attr.attr,
+	&chipid_revision_attr.attr,
+	NULL,
+};
+
+static struct attribute_group chipid_sysfs_group = {
+	.attrs = chipid_sysfs_attrs,
+};
+
+static const struct attribute_group *chipid_sysfs_groups[] = {
+	&chipid_sysfs_group,
+	NULL,
+};
+
+static int __init chipid_sysfs_init(void)
+{
+	int ret = 0;
+
+	ret = subsys_system_register(&chipid_subsys, chipid_sysfs_groups);
+	if (ret)
+		pr_err("fail to register exynos-snapshop subsys\n");
+
+	return ret;
+}
+late_initcall(chipid_sysfs_init);
+

drivers/soc/samsung/exynos-cpu_hotplug.c

@@ -0,0 +1,470 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *
+ * Park Bumgyu <bumgyu.park@samsung.com>
+ *
+ * CPU Hotplug driver for Exynos
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/cpu.h>
+#include <linux/kthread.h>
+#include <linux/of.h>
+#include <linux/pm_qos.h>
+#include <linux/suspend.h>
+
+static int cpu_hotplug_in(const struct cpumask *mask)
+{
+	int cpu, ret = 0;
+
+	for_each_cpu(cpu, mask) {
+		ret = cpu_up(cpu);
+		if (ret) {
+			/*
+			 * -EIO means core fail to come online by itself
+			 * it is critical error
+			 */
+			if (ret == -EIO)
+				panic("I/O error(-EIO) occurs while CPU%d comes online\n", cpu);
+
+			/*
+			 * If it fails to enable cpu,
+			 * it cancels cpu hotplug request and retries later.
+			 */
+			pr_err("%s: Failed to hotplug in CPU%d with error %d\n",
+								__func__, cpu, ret);
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int cpu_hotplug_out(const struct cpumask *mask)
+{
+	int cpu, ret = 0;
+
+	/*
+	 * Reverse order of cpu,
+	 * explore cpu7, cpu6, cpu5, ... cpu0
+	 */
+	for (cpu = nr_cpu_ids - 1; cpu > 0; cpu--) {
+		if (!cpumask_test_cpu(cpu, mask))
+			continue;
+
+		ret = cpu_down(cpu);
+		if (ret) {
+			pr_err("%s: Failed to hotplug out CPU%d with error %d\n",
+								__func__, cpu, ret);
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static struct {
+	/* Disable cpu hotplug operation */
+	bool			enabled;
+
+	/* flag for suspend */
+	bool			suspended;
+
+	/* Synchronizes accesses to refcount and cpumask */
+	struct mutex		lock;
+
+	/* all CPUs running time during booting */
+	int			boot_lock_time;
+
+	/* user input minimum and maximum online cpu */
+	int			user_min;
+	int			user_max;
+
+	/*
+	 * In blocking notifier call chain, it is not supposed to call
+	 * cpu_up() or cpu_down(). In this case, use workqueue.
+	 */
+	struct workqueue_struct	*workqueue;
+
+	/*
+	 * During reuesting cpu hotplug by other drivers, cpu hotplug framework
+	 * rejects cpu hotplug request. To guarantee the request, re-request cpu
+	 * hotplug using delayed work.
+	 */
+	struct delayed_work	delayed_work;
+
+	/* cpu_hotplug kobject */
+	struct kobject		*kobj;
+} cpu_hotplug = {
+	.lock = __MUTEX_INITIALIZER(cpu_hotplug.lock),
+};
+
+static inline void cpu_hotplug_suspend(bool enable)
+{
+	/* This lock guarantees completion of do_cpu_hotplug() */
+	mutex_lock(&cpu_hotplug.lock);
+	cpu_hotplug.suspended = enable;
+	mutex_unlock(&cpu_hotplug.lock);
+}
+
+static inline void update_enable_flag(bool enable)
+{
+	mutex_lock(&cpu_hotplug.lock);
+	cpu_hotplug.enabled = enable;
+	mutex_unlock(&cpu_hotplug.lock);
+}
+
+struct kobject *exynos_cpu_hotplug_kobj(void)
+{
+	return cpu_hotplug.kobj;
+}
+
+bool exynos_cpu_hotplug_enabled(void)
+{
+	return cpu_hotplug.enabled;
+}
+
+/*
+ * If somebody requests CPU hotplug, hotplug driver creates cpumask with minimum
+ * and maxinum online CPU in PM QoS. The number of online CPU will be same as
+ * minimum online CPU on the assumption that minimum online CPU is not greater
+ * than maximum online CPU. If mininum is greater than maximum, online CPU will
+ * be maximum.
+ */
+static struct cpumask create_cpumask(void)
+{
+	int online_cpu_min, online_cpu_max;
+	int cpu;
+	struct cpumask mask;
+
+	online_cpu_min = min(pm_qos_request(PM_QOS_CPU_ONLINE_MIN), nr_cpu_ids);
+	online_cpu_max = min(pm_qos_request(PM_QOS_CPU_ONLINE_MAX), nr_cpu_ids);
+
+	cpumask_clear(&mask);
+
+	for (cpu = 0; cpu < online_cpu_min; cpu++)
+		cpumask_set_cpu(cpu, &mask);
+
+	for (cpu = nr_cpu_ids - 1; cpu >= online_cpu_max; cpu--)
+		cpumask_clear_cpu(cpu, &mask);
+
+	return mask;
+}
+
+/*
+ * do_cpu_hotplug() is the main function for cpu hotplug. Only this function
+ * enables or disables cpus, so all APIs in this driver call do_cpu_hotplug()
+ * eventually.
+ */
+static int do_cpu_hotplug(void)
+{
+	int ret = 0;
+	struct cpumask disable_cpus, enable_cpus;
+	char cpus_buf[10];
+
+	mutex_lock(&cpu_hotplug.lock);
+
+	/*
+	 * If cpu hotplug is disabled or suspended,
+	 * do_cpu_hotplug() do nothing.
+	 */
+	if (!cpu_hotplug.enabled || cpu_hotplug.suspended) {
+		mutex_unlock(&cpu_hotplug.lock);
+		return 0;
+	}
+
+	/* Create online cpumask */
+	enable_cpus = create_cpumask();
+
+	/*
+	 * disable_cpus is the opposite of enable_cpus:
+	 * disable_cpus = ~enable_cpus
+	 */
+	cpumask_xor(&disable_cpus, cpu_possible_mask, &enable_cpus);
+
+	/*
+	 * Remove unnecessary cpumask bit:
+	 * enable_cpus = enable_cpus & ~online mask
+	 * disable_cpus = disable_cpus & online mask
+	 */
+	cpumask_andnot(&enable_cpus, &enable_cpus, cpu_online_mask);
+	cpumask_and(&disable_cpus, &disable_cpus, cpu_online_mask);
+
+	cpulist_scnprintf(cpus_buf, sizeof(cpus_buf), &enable_cpus);
+	pr_debug("%s: enable_cpus=%s\n", __func__, cpus_buf);
+	cpulist_scnprintf(cpus_buf, sizeof(cpus_buf), &disable_cpus);
+	pr_debug("%s: disable_cpus=%s\n", __func__, cpus_buf);
+
+	/* If request has the callback, call cpus_up() and cpus_down() */
+	if (!cpumask_empty(&enable_cpus)) {
+		ret = cpu_hotplug_in(&enable_cpus);
+		if (ret)
+			goto out;
+	}
+
+	if (!cpumask_empty(&disable_cpus))
+		ret = cpu_hotplug_out(&disable_cpus);
+
+out:
+	/* If it fails to complete cpu hotplug request, retries after 100ms */
+	if (ret)
+		queue_delayed_work(cpu_hotplug.workqueue, &cpu_hotplug.delayed_work,
+							msecs_to_jiffies(100));
+
+	mutex_unlock(&cpu_hotplug.lock);
+
+	return ret;
+}
+
+static void cpu_hotplug_work(struct work_struct *work)
+{
+	do_cpu_hotplug();
+}
+
+static int control_cpu_hotplug(bool enable)
+{
+	struct cpumask mask;
+	int ret = 0;
+
+	if (enable) {
+		update_enable_flag(true);
+		do_cpu_hotplug();
+	} else {
+		mutex_lock(&cpu_hotplug.lock);
+
+		cpumask_setall(&mask);
+		cpumask_andnot(&mask, &mask, cpu_online_mask);
+
+		/*
+		 * If it success to enable all CPUs, clear cpu_hotplug.enabled flag.
+		 * Since then all hotplug requests are ignored.
+		 */
+		ret = cpu_hotplug_in(&mask);
+		if (!ret) {
+			/*
+			 * In this position, can't use update_enable_flag()
+			 * because already taken cpu_hotplug.lock
+			 */
+			cpu_hotplug.enabled = false;
+		} else {
+			pr_err("Fail to disable cpu hotplug, please try again\n");
+		}
+
+		mutex_unlock(&cpu_hotplug.lock);
+	}
+
+	return ret;
+}
+
+/*
+ * If PM_QOS_CPU_ONLINE_MIN and PM_QOS_CPU_ONLINE_MAX request is updated,
+ * cpu_hotplug_qos_handler is called.
+ */
+static int cpu_hotplug_qos_handler(struct notifier_block *b,
+					 unsigned long val, void *v)
+{
+	return do_cpu_hotplug();
+}
+
+static struct notifier_block cpu_hotplug_qos_notifier = {
+	.notifier_call = cpu_hotplug_qos_handler,
+};
+
+/*
+ * User can change the number of online cpu by using min_online_cpu and
+ * max_online_cpu sysfs node. User input minimum and maxinum online cpu
+ * to this node as below:
+ *
+ * #echo min > /sys/power/cpuhotplug/min_online_cpu
+ * #echo max > /sys/power/cpuhotplug/max_online_cpus
+ */
+
+struct pm_qos_request user_min_cpu_hotplug_request;
+struct pm_qos_request user_max_cpu_hotplug_request;
+
+#define attr_online_cpu(type)						\
+static ssize_t show_##type##_online_cpu(struct kobject *kobj,		\
+	struct kobj_attribute *attr, char *buf)				\
+{									\
+	return snprintf(buf, 30, #type " online cpu : %d\n",		\
+			cpu_hotplug.user_##type);			\
+}									\
+									\
+static ssize_t store_##type##_online_cpu(struct kobject *kobj,		\
+	struct kobj_attribute *attr, const char *buf,			\
+	size_t count)							\
+{									\
+	int input;							\
+									\
+	if (!sscanf(buf, "%d", &input))					\
+		return -EINVAL;						\
+									\
+	if (input <= 0 || input > NR_CPUS)							\
+		return -EINVAL;						\
+									\
+	pm_qos_update_request(&user_##type##_cpu_hotplug_request,	\
+				input);					\
+	cpu_hotplug.user_##type = input;				\
+									\
+	return count;							\
+}									\
+									\
+static struct kobj_attribute type##_online_cpu =			\
+__ATTR(type##_online_cpu, 0644,					\
+	show_##type##_online_cpu, store_##type##_online_cpu)
+
+attr_online_cpu(min);
+attr_online_cpu(max);
+
+/*
+ * User can control the cpu hotplug operation as below:
+ *
+ * #echo 1 > /sys/power/cpuhotplug/enable => enable
+ * #echo 0 > /sys/power/cpuhotplug/enable => disable
+ *
+ * If disable become 0, hotplug driver enable the all cpus and no hotplug
+ * operation happen from hotplug driver.
+ */
+static ssize_t show_cpu_hotplug_enable(struct kobject *kobj,
+		struct kobj_attribute *attr, char *buf)
+{
+	return snprintf(buf, 10, "%d\n", cpu_hotplug.enabled);
+}
+
+static ssize_t store_cpu_hotplug_enable(struct kobject *kobj,
+		struct kobj_attribute *attr, const char *buf,
+		size_t count)
+{
+	int input;
+
+	if (!sscanf(buf, "%d", &input))
+		return -EINVAL;
+
+	control_cpu_hotplug(!!input);
+
+	return count;
+}
+
+static struct kobj_attribute cpu_hotplug_enabled =
+__ATTR(enable, 0644, show_cpu_hotplug_enable, store_cpu_hotplug_enable);
+
+static struct attribute *cpu_hotplug_attrs[] = {
+	&min_online_cpu.attr,
+	&max_online_cpu.attr,
+	&cpu_hotplug_enabled.attr,
+	NULL,
+};
+
+static const struct attribute_group cpu_hotplug_group = {
+	.attrs = cpu_hotplug_attrs,
+};
+
+static void __init cpu_hotplug_dt_init(void)
+{
+	struct device_node *np = of_find_node_by_name(NULL, "cpu_hotplug");
+
+	if (of_property_read_u32(np, "boot_lock_time", &cpu_hotplug.boot_lock_time))
+		pr_warn("boot_lock_time property is omitted!\n");
+}
+
+static int exynos_cpu_hotplug_pm_notifier(struct notifier_block *notifier,
+				       unsigned long pm_event, void *v)
+{
+	switch (pm_event) {
+	case PM_SUSPEND_PREPARE:
+		cpu_hotplug_suspend(true);
+		break;
+
+	case PM_POST_SUSPEND:
+		cpu_hotplug_suspend(false);
+		do_cpu_hotplug();
+		break;
+	}
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block exynos_cpu_hotplug_nb = {
+	.notifier_call = exynos_cpu_hotplug_pm_notifier,
+};
+
+
+static struct pm_qos_request boot_min_cpu_hotplug_request;
+static void __init cpu_hotplug_pm_qos_init(void)
+{
+	/* Register PM QoS notifier handler */
+	pm_qos_add_notifier(PM_QOS_CPU_ONLINE_MIN, &cpu_hotplug_qos_notifier);
+	pm_qos_add_notifier(PM_QOS_CPU_ONLINE_MAX, &cpu_hotplug_qos_notifier);
+
+	/* Guarantee all CPUs running during booting time */
+	pm_qos_add_request(&boot_min_cpu_hotplug_request,
+		PM_QOS_CPU_ONLINE_MIN, NR_CPUS);
+	pm_qos_update_request_timeout(&boot_min_cpu_hotplug_request,
+		NR_CPUS, cpu_hotplug.boot_lock_time * USEC_PER_SEC);
+
+	/* Add PM QoS for sysfs node */
+#if defined(CONFIG_EXYNOS_HOTPLUG_GOVERNOR)
+	pm_qos_add_request(&user_min_cpu_hotplug_request,
+		PM_QOS_CPU_ONLINE_MIN, PM_QOS_CPU_ONLINE_MIN_DEFAULT_VALUE);
+	pm_qos_add_request(&user_max_cpu_hotplug_request,
+		PM_QOS_CPU_ONLINE_MAX, PM_QOS_CPU_ONLINE_MAX_DEFAULT_VALUE);
+#else
+	pm_qos_add_request(&user_min_cpu_hotplug_request,
+		PM_QOS_CPU_ONLINE_MIN, PM_QOS_CPU_ONLINE_MAX_DEFAULT_VALUE);
+	pm_qos_add_request(&user_max_cpu_hotplug_request,
+		PM_QOS_CPU_ONLINE_MAX, PM_QOS_CPU_ONLINE_MAX_DEFAULT_VALUE);
+#endif
+}
+
+static void __init cpu_hotplug_sysfs_init(void)
+{
+	cpu_hotplug.kobj = kobject_create_and_add("cpuhotplug", power_kobj);
+	if (!cpu_hotplug.kobj) {
+		pr_err("Fail to create cpu_hotplug kboject\n");
+		return;
+	}
+
+	/* Create /sys/power/cpuhotplug */
+	if (sysfs_create_group(cpu_hotplug.kobj, &cpu_hotplug_group)) {
+		pr_err("Fail to create cpu_hotplug group\n");
+		return;
+	}
+
+	/* link cpuhotplug directory to /sys/devices/system/cpu/cpuhotplug */
+	if (sysfs_create_link(&cpu_subsys.dev_root->kobj, cpu_hotplug.kobj, "cpuhotplug"))
+		pr_err("Fail to link cpuhotplug directory");
+}
+
+static int __init cpu_hotplug_init(void)
+{
+	/* Initialize delayed work */
+	INIT_DELAYED_WORK(&cpu_hotplug.delayed_work, cpu_hotplug_work);
+
+	/* Initialize workqueue */
+	cpu_hotplug.workqueue = alloc_workqueue("%s", WQ_HIGHPRI | WQ_UNBOUND |\
+					WQ_MEM_RECLAIM | WQ_FREEZABLE,
+					1, "exynos_cpu_hotplug");
+	if (!cpu_hotplug.workqueue)
+		return -ENOMEM;
+
+	/* Parse data from device tree */
+	cpu_hotplug_dt_init();
+
+	/* Initialize pm_qos request and handler */
+	cpu_hotplug_pm_qos_init();
+
+	/* Create sysfs */
+	cpu_hotplug_sysfs_init();
+
+	/* register pm notifier */
+	register_pm_notifier(&exynos_cpu_hotplug_nb);
+
+	/* Enable cpu_hotplug */
+	update_enable_flag(true);
+
+	return 0;
+}
+arch_initcall(cpu_hotplug_init);

drivers/soc/samsung/exynos-el3_mon.c

@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *	      http://www.samsung.com/
+ *
+ * EXYNOS - EL3 monitor support
+ * Author: Jang Hyunsung <hs79.jang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/slab.h>
+#include <linux/smc.h>
+#include <asm/cacheflush.h>
+
+#define EXYNOS_EXCEPTION_FROM_SHIFT			(63)
+
+#define EXYNOS_EXCEPTION_FROM_EL3			(1)
+#define EXYNOS_EXCEPTION_FROM_EL1			(0)
+
+#define EXYNOS_EXCEPTION_ETYPE_MAX_NUM			(6)
+#define EXYNOS_EXCEPTION_ETYPE_MASK			(0x7)
+
+static char *smc_lockup;
+
+static int  __init exynos_set_debug_mem(void)
+{
+	int ret;
+	static char *smc_debug_mem;
+	char *phys;
+
+	smc_debug_mem = kmalloc(PAGE_SIZE, GFP_KERNEL);
+
+	if (!smc_debug_mem) {
+		pr_err("%s: kmalloc for smc_debug failed.\n", __func__);
+		return 0;
+	}
+
+	/* to map & flush memory */
+	memset(smc_debug_mem, 0x00, PAGE_SIZE);
+	__dma_flush_range(smc_debug_mem, smc_debug_mem+PAGE_SIZE);
+
+	phys = (char *)virt_to_phys(smc_debug_mem);
+	pr_err("%s: alloc kmem for smc_dbg virt: 0x%p phys: 0x%p size: %ld.\n",
+			__func__, smc_debug_mem, phys, PAGE_SIZE);
+	ret = exynos_smc(SMC_CMD_SET_DEBUG_MEM, (u64)phys, (u64)PAGE_SIZE, 0);
+
+	/* correct return value is input size */
+	if (ret != PAGE_SIZE) {
+		pr_err("%s: Can not set the address to el3 monitor. "
+				"ret = 0x%x. free the kmem\n", __func__, ret);
+		kfree(smc_debug_mem);
+	}
+
+	return 0;
+}
+arch_initcall(exynos_set_debug_mem);
+
+static int  __init exynos_get_reason_mem(void)
+{
+	smc_lockup = kmalloc(PAGE_SIZE, GFP_KERNEL);
+
+	if (!smc_lockup) {
+		pr_err("%s: kmalloc for smc_lockup failed.\n", __func__);
+		smc_lockup = NULL;
+	}
+
+	return 0;
+}
+arch_initcall(exynos_get_reason_mem);
+
+struct __exception_info {
+	unsigned long exception_type;
+	unsigned long sp_el1;
+	unsigned long sp_el3;
+	unsigned long elr_el3;
+	unsigned long esr_el3;
+};
+
+struct __lockup_info {
+	struct __exception_info exception_info[NR_CPUS];
+};
+
+static const char *ename[] = {
+	"info38961",
+	"sync",
+	"irq",
+	"fiq",
+	"async",
+	"stack corruption",
+	"unknown"
+};
+
+static const char *el_mode[] = {
+	"el1 mode",
+	"el3 mode"
+};
+
+
+static int exynos_parse_reason(struct __lockup_info *ptr)
+{
+	int i, count, ekind, efrom;
+	struct __lockup_info *lockup_info = ptr;
+	unsigned long etype, elr_el3, sp_el1, sp_el3, esr_el3;
+
+	for(i = 0, count = 0; i < NR_CPUS; i++) {
+		etype = lockup_info->exception_info[i].exception_type;
+
+		if (!etype) {
+			/* this core has not got stuck in EL3 monitor */
+			continue;
+		}
+
+		/* add 1 to count for the core got stuck in EL3 monitor */
+		count++;
+
+		/* parsing the information */
+		ekind = (etype & EXYNOS_EXCEPTION_ETYPE_MASK) > EXYNOS_EXCEPTION_ETYPE_MAX_NUM	\
+			? EXYNOS_EXCEPTION_ETYPE_MAX_NUM : (etype & EXYNOS_EXCEPTION_ETYPE_MASK) - 1;
+		efrom = (etype >> EXYNOS_EXCEPTION_FROM_SHIFT) & 0x1;
+		elr_el3 = lockup_info->exception_info[i].elr_el3;
+		sp_el1 = lockup_info->exception_info[i].sp_el1;
+		sp_el3 = lockup_info->exception_info[i].sp_el3;
+		esr_el3 = lockup_info->exception_info[i].esr_el3;
+
+		/* it got stuck due to unexpected exception */
+		pr_emerg("%s: %dth core gets stuck in EL3 monitor due to " \
+			"%s exception from %s.\n", \
+			 __func__, i, ename[ekind], el_mode[efrom]);
+		pr_emerg("%s: elr 0x%lx sp_el1 0x%lx sp_el3 0x%lx " \
+			"esr_el3 0x%lx\n", __func__, elr_el3, sp_el1, \
+			sp_el3, esr_el3);
+	}
+
+	/* count should be more than '1' */
+	return !count;
+}
+
+int exynos_check_hardlockup_reason(void)
+{
+	int ret;
+	char *phys;
+
+	if (!smc_lockup) {
+		pr_err("%s: fail to alloc memory for storing lockup info.\n",
+			__func__);
+		ret = -EINVAL;
+		goto check_exit;
+	}
+
+	/* to map & flush memory */
+	memset(smc_lockup, 0x00, PAGE_SIZE);
+	__dma_flush_range(smc_lockup, smc_lockup + PAGE_SIZE);
+
+	phys = (char *)virt_to_phys(smc_lockup);
+	pr_err("%s: smc_lockup virt: 0x%p phys: 0x%p size: %ld.\n",
+			__func__, smc_lockup, phys, PAGE_SIZE);
+
+	ret = exynos_smc(SMC_CMD_GET_LOCKUP_REASON, (u64)phys, (u64)PAGE_SIZE, 0);
+
+	if (ret) {
+		pr_emerg("%s: SMC_CMD_GET_LOCKUP_REASON returns 0x%x. fail " \
+			"to get the information.\n",  __func__, ret);
+		goto check_exit;
+	}
+
+	ret = exynos_parse_reason((struct __lockup_info *)smc_lockup);
+
+check_exit:
+	return ret;
+}

drivers/soc/samsung/exynos-hotplug_governor.c

@@ -0,0 +1,521 @@
+/*
+ * linux/drivers/exynos/soc/samsung/exynos-hotplug_governor.c
+ *
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/cpumask.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/kthread.h>
+#include <linux/kobject.h>
+#include <linux/ktime.h>
+#include <linux/hrtimer.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/cpu.h>
+#include <linux/stringify.h>
+#include <linux/sched.h>
+#include <linux/platform_device.h>
+#include <linux/debugfs.h>
+#include <linux/cpu_pm.h>
+#include <linux/cpu.h>
+#include <linux/cpufreq.h>
+#include <linux/sched.h>
+#include <linux/fb.h>
+#include <linux/irq_work.h>
+#include <linux/workqueue.h>
+#include <linux/pm_qos.h>
+
+#include <soc/samsung/cpufreq.h>
+#include <soc/samsung/exynos-cpu_hotplug.h>
+
+#include <asm/atomic.h>
+#include <asm/page.h>
+#define CREATE_TRACE_POINTS
+#include <trace/events/hotplug_governor.h>
+
+#include "../../cpufreq/cpu_load_metric.h"
+
+#define DEFAULT_UP_CHANGE_FREQ		(1300000)	/* MHz */
+#define DEFAULT_DOWN_CHANGE_FREQ	(800000)	/* MHz */
+#define DEFAULT_MONITOR_MS		(100)		/* ms */
+#define DEFAULT_BOOT_ENABLE_MS (30000)		/* 30 s */
+#define RETRY_BOOT_ENABLE_MS (100)		/* 100 ms */
+
+enum hpgov_event {
+	HPGOV_DYNAMIC,
+	HPGOV_EVENT_END,
+};
+
+typedef enum {
+	H0,
+	H1,
+	MAX_HSTATE,
+} hstate_t;
+
+typedef enum {
+	GO_DOWN,
+	GO_UP,
+	STAY,
+} action_t;
+
+struct hpgov_attrib {
+	struct kobj_attribute	enabled;
+	struct kobj_attribute	up_freq;
+	struct kobj_attribute	down_freq;
+	struct kobj_attribute	rate;
+	struct kobj_attribute	load;
+
+	struct attribute_group	attrib_group;
+};
+
+struct hpgov_data {
+	enum hpgov_event event;
+	int req_cpu_max;
+	int req_cpu_min;
+};
+
+struct {
+	uint32_t			enabled;
+	atomic_t			cur_cpu_max;
+	atomic_t			cur_cpu_min;
+	uint32_t			down_freq;
+	uint32_t			up_freq;
+	uint32_t			rate;
+	uint32_t			load;
+
+	struct hpgov_attrib		attrib;
+	struct mutex			attrib_lock;
+	struct task_struct		*task;
+	struct task_struct		*hptask;
+	struct irq_work			update_irq_work;
+	struct hpgov_data		data;
+	int				hp_state;
+	wait_queue_head_t		wait_q;
+	wait_queue_head_t		wait_hpq;
+} exynos_hpgov;
+
+struct cpu_hstate {
+	hstate_t state;
+	int cpu_nr;
+} hstate_state[] = {
+	{
+		.state = H0,
+		.cpu_nr = NR_CPUS,
+	}, {
+		.state = H1,
+		.cpu_nr = NR_CPUS / 2,
+	},
+};
+
+#define MONITOR_DURATION_NUM   3
+#define TASKS_THRESHOLD		6
+#define DEFAULT_LOAD_THRESHOLD	320
+#define MAX_CLUSTERS   2
+static atomic_t freq_history[MAX_CLUSTERS] =  {ATOMIC_INIT(0), ATOMIC_INIT(0)};
+static struct delayed_work hpgov_dynamic_work;
+
+static struct pm_qos_request hpgov_max_pm_qos;
+static struct pm_qos_request hpgov_min_pm_qos;
+
+static DEFINE_SPINLOCK(hpgov_lock);
+
+enum {
+	HP_STATE_WAITING = 0,		/* waiting for cpumask update */
+	HP_STATE_SCHEDULED = 1,		/* hotplugging is scheduled */
+	HP_STATE_IN_PROGRESS = 2,	/* in the process of hotplugging */
+};
+
+static void exynos_hpgov_irq_work(struct irq_work *irq_work)
+{
+	wake_up(&exynos_hpgov.wait_q);
+}
+
+static int exynos_hpgov_update_governor(enum hpgov_event event, int req_cpu_max, int req_cpu_min)
+{
+	int ret = 0;
+	int cur_cpu_max = atomic_read(&exynos_hpgov.cur_cpu_max);
+	int cur_cpu_min = atomic_read(&exynos_hpgov.cur_cpu_min);
+
+	switch(event) {
+	default:
+		break;
+	}
+
+	if (req_cpu_max == cur_cpu_max)
+		req_cpu_max = 0;
+
+	if (req_cpu_min == cur_cpu_min)
+		req_cpu_min = 0;
+
+	if (!req_cpu_max && !req_cpu_min)
+		return ret;
+
+	trace_exynos_hpgov_governor_update(event, req_cpu_max, req_cpu_min);
+	if (req_cpu_max)
+		atomic_set(&exynos_hpgov.cur_cpu_max, req_cpu_max);
+	if (req_cpu_min)
+		atomic_set(&exynos_hpgov.cur_cpu_min, req_cpu_min);
+
+	exynos_hpgov.hp_state = HP_STATE_SCHEDULED;
+	wake_up(&exynos_hpgov.wait_hpq);
+
+	return ret;
+}
+
+static int exynos_hpgov_do_update_governor(void *data)
+{
+	struct hpgov_data *pdata = (struct hpgov_data *)data;
+	unsigned long flags;
+	enum hpgov_event event;
+	int req_cpu_max;
+	int req_cpu_min;
+
+	while (1) {
+		wait_event(exynos_hpgov.wait_q, pdata->event || kthread_should_stop());
+		if (kthread_should_stop())
+			break;
+
+		spin_lock_irqsave(&hpgov_lock, flags);
+		event = pdata->event;
+		req_cpu_max = pdata->req_cpu_max;
+		req_cpu_min = pdata->req_cpu_min;
+		pdata->event = 0;
+		pdata->req_cpu_max = 0;
+		pdata->req_cpu_min = 0;
+		spin_unlock_irqrestore(&hpgov_lock, flags);
+
+		exynos_hpgov_update_governor(event, req_cpu_max, req_cpu_min);
+	}
+	return 0;
+}
+
+static int exynos_hpgov_do_hotplug(void *data)
+{
+	int *event = (int *)data;
+	int cpu_max;
+	int cpu_min;
+	int last_max = 0;
+	int last_min = 0;
+
+	while (1) {
+		wait_event(exynos_hpgov.wait_hpq, *event || kthread_should_stop());
+		if (kthread_should_stop())
+			break;
+
+restart:
+		exynos_hpgov.hp_state = HP_STATE_IN_PROGRESS;
+		cpu_max = atomic_read(&exynos_hpgov.cur_cpu_max);
+		cpu_min = atomic_read(&exynos_hpgov.cur_cpu_min);
+
+		if (cpu_max != last_max) {
+			pm_qos_update_request(&hpgov_max_pm_qos, cpu_max);
+			last_max = cpu_max;
+		}
+
+		if (cpu_min != last_min) {
+			pm_qos_update_request(&hpgov_min_pm_qos, cpu_min);
+			last_min = cpu_min;
+		}
+
+		exynos_hpgov.hp_state = HP_STATE_WAITING;
+		if (last_max != atomic_read(&exynos_hpgov.cur_cpu_max) ||
+			last_min != atomic_read(&exynos_hpgov.cur_cpu_min))
+			goto restart;
+	}
+
+	return 0;
+}
+
+static int exynos_hpgov_set_enabled(uint32_t enable)
+{
+	int ret = 0;
+	static uint32_t last_enable;
+
+	enable = (enable > 0) ? 1 : 0;
+	if (last_enable == enable)
+		return ret;
+
+	last_enable = enable;
+
+	if (enable) {
+		exynos_hpgov.task = kthread_create(exynos_hpgov_do_update_governor,
+					      &exynos_hpgov.data, "exynos_hpgov");
+		if (IS_ERR(exynos_hpgov.task))
+			return -EFAULT;
+
+		kthread_bind(exynos_hpgov.task, 0);
+		wake_up_process(exynos_hpgov.task);
+
+		exynos_hpgov.hptask = kthread_create(exynos_hpgov_do_hotplug,
+						&exynos_hpgov.hp_state, "exynos_hp");
+		if (IS_ERR(exynos_hpgov.hptask)) {
+			kthread_stop(exynos_hpgov.task);
+			return -EFAULT;
+		}
+
+		kthread_bind(exynos_hpgov.hptask, 0);
+		wake_up_process(exynos_hpgov.hptask);
+
+		exynos_hpgov.enabled = 1;
+#ifndef CONFIG_SCHED_HMP
+		queue_delayed_work_on(0, system_freezable_wq, &hpgov_dynamic_work, msecs_to_jiffies(exynos_hpgov.rate));
+#endif
+	} else {
+		kthread_stop(exynos_hpgov.hptask);
+		kthread_stop(exynos_hpgov.task);
+#ifndef CONFIG_SCHED_HMP
+		cancel_delayed_work_sync(&hpgov_dynamic_work);
+#endif
+		exynos_hpgov.enabled = 0;
+
+		smp_wmb();
+
+		pm_qos_update_request(&hpgov_max_pm_qos, PM_QOS_CPU_ONLINE_MAX_DEFAULT_VALUE);
+		pm_qos_update_request(&hpgov_min_pm_qos, PM_QOS_CPU_ONLINE_MAX_DEFAULT_VALUE);
+
+		atomic_set(&exynos_hpgov.cur_cpu_max, PM_QOS_CPU_ONLINE_MAX_DEFAULT_VALUE);
+		atomic_set(&exynos_hpgov.cur_cpu_min, PM_QOS_CPU_ONLINE_MAX_DEFAULT_VALUE);
+	}
+
+	return ret;
+}
+
+static int exynos_hpgov_set_load(uint32_t val)
+{
+	exynos_hpgov.load = val;
+
+	return 0;
+}
+
+static int exynos_hpgov_set_rate(uint32_t val)
+{
+	exynos_hpgov.rate = val;
+
+	return 0;
+}
+
+static int exynos_hpgov_set_up_freq(uint32_t val)
+{
+	exynos_hpgov.up_freq = val;
+
+	return 0;
+}
+
+static int exynos_hpgov_set_down_freq(uint32_t val)
+{
+	exynos_hpgov.down_freq = val;
+
+	return 0;
+}
+
+#define HPGOV_PARAM(_name, _param) \
+static ssize_t exynos_hpgov_attr_##_name##_show(struct kobject *kobj, \
+			struct kobj_attribute *attr, char *buf) \
+{ \
+	return snprintf(buf, PAGE_SIZE, "%d\n", _param); \
+} \
+static ssize_t exynos_hpgov_attr_##_name##_store(struct kobject *kobj, \
+		struct kobj_attribute *attr, const char *buf, size_t count) \
+{ \
+	int ret = 0; \
+	uint32_t val; \
+	uint32_t old_val; \
+	mutex_lock(&exynos_hpgov.attrib_lock); \
+	ret = kstrtouint(buf, 10, &val); \
+	if (ret) { \
+		pr_err("Invalid input %s for %s %d\n", \
+				buf, __stringify(_name), ret);\
+		mutex_unlock(&exynos_hpgov.attrib_lock); \
+		return 0; \
+	} \
+	old_val = _param; \
+	ret = exynos_hpgov_set_##_name(val); \
+	if (ret) { \
+		pr_err("Error %d returned when setting param %s to %d\n",\
+				ret, __stringify(_name), val); \
+		_param = old_val; \
+	} \
+	mutex_unlock(&exynos_hpgov.attrib_lock); \
+	return count; \
+}
+
+#define HPGOV_RW_ATTRIB(i, _name) \
+	exynos_hpgov.attrib._name.attr.name = __stringify(_name); \
+	exynos_hpgov.attrib._name.attr.mode = S_IRUGO | S_IWUSR; \
+	exynos_hpgov.attrib._name.show = exynos_hpgov_attr_##_name##_show; \
+	exynos_hpgov.attrib._name.store = exynos_hpgov_attr_##_name##_store; \
+	exynos_hpgov.attrib.attrib_group.attrs[i] = &exynos_hpgov.attrib._name.attr;
+
+HPGOV_PARAM(enabled, exynos_hpgov.enabled);
+HPGOV_PARAM(up_freq, exynos_hpgov.up_freq);
+HPGOV_PARAM(down_freq, exynos_hpgov.down_freq);
+HPGOV_PARAM(rate, exynos_hpgov.rate);
+HPGOV_PARAM(load, exynos_hpgov.load);
+
+static void hpgov_boot_enable(struct work_struct *work);
+static DECLARE_DELAYED_WORK(hpgov_boot_work, hpgov_boot_enable);
+static void hpgov_boot_enable(struct work_struct *work)
+{
+	if (exynos_hpgov_set_enabled(1))
+		schedule_delayed_work_on(0, &hpgov_boot_work, msecs_to_jiffies(RETRY_BOOT_ENABLE_MS));
+}
+
+static action_t exynos_hpgov_select_up_down(void)
+{
+	unsigned int down_freq, up_freq;
+	unsigned int c0_freq, c1_freq;
+	unsigned int c0_util, c1_util;
+	unsigned int load;
+	struct cluster_stats cl_stat[2];
+	int nr;
+
+	nr = nr_running();
+
+	cpumask_copy(cl_stat[0].mask, topology_core_cpumask(0));
+	cpumask_copy(cl_stat[1].mask, topology_core_cpumask(4));
+	get_cluster_stats(cl_stat);
+
+	c0_freq = cpufreq_quick_get(0);	/* 0 : first cpu number for Cluster 0 */
+	c1_freq = cpufreq_quick_get(4); /* 4 : first cpu number for Cluster 1 */
+
+	c0_util = cl_stat[0].util;
+	c1_util = cl_stat[1].util;
+
+	down_freq = exynos_hpgov.down_freq;
+	up_freq = exynos_hpgov.up_freq;
+
+	load = exynos_hpgov.load;
+
+	if (((c1_freq <= down_freq) && (c0_freq <= down_freq)) &&
+			((c1_util <= load) && (c0_util <= load))) {
+		atomic_inc(&freq_history[GO_DOWN]);
+		atomic_set(&freq_history[GO_UP], 0);
+	} else if (((c0_freq >= up_freq) || (c1_freq >= up_freq)) &&
+			((c0_util >= load) || nr >= TASKS_THRESHOLD)) {
+		atomic_inc(&freq_history[GO_UP]);
+		atomic_set(&freq_history[GO_DOWN], 0);
+	} else {
+		atomic_set(&freq_history[GO_UP], 0);
+		atomic_set(&freq_history[GO_DOWN], 0);
+	}
+
+	if (atomic_read(&freq_history[GO_UP]) > MONITOR_DURATION_NUM)
+		return GO_UP;
+	else if (atomic_read(&freq_history[GO_DOWN]) > MONITOR_DURATION_NUM)
+		return GO_DOWN;
+
+	return STAY;
+}
+
+static hstate_t exynos_hpgov_hotplug_adjust_state(action_t move, hstate_t old_state)
+{
+	hstate_t state;
+
+	if (move == GO_DOWN) {
+		state = old_state + 1;
+		if ((int)state >= (int)MAX_HSTATE)
+			state = MAX_HSTATE - 1;
+	} else {
+		state = old_state - 1;
+		if ((int)state < (int)H0)
+			state = H0;
+	}
+
+	return state;
+}
+
+static hstate_t exynos_hpgov_hstate_get_index(int nr)
+{
+	int i, size;
+
+	size = ARRAY_SIZE(hstate_state);
+
+	for (i = 0; i < size; i++)
+		if (hstate_state[i].cpu_nr == nr)
+			return hstate_state[i].state;
+
+	return MAX_HSTATE;
+}
+
+static void hpgov_dynamic_monitor(struct work_struct *work)
+{
+	action_t action;
+	hstate_t state, old_state;
+	int nr;
+
+	action = exynos_hpgov_select_up_down();
+
+	if (action != STAY) {
+		nr = num_online_cpus();
+		old_state = exynos_hpgov_hstate_get_index(nr);
+		state = exynos_hpgov_hotplug_adjust_state(action, old_state);
+		if (state < MAX_HSTATE && old_state != state) {
+			nr = hstate_state[state].cpu_nr;
+			exynos_hpgov_update_governor(HPGOV_DYNAMIC, NR_CPUS, nr);
+		}
+
+		atomic_set(&freq_history[GO_UP], 0);
+		atomic_set(&freq_history[GO_DOWN], 0);
+	}
+
+	queue_delayed_work_on(0, system_freezable_wq, &hpgov_dynamic_work, msecs_to_jiffies(100));
+}
+
+static int __init exynos_hpgov_init(void)
+{
+	int ret = 0;
+	const int attr_count = 5;
+
+	mutex_init(&exynos_hpgov.attrib_lock);
+	init_waitqueue_head(&exynos_hpgov.wait_q);
+	init_waitqueue_head(&exynos_hpgov.wait_hpq);
+	init_irq_work(&exynos_hpgov.update_irq_work, exynos_hpgov_irq_work);
+	INIT_DELAYED_WORK(&hpgov_dynamic_work, hpgov_dynamic_monitor);
+
+	exynos_hpgov.attrib.attrib_group.attrs =
+		kzalloc(attr_count * sizeof(struct attribute *), GFP_KERNEL);
+	if (!exynos_hpgov.attrib.attrib_group.attrs) {
+		ret = -ENOMEM;
+		goto done;
+	}
+
+	HPGOV_RW_ATTRIB(0, enabled);
+#ifndef CONFIG_SCHED_HMP
+	HPGOV_RW_ATTRIB(1, up_freq);
+	HPGOV_RW_ATTRIB(2, down_freq);
+	HPGOV_RW_ATTRIB(3, rate);
+	HPGOV_RW_ATTRIB(4, load);
+#endif
+
+	exynos_hpgov.attrib.attrib_group.name = "governor";
+	ret = sysfs_create_group(exynos_cpu_hotplug_kobj(), &exynos_hpgov.attrib.attrib_group);
+	if (ret)
+		pr_err("Unable to create sysfs objects :%d\n", ret);
+
+	atomic_set(&exynos_hpgov.cur_cpu_max, PM_QOS_CPU_ONLINE_MAX_DEFAULT_VALUE);
+	atomic_set(&exynos_hpgov.cur_cpu_min, PM_QOS_CPU_ONLINE_MIN_DEFAULT_VALUE);
+
+	pm_qos_add_request(&hpgov_max_pm_qos, PM_QOS_CPU_ONLINE_MAX, PM_QOS_CPU_ONLINE_MAX_DEFAULT_VALUE);
+	pm_qos_add_request(&hpgov_min_pm_qos, PM_QOS_CPU_ONLINE_MIN, PM_QOS_CPU_ONLINE_MIN_DEFAULT_VALUE);
+
+	exynos_hpgov.down_freq = DEFAULT_DOWN_CHANGE_FREQ;
+	exynos_hpgov.up_freq = DEFAULT_UP_CHANGE_FREQ;
+	exynos_hpgov.rate = DEFAULT_MONITOR_MS;
+	exynos_hpgov.load = DEFAULT_LOAD_THRESHOLD;
+
+	schedule_delayed_work_on(0, &hpgov_boot_work, msecs_to_jiffies(DEFAULT_BOOT_ENABLE_MS));
+
+done:
+	return ret;
+}
+late_initcall(exynos_hpgov_init);
+

drivers/soc/samsung/exynos-mcinfo.c

@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *	      http://www.samsung.com/
+ *
+ * Exynos - Support Memory controller specific information
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/debugfs.h>
+
+struct mcinfo_data {
+	struct device	*dev;
+	void __iomem	**base;
+
+	u32		basecnt;
+	u32		irqcnt;
+	u32		bit_array[2];
+};
+
+#if defined(CONFIG_MCINFO_SYSFS)
+static ssize_t show_exynos_ref_rate(struct device *dev,
+			struct device_attribute *attr, char *buf)
+{
+	struct mcinfo_data *data = dev_get_drvdata(dev);
+	ssize_t count = 0;
+	unsigned int tmp;
+	int i = 0;
+
+	count = snprintf(buf, PAGE_SIZE, "HW Refreshing rate\n");
+
+	for (i = 0; i < data->basecnt; i++) {
+		tmp = __raw_readl(data->base[i])
+			<< (31 - data->bit_array[0] - data->bit_array[1])
+			>> (31 - data->bit_array[1]);
+		count += snprintf(buf + count, PAGE_SIZE,
+			"HwTempRange#%d: 0x%x\n", i, tmp);
+	}
+
+	return count;
+}
+static DEVICE_ATTR(ref_rate, 0640, show_exynos_ref_rate, NULL);
+
+static struct attribute *exynos_mcinfo_sysfs_entries[] = {
+	&dev_attr_ref_rate.attr,
+	NULL,
+};
+
+static struct attribute_group exynos_mcinfo_attr_group = {
+	.name	= "ref_rate",
+	.attrs	= exynos_mcinfo_sysfs_entries,
+};
+#endif /* MCINFO_SYSFS */
+
+#if defined(CONFIG_SOC_EXYNOS7870)
+static irqreturn_t exynos_mc_irq_handler(int irq, void *p)
+{
+	unsigned int memory_stat;
+	unsigned int mr4;
+	struct mcinfo_data *data = p;
+	int i;
+
+	pr_err("DREX high temperature\n");
+	for (i = 0; i < data->basecnt; i++) {
+		memory_stat = __raw_readl(data->base[i]);
+		mr4 = memory_stat << (31 - data->bit_array[0] - data->bit_array[1])
+				  >> (31 - data->bit_array[1]);
+		pr_err("DREX(%d): MEMORY_STATUS_SFR(%u) MR4(%u)\n", i, memory_stat, mr4);
+	}
+
+	return IRQ_HANDLED;
+}
+#else
+static irqreturn_t exynos_mc_irq_handler(int irq, void *p)
+{
+	panic("[SW Trip]Memory temperature is too high");
+
+	return IRQ_HANDLED;
+}
+#endif
+
+#if defined(CONFIG_OF)
+static int exynos_mcinfo_parse_dt(struct device_node *np, struct mcinfo_data *data)
+{
+	int i, ret = 0;
+	unsigned int irqnum = 0;
+
+	if (!np)
+		return -ENODEV;
+
+	ret = of_property_read_u32(np, "basecnt", &data->basecnt);
+	if (ret) {
+		dev_err(data->dev, "Failed to get basecnt value!\n");
+		return ret;
+	}
+
+	ret = of_property_read_u32(np, "irqcnt", &data->irqcnt);
+	if (ret) {
+		dev_err(data->dev, "Failed to get irqcnt value!\n");
+		return ret;
+	}
+
+	ret = of_property_read_u32_array(np, "bit_field", (u32 *)&data->bit_array,
+				(size_t)(ARRAY_SIZE(data->bit_array)));
+	if (ret) {
+		dev_err(data->dev, "Failed to get bit field information!\n");
+		return ret;
+	}
+
+	/* Register IRQ for SW trip */
+	for (i = 0; i < data->irqcnt; i++) {
+		irqnum = irq_of_parse_and_map(data->dev->of_node, i);
+		if (!irqnum) {
+			dev_err(data->dev, "Failed to get IRQ map\n");
+			return -EINVAL;
+		}
+		ret = devm_request_irq(data->dev, irqnum,
+			exynos_mc_irq_handler,
+			IRQF_SHARED, dev_name(data->dev), data);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+#else
+static int exynos_mcinfo_parse_dt(struct device_node *np, struct mcinfo_data *data)
+{
+	return -EINVAL;
+}
+#endif /* OF */
+
+static int __devinit exynos_mcinfo_probe(struct platform_device *pdev)
+{
+	struct mcinfo_data *data;
+	struct resource *res;
+	int i, ret = 0;
+
+	data = devm_kzalloc(&pdev->dev, sizeof(struct mcinfo_data), GFP_KERNEL);
+	if (!data) {
+		dev_err(&pdev->dev, "Not enough memory\n");
+		return -ENOMEM;
+	}
+
+	data->dev = &pdev->dev;
+	dev_set_drvdata(data->dev, data);
+
+	ret = exynos_mcinfo_parse_dt(data->dev->of_node, data);
+	if (ret) {
+		dev_err(data->dev, "Failed to parse device tree\n");
+		return ret;
+	}
+
+	/* Allocate memory for Memory controller base address */
+	if (data->basecnt) {
+		data->base = kzalloc((sizeof(void __iomem *)) * data->basecnt,
+					GFP_KERNEL);
+		if (data->base == NULL) {
+			dev_err(data->dev, "Failed to allocate memory\n");
+			return -ENOMEM;
+		}
+		for (i = 0; i < data->basecnt; i++) {
+			res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+			data->base[i] = devm_ioremap_resource(&pdev->dev, res);
+			if (IS_ERR(data->base[i]))
+				return PTR_ERR(data->base[i]);
+		}
+	}
+
+#if defined(CONFIG_MCINFO_SYSFS)
+	ret = sysfs_create_group(&data->dev->kobj,
+					&exynos_mcinfo_attr_group);
+	if (ret)
+		dev_warn(data->dev, "Failed to create sysfs for MR4\n");
+#endif /* MCINFO_SYSFS */
+
+	dev_info(data->dev, "probe finished!\n");
+	return 0;
+}
+
+static int __devexit exynos_mcinfo_remove(struct platform_device *pdev)
+{
+	struct mcinfo_data *data = platform_get_drvdata(pdev);
+	int i;
+
+#if defined(CONFIG_MCINFO_SYSFS)
+	sysfs_remove_group(&data->dev->kobj,
+				&exynos_mcinfo_attr_group);
+#endif /* MCINFO_SYSFS */
+
+	platform_set_drvdata(pdev, NULL);
+
+	for (i = 0; i < data->basecnt; i++) {
+		devm_iounmap(&pdev->dev, data->base[i]);
+	}
+
+	kfree(data->base);
+	kfree(data);
+
+	return 0;
+}
+
+static const struct of_device_id exynos_mcinfo_match[] = {
+	{ .compatible	= "samsung,exynos-mcinfo", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, exynos_mcinfo_match);
+
+static struct platform_driver exynos_mcinfo_driver = {
+	.probe		= exynos_mcinfo_probe,
+	.remove		= exynos_mcinfo_remove,
+	.driver	= {
+		.name	= "exynos-mcinfo",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(exynos_mcinfo_match),
+	},
+};
+module_platform_driver(exynos_mcinfo_driver);
+
+MODULE_AUTHOR("Eunok Jo <eunok25.jo@samsung.com");
+MODULE_DESCRIPTION("Samsung EXYNOS Memory controller specific information");
+MODULE_LICENSE("GPU v2");

drivers/soc/samsung/exynos-pd-dbg.c

@@ -0,0 +1,309 @@
+/*
+ * Exynos PM domain debugfs support.
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/sched.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+
+#include <soc/samsung/exynos-pd.h>
+
+#ifdef CONFIG_DEBUG_FS
+static struct dentry *exynos_pd_dbg_root;
+
+static int exynos_pd_dbg_long_test(struct device *dev)
+{
+	int ret, i;
+
+	pr_info("%s %s: test start.\n", EXYNOS_PD_DBG_PREFIX, __func__);
+
+	if (pm_runtime_enabled(dev) && pm_runtime_active(dev)) {
+		ret = pm_runtime_put_sync(dev);
+		if (ret) {
+			pr_err("%s %s: put sync failed.\n",
+					EXYNOS_PD_DBG_PREFIX, __func__);
+			return ret;
+		}
+	}
+
+	for (i = 0; i < 100; i++) {
+		ret = pm_runtime_get_sync(dev);
+		if (ret) {
+			pr_err("%s %s: get sync failed.\n",
+					EXYNOS_PD_DBG_PREFIX, __func__);
+			return ret;
+		}
+		mdelay(50);
+		ret = pm_runtime_put_sync(dev);
+		if (ret) {
+			pr_err("%s %s: put sync failed.\n",
+					EXYNOS_PD_DBG_PREFIX, __func__);
+			return ret;
+		}
+		mdelay(50);
+	}
+
+	pr_info("%s %s: test done.\n", EXYNOS_PD_DBG_PREFIX, __func__);
+
+	return ret;
+}
+
+static struct generic_pm_domain *exynos_pd_dbg_dev_to_genpd(struct device *dev)
+{
+	if (IS_ERR_OR_NULL(dev->pm_domain))
+		return ERR_PTR(-EINVAL);
+
+	return pd_to_genpd(dev->pm_domain);
+}
+
+static void exynos_pd_dbg_summary_show(struct generic_pm_domain *genpd)
+{
+	static const char * const gpd_status_lookup[] = {
+		[GPD_STATE_ACTIVE] = "on",
+		[GPD_STATE_WAIT_MASTER] = "wait-master",
+		[GPD_STATE_BUSY] = "busy",
+		[GPD_STATE_REPEAT] = "off-in-progress",
+		[GPD_STATE_POWER_OFF] = "off"
+	};
+	static const char * const rpm_status_lookup[] = {
+		[RPM_ACTIVE] = "active",
+		[RPM_RESUMING] = "resuming",
+		[RPM_SUSPENDED] = "suspended",
+		[RPM_SUSPENDING] = "suspending"
+	};
+	const char *p = "";
+	struct pm_domain_data *pm_data;
+	struct gpd_link *link;
+
+	mutex_lock(&genpd->lock);
+
+	if (WARN_ON(genpd->status >= ARRAY_SIZE(gpd_status_lookup))) {
+		pr_err("%s invalid GPD_STATUS\n", EXYNOS_PD_DBG_PREFIX);
+		return ;
+	}
+
+	pr_info("[GENPD] : %-30s [GPD_STATUS] : %-15s\n",
+			genpd->name, gpd_status_lookup[genpd->status]);
+
+	list_for_each_entry(pm_data, &genpd->dev_list, list_node) {
+		if (pm_data->dev->power.runtime_error)
+			p = "error";
+		else if (pm_data->dev->power.disable_depth)
+			p = "unsupported";
+		else if (pm_data->dev->power.runtime_status < ARRAY_SIZE(rpm_status_lookup))
+			p = rpm_status_lookup[pm_data->dev->power.runtime_status];
+		else
+			WARN_ON(1);
+
+		pr_info("\t[DEV] : %-30s [RPM_STATUS] : %-15s\n",
+					dev_name(pm_data->dev), p);
+	}
+
+	list_for_each_entry(link, &genpd->master_links, master_node)
+		exynos_pd_dbg_summary_show(link->slave);
+
+	mutex_unlock(&genpd->lock);
+}
+
+static ssize_t exynos_pd_dbg_read(struct file *file, char __user *user_buf,
+				size_t count, loff_t *ppos)
+{
+	const struct file_operations *ops = file->f_op;
+	struct exynos_pd_dbg_info *info = container_of(ops, struct exynos_pd_dbg_info, fops);
+	struct device *dev = info->dev;
+	struct generic_pm_domain *genpd = exynos_pd_dbg_dev_to_genpd(dev);
+
+	exynos_pd_dbg_summary_show(genpd);
+
+	return 0;
+}
+
+static ssize_t exynos_pd_dbg_write(struct file *file, const char __user *user_buf,
+				size_t count, loff_t *ppos)
+{
+	const struct file_operations *ops = file->f_op;
+	struct exynos_pd_dbg_info *info = container_of(ops, struct exynos_pd_dbg_info, fops);
+	struct device *dev = info->dev;
+	char buf[32];
+	size_t buf_size;
+
+	buf_size = min(count, (sizeof(buf)-1));
+	if (copy_from_user(buf, user_buf, buf_size))
+		return -EFAULT;
+
+	switch (buf[0]) {
+	case '0':
+		if (pm_runtime_put_sync(dev))
+			pr_err("%s %s: put sync failed.\n",
+					EXYNOS_PD_DBG_PREFIX, __func__);
+		break;
+	case '1':
+		if (pm_runtime_get_sync(dev))
+			pr_err("%s %s: get sync failed.\n",
+					EXYNOS_PD_DBG_PREFIX, __func__);
+		break;
+	case 'c':
+		exynos_pd_dbg_long_test(dev);
+		break;
+	default:
+		pr_err("%s %s: Invalid input ['0'|'1'|'c']\n",
+				EXYNOS_PD_DBG_PREFIX, __func__);
+		break;
+	}
+
+	return count;
+}
+
+static const struct file_operations exynos_pd_dbg_fops = {
+	.open = simple_open,
+	.read = exynos_pd_dbg_read,
+	.write = exynos_pd_dbg_write,
+	.llseek = default_llseek,
+};
+#endif
+
+static int exynos_pd_dbg_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct exynos_pd_dbg_info *dbg_info;
+
+	dbg_info = kzalloc(sizeof(struct exynos_pd_dbg_info), GFP_KERNEL);
+	if (!dbg_info) {
+		pr_err("%s %s: could not allocate mem for dbg_info\n",
+				EXYNOS_PD_DBG_PREFIX, __func__);
+		ret = -ENOMEM;
+		goto err_dbg_info;
+	}
+	dbg_info->dev = &pdev->dev;
+#ifdef CONFIG_DEBUG_FS
+	if (!exynos_pd_dbg_root) {
+		exynos_pd_dbg_root = debugfs_create_dir("exynos-pd", NULL);
+		if (!exynos_pd_dbg_root) {
+			pr_err("%s %s: could not create debugfs dir\n",
+					EXYNOS_PD_DBG_PREFIX, __func__);
+			ret = -ENOMEM;
+			goto err_dbgfs_root;
+		}
+	}
+
+	dbg_info->fops = exynos_pd_dbg_fops;
+	dbg_info->d = debugfs_create_file(dev_name(&pdev->dev), 0644,
+			exynos_pd_dbg_root, NULL, &dbg_info->fops);
+	if (!dbg_info->d) {
+		pr_err("%s %s: could not creatd debugfs file\n",
+				EXYNOS_PD_DBG_PREFIX, __func__);
+		ret = -ENOMEM;
+		goto err_dbgfs_pd;
+	}
+#endif
+	platform_set_drvdata(pdev, dbg_info);
+
+	pm_runtime_enable(&pdev->dev);
+
+	ret = pm_runtime_get_sync(&pdev->dev);
+	if (ret) {
+		pr_err("%s %s: get_sync of %s failed.\n",
+			EXYNOS_PD_DBG_PREFIX, __func__, dev_name(&pdev->dev));
+		goto err_get_sync;
+	}
+
+	ret = pm_runtime_put_sync(&pdev->dev);
+	if (ret) {
+		pr_err("%s %s: put sync of %s failed.\n",
+			EXYNOS_PD_DBG_PREFIX, __func__, dev_name(&pdev->dev));
+		goto err_put_sync;
+	}
+
+	return 0;
+
+err_get_sync:
+err_put_sync:
+#ifdef CONFIG_DEBUG_FS
+	debugfs_remove_recursive(dbg_info->d);
+err_dbgfs_pd:
+	debugfs_remove_recursive(exynos_pd_dbg_root);
+err_dbgfs_root:
+#endif
+	kfree(dbg_info);
+err_dbg_info:
+	return ret;
+}
+
+static int exynos_pd_dbg_remove(struct platform_device *pdev)
+{
+	struct exynos_pd_dbg_info *dbg_info = platform_get_drvdata(pdev);
+	struct device *dev = dbg_info->dev;
+
+	if (pm_runtime_enabled(dev) && pm_runtime_active(dev))
+		pm_runtime_put_sync(dev);
+
+	pm_runtime_disable(dev);
+
+#ifdef CONFIG_DEBUG_FS
+	debugfs_remove_recursive(dbg_info->d);
+	debugfs_remove_recursive(exynos_pd_dbg_root);
+#endif
+	kfree(dbg_info);
+
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static int exynos_pd_dbg_runtime_suspend(struct device *dev)
+{
+	pr_info("%s %s's Runtime_Suspend\n",
+			EXYNOS_PD_DBG_PREFIX, dev_name(dev));
+	return 0;
+}
+
+static int exynos_pd_dbg_runtime_resume(struct device *dev)
+{
+	pr_info("%s %s's Runtime_Resume\n",
+			EXYNOS_PD_DBG_PREFIX, dev_name(dev));
+	return 0;
+}
+
+static struct dev_pm_ops exynos_pd_dbg_pm_ops = {
+	SET_RUNTIME_PM_OPS(exynos_pd_dbg_runtime_suspend,
+			exynos_pd_dbg_runtime_resume,
+			NULL)
+};
+
+#ifdef CONFIG_OF
+static const struct of_device_id exynos_pd_dbg_match[] = {
+	{
+		.compatible = "samsung,exynos-pd-dbg",
+	},
+	{},
+};
+#endif
+
+static struct platform_driver exynos_pd_dbg_drv = {
+	.probe		= exynos_pd_dbg_probe,
+	.remove		= exynos_pd_dbg_remove,
+	.driver		= {
+		.name	= "exynos_pd_dbg",
+		.owner	= THIS_MODULE,
+		.pm	= &exynos_pd_dbg_pm_ops,
+#ifdef CONFIG_OF
+		.of_match_table = exynos_pd_dbg_match,
+#endif
+	},
+};
+
+static int __init exynos_pd_dbg_init(void)
+{
+	return platform_driver_register(&exynos_pd_dbg_drv);
+}
+late_initcall(exynos_pd_dbg_init);

drivers/soc/samsung/exynos-pd.c

@@ -0,0 +1,473 @@
+/*
+ * Exynos PM domain support for PMUCAL 3.0 interface.
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Implementation of Exynos specific power domain control which is used in
+ * conjunction with runtime-pm.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <soc/samsung/exynos-pd.h>
+#include <sound/exynos-audmixer.h>
+
+struct exynos_pm_domain *exynos_pd_lookup_name(const char *domain_name)
+{
+	struct exynos_pm_domain *exypd = NULL;
+	struct device_node *np;
+
+	if (IS_ERR_OR_NULL(domain_name))
+		return NULL;
+
+	for_each_compatible_node(np, NULL, "samsung,exynos-pd") {
+		struct platform_device *pdev;
+		struct exynos_pm_domain *pd;
+
+		if (of_device_is_available(np)) {
+			pdev = of_find_device_by_node(np);
+			if (!pdev)
+				continue;
+			pd = platform_get_drvdata(pdev);
+			if (!strcmp(pd->name, domain_name)) {
+				exypd = pd;
+				break;
+			}
+		}
+	}
+	return exypd;
+}
+EXPORT_SYMBOL(exynos_pd_lookup_name);
+
+static int exynos_pd_status(struct exynos_pm_domain *pd)
+{
+	int status;
+
+	if (unlikely(!pd))
+		return -EINVAL;
+
+	mutex_lock(&pd->access_lock);
+	status = cal_pd_status(pd->cal_pdid);
+	mutex_unlock(&pd->access_lock);
+
+	return status;
+}
+
+/* Power domain on sequence.
+ * on_pre, on_post functions are registered as notification handler at CAL code.
+ */
+static void exynos_pd_power_on_pre(struct exynos_pm_domain *pd)
+{
+	exynos_update_ip_idle_status(pd->idle_ip_index, 0);
+
+	if (pd->devfreq_index >= 0)
+		exynos_devfreq_sync_voltage(pd->devfreq_index, true);
+}
+
+static void exynos_pd_power_on_post(struct exynos_pm_domain *pd)
+{
+#if defined(CONFIG_EXYNOS_BCM)
+	if (cal_pd_status(pd->cal_pdid) && pd->bcm)
+			bcm_pd_sync(pd->bcm, true);
+#endif
+}
+
+static void exynos_pd_power_off_pre(struct exynos_pm_domain *pd)
+{
+#if 0
+	/* HACK_APM */
+	if (!strcmp(pd->name, "pd-g3d"))
+		exynos_g3d_power_down_noti_apm();
+#endif
+#if defined(CONFIG_EXYNOS_BCM)
+	if(cal_pd_status(pd->cal_pdid) && pd->bcm)
+			bcm_pd_sync(pd->bcm, false);
+#endif
+}
+
+static void exynos_pd_power_off_post(struct exynos_pm_domain *pd)
+{
+	exynos_update_ip_idle_status(pd->idle_ip_index, 1);
+
+	if (pd->devfreq_index >= 0)
+		exynos_devfreq_sync_voltage(pd->devfreq_index, false);
+}
+
+static void exynos_pd_prepare_forced_off(struct exynos_pm_domain *pd)
+{
+}
+
+static int exynos_pd_power_on(struct generic_pm_domain *genpd)
+{
+	struct exynos_pm_domain *pd = container_of(genpd, struct exynos_pm_domain, genpd);
+	int ret;
+
+	DEBUG_PRINT_INFO("%s(%s)+\n", __func__, pd->name);
+	if (unlikely(!pd->pd_control)) {
+		pr_debug(EXYNOS_PD_PREFIX "%s is Logical sub power domain, dose not have to power on control\n", pd->name);
+		return 0;
+	}
+
+	if (pd->check_cp_status && (is_cp_aud_enabled() || is_test_cp_call_set())) {
+		pr_info(EXYNOS_PD_PREFIX "%s power-on is skipped due to CP call.\n", pd->name);
+		return 0;
+	}
+
+	mutex_lock(&pd->access_lock);
+
+	exynos_pd_power_on_pre(pd);
+
+	ret = pd->pd_control(pd->cal_pdid, 1);
+	if (ret) {
+		pr_err(EXYNOS_PD_PREFIX "%s cannot be powered on\n", pd->name);
+		exynos_pd_power_off_post(pd);
+
+		mutex_unlock(&pd->access_lock);
+		return -EAGAIN;
+	}
+
+	exynos_pd_power_on_post(pd);
+
+	/* enable bts features if exists */
+	if (pd->bts)
+		bts_initialize(pd->name, true);
+
+	mutex_unlock(&pd->access_lock);
+
+	DEBUG_PRINT_INFO("%s(%s)-\n", __func__, pd->name);
+	return 0;
+}
+
+static int exynos_pd_power_off(struct generic_pm_domain *genpd)
+{
+	struct exynos_pm_domain *pd = container_of(genpd, struct exynos_pm_domain, genpd);
+	int ret;
+
+	DEBUG_PRINT_INFO("%s(%s)+\n", __func__, pd->name);
+
+	if (unlikely(!pd->pd_control)) {
+		pr_debug(EXYNOS_PD_PREFIX "%s is Logical sub power domain, dose not have to power off control\n", genpd->name);
+		return 0;
+	}
+
+	if (pd->check_cp_status && (is_cp_aud_enabled() || is_test_cp_call_set())) {
+		pr_info(EXYNOS_PD_PREFIX "%s power-off is skipped due to CP call.\n", pd->name);
+		return 0;
+	}
+
+	mutex_lock(&pd->access_lock);
+
+	/* disable bts features if exists */
+	if (pd->bts)
+		bts_initialize(pd->name, false);
+
+	exynos_pd_power_off_pre(pd);
+
+	ret = pd->pd_control(pd->cal_pdid, 0);
+	if (unlikely(ret)) {
+		if (ret == -4) {
+			pr_err(EXYNOS_PD_PREFIX "Timed out during %s  power off! -> forced power off\n", genpd->name);
+			exynos_pd_prepare_forced_off(pd);
+			ret = pd->pd_control(pd->cal_pdid, 0);
+			if (unlikely(ret)) {
+				pr_err(EXYNOS_PD_PREFIX "%s occur error at power off!\n", genpd->name);
+				goto acc_unlock;
+			}
+		} else {
+			pr_err(EXYNOS_PD_PREFIX "%s occur error at power off!\n", genpd->name);
+			goto acc_unlock;
+		}
+	}
+
+	exynos_pd_power_off_post(pd);
+
+acc_unlock:
+	mutex_unlock(&pd->access_lock);
+	DEBUG_PRINT_INFO("%s(%s)-\n", __func__, pd->name);
+	return ret;
+}
+
+#ifdef CONFIG_OF
+
+/**
+ *  of_device_bts_is_available - check if bts feature is enabled or not
+ *
+ *  @device: Node to check for availability, with locks already held
+ *
+ *  Returns 1 if the status property is "enabled" or "ok",
+ *  0 otherwise
+ */
+static int of_device_bts_is_available(const struct device_node *device)
+{
+	const char *status;
+	int statlen;
+
+	status = of_get_property(device, "bts-status", &statlen);
+	if (status == NULL)
+		return 0;
+
+	if (statlen > 0) {
+		if (!strcmp(status, "enabled") || !strcmp(status, "ok"))
+			return 1;
+	}
+
+	return 0;
+}
+
+static bool of_get_check_cp_status(const struct device_node *device)
+{
+	const char *check_cp_status;
+	int len;
+
+	check_cp_status = of_get_property(device, "check-cp-status", &len);
+	if (check_cp_status == NULL)
+		return false;
+
+	if (len > 0) {
+		if (!strcmp(check_cp_status, "true"))
+			return true;
+	}
+
+	return false;
+}
+
+/**
+ *  of_get_devfreq_sync_volt_idx - check devfreq sync voltage idx
+ *
+ *  Returns the index if the "devfreq-sync-voltage" is described in DT pd node,
+ *  -ENOENT otherwise.
+ */
+static int of_get_devfreq_sync_volt_idx(const struct device_node *device)
+{
+	int ret;
+	u32 val;
+
+	ret = of_property_read_u32(device, "devfreq-sync-voltage", &val);
+	if (ret)
+		return -ENOENT;
+
+	return val;
+}
+
+static void exynos_pd_genpd_init(struct exynos_pm_domain *pd, int state)
+{
+	pd->genpd.name = pd->name;
+	pd->genpd.power_off = exynos_pd_power_off;
+	pd->genpd.power_on = exynos_pd_power_on;
+
+	/* pd power on/off latency is less than 1ms */
+	pd->genpd.power_on_latency_ns = 1000000;
+	pd->genpd.power_off_latency_ns = 1000000;
+
+	do {
+		int ret;
+
+		/* bts feature is enabled if exists */
+		ret = of_device_bts_is_available(pd->of_node);
+		if (ret) {
+			pd->bts = 1;
+			bts_initialize(pd->name, true);
+			DEBUG_PRINT_INFO("%s - bts feature is enabled\n", pd->name);
+		}
+	} while (0);
+
+	pm_genpd_init(&pd->genpd, NULL, state ? false : true);
+}
+
+/* exynos_pd_show_power_domain - show current power domain status.
+ *
+ * read the status of power domain and show it.
+ */
+static void exynos_pd_show_power_domain(void)
+{
+	struct device_node *np;
+	for_each_compatible_node(np, NULL, "samsung,exynos-pd") {
+		struct platform_device *pdev;
+		struct exynos_pm_domain *pd;
+
+		if (of_device_is_available(np)) {
+			pdev = of_find_device_by_node(np);
+			if (!pdev)
+				continue;
+			pd = platform_get_drvdata(pdev);
+			pr_info("   %-9s - %-3s\n", pd->genpd.name,
+					cal_pd_status(pd->cal_pdid) ? "on" : "off");
+		} else
+			pr_info("   %-9s - %s\n", np->name, "on,  always");
+	}
+
+	return;
+}
+
+static __init int exynos_pd_dt_parse(void)
+{
+	struct platform_device *pdev = NULL;
+	struct device_node *np = NULL;
+	int ret = 0;
+
+	for_each_compatible_node(np, NULL, "samsung,exynos-pd") {
+		struct exynos_pm_domain *pd;
+		struct device_node *children;
+		int initial_state;
+
+		/* skip unmanaged power domain */
+		if (!of_device_is_available(np))
+			continue;
+
+		pdev = of_find_device_by_node(np);
+
+		pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+		if (!pd) {
+			pr_err(EXYNOS_PD_PREFIX "%s: failed to allocate memory for domain\n",
+					__func__);
+			return -ENOMEM;
+		}
+
+		/* init exynos_pm_domain's members  */
+		pd->name = kstrdup(np->name, GFP_KERNEL);
+		ret = of_property_read_u32(np, "cal_id", (u32 *)&pd->cal_pdid);
+		if (ret) {
+			pr_err(EXYNOS_PD_PREFIX "%s: failed to get cal_pdid  from of %s\n",
+					__func__, pd->name);
+			return -ENODEV;
+		}
+		pd->of_node = np;
+		pd->pd_control = cal_pd_control;
+		pd->check_status = exynos_pd_status;
+		pd->devfreq_index = of_get_devfreq_sync_volt_idx(pd->of_node);
+		pd->check_cp_status = of_get_check_cp_status(pd->of_node);
+		initial_state = cal_pd_status(pd->cal_pdid);
+		if (initial_state == -1) {
+			pr_err(EXYNOS_PD_PREFIX "%s: %s is in unknown state\n",
+					__func__, pd->name);
+			return -EINVAL;
+		}
+
+		pd->idle_ip_index = exynos_get_idle_ip_index(pd->name);
+
+		mutex_init(&pd->access_lock);
+		platform_set_drvdata(pdev, pd);
+
+		__of_genpd_add_provider(np, __of_genpd_xlate_simple, &pd->genpd);
+
+		exynos_pd_genpd_init(pd, initial_state);
+
+		/* add LOGICAL sub-domain
+		 * It is not assumed that there is REAL sub-domain.
+		 * Power on/off functions are not defined here.
+		 */
+		for_each_child_of_node(np, children) {
+			struct exynos_pm_domain *sub_pd;
+			struct platform_device *sub_pdev;
+
+			sub_pd = kzalloc(sizeof(*sub_pd), GFP_KERNEL);
+			if (!sub_pd) {
+				pr_err("%s %s: failed to allocate memory for power domain\n",
+						EXYNOS_PD_PREFIX, __func__);
+				return -ENOMEM;
+			}
+
+			sub_pd->name = kstrdup(children->name, GFP_KERNEL);
+			sub_pd->of_node = children;
+
+			/* Logical sub-domain does not have to power on/off control*/
+			sub_pd->pd_control = NULL;
+
+			sub_pd->devfreq_index = of_get_devfreq_sync_volt_idx(sub_pd->of_node);
+
+			/* kernel does not create sub-domain pdev. */
+			sub_pdev = of_find_device_by_node(children);
+			if (!sub_pdev)
+				sub_pdev = of_platform_device_create(children, NULL, &pdev->dev);
+			if (!sub_pdev) {
+				pr_err(EXYNOS_PD_PREFIX "sub domain allocation failed: %s\n",
+							kstrdup(children->name, GFP_KERNEL));
+				continue;
+			}
+
+			mutex_init(&sub_pd->access_lock);
+			platform_set_drvdata(sub_pdev, sub_pd);
+
+			__of_genpd_add_provider(children, __of_genpd_xlate_simple, &sub_pd->genpd);
+			exynos_pd_genpd_init(sub_pd, initial_state);
+
+			if (pm_genpd_add_subdomain(&pd->genpd, &sub_pd->genpd))
+				pr_err("%s %s can't add subdomain %s\n",
+					EXYNOS_PD_PREFIX, pd->genpd.name, sub_pd->genpd.name);
+			else
+				pr_info(EXYNOS_PD_PREFIX "%s has a new logical child %s.\n",
+						pd->genpd.name, sub_pd->genpd.name);
+		}
+	}
+
+	/* EXCEPTION: add physical sub-pd to master pd using device tree */
+	for_each_compatible_node(np, NULL, "samsung,exynos-pd") {
+		struct exynos_pm_domain *parent_pd, *child_pd;
+		struct device_node *parent;
+		struct platform_device *parent_pd_pdev, *child_pd_pdev;
+		int i;
+
+		/* skip unmanaged power domain */
+		if (!of_device_is_available(np))
+			continue;
+
+		/* child_pd_pdev should have value. */
+		child_pd_pdev = of_find_device_by_node(np);
+		child_pd = platform_get_drvdata(child_pd_pdev);
+
+		/* search parents in device tree */
+		for (i = 0; i < MAX_PARENT_POWER_DOMAIN; i++) {
+			/* find parent node if available */
+			parent = of_parse_phandle(np, "parent", i);
+			if (!parent)
+				break;
+
+			/* display error when parent is unmanaged. */
+			if (!of_device_is_available(parent)) {
+				pr_err(EXYNOS_PD_PREFIX "%s is not managed by runtime pm.\n",
+						kstrdup(parent->name, GFP_KERNEL));
+				continue;
+			}
+
+			/* parent_pd_pdev should have value. */
+			parent_pd_pdev = of_find_device_by_node(parent);
+			parent_pd = platform_get_drvdata(parent_pd_pdev);
+
+			if (pm_genpd_add_subdomain(&parent_pd->genpd, &child_pd->genpd))
+				pr_err(EXYNOS_PD_PREFIX "%s cannot add subdomain %s\n",
+						parent_pd->name, child_pd->name);
+			else
+				pr_info(EXYNOS_PD_PREFIX "%s has a new child %s.\n",
+						parent_pd->name, child_pd->name);
+		}
+	}
+
+	return 0;
+}
+#endif /* CONFIG_OF */
+
+static int __init exynos_pd_init(void)
+{
+	int ret;
+#ifdef CONFIG_OF
+	if (of_have_populated_dt()) {
+		ret = exynos_pd_dt_parse();
+		if (ret) {
+			pr_err(EXYNOS_PD_PREFIX "dt parse failed.\n");
+			return ret;
+		}
+
+		pr_info("%s PM Domain Initialize\n", EXYNOS_PD_PREFIX);
+		/* show information of power domain registration */
+		exynos_pd_show_power_domain();
+
+		return 0;
+	}
+#endif
+	pr_err(EXYNOS_PD_PREFIX "PM Domain works along with Device Tree\n");
+	return -EPERM;
+}
+subsys_initcall(exynos_pd_init);

drivers/soc/samsung/exynos-pm.c

@@ -0,0 +1,633 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/notifier.h>
+#include <linux/spinlock.h>
+#include <linux/suspend.h>
+#include <linux/wakeup_reason.h>
+#include <linux/gpio.h>
+#include <linux/syscore_ops.h>
+#ifdef CONFIG_SEC_DEBUG
+#include <linux/sec_debug.h>
+#endif
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <asm/psci.h>
+#include <asm/suspend.h>
+#include <asm/smp_plat.h>
+
+#include <soc/samsung/exynos-pm.h>
+#include <soc/samsung/exynos-pmu.h>
+#include <soc/samsung/exynos-powermode.h>
+
+#include <sound/exynos-audmixer.h>
+
+#define WAKEUP_STAT_EINT                (1 << 0)
+#define WAKEUP_STAT_RTC_ALARM           (1 << 1)
+#define WAKEUP_STAT_RTC_TICK		(1 << 2)
+#define WAKEUP_STAT_TRTC_ALARM		(1 << 3)
+#define WAKEUP_STAT_TRTC_TICK		(1 << 4)
+#define WAKEUP_STAT_MMC0		(1 << 9)
+#define WAKEUP_STAT_MMC1		(1 << 10)
+#define WAKEUP_STAT_MMC2		(1 << 11)
+#define WAKEUP_STAT_I2S			(1 << 13)
+#define WAKEUP_STAT_TIMER		(1 << 14)
+#define WAKEUP_STAT_WIFI_ACTIVE		(1 << 19)
+#define WAKEUP_STAT_CP_RESET_REQ	(1 << 20)
+#define WAKEUP_STAT_GNSS_WAKEUP_REQ	(1 << 21)
+#define WAKEUP_STAT_GNSS_RESET_REQ	(1 << 22)
+#define WAKEUP_STAT_GNSS_ACTIVE		(1 << 23)
+#define WAKEUP_STAT_INT_MBOX_CP		(1 << 24)
+#define WAKEUP_STAT_CP_ACTIVE		(1 << 25)
+#define WAKEUP_STAT_INT_MBOX_GNSS	(1 << 26)
+#define WAKEUP_STAT_INT_MBOX_WIFI	(1 << 27)
+#define WAKEUP_STAT_CORTEXM0_APM	(1 << 28)
+#define WAKEUP_STAT_WIFI_RESET_REQ	(1 << 29)
+
+/*
+ * PMU register offset
+ */
+#define EXYNOS_PMU_WAKEUP_STAT		0x0600
+#define EXYNOS_PMU_EINT_WAKEUP_MASK	0x060C
+#define BOOT_CPU			0
+#define NR_CPUS_PER_CLUSTER		4
+
+extern u32 exynos_eint_to_pin_num(int eint);
+#define EXYNOS_EINT_PEND(b, x)      ((b) + 0xA00 + (((x) >> 3) * 4))
+
+struct exynos_pm_info {
+	void __iomem *eint_base;		/* GPIO_ALIVE base to check wkup reason */
+	void __iomem *gic_base;			/* GICD_ISPENDRn base to check wkup reason */
+	unsigned int num_eint;			/* Total number of EINT sources */
+	unsigned int num_gic;			/* Total number of GIC sources */
+	bool is_early_wakeup;
+	bool is_cp_call;
+	unsigned int suspend_mode_idx;		/* power mode to be used in suspend scenario */
+	unsigned int suspend_psci_idx;		/* psci index to be used in suspend scenario */
+	unsigned int cp_call_mode_idx;		/* power mode to be used in cp_call scenario */
+	unsigned int cp_call_psci_idx;		/* psci index to be used in cp_call scenario */
+};
+static struct exynos_pm_info *pm_info;
+
+struct exynos_pm_dbg {
+	u32 test_early_wakeup;
+	u32 test_cp_call;
+};
+static struct exynos_pm_dbg *pm_dbg;
+
+static void exynos_show_wakeup_reason_eint(void)
+{
+	int bit;
+	int i, size;
+	long unsigned int ext_int_pend;
+	u64 eint_wakeup_mask;
+	bool found = 0;
+	unsigned int val;
+
+	pr_info("EINT_PEND: ");
+	for (i = 0, size = 8; i < pm_info->num_eint; i += size)
+		pr_info("0x%02x ", __raw_readl(EXYNOS_EINT_PEND(pm_info->eint_base, i)));
+
+	pr_info("\n");
+
+	exynos_pmu_read(EXYNOS_PMU_EINT_WAKEUP_MASK, &val);
+	eint_wakeup_mask = val;
+
+	for (i = 0, size = 8; i < pm_info->num_eint; i += size) {
+		ext_int_pend =
+			__raw_readl(EXYNOS_EINT_PEND(pm_info->eint_base, i));
+
+		for_each_set_bit(bit, &ext_int_pend, size) {
+			u32 gpio;
+			int irq;
+
+			if (eint_wakeup_mask & (1 << (i + bit)))
+				continue;
+
+			gpio = exynos_eint_to_pin_num(i + bit);
+			irq = gpio_to_irq(gpio);
+
+#ifdef CONFIG_SUSPEND
+			log_wakeup_reason(irq);
+			update_wakeup_reason_stats(irq, i + bit);
+#endif
+			found = 1;
+		}
+	}
+
+	if (!found)
+		pr_info("%s Resume caused by unknown EINT\n", EXYNOS_PM_PREFIX);
+}
+
+static void exynos_show_wakeup_reason(bool sleep_abort)
+{
+	unsigned int wakeup_stat;
+	int i, size;
+
+	if (sleep_abort) {
+		pr_info("%s early wakeup! Dumping pending registers...\n", EXYNOS_PM_PREFIX);
+
+		pr_info("EINT_PEND:\n");
+		for (i = 0, size = 8; i < pm_info->num_eint; i += size)
+			pr_info("0x%x\n", __raw_readl(EXYNOS_EINT_PEND(pm_info->eint_base, i)));
+
+		pr_info("GIC_PEND:\n");
+		for (i = 0; i < pm_info->num_gic; i++)
+			pr_info("GICD_ISPENDR[%d] = 0x%x\n", i, __raw_readl(pm_info->gic_base + i*4));
+
+		pr_info("%s done.\n", EXYNOS_PM_PREFIX);
+		return ;
+	}
+
+	exynos_pmu_read(EXYNOS_PMU_WAKEUP_STAT, &wakeup_stat);
+
+	pr_info("%s WAKEUP_STAT: 0x%08x\n", EXYNOS_PM_PREFIX, wakeup_stat);
+
+	if (wakeup_stat & WAKEUP_STAT_EINT)
+		exynos_show_wakeup_reason_eint();
+	else if (wakeup_stat & WAKEUP_STAT_RTC_ALARM)
+		pr_info("%s Resume caused by RTC alarm\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_RTC_TICK)
+		pr_info("%s Resume caused by RTC tick\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_TRTC_ALARM)
+		pr_info("%s Resume caused by TRTC alarm\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_TRTC_TICK)
+		pr_info("%s Resume caused by TRTC tick\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_MMC0)
+		pr_info("%s Resume caused by MMC0\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_MMC1)
+		pr_info("%s Resume caused by MMC1\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_MMC2)
+		pr_info("%s Resume caused by MMC2\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_I2S)
+		pr_info("%s Resume caused by I2S\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_TIMER)
+		pr_info("%s Resume caused by TIMER\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_WIFI_ACTIVE)
+		pr_info("%s Resume caused by WIFI_ACTIVE\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_CP_RESET_REQ)
+		pr_info("%s Resume caused by CP_RESET_REQ\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_GNSS_WAKEUP_REQ)
+		pr_info("%s Resume caused by GNSS_WAKEUP_REQ\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_GNSS_RESET_REQ)
+		pr_info("%s Resume caused by GNSS_RESET_REQ\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_GNSS_ACTIVE)
+		pr_info("%s Resume caused by GNSS active\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_INT_MBOX_CP)
+		pr_info("%s Resume caused by INT_MBOX_CP\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_CP_ACTIVE)
+		pr_info("%s Resume caused by CP active\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_INT_MBOX_GNSS)
+		pr_info("%s Resume caused by INT_MBOX_GNSS\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_INT_MBOX_WIFI)
+		pr_info("%s Resume caused by INT_MBOX_WIFI\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_CORTEXM0_APM)
+		pr_info("%s Resume caused by CORTEXM0_APM\n", EXYNOS_PM_PREFIX);
+	else if (wakeup_stat & WAKEUP_STAT_WIFI_RESET_REQ)
+		pr_info("%s Resume caused by WIFI_RESET_REQ\n", EXYNOS_PM_PREFIX);
+	else
+		pr_info("%s Resume caused by wakeup_stat 0x%08x\n",
+			EXYNOS_PM_PREFIX, wakeup_stat);
+}
+
+#ifdef CONFIG_CPU_IDLE
+static DEFINE_RWLOCK(exynos_pm_notifier_lock);
+static RAW_NOTIFIER_HEAD(exynos_pm_notifier_chain);
+
+static int exynos_pm_notify(enum exynos_pm_event event, int nr_to_call, int *nr_calls)
+{
+	int ret;
+
+	ret = __raw_notifier_call_chain(&exynos_pm_notifier_chain, event, NULL,
+		nr_to_call, nr_calls);
+
+	return notifier_to_errno(ret);
+}
+
+int exynos_pm_register_notifier(struct notifier_block *nb)
+{
+	unsigned long flags;
+	int ret;
+
+	write_lock_irqsave(&exynos_pm_notifier_lock, flags);
+	ret = raw_notifier_chain_register(&exynos_pm_notifier_chain, nb);
+	write_unlock_irqrestore(&exynos_pm_notifier_lock, flags);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(exynos_pm_register_notifier);
+
+int exynos_pm_unregister_notifier(struct notifier_block *nb)
+{
+	unsigned long flags;
+	int ret;
+
+	write_lock_irqsave(&exynos_pm_notifier_lock, flags);
+	ret = raw_notifier_chain_unregister(&exynos_pm_notifier_chain, nb);
+	write_unlock_irqrestore(&exynos_pm_notifier_lock, flags);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(exynos_pm_unregister_notifier);
+
+int exynos_pm_lpa_enter(void)
+{
+	int nr_calls;
+	int ret = 0;
+
+	read_lock(&exynos_pm_notifier_lock);
+	ret = exynos_pm_notify(LPA_ENTER, -1, &nr_calls);
+	if (ret)
+		/*
+		 * Inform listeners (nr_calls - 1) about failure of LPA
+		 * entry who are notified earlier to prepare for it.
+		 */
+		exynos_pm_notify(LPA_ENTER_FAIL, nr_calls - 1, NULL);
+	read_unlock(&exynos_pm_notifier_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(exynos_pm_lpa_enter);
+
+int exynos_pm_lpa_exit(void)
+{
+	int ret;
+
+	read_lock(&exynos_pm_notifier_lock);
+	ret = exynos_pm_notify(LPA_EXIT, -1, NULL);
+	read_unlock(&exynos_pm_notifier_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(exynos_pm_lpa_exit);
+
+int exynos_pm_sicd_enter(void)
+{
+	int nr_calls;
+	int ret = 0;
+
+	read_lock(&exynos_pm_notifier_lock);
+	ret = exynos_pm_notify(SICD_ENTER, -1, &nr_calls);
+	read_unlock(&exynos_pm_notifier_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(exynos_pm_sicd_enter);
+
+int exynos_pm_sicd_exit(void)
+{
+	int ret;
+
+	read_lock(&exynos_pm_notifier_lock);
+	ret = exynos_pm_notify(SICD_EXIT, -1, NULL);
+	read_unlock(&exynos_pm_notifier_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(exynos_pm_sicd_exit);
+#endif /* CONFIG_CPU_IDLE */
+
+static int exynos_pm_syscore_suspend(void)
+{
+#ifdef CONFIG_SEC_DEBUG
+	unsigned int val;
+	unsigned int addr;
+	int debug_level;
+#endif
+	if (!exynos_check_cp_status()) {
+		pr_info("%s %s: sleep canceled by CP reset \n",
+					EXYNOS_PM_PREFIX, __func__);
+		return -EINVAL;
+	}
+
+#ifdef CONFIG_SEC_DEBUG
+	debug_level = sec_debug_get_debug_level();
+
+	if (debug_level >= 1) {
+		/* debug level MID or HIGH */
+		addr = 0x0038;
+		exynos_pmu_read(addr, &val);
+		pr_info("CP_STAT (0x%x) = 0x%08x\n", addr, val);
+		addr = 0x0048;
+		exynos_pmu_read(addr, &val);
+		pr_info("GNSS_STAT (0x%x) = 0x%08x\n", addr, val);
+		addr = 0x0148;
+		exynos_pmu_read(addr, &val);
+		pr_info("WIFI_STAT (0x%x) = 0x%08x\n", addr, val);
+	}
+#endif
+
+	pm_info->is_cp_call = is_cp_aud_enabled();
+	if (pm_info->is_cp_call || pm_dbg->test_cp_call) {
+		exynos_prepare_sys_powerdown(pm_info->cp_call_mode_idx, true);
+		pr_info("%s %s: Enter CP Call scenario. (mode_idx = %d)\n",
+				EXYNOS_PM_PREFIX, __func__, pm_info->cp_call_mode_idx);
+	} else {
+		exynos_prepare_sys_powerdown(pm_info->suspend_mode_idx, true);
+		pr_info("%s %s: Enter Suspend scenario. (mode_idx = %d)\n",
+				EXYNOS_PM_PREFIX,__func__, pm_info->suspend_mode_idx);
+	}
+
+	return 0;
+}
+
+static void exynos_pm_syscore_resume(void)
+{
+	pr_info("========== wake up ==========\n");
+	if (pm_info->is_cp_call || pm_dbg->test_cp_call)
+		exynos_wakeup_sys_powerdown(pm_info->cp_call_mode_idx, pm_info->is_early_wakeup);
+	else
+		exynos_wakeup_sys_powerdown(pm_info->suspend_mode_idx, pm_info->is_early_wakeup);
+
+	exynos_show_wakeup_reason(pm_info->is_early_wakeup);
+
+	if (!pm_info->is_early_wakeup)
+		pr_debug("%s %s: post sleep, preparing to return\n",
+						EXYNOS_PM_PREFIX, __func__);
+}
+
+static struct syscore_ops exynos_pm_syscore_ops = {
+	.suspend	= exynos_pm_syscore_suspend,
+	.resume		= exynos_pm_syscore_resume,
+};
+
+#ifdef CONFIG_SEC_GPIO_DVS
+extern void gpio_dvs_check_sleepgpio(void);
+#endif
+
+static int exynos_pm_enter(suspend_state_t state)
+{
+	unsigned int psci_index;
+
+	if (pm_info->is_cp_call || pm_dbg->test_cp_call)
+		psci_index = pm_info->cp_call_psci_idx;
+	else
+		psci_index = pm_info->suspend_psci_idx;
+
+	/* Send an IPI if test_early_wakeup flag is set */
+	if (pm_dbg->test_early_wakeup)
+		arch_send_call_function_single_ipi(0);
+
+#ifdef CONFIG_SEC_GPIO_DVS
+	/************************ Caution !!! ****************************/
+	/* This function must be located in appropriate SLEEP position
+	 * in accordance with the specification of each BB vendor.
+	 */
+	/************************ Caution !!! ****************************/
+	gpio_dvs_check_sleepgpio();
+#endif
+
+	/* This will also act as our return point when
+	 * we resume as it saves its own register state and restores it
+	 * during the resume. */
+	pm_info->is_early_wakeup = (bool)cpu_suspend(psci_index);
+	if (pm_info->is_early_wakeup)
+		pr_info("%s %s: return to originator\n",
+				EXYNOS_PM_PREFIX, __func__);
+
+	return pm_info->is_early_wakeup;
+}
+
+static const struct platform_suspend_ops exynos_pm_ops = {
+	.enter		= exynos_pm_enter,
+	.valid		= suspend_valid_only_mem,
+};
+
+static struct bus_type exynos_info_subsys = {
+	.name = "exynos_info",
+	.dev_name = "exynos_info",
+};
+
+static ssize_t core_status_show(struct kobject *kobj,
+			struct kobj_attribute *attr, char *buf)
+{
+	ssize_t n = 0;
+	int cpu, cluster = 0;
+	unsigned int mpidr;
+
+	for_each_possible_cpu(cpu) {
+		/*
+		 * Each cluster has four cores.
+		 * "cpu % NR_CPUS_PER_CLUSTER == 0" means that
+		 * the cpu is a first one of each cluster.
+		 */
+		if (!(cpu % NR_CPUS_PER_CLUSTER)) {
+			mpidr = cpu_logical_map(cpu);
+			cluster =  MPIDR_AFFINITY_LEVEL(mpidr, 1);
+			n += scnprintf(buf + n, 24, "%s L2 : %d\n",
+				(!cpu) ? "boot" : "nonboot",
+				exynos_cpu.l2_state(cluster));
+
+			n += scnprintf(buf + n, 24, "%s Noncpu : %d\n",
+				(!cpu) ? "boot" : "nonboot",
+				exynos_cpu.noncpu_state(cluster));
+		}
+		n += scnprintf(buf + n, 24, "CPU%d : %d\n",
+				cpu, exynos_cpu.power_state(cpu));
+	}
+
+	return n;
+}
+
+static struct kobj_attribute exynos_info_attr =
+	__ATTR(core_status, 0644, core_status_show, NULL);
+
+static struct attribute *exynos_info_sysfs_attrs[] = {
+	&exynos_info_attr.attr,
+	NULL,
+};
+
+static struct attribute_group exynos_info_sysfs_group = {
+	.attrs = exynos_info_sysfs_attrs,
+};
+
+static const struct attribute_group *exynos_info_sysfs_groups[] = {
+	&exynos_info_sysfs_group,
+	NULL,
+};
+
+bool is_test_cp_call_set(void)
+{
+	if (!pm_dbg)
+		return false;
+
+	return pm_dbg->test_cp_call;
+}
+EXPORT_SYMBOL_GPL(is_test_cp_call_set);
+
+#ifdef CONFIG_DEBUG_FS
+static void __init exynos_pm_debugfs_init(void)
+{
+	struct dentry *root, *d;
+
+	root = debugfs_create_dir("exynos-pm", NULL);
+	if (!root) {
+		pr_err("%s %s: could't create debugfs dir\n", EXYNOS_PM_PREFIX, __func__);
+		return;
+	}
+
+	d = debugfs_create_u32("test_early_wakeup", 0644, root, &pm_dbg->test_early_wakeup);
+	if (!d) {
+		pr_err("%s %s: could't create debugfs test_early_wakeup\n",
+					EXYNOS_PM_PREFIX, __func__);
+		return;
+	}
+
+	d = debugfs_create_u32("test_cp_call", 0644, root, &pm_dbg->test_cp_call);
+	if (!d) {
+		pr_err("%s %s: could't create debugfs test_cp_call\n",
+					EXYNOS_PM_PREFIX, __func__);
+		return;
+	}
+}
+#endif
+
+#if defined(CONFIG_SEC_FACTORY)
+enum ids_info {
+	table_ver,
+	big_asv,
+	g3d_asv,
+	cpu_ids,
+};
+
+extern int asv_ids_information(enum ids_info id);
+
+static ssize_t show_asv_info(struct device *dev,
+					struct device_attribute *attr,
+					char *buf)
+{
+	int count = 0;
+
+	/* Set asv group info to buf */
+	count += sprintf(&buf[count], "%d ", asv_ids_information(table_ver));
+	count += sprintf(&buf[count], "%03x ", asv_ids_information(big_asv));
+	count += sprintf(&buf[count], "%03x ", asv_ids_information(g3d_asv));
+	count += sprintf(&buf[count], "%u ", asv_ids_information(cpu_ids));
+	count += sprintf(&buf[count], "\n");
+
+	return count;
+}
+
+static DEVICE_ATTR(asv_info, 0664, show_asv_info, NULL);
+#endif /* CONFIG_SEC_FACTORY */
+
+static __init int exynos_pm_drvinit(void)
+{
+	int ret;
+
+	pm_info = kzalloc(sizeof(struct exynos_pm_info), GFP_KERNEL);
+	if (pm_info == NULL) {
+		pr_err("%s %s: failed to allocate memory for exynos_pm_info\n",
+					EXYNOS_PM_PREFIX, __func__);
+		BUG();
+	}
+
+	pm_dbg = kzalloc(sizeof(struct exynos_pm_dbg), GFP_KERNEL);
+	if (pm_dbg == NULL) {
+		pr_err("%s %s: failed to allocate memory for exynos_pm_dbg\n",
+					EXYNOS_PM_PREFIX, __func__);
+		BUG();
+	}
+
+	if (of_have_populated_dt()) {
+		struct device_node *np;
+		np = of_find_compatible_node(NULL, NULL, "samsung,exynos-pm");
+		if (!np) {
+			pr_err("%s %s: unabled to find compatible node (%s)\n",
+					EXYNOS_PM_PREFIX, __func__, "samsung,exynos-pm");
+			BUG();
+		}
+
+		pm_info->eint_base = of_iomap(np, 0);
+		if (!pm_info->eint_base) {
+			pr_err("%s %s: unabled to ioremap EINT base address\n",
+					EXYNOS_PM_PREFIX, __func__);
+			BUG();
+		}
+
+		pm_info->gic_base = of_iomap(np, 1);
+		if (!pm_info->gic_base) {
+			pr_err("%s %s: unbaled to ioremap GIC base address\n",
+					EXYNOS_PM_PREFIX, __func__);
+			BUG();
+		}
+
+		ret = of_property_read_u32(np, "num-eint", &pm_info->num_eint);
+		if (ret) {
+			pr_err("%s %s: unabled to get the number of eint from DT\n",
+					EXYNOS_PM_PREFIX, __func__);
+			BUG();
+		}
+
+		ret = of_property_read_u32(np, "num-gic", &pm_info->num_gic);
+		if (ret) {
+			pr_err("%s %s: unabled to get the number of gic from DT\n",
+					EXYNOS_PM_PREFIX, __func__);
+			BUG();
+		}
+
+		ret = of_property_read_u32(np, "suspend_mode_idx", &pm_info->suspend_mode_idx);
+		if (ret) {
+			pr_err("%s %s: unabled to get suspend_mode_idx from DT\n",
+					EXYNOS_PM_PREFIX, __func__);
+			BUG();
+		}
+
+		ret = of_property_read_u32(np, "suspend_psci_idx", &pm_info->suspend_psci_idx);
+		if (ret) {
+			pr_err("%s %s: unabled to get suspend_psci_idx from DT\n",
+					EXYNOS_PM_PREFIX, __func__);
+			BUG();
+		}
+
+		ret = of_property_read_u32(np, "cp_call_mode_idx", &pm_info->cp_call_mode_idx);
+		if (ret) {
+			pr_err("%s %s: unabled to get cp_call_mode_idx from DT\n",
+					EXYNOS_PM_PREFIX, __func__);
+			BUG();
+		}
+
+		ret = of_property_read_u32(np, "cp_call_psci_idx", &pm_info->cp_call_psci_idx);
+		if (ret) {
+			pr_err("%s %s: unabled to get cp_call_psci_idx from DT\n",
+					EXYNOS_PM_PREFIX, __func__);
+			BUG();
+		}
+
+	} else {
+		pr_err("%s %s: failed to have populated device tree\n",
+					EXYNOS_PM_PREFIX, __func__);
+		BUG();
+	}
+
+	if (subsys_system_register(&exynos_info_subsys,
+					exynos_info_sysfs_groups))
+		pr_err("%s %s: fail to register exynos_info subsys\n",
+					EXYNOS_PM_PREFIX, __func__);
+
+	suspend_set_ops(&exynos_pm_ops);
+	register_syscore_ops(&exynos_pm_syscore_ops);
+#ifdef CONFIG_DEBUG_FS
+	exynos_pm_debugfs_init();
+#endif
+
+#if defined(CONFIG_SEC_FACTORY)
+	/* create sysfs group */
+	ret = sysfs_create_file(power_kobj, &dev_attr_asv_info.attr);
+	if (ret) {
+		pr_err("%s: failed to create exynos7570 asv attribute file\n", __func__);
+	}
+#endif /* CONFIG_SEC_FACTORY */
+
+	return 0;
+}
+arch_initcall(exynos_pm_drvinit);

drivers/soc/samsung/exynos-pmu.c

@@ -0,0 +1,226 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS - CPU PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/smp.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+
+#include <asm/smp_plat.h>
+
+#include <soc/samsung/exynos-pmu.h>
+#include <soc/samsung/pmu-cp.h>
+
+/**
+ * register offset value from base address
+ */
+#define PMU_CP_STAT				0x0038
+
+#define PMU_CPU_CONFIG_BASE			0x2000
+#define PMU_CPU_STATUS_BASE			0x2004
+#define PMU_CPU_ADDR_OFFSET			0x80
+#define CPU_LOCAL_PWR_CFG			0xF
+
+#define PMU_NONCPU_STATUS_BASE			0x2404
+#define PMU_CPUSEQ_OPTION_BASE			0x2488
+#define PMU_L2_STATUS_BASE			0x2604
+#define PMU_CLUSTER_ADDR_OFFSET			0x20
+#define NONCPU_LOCAL_PWR_CFG			0xF
+#define L2_LOCAL_PWR_CFG			0x7
+
+/**
+ * "pmureg" has the mapped base address of PMU(Power Management Unit)
+ */
+static struct regmap *pmureg;
+
+/**
+ * No driver refers the "pmureg" directly, through the only exported API.
+ */
+int exynos_pmu_read(unsigned int offset, unsigned int *val)
+{
+	return regmap_read(pmureg, offset, val);
+}
+
+int exynos_pmu_write(unsigned int offset, unsigned int val)
+{
+	return regmap_write(pmureg, offset, val);
+}
+
+int exynos_pmu_update(unsigned int offset, unsigned int mask, unsigned int val)
+{
+	return regmap_update_bits(pmureg, offset, mask, val);
+}
+
+EXPORT_SYMBOL(exynos_pmu_read);
+EXPORT_SYMBOL(exynos_pmu_write);
+EXPORT_SYMBOL(exynos_pmu_update);
+
+/**
+ * CPU power control registers in PMU are arranged at regular intervals
+ * (interval = 0x80). pmu_cpu_offset calculates how far cpu is from address
+ * of first cpu. This expression is based on cpu and cluster id in MPIDR,
+ * refer below.
+
+ * cpu address offset : ((cluster id << 2) | (cpu id)) * 0x80
+ */
+#define pmu_cpu_offset(mpidr)			\
+	(( MPIDR_AFFINITY_LEVEL(mpidr, 1) << 2	\
+	 | MPIDR_AFFINITY_LEVEL(mpidr, 0))	\
+	 * PMU_CPU_ADDR_OFFSET)
+
+static int exynos_l2_state(unsigned int cluster)
+{
+	unsigned int l2_stat = 0;
+	unsigned int offset;
+
+	offset = cluster * PMU_CLUSTER_ADDR_OFFSET;
+
+	regmap_read(pmureg, PMU_L2_STATUS_BASE + offset, &l2_stat);
+
+	return ((l2_stat & L2_LOCAL_PWR_CFG) == L2_LOCAL_PWR_CFG);
+}
+
+static int exynos_noncpu_state(unsigned int cluster)
+{
+	unsigned int noncpu_stat = 0;
+	unsigned int offset;
+
+	offset = cluster * PMU_CLUSTER_ADDR_OFFSET;
+
+	regmap_read(pmureg, PMU_NONCPU_STATUS_BASE + offset, &noncpu_stat);
+
+	return ((noncpu_stat & NONCPU_LOCAL_PWR_CFG) == NONCPU_LOCAL_PWR_CFG);
+}
+
+static void exynos_cpu_up(unsigned int cpu)
+{
+	unsigned int mpidr = cpu_logical_map(cpu);
+	unsigned int offset;
+
+	offset = pmu_cpu_offset(mpidr);
+	regmap_update_bits(pmureg, PMU_CPU_CONFIG_BASE + offset,
+			CPU_LOCAL_PWR_CFG, CPU_LOCAL_PWR_CFG);
+}
+
+static void exynos_cpu_down(unsigned int cpu)
+{
+	unsigned int mpidr = cpu_logical_map(cpu);
+	unsigned int offset;
+
+	offset = pmu_cpu_offset(mpidr);
+	regmap_update_bits(pmureg, PMU_CPU_CONFIG_BASE + offset,
+			CPU_LOCAL_PWR_CFG, 0);
+}
+
+static int exynos_cpu_state(unsigned int cpu)
+{
+	unsigned int mpidr = cpu_logical_map(cpu);
+	unsigned int offset, val = 0;
+
+	offset = pmu_cpu_offset(mpidr);
+	regmap_read(pmureg, PMU_CPU_STATUS_BASE + offset, &val);
+
+	return ((val & CPU_LOCAL_PWR_CFG) == CPU_LOCAL_PWR_CFG);
+}
+
+static int exynos_cluster_state(unsigned int cluster)
+{
+	unsigned int noncpu_stat, l2_stat = 0;
+
+	noncpu_stat = exynos_noncpu_state(cluster);
+	l2_stat = exynos_l2_state(cluster);
+
+	return l2_stat && noncpu_stat;
+}
+
+/**
+ * While Exynos with multi cluster supports to shutdown down both cluster,
+ * there is no benefit in boot cluster. So Exynos-PMU driver supports
+ * only non-boot cluster down.
+ */
+void exynos_cpu_sequencer_ctrl(unsigned int cluster, int enable)
+{
+	unsigned int offset;
+
+	offset = cluster * PMU_CLUSTER_ADDR_OFFSET;
+	regmap_update_bits(pmureg, PMU_CPUSEQ_OPTION_BASE + offset, 1, enable);
+}
+
+static void exynos_cluster_up(unsigned int cluster)
+{
+	exynos_cpu_sequencer_ctrl(cluster, false);
+}
+
+static void exynos_cluster_down(unsigned int cluster)
+{
+	exynos_cpu_sequencer_ctrl(cluster, true);
+}
+
+struct exynos_cpu_power_ops exynos_cpu = {
+	.power_up = exynos_cpu_up,
+	.power_down = exynos_cpu_down,
+	.power_state = exynos_cpu_state,
+	.cluster_up = exynos_cluster_up,
+	.cluster_down = exynos_cluster_down,
+	.cluster_state = exynos_cluster_state,
+	.l2_state = exynos_l2_state,
+	.noncpu_state = exynos_noncpu_state,
+};
+
+
+int exynos_check_cp_status(void)
+{
+	unsigned int val;
+
+	exynos_pmu_read(PMU_CP_STAT, &val);
+
+	return val;
+}
+
+static int exynos_pmu_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+
+	pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
+						"samsung,syscon-phandle");
+	if (IS_ERR(pmureg)) {
+		pr_err("Fail to get regmap of PMU\n");
+		return PTR_ERR(pmureg);
+	}
+
+	return 0;
+}
+
+static const struct of_device_id of_exynos_pmu_match[] = {
+	{ .compatible = "samsung,exynos-pmu", },
+	{ },
+};
+
+static const struct platform_device_id exynos_pmu_ids[] = {
+	{ "exynos-pmu", },
+	{ }
+};
+
+static struct platform_driver exynos_pmu_driver = {
+	.driver = {
+		.name = "exynos-pmu",
+		.owner = THIS_MODULE,
+		.of_match_table = of_exynos_pmu_match,
+	},
+	.probe		= exynos_pmu_probe,
+	.id_table	= exynos_pmu_ids,
+};
+
+int __init exynos_pmu_init(void)
+{
+	return platform_driver_register(&exynos_pmu_driver);
+}
+subsys_initcall(exynos_pmu_init);

drivers/soc/samsung/exynos-powermode.c

@@ -0,0 +1,847 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS Power mode
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/tick.h>
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+#include <linux/slab.h>
+#include <linux/cpu.h>
+#include <linux/cpuidle_profiler.h>
+#include <linux/irq.h>
+#include <linux/irqchip/arm-gic.h>
+
+#include <asm/smp_plat.h>
+#include <asm/psci.h>
+
+#include <soc/samsung/exynos-pm.h>
+#include <soc/samsung/exynos-pmu.h>
+#include <soc/samsung/exynos-powermode.h>
+
+#include "pwrcal/pwrcal.h"
+#include <trace/events/exynos.h>
+
+#define NUM_WAKEUP_MASK		3
+
+struct exynos_powermode_info {
+	unsigned int	cpd_residency;		/* target residency of cpd */
+	unsigned int	sicd_residency;		/* target residency of sicd */
+
+	struct cpumask	c2_mask;		/* per cpu c2 status */
+
+	/*
+	 * cpd_blocked prevents to power down the cluster. It used by cpufreq
+	 * driver using block_cpd() and release_cpd() or usespace using sysfs
+	 * interface.
+	 */
+	int		cpd_blocked;
+
+	/*
+	 * sicd_enabled is changed by sysfs interface. It is just for
+	 * development convenience because console does not work during
+	 * SICD mode.
+	 */
+	int		sicd_enabled;
+	int		sicd_entered;
+	int		sicd_factory;
+
+	/*
+	 * During intializing time, wakeup_mask and idle_ip_mask is intialized
+	 * with device tree data. These are used when system enter system
+	 * power down mode.
+	 */
+	unsigned int	wakeup_mask[NUM_SYS_POWERDOWN][NUM_WAKEUP_MASK];
+	int		idle_ip_mask[NUM_SYS_POWERDOWN][NUM_IDLE_IP];
+};
+
+static struct exynos_powermode_info *powermode_info;
+
+int is_sicd_factory(void)
+{
+	if (powermode_info->sicd_factory)
+		return true;
+	else
+		return false;
+}
+
+#ifdef CONFIG_ARM64_EXYNOS_CPUIDLE
+
+/******************************************************************************
+ *                                  IDLE_IP                                   *
+ ******************************************************************************/
+#define PMU_IDLE_IP_BASE		0x03E0
+#define PMU_IDLE_IP_MASK_BASE		0x03F0
+#define PMU_IDLE_IP(x)			(PMU_IDLE_IP_BASE + (x * 0x4))
+#define PMU_IDLE_IP_MASK(x)		(PMU_IDLE_IP_MASK_BASE + (x * 0x4))
+
+static int exynos_check_idle_ip_stat(int mode, int reg_index)
+{
+	unsigned int val, mask;
+	int ret;
+
+	exynos_pmu_read(PMU_IDLE_IP(reg_index), &val);
+	mask = powermode_info->idle_ip_mask[mode][reg_index];
+
+	ret = (val & ~mask) == ~mask ? 0 : -EBUSY;
+
+	if (ret) {
+		/*
+		 * Profile non-idle IP using idle_ip.
+		 * A bit of idle-ip equals 0, it means non-idle. But then, if
+		 * same bit of idle-ip-mask is 1, PMU does not see this bit.
+		 * To know what IP blocks to enter system power mode, suppose
+		 * below example: (express only 8 bits)
+		 *
+		 * idle-ip  : 1 0 1 1 0 0 1 0
+		 * mask     : 1 1 0 0 1 0 0 1
+		 *
+		 * First, clear masked idle-ip bit.
+		 *
+		 * idle-ip  : 1 0 1 1 0 0 1 0
+		 * ~mask    : 0 0 1 1 0 1 1 0
+		 * -------------------------- (AND)
+		 * idle-ip' : 0 0 1 1 0 0 1 0
+		 *
+		 * In upper case, only idle-ip[2] is not in idle. Calculates
+		 * as follows, then we can get the non-idle IP easily.
+		 *
+		 * idle-ip' : 0 0 1 1 0 0 1 0
+		 * ~mask    : 0 0 1 1 0 1 1 0
+		 *--------------------------- (XOR)
+		 *            0 0 0 0 0 1 0 0
+		 */
+		cpuidle_profile_collect_idle_ip(mode, reg_index,
+				((val & ~mask) ^ ~mask));
+	}
+
+	return ret;
+}
+
+static DEFINE_SPINLOCK(idle_ip_mask_lock);
+static void exynos_set_idle_ip_mask(enum sys_powerdown mode)
+{
+	int i;
+	unsigned long flags;
+
+	spin_lock_irqsave(&idle_ip_mask_lock, flags);
+	for_each_idle_ip(i)
+		exynos_pmu_write(PMU_IDLE_IP_MASK(i),
+				powermode_info->idle_ip_mask[mode][i]);
+	spin_unlock_irqrestore(&idle_ip_mask_lock, flags);
+}
+
+/**
+ * There are 4 IDLE_IP registers in PMU, IDLE_IP therefore supports 128 index,
+ * 0 from 127. To access the IDLE_IP register, convert_idle_ip_index() converts
+ * idle_ip index to register index and bit in regster. For example, idle_ip index
+ * 33 converts to IDLE_IP1[1]. convert_idle_ip_index() returns register index
+ * and ships bit in register to *ip_index.
+ */
+static int convert_idle_ip_index(int *ip_index)
+{
+	int reg_index;
+
+	reg_index = *ip_index / IDLE_IP_REG_SIZE;
+	*ip_index = *ip_index % IDLE_IP_REG_SIZE;
+
+	return reg_index;
+}
+
+static void idle_ip_unmask(int mode, int ip_index)
+{
+	int reg_index = convert_idle_ip_index(&ip_index);
+	unsigned long flags;
+
+	spin_lock_irqsave(&idle_ip_mask_lock, flags);
+	powermode_info->idle_ip_mask[mode][reg_index] &= ~(0x1 << ip_index);
+	spin_unlock_irqrestore(&idle_ip_mask_lock, flags);
+}
+
+static int is_idle_ip_index_used(struct device_node *node, int ip_index)
+{
+	int proplen;
+	int ref_idle_ip[IDLE_IP_MAX_INDEX];
+	int i;
+
+	proplen = of_property_count_u32_elems(node, "ref-idle-ip");
+
+	if (proplen <= 0)
+		return false;
+
+	if (!of_property_read_u32_array(node, "ref-idle-ip",
+					ref_idle_ip, proplen)) {
+		for (i = 0; i < proplen; i++)
+			if (ip_index == ref_idle_ip[i])
+				return true;
+	}
+
+	return false;
+}
+
+static void exynos_create_idle_ip_mask(int ip_index)
+{
+	struct device_node *root = of_find_node_by_path("/exynos-powermode/idle_ip_mask");
+	struct device_node *node;
+
+	for_each_child_of_node(root, node) {
+		int mode;
+
+		if (of_property_read_u32(node, "mode-index", &mode))
+			continue;
+
+		if (is_idle_ip_index_used(node, ip_index))
+			idle_ip_unmask(mode, ip_index);
+	}
+}
+
+int exynos_get_idle_ip_index(const char *ip_name)
+{
+	struct device_node *np = of_find_node_by_name(NULL, "exynos-powermode");
+	int ip_index, fix_idle_ip;
+	int ret;
+
+	fix_idle_ip = of_property_match_string(np, "fix-idle-ip", ip_name);
+	if (fix_idle_ip >= 0) {
+		ret = of_property_read_u32_index(np, "fix-idle-ip-index",
+						fix_idle_ip, &ip_index);
+		if (ret) {
+			pr_err("%s: Cannot get fix-idle-ip-index property\n", __func__);
+			return ret;
+		}
+
+		goto create_idle_ip;
+	}
+
+	ip_index = of_property_match_string(np, "idle-ip", ip_name);
+	if (ip_index < 0) {
+		pr_err("%s: Fail to find %s in idle-ip list with err %d\n",
+					__func__, ip_name, ip_index);
+		return ip_index;
+	}
+
+	if (ip_index > IDLE_IP_MAX_CONFIGURABLE_INDEX) {
+		pr_err("%s: %s index %d is out of range\n",
+					__func__, ip_name, ip_index);
+		return ip_index;
+	}
+
+create_idle_ip:
+	/**
+	 * If it successes to find IP in idle_ip list, we set
+	 * corresponding bit in idle_ip mask.
+	 */
+	exynos_create_idle_ip_mask(ip_index);
+
+	return ip_index;
+}
+
+static DEFINE_SPINLOCK(ip_idle_lock);
+void exynos_update_ip_idle_status(int ip_index, int idle)
+{
+	unsigned long flags;
+	int reg_index;
+
+	/*
+	 * If ip_index is not valid, it should not update IDLE_IP.
+	 */
+	if (ip_index < 0 || ip_index > IDLE_IP_MAX_CONFIGURABLE_INDEX)
+		return;
+
+	reg_index = convert_idle_ip_index(&ip_index);
+
+	spin_lock_irqsave(&ip_idle_lock, flags);
+	exynos_pmu_update(PMU_IDLE_IP(reg_index),
+				1 << ip_index, idle << ip_index);
+	spin_unlock_irqrestore(&ip_idle_lock, flags);
+
+	return;
+}
+
+void exynos_get_idle_ip_list(char *(*idle_ip_list)[IDLE_IP_REG_SIZE])
+{
+	struct device_node *np = of_find_node_by_name(NULL, "exynos-powermode");
+	int size;
+	const char *list[IDLE_IP_MAX_CONFIGURABLE_INDEX];
+	int i, bit, reg_index;
+
+	size = of_property_count_strings(np, "idle-ip");
+	if (of_property_read_string_array(np, "idle-ip", list, size) < 0) {
+		pr_err("%s: Cannot find idle-ip property\n", __func__);
+		return;
+	}
+
+	for (i = 0, bit = 0; i < size; i++, bit = i) {
+		reg_index = convert_idle_ip_index(&bit);
+		idle_ip_list[reg_index][bit] = (char *)list[i];
+	}
+
+	/* IDLE_IP3[31:30] is for the exclusive use of pcie wifi */
+	size = of_property_count_strings(np, "fix-idle-ip");
+	if (of_property_read_string_array(np, "fix-idle-ip", list, size) < 0) {
+		pr_err("%s: Cannot find fix-idle-ip property\n", __func__);
+		return;
+	}
+
+	for (i = 0; i < size; i++) {
+		if (!of_property_read_u32_index(np, "fix-idle-ip-index", i, &bit)) {
+			reg_index = convert_idle_ip_index(&bit);
+			idle_ip_list[reg_index][bit] = (char *)list[i];
+		}
+	}
+}
+
+/******************************************************************************
+ *                          Local power gating (C2)                           *
+ ******************************************************************************/
+/**
+ * If cpu is powered down, c2_mask in struct exynos_powermode_info is set. On
+ * the contrary, cpu is powered on, c2_mask is cleard. To keep coherency of
+ * c2_mask, use the spinlock, c2_lock. In Exynos, it supports C2 subordinate
+ * power mode, CPD.
+ *
+ * - CPD (Cluster Power Down)
+ * All cpus in a cluster are set c2_mask, and these cpus have enough idle
+ * time which is longer than cpd_residency, cluster can be powered off.
+ *
+ * SICD (System Idle Clock Down) : All cpus are set c2_mask and these cpus
+ * have enough idle time which is longer than sicd_residency, AP can be put
+ * into SICD. During SICD, no one access to DRAM.
+ */
+
+static DEFINE_SPINLOCK(c2_lock);
+
+static void update_c2_state(bool down, unsigned int cpu)
+{
+	if (down)
+		cpumask_set_cpu(cpu, &powermode_info->c2_mask);
+	else
+		cpumask_clear_cpu(cpu, &powermode_info->c2_mask);
+}
+
+static s64 get_next_event_time_us(unsigned int cpu)
+{
+	struct clock_event_device *dev = per_cpu(tick_cpu_device, cpu).evtdev;
+
+	return ktime_to_us(ktime_sub(dev->next_event, ktime_get()));
+}
+
+static int is_cpus_busy(unsigned int target_residency,
+				const struct cpumask *mask)
+{
+	int cpu;
+
+	/*
+	 * If there is even one cpu in "mask" which has the smaller idle time
+	 * than "target_residency", it returns -EBUSY.
+	 */
+	for_each_cpu_and(cpu, cpu_online_mask, mask) {
+		if (!cpumask_test_cpu(cpu, &powermode_info->c2_mask))
+			return -EBUSY;
+
+		/*
+		 * Compare cpu's next event time and target_residency.
+		 * Next event time means idle time.
+		 */
+		if (get_next_event_time_us(cpu) < target_residency)
+			return -EBUSY;
+	}
+
+	return 0;
+}
+
+/**
+ * powermode_info->cpd_blocked prevents to power down the cluster while cpu
+ * frequency is changed. Before frequency changing, cpufreq driver call
+ * block_cpd() to block cluster power down. After finishing changing
+ * frequency, call release_cpd() to allow cluster power down again.
+ */
+void block_cpd(void)
+{
+	powermode_info->cpd_blocked = true;
+}
+
+void release_cpd(void)
+{
+	powermode_info->cpd_blocked = false;
+}
+
+static unsigned int get_cluster_id(unsigned int cpu)
+{
+	return MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 1);
+}
+
+static bool is_cpu_boot_cluster(unsigned int cpu)
+{
+	/*
+	 * The cluster included cpu0 is boot cluster
+	 */
+	return (get_cluster_id(0) == get_cluster_id(cpu));
+}
+
+static int is_cpd_available(unsigned int cpu)
+{
+	struct cpumask mask;
+
+	if (powermode_info->cpd_blocked)
+		return false;
+
+	/*
+	 * Power down of boot cluster have nothing to gain power consumption,
+	 * so it is not supported.
+	 */
+	if (is_cpu_boot_cluster(cpu))
+		return false;
+
+	cpumask_and(&mask, cpu_coregroup_mask(cpu), cpu_online_mask);
+	if (is_cpus_busy(powermode_info->cpd_residency, &mask))
+		return false;
+
+	return true;
+}
+
+/**
+ * cluster_idle_state shows whether cluster is in idle or not.
+ *
+ * check_cluster_idle_state() : Show cluster idle state.
+ * 		If it returns true, cluster is in idle state.
+ * update_cluster_idle_state() : Update cluster idle state.
+ */
+#define CLUSTER_TYPE_MAX	2
+static int cluster_idle_state[CLUSTER_TYPE_MAX];
+
+int check_cluster_idle_state(unsigned int cpu)
+{
+	return cluster_idle_state[get_cluster_id(cpu)];
+}
+
+static void update_cluster_idle_state(int idle, unsigned int cpu)
+{
+	cluster_idle_state[get_cluster_id(cpu)] = idle;
+}
+
+/**
+ * If AP put into SICD, console cannot work normally. For development,
+ * support sysfs to enable or disable SICD.
+ * And It is possible to use console by SICD factory mode.
+ * Refer below :
+ *
+ * echo 0/1 > /sys/power/sicd (0:disable, 1:enable)
+ * or
+ * echo 0/1 > /sys/power/sicd_factory_mode (0:disable, 1:enable)
+ */
+static int is_sicd_available(unsigned int cpu)
+{
+	int index;
+
+	if (!powermode_info->sicd_enabled)
+		return false;
+
+	/*
+	 * When the cpu in non-boot cluster enters SICD, interrupts of
+	 * boot cluster is not blocked. For stability, SICD entry by
+	 * non-boot cluster is not supported.
+	 */
+	if (!is_cpu_boot_cluster(cpu))
+		return false;
+
+	if (is_cpus_busy(powermode_info->sicd_residency, cpu_online_mask))
+		return false;
+
+	if (!exynos_check_cp_status())
+		return false;
+
+	for_each_idle_ip(index)
+		if (exynos_check_idle_ip_stat(SYS_SICD, index))
+			return false;
+
+	return true;
+}
+
+/**
+ * Exynos cpuidle driver call enter_c2() and wakeup_from_c2() to handle platform
+ * specific configuration to power off the cpu power domain. It handles not only
+ * cpu power control, but also power mode subordinate to C2.
+ */
+int enter_c2(unsigned int cpu, int index)
+{
+	unsigned int cluster = get_cluster_id(cpu);
+#ifdef CONFIG_PMUCAL_MOD
+	cal_cpu_disable(cpu);
+#else
+	exynos_cpu.power_down(cpu);
+#endif
+
+	spin_lock(&c2_lock);
+	update_c2_state(true, cpu);
+
+	/*
+	 * Below sequence determines whether to power down the cluster/enter SICD
+	 * or not. If idle time of cpu is not enough, go out of this function.
+	 */
+	if (get_next_event_time_us(cpu) <
+			min(powermode_info->cpd_residency, powermode_info->sicd_residency))
+		goto out;
+
+	if (is_cpd_available(cpu)) {
+#ifdef CONFIG_PMUCAL_MOD
+		cal_cluster_disable(cluster);
+#else
+		exynos_cpu.cluster_down(cluster);
+#endif
+		update_cluster_idle_state(true, cpu);
+
+		index = PSCI_CLUSTER_SLEEP;
+	}
+
+	if (is_sicd_available(cpu)) {
+		if (check_cluster_idle_state(cpu)) {
+#if defined(CONFIG_SOC_EXYNOS8890)
+			exynos_prepare_sys_powerdown(SYS_SICD_CPD, false);
+			index = PSCI_SYSTEM_IDLE_CLUSTER_SLEEP;
+#endif
+		} else {
+			exynos_prepare_sys_powerdown(SYS_SICD, false);
+			index = PSCI_SYSTEM_IDLE;
+		}
+
+		s3c24xx_serial_fifo_wait();
+		powermode_info->sicd_entered = SYS_SICD;
+
+		exynos_ss_cpuidle(EXYNOS_SS_SICD_INDEX, 0, 0, ESS_FLAG_IN);
+		trace_exynos_cpuidle_in(EXYNOS_SS_SICD_INDEX);
+	}
+out:
+	spin_unlock(&c2_lock);
+
+	return index;
+}
+
+void wakeup_from_c2(unsigned int cpu, int early_wakeup)
+{
+	if (early_wakeup)
+#ifdef CONFIG_PMUCAL_MOD
+		cal_cpu_enable(cpu);
+#else
+		exynos_cpu.power_up(cpu);
+#endif
+
+	spin_lock(&c2_lock);
+
+	if (check_cluster_idle_state(cpu)) {
+#ifdef CONFIG_PMUCAL_MOD
+		cal_cluster_enable(get_cluster_id(cpu));
+#else
+		exynos_cpu.cluster_up(get_cluster_id(cpu));
+#endif
+		update_cluster_idle_state(false, cpu);
+	}
+
+	if (powermode_info->sicd_entered != -1) {
+		exynos_wakeup_sys_powerdown(powermode_info->sicd_entered, early_wakeup);
+		powermode_info->sicd_entered = -1;
+
+		exynos_ss_cpuidle(EXYNOS_SS_SICD_INDEX, 0, 0, ESS_FLAG_OUT);
+		trace_exynos_cpuidle_out(EXYNOS_SS_SICD_INDEX);
+	}
+
+	update_c2_state(false, cpu);
+
+	spin_unlock(&c2_lock);
+}
+
+/**
+ * powermode_attr_read() / show_##file_name() -
+ * print out power mode information
+ *
+ * powermode_attr_write() / store_##file_name() -
+ * sysfs write access
+ */
+#define show_one(file_name, object)			\
+static ssize_t show_##file_name(struct kobject *kobj,	\
+	struct kobj_attribute *attr, char *buf)		\
+{							\
+	return snprintf(buf, 3, "%d\n",			\
+				powermode_info->object);	\
+}
+
+#define store_one(file_name, object)			\
+static ssize_t store_##file_name(struct kobject *kobj,	\
+	struct kobj_attribute *attr, const char *buf,	\
+	size_t count)					\
+{							\
+	int input;					\
+							\
+	if (!sscanf(buf, "%1d", &input))		\
+		return -EINVAL;				\
+							\
+	powermode_info->object = !!input;				\
+							\
+	return count;					\
+}
+
+#define attr_rw(_name)					\
+static struct kobj_attribute _name =			\
+__ATTR(_name, 0644, show_##_name, store_##_name)
+
+show_one(blocking_cpd, cpd_blocked);
+show_one(sicd, sicd_enabled);
+show_one(sicd_factory_mode, sicd_factory);
+store_one(blocking_cpd, cpd_blocked);
+store_one(sicd, sicd_enabled);
+store_one(sicd_factory_mode, sicd_factory);
+
+attr_rw(blocking_cpd);
+attr_rw(sicd);
+attr_rw(sicd_factory_mode);
+
+/**
+ * To determine which power mode system enter, check clock or power
+ * registers and other devices by notifier.
+ */
+int determine_lpm(void)
+{
+#if !defined(CONFIG_SOC_EXYNOS7870) && !defined(CONFIG_SOC_EXYNOS7570)
+	int index;
+#endif
+
+	if (!exynos_check_cp_status())
+		return SYS_AFTR;
+
+#if !defined(CONFIG_SOC_EXYNOS7870) && !defined(CONFIG_SOC_EXYNOS7570)
+	for_each_idle_ip(index) {
+		if (exynos_check_idle_ip_stat(SYS_ALPA, index))
+			return SYS_AFTR;
+	}
+	return SYS_ALPA;
+#else
+	return SYS_AFTR;
+#endif
+}
+
+/*
+ * In case of non-boot cluster, CPU sequencer should be disabled
+ * even each cpu wake up through hotplug in.
+ */
+static int exynos_cpuidle_hotcpu_callback(struct notifier_block *nfb,
+                                       unsigned long action, void *hcpu)
+{
+       unsigned int cpu = (unsigned long)hcpu;
+       int ret = NOTIFY_OK;
+
+       switch (action) {
+       case CPU_STARTING:
+               spin_lock(&c2_lock);
+
+               if (!is_cpu_boot_cluster(cpu))
+                       exynos_cpu.cluster_up(get_cluster_id(cpu));
+
+               spin_unlock(&c2_lock);
+               break;
+       }
+
+       return ret;
+}
+
+static struct notifier_block __refdata cpuidle_hotcpu_notifier = {
+       .notifier_call = exynos_cpuidle_hotcpu_callback,
+       .priority = INT_MAX,
+};
+
+#endif /* __CONFIG_ARM64_EXYNOS_CPUIDLE__ */
+
+/******************************************************************************
+ *                          Wakeup mask configuration                         *
+ ******************************************************************************/
+#define PMU_EINT_WAKEUP_MASK	0x60C
+#define PMU_WAKEUP_MASK		0x610
+#define PMU_WAKEUP_MASK2	0x614
+#define PMU_WAKEUP_MASK3	0x618
+#define WAKEUP_MASK_RTC_TICK	BIT(2)
+#define WAKEUP_MASK_RTC_ALARM	BIT(1)
+
+static void exynos_set_wakeupmask(enum sys_powerdown mode)
+{
+	u64 eintmask = exynos_get_eint_wake_mask();
+
+	/* Set external interrupt mask */
+	exynos_pmu_write(PMU_EINT_WAKEUP_MASK, (u32)eintmask);
+
+	exynos_pmu_write(PMU_WAKEUP_MASK, powermode_info->wakeup_mask[mode][0]);
+	exynos_pmu_write(PMU_WAKEUP_MASK2, powermode_info->wakeup_mask[mode][1]);
+	exynos_pmu_write(PMU_WAKEUP_MASK3, powermode_info->wakeup_mask[mode][2]);
+}
+
+static int exynos_irq_set_wake(struct irq_data *data, unsigned int on)
+{
+	unsigned int ret = -ENXIO;
+	unsigned int val = powermode_info->wakeup_mask[SYS_SLEEP][0];
+
+	if (!(val & WAKEUP_MASK_RTC_ALARM) || !(val & WAKEUP_MASK_RTC_TICK))
+		ret = 0;
+
+	return ret;
+}
+
+static int __maybe_unused parsing_dt_wakeup_mask(struct device_node *np)
+{
+	int ret;
+	unsigned int pdn_num;
+
+	for_each_syspower_mode(pdn_num) {
+		ret = of_property_read_u32_index(np, "wakeup_mask",
+				pdn_num, &powermode_info->wakeup_mask[pdn_num][0]);
+		if (ret)
+			return ret;
+
+		ret = of_property_read_u32_index(np, "wakeup_mask2",
+				pdn_num, &powermode_info->wakeup_mask[pdn_num][1]);
+		if (ret)
+			return ret;
+
+		ret = of_property_read_u32_index(np, "wakeup_mask3",
+				pdn_num, &powermode_info->wakeup_mask[pdn_num][2]);
+		if (ret)
+			return ret;
+	}
+
+	gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
+
+	return 0;
+}
+
+/******************************************************************************
+ *                           System power down mode                           *
+ ******************************************************************************/
+void exynos_prepare_sys_powerdown(enum sys_powerdown mode, bool is_suspend)
+{
+	/*
+	 * exynos_prepare_sys_powerdown() is called by only cpu0.
+	 */
+	unsigned int cpu = 0;
+#ifdef CONFIG_ARM64_EXYNOS_CPUIDLE
+	if (is_suspend)
+		exynos_set_idle_ip_mask(SYS_SLEEP);
+	else
+		exynos_set_idle_ip_mask(mode);
+#endif
+	if (is_suspend)
+		exynos_set_wakeupmask(SYS_SLEEP);
+	else
+		exynos_set_wakeupmask(mode);
+
+	cal_pm_enter(mode);
+
+	switch (mode) {
+#if !defined(CONFIG_SOC_EXYNOS7870) && !defined(CONFIG_SOC_EXYNOS7570)
+	case SYS_SICD_AUD:
+		exynos_pm_sicd_enter();
+		break;
+#endif
+	case SYS_AFTR:
+#ifdef CONFIG_PMUCAL_MOD
+		cal_cpu_disable(cpu);
+#else
+		exynos_cpu.power_down(cpu);
+#endif
+		break;
+	default:
+		break;
+	}
+}
+
+void exynos_wakeup_sys_powerdown(enum sys_powerdown mode, bool early_wakeup)
+{
+	/*
+	 * exynos_wakeup_sys_powerdown() is called by only cpu0.
+	 */
+	unsigned int cpu = 0;
+
+	if (early_wakeup)
+		cal_pm_earlywakeup(mode);
+	else
+		cal_pm_exit(mode);
+
+	switch (mode) {
+#if !defined(CONFIG_SOC_EXYNOS7870) && !defined(CONFIG_SOC_EXYNOS7570)
+	case SYS_SICD_AUD:
+		exynos_pm_sicd_exit();
+		break;
+#endif
+	case SYS_AFTR:
+		if (early_wakeup)
+#ifdef CONFIG_PMUCAL_MOD
+			cal_cpu_enable(cpu);
+#else
+			exynos_cpu.power_up(cpu);
+#endif
+		break;
+	default:
+		break;
+	}
+}
+
+/******************************************************************************
+ *                              Driver initialized                            *
+ ******************************************************************************/
+static int __init dt_init_exynos_powermode(void)
+{
+	struct device_node *np = of_find_node_by_name(NULL, "exynos-powermode");
+	int ret;
+
+	ret = parsing_dt_wakeup_mask(np);
+	if (ret)
+		pr_warn("Fail to initialize the wakeup mask with err = %d\n", ret);
+
+	if (of_property_read_u32(np, "cpd_residency", &powermode_info->cpd_residency))
+		pr_warn("No matching property: cpd_residency\n");
+
+	if (of_property_read_u32(np, "sicd_residency", &powermode_info->sicd_residency))
+		pr_warn("No matching property: sicd_residency\n");
+
+	if (of_property_read_u32(np, "sicd_enabled", &powermode_info->sicd_enabled))
+		pr_warn("No matching property: sicd_enabled\n");
+
+	return 0;
+}
+
+int __init exynos_powermode_init(void)
+{
+	int mode, index;
+
+	powermode_info = kzalloc(sizeof(struct exynos_powermode_info), GFP_KERNEL);
+	if (powermode_info == NULL) {
+		pr_err("%s: failed to allocate exynos_powermode_info\n", __func__);
+		return -ENOMEM;
+	}
+
+	dt_init_exynos_powermode();
+
+	for_each_syspower_mode(mode)
+		for_each_idle_ip(index)
+			powermode_info->idle_ip_mask[mode][index] = 0xFFFFFFFF;
+
+#ifdef CONFIG_ARM64_EXYNOS_CPUIDLE
+	if (sysfs_create_file(power_kobj, &blocking_cpd.attr))
+		pr_err("%s: failed to create sysfs to control CPD\n", __func__);
+
+	if (sysfs_create_file(power_kobj, &sicd.attr))
+		pr_err("%s: failed to create sysfs to control CPD\n", __func__);
+
+	if (sysfs_create_file(power_kobj, &sicd_factory_mode.attr))
+		pr_err("%s: failed to create sysfs to control SICD Factory mode\n", __func__);
+
+	register_hotcpu_notifier(&cpuidle_hotcpu_notifier);
+#endif
+
+	return 0;
+}
+arch_initcall(exynos_powermode_init);

drivers/soc/samsung/exynos-reboot.c

@@ -0,0 +1,247 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *	      http://www.samsung.com/
+ *
+ * Exynos - Support SoC specific Reboot
+ * Author: Hosung Kim <hosung0.kim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/reboot.h>
+#include <linux/soc/samsung/exynos-soc.h>
+
+extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
+static void __iomem *exynos_pmu_base = NULL;
+
+static const char * const mngs_cores[] = {
+	"arm,mongoose",
+	NULL,
+};
+
+static bool is_mngs_cpu(struct device_node *cn)
+{
+	const char * const *lc;
+	for (lc = mngs_cores; *lc; lc++)
+		if (of_device_is_compatible(cn, *lc))
+			return true;
+	return false;
+}
+
+int soc_has_mongoose(void)
+{
+	struct device_node *cn = NULL;
+	u32 mngs_cpu_cnt = 0;
+
+	/* find arm,mongoose compatable in device tree */
+	while ((cn = of_find_node_by_type(cn, "cpu"))) {
+		if (is_mngs_cpu(cn))
+			mngs_cpu_cnt++;
+	}
+	return mngs_cpu_cnt;
+}
+
+/* defines for MNGS reset */
+#define PEND_MNGS				(1 << 1)
+#define PEND_APOLLO				(1 << 0)
+#define DEFAULT_VAL_CPU_RESET_DISABLE		(0xFFFFFFFC)
+#define RESET_DISABLE_GPR_CPUPORESET		(1 << 15)
+#define RESET_DISABLE_WDT_CPUPORESET		(1 << 12)
+#define RESET_DISABLE_CORERESET			(1 << 9)
+#define RESET_DISABLE_CPUPORESET		(1 << 8)
+#define RESET_DISABLE_WDT_PRESET_DBG		(1 << 25)
+#define RESET_DISABLE_PRESET_DBG		(1 << 18)
+#define DFD_EDPCSR_DUMP_EN			(1 << 0)
+#define RESET_DISABLE_L2RESET			(1 << 16)
+#define RESET_DISABLE_WDT_L2RESET		(1 << 31)
+
+#define EXYNOS_PMU_CPU_RESET_DISABLE_FROM_SOFTRESET	(0x041C)
+#define EXYNOS_PMU_CPU_RESET_DISABLE_FROM_WDTRESET	(0x0414)
+#define EXYNOS_PMU_ATLAS_CPU0_RESET			(0x200C)
+#define EXYNOS_PMU_ATLAS_DBG_RESET			(0x244C)
+#define EXYNOS_PMU_ATLAS_NONCPU_RESET			(0x240C)
+#define EXYNOS_PMU_SWRESET				(0x0400)
+#define EXYNOS_PMU_RESET_SEQUENCER_CONFIGURATION	(0x0500)
+#define EXYNOS_PMU_PS_HOLD_CONTROL			(0x330C)
+
+static void mngs_reset_control(int en)
+{
+	u32 reg_val, val;
+	u32 mngs_cpu_cnt = soc_has_mongoose();
+
+	if (mngs_cpu_cnt == 0 || !exynos_pmu_base)
+		return;
+
+	if (en) {
+		/* reset disable for MNGS */
+		pr_err("%s: mngs cpu reset disable\n", __func__);
+		reg_val = readl(exynos_pmu_base + EXYNOS_PMU_CPU_RESET_DISABLE_FROM_SOFTRESET);
+		if (reg_val & (PEND_MNGS | PEND_APOLLO)) {
+			reg_val &= ~(PEND_MNGS | PEND_APOLLO);
+			writel(reg_val, exynos_pmu_base + EXYNOS_PMU_CPU_RESET_DISABLE_FROM_SOFTRESET);
+		}
+
+		reg_val = readl(exynos_pmu_base + EXYNOS_PMU_CPU_RESET_DISABLE_FROM_WDTRESET);
+		if (reg_val != DEFAULT_VAL_CPU_RESET_DISABLE) {
+			reg_val &= ~(PEND_MNGS | PEND_APOLLO);
+			writel(reg_val, exynos_pmu_base + EXYNOS_PMU_CPU_RESET_DISABLE_FROM_WDTRESET);
+		}
+
+		for (val = 0; val < mngs_cpu_cnt; val++) {
+			reg_val = readl(exynos_pmu_base + EXYNOS_PMU_ATLAS_CPU0_RESET + (val * 0x80));
+#ifdef CONFIG_SOC_EXYNOS8890_EVT1
+			reg_val |= (RESET_DISABLE_WDT_CPUPORESET
+					| RESET_DISABLE_CORERESET | RESET_DISABLE_CPUPORESET);
+#else
+			reg_val |= (RESET_DISABLE_CORERESET | RESET_DISABLE_CPUPORESET);
+#endif
+			writel(reg_val, exynos_pmu_base + EXYNOS_PMU_ATLAS_CPU0_RESET + (val * 0x80));
+		}
+
+		reg_val = readl(exynos_pmu_base + EXYNOS_PMU_ATLAS_DBG_RESET);
+#ifdef CONFIG_SOC_EXYNOS8890_EVT1
+		reg_val |= (RESET_DISABLE_WDT_PRESET_DBG | RESET_DISABLE_PRESET_DBG);
+#else
+		reg_val |= (RESET_DISABLE_PRESET_DBG);
+#endif
+		writel(reg_val, exynos_pmu_base + EXYNOS_PMU_ATLAS_DBG_RESET);
+
+                reg_val = readl(exynos_pmu_base + EXYNOS_PMU_ATLAS_NONCPU_RESET);
+#ifdef CONFIG_SOC_EXYNOS8890_EVT1
+                reg_val |= (RESET_DISABLE_L2RESET | RESET_DISABLE_WDT_L2RESET);
+#else
+                reg_val |= (RESET_DISABLE_L2RESET);
+#endif
+                writel(reg_val, exynos_pmu_base + EXYNOS_PMU_ATLAS_NONCPU_RESET);
+	} else {
+		/* reset enable for MNGS */
+		pr_err("%s: mngs cpu reset enable before s/w reset\n", __func__);
+		for (val = 0; val < mngs_cpu_cnt; val++) {
+			reg_val = readl(exynos_pmu_base + EXYNOS_PMU_ATLAS_CPU0_RESET + (val * 0x80));
+#ifdef CONFIG_SOC_EXYNOS8890_EVT1
+			reg_val &= ~(RESET_DISABLE_WDT_CPUPORESET
+					| RESET_DISABLE_CORERESET | RESET_DISABLE_CPUPORESET);
+#else
+			reg_val &= ~(RESET_DISABLE_CORERESET | RESET_DISABLE_CPUPORESET);
+#endif
+			writel(reg_val, exynos_pmu_base + EXYNOS_PMU_ATLAS_CPU0_RESET + (val * 0x80));
+		}
+
+		reg_val = readl(exynos_pmu_base + EXYNOS_PMU_ATLAS_DBG_RESET);
+#ifdef CONFIG_SOC_EXYNOS8890_EVT1
+		reg_val &= ~(RESET_DISABLE_WDT_PRESET_DBG | RESET_DISABLE_PRESET_DBG);
+#else
+		reg_val &= ~(RESET_DISABLE_PRESET_DBG);
+#endif
+		writel(reg_val, exynos_pmu_base + EXYNOS_PMU_ATLAS_DBG_RESET);
+
+                reg_val = readl(exynos_pmu_base + EXYNOS_PMU_ATLAS_NONCPU_RESET);
+#ifdef CONFIG_SOC_EXYNOS8890_EVT1
+                reg_val &= ~(RESET_DISABLE_L2RESET);
+#endif
+                writel(reg_val, exynos_pmu_base + EXYNOS_PMU_ATLAS_NONCPU_RESET);
+	}
+}
+
+#define INFORM_NONE		0x0
+#define INFORM_RAMDUMP		0xd
+#define INFORM_RECOVERY		0xf
+
+#if !defined(CONFIG_SEC_REBOOT)
+#ifdef CONFIG_OF
+static void exynos_power_off(void)
+{
+	pr_emerg("%s: Set PS_HOLD Low.\n", __func__);
+	writel(readl(exynos_pmu_base + EXYNOS_PMU_PS_HOLD_CONTROL) & 0xFFFFFEFF,
+				exynos_pmu_base + EXYNOS_PMU_PS_HOLD_CONTROL);
+}
+#else
+static void exynos_power_off(void)
+{
+	pr_info("Exynos power off does not support.\n");
+}
+#endif
+#endif
+
+static void exynos_reboot(enum reboot_mode mode, const char *cmd)
+{
+	u32 restart_inform, soc_id;
+
+	if (!exynos_pmu_base)
+		return;
+
+	restart_inform = INFORM_NONE;
+
+	if (cmd) {
+		if (!strcmp((char *)cmd, "recovery"))
+			restart_inform = INFORM_RECOVERY;
+		else if(!strcmp((char *)cmd, "ramdump"))
+			restart_inform = INFORM_RAMDUMP;
+	}
+
+	/* Check by each SoC */
+	soc_id = exynos_soc_info.product_id & EXYNOS_SOC_MASK;
+	switch(soc_id) {
+	case EXYNOS8890_SOC_ID:
+		/* Check reset_sequencer_configuration register */
+		if (readl(exynos_pmu_base + EXYNOS_PMU_RESET_SEQUENCER_CONFIGURATION) & DFD_EDPCSR_DUMP_EN)
+			mngs_reset_control(0);
+		break;
+	default:
+		break;
+	}
+
+	/* Do S/W Reset */
+	__raw_writel(0x1, exynos_pmu_base + EXYNOS_PMU_SWRESET);
+}
+
+static int __init exynos_reboot_setup(struct device_node *np)
+{
+	int err = 0;
+	u32 id;
+
+	if (!of_property_read_u32(np, "pmu_base", &id)) {
+		exynos_pmu_base = ioremap(id, SZ_16K);
+		if (!exynos_pmu_base) {
+			pr_err("%s: failed to map to exynos-pmu-base address 0x%x\n",
+				__func__, id);
+			err = -ENOMEM;
+		}
+	}
+
+	of_node_put(np);
+	return err;
+}
+
+static const struct of_device_id reboot_of_match[] __initconst = {
+	{ .compatible = "exynos,reboot", .data = exynos_reboot_setup},
+	{},
+};
+
+typedef int (*reboot_initcall_t)(const struct device_node *);
+static int __init exynos_reboot_init(void)
+{
+	struct device_node *np;
+	const struct of_device_id *matched_np;
+	reboot_initcall_t init_fn;
+
+	np = of_find_matching_node_and_match(NULL, reboot_of_match, &matched_np);
+	if (!np)
+		return -ENODEV;
+
+	arm_pm_restart = exynos_reboot;
+#if !defined(CONFIG_SEC_REBOOT)
+	pm_power_off = exynos_power_off;
+#endif
+	init_fn = (reboot_initcall_t)matched_np->data;
+
+	return init_fn(np);
+}
+subsys_initcall(exynos_reboot_init);

drivers/soc/samsung/exynos-rgt.c

@@ -0,0 +1,374 @@
+/*
+ * Exynos regulator support.
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/sched.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/mutex.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include "../../regulator/internal.h"
+
+#define EXYNOS_RGT_PREFIX	"EXYNOS-RGT: "
+
+struct exynos_rgt_info {
+	struct regulator *rgt;
+	struct dentry *reg_dir;
+	struct dentry *f_get;
+	struct dentry *f_ena;
+	struct dentry *f_volt;
+	struct file_operations get_fops;
+	struct file_operations ena_fops;
+	struct file_operations volt_fops;
+};
+
+static struct dentry *exynos_rgt_root;
+static int num_regulators;
+
+static const char *rdev_get_name(struct regulator_dev *rdev)
+{
+	if (rdev->desc->name)
+		return rdev->desc->name;
+	else if (rdev->constraints && rdev->constraints->name)
+		return rdev->constraints->name;
+	else
+		return "";
+}
+
+static ssize_t exynos_rgt_get_read(struct file *file, char __user *user_buf,
+					size_t count, loff_t *ppos)
+{
+	const struct file_operations *ops = file->f_op;
+	struct exynos_rgt_info *rgt_info = container_of(ops, struct exynos_rgt_info, get_fops);
+	struct regulator *cons, *rgt = rgt_info->rgt;
+	const char *dev;
+	char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+	ssize_t len, ret = 0;
+
+	if (!buf)
+		return -ENOMEM;
+
+	len = snprintf(buf + ret, PAGE_SIZE - ret, "[%s]\t open_count %d expected %d\n",
+			rdev_get_name(rgt->rdev),
+			rgt->rdev->open_count,
+			rgt->rdev->constraints->expected_consumer);
+	if (len > 0)
+		ret += len;
+
+	len = snprintf(buf + ret, PAGE_SIZE - ret, "consumer list ->\n");
+	if (len > 0)
+		ret += len;
+
+	list_for_each_entry(cons, &rgt->rdev->consumer_list, list) {
+		if (cons->dev && dev_name(cons->dev))
+			dev = dev_name(cons->dev);
+		else
+			dev = "unknown";
+
+		len = snprintf(buf + ret, PAGE_SIZE - ret, "\t [%s]\n", dev);
+		if (len > 0)
+			ret += len;
+
+		if (ret > PAGE_SIZE) {
+			ret = PAGE_SIZE;
+			break;
+		}
+	}
+	ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
+
+	kfree(buf);
+	return ret;
+}
+
+static ssize_t exynos_rgt_ena_read(struct file *file, char __user *user_buf,
+					size_t count, loff_t *ppos)
+{
+	const struct file_operations *ops = file->f_op;
+	struct exynos_rgt_info *rgt_info = container_of(ops, struct exynos_rgt_info, ena_fops);
+	struct regulator *rgt = rgt_info->rgt;
+	char buf[80];
+	ssize_t ret;
+
+	ret = snprintf(buf, sizeof(buf), "[%s]\t %s (always_on %d, use_count %d)\n",
+			rdev_get_name(rgt->rdev),
+			rgt->rdev->desc->ops->is_enabled(rgt->rdev) ? "enabled " : "disabled",
+			rgt->rdev->constraints->always_on,
+			rgt->rdev->use_count);
+	if (ret < 0)
+		return ret;
+
+	return simple_read_from_buffer(user_buf, count, ppos, buf, ret);
+}
+
+static ssize_t exynos_rgt_ena_write(struct file *file, const char __user *user_buf,
+					size_t count, loff_t *ppos)
+{
+	const struct file_operations *ops = file->f_op;
+	struct exynos_rgt_info *rgt_info = container_of(ops, struct exynos_rgt_info, ena_fops);
+	struct regulator *rgt = rgt_info->rgt;
+	char buf[32];
+	ssize_t len, ret;
+
+	len = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, count);
+	if (len < 0)
+		return len;
+
+	buf[len] = '\0';
+
+	switch (buf[0]) {
+	case '0':
+		ret = regulator_disable(rgt);
+		if (ret)
+			return ret;
+		break;
+	case '1':
+		ret = regulator_enable(rgt);
+		if (ret)
+			return ret;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return len;
+}
+
+static ssize_t exynos_rgt_volt_read(struct file *file, char __user *user_buf,
+					size_t count, loff_t *ppos)
+{
+	const struct file_operations *ops = file->f_op;
+	struct exynos_rgt_info *rgt_info = container_of(ops, struct exynos_rgt_info, volt_fops);
+	struct regulator *cons, *rgt = rgt_info->rgt;
+	struct regulation_constraints *constraints = rgt->rdev->constraints;
+	const char *dev;
+	char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+	ssize_t len, ret = 0;
+
+	if (!buf)
+		return -ENOMEM;
+
+	len = snprintf(buf + ret, PAGE_SIZE - ret, "[%s]\t curr %4d mV\t constraint min %4d mV, max %4d mV\n",
+			rdev_get_name(rgt->rdev),
+			regulator_get_voltage(rgt) / 1000,
+			constraints->min_uV / 1000,
+			constraints->max_uV / 1000);
+	if (len > 0)
+		ret += len;
+
+	len = snprintf(buf + ret, PAGE_SIZE - ret, "consumer list ->\n");
+	if (len > 0)
+		ret += len;
+
+	list_for_each_entry(cons, &rgt->rdev->consumer_list, list) {
+		if (cons->dev && dev_name(cons->dev))
+			dev = dev_name(cons->dev);
+		else
+			dev = "unknown";
+
+		len = snprintf(buf + ret, PAGE_SIZE - ret,
+				"\t [%s]\t min %4d mV, max %4d mV %s\n",
+				dev,
+				cons->min_uV / 1000,
+				cons->max_uV / 1000,
+				cons->min_uV ? "(requested)" : "");
+		if (len > 0)
+			ret += len;
+
+		if (ret > PAGE_SIZE) {
+			ret = PAGE_SIZE;
+			break;
+		}
+	}
+	ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
+
+	kfree(buf);
+	return ret;
+}
+
+static ssize_t exynos_rgt_volt_write(struct file *file, const char __user *user_buf,
+					size_t count, loff_t *ppos)
+{
+	const struct file_operations *ops = file->f_op;
+	struct exynos_rgt_info *rgt_info = container_of(ops, struct exynos_rgt_info, volt_fops);
+	struct regulator *rgt = rgt_info->rgt;
+	int min_mV, min_uV, max_uV = rgt->rdev->constraints->max_uV;
+	char buf[32];
+	ssize_t len, ret;
+
+	len = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, count);
+	if (len < 0)
+		return len;
+
+	buf[len] = '\0';
+
+	ret = kstrtos32(buf, 10, &min_mV);
+	if (ret)
+		return ret;
+
+	min_uV = min_mV * 1000;
+
+	if (min_uV < rgt->rdev->constraints->min_uV || min_uV > max_uV)
+		return -EINVAL;
+
+	ret = regulator_set_voltage(rgt, min_uV, max_uV);
+	if (ret)
+		return ret;
+
+	return len;
+}
+
+static const struct file_operations exynos_rgt_get_fops = {
+	.open = simple_open,
+	.read = exynos_rgt_get_read,
+	.llseek = default_llseek,
+};
+
+static const struct file_operations exynos_rgt_ena_fops = {
+	.open = simple_open,
+	.read = exynos_rgt_ena_read,
+	.write = exynos_rgt_ena_write,
+	.llseek = default_llseek,
+};
+
+static const struct file_operations exynos_rgt_volt_fops = {
+	.open = simple_open,
+	.read = exynos_rgt_volt_read,
+	.write = exynos_rgt_volt_write,
+	.llseek = default_llseek,
+};
+
+static int exynos_rgt_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct exynos_rgt_info *rgt_info;
+	struct device_node *regulators_np, *reg_np;
+	int rgt_idx = 0;
+	const char *rgt_name;
+
+	regulators_np = of_find_node_by_name(NULL, "regulators");
+	if (!regulators_np) {
+		pr_err("%s %s: could not find regulators sub-node\n", EXYNOS_RGT_PREFIX, __func__);
+		ret = -EINVAL;
+		goto err_find_regs;
+	}
+
+	while (regulators_np) {
+		num_regulators += of_get_child_count(regulators_np);
+		regulators_np = of_find_node_by_name(regulators_np, "regulators");
+	}
+
+	rgt_info = kzalloc(sizeof(struct exynos_rgt_info) * num_regulators, GFP_KERNEL);
+	if (!rgt_info) {
+		pr_err("%s %s: could not allocate mem for rgt_info\n", EXYNOS_RGT_PREFIX, __func__);
+		ret = -ENOMEM;
+		goto err_rgt_info;
+	}
+
+	exynos_rgt_root = debugfs_create_dir("exynos-rgt", NULL);
+	if (!exynos_rgt_root) {
+		pr_err("%s %s: could not create debugfs root dir\n",
+				EXYNOS_RGT_PREFIX, __func__);
+		ret = -ENOMEM;
+		goto err_dbgfs_root;
+	}
+
+	regulators_np = of_find_node_by_name(NULL, "regulators");
+	while (regulators_np) {
+		for_each_child_of_node(regulators_np, reg_np) {
+			rgt_name = of_get_property(reg_np, "regulator-name", NULL);
+			if (!rgt_name)
+				continue;
+
+			rgt_info[rgt_idx].rgt = regulator_get(&pdev->dev, rgt_name);
+			if (IS_ERR(rgt_info[rgt_idx].rgt)) {
+				pr_err("%s %s: failed to getting regulator %s\n", EXYNOS_RGT_PREFIX, __func__, rgt_name);
+				continue;
+			}
+
+			rgt_info[rgt_idx].get_fops = exynos_rgt_get_fops;
+			rgt_info[rgt_idx].ena_fops = exynos_rgt_ena_fops;
+			rgt_info[rgt_idx].volt_fops = exynos_rgt_volt_fops;
+			rgt_info[rgt_idx].reg_dir =
+				debugfs_create_dir(rgt_name, exynos_rgt_root);
+			rgt_info[rgt_idx].f_get =
+				debugfs_create_file("get", 0444, rgt_info[rgt_idx].reg_dir, NULL, &rgt_info[rgt_idx].get_fops);
+			rgt_info[rgt_idx].f_ena =
+				debugfs_create_file("enable", 0644, rgt_info[rgt_idx].reg_dir, NULL, &rgt_info[rgt_idx].ena_fops);
+			rgt_info[rgt_idx].f_volt =
+				debugfs_create_file("voltage", 0644, rgt_info[rgt_idx].reg_dir, NULL, &rgt_info[rgt_idx].volt_fops);
+
+			rgt_idx++;
+		}
+		regulators_np = of_find_node_by_name(regulators_np, "regulators");
+	}
+
+	platform_set_drvdata(pdev, rgt_info);
+
+	return 0;
+
+err_dbgfs_root:
+	kfree(rgt_info);
+err_rgt_info:
+err_find_regs:
+	return ret;
+}
+
+static int exynos_rgt_remove(struct platform_device *pdev)
+{
+	struct exynos_rgt_info *rgt_info = platform_get_drvdata(pdev);
+	int i = 0;
+
+	for (i = 0; i < num_regulators; i++) {
+		debugfs_remove_recursive(rgt_info[i].f_volt);
+		debugfs_remove_recursive(rgt_info[i].f_ena);
+		debugfs_remove_recursive(rgt_info[i].f_get);
+		debugfs_remove_recursive(rgt_info[i].reg_dir);
+		regulator_put(rgt_info[i].rgt);
+	}
+
+	debugfs_remove_recursive(exynos_rgt_root);
+	kfree(rgt_info);
+
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static const struct of_device_id exynos_rgt_match[] = {
+	{
+		.compatible = "samsung,exynos-rgt",
+	},
+	{},
+};
+
+static struct platform_driver exynos_rgt_drv = {
+	.probe		= exynos_rgt_probe,
+	.remove		= exynos_rgt_remove,
+	.driver		= {
+		.name	= "exynos_rgt",
+		.owner	= THIS_MODULE,
+		.of_match_table = exynos_rgt_match,
+	},
+};
+
+static int __init exynos_rgt_init(void)
+{
+	return platform_driver_register(&exynos_rgt_drv);
+}
+late_initcall(exynos_rgt_init);

drivers/soc/samsung/exynos-smc.c

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS SMC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/smc.h>
+#include <trace/events/exynos.h>
+
+#define CONFIG_EXYNOS_SMC_LOGGING
+
+#ifdef CONFIG_EXYNOS_SMC_LOGGING
+#define EXYNOS_SMC_LOG_SIZE	1024
+
+struct exynos_smc_log_entry {
+        u64 cpu_clk;
+        u32 cmd;
+	u32 arg1;
+	u32 arg2;
+	u32 arg3;
+};
+
+static DEFINE_SPINLOCK(drm_smc_log_lock);
+
+struct exynos_smc_log_entry drm_smc_log[EXYNOS_SMC_LOG_SIZE];
+
+static unsigned int drm_smc_log_idx;
+#endif
+
+int exynos_smc(unsigned long cmd, unsigned long arg1, unsigned long arg2, unsigned long arg3)
+{
+	int smc_ret;
+#ifdef CONFIG_EXYNOS_SMC_LOGGING
+	unsigned long flags;
+#endif
+
+#ifdef CONFIG_EXYNOS_SMC_LOGGING
+	if ((uint32_t)cmd >= SMC_PROTECTION_SET && (uint32_t)cmd < MC_FC_SET_CFW_PROT) {
+		pr_debug("%s: cmd: 0x%x, arg1: 0x%x, arg2: 0x%x, arg3: 0x%x\n",
+			__func__, (u32)cmd, (u32)arg1, (u32)arg2, (u32)arg3);
+		spin_lock_irqsave(&drm_smc_log_lock, flags);
+		drm_smc_log[drm_smc_log_idx].cpu_clk = local_clock();
+		drm_smc_log[drm_smc_log_idx].cmd = (u32)cmd;
+		drm_smc_log[drm_smc_log_idx].arg1 = (u32)arg1;
+		drm_smc_log[drm_smc_log_idx].arg2 = (u32)arg2;
+		drm_smc_log[drm_smc_log_idx].arg3 = (u32)arg3;
+		drm_smc_log_idx++;
+		if (drm_smc_log_idx == EXYNOS_SMC_LOG_SIZE)
+			drm_smc_log_idx = 0;
+		spin_unlock_irqrestore(&drm_smc_log_lock, flags);
+	}
+#endif
+
+	trace_exynos_smc_in(cmd, arg1, arg2, arg3);
+	smc_ret = __exynos_smc(cmd, arg1, arg2, arg3);
+	trace_exynos_smc_out(cmd, arg1, arg2, arg3);
+
+	return smc_ret;
+}

drivers/soc/samsung/pmu-cp.c

@@ -0,0 +1,456 @@
+#include <linux/io.h>
+#include <linux/cpumask.h>
+#include <linux/suspend.h>
+#include <linux/notifier.h>
+#include <linux/bug.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/regmap.h>
+#include <linux/smc.h>
+#include <linux/shm_ipc.h>
+#include <soc/samsung/exynos-pmu.h>
+#include <soc/samsung/pmu-cp.h>
+
+#if defined(CONFIG_CP_SECURE_BOOT)
+static u32 exynos_smc_read(enum cp_control reg)
+{
+	u32 cp_ctrl;
+	u32 cp_ctrl_low;
+	u32 cp_ctrl_high;
+
+	pr_info("exynos_smc input : 0x%X, 0x%X, 0x%X, 0x%X\n", SMC_ID, READ_CTRL,
+		0, reg);
+	cp_ctrl = exynos_smc(SMC_ID, READ_CTRL, 0, reg);
+	pr_info("exynos_smc output: 0x%X\n", cp_ctrl);
+
+	if (!(cp_ctrl & 0xffff)) {
+		cp_ctrl >>= 16;
+		cp_ctrl_low = cp_ctrl;
+	} else {
+		pr_err("%s: ERR! read Fail: %d\n", __func__, cp_ctrl & 0xffff);
+
+		return -1;
+	}
+
+	pr_info("exynos_smc input : 0x%X, 0x%X, 0x%X, 0x%X\n", SMC_ID, READ_CTRL,
+		1, reg);
+	cp_ctrl = exynos_smc(SMC_ID, READ_CTRL, 1, reg);
+	pr_info("exynos_smc output: 0x%X\n", cp_ctrl);
+
+	if (!(cp_ctrl & 0xffff)) {
+		cp_ctrl >>= 16;
+		cp_ctrl_high = cp_ctrl;
+	} else {
+		pr_err("%s: ERR! read Fail: %d\n", __func__, cp_ctrl & 0xffff);
+
+		return -1;
+	}
+
+	return (cp_ctrl_high << 16) | cp_ctrl_low;
+}
+
+static u32 exynos_smc_write(enum cp_control reg, u32 value)
+{
+	int ret = 0;
+
+	pr_info("exynos_smc input  : 0x%X, 0x%X, 0x%X, 0x%X\n", SMC_ID, WRITE_CTRL,
+		value, reg);
+	ret = exynos_smc(SMC_ID, WRITE_CTRL, value, reg);
+	pr_info("exynos_smc output : 0x%X\n", ret);
+	if (ret > 0) {
+		pr_err("%s: ERR! CP_CTRL Write Fail: %d\n", __func__, ret);
+		return -1;
+	}
+
+	return 0;
+}
+#endif
+
+/* reset cp */
+int exynos_cp_reset(void)
+{
+	int ret = 0;
+	u32 __maybe_unused cp_ctrl;
+
+	pr_info("%s\n", __func__);
+
+	/* set sys_pwr_cfg registers */
+	exynos_sys_powerdown_conf_cp();
+
+#if defined(CONFIG_CP_SECURE_BOOT)
+	/* assert cp_reset */
+	cp_ctrl = exynos_smc_read(CP_CTRL_NS);
+	if (cp_ctrl == -1)
+		return -1;
+
+	ret = exynos_smc_write(CP_CTRL_NS, cp_ctrl | CP_RESET_SET | CP_PWRON);
+	if (ret < 0) {
+		pr_err("%s: ERR! CP Reset Fail: %d\n", __func__, ret);
+		return -1;
+	}
+#else
+	ret = exynos_pmu_read(EXYNOS_PMU_CP_CTRL_NS, &cp_ctrl);
+	cp_ctrl |= CP_RESET_SET | CP_PWRON;
+
+	ret = exynos_pmu_write(EXYNOS_PMU_CP_CTRL_NS, cp_ctrl);
+	if (ret < 0) {
+		pr_err("%s: ERR! CP Reset Fail: %d\n", __func__, ret);
+		return -1;
+	}
+#endif
+
+	/* some delay */
+	cpu_relax();
+	usleep_range(80, 100);
+
+	return ret;
+}
+
+/* release cp */
+int exynos_cp_release(void)
+{
+	u32 cp_ctrl;
+	int ret = 0;
+
+	pr_info("%s\n", __func__);
+
+#if defined(CONFIG_CP_SECURE_BOOT)
+	cp_ctrl = exynos_smc_read(CP_CTRL_S);
+	if (cp_ctrl == -1)
+		return -1;
+
+	ret = exynos_smc_write(CP_CTRL_S, cp_ctrl | CP_START);
+	if (ret < 0)
+		pr_err("ERR! CP Release Fail: %d\n", ret);
+	else
+		pr_info("%s, cp_ctrl[0x%08x] -> [0x%08x]\n", __func__, cp_ctrl,
+			exynos_smc_read(CP_CTRL_S));
+#else
+
+	ret = exynos_pmu_read(EXYNOS_PMU_CP_CTRL_S, &cp_ctrl);
+	cp_ctrl |= CP_START;
+
+	ret = exynos_pmu_write(EXYNOS_PMU_CP_CTRL_S, cp_ctrl);
+	if (ret < 0)
+		pr_err("ERR! CP Release Fail: %d\n", ret);
+	else {
+		exynos_pmu_read(EXYNOS_PMU_CP_CTRL_S, &cp_ctrl);
+		pr_info("%s, PMU_CP_CTRL_S[0x%08x]\n", __func__, cp_ctrl);
+	}
+#endif
+
+	return ret;
+}
+
+/* clear cp active */
+int exynos_cp_active_clear(void)
+{
+	u32 cp_ctrl;
+	int ret = 0;
+
+	pr_info("%s\n", __func__);
+
+#if defined(CONFIG_CP_SECURE_BOOT)
+	cp_ctrl = exynos_smc_read(CP_CTRL_NS);
+	if (cp_ctrl == -1)
+		return -1;
+
+	ret = exynos_smc_write(CP_CTRL_NS, cp_ctrl | CP_ACTIVE_REQ_CLR);
+	if (ret < 0)
+		pr_err("%s: ERR! CP active_clear Fail: %d\n", __func__, ret);
+	else
+		pr_info("%s: cp_ctrl[0x%08x] -> [0x%08x]\n", __func__, cp_ctrl,
+			exynos_smc_read(CP_CTRL_NS));
+#else
+
+	ret = exynos_pmu_read(EXYNOS_PMU_CP_CTRL_NS, &cp_ctrl);
+	cp_ctrl |= CP_ACTIVE_REQ_CLR;
+
+	ret = exynos_pmu_write(EXYNOS_PMU_CP_CTRL_NS, cp_ctrl);
+	if (ret < 0)
+		pr_err("%s: ERR! CP active_clear Fail: %d\n", __func__, ret);
+	else {
+		exynos_pmu_read(EXYNOS_PMU_CP_CTRL_NS, &cp_ctrl);
+		pr_info("%s, PMU_CP_CTRL_NS[0x%08x]\n", __func__, cp_ctrl);
+	}
+#endif
+	return ret;
+}
+
+/* clear cp_reset_req from cp */
+int exynos_clear_cp_reset(void)
+{
+	u32 cp_ctrl;
+	int ret = 0;
+
+	pr_info("%s\n", __func__);
+
+#if defined(CONFIG_CP_SECURE_BOOT)
+	cp_ctrl = exynos_smc_read(CP_CTRL_NS);
+	if (cp_ctrl == -1)
+		return -1;
+
+	ret = exynos_smc_write(CP_CTRL_NS, cp_ctrl | CP_RESET_REQ_CLR);
+	if (ret < 0)
+		pr_err("%s: ERR! CP clear_cp_reset Fail: %d\n", __func__, ret);
+	else
+		pr_info("%s: cp_ctrl[0x%08x] -> [0x%08x]\n", __func__, cp_ctrl,
+			exynos_smc_read(CP_CTRL_NS));
+#else
+
+	ret = exynos_pmu_read(EXYNOS_PMU_CP_CTRL_NS, &cp_ctrl);
+	cp_ctrl |= CP_RESET_REQ_CLR;
+
+	ret = exynos_pmu_write(EXYNOS_PMU_CP_CTRL_NS, cp_ctrl);
+	if (ret < 0)
+		pr_err("%s: ERR! CP clear_cp_reset Fail: %d\n", __func__, ret);
+	else {
+		exynos_pmu_read(EXYNOS_PMU_CP_CTRL_NS, &cp_ctrl);
+		pr_info("%s, PMU_CP_CTRL_NS[0x%08x]\n", __func__, cp_ctrl);
+	}
+#endif
+
+	return ret;
+}
+
+int exynos_get_cp_power_status(void)
+{
+	u32 cp_state;
+
+#if defined(CONFIG_CP_SECURE_BOOT)
+	cp_state = exynos_smc_read(CP_CTRL_NS);
+	if (cp_state == -1)
+		return -1;
+#else
+	exynos_pmu_read(EXYNOS_PMU_CP_CTRL_NS, &cp_state);
+#endif
+
+	if (cp_state & CP_PWRON)
+		return 1;
+	else
+		return 0;
+}
+
+int exynos_cp_init(void)
+{
+	u32 __maybe_unused cp_ctrl;
+	int ret = 0;
+
+	pr_info("%s: cp_ctrl init\n", __func__);
+
+#if defined(CONFIG_CP_SECURE_BOOT)
+	cp_ctrl = exynos_smc_read(CP_CTRL_NS);
+	if (cp_ctrl == -1)
+		return -1;
+
+	ret = exynos_smc_write(CP_CTRL_NS, cp_ctrl & ~CP_RESET_SET & ~CP_PWRON);
+	if (ret < 0)
+		pr_err("%s: ERR! write Fail: %d\n", __func__, ret);
+
+	cp_ctrl = exynos_smc_read(CP_CTRL_S);
+	if (cp_ctrl == -1)
+		return -1;
+
+	ret = exynos_smc_write(CP_CTRL_S, cp_ctrl & ~CP_START);
+	if (ret < 0)
+		pr_err("%s: ERR! write Fail: %d\n", __func__, ret);
+#else
+	exynos_pmu_cp_init();
+
+	ret = exynos_pmu_read(EXYNOS_PMU_CP_CTRL_NS, &cp_ctrl);
+	cp_ctrl &= ~CP_RESET_SET;
+
+	ret = exynos_pmu_write(EXYNOS_PMU_CP_CTRL_NS, cp_ctrl);
+	if (ret < 0)
+		pr_err("%s: ERR! CP_RESET_SET Fail: %d\n", __func__, ret);
+
+	ret = exynos_pmu_read(EXYNOS_PMU_CP_CTRL_NS, &cp_ctrl);
+	cp_ctrl &= ~CP_PWRON;
+
+	ret = exynos_pmu_write(EXYNOS_PMU_CP_CTRL_NS, cp_ctrl);
+	if (ret < 0)
+		pr_err("%s: ERR! CP_PWRON Fail: %d\n", __func__, ret);
+
+	ret = exynos_pmu_read(EXYNOS_PMU_CP_CTRL_NS, &cp_ctrl);
+	cp_ctrl &= ~CP_START;
+
+	ret = exynos_pmu_write(EXYNOS_PMU_CP_CTRL_NS, cp_ctrl);
+	if (ret < 0)
+		pr_err("%s: ERR! CP_START Fail: %d\n", __func__, ret);
+
+	ret = exynos_pmu_read(EXYNOS_PMU_CP_CTRL_S, &cp_ctrl);
+	pr_err("EXYNOS_PMU_CP_CTRL_S: %08X\n", cp_ctrl);
+
+	ret = exynos_pmu_read(EXYNOS_PMU_CP_CTRL_NS, &cp_ctrl);
+	pr_err("EXYNOS_PMU_CP_CTRL_NS: %08X\n", cp_ctrl);
+#endif
+
+	return ret;
+}
+
+int exynos_set_cp_power_onoff(enum cp_mode mode)
+{
+	u32 cp_ctrl;
+	int ret = 0;
+
+	pr_info("%s: mode[%d]\n", __func__, mode);
+
+#if defined(CONFIG_CP_SECURE_BOOT)
+	/* set power on/off */
+	cp_ctrl = exynos_smc_read(CP_CTRL_NS);
+	if (cp_ctrl == -1)
+		return -1;
+
+	if (mode == CP_POWER_ON) {
+		if (!(cp_ctrl & CP_PWRON)) {
+			ret = exynos_smc_write(CP_CTRL_NS, cp_ctrl | CP_PWRON);
+			if (ret < 0)
+				pr_err("%s: ERR! write Fail: %d\n", __func__, ret);
+			else
+				pr_info("%s: CP Power: [0x%08X] -> [0x%08X]\n",
+					__func__, cp_ctrl, exynos_smc_read(CP_CTRL_NS));
+		}
+		cp_ctrl = exynos_smc_read(CP_CTRL_S);
+		if (cp_ctrl == -1)
+			return -1;
+
+		ret = exynos_smc_write(CP_CTRL_S, cp_ctrl | CP_START);
+		if (ret < 0)
+			pr_err("%s: ERR! write Fail: %d\n", __func__, ret);
+		else
+			pr_info("%s: CP Start: [0x%08X] -> [0x%08X]\n", __func__,
+				cp_ctrl, exynos_smc_read(CP_CTRL_S));
+	} else {
+		/* set sys_pwr_cfg registers */
+		exynos_sys_powerdown_conf_cp();
+
+		ret = exynos_smc_write(CP_CTRL_NS, cp_ctrl | CP_RESET_SET | CP_PWRON);
+		if (ret < 0)
+			pr_err("ERR! write Fail: %d\n", ret);
+		else
+			pr_info("%s: CP Power Down: [0x%08X] -> [0x%08X]\n", __func__,
+				cp_ctrl, exynos_smc_read(CP_CTRL_NS));
+	}
+#else
+	exynos_pmu_read(EXYNOS_PMU_CP_CTRL_NS, &cp_ctrl);
+	if (mode == CP_POWER_ON) {
+		if (!(cp_ctrl & CP_PWRON)) {
+			ret = exynos_pmu_read(EXYNOS_PMU_CP_CTRL_NS, &cp_ctrl);
+			cp_ctrl |= CP_PWRON;
+
+			ret = exynos_pmu_write(EXYNOS_PMU_CP_CTRL_NS, cp_ctrl);
+			if (ret < 0)
+				pr_err("%s: ERR! write Fail: %d\n",
+						__func__, ret);
+		}
+
+		ret = exynos_pmu_read(EXYNOS_PMU_CP_CTRL_S, &cp_ctrl);
+		cp_ctrl |= CP_START;
+
+		ret = exynos_pmu_write(EXYNOS_PMU_CP_CTRL_S, cp_ctrl);
+		if (ret < 0)
+			pr_err("%s: ERR! write Fail: %d\n", __func__, ret);
+	} else {
+		/* set sys_pwr_cfg registers */
+		exynos_sys_powerdown_conf_cp();
+
+		ret = exynos_pmu_read(EXYNOS_PMU_CP_CTRL_NS, &cp_ctrl);
+		cp_ctrl |= CP_RESET_SET | CP_PWRON;
+
+		ret = exynos_pmu_write(EXYNOS_PMU_CP_CTRL_NS, cp_ctrl);
+		if (ret < 0)
+			pr_err("ERR! write Fail: %d\n", ret);
+	}
+#endif
+	return ret;
+}
+
+void exynos_sys_powerdown_conf_cp(void)
+{
+	pr_info("%s\n", __func__);
+
+	exynos_pmu_write(EXYNOS_PMU_RESET_AHEAD_CP_SYS_PWR_REG, 0);
+	exynos_pmu_write(EXYNOS_PMU_LOGIC_RESET_CP_SYS_PWR_REG, 0);
+	exynos_pmu_write(EXYNOS_PMU_RESET_ASB_CP_SYS_PWR_REG, 0);
+	exynos_pmu_write(EXYNOS_PMU_TCXO_GATE_SYS_PWR_REG, 0);
+	exynos_pmu_write(EXYNOS_PMU_CLEANY_BUS_SYS_PWR_REG, 0);
+	exynos_pmu_write(EXYNOS_PMU_CENTRAL_SEQ_CP_CONFIGURATION, 0);
+}
+
+#if !defined(CONFIG_CP_SECURE_BOOT)
+static void __init set_shdmem_size(unsigned memsz)
+{
+	u32 tmp;
+	pr_info("[Modem_IF]Set shared mem size: %dMB\n", memsz);
+
+#if defined(CONFIG_SOC_EXYNOS7570)
+	memsz *= 256;
+#else
+	memsz /= 4;
+#endif
+	exynos_pmu_write(EXYNOS_PMU_CP2AP_MEM_CONFIG, memsz);
+
+	exynos_pmu_read(EXYNOS_PMU_CP2AP_MEM_CONFIG, &tmp);
+	pr_info("[Modem_IF] EXYNOS_PMU_CP2AP_MEM_CONFIG: 0x%x\n", tmp);
+
+#if defined(CONFIG_SOC_EXYNOS7570)
+	exynos_pmu_write(EXYNOS_PMU_CP2AP_ADDR_RNG, memsz);
+
+	exynos_pmu_read(EXYNOS_PMU_CP2AP_ADDR_RNG, &tmp);
+	pr_info("[Modem_IF] EXYNOS_PMU_CP2AP_ADDR_RNG: 0x%x\n", tmp);
+#endif
+}
+
+static void __init set_shdmem_base(unsigned long base)
+{
+	u32 tmp, base_addr;
+	pr_info("[Modem_IF]Set shared mem baseaddr : 0x%x\n", (unsigned int)base);
+
+#if defined(CONFIG_SOC_EXYNOS7570)
+	base_addr = (base >> 12);
+#else
+	base_addr = (base >> 22);
+#endif
+	exynos_pmu_write(EXYNOS_PMU_CP2AP_MIF_CONFIG1, base_addr);
+	exynos_pmu_write(EXYNOS_PMU_CP2AP_MIF_CONFIG2, base_addr);
+
+	exynos_pmu_read(EXYNOS_PMU_CP2AP_MIF_CONFIG1, &tmp);
+	pr_info("[Modem_IF] EXYNOS_PMU_CP2AP_MIF_CONFIG1: 0x%x\n", tmp);
+
+	exynos_pmu_read(EXYNOS_PMU_CP2AP_MIF_CONFIG2, &tmp);
+	pr_info("[Modem_IF] EXYNOS_PMU_CP2AP_MIF_CONFIG2: 0x%x\n", tmp);
+}
+
+static void set_batcher(void)
+{
+	exynos_pmu_write(EXYNOS_PMU_MODAPIF_CONFIG, 0x3);
+}
+#endif
+
+int exynos_pmu_cp_init(void)
+{
+
+#if !defined(CONFIG_CP_SECURE_BOOT)
+	unsigned shm_size;
+	unsigned long shm_base;
+
+	shm_size = shm_get_phys_size();
+	shm_base = shm_get_phys_base();
+
+	/* Change size from byte to Mega byte*/
+	shm_size /= 1048510;
+
+	set_shdmem_size(shm_size);
+	set_shdmem_base(shm_base);
+	set_batcher();
+
+	/* set access window for CP */
+	exynos_pmu_write(EXYNOS_PMU_CP2AP_MIF_ACCESS_WIN0, 0xffffffff);
+	exynos_pmu_write(EXYNOS_PMU_CP2AP_MIF_ACCESS_WIN1, 0xffffffff);
+	exynos_pmu_write(EXYNOS_PMU_CP2AP_MIF_ACCESS_WIN2, 0xffffffff);
+	exynos_pmu_write(EXYNOS_PMU_CP2AP_MIF_ACCESS_WIN3, 0xffffffff);
+	exynos_pmu_write(EXYNOS_PMU_CP2AP_PERI_ACCESS_WIN, 0xffffffff);
+#endif
+
+	return 0;
+}

drivers/soc/samsung/pwrcal/Makefile

@@ -0,0 +1,39 @@
+# arch/arm/mach-exynos/pwrcal/Makefile
+#
+# Copyright (c) 2014-2014 Samsung Electronics Co., Ltd.
+#		http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+
+obj-y				+= power-cal.o pwrcal-cmu.o pwrcal-pll.o pwrcal-dfs.o \
+				pwrcal-pmu.o pwrcal-rae.o pwrcal-vclk.o pwrcal-dbg.o
+obj-$(CONFIG_PMUCAL_MOD)	+= pmucal_mod/pmucal_system.o pmucal_mod/pmucal_local.o \
+				   pmucal_mod/pmucal_cpu.o pmucal_mod/pmucal_rae.o
+
+ifeq ($(CONFIG_SOC_EXYNOS8890), y)
+ifeq ($(CONFIG_SOC_EXYNOS8890_EVT1), y)
+obj-y				+= S5E8890/S5E8890-cmu.o S5E8890/S5E8890-pmu.o \
+				S5E8890/S5E8890-dfs.o S5E8890/S5E8890-asv.o \
+				S5E8890/S5E8890-syspwr.o S5E8890/S5E8890-vclk.o \
+				S5E8890/S5E8890-drampara.o S5E8890/S5E8890-pll.o \
+				S5E8890/S5E8890-rae.o
+else
+obj-y				+= S5E8890_EVT0/S5E8890-cmu.o S5E8890_EVT0/S5E8890-pmu.o \
+				S5E8890_EVT0/S5E8890-dfs.o S5E8890_EVT0/S5E8890-asv.o \
+				S5E8890_EVT0/S5E8890-syspwr.o S5E8890_EVT0/S5E8890-vclk.o \
+				S5E8890_EVT0/S5E8890-drampara.o S5E8890_EVT0/S5E8890-pll.o \
+				S5E8890_EVT0/S5E8890-rae.o
+endif
+endif
+obj-$(CONFIG_SOC_EXYNOS7870)	+= S5E7870/S5E7870-cmu.o S5E7870/S5E7870-pmu.o \
+				S5E7870/S5E7870-dfs.o S5E7870/S5E7870-asv.o \
+				S5E7870/S5E7870-syspwr.o S5E7870/S5E7870-vclk.o \
+				S5E7870/S5E7870-drampara.o S5E7870/S5E7870-pll.o \
+				S5E7870/S5E7870-rae.o \
+
+obj-$(CONFIG_SOC_EXYNOS7570)	+= S5E7570/S5E7570-cmu.o \
+				S5E7570/S5E7570-dfs.o S5E7570/S5E7570-asv.o \
+				S5E7570/S5E7570-vclk.o \
+				S5E7570/S5E7570-drampara.o S5E7570/S5E7570-pll.o \
+				S5E7570/S5E7570-rae.o \

drivers/soc/samsung/pwrcal/S5E7570/S5E7570-cmu.h

@@ -0,0 +1,810 @@
+#ifndef __EXYNOS7570_CMU_H__
+#define __EXYNOS7570_CMU_H__
+
+#include "../pwrcal-clk.h"
+
+enum clk_id {
+	OSCCLK = fixed_rate_type,
+	OSCCLK_FM_52M,
+	CLK_MIF_DDRPHY0,
+	TCXO, /*52MHZ*/
+	WIFI2AP_USBPLL_CLK,
+	CLKPHY_FSYS_USB20DRD_PHYCLOCK,
+	CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS,
+	CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0,
+	CLKIO_DISPAUD_MIXER_BCLK_CP,
+	CLKPHY_ISP_S_RXBYTECLKHS0_S4,
+	NUM_OF_FIXED_RATE_TYPE = CLKPHY_ISP_S_RXBYTECLKHS0_S4 - fixed_rate_type + 1,
+
+	MIF_FF_SHARED0_PLL_DIV2 = fixed_factor_type,
+	MIF_FF_SHARED1_PLL_DIV2,
+	MIF_FF_SHARED2_PLL_DIV2,
+	NUM_OF_FIXED_FACTOR_TYPE = MIF_FF_SHARED2_PLL_DIV2 - fixed_factor_type + 1,
+
+	CPUCL0_PLL = pll_type,
+	SHARED0_PLL,
+	SHARED1_PLL,
+	SHARED2_PLL,
+	AUD_PLL,
+	WPLL_USB_PLL,
+	NUM_OF_PLL_TYPE = WPLL_USB_PLL - pll_type + 1,
+
+	CPUCL0_MUX_CPUCL0_PLL = mux_type,
+	CPUCL0_MUX_CLK_CPUCL0,
+	DISPAUD_MUX_AUD_PLL,
+	MIF_MUX_SHARED0_PLL,
+	MIF_MUX_SHARED1_PLL,
+	MIF_MUX_SHARED2_PLL,
+	MIF_MUX_CLK_MIF_PHY_CLK,
+	MIF_MUX_CLK_MIF_PHY_CLK_A,
+	MIF_MUX_CLK_MIF_PHY_CLK_B,
+	MIF_MUX_CLK_MIF_BUSD,
+	MIF_MUX_CLKCMU_G3D,
+	MIF_MUX_CLKCMU_ISP_VRA,
+	MIF_MUX_CLKCMU_ISP_CAM,
+	MIF_MUX_CLKCMU_DISPAUD_BUS,
+	MIF_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK,
+	MIF_MUX_CLKCMU_MFCMSCL_MSCL,
+	MIF_MUX_CLKCMU_MFCMSCL_MFC,
+	MIF_MUX_CLKCMU_FSYS_BUS,
+	MIF_MUX_CLKCMU_FSYS_MMC0,
+	MIF_MUX_CLKCMU_FSYS_MMC2,
+	MIF_MUX_CLKCMU_FSYS_USB20DRD_REFCLK,
+	MIF_MUX_CLKCMU_PERI_BUS,
+	MIF_MUX_CLKCMU_PERI_UART_DEBUG,
+	MIF_MUX_CLKCMU_PERI_UART_SENSOR,
+	MIF_MUX_CLKCMU_PERI_SPI_REARFROM,
+	MIF_MUX_CLKCMU_PERI_SPI_ESE,
+	MIF_MUX_CLKCMU_PERI_USI_0,
+	MIF_MUX_CLKCMU_PERI_USI_1,
+	MIF_MUX_CLKCMU_APM,
+	MIF_MUX_CLKCMU_ISP_SENSOR0,
+
+	/* user_mux_type */
+	APM_MUX_CLKCMU_APM_USER  = MIF_MUX_CLKCMU_ISP_SENSOR0 + 0x1001,
+	CPUCL0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
+	DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER,
+	DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER,
+	DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER,
+	DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER,
+	DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER,
+	FSYS_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER,
+	G3D_MUX_CLKCMU_G3D_USER,
+	ISP_MUX_CLKCMU_ISP_VRA_USER,
+	ISP_MUX_CLKCMU_ISP_CAM_USER,
+	ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER,
+	MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER,
+	MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER,
+	NUM_OF_MUX_TYPE = MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER - 0x1000 - mux_type + 1,
+
+	CPUCL0_DIV_CLK_CPUCL0_1 = div_type,
+	CPUCL0_DIV_CLK_CPUCL0_2,
+	CPUCL0_DIV_CLK_CPUCL0_ACLK,
+	CPUCL0_DIV_CLK_CPUCL0_PCLK,
+	CPUCL0_DIV_CLK_CPUCL0_ATCLK,
+	CPUCL0_DIV_CLK_CPUCL0_PCLKDBG,
+	CPUCL0_DIV_CLK_CPUCL0_CNTCLK,
+	CPUCL0_DIV_CLK_CPUCL0_RUN_MONITOR,
+	CPUCL0_DIV_CLK_CPUCL0_HPM,
+	CPUCL0_DIV_CLK_CPUCL0_PLL,
+	DISPAUD_DIV_CLK_DISPAUD_APB,
+	DISPAUD_DIV_CLK_DISPAUD_DECON_INT_VCLK,
+	DISPAUD_DIV_CLK_DISPAUD_DECON_INT_ECLK,
+	DISPAUD_DIV_CLK_DISPAUD_MI2S,
+	DISPAUD_DIV_CLK_DISPAUD_MIXER,
+	DISPAUD_DIV_CLK_DISPAUD_OSCCLK_FM_52M_DIV,
+	G3D_DIV_CLK_G3D_BUS,
+	G3D_DIV_CLK_G3D_APB,
+	ISP_DIV_CLK_ISP_CAM_HALF,
+	MFCMSCL_DIV_CLK_MFCMSCL_APB,
+	MIF_DIV_CLK_MIF_PHY_CLK2X,
+	MIF_DIV_CLK_MIF_PHY_CLKM,
+	MIF_DIV_CLKCMU_CP_SHARED0_PLL,
+	MIF_DIV_CLKCMU_CP_SHARED1_PLL,
+	MIF_DIV_CLKCMU_CP_SHARED2_PLL,
+	MIF_DIV_CLK_MIF_BUSD,
+	MIF_DIV_CLK_MIF_APB,
+	MIF_DIV_CLKCMU_CPUCL0_SWITCH,
+	MIF_DIV_CLKCMU_G3D,
+	MIF_DIV_CLKCMU_ISP_VRA,
+	MIF_DIV_CLKCMU_ISP_CAM,
+	MIF_DIV_CLKCMU_DISPAUD_BUS,
+	MIF_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK,
+	MIF_DIV_CLKCMU_MFCMSCL_MSCL,
+	MIF_DIV_CLKCMU_MFCMSCL_MFC,
+	MIF_DIV_CLKCMU_FSYS_BUS,
+	MIF_DIV_CLKCMU_FSYS_MMC0,
+	MIF_DIV_CLKCMU_FSYS_MMC2,
+	MIF_DIV_CLKCMU_FSYS_USB20DRD_REFCLK,
+	MIF_DIV_CLKCMU_PERI_BUS,
+	MIF_DIV_CLKCMU_PERI_UART_DEBUG,
+	MIF_DIV_CLKCMU_PERI_UART_SENSOR,
+	MIF_DIV_CLKCMU_PERI_SPI_REARFROM,
+	MIF_DIV_CLKCMU_PERI_SPI_ESE,
+	MIF_DIV_CLKCMU_PERI_USI_0,
+	MIF_DIV_CLKCMU_PERI_USI_1,
+	MIF_DIV_CLKCMU_APM,
+	MIF_DIV_CLKCMU_ISP_SENSOR0,
+	MIF_DIV_CLKCMU_GNSS_EXTPLL_SCAN,
+	PERI_DIV_CLK_PERI_USI_0_SPI,
+	PERI_DIV_CLK_PERI_USI_1_SPI,
+	NUM_OF_DIV_TYPE = PERI_DIV_CLK_PERI_USI_1_SPI - div_type + 1,
+
+	APM_GATE_CLK_APM_UID_APM_IPCLKPORT_ACLK_SYS = gate_type,
+	APM_GATE_CLK_APM_UID_APM_IPCLKPORT_ACLK_CPU,
+	APM_GATE_CLK_APM_UID_ASYNCS_APM_IPCLKPORT_I_CLK,
+	APM_GATE_CLK_APM_UID_ASYNCM_APM_IPCLKPORT_I_CLK,
+	CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_CLK,
+	CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_CLK__PMU_CPUCL0,
+	CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_D_CPUCL0_IPCLKPORT_I_CLK,
+	CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK,
+	CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_PCLK,
+	CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_PCLK,
+	CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK,
+	CPUCL0_GATE_CLK_CPUCL0_UID_BUSP1_CPUCL0_IPCLKPORT_ACLK,
+	CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CPUCL0_IPCLKPORT_I_CLK,
+	CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_ATCLK,
+	CPUCL0_GATE_CLK_CPUCL0_UID_SECJTAG_IPCLKPORT_i_clk,
+	CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLKDBG,
+	CPUCL0_GATE_CLK_CPUCL0_UID_DBG_MUX_CPUCL0_IPCLKPORT_I_CLK,
+	CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG,
+	CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_CSSYS_DBG_IPCLKPORT_PCLKS,
+	CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_T_CSSYS_DBG_IPCLKPORT_ACLK,
+	CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CSSYS_DBG_IPCLKPORT_PCLKM,
+	CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_I_HPM_TARGETCLK_C,
+	DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK,
+	DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU,
+	DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP,
+	DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_VPP,
+	DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS,
+	DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_FM,
+	DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP,
+	DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD,
+	DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP,
+	DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB,
+	DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_APB_SECURE_SMMU_DISP,
+	DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK,
+	DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_TXBYTECLKHS,
+	DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_RXCLKESC0,
+	DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI,
+	DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI,
+	DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK,
+	DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK,
+	DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK_FM_52M,
+	DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK_FM_52M_DIV,
+	FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_CLK,
+	FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_CLK__PMU_FSYS,
+	FSYS_GATE_CLK_FSYS_UID_BUSD1_FSYS_IPCLKPORT_ACLK,
+	FSYS_GATE_CLK_FSYS_UID_BUSD0_FSYS_IPCLKPORT_ACLK,
+	FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HCLK_USB20_CTRL,
+	FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_HSDRD,
+	FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK,
+	FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK,
+	FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK,
+	FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_PCLK,
+	FSYS_GATE_CLK_FSYS_UID_ASYNCS_D_FSYS_IPCLKPORT_I_CLK,
+	FSYS_GATE_CLK_FSYS_UID_ASYNCM_P_FSYS_IPCLKPORT_I_CLK,
+	FSYS_GATE_CLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK,
+	FSYS_GATE_CLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK,
+	FSYS_GATE_CLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK,
+	FSYS_GATE_CLK_FSYS_UID_BR_BUSP1_FSYS_IPCLKPORT_aclk,
+	FSYS_GATE_CLK_FSYS_UID_BUSP5_FSYS_IPCLKPORT_HCLK,
+	FSYS_GATE_CLK_FSYS_UID_BUSP3_FSYS_IPCLKPORT_HCLK,
+	FSYS_GATE_CLK_FSYS_UID_BUSP2_FSYS_IPCLKPORT_HCLK,
+	FSYS_GATE_CLK_FSYS_UID_BUSP1_FSYS_IPCLKPORT_HCLK,
+	FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_PCLK,
+	FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_ACLK,
+	FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_PCLK,
+	FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_ACLK,
+	FSYS_GATE_CLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN,
+	FSYS_GATE_CLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
+	FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_ref_clk,
+	FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_PHYCLOCK,
+	FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_USB20_CLKCORE_0,
+	G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_CLK,
+	G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_CLK__PMU_G3D,
+	G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_ACLK,
+	G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK,
+	G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK,
+	G3D_GATE_CLK_G3D_UID_REGSLICE_D1_G3D_IPCLKPORT_aclk,
+	G3D_GATE_CLK_G3D_UID_REGSLICE_D0_G3D_IPCLKPORT_aclk,
+	G3D_GATE_CLK_G3D_UID_IXIU_D_G3D_IPCLKPORT_ACLK,
+	G3D_GATE_CLK_G3D_UID_ASYNCS_D1_G3D_IPCLKPORT_I_CLK,
+	G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK,
+	G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM,
+	G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK,
+	G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_PCLK,
+	G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK,
+	G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_PCLK,
+	G3D_GATE_CLK_G3D_UID_BUSP_G3D_IPCLKPORT_ACLK,
+	G3D_GATE_CLK_G3D_UID_ASYNCM_P_G3D_IPCLKPORT_I_CLK,
+	G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKS,
+	G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_ACLK,
+	G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_PCLK,
+	ISP_GATE_CLK_ISP_UID_CLK_ISP_OSCCLK,
+	ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA,
+	ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM,
+	ISP_GATE_CLK_ISP_UID_CLKPHY_ISP_S_RXBYTECLKHS0_S4,
+	MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_OSCCLK,
+	MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI,
+	MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_D,
+	MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_JPEG,
+	MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_POLY,
+	MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_MFC,
+	MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_APB,
+	MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_APB_SMMU_MSCL,
+	MIF_GATE_CLK_MIF_UID_OTP_DESERIAL_MIF_IPCLKPORT_I_CLK,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_RCLK,
+	MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_I_OSC_SYS,
+	MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_CLK,
+	MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_CLK__PMU_MIF_JV,
+	MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clk,
+	MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clkm,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_APB_ACLK,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SECURE_APB_ACLK,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PEREV_CLK,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_WR_CLK,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_RD_CLK,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_CLK,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_SLICE1_CLK,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_SLICE0_CLK,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_CLK,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_WR_CLK,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_RD_CLK,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_CLK,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_ACLK,
+	MIF_GATE_CLK_MIF_UID_PPMU_CPU_IPCLKPORT_ACLK,
+	MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_ACLK,
+	MIF_GATE_CLK_MIF_UID_ASYNCM_CPUCL0_IPCLKPORT_ACLK,
+	MIF_GATE_CLK_MIF_UID_ASYNCM_DBG_IPCLKPORT_ACLK,
+	MIF_GATE_CLK_MIF_UID_PDMA_MIF_IPCLKPORT_ACLK_PDMA0,
+	MIF_GATE_CLK_MIF_UID_CLEANY_WLBT_IPCLKPORT_ACLK,
+	MIF_GATE_CLK_MIF_UID_CLEANY_GNSS_IPCLKPORT_ACLK,
+	MIF_GATE_CLK_MIF_UID_CLEANY_CEL_IPCLKPORT_ACLK,
+	MIF_GATE_CLK_MIF_UID_CPU0_MO_MON_IPCLKPORT_I_ACLK,
+	MIF_GATE_CLK_MIF_UID_PPMU_CPU_IPCLKPORT_PCLK,
+	MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_SPEEDY,
+	MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_CP,
+	MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_AP,
+	MIF_GATE_CLK_MIF_UID_SPEEDY_MIF_IPCLKPORT_PCLK,
+	MIF_GATE_CLK_MIF_UID_MAILBOX_WLBT_IPCLKPORT_CLK,
+	MIF_GATE_CLK_MIF_UID_MAILBOX_GNSS_IPCLKPORT_CLK,
+	MIF_GATE_CLK_MIF_UID_MAILBOX_CEL_IPCLKPORT_CLK,
+	MIF_GATE_CLK_MIF_UID_ASYNCAPB_MIF_CSSYS_IPCLKPORT_PCLKS,
+	MIF_GATE_CLK_MIF_UID_SYNC_INTC_SOC_IPCLKPORT_CLK,
+	MIF_GATE_CLK_MIF_UID_INTC_SOC_IPCLKPORT_CLK,
+	MIF_GATE_CLK_MIF_UID_AXI2APB_MIF_TREX_IPCLKPORT_ACLK,
+	MIF_GATE_CLK_MIF_UID_AXI2AHB_MIF_P_IPCLKPORT_HCLK,
+	MIF_GATE_CLK_MIF_UID_AHB2APB_MIF2_IPCLKPORT_HCLK,
+	MIF_GATE_CLK_MIF_UID_AHB2APB_MIF1_IPCLKPORT_HCLK,
+	MIF_GATE_CLK_MIF_UID_AHB2APB_MIF0_IPCLKPORT_HCLK,
+	MIF_GATE_CLK_MIF_UID_AHB_BRIDGE_MIF_IPCLKPORT_HCLK,
+	MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_PCLK,
+	MIF_GATE_CLK_MIF_UID_DDRDMC0_APB_IPCLKPORT_PCLK,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK,
+	MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_PCLK,
+	MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1,
+	MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0,
+	MIF_GATE_CLK_MIF_UID_GPIO_MIF_IPCLKPORT_PCLK,
+	MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK,
+	MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_PCLK,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF_SECURE,
+	MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_SECURE,
+	MIF_GATE_CLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_CLK,
+	MIF_GATE_CLKCMU_CP_SHARED0_PLL,
+	MIF_GATE_CLKCMU_CP_SHARED1_PLL,
+	MIF_GATE_CLKCMU_CP_SHARED2_PLL,
+	MIF_GATE_CLKCMU_CPUCL0_SWITCH,
+	MIF_GATE_CLKCMU_G3D,
+	MIF_GATE_CLKCMU_ISP_VRA,
+	MIF_GATE_CLKCMU_ISP_CAM,
+	MIF_GATE_CLKCMU_DISPAUD_BUS,
+	MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK,
+	MIF_GATE_CLKCMU_MFCMSCL_MFC,
+	MIF_GATE_CLKCMU_MFCMSCL_MSCL,
+	MIF_GATE_CLKCMU_FSYS_BUS,
+	MIF_GATE_CLKCMU_FSYS_MMC0,
+	MIF_GATE_CLKCMU_FSYS_MMC2,
+	MIF_GATE_CLKCMU_FSYS_USB20DRD_REFCLK,
+	MIF_GATE_CLKCMU_PERI_BUS,
+	MIF_GATE_CLKCMU_PERI_UART_DEBUG,
+	MIF_GATE_CLKCMU_PERI_UART_SENSOR,
+	MIF_GATE_CLKCMU_PERI_SPI_REARFROM,
+	MIF_GATE_CLKCMU_PERI_SPI_ESE,
+	MIF_GATE_CLKCMU_PERI_USI_0,
+	MIF_GATE_CLKCMU_PERI_USI_1,
+	MIF_GATE_CLKCMU_APM,
+	MIF_GATE_CLKCMU_ISP_SENSOR0,
+	MIF_GATE_CLKCMU_GNSS_TEST_EXTPLL_SCAN_CLK,
+	MIF_GATE_CLK_MIF_UID_SPEEDY_MIF_IPCLKPORT_CLK,
+	PERI_GATE_CLK_PERI_UID_TMU_CPUCL0_IPCLKPORT_I_CLK,
+	PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_CLK,
+	PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_OSCCLK,
+	PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_CLK__PMU_PERI,
+	PERI_GATE_CLK_PERI_UID_CHIPID_IPCLKPORT_CLK,
+	PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0,
+	PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_PCLK,
+	PERI_GATE_CLK_PERI_UID_MCT_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_I2C_SENSOR2_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_I2C_SENSOR1_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_I2C_TSP_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_I2C_FUELGAUGE_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_I2C_NFC_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_I2C_MUIC_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_HSI2C_FRONTCAM_IPCLKPORT_iPCLK,
+	PERI_GATE_CLK_PERI_UID_HSI2C_MAINCAM_IPCLKPORT_iPCLK,
+	PERI_GATE_CLK_PERI_UID_HSI2C_FRONTSENSOR_IPCLKPORT_iPCLK,
+	PERI_GATE_CLK_PERI_UID_HSI2C_REARAF_IPCLKPORT_iPCLK,
+	PERI_GATE_CLK_PERI_UID_HSI2C_REARSENSOR_IPCLKPORT_iPCLK,
+	PERI_GATE_CLK_PERI_UID_GPIO_TOUCH_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_GPIO_TOP_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_GPIO_NFC_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_GPIO_ESE_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_BUSP1_PERIS1_IPCLKPORT_HCLK,
+	PERI_GATE_CLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK,
+	PERI_GATE_CLK_PERI_UID_BUSP1_PERIC1_IPCLKPORT_HCLK,
+	PERI_GATE_CLK_PERI_UID_BUSP1_PERIC0_IPCLKPORT_HCLK,
+	PERI_GATE_CLK_PERI_UID_BUSP_BR_PERIC_IPCLKPORT_HCLK,
+	PERI_GATE_CLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_aclk,
+	PERI_GATE_CLK_PERI_UID_ASYNCM_PERI_IPCLKPORT_I_CLK,
+	PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_PCLK,
+	PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_PCLK,
+	PERI_GATE_CLK_PERI_UID_WDT_CPUCL0_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL0_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_SFRIF_GPIO_ALIVE_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_TZPC10_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_TZPC9_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_TZPC8_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_TZPC7_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_TZPC6_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_TZPC5_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_TZPC4_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_TZPC3_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_TZPC2_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_TZPC1_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_TZPC0_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_SFRIF_CHIPID_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_SFRIF_RTC_ALIVE_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_SFRIF_RTC_TOP_IPCLKPORT_PCLK,
+	PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_EXT_UCLK,
+	PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_EXT_UCLK,
+	PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_SPI_EXT_CLK,
+	PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_SPI_EXT_CLK,
+	PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_SCLK_UART,
+	PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_SCLK_UART,
+	PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_SCLK_SPI,
+	PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_SCLK_SPI,
+	MIF_MUXGATE_CLKCMU_ISP_VRA,
+	MIF_MUXGATE_CLKCMU_ISP_CAM,
+	MIF_MUXGATE_CLKCMU_DISPAUD_BUS,
+	MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_VCLK,
+	MIF_MUXGATE_CLKCMU_MFCMSCL_MSCL,
+	MIF_MUXGATE_CLKCMU_MFCMSCL_MFC,
+	MIF_MUXGATE_CLKCMU_FSYS_BUS,
+	MIF_MUXGATE_CLKCMU_FSYS_MMC0,
+	MIF_MUXGATE_CLKCMU_FSYS_MMC2,
+	MIF_MUXGATE_CLKCMU_FSYS_USB20DRD_REFCLK,
+	MIF_MUXGATE_CLKCMU_PERI_BUS,
+	MIF_MUXGATE_CLKCMU_PERI_UART_DEBUG,
+	MIF_MUXGATE_CLKCMU_PERI_UART_SENSOR,
+	MIF_MUXGATE_CLKCMU_PERI_SPI_REARFROM,
+	MIF_MUXGATE_CLKCMU_PERI_SPI_ESE,
+	MIF_MUXGATE_CLKCMU_PERI_USI_0,
+	MIF_MUXGATE_CLKCMU_PERI_USI_1,
+	MIF_MUXGATE_CLKCMU_APM,
+	MIF_MUXGATE_CLKCMU_ISP_SENSOR0,
+	PMU_DEBUG_CLKOUT_SEL08,
+	PMU_DEBUG_CLKOUT_SEL09,
+	PMU_DEBUG_CLKOUT_SEL10,
+	PMU_DEBUG_CLKOUT_SEL11,
+	PMU_DEBUG_CLKOUT_SEL12,
+	PMU_DEBUG_CLKOUT_DISABLE,
+	NUM_OF_GATE_TYPE = PMU_DEBUG_CLKOUT_DISABLE - gate_type + 1,
+
+};
+
+FIXEDRATE_EXTERN(OSCCLK)
+FIXEDRATE_EXTERN(OSCCLK_FM_52M)
+FIXEDRATE_EXTERN(CLK_MIF_DDRPHY0)
+FIXEDRATE_EXTERN(TCXO)
+FIXEDRATE_EXTERN(WIFI2AP_USBPLL_CLK)
+FIXEDRATE_EXTERN(CLKPHY_FSYS_USB20DRD_PHYCLOCK)
+FIXEDRATE_EXTERN(CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS)
+FIXEDRATE_EXTERN(CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0)
+FIXEDRATE_EXTERN(CLKIO_DISPAUD_MIXER_BCLK_CP)
+FIXEDRATE_EXTERN(CLKPHY_ISP_S_RXBYTECLKHS0_S4)
+
+FIXEDFACTOR_EXTERN(MIF_FF_SHARED0_PLL_DIV2)
+FIXEDFACTOR_EXTERN(MIF_FF_SHARED1_PLL_DIV2)
+FIXEDFACTOR_EXTERN(MIF_FF_SHARED2_PLL_DIV2)
+
+PLL_EXTERN(CPUCL0_PLL)
+PLL_EXTERN(SHARED0_PLL)
+PLL_EXTERN(SHARED1_PLL)
+PLL_EXTERN(SHARED2_PLL)
+PLL_EXTERN(AUD_PLL)
+PLL_EXTERN(WPLL_USB_PLL)
+
+DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_1)
+DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_2)
+DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_ACLK)
+DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_PCLK)
+DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_ATCLK)
+DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_PCLKDBG)
+DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_CNTCLK)
+DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_RUN_MONITOR)
+DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_HPM)
+DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_PLL)
+DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_APB)
+DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_DECON_INT_VCLK)
+DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_DECON_INT_ECLK)
+DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_MI2S)
+DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_MIXER)
+DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_OSCCLK_FM_52M_DIV)
+DIV_EXTERN(G3D_DIV_CLK_G3D_BUS)
+DIV_EXTERN(G3D_DIV_CLK_G3D_APB)
+DIV_EXTERN(ISP_DIV_CLK_ISP_CAM_HALF)
+DIV_EXTERN(MFCMSCL_DIV_CLK_MFCMSCL_APB)
+DIV_EXTERN(MIF_DIV_CLK_MIF_PHY_CLK2X)
+DIV_EXTERN(MIF_DIV_CLK_MIF_PHY_CLKM)
+DIV_EXTERN(MIF_DIV_CLKCMU_CP_SHARED0_PLL)
+DIV_EXTERN(MIF_DIV_CLKCMU_CP_SHARED1_PLL)
+DIV_EXTERN(MIF_DIV_CLKCMU_CP_SHARED2_PLL)
+DIV_EXTERN(MIF_DIV_CLK_MIF_BUSD)
+DIV_EXTERN(MIF_DIV_CLK_MIF_APB)
+DIV_EXTERN(MIF_DIV_CLKCMU_CPUCL0_SWITCH)
+DIV_EXTERN(MIF_DIV_CLKCMU_G3D)
+DIV_EXTERN(MIF_DIV_CLKCMU_ISP_VRA)
+DIV_EXTERN(MIF_DIV_CLKCMU_ISP_CAM)
+DIV_EXTERN(MIF_DIV_CLKCMU_DISPAUD_BUS)
+DIV_EXTERN(MIF_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK)
+DIV_EXTERN(MIF_DIV_CLKCMU_MFCMSCL_MSCL)
+DIV_EXTERN(MIF_DIV_CLKCMU_MFCMSCL_MFC)
+DIV_EXTERN(MIF_DIV_CLKCMU_FSYS_BUS)
+DIV_EXTERN(MIF_DIV_CLKCMU_FSYS_MMC0)
+DIV_EXTERN(MIF_DIV_CLKCMU_FSYS_MMC2)
+DIV_EXTERN(MIF_DIV_CLKCMU_FSYS_USB20DRD_REFCLK)
+DIV_EXTERN(MIF_DIV_CLKCMU_PERI_BUS)
+DIV_EXTERN(MIF_DIV_CLKCMU_PERI_UART_DEBUG)
+DIV_EXTERN(MIF_DIV_CLKCMU_PERI_UART_SENSOR)
+DIV_EXTERN(MIF_DIV_CLKCMU_PERI_SPI_REARFROM)
+DIV_EXTERN(MIF_DIV_CLKCMU_PERI_SPI_ESE)
+DIV_EXTERN(MIF_DIV_CLKCMU_PERI_USI_0)
+DIV_EXTERN(MIF_DIV_CLKCMU_PERI_USI_1)
+DIV_EXTERN(MIF_DIV_CLKCMU_APM)
+DIV_EXTERN(MIF_DIV_CLKCMU_ISP_SENSOR0)
+DIV_EXTERN(MIF_DIV_CLKCMU_GNSS_EXTPLL_SCAN)
+DIV_EXTERN(PERI_DIV_CLK_PERI_USI_0_SPI)
+DIV_EXTERN(PERI_DIV_CLK_PERI_USI_1_SPI)
+
+MUX_EXTERN(APM_MUX_CLKCMU_APM_USER)
+MUX_EXTERN(CPUCL0_MUX_CPUCL0_PLL)
+MUX_EXTERN(CPUCL0_MUX_CLKCMU_CPUCL0_SWITCH_USER)
+MUX_EXTERN(CPUCL0_MUX_CLK_CPUCL0)
+MUX_EXTERN(DISPAUD_MUX_AUD_PLL)
+MUX_EXTERN(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER)
+MUX_EXTERN(DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER)
+MUX_EXTERN(DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER)
+MUX_EXTERN(DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER)
+MUX_EXTERN(DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER)
+MUX_EXTERN(FSYS_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER)
+MUX_EXTERN(G3D_MUX_CLKCMU_G3D_USER)
+MUX_EXTERN(ISP_MUX_CLKCMU_ISP_VRA_USER)
+MUX_EXTERN(ISP_MUX_CLKCMU_ISP_CAM_USER)
+MUX_EXTERN(ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER)
+MUX_EXTERN(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER)
+MUX_EXTERN(MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER)
+MUX_EXTERN(MIF_MUX_SHARED0_PLL)
+MUX_EXTERN(MIF_MUX_SHARED1_PLL)
+MUX_EXTERN(MIF_MUX_SHARED2_PLL)
+MUX_EXTERN(MIF_MUX_CLK_MIF_PHY_CLK)
+MUX_EXTERN(MIF_MUX_CLK_MIF_PHY_CLK_A)
+MUX_EXTERN(MIF_MUX_CLK_MIF_PHY_CLK_B)
+MUX_EXTERN(MIF_MUX_CLK_MIF_BUSD)
+MUX_EXTERN(MIF_MUX_CLKCMU_G3D)
+MUX_EXTERN(MIF_MUX_CLKCMU_ISP_VRA)
+MUX_EXTERN(MIF_MUX_CLKCMU_ISP_CAM)
+MUX_EXTERN(MIF_MUX_CLKCMU_DISPAUD_BUS)
+MUX_EXTERN(MIF_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK)
+MUX_EXTERN(MIF_MUX_CLKCMU_MFCMSCL_MSCL)
+MUX_EXTERN(MIF_MUX_CLKCMU_MFCMSCL_MFC)
+MUX_EXTERN(MIF_MUX_CLKCMU_FSYS_BUS)
+MUX_EXTERN(MIF_MUX_CLKCMU_FSYS_MMC0)
+MUX_EXTERN(MIF_MUX_CLKCMU_FSYS_MMC2)
+MUX_EXTERN(MIF_MUX_CLKCMU_FSYS_USB20DRD_REFCLK)
+MUX_EXTERN(MIF_MUX_CLKCMU_PERI_BUS)
+MUX_EXTERN(MIF_MUX_CLKCMU_PERI_UART_DEBUG)
+MUX_EXTERN(MIF_MUX_CLKCMU_PERI_UART_SENSOR)
+MUX_EXTERN(MIF_MUX_CLKCMU_PERI_SPI_REARFROM)
+MUX_EXTERN(MIF_MUX_CLKCMU_PERI_SPI_ESE)
+MUX_EXTERN(MIF_MUX_CLKCMU_PERI_USI_0)
+MUX_EXTERN(MIF_MUX_CLKCMU_PERI_USI_1)
+MUX_EXTERN(MIF_MUX_CLKCMU_APM)
+MUX_EXTERN(MIF_MUX_CLKCMU_ISP_SENSOR0)
+
+GATE_EXTERN(APM_GATE_CLK_APM_UID_APM_IPCLKPORT_ACLK_SYS)
+GATE_EXTERN(APM_GATE_CLK_APM_UID_APM_IPCLKPORT_ACLK_CPU)
+GATE_EXTERN(APM_GATE_CLK_APM_UID_ASYNCS_APM_IPCLKPORT_I_CLK)
+GATE_EXTERN(APM_GATE_CLK_APM_UID_ASYNCM_APM_IPCLKPORT_I_CLK)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_CLK)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_CLK__PMU_CPUCL0)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_D_CPUCL0_IPCLKPORT_I_CLK)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_PCLK)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_PCLK)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_BUSP1_CPUCL0_IPCLKPORT_ACLK)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CPUCL0_IPCLKPORT_I_CLK)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_ATCLK)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_SECJTAG_IPCLKPORT_i_clk)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLKDBG)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_DBG_MUX_CPUCL0_IPCLKPORT_I_CLK)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_CSSYS_DBG_IPCLKPORT_PCLKS)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_T_CSSYS_DBG_IPCLKPORT_ACLK)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CSSYS_DBG_IPCLKPORT_PCLKM)
+GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_I_HPM_TARGETCLK_C)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_VPP)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_FM)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_APB_SECURE_SMMU_DISP)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_TXBYTECLKHS)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_RXCLKESC0)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK_FM_52M)
+GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK_FM_52M_DIV)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_CLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_CLK__PMU_FSYS)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSD1_FSYS_IPCLKPORT_ACLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSD0_FSYS_IPCLKPORT_ACLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HCLK_USB20_CTRL)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_HSDRD)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_PCLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_ASYNCS_D_FSYS_IPCLKPORT_I_CLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_ASYNCM_P_FSYS_IPCLKPORT_I_CLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BR_BUSP1_FSYS_IPCLKPORT_aclk)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSP5_FSYS_IPCLKPORT_HCLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSP3_FSYS_IPCLKPORT_HCLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSP2_FSYS_IPCLKPORT_HCLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSP1_FSYS_IPCLKPORT_HCLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_PCLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_ACLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_PCLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_ACLK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_ref_clk)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_PHYCLOCK)
+GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_USB20_CLKCORE_0)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_CLK)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_CLK__PMU_G3D)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_ACLK)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_REGSLICE_D1_G3D_IPCLKPORT_aclk)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_REGSLICE_D0_G3D_IPCLKPORT_aclk)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_IXIU_D_G3D_IPCLKPORT_ACLK)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_ASYNCS_D1_G3D_IPCLKPORT_I_CLK)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_PCLK)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_PCLK)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_BUSP_G3D_IPCLKPORT_ACLK)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_ASYNCM_P_G3D_IPCLKPORT_I_CLK)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKS)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_ACLK)
+GATE_EXTERN(G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_PCLK)
+GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLK_ISP_OSCCLK)
+GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA)
+GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM)
+GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLKPHY_ISP_S_RXBYTECLKHS0_S4)
+GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_OSCCLK)
+GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI)
+GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_D)
+GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_JPEG)
+GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_POLY)
+GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_MFC)
+GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_APB)
+GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_APB_SMMU_MSCL)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_OTP_DESERIAL_MIF_IPCLKPORT_I_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_RCLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_I_OSC_SYS)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_CLK__PMU_MIF_JV)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clk)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clkm)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_APB_ACLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SECURE_APB_ACLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PEREV_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_WR_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_RD_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_SLICE1_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_SLICE0_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_WR_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_RD_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_ACLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PPMU_CPU_IPCLKPORT_ACLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_ACLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCM_CPUCL0_IPCLKPORT_ACLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCM_DBG_IPCLKPORT_ACLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PDMA_MIF_IPCLKPORT_ACLK_PDMA0)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_CLEANY_WLBT_IPCLKPORT_ACLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_CLEANY_GNSS_IPCLKPORT_ACLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_CLEANY_CEL_IPCLKPORT_ACLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_CPU0_MO_MON_IPCLKPORT_I_ACLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PPMU_CPU_IPCLKPORT_PCLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_SPEEDY)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_CP)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_AP)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SPEEDY_MIF_IPCLKPORT_PCLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MAILBOX_WLBT_IPCLKPORT_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MAILBOX_GNSS_IPCLKPORT_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MAILBOX_CEL_IPCLKPORT_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCAPB_MIF_CSSYS_IPCLKPORT_PCLKS)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SYNC_INTC_SOC_IPCLKPORT_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_INTC_SOC_IPCLKPORT_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AXI2APB_MIF_TREX_IPCLKPORT_ACLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AXI2AHB_MIF_P_IPCLKPORT_HCLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AHB2APB_MIF2_IPCLKPORT_HCLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AHB2APB_MIF1_IPCLKPORT_HCLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AHB2APB_MIF0_IPCLKPORT_HCLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AHB_BRIDGE_MIF_IPCLKPORT_HCLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_PCLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DDRDMC0_APB_IPCLKPORT_PCLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_PCLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_GPIO_MIF_IPCLKPORT_PCLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_PCLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF_SECURE)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_SECURE)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_CLK)
+GATE_EXTERN(MIF_GATE_CLKCMU_CP_SHARED0_PLL)
+GATE_EXTERN(MIF_GATE_CLKCMU_CP_SHARED1_PLL)
+GATE_EXTERN(MIF_GATE_CLKCMU_CP_SHARED2_PLL)
+GATE_EXTERN(MIF_GATE_CLKCMU_CPUCL0_SWITCH)
+GATE_EXTERN(MIF_GATE_CLKCMU_G3D)
+GATE_EXTERN(MIF_GATE_CLKCMU_ISP_VRA)
+GATE_EXTERN(MIF_GATE_CLKCMU_ISP_CAM)
+GATE_EXTERN(MIF_GATE_CLKCMU_DISPAUD_BUS)
+GATE_EXTERN(MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK)
+GATE_EXTERN(MIF_GATE_CLKCMU_MFCMSCL_MFC)
+GATE_EXTERN(MIF_GATE_CLKCMU_MFCMSCL_MSCL)
+GATE_EXTERN(MIF_GATE_CLKCMU_FSYS_BUS)
+GATE_EXTERN(MIF_GATE_CLKCMU_FSYS_MMC0)
+GATE_EXTERN(MIF_GATE_CLKCMU_FSYS_MMC2)
+GATE_EXTERN(MIF_GATE_CLKCMU_FSYS_USB20DRD_REFCLK)
+GATE_EXTERN(MIF_GATE_CLKCMU_PERI_BUS)
+GATE_EXTERN(MIF_GATE_CLKCMU_PERI_UART_DEBUG)
+GATE_EXTERN(MIF_GATE_CLKCMU_PERI_UART_SENSOR)
+GATE_EXTERN(MIF_GATE_CLKCMU_PERI_SPI_REARFROM)
+GATE_EXTERN(MIF_GATE_CLKCMU_PERI_SPI_ESE)
+GATE_EXTERN(MIF_GATE_CLKCMU_PERI_USI_0)
+GATE_EXTERN(MIF_GATE_CLKCMU_PERI_USI_1)
+GATE_EXTERN(MIF_GATE_CLKCMU_APM)
+GATE_EXTERN(MIF_GATE_CLKCMU_ISP_SENSOR0)
+GATE_EXTERN(MIF_GATE_CLKCMU_GNSS_TEST_EXTPLL_SCAN_CLK)
+GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SPEEDY_MIF_IPCLKPORT_CLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TMU_CPUCL0_IPCLKPORT_I_CLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_CLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_OSCCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_CLK__PMU_PERI)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_CHIPID_IPCLKPORT_CLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_MCT_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_SENSOR2_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_SENSOR1_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_TSP_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_FUELGAUGE_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_NFC_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_MUIC_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTCAM_IPCLKPORT_iPCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_HSI2C_MAINCAM_IPCLKPORT_iPCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTSENSOR_IPCLKPORT_iPCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_HSI2C_REARAF_IPCLKPORT_iPCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_HSI2C_REARSENSOR_IPCLKPORT_iPCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_GPIO_TOUCH_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_GPIO_TOP_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_GPIO_NFC_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_GPIO_ESE_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_BUSP1_PERIS1_IPCLKPORT_HCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC1_IPCLKPORT_HCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC0_IPCLKPORT_HCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_BUSP_BR_PERIC_IPCLKPORT_HCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_aclk)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_ASYNCM_PERI_IPCLKPORT_I_CLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_WDT_CPUCL0_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL0_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_GPIO_ALIVE_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC10_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC9_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC8_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC7_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC6_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC5_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC4_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC3_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC2_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC1_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC0_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_CHIPID_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_RTC_ALIVE_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_RTC_TOP_IPCLKPORT_PCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_EXT_UCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_EXT_UCLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_SPI_EXT_CLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_SPI_EXT_CLK)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_SCLK_UART)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_SCLK_UART)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_SCLK_SPI)
+GATE_EXTERN(PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_SCLK_SPI)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_ISP_VRA)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_ISP_CAM)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_DISPAUD_BUS)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_VCLK)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_MFCMSCL_MSCL)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_MFCMSCL_MFC)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_FSYS_BUS)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_FSYS_MMC0)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_FSYS_MMC2)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_FSYS_USB20DRD_REFCLK)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_BUS)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_UART_DEBUG)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_UART_SENSOR)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_SPI_REARFROM)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_SPI_ESE)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_USI_0)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_USI_1)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_APM)
+GATE_EXTERN(MIF_MUXGATE_CLKCMU_ISP_SENSOR0)
+
+GATE_EXTERN(PMU_DEBUG_CLKOUT_SEL08)
+GATE_EXTERN(PMU_DEBUG_CLKOUT_SEL09)
+GATE_EXTERN(PMU_DEBUG_CLKOUT_SEL10)
+GATE_EXTERN(PMU_DEBUG_CLKOUT_SEL11)
+GATE_EXTERN(PMU_DEBUG_CLKOUT_SEL12)
+GATE_EXTERN(PMU_DEBUG_CLKOUT_DISABLE)
+
+#endif

drivers/soc/samsung/pwrcal/S5E7570/S5E7570-cmusfr.h

@@ -0,0 +1,403 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd. All rights reserved.
+ *		http://www.samsung.com
+ *
+ * Chip Abstraction Layer for local/system power down support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __EXYNOS7570_CMUSFR_H__
+#define __EXYNOS7570_CMUSFR_H__
+
+#include "S5E7570-sfrbase.h"
+
+#define CLK_CON_MUX_CLKCMU_APM_USER	((void *)(CMU_APM_BASE + 0x0200))
+#define CLK_STAT_MUX_CLKCMU_APM_USER	((void *)(CMU_APM_BASE + 0x0600))
+#define CLK_ENABLE_CLKCMU_APM_USER	((void *)(CMU_APM_BASE + 0x080C))
+#define CLKOUT_CMU_APM	((void *)(CMU_APM_BASE + 0x0D00))
+#define CLKOUT_CMU_APM_DIV_STAT	((void *)(CMU_APM_BASE + 0x0D04))
+#define CMU_APM_SPARE0	((void *)(CMU_APM_BASE + 0x0D08))
+#define CMU_APM_SPARE1	((void *)(CMU_APM_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_APM	((void *)(CMU_APM_BASE + 0x0E00))
+#define APM_SFR_IGNORE_REQ_SYSCLK	((void *)(CMU_APM_BASE + 0x0F00))
+
+#define CPUCL0_PLL_LOCK	((void *)(CMU_CPUCL0_BASE + 0x0000))
+#define CPUCL0_PLL_CON0	((void *)(CMU_CPUCL0_BASE + 0x0100))
+#define CPUCL0_PLL_CON1	((void *)(CMU_CPUCL0_BASE + 0x0104))
+#define CLK_CON_MUX_CPUCL0_PLL	((void *)(CMU_CPUCL0_BASE + 0x0200))
+#define CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_USER	((void *)(CMU_CPUCL0_BASE + 0x0204))
+#define CLK_CON_MUX_CLK_CPUCL0	((void *)(CMU_CPUCL0_BASE + 0x0208))
+#define CLK_CON_DIV_CLK_CPUCL0_1	((void *)(CMU_CPUCL0_BASE + 0x0400))
+#define CLK_CON_DIV_CLK_CPUCL0_2	((void *)(CMU_CPUCL0_BASE + 0x0404))
+#define CLK_CON_DIV_CLK_CPUCL0_ACLK	((void *)(CMU_CPUCL0_BASE + 0x0408))
+#define CLK_CON_DIV_CLK_CPUCL0_PCLK	((void *)(CMU_CPUCL0_BASE + 0x040C))
+#define CLK_CON_DIV_CLK_CPUCL0_ATCLK	((void *)(CMU_CPUCL0_BASE + 0x0410))
+#define CLK_CON_DIV_CLK_CPUCL0_PCLKDBG	((void *)(CMU_CPUCL0_BASE + 0x0414))
+#define CLK_CON_DIV_CLK_CPUCL0_CNTCLK	((void *)(CMU_CPUCL0_BASE + 0x0418))
+#define CLK_CON_DIV_CLK_CPUCL0_RUN_MONITOR	((void *)(CMU_CPUCL0_BASE + 0x041C))
+#define CLK_CON_DIV_CLK_CPUCL0_HPM	((void *)(CMU_CPUCL0_BASE + 0x0420))
+#define CLK_CON_DIV_CLK_CPUCL0_PLL	((void *)(CMU_CPUCL0_BASE + 0x0424))
+#define CLK_STAT_MUX_CPUCL0_PLL	((void *)(CMU_CPUCL0_BASE + 0x0600))
+#define CLK_STAT_MUX_CLKCMU_CPUCL0_SWITCH_USER	((void *)(CMU_CPUCL0_BASE + 0x0604))
+#define CLK_STAT_MUX_CLK_CPUCL0	((void *)(CMU_CPUCL0_BASE + 0x0608))
+#define CLK_ENABLE_CLK_CPUCL0_OSCCLK	((void *)(CMU_CPUCL0_BASE + 0x0800))
+#define CLK_ENABLE_CLK_CPUCL0_ACLK	((void *)(CMU_CPUCL0_BASE + 0x0808))
+#define CLK_ENABLE_CLK_CPUCL0_PCLK	((void *)(CMU_CPUCL0_BASE + 0x080C))
+#define CLK_ENABLE_CLK_CPUCL0_ATCLK	((void *)(CMU_CPUCL0_BASE + 0x0810))
+#define CLK_ENABLE_CLK_CPUCL0_PCLKDBG	((void *)(CMU_CPUCL0_BASE + 0x0814))
+#define CLK_ENABLE_CLK_CPUCL0_HPM	((void *)(CMU_CPUCL0_BASE + 0x0820))
+#define CLKOUT_CMU_CPUCL0	((void *)(CMU_CPUCL0_BASE + 0x0D00))
+#define CLKOUT_CMU_CPUCL0_DIV_STAT	((void *)(CMU_CPUCL0_BASE + 0x0D04))
+#define CMU_CPUCL0_SPARE0	((void *)(CMU_CPUCL0_BASE + 0x0D08))
+#define CMU_CPUCL0_SPARE1	((void *)(CMU_CPUCL0_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_CPUCL0	((void *)(CMU_CPUCL0_BASE + 0x0E00))
+#define CPUCL0_SFR_IGNORE_REQ_SYSCLK	((void *)(CMU_CPUCL0_BASE + 0x0F00))
+#define ARMCLK_STOPCTRL	((void *)(CMU_CPUCL0_BASE + 0x1000))
+#define PWR_CTRL	((void *)(CMU_CPUCL0_BASE + 0x1020))
+#define PWR_CTRL2	((void *)(CMU_CPUCL0_BASE + 0x1024))
+#define PWR_CTRL3	((void *)(CMU_CPUCL0_BASE + 0x1028))
+#define INTR_SPREAD_ENABLE	((void *)(CMU_CPUCL0_BASE + 0x1080))
+#define INTR_SPREAD_USE_STANDBYWFI	((void *)(CMU_CPUCL0_BASE + 0x1084))
+#define INTR_SPREAD_BLOCKING_DURATION	((void *)(CMU_CPUCL0_BASE + 0x1088))
+
+#define AUD_PLL_LOCK	((void *)(CMU_DISPAUD_BASE + 0x00C0))
+#define AUD_PLL_CON0	((void *)(CMU_DISPAUD_BASE + 0x01C0))
+#define AUD_PLL_CON1	((void *)(CMU_DISPAUD_BASE + 0x01C4))
+#define AUD_PLL_CON2	((void *)(CMU_DISPAUD_BASE + 0x01C8))
+#define CLK_CON_MUX_AUD_PLL	((void *)(CMU_DISPAUD_BASE + 0x0204))
+#define CLK_CON_MUX_CLKCMU_DISPAUD_BUS_USER	((void *)(CMU_DISPAUD_BASE + 0x0210))
+#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER	((void *)(CMU_DISPAUD_BASE + 0x0214))
+#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER	((void *)(CMU_DISPAUD_BASE + 0x0218))
+#define CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER	((void *)(CMU_DISPAUD_BASE + 0x0224))
+#define CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER	((void *)(CMU_DISPAUD_BASE + 0x0228))
+#define CLK_CON_DIV_CLK_DISPAUD_APB	((void *)(CMU_DISPAUD_BASE + 0x0400))
+#define CLK_CON_DIV_CLK_DISPAUD_DECON_INT_VCLK	((void *)(CMU_DISPAUD_BASE + 0x0404))
+#define CLK_CON_DIV_CLK_DISPAUD_DECON_INT_ECLK	((void *)(CMU_DISPAUD_BASE + 0x0408))
+#define CLK_CON_DIV_CLK_DISPAUD_MI2S	((void *)(CMU_DISPAUD_BASE + 0x040C))
+#define CLK_CON_DIV_CLK_DISPAUD_MIXER	((void *)(CMU_DISPAUD_BASE + 0x0410))
+#define CLK_CON_DIV_CLK_DISPAUD_OSCCLK_FM_52M_DIV	((void *)(CMU_DISPAUD_BASE + 0x0414))
+#define CLK_STAT_MUX_AUD_PLL	((void *)(CMU_DISPAUD_BASE + 0x0604))
+#define CLK_STAT_MUX_CLKCMU_DISPAUD_BUS_USER	((void *)(CMU_DISPAUD_BASE + 0x0610))
+#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER	((void *)(CMU_DISPAUD_BASE + 0x0614))
+#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER	((void *)(CMU_DISPAUD_BASE + 0x0618))
+#define CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER	((void *)(CMU_DISPAUD_BASE + 0x0624))
+#define CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER	((void *)(CMU_DISPAUD_BASE + 0x0628))
+#define CLK_ENABLE_CLK_DISPAUD_OSCCLK	((void *)(CMU_DISPAUD_BASE + 0x0800))
+#define CLK_ENABLE_CLK_DISPAUD_BUS	((void *)(CMU_DISPAUD_BASE + 0x0810))
+#define CLK_ENABLE_CLK_DISPAUD_APB	((void *)(CMU_DISPAUD_BASE + 0x0814))
+#define CLK_ENABLE_CLK_DISPAUD_APB_SECURE_SMMU_DISP	((void *)(CMU_DISPAUD_BASE + 0x0818))
+#define SECURE_ENABLE_SMMU_DISP	((void *)(CMU_DISPAUD_BASE + 0x081C))
+#define CLK_ENABLE_CLK_DISPAUD_DECON_INT_VCLK	((void *)(CMU_DISPAUD_BASE + 0x0820))
+#define CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS	((void *)(CMU_DISPAUD_BASE + 0x0824))
+#define CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0	((void *)(CMU_DISPAUD_BASE + 0x0828))
+#define CLK_ENABLE_CLK_DISPAUD_MI2S	((void *)(CMU_DISPAUD_BASE + 0x082C))
+#define CLK_ENABLE_CLK_DISPAUD_MIXER	((void *)(CMU_DISPAUD_BASE + 0x0830))
+#define CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_CP	((void *)(CMU_DISPAUD_BASE + 0x083C))
+#define CLK_ENABLE_CLK_OSCCLK_FM_52M	((void *)(CMU_DISPAUD_BASE + 0x0844))
+#define CLK_ENABLE_CLK_OSCCLK_FM_52M_DIV	((void *)(CMU_DISPAUD_BASE + 0x0848))
+#define CLKOUT_CMU_DISPAUD	((void *)(CMU_DISPAUD_BASE + 0x0D00))
+#define CLKOUT_CMU_DISPAUD_DIV_STAT	((void *)(CMU_DISPAUD_BASE + 0x0D04))
+#define CMU_DISPAUD_SPARE0	((void *)(CMU_DISPAUD_BASE + 0x0D08))
+#define CMU_DISPAUD_SPARE1	((void *)(CMU_DISPAUD_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_DISPAUD	((void *)(CMU_DISPAUD_BASE + 0x0E00))
+#define DISPAUD_SFR_IGNORE_REQ_SYSCLK	((void *)(CMU_DISPAUD_BASE + 0x0F00))
+
+#define CLK_CON_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER	((void *)(CMU_FSYS_BASE + 0x0230))
+#define CLK_STAT_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER	((void *)(CMU_FSYS_BASE + 0x0630))
+#define CLK_ENABLE_CLK_FSYS_OSCCLK	((void *)(CMU_FSYS_BASE + 0x0800))
+#define CLK_ENABLE_CLK_FSYS_BUS	((void *)(CMU_FSYS_BASE + 0x0804))
+#define CLK_ENABLE_CLK_FSYS_SECURE_RTIC	((void *)(CMU_FSYS_BASE + 0x0808))
+#define CLK_ENABLE_CLK_FSYS_SECURE_SSS	((void *)(CMU_FSYS_BASE + 0x080C))
+#define CLK_ENABLE_CLK_FSYS_MMC_EMBD	((void *)(CMU_FSYS_BASE + 0x0814))
+#define CLK_ENABLE_CLK_FSYS_MMC_CARD	((void *)(CMU_FSYS_BASE + 0x081C))
+#define CLK_ENABLE_CLK_FSYS_USB20DRD_REFCLK	((void *)(CMU_FSYS_BASE + 0x0828))
+#define CLK_ENABLE_CLKPHY_FSYS_USB20DRD_PHYCLOCK	((void *)(CMU_FSYS_BASE + 0x0830))
+#define CLK_ENABLE_CLK_FSYS_USB20PHY_CLKCORE	((void *)(CMU_FSYS_BASE + 0x083C))
+#define SECURE_ENABLE_BUSD0_FSYS	((void *)(CMU_FSYS_BASE + 0x08D0))
+#define CLKOUT_CMU_FSYS	((void *)(CMU_FSYS_BASE + 0x0D00))
+#define CLKOUT_CMU_FSYS_DIV_STAT	((void *)(CMU_FSYS_BASE + 0x0D04))
+#define CMU_FSYS_SPARE0	((void *)(CMU_FSYS_BASE + 0x0D08))
+#define CMU_FSYS_SPARE1	((void *)(CMU_FSYS_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_FSYS	((void *)(CMU_FSYS_BASE + 0x0E00))
+#define FSYS_SFR_IGNORE_REQ_SYSCLK	((void *)(CMU_FSYS_BASE + 0x0F00))
+#define USBPLL_CON0	((void *)(CMU_FSYS_BASE + 0x1000))
+#define USBPLL_CON1	((void *)(CMU_FSYS_BASE + 0x1004))
+
+#define CLK_CON_MUX_CLKCMU_G3D_USER	((void *)(CMU_G3D_BASE + 0x0204))
+#define CLK_CON_DIV_CLK_G3D_BUS	((void *)(CMU_G3D_BASE + 0x0400))
+#define CLK_CON_DIV_CLK_G3D_APB	((void *)(CMU_G3D_BASE + 0x0404))
+#define CLK_STAT_MUX_CLKCMU_G3D_USER	((void *)(CMU_G3D_BASE + 0x0604))
+#define CLK_ENABLE_CLK_G3D_OSCCLK	((void *)(CMU_G3D_BASE + 0x0800))
+#define CLK_ENABLE_CLK_G3D_BUS	((void *)(CMU_G3D_BASE + 0x0804))
+#define CLK_ENABLE_CLK_G3D_APB	((void *)(CMU_G3D_BASE + 0x0808))
+#define CLK_ENABLE_CLK_G3D_BUS_SECURE_CFW_G3D	((void *)(CMU_G3D_BASE + 0x0810))
+#define CLK_ENABLE_CLK_G3D_APB_SECURE_CFW_G3D	((void *)(CMU_G3D_BASE + 0x0814))
+#define CLKOUT_CMU_G3D	((void *)(CMU_G3D_BASE + 0x0D00))
+#define CLKOUT_CMU_G3D_DIV_STAT	((void *)(CMU_G3D_BASE + 0x0D04))
+#define CMU_G3D_SPARE0	((void *)(CMU_G3D_BASE + 0x0D08))
+#define CMU_G3D_SPARE1	((void *)(CMU_G3D_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_G3D	((void *)(CMU_G3D_BASE + 0x0E00))
+#define G3D_SFR_IGNORE_REQ_SYSCLK	((void *)(CMU_G3D_BASE + 0x0F00))
+#define CLK_STOPCTRL	((void *)(CMU_G3D_BASE + 0x1000))
+
+#define CLK_CON_MUX_CLKCMU_ISP_VRA_USER	((void *)(CMU_ISP_BASE + 0x0210))
+#define CLK_CON_MUX_CLKCMU_ISP_CAM_USER	((void *)(CMU_ISP_BASE + 0x0214))
+#define CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER	((void *)(CMU_ISP_BASE + 0x0230))
+#define CLK_CON_DIV_CLK_ISP_CAM_HALF	((void *)(CMU_ISP_BASE + 0x0404))
+#define CLK_STAT_MUX_CLKCMU_ISP_VRA_USER	((void *)(CMU_ISP_BASE + 0x0610))
+#define CLK_STAT_MUX_CLKCMU_ISP_CAM_USER	((void *)(CMU_ISP_BASE + 0x0614))
+#define CLK_STAT_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER	((void *)(CMU_ISP_BASE + 0x0630))
+#define CLK_ENABLE_CLK_ISP_OSCCLK	((void *)(CMU_ISP_BASE + 0x0800))
+#define CLK_ENABLE_CLK_ISP_VRA	((void *)(CMU_ISP_BASE + 0x0810))
+#define CLK_ENABLE_CLK_ISP_CAM	((void *)(CMU_ISP_BASE + 0x081C))
+#define CLK_ENABLE_CLKPHY_ISP_S_RXBYTECLKHS0_S4	((void *)(CMU_ISP_BASE + 0x0828))
+#define CLKOUT_CMU_ISP	((void *)(CMU_ISP_BASE + 0x0D00))
+#define CLKOUT_CMU_ISP_DIV_STAT	((void *)(CMU_ISP_BASE + 0x0D04))
+#define CMU_ISP_SPARE0	((void *)(CMU_ISP_BASE + 0x0D08))
+#define CMU_ISP_SPARE1	((void *)(CMU_ISP_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_ISP	((void *)(CMU_ISP_BASE + 0x0E00))
+#define ISP_SFR_IGNORE_REQ_SYSCLK	((void *)(CMU_ISP_BASE + 0x0F00))
+
+#define CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL_USER	((void *)(CMU_MFCMSCL_BASE + 0x0200))
+#define CLK_CON_MUX_CLKCMU_MFCMSCL_MFC_USER	((void *)(CMU_MFCMSCL_BASE + 0x0204))
+#define CLK_CON_DIV_CLK_MFCMSCL_APB	((void *)(CMU_MFCMSCL_BASE + 0x0400))
+#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MSCL_USER	((void *)(CMU_MFCMSCL_BASE + 0x0600))
+#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MFC_USER	((void *)(CMU_MFCMSCL_BASE + 0x0604))
+#define CLK_ENABLE_CLK_MFCMSCL_OSCCLK	((void *)(CMU_MFCMSCL_BASE + 0x0800))
+#define CLK_ENABLE_CLK_MFCMSCL_MSCL	((void *)(CMU_MFCMSCL_BASE + 0x0804))
+#define CLK_ENABLE_CLK_MFCMSCL_MFC	((void *)(CMU_MFCMSCL_BASE + 0x0808))
+#define CLK_ENABLE_CLK_MFCMSCL_APB	((void *)(CMU_MFCMSCL_BASE + 0x080C))
+#define CLK_ENABLE_CLK_MFCMSCL_APB_SMMU_MSCL	((void *)(CMU_MFCMSCL_BASE + 0x0810))
+#define SECURE_ENABLE_SMMU_MSCL	((void *)(CMU_MFCMSCL_BASE + 0x0814))
+#define CLKOUT_CMU_MFCMSCL	((void *)(CMU_MFCMSCL_BASE + 0x0D00))
+#define CLKOUT_CMU_MFCMSCL_DIV_STAT	((void *)(CMU_MFCMSCL_BASE + 0x0D04))
+#define CMU_MFCMSCL_SPARE0	((void *)(CMU_MFCMSCL_BASE + 0x0D08))
+#define CMU_MFCMSCL_SPARE1	((void *)(CMU_MFCMSCL_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_MFCMSCL	((void *)(CMU_MFCMSCL_BASE + 0x0E00))
+#define MFCMSCL_SFR_IGNORE_REQ_SYSCLK	((void *)(CMU_MFCMSCL_BASE + 0x0F00))
+
+#define SHARED0_PLL_LOCK	((void *)(CMU_MIF_BASE + 0x0000))
+#define SHARED1_PLL_LOCK	((void *)(CMU_MIF_BASE + 0x0020))
+#define SHARED2_PLL_LOCK	((void *)(CMU_MIF_BASE + 0x0040))
+#define SHARED0_PLL_CON0	((void *)(CMU_MIF_BASE + 0x0100))
+#define SHARED0_PLL_CON1	((void *)(CMU_MIF_BASE + 0x0104))
+#define SHARED1_PLL_CON0	((void *)(CMU_MIF_BASE + 0x0120))
+#define SHARED1_PLL_CON1	((void *)(CMU_MIF_BASE + 0x0124))
+#define SHARED2_PLL_CON0	((void *)(CMU_MIF_BASE + 0x0140))
+#define SHARED2_PLL_CON1	((void *)(CMU_MIF_BASE + 0x0144))
+#define CLK_CON_MUX_SHARED0_PLL	((void *)(CMU_MIF_BASE + 0x0200))
+#define CLK_CON_MUX_SHARED1_PLL	((void *)(CMU_MIF_BASE + 0x0204))
+#define CLK_CON_MUX_SHARED2_PLL	((void *)(CMU_MIF_BASE + 0x0208))
+#define CLK_CON_MUX_CLK_MIF_PHY_CLK_A	((void *)(CMU_MIF_BASE + 0x0210))
+#define CLK_CON_MUX_CLK_MIF_PHY_CLK_B	((void *)(CMU_MIF_BASE + 0x0214))
+#define CLK_CON_MUX_CLK_MIF_BUSD	((void *)(CMU_MIF_BASE + 0x0220))
+#define CLK_CON_MUX_CLKCMU_G3D	((void *)(CMU_MIF_BASE + 0x0228))
+#define CLK_CON_MUX_CLKCMU_ISP_VRA	((void *)(CMU_MIF_BASE + 0x022C))
+#define CLK_CON_MUX_CLKCMU_ISP_CAM	((void *)(CMU_MIF_BASE + 0x0230))
+#define CLK_CON_MUX_CLKCMU_DISPAUD_BUS	((void *)(CMU_MIF_BASE + 0x0234))
+#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK	((void *)(CMU_MIF_BASE + 0x0238))
+#define CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL	((void *)(CMU_MIF_BASE + 0x0240))
+#define CLK_CON_MUX_CLKCMU_MFCMSCL_MFC	((void *)(CMU_MIF_BASE + 0x0244))
+#define CLK_CON_MUX_CLKCMU_FSYS_BUS	((void *)(CMU_MIF_BASE + 0x0248))
+#define CLK_CON_MUX_CLKCMU_FSYS_MMC0	((void *)(CMU_MIF_BASE + 0x024C))
+#define CLK_CON_MUX_CLKCMU_FSYS_MMC2	((void *)(CMU_MIF_BASE + 0x0250))
+#define CLK_CON_MUX_CLKCMU_FSYS_USB20DRD_REFCLK	((void *)(CMU_MIF_BASE + 0x0254))
+#define CLK_CON_MUX_CLKCMU_PERI_BUS	((void *)(CMU_MIF_BASE + 0x0258))
+#define CLK_CON_MUX_CLKCMU_PERI_UART_DEBUG	((void *)(CMU_MIF_BASE + 0x0260))
+#define CLK_CON_MUX_CLKCMU_PERI_UART_SENSOR	((void *)(CMU_MIF_BASE + 0x0264))
+#define CLK_CON_MUX_CLKCMU_PERI_SPI_REARFROM	((void *)(CMU_MIF_BASE + 0x026C))
+#define CLK_CON_MUX_CLKCMU_PERI_SPI_ESE	((void *)(CMU_MIF_BASE + 0x0270))
+#define CLK_CON_MUX_CLKCMU_PERI_USI_0	((void *)(CMU_MIF_BASE + 0x0274))
+#define CLK_CON_MUX_CLKCMU_PERI_USI_1	((void *)(CMU_MIF_BASE + 0x0278))
+#define CLK_CON_MUX_CLKCMU_APM	((void *)(CMU_MIF_BASE + 0x027C))
+#define CLK_CON_MUX_CLKCMU_ISP_SENSOR0	((void *)(CMU_MIF_BASE + 0x0280))
+#define CLK_CON_DIV_CLK_MIF_PHY_CLK2X	((void *)(CMU_MIF_BASE + 0x0400))
+#define CLK_CON_DIV_CLK_MIF_PHY_CLKM	((void *)(CMU_MIF_BASE + 0x0404))
+#define CLK_CON_DIV_CLKCMU_CP_SHARED0_PLL	((void *)(CMU_MIF_BASE + 0x0408))
+#define CLK_CON_DIV_CLKCMU_CP_SHARED1_PLL	((void *)(CMU_MIF_BASE + 0x040C))
+#define CLK_CON_DIV_CLKCMU_CP_SHARED2_PLL	((void *)(CMU_MIF_BASE + 0x0410))
+#define CLK_CON_DIV_CLK_MIF_BUSD	((void *)(CMU_MIF_BASE + 0x0414))
+#define CLK_CON_DIV_CLK_MIF_APB	((void *)(CMU_MIF_BASE + 0x0418))
+#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH	((void *)(CMU_MIF_BASE + 0x0420))
+#define CLK_CON_DIV_CLKCMU_G3D	((void *)(CMU_MIF_BASE + 0x0424))
+#define CLK_CON_DIV_CLKCMU_ISP_VRA	((void *)(CMU_MIF_BASE + 0x0428))
+#define CLK_CON_DIV_CLKCMU_ISP_CAM	((void *)(CMU_MIF_BASE + 0x042C))
+#define CLK_CON_DIV_CLKCMU_DISPAUD_BUS	((void *)(CMU_MIF_BASE + 0x0430))
+#define CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK	((void *)(CMU_MIF_BASE + 0x0434))
+#define CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL	((void *)(CMU_MIF_BASE + 0x043C))
+#define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC	((void *)(CMU_MIF_BASE + 0x0440))
+#define CLK_CON_DIV_CLKCMU_FSYS_BUS	((void *)(CMU_MIF_BASE + 0x0444))
+#define CLK_CON_DIV_CLKCMU_FSYS_MMC0	((void *)(CMU_MIF_BASE + 0x0448))
+#define CLK_CON_DIV_CLKCMU_FSYS_MMC2	((void *)(CMU_MIF_BASE + 0x044C))
+#define CLK_CON_DIV_CLKCMU_FSYS_USB20DRD_REFCLK	((void *)(CMU_MIF_BASE + 0x0450))
+#define CLK_CON_DIV_CLKCMU_PERI_BUS	((void *)(CMU_MIF_BASE + 0x0454))
+#define CLK_CON_DIV_CLKCMU_PERI_UART_DEBUG	((void *)(CMU_MIF_BASE + 0x045C))
+#define CLK_CON_DIV_CLKCMU_PERI_UART_SENSOR	((void *)(CMU_MIF_BASE + 0x0460))
+#define CLK_CON_DIV_CLKCMU_PERI_SPI_REARFROM	((void *)(CMU_MIF_BASE + 0x0468))
+#define CLK_CON_DIV_CLKCMU_PERI_SPI_ESE	((void *)(CMU_MIF_BASE + 0x046C))
+#define CLK_CON_DIV_CLKCMU_PERI_USI_0	((void *)(CMU_MIF_BASE + 0x0470))
+#define CLK_CON_DIV_CLKCMU_PERI_USI_1	((void *)(CMU_MIF_BASE + 0x0474))
+#define CLK_CON_DIV_CLKCMU_APM	((void *)(CMU_MIF_BASE + 0x0478))
+#define CLK_CON_DIV_CLKCMU_ISP_SENSOR0	((void *)(CMU_MIF_BASE + 0x04C4))
+#define CLK_CON_DIV_CLKCMU_GNSS_EXTPLL_SCAN	((void *)(CMU_MIF_BASE + 0x04C8))
+#define CLK_CON_DIV_CLKCMU_WLBT_EXTPLL_SCAN	((void *)(CMU_MIF_BASE + 0x04CC))
+#define CLK_STAT_MUX_SHARED0_PLL	((void *)(CMU_MIF_BASE + 0x0600))
+#define CLK_STAT_MUX_SHARED1_PLL	((void *)(CMU_MIF_BASE + 0x0604))
+#define CLK_STAT_MUX_SHARED2_PLL	((void *)(CMU_MIF_BASE + 0x0608))
+#define CLK_STAT_MUX_CLK_MIF_PHY_CLK_A	((void *)(CMU_MIF_BASE + 0x0610))
+#define CLK_STAT_MUX_CLK_MIF_PHY_CLK_B	((void *)(CMU_MIF_BASE + 0x0614))
+#define CLK_STAT_MUX_CLK_MIF_BUSD	((void *)(CMU_MIF_BASE + 0x0620))
+#define CLK_STAT_MUX_CLKCMU_G3D	((void *)(CMU_MIF_BASE + 0x0628))
+#define CLK_STAT_MUX_CLKCMU_ISP_VRA	((void *)(CMU_MIF_BASE + 0x062C))
+#define CLK_STAT_MUX_CLKCMU_ISP_CAM	((void *)(CMU_MIF_BASE + 0x0630))
+#define CLK_STAT_MUX_CLKCMU_DISPAUD_BUS	((void *)(CMU_MIF_BASE + 0x0634))
+#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK	((void *)(CMU_MIF_BASE + 0x0638))
+#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MSCL	((void *)(CMU_MIF_BASE + 0x0640))
+#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MFC	((void *)(CMU_MIF_BASE + 0x0644))
+#define CLK_STAT_MUX_CLKCMU_FSYS_BUS	((void *)(CMU_MIF_BASE + 0x0648))
+#define CLK_STAT_MUX_CLKCMU_FSYS_MMC0	((void *)(CMU_MIF_BASE + 0x064C))
+#define CLK_STAT_MUX_CLKCMU_FSYS_MMC2	((void *)(CMU_MIF_BASE + 0x0650))
+#define CLK_STAT_MUX_CLKCMU_FSYS_USB20DRD_REFCLK	((void *)(CMU_MIF_BASE + 0x0654))
+#define CLK_STAT_MUX_CLKCMU_PERI_BUS	((void *)(CMU_MIF_BASE + 0x0658))
+#define CLK_STAT_MUX_CLKCMU_PERI_UART_DEBUG	((void *)(CMU_MIF_BASE + 0x0660))
+#define CLK_STAT_MUX_CLKCMU_PERI_UART_SENSOR	((void *)(CMU_MIF_BASE + 0x0664))
+#define CLK_STAT_MUX_CLKCMU_PERI_SPI_REARFROM	((void *)(CMU_MIF_BASE + 0x066C))
+#define CLK_STAT_MUX_CLKCMU_PERI_SPI_ESE	((void *)(CMU_MIF_BASE + 0x0670))
+#define CLK_STAT_MUX_CLKCMU_PERI_USI_0	((void *)(CMU_MIF_BASE + 0x0674))
+#define CLK_STAT_MUX_CLKCMU_PERI_USI_1	((void *)(CMU_MIF_BASE + 0x0678))
+#define CLK_STAT_MUX_CLKCMU_APM	((void *)(CMU_MIF_BASE + 0x067C))
+#define CLK_STAT_MUX_CLKCMU_ISP_SENSOR0	((void *)(CMU_MIF_BASE + 0x0680))
+#define CLK_ENABLE_CLK_MIF_OSCCLK	((void *)(CMU_MIF_BASE + 0x0800))
+#define CLK_ENABLE_CLK_MIF_PHY_CLK2X	((void *)(CMU_MIF_BASE + 0x0804))
+#define CLK_ENABLE_CLK_MIF_PHY_CLKM	((void *)(CMU_MIF_BASE + 0x0808))
+#define CLK_ENABLE_CLK_MIF_DDRPHY0	((void *)(CMU_MIF_BASE + 0x080C))
+#define CLK_ENABLE_CLK_MIF_BUSD	((void *)(CMU_MIF_BASE + 0x0810))
+#define CLK_ENABLE_CLK_MIF_APB	((void *)(CMU_MIF_BASE + 0x0814))
+#define CLK_ENABLE_CLK_MIF_APB_SECURE_DMC0	((void *)(CMU_MIF_BASE + 0x0818))
+#define CLK_ENABLE_CLK_MIF_APB_SECURE_MAILBOX_SECURE	((void *)(CMU_MIF_BASE + 0x081C))
+#define CLK_ENABLE_CLKCMU_CP_SHARED0_PLL	((void *)(CMU_MIF_BASE + 0x0820))
+#define CLK_ENABLE_CLKCMU_CP_SHARED1_PLL	((void *)(CMU_MIF_BASE + 0x0824))
+#define CLK_ENABLE_CLKCMU_CP_SHARED2_PLL	((void *)(CMU_MIF_BASE + 0x0828))
+#define CLK_ENABLE_CLKCMU_CPUCL0_SWITCH	((void *)(CMU_MIF_BASE + 0x082C))
+#define CLK_ENABLE_CLKCMU_G3D	((void *)(CMU_MIF_BASE + 0x0830))
+#define CLK_ENABLE_CLKCMU_ISP_VRA	((void *)(CMU_MIF_BASE + 0x0834))
+#define CLK_ENABLE_CLKCMU_ISP_CAM	((void *)(CMU_MIF_BASE + 0x0838))
+#define CLK_ENABLE_CLKCMU_DISPAUD_BUS	((void *)(CMU_MIF_BASE + 0x083C))
+#define CLK_ENABLE_CLKCMU_DISPAUD_DECON_INT_VCLK	((void *)(CMU_MIF_BASE + 0x0840))
+#define CLK_ENABLE_CLKCMU_MFCMSCL_MFC	((void *)(CMU_MIF_BASE + 0x0848))
+#define CLK_ENABLE_CLKCMU_MFCMSCL_MSCL	((void *)(CMU_MIF_BASE + 0x084C))
+#define CLK_ENABLE_CLKCMU_FSYS_BUS	((void *)(CMU_MIF_BASE + 0x0850))
+#define CLK_ENABLE_CLKCMU_FSYS_MMC0	((void *)(CMU_MIF_BASE + 0x0854))
+#define CLK_ENABLE_CLKCMU_FSYS_MMC2	((void *)(CMU_MIF_BASE + 0x0858))
+#define CLK_ENABLE_CLKCMU_FSYS_USB20DRD_REFCLK	((void *)(CMU_MIF_BASE + 0x085C))
+#define CLK_ENABLE_CLKCMU_PERI_BUS	((void *)(CMU_MIF_BASE + 0x0860))
+#define CLK_ENABLE_CLKCMU_PERI_UART_DEBUG	((void *)(CMU_MIF_BASE + 0x0868))
+#define CLK_ENABLE_CLKCMU_PERI_UART_SENSOR	((void *)(CMU_MIF_BASE + 0x086C))
+#define CLK_ENABLE_CLKCMU_PERI_SPI_REARFROM	((void *)(CMU_MIF_BASE + 0x0874))
+#define CLK_ENABLE_CLKCMU_PERI_SPI_ESE	((void *)(CMU_MIF_BASE + 0x0878))
+#define CLK_ENABLE_CLKCMU_PERI_USI_0	((void *)(CMU_MIF_BASE + 0x087C))
+#define CLK_ENABLE_CLKCMU_PERI_USI_1	((void *)(CMU_MIF_BASE + 0x0880))
+#define CLK_ENABLE_CLKCMU_APM	((void *)(CMU_MIF_BASE + 0x0884))
+#define CLK_ENABLE_CLKCMU_ISP_SENSOR0	((void *)(CMU_MIF_BASE + 0x0888))
+#define CLK_ENABLE_CLKCMU_GNSS_EXTPLL_SCAN	((void *)(CMU_MIF_BASE + 0x088C))
+#define CLK_ENABLE_CLKCMU_WLBT_EXTPLL_SCAN	((void *)(CMU_MIF_BASE + 0x0890))
+#define SECURE_ENABLE_CLKCMU_FSYS_BUS	((void *)(CMU_MIF_BASE + 0x0894))
+#define CLK_ENABLE_CLK_MIF_TCXO	((void *)(CMU_MIF_BASE + 0x089C))
+#define CLKOUT_CMU_MIF	((void *)(CMU_MIF_BASE + 0x0D00))
+#define CLKOUT_CMU_MIF_DIV_STAT	((void *)(CMU_MIF_BASE + 0x0D04))
+#define CMU_MIF_SPARE0	((void *)(CMU_MIF_BASE + 0x0D08))
+#define CMU_MIF_SPARE1	((void *)(CMU_MIF_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_MIF	((void *)(CMU_MIF_BASE + 0x0E00))
+#define MIF_SFR_IGNORE_REQ_SYSCLK	((void *)(CMU_MIF_BASE + 0x0F00))
+#define MIF_ROOTCLKEN	((void *)(CMU_MIF_BASE + 0x0F04))
+#define MIF_ROOTCLKEN_ON_GATE	((void *)(CMU_MIF_BASE + 0x0F10))
+#define DREX_FREQ_CTRL0	((void *)(CMU_MIF_BASE + 0x1000))
+#define DREX_FREQ_CTRL1	((void *)(CMU_MIF_BASE + 0x1004))
+#define PAUSE	((void *)(CMU_MIF_BASE + 0x1008))
+#define DDRPHY_LOCK_CTRL	((void *)(CMU_MIF_BASE + 0x100C))
+#define CP_CTRL_SPEEDY_ENABLE	((void *)(CMU_MIF_BASE + 0x1014))
+#define CP_CTRL_ADCIF_ENABLE	((void *)(CMU_MIF_BASE + 0x1018))
+#define FAKE_PAUSE	((void *)(CMU_MIF_BASE + 0x1020))
+#define CG_CTRL_VAL_CLK_MIF_DDRPHY0	((void *)(CMU_MIF_BASE + 0x1800))
+#define CG_CTRL_VAL_CLK_MIF_BUSD	((void *)(CMU_MIF_BASE + 0x1804))
+#define CG_CTRL_VAL_CLK_MIF_APB	((void *)(CMU_MIF_BASE + 0x1808))
+#define CG_CTRL_MAN_CLK_MIF_DDRPHY0	((void *)(CMU_MIF_BASE + 0x1900))
+#define CG_CTRL_MAN_CLK_MIF_BUSD	((void *)(CMU_MIF_BASE + 0x1904))
+#define CG_CTRL_MAN_CLK_MIF_APB	((void *)(CMU_MIF_BASE + 0x1908))
+#define CG_CTRL_STAT_CLK_MIF_DDRPHY0	((void *)(CMU_MIF_BASE + 0x1A00))
+#define CG_CTRL_STAT_CLK_MIF_BUSD_1	((void *)(CMU_MIF_BASE + 0x1A04))
+#define CG_CTRL_STAT_CLK_MIF_BUSD_2	((void *)(CMU_MIF_BASE + 0x1A08))
+#define CG_CTRL_STAT_CLK_MIF_APB_1	((void *)(CMU_MIF_BASE + 0x1A0C))
+#define CG_CTRL_STAT_CLK_MIF_APB_2	((void *)(CMU_MIF_BASE + 0x1A10))
+#define QCH_CTRL_UID_TREX_MIF_D	((void *)(CMU_MIF_BASE + 0x2000))
+#define QCH_CTRL_UID_ASYNCM_LH_G3D0_MIF_D_NRT	((void *)(CMU_MIF_BASE + 0x2004))
+#define QCH_CTRL_UID_ASYNCM_LH_MFCMSCL0_MIF_D_NRT	((void *)(CMU_MIF_BASE + 0x2008))
+#define QCH_CTRL_UID_ASYNCM_LH_FSYS_MIF_D_NRT	((void *)(CMU_MIF_BASE + 0x200C))
+#define QCH_CTRL_UID_ASYNCM_LH_ISP_MIF_D_RT	((void *)(CMU_MIF_BASE + 0x2010))
+#define QCH_CTRL_UID_ASYNCM_LH_DISPAUD_MIF_D_RT	((void *)(CMU_MIF_BASE + 0x2014))
+#define QCH_CTRL_UID_ASYNCM_LH_WFBT_MIF_D_CP	((void *)(CMU_MIF_BASE + 0x201C))
+#define QCH_CTRL_UID_ASYNCS_LH_APM_P	((void *)(CMU_MIF_BASE + 0x2024))
+#define QCH_CTRL_UID_ASYNCM_LH_CP_MIF_D_CP	((void *)(CMU_MIF_BASE + 0x2028))
+#define QCH_CTRL_UID_ASYNCM_LH_GNSS_MIF_D_CP	((void *)(CMU_MIF_BASE + 0x202C))
+#define QCH_CTRL_UID_TREX_MIF_P	((void *)(CMU_MIF_BASE + 0x2030))
+#define QCH_CTRL_UID_ASYNCM_LH_APM_D	((void *)(CMU_MIF_BASE + 0x2034))
+#define QCH_CTRL_UID_ASYNCS_LH_MIF_P_CPUCL0	((void *)(CMU_MIF_BASE + 0x2038))
+#define QCH_CTRL_UID_ASYNCS_LH_MIF_P_DISPAUD	((void *)(CMU_MIF_BASE + 0x203C))
+#define QCH_CTRL_UID_ASYNCS_LH_MIF_P_FSYS	((void *)(CMU_MIF_BASE + 0x2040))
+#define QCH_CTRL_UID_ASYNCS_LH_MIF_P_G3D	((void *)(CMU_MIF_BASE + 0x2044))
+#define QCH_CTRL_UID_ASYNCS_LH_MIF_P_ISP	((void *)(CMU_MIF_BASE + 0x2048))
+#define QCH_CTRL_UID_ASYNCS_LH_MIF_P_MFCMSCL	((void *)(CMU_MIF_BASE + 0x204C))
+#define QCH_CTRL_UID_ASYNCS_LH_MIF_P_PERI	((void *)(CMU_MIF_BASE + 0x2050))
+
+#define CLK_CON_DIV_CLK_PERI_USI_0_SPI	((void *)(CMU_PERI_BASE + 0x0400))
+#define CLK_CON_DIV_CLK_PERI_USI_1_SPI	((void *)(CMU_PERI_BASE + 0x0404))
+#define CLK_ENABLE_CLK_PERI_OSCCLK	((void *)(CMU_PERI_BASE + 0x0800))
+#define CLK_ENABLE_CLK_PERI_OSCCLK_SECURE_CHIPID	((void *)(CMU_PERI_BASE + 0x0804))
+#define CLK_ENABLE_CLK_PERI_BUS0	((void *)(CMU_PERI_BASE + 0x0810))
+#define CLK_ENABLE_CLK_PERI_BUS1	((void *)(CMU_PERI_BASE + 0x0814))
+#define CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC	((void *)(CMU_PERI_BASE + 0x0818))
+#define CLK_ENABLE_CLK_PERI_BUS_SECURE_CHIPID	((void *)(CMU_PERI_BASE + 0x081C))
+#define CLK_ENABLE_CLK_PERI_BUS_SECURE_OTP_CON_TOP	((void *)(CMU_PERI_BASE + 0x0820))
+#define CLK_ENABLE_CLK_PERI_BUS_SECURE_RTC_ALIVE	((void *)(CMU_PERI_BASE + 0x0824))
+#define CLK_ENABLE_CLK_PERI_BUS_SECURE_RTC_TOP	((void *)(CMU_PERI_BASE + 0x0828))
+#define CLK_ENABLE_CLK_PERI_UART_DEBUG	((void *)(CMU_PERI_BASE + 0x0834))
+#define CLK_ENABLE_CLK_PERI_UART_SENSOR	((void *)(CMU_PERI_BASE + 0x0838))
+#define CLK_ENABLE_CLK_PERI_SPI_REARFROM	((void *)(CMU_PERI_BASE + 0x0840))
+#define CLK_ENABLE_CLK_PERI_SPI_ESE	((void *)(CMU_PERI_BASE + 0x0844))
+#define CLK_ENABLE_CLK_PERI_USI_0	((void *)(CMU_PERI_BASE + 0x0850))
+#define CLK_ENABLE_CLK_PERI_USI_1	((void *)(CMU_PERI_BASE + 0x0854))
+#define CLK_ENABLE_CLK_PERI_USI_0_SPI	((void *)(CMU_PERI_BASE + 0x0858))
+#define CLK_ENABLE_CLK_PERI_USI_1_SPI	((void *)(CMU_PERI_BASE + 0x085C))
+#define CLKOUT_CMU_PERI	((void *)(CMU_PERI_BASE + 0x0D00))
+#define CLKOUT_CMU_PERI_DIV_STAT	((void *)(CMU_PERI_BASE + 0x0D04))
+#define CMU_PERI_SPARE0	((void *)(CMU_PERI_BASE + 0x0D08))
+#define CMU_PERI_SPARE1	((void *)(CMU_PERI_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_PERI	((void *)(CMU_PERI_BASE + 0x0E00))
+
+#define CPUCL0_EMA_CON		((void *)(SYSREG_CPUCL0_BASE + 0x0330))
+#define CPUCL0_EMA		((void *)(SYSREG_CPUCL0_BASE + 0x0340))
+#define G3D_EMA_RA1_HS_CON	((void *)(SYSREG_G3D_BASE + 0x0304))
+#define G3D_EMA_RF1_HS_CON	((void *)(SYSREG_G3D_BASE + 0x0314))
+#define G3D_EMA_RF2_HS_CON	((void *)(SYSREG_G3D_BASE + 0x031C))
+#define G3D_EMA_UHD_CON		((void *)(SYSREG_G3D_BASE + 0x0320))
+
+#if !defined(CONFIG_PM_RUNTIME) && !defined(CONFIG_CAL_SYS_PWRDOWN)
+struct exynos_pd_clk {
+	void __iomem *reg;
+	u8 bit_offset;
+	char *domain_name;
+};
+
+struct exynos_pd_reg {
+	void __iomem *reg;
+	u8 bit_offset;
+};
+
+struct sfr_save {
+	void __iomem *reg;
+};
+#endif
+#endif

drivers/soc/samsung/pwrcal/S5E7570/S5E7570-dfs.c

@@ -0,0 +1,506 @@
+#include "../pwrcal.h"
+#include "../pwrcal-env.h"
+#include "../pwrcal-clk.h"
+#include "../pwrcal-pmu.h"
+#include "../pwrcal-dfs.h"
+#include "../pwrcal-rae.h"
+#include "../pwrcal-asv.h"
+#include "S5E7570-cmusfr.h"
+#include "S5E7570-pmusfr.h"
+#include "S5E7570-cmu.h"
+#include "S5E7570-vclk-internal.h"
+
+extern unsigned int dfscpucl0_rate_table[];
+extern unsigned int dfsg3d_rate_table[];
+extern unsigned int dfsmif_rate_table[];
+extern unsigned int dfsint_rate_table[];
+extern unsigned int dfsdisp_rate_table[];
+extern unsigned int dfscam_rate_table[];
+
+static struct dfs_switch dfscpucl0_switches[] = {
+#ifdef CONFIG_SOC_EXYNOS7570_DUAL
+	{840000,	0,	0},
+	{840000 / 2,	0,	1},
+	{840000 / 3,	0,	2},
+	{840000 / 4,	0,	3},
+#else
+	{830000,	0,	0},
+	{830000 / 2,	0,	1},
+	{830000 / 3,	0,	2},
+	{830000 / 4,	0,	3},
+#endif
+};
+
+static struct dfs_table dfscpucl0_table = {
+	.switches = dfscpucl0_switches,
+	.num_of_switches = ARRAY_SIZE(dfscpucl0_switches),
+	.switch_mux = CLK(CPUCL0_MUX_CLK_CPUCL0),
+	.switch_use = 1,
+	.switch_notuse = 0,
+	.switch_src_div = CLK(MIF_DIV_CLKCMU_CPUCL0_SWITCH),
+	.switch_src_gate = CLK(MIF_GATE_CLKCMU_CPUCL0_SWITCH),
+	.switch_src_usermux = CLK(CPUCL0_MUX_CLKCMU_CPUCL0_SWITCH_USER),
+};
+
+struct pwrcal_clk_set dfscpucl0_en_list[] = {
+	{CLK_NONE,	0,	-1},
+};
+
+static struct dfs_switch dfsg3d_switches[] = {
+};
+
+static struct dfs_table dfsg3d_table = {
+	.switches = dfsg3d_switches,
+	.num_of_switches = ARRAY_SIZE(dfsg3d_switches),
+	.switch_use = 1,
+	.switch_notuse = 0,
+};
+
+struct pwrcal_clk_set dfsg3d_en_list[] = {
+	{CLK(G3D_MUX_CLKCMU_G3D_USER),	1,	0},
+	{CLK(G3D_DIV_CLK_G3D_BUS),	3,	-1},
+	{CLK(G3D_DIV_CLK_G3D_APB),	3,	-1},
+	{CLK_NONE,	0,	-1},
+};
+
+static struct dfs_switch dfsmif_switches[] = {
+};
+
+extern void pwrcal_dmc_set_dvfs(unsigned long long target_mif_freq, unsigned int timing_set_idx);
+extern void pwrcal_dmc_set_pre_dvfs(void);
+extern void pwrcal_dmc_set_post_dvfs(unsigned long long target_freq);
+extern void pwrcal_dmc_set_vtmon_on_swithing(void);
+extern void pwrcal_dmc_set_refresh_method_pre_dvfs(unsigned long long current_rate, unsigned long long target_rate);
+extern void pwrcal_dmc_set_refresh_method_post_dvfs(unsigned long long current_rate, unsigned long long target_rate);
+extern void pwrcal_dmc_set_dsref_cycle(unsigned long long target_rate);
+
+static int pwrcal_clk_set_mif_pause_enable(int enable)
+{
+	pwrcal_writel(PAUSE, (enable<<0)); /* CMU Pause enable */
+	return 0;
+}
+
+static int pwrcal_clk_wait_mif_pause(void)
+{
+	int timeout;
+	unsigned int status;
+
+	for (timeout = 0;; timeout++) {
+		status = pwrcal_getf(PAUSE, 16, 0x3);
+		if (status == 0x0)
+			break;
+
+		if (timeout > CLK_WAIT_CNT)
+			pr_err("PAUSE staus(0x%X) is not stable", status);
+
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+static int is_dll_on_status = 1;
+
+static void dfsmif_trans_pre(unsigned int rate_from, unsigned int rate_to)
+{
+	static unsigned int paraset;
+	unsigned long long from, to;
+
+	is_dll_on_status = 1;
+
+	from = (unsigned long long)rate_from * 1000;
+	to = (unsigned long long)rate_to * 1000;
+
+	pwrcal_dmc_set_refresh_method_pre_dvfs(from, to);
+	pwrcal_clk_set_mif_pause_enable(1);
+
+	/* VTMON disable before MIF DFS sequence*/
+	pwrcal_dmc_set_pre_dvfs();
+
+	paraset = (paraset + 1) % 2;
+	pwrcal_dmc_set_dvfs(to, paraset);
+}
+
+static void dfsmif_trans_post(unsigned int rate_from, unsigned int rate_to)
+{
+	unsigned long long from, to;
+
+	from = (unsigned long long)rate_from * 1000;
+	to = (unsigned long long)rate_to * 1000;
+
+	pwrcal_clk_wait_mif_pause();
+
+	/* VTMON enable before MIF DFS sequence*/
+	pwrcal_dmc_set_post_dvfs(to);
+
+	pwrcal_dmc_set_refresh_method_post_dvfs(from, to);
+	pwrcal_dmc_set_dsref_cycle(to);
+
+	if (rate_to >= 416000)
+		is_dll_on_status = 1;
+	else
+		is_dll_on_status = 0;
+}
+
+static int dfsmif_transition(unsigned int rate_from, unsigned int rate_to, struct dfs_table *table)
+{
+	int lv_from, lv_to;
+
+	lv_from = dfs_get_lv(rate_from, table);
+	if (lv_from >= table->num_of_lv)
+		goto errorout;
+
+	lv_to = dfs_get_lv(rate_to, table);
+	if (lv_to >= table->num_of_lv)
+		goto errorout;
+
+	dfsmif_trans_pre(rate_from, rate_to);
+
+	if (dfs_trans_div(lv_from, lv_to, table, TRANS_HIGH))
+		goto errorout;
+
+	if (dfs_trans_mux(lv_from, lv_to, table, TRANS_DIFF))
+		goto errorout;
+
+	if (dfs_trans_div(lv_from, lv_to, table, TRANS_LOW))
+		goto errorout;
+
+	dfsmif_trans_post(rate_from, rate_to);
+
+
+	return 0;
+
+errorout:
+	return -1;
+}
+
+static unsigned long dfs_mif_get_rate(struct dfs_table *table)
+{
+	int l, m;
+	unsigned int cur[128] = {0, };
+	unsigned long long rate;
+	struct pwrcal_clk *clk;
+	unsigned int drex_freq = 0;
+	unsigned int value[4], temp;
+
+	for (m = 1; m < table->num_of_members; m++) {
+		clk = table->members[m];
+		if (is_pll(clk)) {
+			rate = pwrcal_pll_get_rate(clk);
+			do_div(rate, 1000);
+			cur[m] = (unsigned int)rate;
+		}
+		if (is_mux(clk)) {
+			if (clk->id == MIF_MUX_CLK_MIF_PHY_CLK) {
+				temp = pwrcal_getf(clk->offset, 0, 0xffffffff);
+
+				value[0] = (unsigned char)((temp & (0x1 << 4)) >> 4);
+				value[1] = (unsigned char)((temp & (0x1 << 5)) >> 5);
+				value[2] = (unsigned char)((temp & (0xf << 16)) >> 16);
+				value[3] = (unsigned char)((temp & (0xf << 20)) >> 20);
+
+				drex_freq |= (value[0] & 0x1) << 7;
+				drex_freq |= (value[1] & 0x1) << 6;
+				drex_freq |= (value[2] & 0x7) << 3;
+				drex_freq |= (value[3] & 0x7) << 0;
+
+				cur[m] = drex_freq;
+			} else
+				cur[m] = pwrcal_mux_get_src(clk);
+		}
+		if (is_div(clk))
+			cur[m] = pwrcal_div_get_ratio(clk) - 1;
+		if (is_gate(clk))
+			cur[m] = pwrcal_gate_is_enabled(clk);
+	}
+
+	for (l = 0; l < table->num_of_lv; l++) {
+		for (m = 1; m < table->num_of_members; m++)
+			if (cur[m] != get_value(table, l, m))
+				break;
+
+		if (m == table->num_of_members)
+			return get_value(table, l, 0);
+	}
+
+	for (m = 1; m < table->num_of_members; m++) {
+		clk = table->members[m];
+		pr_err("dfs_get_rate mid : %s : %d\n", clk->name, cur[m]);
+	}
+
+	return 0;
+}
+
+static struct dfs_table dfsmif_table = {
+	.switches = dfsmif_switches,
+	.num_of_switches = ARRAY_SIZE(dfsmif_switches),
+	.switch_use = 1,
+	.switch_notuse = 0,
+	.private_trans = dfsmif_transition,
+	.private_getrate = dfs_mif_get_rate,
+};
+
+struct pwrcal_clk_set dfsmif_en_list[] = {
+	{	CLK_NONE,	0,	-1},
+};
+
+static struct dfs_switch dfsint_switches[] = {
+};
+
+static struct dfs_table dfsint_table = {
+	.switches = dfsint_switches,
+	.num_of_switches = ARRAY_SIZE(dfsint_switches),
+	.switch_use = 1,
+	.switch_notuse = 0,
+};
+
+struct pwrcal_clk_set dfsint_en_list[] = {
+	{CLK_NONE,	0,	-1},
+};
+
+static struct dfs_switch dfsdisp_switches[] = {
+};
+
+static struct dfs_table dfsdisp_table = {
+	.switches = dfsdisp_switches,
+	.num_of_switches = ARRAY_SIZE(dfsdisp_switches),
+	.switch_use = 1,
+	.switch_notuse = 0,
+};
+
+struct pwrcal_clk_set dfsdisp_en_list[] = {
+	{CLK_NONE,	0,	-1},
+};
+
+static struct dfs_switch dfscam_switches[] = {
+};
+
+static struct dfs_table dfscam_table = {
+	.switches = dfscam_switches,
+	.num_of_switches = ARRAY_SIZE(dfscam_switches),
+	.switch_use = 1,
+	.switch_notuse = 0,
+};
+
+struct pwrcal_clk_set dfscam_en_list[] = {
+	{CLK_NONE,	0,	-1},
+};
+
+static int dfscpucl0_get_rate_table(unsigned long *table)
+{
+	return dfs_get_rate_table(&dfscpucl0_table, table);
+}
+
+static int dfscpucl0_idle_clock_down(unsigned int enable)
+{
+	return 0;
+}
+
+static struct vclk_dfs_ops dfscpucl0_dfsops = {
+	.get_rate_table = dfscpucl0_get_rate_table,
+	.cpu_idle_clock_down = dfscpucl0_idle_clock_down,
+};
+
+static int dfsg3d_dvs(int on)
+{
+	return 0;
+}
+
+static int dfsg3d_get_rate_table(unsigned long *table)
+{
+	return dfs_get_rate_table(&dfsg3d_table, table);
+}
+
+static struct vclk_dfs_ops dfsg3d_dfsops = {
+	.dvs = dfsg3d_dvs,
+	.get_rate_table = dfsg3d_get_rate_table,
+};
+
+static int dfsmif_get_rate_table(unsigned long *table)
+{
+	return dfs_get_rate_table(&dfsmif_table, table);
+}
+
+static int dfsmif_is_dll_on(void)
+{
+	return 1;
+}
+
+static struct vclk_dfs_ops dfsmif_dfsops = {
+	.get_rate_table = dfsmif_get_rate_table,
+	.is_dll_on = dfsmif_is_dll_on,
+};
+
+static int dfsint_get_rate_table(unsigned long *table)
+{
+	return dfs_get_rate_table(&dfsint_table, table);
+}
+
+static struct vclk_dfs_ops dfsint_dfsops = {
+	.get_rate_table = dfsint_get_rate_table,
+};
+
+static int dfsdisp_get_rate_table(unsigned long *table)
+{
+	return dfs_get_rate_table(&dfsdisp_table, table);
+}
+
+static struct vclk_dfs_ops dfsdisp_dfsops = {
+	.get_rate_table = dfsdisp_get_rate_table,
+};
+
+static int dfscam_get_rate_table(unsigned long *table)
+{
+	return dfs_get_rate_table(&dfscam_table, table);
+}
+
+static struct vclk_dfs_ops dfscam_dfsops = {
+	.get_rate_table = dfscam_get_rate_table,
+};
+
+static DEFINE_SPINLOCK(dvfs_cpucl0_lock);
+static DEFINE_SPINLOCK(dvfs_g3d_lock);
+static DEFINE_SPINLOCK(dvfs_mif_lock);
+static DEFINE_SPINLOCK(dvfs_int_lock);
+static DEFINE_SPINLOCK(dvfs_disp_lock);
+static DEFINE_SPINLOCK(dvfs_cam_lock);
+
+DFS(dvfs_cpucl0) = {
+	.vclk.type	= vclk_group_dfs,
+	.vclk.parent	= VCLK(pxmxdx_top),
+	.vclk.ref_count	= 1,
+	.vclk.vfreq	= 0,
+	.vclk.name	= "dvfs_cpucl0",
+	.vclk.ops	= &dfs_ops,
+	.lock		= &dvfs_cpucl0_lock,
+	.en_clks	= dfscpucl0_en_list,
+	.table		= &dfscpucl0_table,
+	.dfsops		= &dfscpucl0_dfsops,
+};
+DFS(dvfs_g3d) = {
+	.vclk.type	= vclk_group_dfs,
+	.vclk.parent	= VCLK(pxmxdx_top),
+	.vclk.ref_count	= 0,
+	.vclk.vfreq	= 350000,
+	.vclk.name	= "dvfs_g3d",
+	.vclk.ops	= &dfs_ops,
+	.lock		= &dvfs_g3d_lock,
+	.en_clks	= dfsg3d_en_list,
+	.table		= &dfsg3d_table,
+	.dfsops		= &dfsg3d_dfsops,
+};
+
+DFS(dvfs_mif) = {
+	.vclk.type	= vclk_group_dfs,
+	.vclk.parent	= VCLK(pxmxdx_top),
+	.vclk.ref_count	= 1,
+	.vclk.vfreq	= 0,
+	.vclk.name	= "dvfs_mif",
+	.vclk.ops	= &dfs_ops,
+	.lock		= &dvfs_mif_lock,
+	.en_clks	= dfsmif_en_list,
+	.table		= &dfsmif_table,
+	.dfsops		= &dfsmif_dfsops,
+};
+
+DFS(dvfs_int) = {
+	.vclk.type	= vclk_group_dfs,
+	.vclk.parent	= VCLK(pxmxdx_top),
+	.vclk.ref_count	= 1,
+	.vclk.vfreq	= 0,
+	.vclk.name	= "dvfs_int",
+	.vclk.ops	= &dfs_ops,
+	.lock		= &dvfs_int_lock,
+	.en_clks	= dfsint_en_list,
+	.table		= &dfsint_table,
+	.dfsops		= &dfsint_dfsops,
+};
+
+DFS(dvfs_disp) = {
+	.vclk.type	= vclk_group_dfs,
+	.vclk.parent	= VCLK(pxmxdx_top),
+	.vclk.ref_count	= 0,
+	.vclk.vfreq	= 0,
+	.vclk.name	= "dvfs_disp",
+	.vclk.ops	= &dfs_ops,
+	.lock		= &dvfs_disp_lock,
+	.en_clks	= dfsdisp_en_list,
+	.table		= &dfsdisp_table,
+	.dfsops		= &dfsdisp_dfsops,
+};
+
+DFS(dvfs_cam) = {
+	.vclk.type	= vclk_group_dfs,
+	.vclk.parent	= VCLK(pxmxdx_top),
+	.vclk.ref_count	= 0,
+#ifdef CONFIG_SOC_EXYNOS7570_DUAL
+	.vclk.vfreq	= 560000,
+#else
+	.vclk.vfreq	= 554000,
+#endif
+	.vclk.name	= "dvfs_cam",
+	.vclk.ops	= &dfs_ops,
+	.lock		= &dvfs_cam_lock,
+	.en_clks	= dfscam_en_list,
+	.table		= &dfscam_table,
+	.dfsops		= &dfscam_dfsops,
+};
+
+void dfs_set_clk_information(struct pwrcal_vclk_dfs *dfs)
+{
+	int i, j;
+	void *dvfs_block;
+	struct ect_dvfs_domain *dvfs_domain;
+	struct dfs_table *dvfs_table;
+
+	dvfs_block = ect_get_block("DVFS");
+	if (dvfs_block == NULL)
+		return;
+
+	dvfs_domain = ect_dvfs_get_domain(dvfs_block, dfs->vclk.name);
+	if (dvfs_domain == NULL)
+		return;
+
+	dvfs_table = dfs->table;
+	dvfs_table->num_of_lv = dvfs_domain->num_of_level;
+	dvfs_table->num_of_members = dvfs_domain->num_of_clock + 1;
+	dvfs_table->max_freq = dvfs_domain->max_frequency;
+	dvfs_table->min_freq = dvfs_domain->min_frequency;
+
+	dvfs_table->members = kzalloc(sizeof(struct pwrcal_clk *) * (dvfs_domain->num_of_clock + 1), GFP_KERNEL);
+	if (dvfs_table->members == NULL)
+		return;
+
+	dvfs_table->members[0] = REPRESENT_RATE;
+	for (i = 0; i < dvfs_domain->num_of_clock; ++i) {
+		dvfs_table->members[i + 1] = clk_find(dvfs_domain->list_clock[i]);
+		if (dvfs_table->members[i] == NULL)
+			return;
+	}
+
+	dvfs_table->rate_table = kzalloc(sizeof(unsigned int) * (dvfs_domain->num_of_clock + 1) * dvfs_domain->num_of_level, GFP_KERNEL);
+	if (dvfs_table->rate_table == NULL)
+		return;
+
+	for (i = 0; i < dvfs_domain->num_of_level; ++i) {
+
+		dvfs_table->rate_table[i * (dvfs_domain->num_of_clock + 1)] = dvfs_domain->list_level[i].level;
+		for (j = 0; j <= dvfs_domain->num_of_clock; ++j) {
+			dvfs_table->rate_table[i * (dvfs_domain->num_of_clock + 1) + j + 1] =
+				dvfs_domain->list_dvfs_value[i * dvfs_domain->num_of_clock + j];
+		}
+	}
+
+}
+
+void dfs_init(void)
+{
+	dfs_set_clk_information(&vclk_dvfs_cpucl0);
+	dfs_set_clk_information(&vclk_dvfs_g3d);
+	dfs_set_clk_information(&vclk_dvfs_mif);
+	dfs_set_clk_information(&vclk_dvfs_int);
+	dfs_set_clk_information(&vclk_dvfs_cam);
+	dfs_set_clk_information(&vclk_dvfs_disp);
+
+	dfs_dram_init();
+}

drivers/soc/samsung/pwrcal/S5E7570/S5E7570-drampara.c

@@ -0,0 +1,556 @@
+#include "../pwrcal-env.h"
+#include "../pwrcal-rae.h"
+#include "S5E7570-sfrbase.h"
+#include "S5E7570-vclk-internal.h"
+#include "S5E7570-pmusfr.h"
+
+#ifdef PWRCAL_TARGET_LINUX
+#include <soc/samsung/ect_parser.h>
+#else
+#include <mach/ect_parser.h>
+#endif
+
+#ifndef MHZ
+#define MHZ		((unsigned long long)1000000)
+#endif
+
+#define DMC_WAIT_CNT 10000
+
+#define DREX0_MEMORY_CONTROL0			((void *)(DREX0_BASE + 0x0010))
+#define DREX0_POWER_DOWN_CONFIG			((void *)(DREX0_BASE + 0x0014))
+#define DREX0_CG_CONTROL			((void *)(DREX0_BASE + 0x0018))
+
+#define DREX0_TICK_GRANULARITY_S0		((void *)(DREX0_BASE + 0x0100))
+#define DREX0_TEMP_SENSING_S0					((void *)(DREX0_BASE + 0x0108))
+#define DREX0_DQS_OSC_CON1_S0					((void *)(DREX0_BASE + 0x0110))
+#define DREX0_TERMINATION_CONTROL_S0			((void *)(DREX0_BASE + 0x0114))
+#define DREX0_WINCONFIG_WRITE_ODT_S0			((void *)(DREX0_BASE + 0x0118))
+#define DREX0_TIMING_ROW0_S0		((void *)(DREX0_BASE + 0x0140))
+#define DREX0_TIMING_ROW1_S0		((void *)(DREX0_BASE + 0x0144))
+#define DREX0_TIMING_DATA_ACLK_S0		((void *)(DREX0_BASE + 0x0148))
+#define DREX0_TIMING_DATA_MCLK_S0			((void *)(DREX0_BASE + 0x014C))
+#define DREX0_TIMING_POWER0_S0		((void *)(DREX0_BASE + 0x0150))
+#define DREX0_TIMING_POWER1_S0		((void *)(DREX0_BASE + 0x0154))
+#define DREX0_TIMING_ETC1_S0	((void *)(DREX0_BASE + 0x015c))
+
+#define DREX0_TICK_GRANULARITY_S1		((void *)(DREX0_BASE + 0x0180))
+#define DREX0_TEMP_SENSING_S1					((void *)(DREX0_BASE + 0x0188))
+#define DREX0_DQS_OSC_CON1_S1					((void *)(DREX0_BASE + 0x0190))
+#define DREX0_TERMINATION_CONTROL_S1			((void *)(DREX0_BASE + 0x0194))
+#define DREX0_WINCONFIG_WRITE_ODT_S1			((void *)(DREX0_BASE + 0x0198))
+#define DREX0_TIMING_ROW0_S1		((void *)(DREX0_BASE + 0x01c0))
+#define DREX0_TIMING_ROW1_S1		((void *)(DREX0_BASE + 0x01c4))
+#define DREX0_TIMING_DATA_ACLK_S1		((void *)(DREX0_BASE + 0x01c8))
+#define DREX0_TIMING_DATA_MCLK_S1			((void *)(DREX0_BASE + 0x01cC))
+#define DREX0_TIMING_POWER0_S1		((void *)(DREX0_BASE + 0x01d0))
+#define DREX0_TIMING_POWER1_S1		((void *)(DREX0_BASE + 0x01d4))
+#define DREX0_TIMING_ETC1_S1	((void *)(DREX0_BASE + 0x01dc))
+
+#define PHY0_CAL_CON0		((void *)(DREXPHY0_BASE + 0x0004))
+#define PHY0_DVFS_CON0		((void *)(DREXPHY0_BASE + 0x00B8))
+#define PHY0_DVFS_CON1		((void *)(DREXPHY0_BASE + 0x00E0))
+#define PHY0_DVFS_CON2		((void *)(DREXPHY0_BASE + 0x00BC))
+#define PHY0_DVFS_CON3		((void *)(DREXPHY0_BASE + 0x00C0))
+#define PHY0_DVFS_CON4		((void *)(DREXPHY0_BASE + 0x00C4))
+#define PHY0_DVFS_CON5		((void *)(DREXPHY0_BASE + 0x00C8))
+#define PHY0_DVFS_CON6		((void *)(DREXPHY0_BASE + 0x00CC))
+#define PHY0_ZQ_CON9	((void *)(DREXPHY0_BASE + 0x03EC))
+
+#define DREX0_PAUSE_MRS0	((void *)(DREX0_BASE + 0x0080))
+#define DREX0_PAUSE_MRS1	((void *)(DREX0_BASE + 0x0084))
+#define DREX0_PAUSE_MRS2	((void *)(DREX0_BASE + 0x0088))
+#define DREX0_PAUSE_MRS3	((void *)(DREX0_BASE + 0x008C))
+#define DREX0_PAUSE_MRS4	((void *)(DREX0_BASE + 0x0090))
+
+#define DREX0_TIMING_SET_SW	((void *)(DREX0_BASE + 0x0020))
+
+#define DREX0_PORT_TICK_GRANULARITY_S0	((void *)(DREX0_PF_BASE + 0x0010))
+#define DREX0_PORT_TICK_GRANULARITY_S1	((void *)(DREX0_PF_BASE + 0x0014))
+
+// PHY DVFS CON SFR BIT DEFINITION /
+#define PHY_DVFS_CON0_SET1_MASK	((0x0)|(1<<31)|(1<<29)|(0x0<<24))
+#define PHY_DVFS_CON0_SET0_MASK	((0x0)|(1<<30)|(1<<28)|(0x0<<24)|(0x7<<21)|(0x7<<18)|(0x7<<15)|(0x7<<12)|(0x7<<9)|(0x7<<6)|(0x7<<3)|(0x7<<0))
+#define PHY_DVFS_CON0_DVFS_MODE_MASK	((0x0)|(0x3<<24))
+#define PHY_DVFS_CON0_DVFS_MODE_POSITION	24
+
+#define PHY_DVFS_CON1_SET1_MASK	((0x7<<21)|(0x7<<18)|(0x7<<15)|(0x7<<12)|(0x7<<9)|(0x7<<6)|(0x7<<3)|(0x7<<0))
+#define PHY_DVFS_CON1_SET0_MASK	((0x0))
+#define PHY_DVFS_CON2_SET1_MASK	((0x0)|(0x1<<31)|(0x1F<<24)|(0xF<<12)|(0xF<<8))
+#define PHY_DVFS_CON2_SET0_MASK	((0x0)|(0x1<<30)|(0x1F<<16)|(0xF<<7)|(0xF<<0))
+#define PHY_DVFS_CON3_SET1_MASK	((0x0)|(0x1<<30)|(0x1<<29)|(0x7<<23)|(0x1<<17)|(0xf<<12)|(0xf<<8))
+#define PHY_DVFS_CON3_SET0_MASK	((0x0)|(0x1<<31)|(0x1<<28)|(0x7<<20)|(0x1<<16)|(0xf<<4)|(0xf<<0))
+#define PHY_DVFS_CON4_SET1_MASK	((0x0)|(0x3F<<18)|(0x3F<<12))
+#define PHY_DVFS_CON4_SET0_MASK	((0x0)|(0x3F<<6)|(0x3F<<0))
+#define PHY_DVFS_CON5_SET1_MASK	((0x0)|(0x7<<24)|(0x7<<16)|(0x7<<8)|(0x7<<0))
+#define PHY_DVFS_CON5_SET0_MASK	((0x0))
+#define PHY_DVFS_CON6_SET1_MASK	((0x0))
+#define PHY_DVFS_CON6_SET0_MASK	((0x0)|(0x7<<24)|(0x7<<16)|(0x7<<8)|(0x7<<0))
+
+#define DREX0_DIRECTCMD		((void *)(DREX0_BASE + 0x001C))
+
+
+#define DREX0_timing_set_sw_con 0 /* Pause triggered from CMU */
+
+#define DQS_OSC_UPDATE_EN 0
+#define PERIODIC_WR_TRAIN 0
+
+#if DQS_OSC_UPDATE_EN
+#define dvfs_dqs_osc_en 1
+#else
+#define dvfs_dqs_osc_en 0
+#endif
+
+#if PERIODIC_WR_TRAIN
+#define dvfs_offset 16
+#else
+#define dvfs_offset 0
+#endif
+
+enum dmc_dvfs_mif_level_idx {
+	DMC_DVFS_MIF_L0,
+	DMC_DVFS_MIF_L1,
+	DMC_DVFS_MIF_L2,
+	DMC_DVFS_MIF_L3,
+	DMC_DVFS_MIF_L4,
+	DMC_DVFS_MIF_L5,
+	DMC_DVFS_MIF_L6,
+	DMC_DVFS_MIF_L7,
+	DMC_DVFS_MIF_L8,
+	COUNT_OF_CMU_DVFS_MIF_LEVEL,
+	CMU_DVFS_MIF_INVALID = 0xFF,
+};
+
+enum dmc_timing_set_idx {
+	DMC_TIMING_SET_0 = 0,
+	DMC_TIMING_SET_1
+};
+
+enum phy_timing_set_idx {
+	PHY_Normal_mode = 0 ,
+	PHY_DVFS0_mode,
+	PHY_DVFS1_mode
+};
+
+enum timing_parameter_column {
+	drex_Tick_Granularity,
+	drex_mr4_sensing_cyc,
+	drex_dqs_osc_start_cyc,
+	drex_Termination_Control,
+	drex_Winconfig_Write_Odt,
+	drex_Timing_Row0,
+	drex_Timing_Row1,
+	drex_Timing_Data_Aclk,
+	drex_Timing_Data_Mclk,
+	drex_Timing_Power0,
+	drex_Timing_Power1,
+	drex_Etcl,
+	drex_Puase_MRS0,
+	drex_Puase_MRS1,
+	drex_Puase_MRS2,
+	drex_Puase_MRS3,
+	drex_Puase_MRS4,
+	phy_Dvfs_Con0_set1,
+	phy_Dvfs_Con0_set0,
+	phy_Dvfs_Con0_set1_mask,
+	phy_Dvfs_Con0_set0_mask,
+	phy_Dvfs_Con1_set1,
+	phy_Dvfs_Con1_set0,
+	phy_Dvfs_Con1_set1_mask,
+	phy_Dvfs_Con1_set0_mask,
+	phy_Dvfs_Con2_set1,
+	phy_Dvfs_Con2_set0,
+	phy_Dvfs_Con2_set1_mask,
+	phy_Dvfs_Con2_set0_mask,
+	phy_Dvfs_Con3_set1,
+	phy_Dvfs_Con3_set0,
+	phy_Dvfs_Con3_set1_mask,
+	phy_Dvfs_Con3_set0_mask,
+	num_of_g_dmc_drex_dfs_mif_table_column = drex_Etcl - drex_Tick_Granularity + 1,
+	num_of_g_dmc_directcmd_dfs_mif_table_column = drex_Puase_MRS4 - drex_Puase_MRS0 + 1,
+	num_of_g_dmc_phy_dfs_mif_table_column = phy_Dvfs_Con3_set0_mask - phy_Dvfs_Con0_set1 + 1,
+	num_of_dram_parameter = num_of_g_dmc_drex_dfs_mif_table_column + num_of_g_dmc_directcmd_dfs_mif_table_column + num_of_g_dmc_phy_dfs_mif_table_column,
+};
+
+struct dmc_drex_dfs_mif_table {
+	unsigned int drex_Tick_Granularity;
+	unsigned int drex_mr4_sensing_cyc;
+	unsigned int drex_dqs_osc_start_cyc;
+	unsigned int drex_Termination_Control;
+	unsigned int drex_Winconfig_Write_Odt;
+	unsigned int drex_Timing_Row0;
+	unsigned int drex_Timing_Row1;
+	unsigned int drex_Timing_Data_Aclk;
+	unsigned int drex_Timing_Data_Mclk;
+	unsigned int drex_Timing_Power0;
+	unsigned int drex_Timing_Power1;
+	unsigned int drex_Etcl;
+};
+
+struct dmc_directcmd_dfs_mif_table {
+	unsigned int drex_Puase_MRS0;
+	unsigned int drex_Puase_MRS1;
+	unsigned int drex_Puase_MRS2;
+	unsigned int drex_Puase_MRS3;
+	unsigned int drex_Puase_MRS4;
+};
+
+struct dmc_phy_dfs_mif_table {
+	unsigned int phy_Dvfs_Con0_set1;
+	unsigned int phy_Dvfs_Con0_set0;
+	unsigned int phy_Dvfs_Con0_set1_mask;
+	unsigned int phy_Dvfs_Con0_set0_mask;
+	unsigned int phy_Dvfs_Con1_set1;
+	unsigned int phy_Dvfs_Con1_set0;
+	unsigned int phy_Dvfs_Con1_set1_mask;
+	unsigned int phy_Dvfs_Con1_set0_mask;
+	unsigned int phy_Dvfs_Con2_set1;
+	unsigned int phy_Dvfs_Con2_set0;
+	unsigned int phy_Dvfs_Con2_set1_mask;
+	unsigned int phy_Dvfs_Con2_set0_mask;
+	unsigned int phy_Dvfs_Con3_set1;
+	unsigned int phy_Dvfs_Con3_set0;
+	unsigned int phy_Dvfs_Con3_set1_mask;
+	unsigned int phy_Dvfs_Con3_set0_mask;
+	unsigned int phy_Dvfs_Con4_set1;
+	unsigned int phy_Dvfs_Con4_set0;
+	unsigned int phy_Dvfs_Con4_set1_mask;
+	unsigned int phy_Dvfs_Con4_set0_mask;
+	unsigned int phy_Dvfs_Con5_set1;
+	unsigned int phy_Dvfs_Con5_set0;
+	unsigned int phy_Dvfs_Con5_set1_mask;
+	unsigned int phy_Dvfs_Con5_set0_mask;
+	unsigned int phy_Dvfs_Con6_set1;
+	unsigned int phy_Dvfs_Con6_set0;
+	unsigned int phy_Dvfs_Con6_set1_mask;
+	unsigned int phy_Dvfs_Con6_set0_mask;
+};
+
+enum dmc_dvfs_mif_switching_level_idx {
+	DMC_DVFS_MIF__switching_L0,
+	DMC_DVFS_MIF__switching_L1,
+};
+
+#define LP4_RL 12
+#define LP4_WL 6
+#define LP4_RL_L10 6
+#define LP4_WL_L10 4
+#define DRAM_RLWL 0x09
+#define DRAM_RLWL_L10 0x00
+
+static struct dmc_drex_dfs_mif_table *pwrcal_dfs_drex_mif_table;
+static struct dmc_directcmd_dfs_mif_table *pwrcal_pause_directcmd_dfs_mif_table;
+static struct dmc_phy_dfs_mif_table *pwrcal_dfs_phy_mif_table;
+
+
+static unsigned long long *mif_freq_to_level;
+static int num_mif_freq_to_level;
+
+
+static unsigned int convert_to_level(unsigned long long freq)
+{
+	int idx;
+	int tablesize = num_mif_freq_to_level;
+
+	for (idx = tablesize - 1; idx >= 0; idx--)
+		if (freq <= mif_freq_to_level[idx])
+			return (unsigned int)idx;
+
+	return 0;
+}
+
+void pwrcal_dmc_set_dvfs(unsigned long long target_mif_freq, unsigned int timing_set_idx)
+{
+	unsigned int uReg;
+//	unsigned int soc_vref[4];
+	unsigned int target_mif_level_idx, target_mif_level_switch_idx;
+	unsigned int offset;
+
+
+	target_mif_level_idx = convert_to_level(target_mif_freq);
+	target_mif_level_switch_idx = convert_to_level(target_mif_freq);
+
+	if (timing_set_idx == DMC_TIMING_SET_0) {
+		for (offset = 0; offset < 0x100000; offset += 0x100000) {
+
+			/* Phy & DREX Mode setting */
+			if (target_mif_level_idx != 0) {
+				uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
+				uReg &= ~(PHY_DVFS_CON0_DVFS_MODE_MASK);
+				uReg |= (PHY_DVFS0_mode<<PHY_DVFS_CON0_DVFS_MODE_POSITION);
+				pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
+			} else {
+				uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
+				uReg &= ~(PHY_DVFS_CON0_DVFS_MODE_MASK);
+				uReg |= (PHY_Normal_mode<<PHY_DVFS_CON0_DVFS_MODE_POSITION);
+				pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
+			}
+
+			pwrcal_writel(offset + DREX0_TIMING_SET_SW, DREX0_timing_set_sw_con);
+			pwrcal_writel((void *)CMU_MIF_BASE + 0x1004,  DMC_TIMING_SET_0); /*cmu pause setting */
+
+			#define PHY_DVFS_CON0_DVFS_MODE_MASK	((0x0)|(0x3<<24))
+			#define PHY_DVFS_CON0_DVFS_MODE_POSITION	24
+
+			pwrcal_writel(offset + DREX0_TICK_GRANULARITY_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Tick_Granularity);
+			pwrcal_writel(offset + DREX0_PORT_TICK_GRANULARITY_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Tick_Granularity);
+			pwrcal_writel(offset + DREX0_TEMP_SENSING_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_mr4_sensing_cyc);
+			pwrcal_writel(offset + DREX0_DQS_OSC_CON1_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_dqs_osc_start_cyc);
+			pwrcal_writel(offset + DREX0_TERMINATION_CONTROL_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Termination_Control);
+			pwrcal_writel(offset + DREX0_WINCONFIG_WRITE_ODT_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Winconfig_Write_Odt);
+			pwrcal_writel(offset + DREX0_TIMING_ROW0_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Row0);
+			pwrcal_writel(offset + DREX0_TIMING_ROW1_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Row1);
+			pwrcal_writel(offset + DREX0_TIMING_DATA_ACLK_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Data_Aclk);
+			pwrcal_writel(offset + DREX0_TIMING_DATA_MCLK_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Data_Mclk);
+			pwrcal_writel(offset + DREX0_TIMING_POWER0_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Power0);
+			pwrcal_writel(offset + DREX0_TIMING_POWER1_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Power1);
+			pwrcal_writel(offset + DREX0_TIMING_ETC1_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Etcl);
+
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
+			uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con0_set0_mask);
+			uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con0_set0;
+			pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
+
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON1);
+			uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con1_set0_mask);
+			uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con1_set0;
+			pwrcal_writel(offset + PHY0_DVFS_CON1, uReg);
+
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON2);
+			uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con2_set0_mask);
+			uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con2_set0;
+			pwrcal_writel(offset + PHY0_DVFS_CON2, uReg);
+
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON3);
+			uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con3_set0_mask);
+			uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con3_set0;
+			pwrcal_writel(offset + PHY0_DVFS_CON3, uReg);
+
+			pwrcal_writel(offset + DREX0_PAUSE_MRS0, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS0);
+			pwrcal_writel(offset + DREX0_PAUSE_MRS1, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS1);
+			pwrcal_writel(offset + DREX0_PAUSE_MRS2, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS2);
+			pwrcal_writel(offset + DREX0_PAUSE_MRS3, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS3);
+			pwrcal_writel(offset + DREX0_PAUSE_MRS4, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS4);
+		}
+
+	} else if (timing_set_idx == DMC_TIMING_SET_1) {
+		for (offset = 0; offset < 0x100000; offset += 0x100000) {
+
+			/* Phy & DREX Mode setting */
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
+			uReg &= ~(PHY_DVFS_CON0_DVFS_MODE_MASK);
+			uReg |= (PHY_DVFS1_mode<<PHY_DVFS_CON0_DVFS_MODE_POSITION);
+			pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
+
+			pwrcal_writel(offset + DREX0_TIMING_SET_SW,  DREX0_timing_set_sw_con);
+			pwrcal_writel((void *)CMU_MIF_BASE + 0x1004,  DMC_TIMING_SET_1); /*cmu pause setting */
+
+			pwrcal_writel(offset + DREX0_TICK_GRANULARITY_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Tick_Granularity);
+			pwrcal_writel(offset + DREX0_PORT_TICK_GRANULARITY_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Tick_Granularity);
+			pwrcal_writel(offset + DREX0_TEMP_SENSING_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_mr4_sensing_cyc);
+			pwrcal_writel(offset + DREX0_DQS_OSC_CON1_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_dqs_osc_start_cyc);
+			pwrcal_writel(offset + DREX0_TERMINATION_CONTROL_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Termination_Control);
+			pwrcal_writel(offset + DREX0_WINCONFIG_WRITE_ODT_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Winconfig_Write_Odt);
+			pwrcal_writel(offset + DREX0_TIMING_ROW0_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Row0);
+			pwrcal_writel(offset + DREX0_TIMING_ROW1_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Row1);
+			pwrcal_writel(offset + DREX0_TIMING_DATA_ACLK_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Data_Aclk);
+			pwrcal_writel(offset + DREX0_TIMING_DATA_MCLK_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Data_Mclk);
+			pwrcal_writel(offset + DREX0_TIMING_POWER0_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Power0);
+			pwrcal_writel(offset + DREX0_TIMING_POWER1_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Power1);
+			pwrcal_writel(offset + DREX0_TIMING_ETC1_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Etcl);
+
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
+			uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con0_set1_mask);
+			uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con0_set1;
+			pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
+
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON1);
+			uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con1_set1_mask);
+			uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con1_set1;
+			pwrcal_writel(offset + PHY0_DVFS_CON1, uReg);
+
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON2);
+			uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con2_set1_mask);
+			uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con2_set1;
+			pwrcal_writel(offset + PHY0_DVFS_CON2, uReg);
+
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON3);
+			uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con3_set1_mask);
+			uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con3_set1;
+			pwrcal_writel(offset + PHY0_DVFS_CON3, uReg);
+
+			pwrcal_writel(offset + DREX0_PAUSE_MRS0, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS0);
+			pwrcal_writel(offset + DREX0_PAUSE_MRS1, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS1);
+			pwrcal_writel(offset + DREX0_PAUSE_MRS2, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS2);
+			pwrcal_writel(offset + DREX0_PAUSE_MRS3, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS3);
+			pwrcal_writel(offset + DREX0_PAUSE_MRS4, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS4);
+		}
+	} else {
+		pr_err("wrong DMC timing set selection on DVFS\n");
+		return;
+	}
+}
+
+void pwrcal_dmc_set_pre_dvfs(void)
+{
+
+}
+
+void pwrcal_dmc_set_post_dvfs(unsigned long long target_freq)
+{
+
+}
+
+
+
+void pwrcal_dmc_set_refresh_method_pre_dvfs(unsigned long long current_rate, unsigned long long target_rate)
+{
+	/* target_rate is MIF clock rate */
+	unsigned int uReg;
+	uReg = pwrcal_readl(DREX0_CG_CONTROL);
+	uReg = ((uReg & ~(1 << 24)) | (0 << 24));
+	pwrcal_writel(DREX0_CG_CONTROL, uReg);	//External Clock Gating - PHY Clock Gating disable
+}
+
+void pwrcal_dmc_set_refresh_method_post_dvfs(unsigned long long current_rate, unsigned long long target_rate)
+{
+	/* target_rate is MIF clock rate */
+	unsigned int uReg;
+	uReg = pwrcal_readl(DREX0_CG_CONTROL);
+	uReg = ((uReg & ~(1 << 24)) | (1 << 24));
+	pwrcal_writel(DREX0_CG_CONTROL, uReg);	//External Clock Gating - PHY Clock Gating enable
+}
+
+void pwrcal_dmc_set_dsref_cycle(unsigned long long target_rate)
+{
+	unsigned int  uReg, cycle;
+
+	/* target_rate is MIF clock rate */
+	if (target_rate > 800 * MHZ)
+		cycle = 0x3ff;
+	else if (target_rate > 400 * MHZ)
+		cycle = 0x1ff;
+	else if (target_rate > 200 * MHZ)
+		cycle = 0x90;
+	else
+		cycle = 0x90;
+
+	/* dsref disable */
+	uReg = pwrcal_readl(DREX0_MEMORY_CONTROL0);
+	uReg &= ~(1 << 4);
+	pwrcal_writel(DREX0_MEMORY_CONTROL0, uReg);
+
+	uReg = pwrcal_readl(DREX0_POWER_DOWN_CONFIG);
+	uReg = ((uReg & ~(0xffff << 16)) | (cycle << 16));
+	pwrcal_writel(DREX0_POWER_DOWN_CONFIG, uReg);
+
+	/* dsref enable */
+	uReg = pwrcal_readl(DREX0_MEMORY_CONTROL0);
+	uReg |= (1 << 4);
+	pwrcal_writel(DREX0_MEMORY_CONTROL0, uReg);
+}
+
+
+
+void dfs_dram_param_init(void)
+{
+	int i;
+	void *dram_block;
+	u32 uMem_type;
+//	int memory_size = 2; // means 3GB
+	struct ect_timing_param_size *size;
+
+//	uMem_type = (pwrcal_readl(DREX_CALIBRATION2) & 0xFFFF);
+	uMem_type = 2; // 2GB
+
+	dram_block = ect_get_block(BLOCK_TIMING_PARAM);
+	if (dram_block == NULL)
+		return;
+
+	size = ect_timing_param_get_size(dram_block, uMem_type);
+	if (size == NULL)
+		return;
+
+	if (num_of_dram_parameter != size->num_of_timing_param)
+		return;
+
+	pwrcal_dfs_drex_mif_table = kzalloc(sizeof(struct dmc_drex_dfs_mif_table) * num_of_g_dmc_drex_dfs_mif_table_column * size->num_of_level, GFP_KERNEL);
+	if (pwrcal_dfs_drex_mif_table == NULL)
+		return;
+
+	pwrcal_pause_directcmd_dfs_mif_table = kzalloc(sizeof(struct dmc_directcmd_dfs_mif_table) * num_of_g_dmc_directcmd_dfs_mif_table_column * size->num_of_level, GFP_KERNEL);
+	if (pwrcal_pause_directcmd_dfs_mif_table == NULL)
+		return;
+
+	pwrcal_dfs_phy_mif_table = kzalloc(sizeof(struct dmc_phy_dfs_mif_table) * num_of_g_dmc_phy_dfs_mif_table_column * size->num_of_level, GFP_KERNEL);
+	if (pwrcal_dfs_phy_mif_table == NULL)
+		return;
+
+	for (i = 0; i < size->num_of_level; ++i) {
+		pwrcal_dfs_drex_mif_table[i].drex_Tick_Granularity = size->timing_parameter[i * num_of_dram_parameter + drex_Tick_Granularity];
+		pwrcal_dfs_drex_mif_table[i].drex_mr4_sensing_cyc = size->timing_parameter[i * num_of_dram_parameter + drex_mr4_sensing_cyc];
+		pwrcal_dfs_drex_mif_table[i].drex_dqs_osc_start_cyc = size->timing_parameter[i * num_of_dram_parameter + drex_dqs_osc_start_cyc];
+		pwrcal_dfs_drex_mif_table[i].drex_Termination_Control = size->timing_parameter[i * num_of_dram_parameter + drex_Termination_Control];
+		pwrcal_dfs_drex_mif_table[i].drex_Winconfig_Write_Odt = size->timing_parameter[i * num_of_dram_parameter + drex_Winconfig_Write_Odt];
+		pwrcal_dfs_drex_mif_table[i].drex_Timing_Row0 = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Row0];
+		pwrcal_dfs_drex_mif_table[i].drex_Timing_Row1 = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Row1];
+		pwrcal_dfs_drex_mif_table[i].drex_Timing_Data_Aclk = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Data_Aclk];
+		pwrcal_dfs_drex_mif_table[i].drex_Timing_Data_Mclk = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Data_Mclk];
+		pwrcal_dfs_drex_mif_table[i].drex_Timing_Power0 = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Power0];
+		pwrcal_dfs_drex_mif_table[i].drex_Timing_Power1 = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Power1];
+		pwrcal_dfs_drex_mif_table[i].drex_Etcl = size->timing_parameter[i * num_of_dram_parameter + drex_Etcl];
+
+		pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS0 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS0];
+		pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS1 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS1];
+		pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS2 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS2];
+		pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS3 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS3];
+		pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS4 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS4];
+
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con0_set1 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con0_set1];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con0_set0 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con0_set0];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con0_set1_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con0_set1_mask];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con0_set0_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con0_set0_mask];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con1_set1 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con1_set1];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con1_set0 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con1_set0];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con1_set1_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con1_set1_mask];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con1_set0_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con1_set0_mask];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con2_set1 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con2_set1];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con2_set0 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con2_set0];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con2_set1_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con2_set1_mask];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con2_set0_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con2_set0_mask];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con3_set1 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con3_set1];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con3_set0 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con3_set0];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con3_set1_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con3_set1_mask];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con3_set0_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con3_set0_mask];
+	}
+}
+
+void dfs_mif_level_init(void)
+{
+	int i;
+	void *dvfs_block;
+	struct ect_dvfs_domain *domain;
+
+	dvfs_block = ect_get_block(BLOCK_DVFS);
+	if (dvfs_block == NULL)
+		return;
+
+	domain = ect_dvfs_get_domain(dvfs_block, vclk_dvfs_mif.vclk.name);
+	if (domain == NULL)
+		return;
+
+	mif_freq_to_level = kzalloc(sizeof(unsigned long long) * domain->num_of_level, GFP_KERNEL);
+	if (mif_freq_to_level == NULL)
+		return;
+
+	num_mif_freq_to_level = domain->num_of_level;
+
+	for (i = 0; i < domain->num_of_level; ++i)
+		mif_freq_to_level[i] = domain->list_level[i].level * KHZ;
+}
+
+void dfs_dram_init(void)
+{
+	dfs_dram_param_init();
+	dfs_mif_level_init();
+}
+

drivers/soc/samsung/pwrcal/S5E7570/S5E7570-pll.c

@@ -0,0 +1,864 @@
+#include "../pwrcal.h"
+#include "../pwrcal-clk.h"
+#include "../pwrcal-env.h"
+#include "../pwrcal-rae.h"
+#include "../pwrcal-pmu.h"
+#include "S5E7570-cmusfr.h"
+#include "S5E7570-pmusfr.h"
+#include "S5E7570-cmu.h"
+
+/* PLLs */
+/* PLL141XX Clock Type */
+#define PLL141XX_MDIV_SHIFT		16
+#define PLL141XX_PDIV_SHIFT		8
+#define PLL141XX_SDIV_SHIFT		0
+#define PLL141XX_MDIV_MASK		0x3FF
+#define PLL141XX_PDIV_MASK		0x3F
+#define PLL141XX_SDIV_MASK		0x7
+#define PLL141XX_ENABLE			31
+#define PLL141XX_LOCKED			29
+#define PLL141XX_BYPASS			22
+
+/* PLL1431X Clock Type */
+#define PLL1431X_MDIV_SHIFT		16
+#define PLL1431X_PDIV_SHIFT		8
+#define PLL1431X_SDIV_SHIFT		0
+#define PLL1431X_K_SHIFT		0
+#define PLL1431X_MDIV_MASK		0x3FF
+#define PLL1431X_PDIV_MASK		0x3F
+#define PLL1431X_SDIV_MASK		0x7
+#define PLL1431X_K_MASK		0xFFFF
+#define PLL1431X_ENABLE			31
+#define PLL1431X_LOCKED			29
+#define PLL1431X_BYPASS			4
+
+/* WPLL_USB_PLL Clock Type */
+#define WIFI2AP_USBPLL_ACK	1
+#define AP2WIFI_USBPLL_REQ	0
+#define AP2WLBT_SR7 ((void *)(0x1058009C))
+
+#define USBPLL_WPLL_FREF_SEL	3
+#define USBPLL_WPLL_AFC_START	2
+#define USBPLL_WPLL_EN	1
+#define USBPLL_WPLL_SEL	0
+
+#define FIN_HZ_26M		(26*MHZ)
+
+static const struct pwrcal_pll_rate_table *_clk_get_pll_settings(
+					struct pwrcal_pll *pll_clk,
+					unsigned long long rate)
+{
+	int i;
+	const struct pwrcal_pll_rate_table  *prate_table = pll_clk->rate_table;
+
+	for (i = 0; i < pll_clk->rate_count; i++) {
+		if (rate == prate_table[i].rate)
+			return &prate_table[i];
+	}
+
+	return NULL;
+}
+
+static int _clk_pll141xx_find_pms(struct pll_spec *pll_spec,
+				struct pwrcal_pll_rate_table *rate_table,
+				unsigned long long rate)
+{
+	unsigned int p, m, s;
+	unsigned long long fref, fvco, fout;
+	unsigned long long tmprate, tmpfout = 0;
+	unsigned long long mindiffrate = 0xFFFFFFFFFFFFFFFF;
+	unsigned int min_p = 0, min_m = 0, min_s = 0, min_fout = 0;
+
+	for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
+		fref = FIN_HZ_26M / p;
+		if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
+			continue;
+
+		for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
+			tmprate = rate;
+			do_div(tmprate, KHZ);
+			tmprate = tmprate * p * (1 << s);
+			do_div(tmprate, (FIN_HZ_26M / KHZ));
+			m = (unsigned int)tmprate;
+
+			if ((m < pll_spec->mdiv_min)
+					|| (m > pll_spec->mdiv_max))
+				continue;
+
+			fvco = ((unsigned long long)FIN_HZ_26M) * m;
+			do_div(fvco, p);
+			if ((fvco < pll_spec->fvco_min)
+					|| (fvco > pll_spec->fvco_max))
+				continue;
+
+			fout = fvco >> s;
+			if ((fout >= pll_spec->fout_min)
+					&& (fout <= pll_spec->fout_max)) {
+				tmprate = rate;
+				do_div(tmprate, KHZ);
+				tmpfout = fout;
+				do_div(tmpfout, KHZ);
+				if (tmprate == tmpfout) {
+					rate_table->rate = fout;
+					rate_table->pdiv = p;
+					rate_table->mdiv = m;
+					rate_table->sdiv = s;
+					rate_table->kdiv = 0;
+					return 0;
+				}
+				if (tmpfout < tmprate && mindiffrate > tmprate - tmpfout) {
+					mindiffrate = tmprate - tmpfout;
+					min_fout = fout;
+					min_p = p;
+					min_m = m;
+					min_s = s;
+				}
+			}
+		}
+	}
+
+	if (mindiffrate != 0xFFFFFFFFFFFFFFFF) {
+		rate_table->rate = min_fout;
+		rate_table->pdiv = min_p;
+		rate_table->mdiv = min_m;
+		rate_table->sdiv = min_s;
+		rate_table->kdiv = 0;
+		return 0;
+	}
+	return -1;
+}
+
+
+static int _clk_pll1419x_find_pms(struct pll_spec *pll_spec,
+				struct pwrcal_pll_rate_table *rate_table,
+				unsigned long long rate)
+{
+	unsigned int p, m, s;
+	unsigned long long fref, fvco, fout;
+	unsigned long long tmprate, tmpfout = 0;
+	unsigned long long mindiffrate = 0xFFFFFFFFFFFFFFFF;
+	unsigned int min_p = 0, min_m = 0, min_s = 0, min_fout = 0;
+
+	for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
+		fref = FIN_HZ_26M / p;
+		if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
+			continue;
+
+		for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
+			/*tmprate = rate;*/
+			tmprate = rate/2; /*for PLL1419*/
+			do_div(tmprate, KHZ);
+			tmprate = tmprate * p * (1 << s);
+			do_div(tmprate, (FIN_HZ_26M / KHZ));
+			m = (unsigned int)tmprate;
+
+			if ((m < pll_spec->mdiv_min)
+					|| (m > pll_spec->mdiv_max))
+				continue;
+
+			fvco = ((unsigned long long)FIN_HZ_26M) * m;
+			do_div(fvco, p);
+			if ((fvco < pll_spec->fvco_min)
+					|| (fvco > pll_spec->fvco_max))
+				continue;
+
+			fout = fvco >> s;
+			if ((fout >= pll_spec->fout_min)
+					&& (fout <= pll_spec->fout_max)) {
+				tmprate = rate;
+				do_div(tmprate, KHZ);
+				tmpfout = fout;
+				do_div(tmpfout, KHZ);
+				if (tmprate == tmpfout) {
+					rate_table->rate = fout;
+					rate_table->pdiv = p;
+					rate_table->mdiv = m;
+					rate_table->sdiv = s;
+					rate_table->kdiv = 0;
+					return 0;
+				}
+			}
+			if (tmpfout < tmprate && mindiffrate > tmprate - tmpfout) {
+				mindiffrate = tmprate - tmpfout;
+				min_fout = fout;
+				min_p = p;
+				min_m = m;
+				min_s = s;
+			}
+		}
+	}
+
+	if (mindiffrate != 0xFFFFFFFFFFFFFFFF) {
+		rate_table->rate = min_fout;
+		rate_table->pdiv = min_p;
+		rate_table->mdiv = min_m;
+		rate_table->sdiv = min_s;
+		rate_table->kdiv = 0;
+		return 0;
+	}
+	return -1;
+}
+
+static int _clk_pll141xx_is_enabled(struct pwrcal_clk *clk)
+{
+	return (int)(pwrcal_getbit(clk->offset, PLL141XX_ENABLE));
+}
+
+static int _clk_pll141xx_enable(struct pwrcal_clk *clk)
+{
+	int timeout;
+
+	pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 1);
+
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+static int _clk_pll1419x_enable(struct pwrcal_clk *clk)
+{
+	int timeout;
+
+	pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 1);
+
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+static int _clk_pll141xx_disable(struct pwrcal_clk *clk)
+{
+	pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 0);
+
+	return 0;
+}
+
+int _clk_pll141xx_is_disabled_bypass(struct pwrcal_clk *clk)
+{
+	if (pwrcal_getbit(clk->offset + 1, PLL141XX_BYPASS))
+		return 0;
+
+	return 1;
+}
+
+
+int _clk_pll141xx_set_bypass(struct pwrcal_clk *clk, int bypass_disable)
+{
+	if (bypass_disable == 0)
+		pwrcal_setbit(clk + 1, PLL141XX_BYPASS, 1);
+	else
+		pwrcal_setbit(clk + 1, PLL141XX_BYPASS, 0);
+
+	return 0;
+}
+
+static int _clk_pll141xx_set_pms(struct pwrcal_clk *clk,
+				const struct pwrcal_pll_rate_table  *rate_table)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0;
+
+	int timeout;
+
+	pdiv = rate_table->pdiv;
+	mdiv = rate_table->mdiv;
+	sdiv = rate_table->sdiv;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	pll_con0 &= ~((PLL141XX_MDIV_MASK << PLL141XX_MDIV_SHIFT)
+			| (PLL141XX_PDIV_MASK << PLL141XX_PDIV_SHIFT)
+			| (PLL141XX_SDIV_MASK << PLL141XX_SDIV_SHIFT));
+	pll_con0 |=  (mdiv << PLL141XX_MDIV_SHIFT)
+			| (pdiv << PLL141XX_PDIV_SHIFT)
+			| (sdiv << PLL141XX_SDIV_SHIFT);
+	pll_con0 &= ~(1<<26);
+	pll_con0 |= (1<<5);
+
+	pwrcal_writel(clk->status, pdiv*150);
+	pwrcal_writel(clk->offset, pll_con0);
+
+	if (pll_con0 & (1 << PLL141XX_ENABLE)) {
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+	}
+
+	return 0;
+
+}
+
+static int _clk_pll1419x_set_pms(struct pwrcal_clk *clk,
+				const struct pwrcal_pll_rate_table  *rate_table)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0;
+
+	int timeout;
+
+	pdiv = rate_table->pdiv;
+	mdiv = rate_table->mdiv;
+	sdiv = rate_table->sdiv;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	pll_con0 &= ~((PLL141XX_MDIV_MASK << PLL141XX_MDIV_SHIFT)
+			| (PLL141XX_PDIV_MASK << PLL141XX_PDIV_SHIFT)
+			| (PLL141XX_SDIV_MASK << PLL141XX_SDIV_SHIFT));
+	pll_con0 |=  (mdiv << PLL141XX_MDIV_SHIFT)
+			| (pdiv << PLL141XX_PDIV_SHIFT)
+			| (sdiv << PLL141XX_SDIV_SHIFT);
+
+	pwrcal_writel(clk->status, pdiv * 150);
+	pwrcal_writel(clk->offset, pll_con0);
+
+	if (pll_con0 & (1 << PLL141XX_ENABLE)) {
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+	}
+
+	return 0;
+}
+
+static int _clk_pll141xx_set_rate(struct pwrcal_clk *clk,
+					unsigned long long rate)
+{
+	struct pwrcal_pll *pll = to_pll(clk);
+	struct pll_spec *pll_spec;
+	struct pwrcal_pll_rate_table  tmp_rate_table;
+	const struct pwrcal_pll_rate_table  *rate_table;
+
+	if (rate == 0) {
+		if (_clk_pll141xx_is_enabled(clk) != 0)
+			if (_clk_pll141xx_disable(clk))
+				goto errorout;
+		return 0;
+	}
+
+	rate_table = _clk_get_pll_settings(pll, rate);
+	if (rate_table == NULL) {
+		pll_spec = clk_pll_get_spec(clk);
+		if (pll_spec == NULL)
+			goto errorout;
+
+		if (_clk_pll141xx_find_pms(pll_spec, &tmp_rate_table, rate)) {
+			pr_err("can't find pms value for rate(%lldHz) of \'%s\'",
+				rate,
+				clk->name);
+			goto errorout;
+		}
+
+		rate_table = &tmp_rate_table;
+
+		pr_warn("not exist in rate table, p(%d), m(%d), s(%d), fout(%lldHz) %s",
+				rate_table->pdiv,
+				rate_table->mdiv,
+				rate_table->sdiv,
+				rate,
+				clk->name);
+	}
+
+	if (_clk_pll141xx_set_pms(clk, rate_table))
+		goto errorout;
+
+	if (rate != 0) {
+		if (_clk_pll141xx_is_enabled(clk) == 0)
+			_clk_pll141xx_enable(clk);
+	}
+	return 0;
+
+errorout:
+	return -1;
+}
+
+static int _clk_pll1419x_set_rate(struct pwrcal_clk *clk,
+					unsigned long long rate)
+{
+	struct pwrcal_pll *pll = to_pll(clk);
+	struct pll_spec *pll_spec;
+	struct pwrcal_pll_rate_table  tmp_rate_table;
+	const struct pwrcal_pll_rate_table  *rate_table;
+
+	if (rate == 0) {
+		if (_clk_pll141xx_is_enabled(clk) != 0)
+			if (_clk_pll141xx_disable(clk))
+				goto errorout;
+		return 0;
+	}
+
+	rate_table = _clk_get_pll_settings(pll, rate);
+	if (rate_table == NULL) {
+		pll_spec = clk_pll_get_spec(clk);
+		if (pll_spec == NULL)
+			goto errorout;
+
+		if (_clk_pll1419x_find_pms(pll_spec, &tmp_rate_table, rate)) {
+			pr_err("can't find pms value for rate(%lldHz) of \'%s\'",
+				rate,
+				clk->name);
+			goto errorout;
+		}
+
+		rate_table = &tmp_rate_table;
+
+		pr_warn("not exist in rate table, p(%d), m(%d), s(%d), fout(%lldHz) %s",
+				rate_table->pdiv,
+				rate_table->mdiv,
+				rate_table->sdiv,
+				rate,
+				clk->name);
+	}
+
+	_clk_pll141xx_disable(clk);
+
+	if (_clk_pll1419x_set_pms(clk, rate_table))
+		goto errorout;
+
+	if (rate != 0) {
+		if (_clk_pll141xx_is_enabled(clk) == 0)
+			_clk_pll1419x_enable(clk);
+	}
+	return 0;
+
+errorout:
+	return -1;
+}
+
+static unsigned long long _clk_pll141xx_get_rate(struct pwrcal_clk *clk)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0;
+	unsigned long long fout;
+
+	if (_clk_pll141xx_is_enabled(clk) == 0)
+		return 0;
+	pll_con0 = pwrcal_readl(clk->offset);
+	mdiv = (pll_con0 >> PLL141XX_MDIV_SHIFT) & PLL141XX_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL141XX_PDIV_SHIFT) & PLL141XX_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL141XX_SDIV_SHIFT) & PLL141XX_SDIV_MASK;
+
+	if (pdiv == 0) {
+		pr_err("pdiv is 0, id(%s)", clk->name);
+		return 0;
+	}
+	fout = FIN_HZ_26M * mdiv;
+	do_div(fout, (pdiv << sdiv));
+	return (unsigned long long)fout;
+}
+
+static unsigned long long _clk_pll1419x_get_rate(struct pwrcal_clk *clk)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0;
+	unsigned long long fout;
+
+	if (_clk_pll141xx_is_enabled(clk) == 0)
+		return 0;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	mdiv = (pll_con0 >> PLL141XX_MDIV_SHIFT) & PLL141XX_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL141XX_PDIV_SHIFT) & PLL141XX_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL141XX_SDIV_SHIFT) & PLL141XX_SDIV_MASK;
+
+	if (pdiv == 0) {
+		pr_err("pdiv is 0, id(%s)", clk->name);
+		return 0;
+	}
+	fout = FIN_HZ_26M * 2 * mdiv;
+	do_div(fout, (pdiv << sdiv));
+	return (unsigned long long)fout;
+}
+
+static int _clk_pll1431x_find_pms(struct pll_spec *pll_spec,
+					struct pwrcal_pll_rate_table *rate_table,
+					unsigned long long rate)
+{
+	unsigned int p, m, s;
+	signed short k;
+	unsigned long long fref, fvco, fout;
+	unsigned long long tmprate, tmpfout;
+
+	for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
+		fref = FIN_HZ_26M / p;
+		if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
+			continue;
+
+		for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
+			tmprate = rate;
+			do_div(tmprate, KHZ);
+			tmprate = tmprate * p * (1 << s);
+			do_div(tmprate, (FIN_HZ_26M / KHZ));
+			m = (unsigned int)tmprate;
+
+			if ((m < pll_spec->mdiv_min)
+					|| (m > pll_spec->mdiv_max))
+				continue;
+
+			tmprate = rate;
+			do_div(tmprate, KHZ);
+			tmprate = tmprate * p * (1 << s);
+			do_div(tmprate, (FIN_HZ_26M / KHZ));
+			tmprate = (tmprate - m) * 65536;
+			k = (unsigned int)tmprate;
+			if ((k < pll_spec->kdiv_min)
+					|| (k > pll_spec->kdiv_max))
+				continue;
+
+			fvco = FIN_HZ_26M * ((m << 16) + k);
+			do_div(fvco, p);
+			fvco >>= 16;
+			if ((fvco < pll_spec->fvco_min)
+					|| (fvco > pll_spec->fvco_max))
+				continue;
+
+			fout = fvco >> s;
+			if ((fout >= pll_spec->fout_min)
+				&& (fout <= pll_spec->fout_max)) {
+				tmprate = rate;
+				do_div(tmprate, KHZ);
+				tmpfout = fout;
+				do_div(tmpfout, KHZ);
+				if (tmprate == tmpfout) {
+					rate_table->rate = fout;
+					rate_table->pdiv = p;
+					rate_table->mdiv = m;
+					rate_table->sdiv = s;
+					rate_table->kdiv = k;
+					return 0;
+				}
+			}
+		}
+	}
+
+	return -1;
+}
+
+static int _clk_pll1431x_is_enabled(struct pwrcal_clk *clk)
+{
+	return (int)(pwrcal_getbit(clk->offset, PLL1431X_ENABLE));
+}
+
+static int _clk_pll1431x_enable(struct pwrcal_clk *clk)
+{
+	int timeout;
+
+	pwrcal_setbit(clk->offset, PLL1431X_ENABLE, 1);
+
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(clk->offset, PLL1431X_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+static int _clk_pll1431x_disable(struct pwrcal_clk *clk)
+{
+	pwrcal_setbit(clk->offset, PLL1431X_ENABLE, 0);
+
+	return 0;
+}
+
+int _clk_pll1431x_is_disabled_bypass(struct pwrcal_clk *clk)
+{
+	if (pwrcal_getbit(clk->offset + 2, PLL1431X_BYPASS))
+		return 0;
+
+	return 1;
+}
+
+int _clk_pll1431x_set_bypass(struct pwrcal_clk *clk, int bypass_disable)
+{
+	if (bypass_disable == 0)
+		pwrcal_setbit(clk->offset + 2, PLL1431X_BYPASS, 1);
+	else
+		pwrcal_setbit(clk->offset + 2, PLL1431X_BYPASS, 0);
+
+	return 0;
+}
+
+static int _clk_pll1431x_set_pms(struct pwrcal_clk *clk,
+			const struct pwrcal_pll_rate_table  *rate_table)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0, pll_con1;
+	signed short kdiv;
+	int timeout;
+
+	pdiv = rate_table->pdiv;
+	mdiv = rate_table->mdiv;
+	sdiv = rate_table->sdiv;
+	kdiv = rate_table->kdiv;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	pll_con1 = pwrcal_readl(clk->offset + 1);
+	pll_con0 &= ~((PLL1431X_MDIV_MASK << PLL1431X_MDIV_SHIFT)
+			| (PLL1431X_PDIV_MASK << PLL1431X_PDIV_SHIFT)
+			| (PLL1431X_SDIV_MASK << PLL1431X_SDIV_SHIFT));
+	pll_con0 |=  (mdiv << PLL1431X_MDIV_SHIFT)
+			| (pdiv << PLL1431X_PDIV_SHIFT)
+			| (sdiv << PLL1431X_SDIV_SHIFT);
+	pll_con0 &= ~(1<<26);
+	pll_con0 |= (1<<5);
+
+	pll_con1 &= ~(PLL1431X_K_MASK << PLL1431X_K_SHIFT);
+	pll_con1 |=  (kdiv << PLL1431X_K_SHIFT);
+
+	if (kdiv == 0)
+		pwrcal_writel(clk->status, pdiv*3000);
+	else
+		pwrcal_writel(clk->status, pdiv*3000);
+	pwrcal_writel(clk->offset, pll_con0);
+	pwrcal_writel(clk->offset + 1, pll_con1);
+
+	if (pll_con0 & (1 << PLL1431X_ENABLE)) {
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(clk->offset, PLL1431X_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+	}
+
+	return 0;
+}
+
+static int _clk_pll1431x_set_rate(struct pwrcal_clk *clk,
+					unsigned long long rate)
+{
+	struct pwrcal_pll *pll = to_pll(clk);
+	struct pwrcal_pll_rate_table  tmp_rate_table;
+	const struct pwrcal_pll_rate_table  *rate_table;
+	struct pll_spec *pll_spec;
+
+	if (rate == 0) {
+		if (_clk_pll1431x_is_enabled(clk) != 0)
+			if (_clk_pll1431x_disable(clk))
+				goto errorout;
+		return 0;
+	}
+
+	rate_table = _clk_get_pll_settings(pll, rate);
+	if (rate_table == NULL) {
+		pll_spec = clk_pll_get_spec(clk);
+		if (pll_spec == NULL)
+			goto errorout;
+
+		if (_clk_pll1431x_find_pms(pll_spec, &tmp_rate_table, rate) < 0) {
+			pr_err("can't find pms value for rate(%lldHz) of %s",
+				rate,
+				clk->name);
+			goto errorout;
+		}
+
+		rate_table = &tmp_rate_table;
+		pr_warn("not exist in rate table, p(%d) m(%d) s(%d) k(%d) fout(%lld Hz) of %s",
+				rate_table->pdiv,
+				rate_table->mdiv,
+				rate_table->sdiv,
+				rate_table->kdiv,
+				rate,
+				clk->name);
+	}
+
+	if (_clk_pll1431x_set_pms(clk, rate_table))
+		goto errorout;
+
+	if (rate != 0) {
+		if (_clk_pll1431x_is_enabled(clk) == 0)
+			_clk_pll1431x_enable(clk);
+	}
+
+	return 0;
+
+errorout:
+	return -1;
+}
+
+static unsigned long long _clk_pll1431x_get_rate(struct pwrcal_clk *clk)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0, pll_con1;
+	signed short kdiv;
+	unsigned long long fout;
+
+	if (_clk_pll1431x_is_enabled(clk) == 0)
+		return 0;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	pll_con1 = pwrcal_readl(clk->offset + 1);
+	mdiv = (pll_con0 >> PLL1431X_MDIV_SHIFT) & PLL1431X_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL1431X_PDIV_SHIFT) & PLL1431X_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL1431X_SDIV_SHIFT) & PLL1431X_SDIV_MASK;
+
+	kdiv = (short)(pll_con1 >> PLL1431X_K_SHIFT) & PLL1431X_K_MASK;
+
+	if (pdiv == 0) {
+		pr_err("pdiv is 0, id(%s)", clk->name);
+		return 0;
+	}
+
+	fout = FIN_HZ_26M * ((mdiv << 16) + kdiv);
+	do_div(fout, (pdiv << sdiv));
+	fout >>= 16;
+
+	return (unsigned long long)fout;
+}
+
+static int _clk_wpll_usbpll_is_enabled(struct pwrcal_clk *clk)
+{
+	if (pwrcal_getbit(clk->offset, USBPLL_WPLL_SEL) == 1) {
+		pr_err("%s: USBPLL_WPLL_SEL==1\n", __func__);
+		return (int)(pwrcal_getbit(clk->offset, USBPLL_WPLL_EN));
+	}
+	pr_err("%s: USBPLL_WPLL_SEL==0\n", __func__);
+	return (int)pwrcal_getbit(clk->status, WIFI2AP_USBPLL_ACK);
+}
+
+static int _clk_wpll_usbpll_enable(struct pwrcal_clk *clk)
+{
+	int timeout;
+
+	/* check changed WPLL input selection to AP (AP2WLBT_USBPLL_WPLL_SEL). */
+	if (pwrcal_getbit(clk->offset, USBPLL_WPLL_SEL) == 0x1) {
+		pr_info("%s AP %p\n", __func__, clk->offset);
+
+		if (pwrcal_getbit(clk->offset, USBPLL_WPLL_EN) == 0x1) {
+			pr_info("%s USBPLL_WPLL_EN==1\n", __func__);
+			return 0;
+		}
+
+		/* pwrcal_setbit(clk->offset, 0, 0x1); */
+		if (pwrcal_getbit(TCXO_SHARED_STATUS, 8) == 1)
+			pwrcal_setbit(clk->offset, USBPLL_WPLL_FREF_SEL, 0x1); /* TCXO_SHARED_STATUS = 52Mhz */
+		else
+			pwrcal_setbit(clk->offset, USBPLL_WPLL_FREF_SEL, 0x0); /* 26Mhz */
+
+		/* Set WPLL enable (AP2WLBT_USBPLL_WPLL_EN) */
+		pwrcal_setbit(clk->offset, USBPLL_WPLL_EN, 0x1);
+
+		/* wait 20us for power settle time. */
+		for (timeout = 0;; timeout++) {
+			if (timeout >= 20)
+				break;
+			cpu_relax();
+		}
+
+		/* Set WPLL AFC Start (AP2WLBT_USBPLL_WPLL_AFC_START) */
+		pwrcal_setbit(clk->offset, USBPLL_WPLL_AFC_START, 0x1);
+
+		/* wait 60us for clock stabilization. */
+		for (timeout = 0;; timeout++) {
+			if (timeout >= 60)
+				break;
+			cpu_relax();
+		}
+
+	} else {
+		pr_info("%s WLBT\n", __func__);
+
+		/* WPLL input selection to WLBT */
+
+		/* (IP) use ack */
+		if (pwrcal_getbit(clk->status, WIFI2AP_USBPLL_ACK) == 0x1) {
+			pr_info("%s USBPLL_ACK==1, already\n", __func__);
+			return 0;
+		}
+
+		/* AP2WIFI_USBPLL_REQ */
+		pwrcal_setbit(clk->status, AP2WIFI_USBPLL_REQ, 0x1);
+		pr_info("%s AP2WIFI_USBPLL_REQ=1\n", __func__);
+	}
+
+	return 0;
+}
+
+static int _clk_wpll_usbpll_disable(struct pwrcal_clk *clk)
+{
+	if (pwrcal_getbit(clk->offset, USBPLL_WPLL_SEL) == 0) {
+		pwrcal_setbit(clk->status, AP2WIFI_USBPLL_REQ, 0x0);
+		pr_err("%s AP2WIFI_USBPLL_REQ=0\n", __func__);
+	}
+
+	return 0;
+}
+
+
+static int _clk_wpll_usbpll_set_rate(struct pwrcal_clk *clk,
+					unsigned long long rate)
+{
+
+	if (rate == 0) {
+		if (_clk_wpll_usbpll_is_enabled(clk) != 0)
+			if (_clk_wpll_usbpll_disable(clk))
+				goto errorout;
+	} else { /* rate != 0  */
+		if (_clk_wpll_usbpll_is_enabled(clk) == 0)
+			_clk_wpll_usbpll_enable(clk);
+		/*	pr_warn("WPLL_USBPLL set 20Mhz"); */
+	}
+	return 0;
+
+errorout:
+	return -1;
+}
+
+static unsigned long long _clk_wpll_usbpll_get_rate(struct pwrcal_clk *clk)
+{
+	unsigned long long fout;
+
+	if (_clk_wpll_usbpll_is_enabled(clk) == 0)
+		return 0;
+
+	fout = (20*MHZ);
+	return (unsigned long long)fout;
+}
+
+struct pwrcal_pll_ops pll141xx_ops = {
+	.is_enabled = _clk_pll141xx_is_enabled,
+	.enable = _clk_pll141xx_enable,
+	.disable = _clk_pll141xx_disable,
+	.set_rate = _clk_pll141xx_set_rate,
+	.get_rate = _clk_pll141xx_get_rate,
+};
+
+struct pwrcal_pll_ops pll1419x_ops = {
+	.is_enabled = _clk_pll141xx_is_enabled,
+	.enable = _clk_pll1419x_enable,
+	.disable = _clk_pll141xx_disable,
+	.set_rate = _clk_pll1419x_set_rate,
+	.get_rate = _clk_pll1419x_get_rate,
+};
+
+struct pwrcal_pll_ops pll1431x_ops = {
+	.is_enabled = _clk_pll1431x_is_enabled,
+	.enable = _clk_pll1431x_enable,
+	.disable = _clk_pll1431x_disable,
+	.set_rate = _clk_pll1431x_set_rate,
+	.get_rate = _clk_pll1431x_get_rate,
+};
+
+struct pwrcal_pll_ops wpll_usbpll_ops = {
+	.is_enabled = _clk_wpll_usbpll_is_enabled,
+	.enable = _clk_wpll_usbpll_enable,
+	.disable = _clk_wpll_usbpll_disable,
+	.set_rate = _clk_wpll_usbpll_set_rate,
+	.get_rate = _clk_wpll_usbpll_get_rate,
+};

drivers/soc/samsung/pwrcal/S5E7570/S5E7570-pmu.c

@@ -0,0 +1,104 @@
+#include "../pwrcal.h"
+#include "../pwrcal-env.h"
+#include "../pwrcal-rae.h"
+#include "../pwrcal-pmu.h"
+#include "S5E7570-cmusfr.h"
+#include "S5E7570-pmusfr.h"
+#include "S5E7570-cmu.h"
+
+static void dispaud_prev(int enable)
+{
+	pwrcal_setbit(CLKRUN_CMU_DISPAUD_SYS_PWR_REG, 0, 0);
+	pwrcal_setbit(CLKSTOP_CMU_DISPAUD_SYS_PWR_REG, 0, 0);
+	pwrcal_setbit(DISABLE_PLL_CMU_DISPAUD_SYS_PWR_REG, 0, 0);
+	pwrcal_setf(RESET_LOGIC_DISPAUD_SYS_PWR_REG, 0, 0x3, 0);
+	pwrcal_setf(RESET_CMU_DISPAUD_SYS_PWR_REG, 0, 0x3, 0);
+}
+
+static void g3d_prev(int enable)
+{
+	pwrcal_setbit(CLKRUN_CMU_G3D_SYS_PWR_REG, 0, 0);
+	pwrcal_setbit(CLKSTOP_CMU_G3D_SYS_PWR_REG, 0, 0);
+	pwrcal_setbit(DISABLE_PLL_CMU_G3D_SYS_PWR_REG, 0, 0);
+	pwrcal_setf(RESET_LOGIC_G3D_SYS_PWR_REG, 0, 0x3, 0);
+	pwrcal_setf(RESET_CMU_G3D_SYS_PWR_REG, 0, 0x3, 0);
+}
+
+static void isp_prev(int enable)
+{
+	pwrcal_setbit(CLKRUN_CMU_ISP_SYS_PWR_REG, 0, 0);
+	pwrcal_setbit(CLKSTOP_CMU_ISP_SYS_PWR_REG, 0, 0);
+	pwrcal_setbit(DISABLE_PLL_CMU_ISP_SYS_PWR_REG, 0, 0);
+	pwrcal_setf(RESET_LOGIC_ISP_SYS_PWR_REG, 0, 0x3, 0);
+	pwrcal_setf(RESET_CMU_ISP_SYS_PWR_REG, 0, 0x3, 0);
+}
+
+static void mfcmscl_prev(int enable)
+{
+	pwrcal_setbit(CLKRUN_CMU_MFCMSCL_SYS_PWR_REG, 0, 0);
+	pwrcal_setbit(CLKSTOP_CMU_MFCMSCL_SYS_PWR_REG, 0, 0);
+	pwrcal_setbit(DISABLE_PLL_CMU_MFCMSCL_SYS_PWR_REG, 0, 0);
+	pwrcal_setf(RESET_LOGIC_MFCMSCL_SYS_PWR_REG, 0, 0x3, 0);
+	pwrcal_setf(RESET_CMU_MFCMSCL_SYS_PWR_REG, 0, 0x3, 0);
+}
+
+static void dispaud_post(int enable)
+{
+	pwrcal_setbit(PAD_RETENTION_AUD_OPTION, 28, 1);
+}
+
+static void g3d_post(int enable)
+{
+}
+
+static void isp_post(int enable)
+{
+}
+
+static void mfcmscl_post(int enable)
+{
+}
+
+static void dispaud_config(int enable)
+{
+	pwrcal_setf(DISPAUD_OPTION, 0, 0xFFFFFFFF, 0x2);
+}
+
+static void g3d_config(int enable)
+{
+	pwrcal_setf(G3D_OPTION, 0, 0xFFFFFFFF, 0x1);
+}
+
+static void isp_config(int enable)
+{
+	pwrcal_setf(ISP_OPTION, 0, 0xFFFFFFFF, 0x2);
+}
+
+static void mfcmscl_config(int enable)
+{
+	pwrcal_setf(MFCMSCL_OPTION, 0, 0xFFFFFFFF, 0x2);
+}
+
+BLKPWR(blkpwr_dispaud, DISPAUD_CONFIGURATION, 0, 0xF, DISPAUD_STATUS, 0, 0xF, dispaud_config, dispaud_prev, dispaud_post);
+BLKPWR(blkpwr_g3d, G3D_CONFIGURATION, 0, 0xF, G3D_STATUS, 0, 0xF, g3d_config, g3d_prev, g3d_post);
+BLKPWR(blkpwr_isp, ISP_CONFIGURATION, 0, 0xF, ISP_STATUS, 0, 0xF, isp_config, isp_prev, isp_post);
+BLKPWR(blkpwr_mfcmscl, MFCMSCL_CONFIGURATION, 0, 0xF, MFCMSCL_STATUS, 0, 0xF, mfcmscl_config, mfcmscl_prev, mfcmscl_post);
+
+struct cal_pd *pwrcal_blkpwr_list[4];
+unsigned int pwrcal_blkpwr_size = 4;
+
+static int blkpwr_init(void)
+{
+	pwrcal_blkpwr_list[0] = &blkpwr_blkpwr_dispaud;
+	pwrcal_blkpwr_list[1] = &blkpwr_blkpwr_g3d;
+	pwrcal_blkpwr_list[2] = &blkpwr_blkpwr_isp;
+	pwrcal_blkpwr_list[3] = &blkpwr_blkpwr_mfcmscl;
+
+	return 0;
+}
+
+struct cal_pd_ops cal_pd_ops = {
+	.pd_control = blkpwr_control,
+	.pd_status = blkpwr_status,
+	.pd_init = blkpwr_init,
+};

drivers/soc/samsung/pwrcal/S5E7570/S5E7570-rae.c

@@ -0,0 +1,47 @@
+#include "../pwrcal-rae.h"
+#include "S5E7570-sfrbase.h"
+
+#ifdef PWRCAL_TARGET_LINUX
+
+struct v2p_sfr v2psfrmap[] = {
+	DEFINE_V2P(CMU_APM_BASE,	0x11CE0000),
+	DEFINE_V2P(CMU_MIF_BASE,	0x10460000),
+	DEFINE_V2P(CMU_PERI_BASE,	0x101F0000),
+	DEFINE_V2P(CMU_G3D_BASE,	0x11460000),
+	DEFINE_V2P(CMU_CPUCL0_BASE,	0x10900000),
+	DEFINE_V2P(CMU_MFCMSCL_BASE,	0x12CB0000),
+	DEFINE_V2P(CMU_FSYS_BASE,	0x13730000),
+	DEFINE_V2P(CMU_ISP_BASE,	0x144D0000),
+	DEFINE_V2P(CMU_DISPAUD_BASE,	0x148D0000),
+
+	DEFINE_V2P(PMU_CPUCL0_BASE,	0x10920000),
+	DEFINE_V2P(PMU_FSYS_BASE,	0x13740000),
+	DEFINE_V2P(PMU_G3D_BASE,	0x11470000),
+	DEFINE_V2P(PMU_ISP_BASE,	0x144E0000),
+	DEFINE_V2P(PMU_MFCMSCL_BASE,	0x12CC0000),
+	DEFINE_V2P(PMU_MIF_BASE,	0x10470000),
+	DEFINE_V2P(PMU_PERI_BASE,	0x101E0000),
+	DEFINE_V2P(PMU_IF_BASE,	0x11C70000),
+	DEFINE_V2P(PMU_ALIVE_BASE,	0x11C80000),
+	DEFINE_V2P(PMU_APM_BASE,	0x11CF0000),
+	DEFINE_V2P(PMU_DISPAUD_BASE,	0x148E0000),
+
+	DEFINE_V2P(DREX0_BASE,	0x10400000),
+	DEFINE_V2P(DREX0_PF_BASE,	0x10410000),
+	DEFINE_V2P(DREX0_SECURE_BASE,	0x10420000),
+	DEFINE_V2P(DREX0_PF_SECURE_BASE,	0x10430000),
+	DEFINE_V2P(DREXPHY0_BASE,	0x10440000),
+
+	DEFINE_V2P(SYSREG_CPUCL0_BASE,	0x10910000),
+	DEFINE_V2P(SYSREG_G3D_BASE,	0x11450000),
+	DEFINE_V2P(SYSREG_FSYS_BASE,	0x13720000),
+	DEFINE_V2P(SYSREG_MIF_BASE,	0x10450000),
+	DEFINE_V2P(SYSREG_PERI_BASE,	0x101D0000),
+	DEFINE_V2P(SYSREG_MFCMSCL_BASE,	0x12CA0000),
+	DEFINE_V2P(SYSREG_ISP_BASE,	0x144F0000),
+	DEFINE_V2P(SYSREG_DISPAUD_BASE,	0x148F0000),
+};
+
+int num_of_v2psfrmap = sizeof(v2psfrmap) / sizeof(v2psfrmap[0]);
+void *spinlock_enable_offset = (void *)PMU_CPUCL0_BASE;
+#endif

drivers/soc/samsung/pwrcal/S5E7570/S5E7570-sfrbase.h

@@ -0,0 +1,88 @@
+#ifndef __EXYNOS7570_SFRBASE_H__
+#define __EXYNOS7570_SFRBASE_H__
+
+#include "../pwrcal-env.h"
+
+#ifdef PWRCAL_TARGET_FW
+
+#define	CMU_APM_BASE	0x11CE0000
+#define	CMU_MIF_BASE	0x10460000
+#define	CMU_PERI_BASE	0x101F0000
+#define	CMU_G3D_BASE	0x11460000
+#define	CMU_CPUCL0_BASE	0x10900000
+#define	CMU_MFCMSCL_BASE	0x12CB0000
+#define	CMU_FSYS_BASE	0x13730000
+#define	CMU_ISP_BASE	0x144D0000
+#define	CMU_DISPAUD_BASE	0x148D0000
+
+#define PMU_CPUCL0_BASE		0x10920000
+#define PMU_FSYS_BASE		0x13740000
+#define PMU_G3D_BASE		0x11470000
+#define PMU_ISP_BASE		0x144E0000
+#define PMU_MFCMSCL_BASE	0x12CC0000
+#define PMU_MIF_BASE		0x10470000
+#define PMU_PERI_BASE		0x101E0000
+#define PMU_IF_BASE			0x11C70000
+#define PMU_ALIVE_BASE		0x11C80000
+#define PMU_APM_BASE		0x11CF0000
+#define PMU_DISPAUD_BASE	0x148E0000
+
+#define DREX0_BASE			 0x10400000
+#define DREX0_PF_BASE		 0x10410000
+#define DREX0_SECURE_BASE	 0x10420000
+#define DREX0_PF_SECURE_BASE 0x10430000
+#define DREXPHY0_BASE		 0x10440000
+
+#define	SYSREG_CPUCL0_BASE	0x10910000
+#define	SYSREG_G3D_BASE	0x11450000
+#define	SYSREG_FSYS_BASE	0x13720000
+#define	SYSREG_MIF_BASE	0x10450000
+#define	SYSREG_PERI_BASE	0x101D0000
+#define	SYSREG_MFCMSCL_BASE	0x12CA0000
+#define	SYSREG_ISP_BASE	0x144F0000
+#define	SYSREG_DISPAUD_BASE	0x148F0000
+
+#endif
+
+#ifdef PWRCAL_TARGET_LINUX
+
+#define	CMU_APM_BASE	0x00010000
+#define	CMU_MIF_BASE	0x00020000
+#define	CMU_PERI_BASE	0x00030000
+#define	CMU_G3D_BASE	0x00040000
+#define	CMU_CPUCL0_BASE	0x00050000
+#define	CMU_MFCMSCL_BASE	0x00060000
+#define	CMU_FSYS_BASE	0x00070000
+#define	CMU_ISP_BASE	0x00080000
+#define	CMU_DISPAUD_BASE	0x00090000
+
+#define PMU_CPUCL0_BASE		0x000A0000
+#define PMU_FSYS_BASE		0x000B0000
+#define PMU_G3D_BASE		0x000C0000
+#define PMU_ISP_BASE		0x000D0000
+#define PMU_MFCMSCL_BASE	0x000E0000
+#define PMU_MIF_BASE		0x000F0000
+#define PMU_PERI_BASE		0x00100000
+#define PMU_IF_BASE		0x00110000
+#define PMU_ALIVE_BASE		0x00120000
+#define PMU_APM_BASE		0x00130000
+#define PMU_DISPAUD_BASE	0x00140000
+
+#define DREX0_BASE		0x00150000
+#define DREX0_PF_BASE		0x00160000
+#define DREX0_SECURE_BASE	0x00170000
+#define DREX0_PF_SECURE_BASE	0x00180000
+#define DREXPHY0_BASE		0x00190000
+
+#define	SYSREG_CPUCL0_BASE	0x001A0000
+#define	SYSREG_G3D_BASE	0x001B0000
+#define	SYSREG_FSYS_BASE	0x001C0000
+#define	SYSREG_MIF_BASE	0x001D0000
+#define	SYSREG_PERI_BASE	0x001E0000
+#define	SYSREG_MFCMSCL_BASE	0x001F0000
+#define	SYSREG_ISP_BASE	0x00200000
+#define	SYSREG_DISPAUD_BASE	0x00210000
+
+#endif
+
+#endif

drivers/soc/samsung/pwrcal/S5E7570/S5E7570-syspwr.c

@@ -0,0 +1,598 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd. All rights reserved.
+ *		http://www.samsung.com
+ *
+ * Chip Abstraction Layer for System power down support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../pwrcal-env.h"
+#include "../pwrcal.h"
+#include "../pwrcal-pmu.h"
+#include "../pwrcal-rae.h"
+#include "S5E7570-cmusfr.h"
+#include "S5E7570-pmusfr.h"
+#include "S5E7570-cmu.h"
+
+enum sys_powerdown {
+	SYS_SICD,
+	SYS_AFTR,
+	SYS_STOP,
+	SYS_LPD,
+	SYS_LPA,
+	SYS_DSTOP,
+	SYS_SLEEP,
+	NUM_SYS_POWERDOWN,
+};
+
+struct exynos_pmu_conf {
+	unsigned int *reg;
+	unsigned int val[NUM_SYS_POWERDOWN];
+};
+
+/* init_pmu_l2_option */
+#define MANUAL_ACINACTM_VALUE		(0x1 << 3)
+#define MANUAL_ACINACTM_CONTROL		(0x1 << 2)
+#define MANUAL_AINACTS_VALUE		(0x1 << 1)
+#define MANUAL_AINACTS_CONTROL		(0x1 << 0)
+#define USE_AUTOMATIC_L2FLUSHREQ	(0x1 << 17)
+#define USE_STANDBYWFIL2			(0x1 << 16)
+#define USE_RETENTION				(0x1 << 4)
+
+/* CPU option */
+#define USE_SMPEN					(0x1 << 28)
+#define USE_STANDBYWFE				(0x1 << 24)
+#define USE_STANDBYWFI				(0x1 << 16)
+#define USE_IRQCPU_FOR_PWR			(0x3 << 4)
+#define USE_MEMPWRDOWN_FEEDBACK		(0x1 << 3)
+#define USE_MEMPWRDOWN_COUNTER		(0x1 << 2)
+#define USE_SC_FEEDBACK				(0x1 << 1)
+#define USE_SC_COUNTER				(0x1 << 0)
+#define DUR_WAIT_RESET				(0xF << 20)
+#define DUR_SCALL					(0xF << 4)
+#define DUR_SCALL_VALUE				(0x1 << 4)
+
+/* init_pmu_up_scheduler */
+#define ENABLE_CPUCL0_CPU			(0x1 << 0)
+
+/* init_set_duration */
+#define DUR_STABLE_MASK_AT_RESET	0xFFFFF
+#define DUR_STABLE_MASK				0x3FF
+#define TCXO_DUR_STABLE							0x140		/* 10ms in 32Khz */
+#define EXTREG_SHARED_DUR_STABLE				0x140		/* 10ms in 32Khz */
+#define EXTREG_SHARED_DUR_STABLE_AT_RESET		0x3F7A0		/* 10ms in 26Mhz */
+
+/* init_pshold_setting_value*/
+#define ENABLE_HW_TRIP				(0x1 << 31)
+#define PS_HOLD_OUTPUT_HIGH		(0x3 << 8)
+
+#define PAD_INITIATE_WAKEUP			(0x1 << 28)
+
+struct system_power_backup_reg {
+	void *reg;
+	unsigned int backup;
+	void *reg_stat;
+	unsigned int backup_stat;
+	void *pwr_stat_reg;	/* if pwr_check true, this reg should be set */
+	unsigned int valid;
+};
+
+#define SYS_PWR_BACK_REG(_reg, _reg_stat, _pwr_stat_reg)	\
+{						\
+	.reg		= _reg,			\
+	.backup		= 0,			\
+	.reg_stat		= _reg_stat,		\
+	.backup_stat	= 0,			\
+	.pwr_stat_reg	= _pwr_stat_reg,	\
+	.valid		= 0,			\
+}
+
+static unsigned int *pmu_cpuoption_sfrlist[] = {
+	CPUCL0_CPU0_OPTION,
+	CPUCL0_CPU1_OPTION,
+	CPUCL0_CPU2_OPTION,
+	CPUCL0_CPU3_OPTION,
+};
+
+static void init_pmu_cpu_option(void)
+{
+	int cpu;
+	unsigned int tmp;
+
+	/* use both sc_counter and sc_feedback */
+	/* enable to wait for low SMP-bit at sys power down */
+	for (cpu = 0; cpu < sizeof(pmu_cpuoption_sfrlist) / sizeof(pmu_cpuoption_sfrlist[0]); cpu++) {
+		tmp = pwrcal_readl(pmu_cpuoption_sfrlist[cpu]);
+		tmp |= USE_SC_FEEDBACK;
+		tmp |= USE_SMPEN;
+		tmp &= ~USE_SC_COUNTER;
+		tmp |= USE_STANDBYWFI;
+		tmp |= USE_MEMPWRDOWN_FEEDBACK;
+		tmp &= ~USE_STANDBYWFE;
+		pwrcal_writel(pmu_cpuoption_sfrlist[cpu], tmp);
+	}
+}
+
+static void set_pmu_enable_reset_lpi_timeout(void)
+{
+	pwrcal_setbit(RESET_LPI_TIMEOUT, 0, 1);
+}
+
+static void init_pmu_apm_option(void)
+{
+	pwrcal_setbit(CENTRAL_SEQ_APM_OPTION, 1, 1);	/*USE STANDBYWFI*/
+	pwrcal_setbit(CORTEXM0_APM_OPTION, 16, 1);	/*USE StandbyWFI*/
+}
+
+static void init_pmu_l2_option(void)
+{
+	unsigned int tmp;
+
+	/* disable automatic L2 flush */
+	/* disable L2 retention */
+
+	tmp = pwrcal_readl(CPUCL0_L2_OPTION);
+	tmp &= ~(USE_AUTOMATIC_L2FLUSHREQ | USE_RETENTION);
+	tmp |= USE_STANDBYWFIL2;
+	pwrcal_writel(CPUCL0_L2_OPTION, tmp);
+}
+
+static void init_pmu_cpuseq_option(void)
+{
+}
+
+static void init_pmu_up_scheduler(void)
+{
+	unsigned int tmp;
+
+	/* limit in-rush current for CPUCL0/1 local power up */
+	tmp = pwrcal_readl(UP_SCHEDULER);
+	tmp |= ENABLE_CPUCL0_CPU;
+	pwrcal_writel(UP_SCHEDULER, tmp);
+}
+
+/* init_pmu_feedback */
+static unsigned int *pmu_feedback_sfrlist[] = {
+	CPUCL0_NONCPU_OPTION,
+	TOP_PWR_OPTION,
+	TOP_PWR_MIF_OPTION,
+	DISPAUD_OPTION,
+	MFCMSCL_OPTION,
+	ISP_OPTION,
+};
+
+static void init_set_duration(void)
+{
+	unsigned int tmp;
+
+	tmp = pwrcal_readl(TCXO_SHARED_DURATION3);
+	tmp &= ~DUR_STABLE_MASK;
+	tmp |= TCXO_DUR_STABLE;
+	pwrcal_writel(TCXO_SHARED_DURATION3, tmp);
+
+	tmp = pwrcal_readl(EXT_REGULATOR_SHARED_DURATION1);
+	tmp &= ~DUR_STABLE_MASK_AT_RESET;
+	tmp |= EXTREG_SHARED_DUR_STABLE_AT_RESET;
+	pwrcal_writel(EXT_REGULATOR_SHARED_DURATION1, tmp);
+
+	tmp = pwrcal_readl(EXT_REGULATOR_SHARED_DURATION3);
+	tmp &= ~DUR_STABLE_MASK;
+	tmp |= EXTREG_SHARED_DUR_STABLE;
+	pwrcal_writel(EXT_REGULATOR_SHARED_DURATION3, tmp);
+}
+
+static void init_pmu_feedback(void)
+{
+	int i;
+	unsigned int tmp;
+
+	for (i = 0; i < sizeof(pmu_feedback_sfrlist) / sizeof(pmu_feedback_sfrlist[0]); i++) {
+		tmp = pwrcal_readl(pmu_feedback_sfrlist[i]);
+		tmp &= ~USE_SC_COUNTER;
+		tmp |= USE_SC_FEEDBACK;
+		pwrcal_writel(pmu_feedback_sfrlist[i], tmp);
+	}
+}
+static void init_ps_hold_setting(void)
+{
+	unsigned int tmp;
+
+	tmp = pwrcal_readl(PS_HOLD_CONTROL);
+	tmp |= (ENABLE_HW_TRIP | PS_HOLD_OUTPUT_HIGH);
+	pwrcal_writel(PS_HOLD_CONTROL, tmp);
+}
+
+
+static void enable_armidleclockdown(void);
+static void syspwr_init(void)
+{
+	init_pmu_feedback();
+	init_pmu_l2_option();
+	init_pmu_cpu_option();
+	init_pmu_cpuseq_option();
+	init_pmu_up_scheduler();
+	init_ps_hold_setting();
+	init_set_duration();
+	init_pmu_apm_option();
+	set_pmu_enable_reset_lpi_timeout();
+	enable_armidleclockdown();
+}
+
+static struct exynos_pmu_conf exynos_syspwr_pmu_config[] = {
+	/* { .addr = address, .val = { SICD, AFTR, STOP, LPD, LPA, DSTOP, SLEEP } } */
+	{ CPUCL0_CPU0_SYS_PWR_REG,			{ 0xF, 0x0, 0xF, 0x0, 0x0, 0x0, 0x8} },
+	{ DIS_IRQ_CPUCL0_CPU0_LOCAL_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ DIS_IRQ_CPUCL0_CPU0_CENTRAL_SYS_PWR_REG,			{ 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ DIS_IRQ_CPUCL0_CPU0_CPUSEQUENCER_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ CPUCL0_CPU1_SYS_PWR_REG,			{ 0xF, 0x0, 0xF, 0x0, 0x0, 0x0, 0x8} },
+	{ DIS_IRQ_CPUCL0_CPU1_LOCAL_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ DIS_IRQ_CPUCL0_CPU1_CENTRAL_SYS_PWR_REG,			{ 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ DIS_IRQ_CPUCL0_CPU1_CPUSEQUENCER_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ CPUCL0_CPU2_SYS_PWR_REG,			{ 0xF, 0x0, 0xF, 0x0, 0x0, 0x0, 0x8} },
+	{ DIS_IRQ_CPUCL0_CPU2_LOCAL_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ DIS_IRQ_CPUCL0_CPU2_CENTRAL_SYS_PWR_REG,			{ 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ DIS_IRQ_CPUCL0_CPU2_CPUSEQUENCER_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ CPUCL0_CPU3_SYS_PWR_REG,			{ 0xF, 0x0, 0xF, 0x0, 0x0, 0x0, 0x8} },
+	{ DIS_IRQ_CPUCL0_CPU3_LOCAL_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ DIS_IRQ_CPUCL0_CPU3_CENTRAL_SYS_PWR_REG,			{ 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ DIS_IRQ_CPUCL0_CPU3_CPUSEQUENCER_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ CPUCL1_CPU0_SYS_PWR_REG,			{ 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF} },
+	{ DIS_IRQ_CPUCL1_CPU0_LOCAL_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ DIS_IRQ_CPUCL1_CPU0_CENTRAL_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ DIS_IRQ_CPUCL1_CPU0_CPUSEQUENCER_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ CPUCL1_CPU1_SYS_PWR_REG,			{ 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF} },
+	{ DIS_IRQ_CPUCL1_CPU1_LOCAL_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ DIS_IRQ_CPUCL1_CPU1_CENTRAL_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ DIS_IRQ_CPUCL1_CPU1_CPUSEQUENCER_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ CPUCL1_CPU2_SYS_PWR_REG,			{ 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF} },
+	{ DIS_IRQ_CPUCL1_CPU2_LOCAL_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ DIS_IRQ_CPUCL1_CPU2_CENTRAL_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ DIS_IRQ_CPUCL1_CPU2_CPUSEQUENCER_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ CPUCL1_CPU3_SYS_PWR_REG,			{ 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF} },
+	{ DIS_IRQ_CPUCL1_CPU3_LOCAL_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ DIS_IRQ_CPUCL1_CPU3_CENTRAL_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ DIS_IRQ_CPUCL1_CPU3_CPUSEQUENCER_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ CPUCL0_NONCPU_SYS_PWR_REG,			{ 0xF, 0x0, 0xF, 0x0, 0x0, 0x0, 0x8} },
+	{ CPUCL1_NONCPU_SYS_PWR_REG,			{ 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF} },
+	{ CPUCL0_L2_SYS_PWR_REG,			{ 0x7, 0x0, 0x7, 0x0, 0x0, 0x0, 0x7} },
+	{ CPUCL1_L2_SYS_PWR_REG,			{ 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7} },
+	{ CLKSTOP_CMU_TOP_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ CLKRUN_CMU_TOP_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ RETENTION_CMU_TOP_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x3} },
+	{ RESET_CMU_TOP_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x0} },
+	{ RESET_CPUCLKSTOP_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x0} },
+	{ CLKSTOP_CMU_MIF_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0} },
+	{ CLKRUN_CMU_MIF_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0} },
+	{ RETENTION_CMU_MIF_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x3} },
+	{ RESET_CMU_MIF_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x0} },
+	{ DDRPHY_CLKSTOP_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x1} },
+	{ DDRPHY_ISO_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x1} },
+	{ DDRPHY_DLL_CLK_SYS_PWR_REG,			{ 0x0, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0} },
+	{ DISABLE_PLL_CMU_TOP_SYS_PWR_REG,			{ 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ DISABLE_PLL_AUD_PLL_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ DISABLE_PLL_CMU_MIF_SYS_PWR_REG,			{ 0x0, 0x1, 0x0, 0x1, 0x0, 0x0, 0x0} },
+	{ DISABLE_PLL_APM_MIF_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ RESET_AHEAD_CP_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
+	{ RESET_AHEAD_GNSS_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
+	{ TOP_BUS_SYS_PWR_REG,			{ 0x7, 0x7, 0x7, 0x0, 0x0, 0x0, 0x0} },
+	{ TOP_RETENTION_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x3} },
+	{ TOP_PWR_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x3} },
+	{ TOP_BUS_MIF_SYS_PWR_REG,			{ 0x0, 0x7, 0x7, 0x7, 0x0, 0x0, 0x0} },
+	{ TOP_RETENTION_MIF_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x3} },
+	{ TOP_PWR_MIF_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x3} },
+	{ LOGIC_RESET_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x0} },
+	{ OSCCLK_GATE_SYS_PWR_REG,			{ 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x1} },
+	{ SLEEP_RESET_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x0} },
+	{ LOGIC_RESET_MIF_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0} },
+	{ OSCCLK_GATE_MIF_SYS_PWR_REG,			{ 0x1, 0x1, 0x0, 0x1, 0x0, 0x0, 0x1} },
+	{ SLEEP_RESET_MIF_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x0} },
+	{ RESET_ASB_MIF_GNSS_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
+	{ MEMORY_TOP_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x3} },
+	{ TCXO_GATE_GNSS_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ RESET_ASB_GNSS_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
+	{ CLEANY_BUS_CP_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ LOGIC_RESET_CP_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
+	{ TCXO_GATE_CP_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ RESET_ASB_CP_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
+	{ RESET_ASB_MIF_CP_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
+	{ MEMORY_MIF_ALIVEIRAM_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
+	{ MEMORY_MIF_TOP_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x3} },
+	{ CLEANY_BUS_GNSS_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ LOGIC_RESET_GNSS_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
+	{ PAD_RETENTION_LPDDR3_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0} },
+	{ PAD_RETENTION_AUD_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0} },
+	{ PAD_RETENTION_PEDOMETER_TOP_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ PAD_RETENTION_MMC2_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ PAD_RETENTION_TOP_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ PAD_RETENTION_UART_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ PAD_RETENTION_MMC0_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ PAD_RETENTION_MMC1_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ PAD_RETENTION_SPI_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ PAD_RETENTION_MIF_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0} },
+	{ PAD_ISOLATION_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x1} },
+	{ PAD_RETENTION_BOOTLDO_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ PAD_ISOLATION_MIF_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x1} },
+	{ EXT_REGULATOR_MIF_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0} },
+	{ GPIO_MODE_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ GPIO_MODE_MIF_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0} },
+	{ GPIO_MODE_DISPAUD_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0} },
+	{ G3D_SYS_PWR_REG,			{ 0xF, 0xF, 0xF, 0x0, 0x0, 0x0, 0x0} },
+	{ DISPAUD_SYS_PWR_REG,			{ 0xF, 0xF, 0x0, 0xF, 0xF, 0x0, 0x0} },
+	{ ISP_SYS_PWR_REG,			{ 0xF, 0xF, 0xF, 0x0, 0x0, 0x0, 0x0} },
+	{ MFCMSCL_SYS_PWR_REG,			{ 0xF, 0xF, 0xF, 0x0, 0x0, 0x0, 0x0} },
+	{ CLKRUN_CMU_G3D_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ CLKRUN_CMU_DISPAUD_SYS_PWR_REG,			{ 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ CLKRUN_CMU_ISP_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ CLKRUN_CMU_MFCMSCL_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ CLKSTOP_CMU_G3D_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ CLKSTOP_CMU_DISPAUD_SYS_PWR_REG,			{ 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ CLKSTOP_CMU_ISP_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ CLKSTOP_CMU_MFCMSCL_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ DISABLE_PLL_CMU_G3D_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ DISABLE_PLL_CMU_DISPAUD_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ DISABLE_PLL_CMU_ISP_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ DISABLE_PLL_CMU_MFCMSCL_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ RESET_LOGIC_G3D_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ RESET_LOGIC_DISPAUD_SYS_PWR_REG,			{ 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0} },
+	{ RESET_LOGIC_ISP_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ RESET_LOGIC_MFCMSCL_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ MEMORY_G3D_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ MEMORY_DISPAUD_SYS_PWR_REG,			{ 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0} },
+	{ MEMORY_ISP_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ MEMORY_MFCMSCL_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ RESET_CMU_G3D_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ RESET_CMU_DISPAUD_SYS_PWR_REG,			{ 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0} },
+	{ RESET_CMU_ISP_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ RESET_CMU_MFCMSCL_SYS_PWR_REG,			{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
+
+	{ RESET_AHEAD_WIFI_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
+	{ CLEANY_BUS_WIFI_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ LOGIC_RESET_WIFI_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
+	{ TCXO_GATE_WIFI_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ RESET_ASB_WIFI_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
+	{ RESET_ASB_MIF_WIFI_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
+	{ CORTEXM0_APM_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ CLKRUN_CMU_APM_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ TOP_BUS_APM_SYS_PWR_REG,			{ 0x7, 0x7, 0x7, 0x0, 0x0, 0x0, 0x0} },
+	{ CLKSTOP_CMU_APM_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ CLKSTOP_OPEN_CMU_APM_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ DISABLE_PLL_CMU_APM_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+	{ TOP_RETENTION_APM_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x0} },
+	{ OSCCLK_GATE_APM_SYS_PWR_REG,			{ 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0} },
+	{ MEMORY_APM_TOP_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x0} },
+	{ LOGIC_RESET_APM_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x0} },
+	{ SLEEP_RESET_APM_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
+	{ RETENTION_CMU_APM_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x0} },
+	{ RESET_CMU_APM_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
+	{ TOP_PWR_APM_SYS_PWR_REG,			{ 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x0} },
+	{ TCXO_SYS_PWR_REG,			{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x0, 0x0} },
+	{ PAD_RETENTION_PEDOMETER_APM_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+
+	{ PAD_RETENTION_PEDOMETER_TOP_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
+	{ PAD_RETENTION_PEDOMETER_APM_SYS_PWR_REG,			{ 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
+
+	{ 0, },
+};
+
+static struct exynos_pmu_conf exynos_syspwr_pmu_option[] = {
+	/* { .addr = address, .val =				{ SICD,		AFTR,		STOP,		LPD,			LPA,			DSTOP,		SLEEP		} } */
+	{CENTRAL_SEQ_OPTION,				{0x000F0000,	0x000F0000,	0x000F0000,	0x000F0000,	0x000F0000,	0x000F0000,	0x000F0000	} },
+	{CENTRAL_SEQ_OPTION1,			{0x10000000,	0x10000000,	0x10000000,	0x10000000,	0x10000000,	0x10000000,	0x10000000	} },
+	{CENTRAL_SEQ_MIF_OPTION,			{0x18,		0x18,		0x18,		0x18,		0x18,		0x18,		0x18			} },
+	{TOP_BUS_MIF_OPTION,				{0x3,		0x0,			0x0,			0x0,			0x0,			0x0,			0x0			} },
+	{0, },
+};
+
+static void set_pmu_sys_pwr_reg(enum sys_powerdown mode)
+{
+	int i;
+
+	for (i = 0; exynos_syspwr_pmu_config[i].reg != 0; i++)
+		pwrcal_writel(exynos_syspwr_pmu_config[i].reg, exynos_syspwr_pmu_config[i].val[mode]);
+
+	for (i = 0; exynos_syspwr_pmu_option[i].reg != 0; i++)
+		pwrcal_writel(exynos_syspwr_pmu_option[i].reg, exynos_syspwr_pmu_option[i].val[mode]);
+}
+
+#define	PWRCAL_CENTRALSEQ_PWR_CFG	0x10000
+
+static void set_pmu_central_seq(int mode, bool enable)
+{
+	unsigned int tmp;
+
+	/* central sequencer */
+	tmp = pwrcal_readl(CENTRAL_SEQ_CONFIGURATION);
+	if (enable)
+		tmp &= ~PWRCAL_CENTRALSEQ_PWR_CFG;
+	else
+		tmp |= PWRCAL_CENTRALSEQ_PWR_CFG;
+	pwrcal_writel(CENTRAL_SEQ_CONFIGURATION, tmp);
+
+	/* central sequencer MIF */
+	if (mode == SYS_SICD) {
+		tmp = pwrcal_readl(CENTRAL_SEQ_MIF_CONFIGURATION);
+		if (enable)
+			tmp &= ~PWRCAL_CENTRALSEQ_PWR_CFG;
+		else
+			tmp |= PWRCAL_CENTRALSEQ_PWR_CFG;
+		pwrcal_writel(CENTRAL_SEQ_MIF_CONFIGURATION, tmp);
+	}
+}
+
+static struct system_power_backup_reg backup_reg[] = {
+};
+
+static int syspwr_clkpwr_backup(unsigned int power_mode)
+{
+	int i;
+
+	for (i = 0; i < sizeof(backup_reg) / sizeof(backup_reg[0]); i++) {
+		backup_reg[i].valid = 0;
+		if (backup_reg[i].pwr_stat_reg && pwrcal_getf(backup_reg[i].pwr_stat_reg, 0, 0xF) != 0xF)
+			continue;
+
+		if (backup_reg[i].reg) {
+			backup_reg[i].backup = pwrcal_readl(backup_reg[i].reg);
+			if (backup_reg[i].reg_stat)
+				backup_reg[i].backup_stat = pwrcal_readl(backup_reg[i].reg_stat);
+			backup_reg[i].valid = 1;
+		}
+	}
+
+	return 0;
+}
+
+static int syspwr_clkpwr_restore(unsigned int power_mode)
+{
+	int i;
+	int timeout;
+
+	for (i = 0; i < sizeof(backup_reg) / sizeof(backup_reg[0]); i++) {
+		if (backup_reg[i].valid == 1) {
+			if (backup_reg[i].pwr_stat_reg && pwrcal_getf(backup_reg[i].pwr_stat_reg, 0, 0xF) != 0xF)
+				continue;
+			if (backup_reg[i].reg) {
+				pwrcal_writel(backup_reg[i].reg, backup_reg[i].backup);
+
+				if (backup_reg[i].reg_stat) {
+					for (timeout = 0; timeout < CLK_WAIT_CNT; timeout++) {
+						timeout = pwrcal_readl(backup_reg[i].reg_stat);
+						if (timeout == backup_reg[i].backup_stat)
+							break;
+					}
+					if (timeout == CLK_WAIT_CNT)
+						pr_warn("[%s] timeout wait for (0x%08X)\n",
+							__func__, backup_reg[i].backup_stat);
+				}
+			}
+		}
+	}
+
+	return 0;
+}
+
+static void enable_armidleclockdown(void)
+{
+	/*Use L2QACTIVE*/
+	pwrcal_setbit(PWR_CTRL3, 0, 1);
+	pwrcal_setbit(PWR_CTRL3, 1, 1);
+}
+
+inline void disable_armidleclockdown(void)
+{
+	pwrcal_setbit(PWR_CTRL3, 0, 0);
+}
+
+static void syspwr_clock_config(int mode)
+{
+	pwrcal_setbit(CLK_CON_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER,	12,	0);
+	pwrcal_setbit(CLK_CON_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER,	27,	1);
+	if (pwrcal_getf(ISP_STATUS,	0,	0xf) == 0xf) {
+		pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 27, 1);
+	}
+	if ((pwrcal_getf(DISPAUD_STATUS, 0, 0xf) == 0xf) && (mode != SYS_LPD)) {
+		pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER,	12,	0); /* MIPIDPHY */
+		pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER,	12,	0); /* MIPIDPHY */
+		pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER,	27, 1); /* MIPIDPHY */
+		pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER,	27, 1); /* MIPIDPHY */
+	}
+
+	if (mode == SYS_LPD) {
+		/* PLL sharing is need to discuss, CP needs all PLL */
+		pwrcal_setbit(MIF_ROOTCLKEN,	0,	1);
+		pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_SPI_REARFROM,	0,	0);
+		pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_SPI_ESE,	0,	0);
+		pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_USI_0,	0,	0);
+		pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_USI_1,	0,	0);
+	}
+	/*LPI disable conditionally, when CP/GNSS/WIFI is disabled*/
+}
+
+static int syspwr_clkpwr_optimize(unsigned int power_mode)
+{
+	disable_armidleclockdown();
+
+	return 0;
+}
+
+static void syspwr_set_additional_config(const enum sys_powerdown eMode)
+{
+	/* USE_LEVEL_TRIGGER */
+	pwrcal_setf(WAKEUP_MASK, 30, 0x1, 0x1);
+	pwrcal_setf(WAKEUP_MASK_MIF, 30, 0x1, 0x1);
+
+	if (eMode == SYS_STOP) {
+		pwrcal_setf(DISPAUD_OPTION, 31, 0x1, 0x1);
+		pwrcal_setf(DISPAUD_OPTION, 21, 0x1, 0x1);
+	} else {
+		pwrcal_setf(DISPAUD_OPTION, 31, 0x1, 0x0);
+		pwrcal_setf(DISPAUD_OPTION, 21, 0x1, 0x0);
+	}
+}
+
+static void syspwr_prepare(int mode)
+{
+	syspwr_clkpwr_backup(mode);
+	syspwr_clock_config(mode);
+	syspwr_clkpwr_optimize(mode);
+
+	set_pmu_sys_pwr_reg(mode);
+	syspwr_set_additional_config(mode);
+	set_pmu_central_seq(mode, true);
+}
+
+static void set_pmu_pad_retention_release(void)
+{
+	pwrcal_writel(PAD_RETENTION_AUD_OPTION, PAD_INITIATE_WAKEUP);
+	pwrcal_writel(PAD_RETENTION_TOP_OPTION, PAD_INITIATE_WAKEUP);
+	pwrcal_writel(PAD_RETENTION_UART_OPTION, PAD_INITIATE_WAKEUP);
+	pwrcal_writel(PAD_RETENTION_MMC0_OPTION, PAD_INITIATE_WAKEUP);
+	pwrcal_writel(PAD_RETENTION_MMC2_OPTION, PAD_INITIATE_WAKEUP);
+	pwrcal_writel(PAD_RETENTION_SPI_OPTION, PAD_INITIATE_WAKEUP);
+	pwrcal_writel(PAD_RETENTION_BOOTLDO_OPTION, PAD_INITIATE_WAKEUP);
+}
+
+static void syspwr_post(int mode)
+{
+	if (mode != SYS_SICD)
+		set_pmu_pad_retention_release();
+
+	switch (mode) {
+	case SYS_SICD:
+	case SYS_AFTR:
+	case SYS_DSTOP:
+	case SYS_STOP:
+	case SYS_LPD:
+	case SYS_LPA:
+	case SYS_SLEEP:
+		set_pmu_central_seq(mode, false);
+		break;
+	default:
+		return;
+		break;
+	}
+
+	enable_armidleclockdown();
+
+	syspwr_clkpwr_restore(mode);
+}
+
+static void syspwr_earlywakeup(int mode)
+{
+	set_pmu_central_seq(mode, false);
+
+	enable_armidleclockdown();
+
+	syspwr_clkpwr_restore(mode);
+}
+
+struct cal_pm_ops cal_pm_ops = {
+	.pm_enter = syspwr_prepare,
+	.pm_exit = syspwr_post,
+	.pm_earlywakeup = syspwr_earlywakeup,
+	.pm_init = syspwr_init,
+};

drivers/soc/samsung/pwrcal/S5E7570/S5E7570-sysreg.h

@@ -0,0 +1,13 @@
+#ifndef __EXYNOS7570_H__
+#define __EXYNOS7570_H__
+
+#include "S5E7570-sfrbase.h"
+
+#define CPUCL0_EMA_CON		((void *)(SYSREG_CPUCL0_BASE + 0x0330))
+#define CPUCL0_EMA		((void *)(SYSREG_CPUCL0_BASE + 0x0340))
+#define G3D_EMA_RA1_HS_CON	((void *)(SYSREG_G3D_BASE + 0x0304))
+#define G3D_EMA_RF1_HS_CON	((void *)(SYSREG_G3D_BASE + 0x0314))
+#define G3D_EMA_RF2_HS_CON	((void *)(SYSREG_G3D_BASE + 0x031C))
+#define G3D_EMA_UHD_CON		((void *)(SYSREG_G3D_BASE + 0x0320))
+
+#endif

drivers/soc/samsung/pwrcal/S5E7570/S5E7570-vclk-internal.h

@@ -0,0 +1,131 @@
+#ifndef __EXYNOS7870_VCLKS_H__
+#define __EXYNOS7870_VCLKS_H__
+
+#include "../pwrcal-vclk.h"
+#include "../pwrcal-pmu.h"
+#include "S5E7570-vclk.h"
+
+M1D1G1_EXTERN(sclk_decon_vclk)
+M1D1G1_EXTERN(sclk_mmc0)
+M1D1G1_EXTERN(sclk_mmc2)
+M1D1G1_EXTERN(sclk_usb20drd_refclk)
+M1D1G1_EXTERN(sclk_uart_debug)
+M1D1G1_EXTERN(sclk_uart_sensor)
+M1D1G1_EXTERN(sclk_spi_rearfrom)
+M1D1G1_EXTERN(sclk_spi_ese)
+M1D1G1_EXTERN(sclk_usi0)
+M1D1G1_EXTERN(sclk_usi1)
+M1D1G1_EXTERN(sclk_apm)
+M1D1G1_EXTERN(sclk_isp_sensor0)
+
+PXMXDX_EXTERN(pxmxdx_top)
+PXMXDX_EXTERN(pxmxdx_dispaud)
+PXMXDX_EXTERN(pxmxdx_mfcmscl)
+PXMXDX_EXTERN(pxmxdx_isp_vra)
+PXMXDX_EXTERN(pxmxdx_isp_cam)
+PXMXDX_EXTERN(pxmxdx_oscclk_aud)
+
+P1_EXTERN(p1_aud_pll)
+P1_EXTERN(p1_wpll_usb_pll)
+
+M1_EXTERN(m1_dummy)
+
+D1_EXTERN(sclk_decon_vclk_local)
+D1_EXTERN(d1_dispaud_mi2s)
+D1_EXTERN(d1_dispaud_mixer)
+D1_EXTERN(d1_dispaud_oscclk_fm_52m)
+
+GRPGATE_EXTERN(gate_mif_pdma)
+GRPGATE_EXTERN(gate_mif_adcif)
+GRPGATE_EXTERN(gate_mif_speedy)
+GRPGATE_EXTERN(gate_apm_apm)
+GRPGATE_EXTERN(gate_cpucl0_ppmu)
+GRPGATE_EXTERN(gate_cpucl0_bts)
+GRPGATE_EXTERN(gate_dispaud_common_disp)
+GRPGATE_EXTERN(gate_dispaud_common_dsim0)
+GRPGATE_EXTERN(gate_dispaud_common_aud)
+GRPGATE_EXTERN(gate_dispaud_sysmmu)
+GRPGATE_EXTERN(gate_dispaud_ppmu)
+GRPGATE_EXTERN(gate_dispaud_bts)
+GRPGATE_EXTERN(gate_dispaud_decon)
+GRPGATE_EXTERN(gate_dispaud_dsim0)
+GRPGATE_EXTERN(gate_dispaud_mixer)
+GRPGATE_EXTERN(gate_dispaud_mi2s_aud)
+GRPGATE_EXTERN(gate_dispaud_mi2s_amp)
+GRPGATE_EXTERN(gate_peri_peris0)
+GRPGATE_EXTERN(gate_peri_peric1)
+GRPGATE_EXTERN(gate_peri_peric0)
+GRPGATE_EXTERN(gate_peri_pwm_motor)
+GRPGATE_EXTERN(gate_peri_sclk_pwm_motor)
+GRPGATE_EXTERN(gate_peri_mct)
+GRPGATE_EXTERN(gate_peri_i2c_sensor2)
+GRPGATE_EXTERN(gate_peri_i2c_sensor1)
+GRPGATE_EXTERN(gate_peri_i2c_tsp)
+GRPGATE_EXTERN(gate_peri_i2c_fuelgauge)
+GRPGATE_EXTERN(gate_peri_i2c_nfc)
+GRPGATE_EXTERN(gate_peri_i2c_muic)
+GRPGATE_EXTERN(gate_peri_hsi2c_frontcam)
+GRPGATE_EXTERN(gate_peri_hsi2c_maincam)
+GRPGATE_EXTERN(gate_peri_hsi2c_frontsensor)
+GRPGATE_EXTERN(gate_peri_hsi2c_rearaf)
+GRPGATE_EXTERN(gate_peri_hsi2c_rearsensor)
+GRPGATE_EXTERN(gate_peri_gpio_touch)
+GRPGATE_EXTERN(gate_peri_gpio_top)
+GRPGATE_EXTERN(gate_peri_gpio_nfc)
+GRPGATE_EXTERN(gate_peri_gpio_ese)
+GRPGATE_EXTERN(gate_peri_wdt_cpucl0)
+GRPGATE_EXTERN(gate_peri_uart_debug)
+GRPGATE_EXTERN(gate_peri_uart_sensor)
+GRPGATE_EXTERN(gate_peri_tmu_cpucl0)
+GRPGATE_EXTERN(gate_peri_spi_ese)
+GRPGATE_EXTERN(gate_peri_spi_rearfrom)
+GRPGATE_EXTERN(gate_peri_gpio_alive)
+GRPGATE_EXTERN(gate_peri_chipid)
+GRPGATE_EXTERN(gate_peri_otp_con_top)
+GRPGATE_EXTERN(gate_peri_rtc_alive)
+GRPGATE_EXTERN(gate_peri_rtc_top)
+GRPGATE_EXTERN(gate_peri_usi0)
+GRPGATE_EXTERN(gate_peri_usi1)
+GRPGATE_EXTERN(gate_fsys_common)
+GRPGATE_EXTERN(gate_fsys_common_busp2)
+GRPGATE_EXTERN(gate_fsys_common_busp3)
+GRPGATE_EXTERN(gate_fsys_sysmmu)
+GRPGATE_EXTERN(gate_fsys_ppmu)
+GRPGATE_EXTERN(gate_fsys_bts)
+GRPGATE_EXTERN(gate_fsys_usb20drd)
+GRPGATE_EXTERN(gate_fsys_mmc0)
+GRPGATE_EXTERN(gate_fsys_sclk_mmc0)
+GRPGATE_EXTERN(gate_fsys_mmc2)
+GRPGATE_EXTERN(gate_fsys_sclk_mmc2)
+GRPGATE_EXTERN(gate_fsys_sss)
+GRPGATE_EXTERN(gate_fsys_rtic)
+GRPGATE_EXTERN(gate_g3d_common)
+GRPGATE_EXTERN(gate_g3d_sysmmu)
+GRPGATE_EXTERN(gate_g3d_ppmu)
+GRPGATE_EXTERN(gate_g3d_bts)
+GRPGATE_EXTERN(gate_g3d_g3d)
+GRPGATE_EXTERN(gate_isp_sysmmu)
+GRPGATE_EXTERN(gate_isp_ppmu)
+GRPGATE_EXTERN(gate_isp_bts)
+GRPGATE_EXTERN(gate_isp_cam)
+GRPGATE_EXTERN(gate_isp_vra)
+GRPGATE_EXTERN(gate_mfcmscl_sysmmu)
+GRPGATE_EXTERN(gate_mfcmscl_ppmu)
+GRPGATE_EXTERN(gate_mfcmscl_bts)
+GRPGATE_EXTERN(gate_mfcmscl_mscl)
+GRPGATE_EXTERN(gate_mfcmscl_jpeg)
+GRPGATE_EXTERN(gate_mfcmscl_mfc)
+
+UMUX_EXTERN(umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user)
+UMUX_EXTERN(umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user)
+UMUX_EXTERN(umux_fsys_clkphy_fsys_usb20drd_phyclock_user)
+UMUX_EXTERN(umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user)
+
+DFS_EXTERN(dvfs_cpucl0)
+DFS_EXTERN(dvfs_g3d)
+DFS_EXTERN(dvfs_mif)
+DFS_EXTERN(dvfs_int)
+DFS_EXTERN(dvfs_disp)
+DFS_EXTERN(dvfs_cam)
+
+#endif

drivers/soc/samsung/pwrcal/S5E7570/S5E7570-vclk.c

@@ -0,0 +1,767 @@
+#include "../pwrcal-pmu.h"
+#include "../pwrcal-clk.h"
+#include "../pwrcal-rae.h"
+#include "S5E7570-cmu.h"
+#include "S5E7570-cmusfr.h"
+#include "S5E7570-vclk.h"
+#include "S5E7570-vclk-internal.h"
+
+struct pwrcal_vclk_grpgate *vclk_grpgate_list[num_of_grpgate];
+struct pwrcal_vclk_m1d1g1 *vclk_m1d1g1_list[num_of_m1d1g1];
+struct pwrcal_vclk_p1 *vclk_p1_list[num_of_p1];
+struct pwrcal_vclk_m1 *vclk_m1_list[num_of_m1];
+struct pwrcal_vclk_d1 *vclk_d1_list[num_of_d1];
+struct pwrcal_vclk_pxmxdx *vclk_pxmxdx_list[num_of_pxmxdx];
+struct pwrcal_vclk_umux *vclk_umux_list[num_of_umux];
+struct pwrcal_vclk_dfs *vclk_dfs_list[num_of_dfs];
+unsigned int vclk_grpgate_list_size = num_of_grpgate;
+unsigned int vclk_m1d1g1_list_size = num_of_m1d1g1;
+unsigned int vclk_p1_list_size = num_of_p1;
+unsigned int vclk_m1_list_size = num_of_m1;
+unsigned int vclk_d1_list_size = num_of_d1;
+unsigned int vclk_pxmxdx_list_size = num_of_pxmxdx;
+unsigned int vclk_umux_list_size = num_of_umux;
+unsigned int vclk_dfs_list_size = num_of_dfs;
+
+#define ADD_LIST(to, x)		to[x & 0xFFF] = &(vclk_##x)
+
+static struct pwrcal_clk_set pxmxdx_top_grp[] = {
+	{CLK_NONE,				0,	0},
+};
+static struct pwrcal_clk_set pxmxdx_dispaud_grp[] = {
+	{CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),	1,	0},
+	{CLK(DISPAUD_DIV_CLK_DISPAUD_APB),	1,	-1},
+	{CLK_NONE,				0,	0},
+};
+static struct pwrcal_clk_set pxmxdx_mfcmscl_grp[] = {
+	{CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER),	1,	0},
+	{CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER),	1,	0},
+	{CLK(MFCMSCL_DIV_CLK_MFCMSCL_APB),	2,	-1},
+	{CLK_NONE,				0,	0},
+};
+static struct pwrcal_clk_set pxmxdx_isp_vra_grp[] = {
+	{CLK(ISP_MUX_CLKCMU_ISP_VRA_USER),	1,	0},
+	{CLK_NONE,				0,	0},
+};
+static struct pwrcal_clk_set pxmxdx_isp_cam_grp[] = {
+	{CLK(ISP_MUX_CLKCMU_ISP_CAM_USER),	1,	0},
+	{CLK(ISP_DIV_CLK_ISP_CAM_HALF),	1,	-1},
+	{CLK_NONE,				0,	0},
+};
+static struct pwrcal_clk_set pxmxdx_oscclk_aud_grp[] = {
+	{CLK(PMU_DEBUG_CLKOUT_SEL08),	1,	-1},
+	{CLK(PMU_DEBUG_CLKOUT_SEL09),	1,	-1},
+	{CLK(PMU_DEBUG_CLKOUT_SEL10),	1,	-1},
+	{CLK(PMU_DEBUG_CLKOUT_SEL11),	1,	-1},
+	{CLK(PMU_DEBUG_CLKOUT_SEL12),	1,	-1},
+	{CLK(PMU_DEBUG_CLKOUT_DISABLE),	0,	1},
+	{CLK_NONE,			0,	0},
+};
+
+PXMXDX(pxmxdx_top,	0,	pxmxdx_top_grp);
+PXMXDX(pxmxdx_dispaud,	dvfs_disp,	pxmxdx_dispaud_grp);
+PXMXDX(pxmxdx_mfcmscl,	0,	pxmxdx_mfcmscl_grp);
+PXMXDX(pxmxdx_isp_vra,	0,	pxmxdx_isp_vra_grp);
+PXMXDX(pxmxdx_isp_cam,	0,	pxmxdx_isp_cam_grp);
+PXMXDX(pxmxdx_oscclk_aud,	0,	pxmxdx_oscclk_aud_grp);
+
+P1(p1_aud_pll, 0, AUD_PLL);
+P1(p1_wpll_usb_pll, 0, WPLL_USB_PLL);
+/* USB PHY Ref CLK */
+
+M1(m1_dummy, 0, 0);
+
+D1(sclk_decon_vclk_local, sclk_decon_vclk, DISPAUD_DIV_CLK_DISPAUD_DECON_INT_VCLK);
+D1(d1_dispaud_mi2s, 0, DISPAUD_DIV_CLK_DISPAUD_MI2S);
+D1(d1_dispaud_mixer, 0, DISPAUD_DIV_CLK_DISPAUD_MIXER);
+D1(d1_dispaud_oscclk_fm_52m, 0, DISPAUD_DIV_CLK_DISPAUD_OSCCLK_FM_52M_DIV);
+
+M1D1G1(sclk_decon_vclk, 0, MIF_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK, MIF_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK, MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK, DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER);
+M1D1G1(sclk_mmc0, 0, MIF_MUX_CLKCMU_FSYS_MMC0, MIF_DIV_CLKCMU_FSYS_MMC0, MIF_GATE_CLKCMU_FSYS_MMC0, 0);
+M1D1G1(sclk_mmc2, 0, MIF_MUX_CLKCMU_FSYS_MMC2, MIF_DIV_CLKCMU_FSYS_MMC2, MIF_GATE_CLKCMU_FSYS_MMC2, 0);
+M1D1G1(sclk_usb20drd_refclk, 0, MIF_MUX_CLKCMU_FSYS_USB20DRD_REFCLK, MIF_DIV_CLKCMU_FSYS_USB20DRD_REFCLK, MIF_GATE_CLKCMU_FSYS_USB20DRD_REFCLK, 0);
+M1D1G1(sclk_uart_debug, gate_peri_peric0, MIF_MUX_CLKCMU_PERI_UART_DEBUG, MIF_DIV_CLKCMU_PERI_UART_DEBUG, MIF_GATE_CLKCMU_PERI_UART_DEBUG, 0);
+M1D1G1(sclk_uart_sensor, gate_peri_peric0, MIF_MUX_CLKCMU_PERI_UART_SENSOR, MIF_DIV_CLKCMU_PERI_UART_SENSOR, MIF_GATE_CLKCMU_PERI_UART_SENSOR, 0);
+M1D1G1(sclk_spi_ese, gate_peri_peris0, MIF_MUX_CLKCMU_PERI_SPI_ESE, MIF_DIV_CLKCMU_PERI_SPI_ESE, MIF_GATE_CLKCMU_PERI_SPI_ESE, 0);
+M1D1G1(sclk_spi_rearfrom, gate_peri_peric1, MIF_MUX_CLKCMU_PERI_SPI_REARFROM, MIF_DIV_CLKCMU_PERI_SPI_REARFROM, MIF_GATE_CLKCMU_PERI_SPI_REARFROM, 0);
+M1D1G1(sclk_usi0, gate_peri_peric1, MIF_MUX_CLKCMU_PERI_USI_0, MIF_DIV_CLKCMU_PERI_USI_0, MIF_GATE_CLKCMU_PERI_USI_0, 0);
+M1D1G1(sclk_usi1, gate_peri_peric1, MIF_MUX_CLKCMU_PERI_USI_1, MIF_DIV_CLKCMU_PERI_USI_1, MIF_GATE_CLKCMU_PERI_USI_1, 0);
+M1D1G1(sclk_apm, 0, MIF_MUX_CLKCMU_APM, MIF_DIV_CLKCMU_APM, MIF_GATE_CLKCMU_APM, APM_MUX_CLKCMU_APM_USER);
+M1D1G1(sclk_isp_sensor0, 0, MIF_MUX_CLKCMU_ISP_SENSOR0, MIF_DIV_CLKCMU_ISP_SENSOR0, MIF_GATE_CLKCMU_ISP_SENSOR0, 0);
+
+
+static struct pwrcal_clk *gategrp_mif_pdma[] = {
+	CLK(MIF_GATE_CLK_MIF_UID_PDMA_MIF_IPCLKPORT_ACLK_PDMA0),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mif_adcif[] = {
+	CLK(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0),
+	CLK(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mif_speedy[] = {
+	CLK(MIF_GATE_CLK_MIF_UID_SPEEDY_MIF_IPCLKPORT_PCLK),
+	CLK(MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_AP),
+	CLK(MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_SPEEDY),
+	CLK(MIF_GATE_CLK_MIF_UID_SPEEDY_MIF_IPCLKPORT_CLK), /* TCXO */
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_apm_apm[] = {
+	CLK(APM_GATE_CLK_APM_UID_ASYNCS_APM_IPCLKPORT_I_CLK),
+	CLK(APM_GATE_CLK_APM_UID_APM_IPCLKPORT_ACLK_CPU),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_cpucl0_bcm[] = {
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_cpucl0_bts[] = {
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_common_disp[] = {
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU),
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP),
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS),
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_common_dsim0[] = {
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_TXBYTECLKHS),
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_RXCLKESC0),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_common_aud[] = {
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_sysmmu[] = {
+	CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_bcm[] = {
+	CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_bts[] = {
+	CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_decon[] = {
+	CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_dsim0[] = {
+	CLK(DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_mixer[] = {
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_mi2s_aud[] = {
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_mi2s_amp[] = {
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP),
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_common[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_BUS),
+/* 	CLK(FSYS_GATE_CLK_FSYS_UID_BUSD0_FSYS_IPCLKPORT_ACLK), clocks for secure IP*/
+/*	CLK(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK), */
+/*	CLK(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK), */
+/*	CLK(FSYS_GATE_CLK_FSYS_UID_ASYNCS_D_FSYS_IPCLKPORT_I_CLK), */
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_common_busp2[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_BUS),
+/*	CLK(FSYS_GATE_CLK_FSYS_UID_BUSP2_FSYS_IPCLKPORT_HCLK), clock for secure IP */
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_common_busp3[] = {
+	CLK(FSYS_GATE_CLK_FSYS_UID_BUSP3_FSYS_IPCLKPORT_HCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_sysmmu[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_bcm[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_bts[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_usb20drd[] = {
+	CLK(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HCLK_USB20_CTRL),
+	CLK(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_HSDRD),
+	CLK(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_ref_clk),
+	CLK(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_PHYCLOCK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_mmc0[] = {
+	CLK(FSYS_GATE_CLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_sclk_mmc0[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_MMC0),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_mmc2[] = {
+	CLK(FSYS_GATE_CLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_sclk_mmc2[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_MMC2),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_sss[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_rtic[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_g3d_common[] = {
+	CLK(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK),
+	CLK(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_g3d_sysmmu[] = {
+	CLK(G3D_DIV_CLK_G3D_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_g3d_bcm[] = {
+	CLK(G3D_DIV_CLK_G3D_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_g3d_bts[] = {
+	CLK(G3D_DIV_CLK_G3D_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_g3d_g3d[] = {
+	CLK(G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK),
+	CLK(G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK),
+	CLK(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM),
+	CLK(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_isp_sysmmu[] = {
+	CLK(ISP_MUX_CLKCMU_ISP_CAM_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_isp_bcm[] = {
+	CLK(ISP_MUX_CLKCMU_ISP_CAM_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_isp_bts[] = {
+	CLK(ISP_MUX_CLKCMU_ISP_CAM_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_isp_cam[] = {
+	CLK(ISP_MUX_CLKCMU_ISP_CAM_USER),
+	CLK(ISP_GATE_CLK_ISP_UID_CLKPHY_ISP_S_RXBYTECLKHS0_S4),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_isp_vra[] = {
+	CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA),
+	CLK_NONE,
+};
+
+static struct pwrcal_clk *gategrp_mfcmscl_sysmmu[] = {
+	CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mfcmscl_bcm[] = {
+	CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mfcmscl_bts[] = {
+	CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mfcmscl_mscl[] = {
+	CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_POLY),
+	CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mfcmscl_jpeg[] = {
+	CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_JPEG),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mfcmscl_mfc[] = {
+	CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_MFC),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_peris0[] = {
+	CLK(MIF_DIV_CLKCMU_PERI_BUS),
+/*	CLK(PERI_GATE_CLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK), clock for secure IP */
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_peric1[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC1_IPCLKPORT_HCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_peric0[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC0_IPCLKPORT_HCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_pwm_motor[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_sclk_pwm_motor[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_OSCCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_mct[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_MCT_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_i2c_sensor2[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_I2C_SENSOR2_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_i2c_sensor1[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_I2C_SENSOR1_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_i2c_tsp[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_I2C_TSP_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_i2c_fuelgauge[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_I2C_FUELGAUGE_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_i2c_nfc[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_I2C_NFC_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_i2c_muic[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_I2C_MUIC_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_hsi2c_frontcam[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTCAM_IPCLKPORT_iPCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_hsi2c_maincam[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_HSI2C_MAINCAM_IPCLKPORT_iPCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_hsi2c_frontsensor[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTSENSOR_IPCLKPORT_iPCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_hsi2c_rearaf[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_HSI2C_REARAF_IPCLKPORT_iPCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_hsi2c_rearsensor[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_HSI2C_REARSENSOR_IPCLKPORT_iPCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_gpio_touch[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_GPIO_TOUCH_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_gpio_top[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_GPIO_TOP_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_gpio_nfc[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_GPIO_NFC_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_gpio_ese[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_GPIO_ESE_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_wdt_cpucl0[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_WDT_CPUCL0_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_uart_debug[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_PCLK),
+	CLK(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_EXT_UCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_uart_sensor[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_PCLK),
+/* TEMP	CLK(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_EXT_UCLK),*/
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_tmu_cpucl0[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL0_IPCLKPORT_PCLK),
+	CLK(PERI_GATE_CLK_PERI_UID_TMU_CPUCL0_IPCLKPORT_I_CLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_spi_ese[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_PCLK),
+	CLK(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_SPI_EXT_CLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_spi_rearfrom[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_PCLK),
+	CLK(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_SPI_EXT_CLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_gpio_alive[] = {
+	CLK(MIF_DIV_CLKCMU_PERI_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_chipid[] = {
+	CLK(MIF_DIV_CLKCMU_PERI_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_otp_con_top[] = {
+	CLK(MIF_DIV_CLKCMU_PERI_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_rtc_alive[] = {
+	CLK(MIF_DIV_CLKCMU_PERI_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_rtc_top[] = {
+	CLK(MIF_DIV_CLKCMU_PERI_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_usi0[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_usi1[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_PCLK),
+	CLK_NONE,
+};
+
+
+GRPGATE(gate_mif_pdma, 0, gategrp_mif_pdma);
+GRPGATE(gate_mif_adcif, 0, gategrp_mif_adcif);
+GRPGATE(gate_mif_speedy, 0, gategrp_mif_speedy);
+GRPGATE(gate_apm_apm, 0, gategrp_apm_apm);
+GRPGATE(gate_cpucl0_bcm, 0, gategrp_cpucl0_bcm);
+GRPGATE(gate_cpucl0_bts, 0, gategrp_cpucl0_bts);
+GRPGATE(gate_dispaud_common_disp, pxmxdx_dispaud, gategrp_dispaud_common_disp);
+GRPGATE(gate_dispaud_common_dsim0, gate_dispaud_common_disp, gategrp_dispaud_common_dsim0);
+GRPGATE(gate_dispaud_common_aud, 0, gategrp_dispaud_common_aud);
+GRPGATE(gate_dispaud_sysmmu, gate_dispaud_common_disp, gategrp_dispaud_sysmmu);
+GRPGATE(gate_dispaud_bcm, gate_dispaud_common_disp, gategrp_dispaud_bcm);
+GRPGATE(gate_dispaud_bts, gate_dispaud_common_disp, gategrp_dispaud_bts);
+GRPGATE(gate_dispaud_decon, gate_dispaud_common_disp, gategrp_dispaud_decon);
+GRPGATE(gate_dispaud_dsim0, gate_dispaud_common_dsim0, gategrp_dispaud_dsim0);
+GRPGATE(gate_dispaud_mixer, gate_dispaud_common_aud, gategrp_dispaud_mixer);
+GRPGATE(gate_dispaud_mi2s_aud, gate_dispaud_common_aud, gategrp_dispaud_mi2s_aud);
+GRPGATE(gate_dispaud_mi2s_amp, gate_dispaud_common_aud, gategrp_dispaud_mi2s_amp);
+GRPGATE(gate_fsys_common, 0, gategrp_fsys_common);
+GRPGATE(gate_fsys_common_busp2, gate_fsys_common, gategrp_fsys_common_busp2);
+GRPGATE(gate_fsys_common_busp3, gate_fsys_common, gategrp_fsys_common_busp3);
+GRPGATE(gate_fsys_sysmmu, gate_fsys_common, gategrp_fsys_sysmmu);
+GRPGATE(gate_fsys_bcm, gate_fsys_common, gategrp_fsys_bcm);
+GRPGATE(gate_fsys_bts, gate_fsys_common, gategrp_fsys_bts);
+GRPGATE(gate_fsys_usb20drd, gate_fsys_common_busp3, gategrp_fsys_usb20drd);
+GRPGATE(gate_fsys_mmc0, gate_fsys_common_busp3, gategrp_fsys_mmc0);
+GRPGATE(gate_fsys_sclk_mmc0, sclk_mmc0, gategrp_fsys_sclk_mmc0);
+GRPGATE(gate_fsys_mmc2, gate_fsys_common_busp3, gategrp_fsys_mmc2);
+GRPGATE(gate_fsys_sclk_mmc2, sclk_mmc2, gategrp_fsys_sclk_mmc2);
+GRPGATE(gate_fsys_sss, gate_fsys_common_busp2, gategrp_fsys_sss);
+GRPGATE(gate_fsys_rtic, gate_fsys_common_busp2, gategrp_fsys_rtic);
+
+GRPGATE(gate_g3d_common, dvfs_g3d, gategrp_g3d_common);
+GRPGATE(gate_g3d_sysmmu, gate_g3d_common, gategrp_g3d_sysmmu);
+GRPGATE(gate_g3d_bcm, gate_g3d_common, gategrp_g3d_bcm);
+GRPGATE(gate_g3d_bts, gate_g3d_common, gategrp_g3d_bts);
+GRPGATE(gate_g3d_g3d, gate_g3d_common, gategrp_g3d_g3d);
+
+GRPGATE(gate_isp_sysmmu, dvfs_cam, gategrp_isp_sysmmu);
+GRPGATE(gate_isp_bcm, dvfs_cam, gategrp_isp_bcm);
+GRPGATE(gate_isp_bts, dvfs_cam, gategrp_isp_bts);
+GRPGATE(gate_isp_cam, pxmxdx_isp_cam, gategrp_isp_cam);
+GRPGATE(gate_isp_vra, pxmxdx_isp_vra, gategrp_isp_vra);
+
+GRPGATE(gate_mfcmscl_sysmmu, pxmxdx_mfcmscl, gategrp_mfcmscl_sysmmu);
+GRPGATE(gate_mfcmscl_bcm, pxmxdx_mfcmscl, gategrp_mfcmscl_bcm);
+GRPGATE(gate_mfcmscl_bts, pxmxdx_mfcmscl, gategrp_mfcmscl_bts);
+GRPGATE(gate_mfcmscl_mscl, pxmxdx_mfcmscl, gategrp_mfcmscl_mscl);
+GRPGATE(gate_mfcmscl_jpeg, pxmxdx_mfcmscl, gategrp_mfcmscl_jpeg);
+GRPGATE(gate_mfcmscl_mfc, pxmxdx_mfcmscl, gategrp_mfcmscl_mfc);
+
+GRPGATE(gate_peri_peris0, 0, gategrp_peri_peris0);
+GRPGATE(gate_peri_peric1, 0, gategrp_peri_peric1);
+GRPGATE(gate_peri_peric0, 0, gategrp_peri_peric0);
+GRPGATE(gate_peri_pwm_motor, gate_peri_peric1, gategrp_peri_pwm_motor);
+GRPGATE(gate_peri_sclk_pwm_motor, gate_peri_peric1, gategrp_peri_sclk_pwm_motor);
+GRPGATE(gate_peri_mct, 0, gategrp_peri_mct);
+GRPGATE(gate_peri_i2c_sensor2, gate_peri_peric0, gategrp_peri_i2c_sensor2);
+GRPGATE(gate_peri_i2c_sensor1, gate_peri_peric0, gategrp_peri_i2c_sensor1);
+GRPGATE(gate_peri_i2c_tsp, gate_peri_peric0, gategrp_peri_i2c_tsp);
+GRPGATE(gate_peri_i2c_fuelgauge, gate_peri_peric0, gategrp_peri_i2c_fuelgauge);
+GRPGATE(gate_peri_i2c_nfc, gate_peri_peric0, gategrp_peri_i2c_nfc);
+GRPGATE(gate_peri_i2c_muic, gate_peri_peric0, gategrp_peri_i2c_muic);
+GRPGATE(gate_peri_hsi2c_frontcam, gate_peri_peric1, gategrp_peri_hsi2c_frontcam);
+GRPGATE(gate_peri_hsi2c_maincam, gate_peri_peric1, gategrp_peri_hsi2c_maincam);
+GRPGATE(gate_peri_hsi2c_frontsensor, gate_peri_peric0, gategrp_peri_hsi2c_frontsensor);
+GRPGATE(gate_peri_hsi2c_rearaf, gate_peri_peric0, gategrp_peri_hsi2c_rearaf);
+GRPGATE(gate_peri_hsi2c_rearsensor, gate_peri_peric0, gategrp_peri_hsi2c_rearsensor);
+GRPGATE(gate_peri_gpio_touch, gate_peri_peric1, gategrp_peri_gpio_touch);
+GRPGATE(gate_peri_gpio_top, gate_peri_peric1, gategrp_peri_gpio_top);
+GRPGATE(gate_peri_gpio_nfc, gate_peri_peric1, gategrp_peri_gpio_nfc);
+GRPGATE(gate_peri_gpio_ese, gate_peri_peric1, gategrp_peri_gpio_ese);
+GRPGATE(gate_peri_wdt_cpucl0, 0, gategrp_peri_wdt_cpucl0);
+GRPGATE(gate_peri_uart_debug, sclk_uart_debug, gategrp_peri_uart_debug);
+GRPGATE(gate_peri_uart_sensor, sclk_uart_sensor, gategrp_peri_uart_sensor);
+GRPGATE(gate_peri_tmu_cpucl0, 0, gategrp_peri_tmu_cpucl0);
+GRPGATE(gate_peri_spi_ese, sclk_spi_ese, gategrp_peri_spi_ese);
+GRPGATE(gate_peri_spi_rearfrom, sclk_spi_rearfrom, gategrp_peri_spi_rearfrom);
+
+GRPGATE(gate_peri_gpio_alive, gate_peri_peric1, gategrp_peri_gpio_alive);
+GRPGATE(gate_peri_chipid, 0, gategrp_peri_chipid);
+GRPGATE(gate_peri_otp_con_top, gate_peri_peris0, gategrp_peri_otp_con_top);
+GRPGATE(gate_peri_rtc_alive, 0, gategrp_peri_rtc_alive);
+GRPGATE(gate_peri_rtc_top, 0, gategrp_peri_rtc_top);
+GRPGATE(gate_peri_usi0, sclk_usi0, gategrp_peri_usi0);
+GRPGATE(gate_peri_usi1, sclk_usi1, gategrp_peri_usi1);
+
+UMUX(umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user, 0, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER);
+UMUX(umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user, 0, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER);
+UMUX(umux_fsys_clkphy_fsys_usb20drd_phyclock_user, 0, FSYS_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER);
+UMUX(umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user, 0, ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER);
+
+void vclk_unused_disable(void)
+{
+/*	vclk_disable(VCLK(sclk_decon_vclk)); */
+/*	vclk_disable(VCLK(sclk_decon_vclk_local)); */
+	vclk_disable(VCLK(sclk_mmc0));
+	vclk_disable(VCLK(sclk_mmc2));
+	vclk_disable(VCLK(sclk_usb20drd_refclk));
+	vclk_disable(VCLK(sclk_spi_rearfrom));
+	vclk_disable(VCLK(sclk_spi_ese));
+	vclk_disable(VCLK(sclk_usi0));
+	vclk_disable(VCLK(sclk_usi1));
+	vclk_disable(VCLK(sclk_isp_sensor0));
+
+	vclk_disable(VCLK(gate_mif_pdma));
+	vclk_disable(VCLK(gate_mif_adcif));
+/*	vclk_disable(VCLK(gate_mif_speedy)); */
+	vclk_disable(VCLK(gate_cpucl0_bcm));
+	vclk_disable(VCLK(gate_cpucl0_bts));
+/*	vclk_disable(VCLK(gate_dispaud_common_disp)); */
+/*	vclk_disable(VCLK(gate_dispaud_common_dsim0)); */
+/*	vclk_disable(VCLK(gate_dispaud_common_aud)); */
+/*	vclk_disable(VCLK(gate_dispaud_sysmmu)); */
+/*	vclk_disable(VCLK(gate_dispaud_bcm)); */
+/*	vclk_disable(VCLK(gate_dispaud_bts)); */
+/*	vclk_disable(VCLK(gate_dispaud_decon)); */
+/*	vclk_disable(VCLK(gate_dispaud_dsim0)); */
+/*	vclk_disable(VCLK(gate_dispaud_mixer)); */
+/*	vclk_disable(VCLK(gate_dispaud_mi2s_aud)); */
+/*	vclk_disable(VCLK(gate_dispaud_mi2s_amp)); */
+
+	vclk_disable(VCLK(gate_peri_i2c_sensor2));
+	vclk_disable(VCLK(gate_peri_i2c_sensor1));
+	vclk_disable(VCLK(gate_peri_i2c_tsp));
+	vclk_disable(VCLK(gate_peri_i2c_fuelgauge));
+	vclk_disable(VCLK(gate_peri_i2c_nfc));
+	vclk_disable(VCLK(gate_peri_i2c_muic));
+	vclk_disable(VCLK(gate_peri_hsi2c_frontcam));
+	vclk_disable(VCLK(gate_peri_hsi2c_maincam));
+	vclk_disable(VCLK(gate_peri_hsi2c_frontsensor));
+	vclk_disable(VCLK(gate_peri_hsi2c_rearaf));
+	vclk_disable(VCLK(gate_peri_hsi2c_rearsensor));
+	vclk_disable(VCLK(gate_peri_spi_ese));
+	vclk_disable(VCLK(gate_peri_spi_rearfrom));
+	vclk_disable(VCLK(gate_peri_usi0));
+	vclk_disable(VCLK(gate_peri_usi1));
+
+	vclk_disable(VCLK(gate_fsys_sysmmu));
+	vclk_disable(VCLK(gate_fsys_bcm));
+	vclk_disable(VCLK(gate_fsys_bts));
+	vclk_disable(VCLK(gate_fsys_usb20drd));
+	vclk_disable(VCLK(gate_fsys_mmc0));
+	vclk_disable(VCLK(gate_fsys_sclk_mmc0));
+	vclk_disable(VCLK(gate_fsys_mmc2));
+	vclk_disable(VCLK(gate_fsys_sclk_mmc2));
+/*	vclk_disable(VCLK(gate_fsys_sss)); */
+/*	vclk_disable(VCLK(gate_fsys_rtic)); */
+
+	vclk_disable(VCLK(gate_g3d_sysmmu));
+	vclk_disable(VCLK(gate_g3d_bcm));
+	vclk_disable(VCLK(gate_g3d_bts));
+	vclk_disable(VCLK(gate_g3d_g3d));
+
+	vclk_disable(VCLK(gate_isp_sysmmu));
+	vclk_disable(VCLK(gate_isp_bcm));
+	vclk_disable(VCLK(gate_isp_bts));
+	vclk_disable(VCLK(gate_isp_cam));
+	vclk_disable(VCLK(gate_isp_vra));
+
+	vclk_disable(VCLK(gate_mfcmscl_sysmmu));
+	vclk_disable(VCLK(gate_mfcmscl_bcm));
+	vclk_disable(VCLK(gate_mfcmscl_bts));
+	vclk_disable(VCLK(gate_mfcmscl_mscl));
+	vclk_disable(VCLK(gate_mfcmscl_jpeg));
+	vclk_disable(VCLK(gate_mfcmscl_mfc));
+
+/*	vclk_disable(VCLK(gate_peri_chipid)); */
+/*	vclk_disable(VCLK(gate_peri_otp_con_top)); */
+/*	vclk_disable(VCLK(gate_peri_rtc_alive)); */
+/*	vclk_disable(VCLK(gate_peri_rtc_top)); */
+
+/*	vclk_disable(VCLK(pxmxdx_dispaud)); */
+	vclk_disable(VCLK(pxmxdx_mfcmscl));
+	vclk_disable(VCLK(pxmxdx_isp_vra));
+	vclk_disable(VCLK(pxmxdx_isp_cam));
+	vclk_disable(VCLK(pxmxdx_oscclk_aud));
+
+	vclk_disable(VCLK(p1_aud_pll));
+/*	vclk_disable(VCLK(p1_wpll_usb_pll)); */
+
+	vclk_disable(VCLK(d1_dispaud_mi2s));
+	vclk_disable(VCLK(d1_dispaud_mixer));
+	vclk_disable(VCLK(d1_dispaud_oscclk_fm_52m));
+
+	return;
+}
+
+void vclk_init(void)
+{
+	ADD_LIST(vclk_pxmxdx_list, pxmxdx_top);
+	ADD_LIST(vclk_pxmxdx_list, pxmxdx_dispaud);
+	ADD_LIST(vclk_pxmxdx_list, pxmxdx_mfcmscl);
+	ADD_LIST(vclk_pxmxdx_list, pxmxdx_isp_vra);
+	ADD_LIST(vclk_pxmxdx_list, pxmxdx_isp_cam);
+	ADD_LIST(vclk_pxmxdx_list, pxmxdx_oscclk_aud);
+
+	ADD_LIST(vclk_p1_list, p1_aud_pll);
+	ADD_LIST(vclk_p1_list, p1_wpll_usb_pll);
+
+	ADD_LIST(vclk_m1_list, m1_dummy);
+
+	ADD_LIST(vclk_d1_list, sclk_decon_vclk_local);
+	ADD_LIST(vclk_d1_list, d1_dispaud_mi2s);
+	ADD_LIST(vclk_d1_list, d1_dispaud_mixer);
+	ADD_LIST(vclk_d1_list, d1_dispaud_oscclk_fm_52m);
+
+	ADD_LIST(vclk_m1d1g1_list, sclk_decon_vclk);
+	ADD_LIST(vclk_m1d1g1_list, sclk_mmc0);
+	ADD_LIST(vclk_m1d1g1_list, sclk_mmc2);
+	ADD_LIST(vclk_m1d1g1_list, sclk_usb20drd_refclk);
+	ADD_LIST(vclk_m1d1g1_list, sclk_uart_debug);
+	ADD_LIST(vclk_m1d1g1_list, sclk_uart_sensor);
+	ADD_LIST(vclk_m1d1g1_list, sclk_spi_rearfrom);
+	ADD_LIST(vclk_m1d1g1_list, sclk_spi_ese);
+	ADD_LIST(vclk_m1d1g1_list, sclk_usi0);
+	ADD_LIST(vclk_m1d1g1_list, sclk_usi1);
+	ADD_LIST(vclk_m1d1g1_list, sclk_apm);
+	ADD_LIST(vclk_m1d1g1_list, sclk_isp_sensor0);
+
+	ADD_LIST(vclk_grpgate_list, gate_mif_pdma);
+	ADD_LIST(vclk_grpgate_list, gate_mif_adcif);
+	ADD_LIST(vclk_grpgate_list, gate_mif_speedy);
+	ADD_LIST(vclk_grpgate_list, gate_apm_apm);
+	ADD_LIST(vclk_grpgate_list, gate_cpucl0_bcm);
+	ADD_LIST(vclk_grpgate_list, gate_cpucl0_bts);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_common_disp);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_common_dsim0);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_common_aud);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_sysmmu);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_bcm);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_bts);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_decon);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_dsim0);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_mixer);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_mi2s_aud);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_mi2s_amp);
+
+	ADD_LIST(vclk_grpgate_list, gate_peri_peris0);
+	ADD_LIST(vclk_grpgate_list, gate_peri_peric1);
+	ADD_LIST(vclk_grpgate_list, gate_peri_peric0);
+	ADD_LIST(vclk_grpgate_list, gate_peri_pwm_motor);
+	ADD_LIST(vclk_grpgate_list, gate_peri_sclk_pwm_motor);
+	ADD_LIST(vclk_grpgate_list, gate_peri_mct);
+	ADD_LIST(vclk_grpgate_list, gate_peri_i2c_sensor2);
+	ADD_LIST(vclk_grpgate_list, gate_peri_i2c_sensor1);
+	ADD_LIST(vclk_grpgate_list, gate_peri_i2c_tsp);
+	ADD_LIST(vclk_grpgate_list, gate_peri_i2c_fuelgauge);
+	ADD_LIST(vclk_grpgate_list, gate_peri_i2c_nfc);
+	ADD_LIST(vclk_grpgate_list, gate_peri_i2c_muic);
+	ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_frontcam);
+	ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_maincam);
+	ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_frontsensor);
+	ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_rearaf);
+	ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_rearsensor);
+	ADD_LIST(vclk_grpgate_list, gate_peri_gpio_touch);
+	ADD_LIST(vclk_grpgate_list, gate_peri_gpio_top);
+	ADD_LIST(vclk_grpgate_list, gate_peri_gpio_nfc);
+	ADD_LIST(vclk_grpgate_list, gate_peri_gpio_ese);
+	ADD_LIST(vclk_grpgate_list, gate_peri_wdt_cpucl0);
+	ADD_LIST(vclk_grpgate_list, gate_peri_uart_debug);
+	ADD_LIST(vclk_grpgate_list, gate_peri_uart_sensor);
+	ADD_LIST(vclk_grpgate_list, gate_peri_tmu_cpucl0);
+	ADD_LIST(vclk_grpgate_list, gate_peri_spi_ese);
+	ADD_LIST(vclk_grpgate_list, gate_peri_spi_rearfrom);
+	ADD_LIST(vclk_grpgate_list, gate_peri_usi0);
+	ADD_LIST(vclk_grpgate_list, gate_peri_usi1);
+
+	ADD_LIST(vclk_grpgate_list, gate_fsys_common);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_common_busp2);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_common_busp3);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_sysmmu);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_bcm);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_bts);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_usb20drd);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_mmc0);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_sclk_mmc0);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_mmc2);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_sclk_mmc2);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_sss);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_rtic);
+
+	ADD_LIST(vclk_grpgate_list, gate_g3d_common);
+	ADD_LIST(vclk_grpgate_list, gate_g3d_sysmmu);
+	ADD_LIST(vclk_grpgate_list, gate_g3d_bcm);
+	ADD_LIST(vclk_grpgate_list, gate_g3d_bts);
+	ADD_LIST(vclk_grpgate_list, gate_g3d_g3d);
+
+	ADD_LIST(vclk_grpgate_list, gate_isp_sysmmu);
+	ADD_LIST(vclk_grpgate_list, gate_isp_bcm);
+	ADD_LIST(vclk_grpgate_list, gate_isp_bts);
+	ADD_LIST(vclk_grpgate_list, gate_isp_cam);
+	ADD_LIST(vclk_grpgate_list, gate_isp_vra);
+
+	ADD_LIST(vclk_grpgate_list, gate_mfcmscl_sysmmu);
+	ADD_LIST(vclk_grpgate_list, gate_mfcmscl_bcm);
+	ADD_LIST(vclk_grpgate_list, gate_mfcmscl_bts);
+	ADD_LIST(vclk_grpgate_list, gate_mfcmscl_mscl);
+	ADD_LIST(vclk_grpgate_list, gate_mfcmscl_jpeg);
+	ADD_LIST(vclk_grpgate_list, gate_mfcmscl_mfc);
+
+	ADD_LIST(vclk_grpgate_list, gate_peri_gpio_alive);
+	ADD_LIST(vclk_grpgate_list, gate_peri_chipid);
+	ADD_LIST(vclk_grpgate_list, gate_peri_otp_con_top);
+	ADD_LIST(vclk_grpgate_list, gate_peri_rtc_alive);
+	ADD_LIST(vclk_grpgate_list, gate_peri_rtc_top);
+
+	ADD_LIST(vclk_umux_list, umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user);
+	ADD_LIST(vclk_umux_list, umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user);
+	ADD_LIST(vclk_umux_list, umux_fsys_clkphy_fsys_usb20drd_phyclock_user);
+	ADD_LIST(vclk_umux_list, umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user);
+
+	ADD_LIST(vclk_dfs_list, dvfs_cpucl0);
+	ADD_LIST(vclk_dfs_list, dvfs_g3d);
+	ADD_LIST(vclk_dfs_list, dvfs_mif);
+	ADD_LIST(vclk_dfs_list, dvfs_int);
+	ADD_LIST(vclk_dfs_list, dvfs_disp);
+	ADD_LIST(vclk_dfs_list, dvfs_cam);
+
+	vclk_enable(VCLK(gate_peri_peric0));
+	vclk_enable(VCLK(gate_peri_peric1));
+
+	return;
+}

drivers/soc/samsung/pwrcal/S5E7570/S5E7570-vclk.h

@@ -0,0 +1,147 @@
+#ifndef __EXYNOS7570_VCLK_H__
+#define __EXYNOS7570_VCLK_H__
+
+enum {
+	gate_mif_pdma = 0x0A000000,
+	gate_mif_adcif,
+	gate_mif_speedy,
+	gate_apm_apm,
+	gate_cpucl0_bcm,
+	gate_cpucl0_bts,
+	gate_dispaud_common_disp,
+	gate_dispaud_common_dsim0,
+	gate_dispaud_common_aud,
+	gate_dispaud_sysmmu,
+	gate_dispaud_bcm,
+	gate_dispaud_bts,
+	gate_dispaud_decon,
+	gate_dispaud_dsim0,
+	gate_dispaud_mixer,
+	gate_dispaud_mi2s_aud,
+	gate_dispaud_mi2s_amp,
+
+	gate_peri_peris0,
+	gate_peri_peric1,
+	gate_peri_peric0,
+	gate_peri_pwm_motor,
+	gate_peri_sclk_pwm_motor,
+	gate_peri_mct,
+	gate_peri_i2c_sensor2,
+	gate_peri_i2c_sensor1,
+	gate_peri_i2c_tsp,
+	gate_peri_i2c_fuelgauge,
+	gate_peri_i2c_nfc,
+	gate_peri_i2c_muic,
+	gate_peri_hsi2c_frontcam,
+	gate_peri_hsi2c_maincam,
+	gate_peri_hsi2c_frontsensor,
+	gate_peri_hsi2c_rearaf,
+	gate_peri_hsi2c_rearsensor,
+	gate_peri_gpio_touch,
+	gate_peri_gpio_top,
+	gate_peri_gpio_nfc,
+	gate_peri_gpio_ese,
+	gate_peri_wdt_cpucl0,
+	gate_peri_uart_debug,
+	gate_peri_uart_sensor,
+	gate_peri_tmu_cpucl0,
+	gate_peri_spi_ese,
+	gate_peri_spi_rearfrom,
+	gate_peri_gpio_alive,
+	gate_peri_chipid,
+	gate_peri_otp_con_top,
+	gate_peri_rtc_alive,
+	gate_peri_rtc_top,
+	gate_peri_usi0,
+	gate_peri_usi1,
+
+	gate_fsys_common,
+	gate_fsys_common_busp2,
+	gate_fsys_common_busp3,
+	gate_fsys_sysmmu,
+	gate_fsys_bcm,
+	gate_fsys_bts,
+	gate_fsys_usb20drd,
+	gate_fsys_mmc0,
+	gate_fsys_sclk_mmc0,
+	gate_fsys_mmc2,
+	gate_fsys_sclk_mmc2,
+	gate_fsys_sss,
+	gate_fsys_rtic,
+	gate_g3d_common,
+	gate_g3d_sysmmu,
+	gate_g3d_bcm,
+	gate_g3d_bts,
+	gate_g3d_g3d,
+	gate_isp_sysmmu,
+	gate_isp_bcm,
+	gate_isp_bts,
+	gate_isp_cam,
+	gate_isp_vra,
+	gate_mfcmscl_sysmmu,
+	gate_mfcmscl_bcm,
+	gate_mfcmscl_bts,
+	gate_mfcmscl_mscl,
+	gate_mfcmscl_jpeg,
+	gate_mfcmscl_mfc,
+	vclk_group_grpgate_end,
+	num_of_grpgate = vclk_group_grpgate_end - 0x0A000000,
+
+	sclk_decon_vclk = 0x0A010000,
+	sclk_mmc0,
+	sclk_mmc2,
+	sclk_usb20drd_refclk,
+	sclk_uart_debug,
+	sclk_uart_sensor,
+	sclk_spi_rearfrom,
+	sclk_spi_ese,
+	sclk_usi0,
+	sclk_usi1,
+	sclk_apm,
+	sclk_isp_sensor0,
+	vclk_group_m1d1g1_end,
+	num_of_m1d1g1 = vclk_group_m1d1g1_end - 0x0A010000,
+
+	p1_aud_pll = 0x0A020000,
+	p1_wpll_usb_pll,
+	vclk_group_p1_end,
+	num_of_p1 = vclk_group_p1_end - 0x0A020000,
+
+	m1_dummy = 0x0A030000,
+	vclk_group_m1_end,
+	num_of_m1 = vclk_group_m1_end - 0x0A030000,
+
+	sclk_decon_vclk_local = 0x0A040000,
+	d1_dispaud_mi2s,
+	d1_dispaud_mixer,
+	d1_dispaud_oscclk_fm_52m,
+	vclk_group_d1_end,
+	num_of_d1 = vclk_group_d1_end - 0x0A040000,
+
+	pxmxdx_top = 0x0A050000,
+	pxmxdx_dispaud,
+	pxmxdx_mfcmscl,
+	pxmxdx_isp_vra,
+	pxmxdx_isp_cam,
+	pxmxdx_oscclk_aud,
+	vclk_group_pxmxdx_end,
+	num_of_pxmxdx = vclk_group_pxmxdx_end - 0x0A050000,
+
+	umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user = 0x0A060000,
+	umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user,
+	umux_fsys_clkphy_fsys_usb20drd_phyclock_user,
+	umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user,
+	vclk_group_umux_end,
+	num_of_umux = vclk_group_umux_end - 0x0A060000,
+
+	dvfs_cpucl0 = 0x0A070000,
+	dvfs_g3d,
+	dvfs_mif,
+	dvfs_int,
+	dvfs_disp,
+	dvfs_cam,
+	vclk_group_dfs_end,
+	num_of_dfs = vclk_group_dfs_end - 0x0A070000,
+};
+
+#endif

drivers/soc/samsung/pwrcal/S5E7870/S5E7870-cmusfr.h

@@ -0,0 +1,484 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd. All rights reserved.
+ *		http://www.samsung.com
+ *
+ * Chip Abstraction Layer for local/system power down support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __EXYNOS7870_CMUSFR_H__
+#define __EXYNOS7870_CMUSFR_H__
+
+#include "S5E7870-sfrbase.h"
+
+
+#define MEM_PLL_LOCK	((void *)(CMU_MIF_BASE + 0x0000))
+#define MEDIA_PLL_LOCK	((void *)(CMU_MIF_BASE + 0x0020))
+#define BUS_PLL_LOCK	((void *)(CMU_MIF_BASE + 0x0040))
+#define MEM_PLL_CON0	((void *)(CMU_MIF_BASE + 0x0100))
+#define MEM_PLL_CON1	((void *)(CMU_MIF_BASE + 0x0104))
+#define MEDIA_PLL_CON0	((void *)(CMU_MIF_BASE + 0x0120))
+#define MEDIA_PLL_CON1	((void *)(CMU_MIF_BASE + 0x0124))
+#define BUS_PLL_CON0	((void *)(CMU_MIF_BASE + 0x0140))
+#define BUS_PLL_CON1	((void *)(CMU_MIF_BASE + 0x0144))
+#define CLK_CON_MUX_MEM_PLL	((void *)(CMU_MIF_BASE + 0x0200))
+#define CLK_CON_MUX_MEDIA_PLL	((void *)(CMU_MIF_BASE + 0x0204))
+#define CLK_CON_MUX_BUS_PLL	((void *)(CMU_MIF_BASE + 0x0208))
+#define CLK_CON_MUX_CLK_MIF_PHY_CLK2X	((void *)(CMU_MIF_BASE + 0x0210))
+#define CLK_CON_MUX_CLK_MIF_PHY_SWITCH	((void *)(CMU_MIF_BASE + 0x0214))
+#define CLK_CON_MUX_CLK_MIF_BUSD	((void *)(CMU_MIF_BASE + 0x0220))
+#define CLK_CON_MUX_CLK_MIF_CCI	((void *)(CMU_MIF_BASE + 0x0228))
+#define CLK_CON_MUX_CLKCMU_ISP_VRA	((void *)(CMU_MIF_BASE + 0x0264))
+#define CLK_CON_MUX_CLKCMU_ISP_CAM	((void *)(CMU_MIF_BASE + 0x0268))
+#define CLK_CON_MUX_CLKCMU_ISP_ISP	((void *)(CMU_MIF_BASE + 0x026C))
+#define CLK_CON_MUX_CLKCMU_DISPAUD_BUS	((void *)(CMU_MIF_BASE + 0x0270))
+#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK	((void *)(CMU_MIF_BASE + 0x0274))
+#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK	((void *)(CMU_MIF_BASE + 0x0278))
+#define CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL	((void *)(CMU_MIF_BASE + 0x027C))
+#define CLK_CON_MUX_CLKCMU_MFCMSCL_MFC	((void *)(CMU_MIF_BASE + 0x0280))
+#define CLK_CON_MUX_CLKCMU_FSYS_BUS	((void *)(CMU_MIF_BASE + 0x0284))
+#define CLK_CON_MUX_CLKCMU_FSYS_MMC0	((void *)(CMU_MIF_BASE + 0x0288))
+#define CLK_CON_MUX_CLKCMU_FSYS_MMC1	((void *)(CMU_MIF_BASE + 0x028C))
+#define CLK_CON_MUX_CLKCMU_FSYS_MMC2	((void *)(CMU_MIF_BASE + 0x0290))
+#define CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO	((void *)(CMU_MIF_BASE + 0x0294))
+#define CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG	((void *)(CMU_MIF_BASE + 0x0298))
+#define CLK_CON_MUX_CLKCMU_FSYS_USB20DRD_REFCLK	((void *)(CMU_MIF_BASE + 0x029C))
+#define CLK_CON_MUX_CLKCMU_PERI_BUS	((void *)(CMU_MIF_BASE + 0x02A0))
+#define CLK_CON_MUX_CLKCMU_PERI_UART_BTWIFIFM	((void *)(CMU_MIF_BASE + 0x02A4))
+#define CLK_CON_MUX_CLKCMU_PERI_UART_DEBUG	((void *)(CMU_MIF_BASE + 0x02A8))
+#define CLK_CON_MUX_CLKCMU_PERI_UART_SENSOR	((void *)(CMU_MIF_BASE + 0x02AC))
+#define CLK_CON_MUX_CLKCMU_PERI_SPI_FRONTFROM	((void *)(CMU_MIF_BASE + 0x02B0))
+#define CLK_CON_MUX_CLKCMU_PERI_SPI_REARFROM	((void *)(CMU_MIF_BASE + 0x02B4))
+#define CLK_CON_MUX_CLKCMU_PERI_SPI_ESE	((void *)(CMU_MIF_BASE + 0x02B8))
+#define CLK_CON_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR	((void *)(CMU_MIF_BASE + 0x02BC))
+#define CLK_CON_MUX_CLKCMU_PERI_SPI_SENSORHUB	((void *)(CMU_MIF_BASE + 0x02C0))
+#define CLK_CON_MUX_CLKCMU_ISP_SENSOR0	((void *)(CMU_MIF_BASE + 0x02C4))
+#define CLK_CON_MUX_CLKCMU_ISP_SENSOR1	((void *)(CMU_MIF_BASE + 0x02C8))
+#define CLK_CON_MUX_CLKCMU_ISP_SENSOR2	((void *)(CMU_MIF_BASE + 0x02CC))
+#define CLK_CON_DIV_CLK_MIF_PHY_CLKM	((void *)(CMU_MIF_BASE + 0x0414))
+#define CLK_CON_DIV_CLK_MIF_BUSD	((void *)(CMU_MIF_BASE + 0x0420))
+#define CLK_CON_DIV_CLK_MIF_APB	((void *)(CMU_MIF_BASE + 0x0424))
+#define CLK_CON_DIV_CLK_MIF_CCI	((void *)(CMU_MIF_BASE + 0x0428))
+#define CLK_CON_DIV_CLK_MIF_BUSP	((void *)(CMU_MIF_BASE + 0x042C))
+#define CLK_CON_DIV_CLK_MIF_HSI2C	((void *)(CMU_MIF_BASE + 0x0430))
+#define CLK_CON_DIV_CLKCMU_CP_MEDIA_PLL	((void *)(CMU_MIF_BASE + 0x0450))
+#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH	((void *)(CMU_MIF_BASE + 0x0458))
+#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH	((void *)(CMU_MIF_BASE + 0x045C))
+#define CLK_CON_DIV_CLKCMU_G3D_SWITCH	((void *)(CMU_MIF_BASE + 0x0460))
+#define CLK_CON_DIV_CLKCMU_ISP_VRA	((void *)(CMU_MIF_BASE + 0x0464))
+#define CLK_CON_DIV_CLKCMU_ISP_CAM	((void *)(CMU_MIF_BASE + 0x0468))
+#define CLK_CON_DIV_CLKCMU_ISP_ISP	((void *)(CMU_MIF_BASE + 0x046C))
+#define CLK_CON_DIV_CLKCMU_DISPAUD_BUS	((void *)(CMU_MIF_BASE + 0x0470))
+#define CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK	((void *)(CMU_MIF_BASE + 0x0474))
+#define CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_ECLK	((void *)(CMU_MIF_BASE + 0x0478))
+#define CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL	((void *)(CMU_MIF_BASE + 0x047C))
+#define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC	((void *)(CMU_MIF_BASE + 0x0480))
+#define CLK_CON_DIV_CLKCMU_FSYS_BUS	((void *)(CMU_MIF_BASE + 0x0484))
+#define CLK_CON_DIV_CLKCMU_FSYS_MMC0	((void *)(CMU_MIF_BASE + 0x0488))
+#define CLK_CON_DIV_CLKCMU_FSYS_MMC1	((void *)(CMU_MIF_BASE + 0x048C))
+#define CLK_CON_DIV_CLKCMU_FSYS_MMC2	((void *)(CMU_MIF_BASE + 0x0490))
+#define CLK_CON_DIV_CLKCMU_FSYS_UFSUNIPRO	((void *)(CMU_MIF_BASE + 0x0494))
+#define CLK_CON_DIV_CLKCMU_FSYS_UFSUNIPRO_CFG	((void *)(CMU_MIF_BASE + 0x0498))
+#define CLK_CON_DIV_CLKCMU_FSYS_USB20DRD_REFCLK	((void *)(CMU_MIF_BASE + 0x049C))
+#define CLK_CON_DIV_CLKCMU_PERI_BUS	((void *)(CMU_MIF_BASE + 0x04A0))
+#define CLK_CON_DIV_CLKCMU_PERI_UART_BTWIFIFM	((void *)(CMU_MIF_BASE + 0x04A4))
+#define CLK_CON_DIV_CLKCMU_PERI_UART_DEBUG	((void *)(CMU_MIF_BASE + 0x04A8))
+#define CLK_CON_DIV_CLKCMU_PERI_UART_SENSOR	((void *)(CMU_MIF_BASE + 0x04AC))
+#define CLK_CON_DIV_CLKCMU_PERI_SPI_FRONTFROM	((void *)(CMU_MIF_BASE + 0x04B0))
+#define CLK_CON_DIV_CLKCMU_PERI_SPI_REARFROM	((void *)(CMU_MIF_BASE + 0x04B4))
+#define CLK_CON_DIV_CLKCMU_PERI_SPI_ESE	((void *)(CMU_MIF_BASE + 0x04B8))
+#define CLK_CON_DIV_CLKCMU_PERI_SPI_VOICEPROCESSOR	((void *)(CMU_MIF_BASE + 0x04BC))
+#define CLK_CON_DIV_CLKCMU_PERI_SPI_SENSORHUB	((void *)(CMU_MIF_BASE + 0x04C0))
+#define CLK_CON_DIV_CLKCMU_ISP_SENSOR0	((void *)(CMU_MIF_BASE + 0x04C4))
+#define CLK_CON_DIV_CLKCMU_ISP_SENSOR1	((void *)(CMU_MIF_BASE + 0x04C8))
+#define CLK_CON_DIV_CLKCMU_ISP_SENSOR2	((void *)(CMU_MIF_BASE + 0x04CC))
+#define CLK_STAT_MUX_MEM_PLL	((void *)(CMU_MIF_BASE + 0x0600))
+#define CLK_STAT_MUX_MEDIA_PLL	((void *)(CMU_MIF_BASE + 0x0604))
+#define CLK_STAT_MUX_BUS_PLL	((void *)(CMU_MIF_BASE + 0x0608))
+#define CLK_STAT_MUX_CLK_MIF_PHY_CLK2X	((void *)(CMU_MIF_BASE + 0x0610))
+#define CLK_STAT_MUX_CLK_MIF_PHY_SWITCH	((void *)(CMU_MIF_BASE + 0x0614))
+#define CLK_STAT_MUX_CLK_MIF_BUSD	((void *)(CMU_MIF_BASE + 0x0620))
+#define CLK_STAT_MUX_CLK_MIF_CCI	((void *)(CMU_MIF_BASE + 0x0628))
+#define CLK_STAT_MUX_CLKCMU_ISP_VRA	((void *)(CMU_MIF_BASE + 0x0664))
+#define CLK_STAT_MUX_CLKCMU_ISP_CAM	((void *)(CMU_MIF_BASE + 0x0668))
+#define CLK_STAT_MUX_CLKCMU_ISP_ISP	((void *)(CMU_MIF_BASE + 0x066C))
+#define CLK_STAT_MUX_CLKCMU_DISPAUD_BUS	((void *)(CMU_MIF_BASE + 0x0670))
+#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK	((void *)(CMU_MIF_BASE + 0x0674))
+#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK	((void *)(CMU_MIF_BASE + 0x0678))
+#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MSCL	((void *)(CMU_MIF_BASE + 0x067C))
+#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MFC	((void *)(CMU_MIF_BASE + 0x0680))
+#define CLK_STAT_MUX_CLKCMU_FSYS_BUS	((void *)(CMU_MIF_BASE + 0x0684))
+#define CLK_STAT_MUX_CLKCMU_FSYS_MMC0	((void *)(CMU_MIF_BASE + 0x0688))
+#define CLK_STAT_MUX_CLKCMU_FSYS_MMC1	((void *)(CMU_MIF_BASE + 0x068C))
+#define CLK_STAT_MUX_CLKCMU_FSYS_MMC2	((void *)(CMU_MIF_BASE + 0x0690))
+#define CLK_STAT_MUX_CLKCMU_FSYS_UFSUNIPRO	((void *)(CMU_MIF_BASE + 0x0694))
+#define CLK_STAT_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG	((void *)(CMU_MIF_BASE + 0x0698))
+#define CLK_STAT_MUX_CLKCMU_FSYS_USB20DRD_REFCLK	((void *)(CMU_MIF_BASE + 0x069C))
+#define CLK_STAT_MUX_CLKCMU_PERI_BUS	((void *)(CMU_MIF_BASE + 0x06A0))
+#define CLK_STAT_MUX_CLKCMU_PERI_UART_BTWIFIFM	((void *)(CMU_MIF_BASE + 0x06A4))
+#define CLK_STAT_MUX_CLKCMU_PERI_UART_DEBUG	((void *)(CMU_MIF_BASE + 0x06A8))
+#define CLK_STAT_MUX_CLKCMU_PERI_UART_SENSOR	((void *)(CMU_MIF_BASE + 0x06AC))
+#define CLK_STAT_MUX_CLKCMU_PERI_SPI_FRONTFROM	((void *)(CMU_MIF_BASE + 0x06B0))
+#define CLK_STAT_MUX_CLKCMU_PERI_SPI_REARFROM	((void *)(CMU_MIF_BASE + 0x06B4))
+#define CLK_STAT_MUX_CLKCMU_PERI_SPI_ESE	((void *)(CMU_MIF_BASE + 0x06B8))
+#define CLK_STAT_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR	((void *)(CMU_MIF_BASE + 0x06BC))
+#define CLK_STAT_MUX_CLKCMU_PERI_SPI_SENSORHUB	((void *)(CMU_MIF_BASE + 0x06C0))
+#define CLK_STAT_MUX_CLKCMU_ISP_SENSOR0	((void *)(CMU_MIF_BASE + 0x06C4))
+#define CLK_STAT_MUX_CLKCMU_ISP_SENSOR1	((void *)(CMU_MIF_BASE + 0x06C8))
+#define CLK_STAT_MUX_CLKCMU_ISP_SENSOR2	((void *)(CMU_MIF_BASE + 0x06CC))
+#define CLK_ENABLE_CLK_MIF_OSCCLK	((void *)(CMU_MIF_BASE + 0x080C))
+#define CLK_ENABLE_CLK_MIF_PHY_CLK2X	((void *)(CMU_MIF_BASE + 0x0810))
+#define CLK_ENABLE_CLK_MIF_PHY_CLKM	((void *)(CMU_MIF_BASE + 0x0814))
+#define CLK_ENABLE_CLK_MIF_DDRPHY0	((void *)(CMU_MIF_BASE + 0x0818))
+#define CLK_ENABLE_CLK_MIF_BUSD	((void *)(CMU_MIF_BASE + 0x0820))
+#define CLK_ENABLE_CLK_MIF_APB0	((void *)(CMU_MIF_BASE + 0x0824))
+#define CLK_ENABLE_CLK_MIF_APB1	((void *)(CMU_MIF_BASE + 0x0828))
+#define CLK_ENABLE_CLK_MIF_APB_SECURE_DMC0	((void *)(CMU_MIF_BASE + 0x082C))
+#define CLK_ENABLE_CLK_MIF_APB_SECURE_MODAPIF	((void *)(CMU_MIF_BASE + 0x0830))
+#define CLK_ENABLE_CLK_MIF_CCI	((void *)(CMU_MIF_BASE + 0x0834))
+#define CLK_ENABLE_CLK_MIF_BUSP	((void *)(CMU_MIF_BASE + 0x0838))
+#define CLK_ENABLE_CLK_MIF_BUSP_SECURE_INTMEM	((void *)(CMU_MIF_BASE + 0x083C))
+#define CLK_ENABLE_CLK_MIF_HSI2C	((void *)(CMU_MIF_BASE + 0x0840))
+#define CLK_ENABLE_CLKCMU_CP_MEDIA_PLL	((void *)(CMU_MIF_BASE + 0x0850))
+#define CLK_ENABLE_CLKCMU_CPUCL0_SWITCH	((void *)(CMU_MIF_BASE + 0x0858))
+#define CLK_ENABLE_CLKCMU_CPUCL1_SWITCH	((void *)(CMU_MIF_BASE + 0x085C))
+#define CLK_ENABLE_CLKCMU_G3D_SWITCH	((void *)(CMU_MIF_BASE + 0x0860))
+#define CLK_ENABLE_CLKCMU_ISP_VRA	((void *)(CMU_MIF_BASE + 0x0864))
+#define CLK_ENABLE_CLKCMU_ISP_CAM	((void *)(CMU_MIF_BASE + 0x0868))
+#define CLK_ENABLE_CLKCMU_ISP_ISP	((void *)(CMU_MIF_BASE + 0x086C))
+#define CLK_ENABLE_CLKCMU_DISPAUD_BUS	((void *)(CMU_MIF_BASE + 0x0870))
+#define CLK_ENABLE_CLKCMU_DISPAUD_DECON_INT_VCLK	((void *)(CMU_MIF_BASE + 0x0874))
+#define CLK_ENABLE_CLKCMU_DISPAUD_DECON_INT_ECLK	((void *)(CMU_MIF_BASE + 0x0878))
+#define CLK_ENABLE_CLKCMU_MFCMSCL_MSCL	((void *)(CMU_MIF_BASE + 0x087C))
+#define CLK_ENABLE_CLKCMU_MFCMSCL_MFC	((void *)(CMU_MIF_BASE + 0x0880))
+#define CLK_ENABLE_CLKCMU_FSYS_BUS	((void *)(CMU_MIF_BASE + 0x0884))
+#define CLK_ENABLE_CLKCMU_FSYS_MMC0	((void *)(CMU_MIF_BASE + 0x0888))
+#define CLK_ENABLE_CLKCMU_FSYS_MMC1	((void *)(CMU_MIF_BASE + 0x088C))
+#define CLK_ENABLE_CLKCMU_FSYS_MMC2	((void *)(CMU_MIF_BASE + 0x0890))
+#define CLK_ENABLE_CLKCMU_FSYS_UFSUNIPRO	((void *)(CMU_MIF_BASE + 0x0894))
+#define CLK_ENABLE_CLKCMU_FSYS_UFSUNIPRO_CFG	((void *)(CMU_MIF_BASE + 0x0898))
+#define CLK_ENABLE_CLKCMU_FSYS_USB20DRD_REFCLK	((void *)(CMU_MIF_BASE + 0x089C))
+#define CLK_ENABLE_CLKCMU_PERI_BUS	((void *)(CMU_MIF_BASE + 0x08A0))
+#define CLK_ENABLE_CLKCMU_PERI_UART_BTWIFIFM	((void *)(CMU_MIF_BASE + 0x08A4))
+#define CLK_ENABLE_CLKCMU_PERI_UART_DEBUG	((void *)(CMU_MIF_BASE + 0x08A8))
+#define CLK_ENABLE_CLKCMU_PERI_UART_SENSOR	((void *)(CMU_MIF_BASE + 0x08AC))
+#define CLK_ENABLE_CLKCMU_PERI_SPI_FRONTFROM	((void *)(CMU_MIF_BASE + 0x08B0))
+#define CLK_ENABLE_CLKCMU_PERI_SPI_REARFROM	((void *)(CMU_MIF_BASE + 0x08B4))
+#define CLK_ENABLE_CLKCMU_PERI_SPI_ESE	((void *)(CMU_MIF_BASE + 0x08B8))
+#define CLK_ENABLE_CLKCMU_PERI_SPI_VOICEPROCESSOR	((void *)(CMU_MIF_BASE + 0x08BC))
+#define CLK_ENABLE_CLKCMU_PERI_SPI_SENSORHUB	((void *)(CMU_MIF_BASE + 0x08C0))
+#define CLK_ENABLE_CLKCMU_ISP_SENSOR0	((void *)(CMU_MIF_BASE + 0x08C4))
+#define CLK_ENABLE_CLKCMU_ISP_SENSOR1	((void *)(CMU_MIF_BASE + 0x08C8))
+#define CLK_ENABLE_CLKCMU_ISP_SENSOR2	((void *)(CMU_MIF_BASE + 0x08CC))
+#define SECURE_ENABLE_CLKCMU_FSYS_BUS	((void *)(CMU_MIF_BASE + 0x08D0))
+#define CLKOUT_CMU_MIF	((void *)(CMU_MIF_BASE + 0x0D00))
+#define CLKOUT_CMU_MIF_DIV_STAT	((void *)(CMU_MIF_BASE + 0x0D04))
+#define CMU_MIF_SPARE0	((void *)(CMU_MIF_BASE + 0x0D08))
+#define CMU_MIF_SPARE1	((void *)(CMU_MIF_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_MIF	((void *)(CMU_MIF_BASE + 0x0E00))
+#define MIF_SFR_IGNORE_REQ_SYSCLK	((void *)(CMU_MIF_BASE + 0x0F00))
+#define MIF_ROOTCLKEN	((void *)(CMU_MIF_BASE + 0x0F04))
+#define MIF_ROOTCLKEN_ON_GATE	((void *)(CMU_MIF_BASE + 0x0F10))
+#define DREX_FREQ_CTRL1	((void *)(CMU_MIF_BASE + 0x1004))
+#define PAUSE	((void *)(CMU_MIF_BASE + 0x1008))
+#define DDRPHY_LOCK_CTRL	((void *)(CMU_MIF_BASE + 0x100C))
+#define ACG_ENABLE	((void *)(CMU_MIF_BASE + 0x1010))
+#define CP_CTRL_HSI2C_ENABLE	((void *)(CMU_MIF_BASE + 0x1014))
+#define CP_CTRL_ADCIF_ENABLE	((void *)(CMU_MIF_BASE + 0x1018))
+#define FAKE_PAUSE	((void *)(CMU_MIF_BASE + 0x1020))
+#define CG_CTRL_VAL_CLK_MIF_BUSD	((void *)(CMU_MIF_BASE + 0x1800))
+#define CG_CTRL_VAL_CLK_MIF_APB	((void *)(CMU_MIF_BASE + 0x1804))
+#define CG_CTRL_VAL_CLK_MIF_CCI	((void *)(CMU_MIF_BASE + 0x1808))
+#define CG_CTRL_MAN_CLK_MIF_BUSD	((void *)(CMU_MIF_BASE + 0x1900))
+#define CG_CTRL_MAN_CLK_MIF_APB	((void *)(CMU_MIF_BASE + 0x1904))
+#define CG_CTRL_MAN_CLK_MIF_CCI	((void *)(CMU_MIF_BASE + 0x1908))
+#define CG_CTRL_STAT_CLK_MIF_BUSD	((void *)(CMU_MIF_BASE + 0x1A00))
+#define CG_CTRL_STAT_CLK_MIF_APB	((void *)(CMU_MIF_BASE + 0x1A04))
+#define CG_CTRL_STAT_CLK_MIF_CCI	((void *)(CMU_MIF_BASE + 0x1A08))
+#define QCH_CTRL_UID_MIF_D_CCI	((void *)(CMU_MIF_BASE + 0x2000))
+#define QCH_CTRL_UID_MIF_D_NRT	((void *)(CMU_MIF_BASE + 0x2004))
+#define QCH_CTRL_UID_MIF_D_RT	((void *)(CMU_MIF_BASE + 0x2008))
+#define QCH_CTRL_UID_ASYNCM_LH_G3D0_MIF_D_NRT	((void *)(CMU_MIF_BASE + 0x200C))
+#define QCH_CTRL_UID_ASYNCM_LH_MFCMSCL0_MIF_D_NRT	((void *)(CMU_MIF_BASE + 0x2010))
+#define QCH_CTRL_UID_ASYNCM_LH_FSYS_MIF_D_NRT	((void *)(CMU_MIF_BASE + 0x2014))
+#define QCH_CTRL_UID_ASYNCM_LH_ISP_MIF_D_NRT	((void *)(CMU_MIF_BASE + 0x2018))
+#define QCH_CTRL_UID_ASYNCM_LH_ISP_MIF_D_RT	((void *)(CMU_MIF_BASE + 0x201C))
+#define QCH_CTRL_UID_ASYNCM_LH_DISPAUD_MIF_D_RT	((void *)(CMU_MIF_BASE + 0x2020))
+
+#define CPUCL0_PLL_LOCK	((void *)(CMU_CPUCL0_BASE + 0x0000))
+#define CPUCL0_PLL_CON0	((void *)(CMU_CPUCL0_BASE + 0x0100))
+#define CPUCL0_PLL_CON1	((void *)(CMU_CPUCL0_BASE + 0x0104))
+#define CLK_CON_MUX_CPUCL0_PLL	((void *)(CMU_CPUCL0_BASE + 0x0200))
+#define CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_USER	((void *)(CMU_CPUCL0_BASE + 0x0204))
+#define CLK_CON_MUX_CLK_CPUCL0	((void *)(CMU_CPUCL0_BASE + 0x0208))
+#define CLK_CON_DIV_CLK_CPUCL0_1	((void *)(CMU_CPUCL0_BASE + 0x0400))
+#define CLK_CON_DIV_CLK_CPUCL0_2	((void *)(CMU_CPUCL0_BASE + 0x0404))
+#define CLK_CON_DIV_CLK_CPUCL0_ACLK	((void *)(CMU_CPUCL0_BASE + 0x0408))
+#define CLK_CON_DIV_CLK_CPUCL0_PCLK	((void *)(CMU_CPUCL0_BASE + 0x040C))
+#define CLK_CON_DIV_CLK_CPUCL0_ATCLK	((void *)(CMU_CPUCL0_BASE + 0x0410))
+#define CLK_CON_DIV_CLK_CPUCL0_PCLKDBG	((void *)(CMU_CPUCL0_BASE + 0x0414))
+#define CLK_CON_DIV_CLK_CPUCL0_CNTCLK	((void *)(CMU_CPUCL0_BASE + 0x0418))
+#define CLK_CON_DIV_CLK_CPUCL0_RUN_MONITOR	((void *)(CMU_CPUCL0_BASE + 0x041C))
+#define CLK_CON_DIV_CLK_CPUCL0_HPM	((void *)(CMU_CPUCL0_BASE + 0x0420))
+#define CLK_CON_DIV_CLK_CPUCL0_PLL	((void *)(CMU_CPUCL0_BASE + 0x0424))
+#define CLK_STAT_MUX_CPUCL0_PLL	((void *)(CMU_CPUCL0_BASE + 0x0600))
+#define CLK_STAT_MUX_CLKCMU_CPUCL0_SWITCH_USER	((void *)(CMU_CPUCL0_BASE + 0x0604))
+#define CLK_STAT_MUX_CLK_CPUCL0	((void *)(CMU_CPUCL0_BASE + 0x0608))
+#define CLK_ENABLE_CLK_CPUCL0_OSCCLK	((void *)(CMU_CPUCL0_BASE + 0x0800))
+#define CLK_ENABLE_CLK_CPUCL0_ACLK	((void *)(CMU_CPUCL0_BASE + 0x0808))
+#define CLK_ENABLE_CLK_CPUCL0_PCLK	((void *)(CMU_CPUCL0_BASE + 0x080C))
+#define CLK_ENABLE_CLK_CPUCL0_ATCLK	((void *)(CMU_CPUCL0_BASE + 0x0810))
+#define CLK_ENABLE_CLK_CPUCL0_PCLKDBG	((void *)(CMU_CPUCL0_BASE + 0x0814))
+#define CLK_ENABLE_CLK_CPUCL0_HPM	((void *)(CMU_CPUCL0_BASE + 0x0820))
+#define CLKOUT_CMU_CPUCL0	((void *)(CMU_CPUCL0_BASE + 0x0D00))
+#define CLKOUT_CMU_CPUCL0_DIV_STAT	((void *)(CMU_CPUCL0_BASE + 0x0D04))
+#define CMU_CPUCL0_SPARE0	((void *)(CMU_CPUCL0_BASE + 0x0D08))
+#define CMU_CPUCL0_SPARE1	((void *)(CMU_CPUCL0_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_CPUCL0	((void *)(CMU_CPUCL0_BASE + 0x0E00))
+#define CPUCL0_SFR_IGNORE_REQ_SYSCLK	((void *)(CMU_CPUCL0_BASE + 0x0F00))
+#define CPUCL0_ARMCLK_STOPCTRL	((void *)(CMU_CPUCL0_BASE + 0x1000))
+#define CPUCL0_PWR_CTRL	((void *)(CMU_CPUCL0_BASE + 0x1020))
+#define CPUCL0_PWR_CTRL2	((void *)(CMU_CPUCL0_BASE + 0x1024))
+#define CPUCL0_PWR_CTRL3	((void *)(CMU_CPUCL0_BASE + 0x1028))
+#define CPUCL0_INTR_SPREAD_ENABLE	((void *)(CMU_CPUCL0_BASE + 0x1080))
+#define CPUCL0_INTR_SPREAD_USE_STANDBYWFI	((void *)(CMU_CPUCL0_BASE + 0x1084))
+#define CPUCL0_INTR_SPREAD_BLOCKING_DURATION	((void *)(CMU_CPUCL0_BASE + 0x1088))
+
+#define CPUCL1_PLL_LOCK	((void *)(CMU_CPUCL1_BASE + 0x0000))
+#define CPUCL1_PLL_CON0	((void *)(CMU_CPUCL1_BASE + 0x0100))
+#define CPUCL1_PLL_CON1	((void *)(CMU_CPUCL1_BASE + 0x0104))
+#define CLK_CON_MUX_CPUCL1_PLL	((void *)(CMU_CPUCL1_BASE + 0x0200))
+#define CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH_USER	((void *)(CMU_CPUCL1_BASE + 0x0204))
+#define CLK_CON_MUX_CLK_CPUCL1	((void *)(CMU_CPUCL1_BASE + 0x0208))
+#define CLK_CON_DIV_CLK_CPUCL1_1	((void *)(CMU_CPUCL1_BASE + 0x0400))
+#define CLK_CON_DIV_CLK_CPUCL1_2	((void *)(CMU_CPUCL1_BASE + 0x0404))
+#define CLK_CON_DIV_CLK_CPUCL1_ACLK	((void *)(CMU_CPUCL1_BASE + 0x0408))
+#define CLK_CON_DIV_CLK_CPUCL1_PCLK	((void *)(CMU_CPUCL1_BASE + 0x040C))
+#define CLK_CON_DIV_CLK_CPUCL1_ATCLK	((void *)(CMU_CPUCL1_BASE + 0x0410))
+#define CLK_CON_DIV_CLK_CPUCL1_PCLKDBG	((void *)(CMU_CPUCL1_BASE + 0x0414))
+#define CLK_CON_DIV_CLK_CPUCL1_CNTCLK	((void *)(CMU_CPUCL1_BASE + 0x0418))
+#define CLK_CON_DIV_CLK_CPUCL1_RUN_MONITOR	((void *)(CMU_CPUCL1_BASE + 0x041C))
+#define CLK_CON_DIV_CLK_CPUCL1_HPM	((void *)(CMU_CPUCL1_BASE + 0x0420))
+#define CLK_CON_DIV_CLK_CPUCL1_PLL	((void *)(CMU_CPUCL1_BASE + 0x0424))
+#define CLK_STAT_MUX_CPUCL1_PLL	((void *)(CMU_CPUCL1_BASE + 0x0600))
+#define CLK_STAT_MUX_CLKCMU_CPUCL1_SWITCH_USER	((void *)(CMU_CPUCL1_BASE + 0x0604))
+#define CLK_STAT_MUX_CLK_CPUCL1	((void *)(CMU_CPUCL1_BASE + 0x0608))
+#define CLK_ENABLE_CLK_CPUCL1_OSCCLK	((void *)(CMU_CPUCL1_BASE + 0x0800))
+#define CLK_ENABLE_CLK_CPUCL1_ACLK	((void *)(CMU_CPUCL1_BASE + 0x0808))
+#define CLK_ENABLE_CLK_CPUCL1_PCLK	((void *)(CMU_CPUCL1_BASE + 0x080C))
+#define CLK_ENABLE_CLK_CPUCL1_PCLKDBG	((void *)(CMU_CPUCL1_BASE + 0x0814))
+#define CLK_ENABLE_CLK_CPUCL1_HPM	((void *)(CMU_CPUCL1_BASE + 0x0820))
+#define CLKOUT_CMU_CPUCL1	((void *)(CMU_CPUCL1_BASE + 0x0D00))
+#define CLKOUT_CMU_CPUCL1_DIV_STAT	((void *)(CMU_CPUCL1_BASE + 0x0D04))
+#define CMU_CPUCL1_SPARE0	((void *)(CMU_CPUCL1_BASE + 0x0D08))
+#define CMU_CPUCL1_SPARE1	((void *)(CMU_CPUCL1_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_CPUCL1	((void *)(CMU_CPUCL1_BASE + 0x0E00))
+#define CPUCL1_SFR_IGNORE_REQ_SYSCLK	((void *)(CMU_CPUCL1_BASE + 0x0F00))
+#define CPUCL1_ARMCLK_STOPCTRL	((void *)(CMU_CPUCL1_BASE + 0x1000))
+#define CPUCL1_PWR_CTRL	((void *)(CMU_CPUCL1_BASE + 0x1020))
+#define CPUCL1_PWR_CTRL2	((void *)(CMU_CPUCL1_BASE + 0x1024))
+#define CPUCL1_PWR_CTRL3	((void *)(CMU_CPUCL1_BASE + 0x1028))
+#define CPUCL1_INTR_SPREAD_ENABLE	((void *)(CMU_CPUCL1_BASE + 0x1080))
+#define CPUCL1_INTR_SPREAD_USE_STANDBYWFI	((void *)(CMU_CPUCL1_BASE + 0x1084))
+#define CPUCL1_INTR_SPREAD_BLOCKING_DURATION	((void *)(CMU_CPUCL1_BASE + 0x1088))
+
+#define G3D_PLL_LOCK	((void *)(CMU_G3D_BASE + 0x0000))
+#define G3D_PLL_CON0	((void *)(CMU_G3D_BASE + 0x0100))
+#define G3D_PLL_CON1	((void *)(CMU_G3D_BASE + 0x0104))
+#define CLK_CON_MUX_G3D_PLL	((void *)(CMU_G3D_BASE + 0x0200))
+#define CLK_CON_MUX_CLKCMU_G3D_SWITCH_USER	((void *)(CMU_G3D_BASE + 0x0204))
+#define CLK_CON_MUX_CLK_G3D	((void *)(CMU_G3D_BASE + 0x0208))
+#define CLK_CON_DIV_CLK_G3D_BUS	((void *)(CMU_G3D_BASE + 0x0400))
+#define CLK_CON_DIV_CLK_G3D_APB	((void *)(CMU_G3D_BASE + 0x0404))
+#define CLK_STAT_MUX_G3D_PLL	((void *)(CMU_G3D_BASE + 0x0600))
+#define CLK_STAT_MUX_CLKCMU_G3D_SWITCH_USER	((void *)(CMU_G3D_BASE + 0x0604))
+#define CLK_STAT_MUX_CLK_G3D	((void *)(CMU_G3D_BASE + 0x0608))
+#define CLK_ENABLE_CLK_G3D_OSCCLK	((void *)(CMU_G3D_BASE + 0x0800))
+#define CLK_ENABLE_CLK_G3D_BUS	((void *)(CMU_G3D_BASE + 0x0804))
+#define CLK_ENABLE_CLK_G3D_APB	((void *)(CMU_G3D_BASE + 0x0808))
+#define CLK_ENABLE_CLK_G3D_BUS_SECURE_CFW_G3D	((void *)(CMU_G3D_BASE + 0x0810))
+#define CLK_ENABLE_CLK_G3D_APB_SECURE_CFW_G3D	((void *)(CMU_G3D_BASE + 0x0814))
+#define CLKOUT_CMU_G3D	((void *)(CMU_G3D_BASE + 0x0D00))
+#define CLKOUT_CMU_G3D_DIV_STAT	((void *)(CMU_G3D_BASE + 0x0D04))
+#define CMU_G3D_SPARE0	((void *)(CMU_G3D_BASE + 0x0D08))
+#define CMU_G3D_SPARE1	((void *)(CMU_G3D_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_G3D	((void *)(CMU_G3D_BASE + 0x0E00))
+#define G3D_SFR_IGNORE_REQ_SYSCLK	((void *)(CMU_G3D_BASE + 0x0F00))
+#define CLK_STOPCTRL	((void *)(CMU_G3D_BASE + 0x1000))
+
+#define CLK_ENABLE_CLK_PERI_OSCCLK	((void *)(CMU_PERI_BASE + 0x0800))
+#define CLK_ENABLE_CLK_PERI_OSCCLK_SECURE_CHIPID	((void *)(CMU_PERI_BASE + 0x0804))
+#define CLK_ENABLE_CLK_PERI_BUS0	((void *)(CMU_PERI_BASE + 0x0810))
+#define CLK_ENABLE_CLK_PERI_BUS1	((void *)(CMU_PERI_BASE + 0x0814))
+#define CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC	((void *)(CMU_PERI_BASE + 0x0818))
+#define CLK_ENABLE_CLK_PERI_BUS_SECURE_CHIPID	((void *)(CMU_PERI_BASE + 0x081C))
+#define CLK_ENABLE_CLK_PERI_BUS_SECURE_OTP_CON_TOP	((void *)(CMU_PERI_BASE + 0x0820))
+#define CLK_ENABLE_CLK_PERI_BUS_SECURE_RTC_ALIVE	((void *)(CMU_PERI_BASE + 0x0824))
+#define CLK_ENABLE_CLK_PERI_BUS_SECURE_RTC_TOP	((void *)(CMU_PERI_BASE + 0x0828))
+#define CLK_ENABLE_CLK_PERI_UART_BTWIFIFM	((void *)(CMU_PERI_BASE + 0x0830))
+#define CLK_ENABLE_CLK_PERI_UART_DEBUG	((void *)(CMU_PERI_BASE + 0x0834))
+#define CLK_ENABLE_CLK_PERI_UART_SENSOR	((void *)(CMU_PERI_BASE + 0x0838))
+#define CLK_ENABLE_CLK_PERI_SPI_FRONTFROM	((void *)(CMU_PERI_BASE + 0x083C))
+#define CLK_ENABLE_CLK_PERI_SPI_REARFROM	((void *)(CMU_PERI_BASE + 0x0840))
+#define CLK_ENABLE_CLK_PERI_SPI_ESE	((void *)(CMU_PERI_BASE + 0x0844))
+#define CLK_ENABLE_CLK_PERI_SPI_VOICEPROCESSOR	((void *)(CMU_PERI_BASE + 0x0848))
+#define CLK_ENABLE_CLK_PERI_SPI_SENSORHUB	((void *)(CMU_PERI_BASE + 0x084C))
+#define CLKOUT_CMU_PERI	((void *)(CMU_PERI_BASE + 0x0D00))
+#define CLKOUT_CMU_PERI_DIV_STAT	((void *)(CMU_PERI_BASE + 0x0D04))
+#define CMU_PERI_SPARE0	((void *)(CMU_PERI_BASE + 0x0D08))
+#define CMU_PERI_SPARE1	((void *)(CMU_PERI_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_PERI	((void *)(CMU_PERI_BASE + 0x0E00))
+
+#define USB_PLL_LOCK	((void *)(CMU_FSYS_BASE + 0x0000))
+#define USB_PLL_CON0	((void *)(CMU_FSYS_BASE + 0x0100))
+#define USB_PLL_CON1	((void *)(CMU_FSYS_BASE + 0x0104))
+#define CLK_CON_MUX_USB_PLL	((void *)(CMU_FSYS_BASE + 0x0200))
+#define CLK_CON_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER	((void *)(CMU_FSYS_BASE + 0x0230))
+#define CLK_CON_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER	((void *)(CMU_FSYS_BASE + 0x0234))
+#define CLK_CON_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER	((void *)(CMU_FSYS_BASE + 0x0238))
+#define CLK_STAT_MUX_USB_PLL	((void *)(CMU_FSYS_BASE + 0x0600))
+#define CLK_STAT_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER	((void *)(CMU_FSYS_BASE + 0x0630))
+#define CLK_STAT_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER	((void *)(CMU_FSYS_BASE + 0x0634))
+#define CLK_STAT_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER	((void *)(CMU_FSYS_BASE + 0x0638))
+#define CLK_ENABLE_CLK_FSYS_OSCCLK	((void *)(CMU_FSYS_BASE + 0x0800))
+#define CLK_ENABLE_CLK_FSYS_BUS	((void *)(CMU_FSYS_BASE + 0x0804))
+#define CLK_ENABLE_CLK_FSYS_SECURE_RTIC	((void *)(CMU_FSYS_BASE + 0x0808))
+#define CLK_ENABLE_CLK_FSYS_SECURE_SSS	((void *)(CMU_FSYS_BASE + 0x080C))
+#define CLK_ENABLE_CLK_FSYS_SECURE_PDMA1	((void *)(CMU_FSYS_BASE + 0x0810))
+#define CLK_ENABLE_CLK_FSYS_MMC0	((void *)(CMU_FSYS_BASE + 0x0814))
+#define CLK_ENABLE_CLK_FSYS_MMC1	((void *)(CMU_FSYS_BASE + 0x0818))
+#define CLK_ENABLE_CLK_FSYS_MMC2	((void *)(CMU_FSYS_BASE + 0x081C))
+#define CLK_ENABLE_CLK_FSYS_UFSUNIPRO	((void *)(CMU_FSYS_BASE + 0x0820))
+#define CLK_ENABLE_CLK_FSYS_UFSUNIPRO_CFG	((void *)(CMU_FSYS_BASE + 0x0824))
+#define CLK_ENABLE_CLK_FSYS_USB20DRD_REFCLK	((void *)(CMU_FSYS_BASE + 0x0828))
+#define CLK_ENABLE_CLKPHY_FSYS_USB20DRD_PHYCLOCK	((void *)(CMU_FSYS_BASE + 0x0830))
+#define CLK_ENABLE_CLKPHY_FSYS_UFS_TX0_SYMBOL	((void *)(CMU_FSYS_BASE + 0x0834))
+#define CLK_ENABLE_CLKPHY_FSYS_UFS_RX0_SYMBOL	((void *)(CMU_FSYS_BASE + 0x0838))
+#define SECURE_ENABLE_BUSD0_FSYS	((void *)(CMU_FSYS_BASE + 0x08D0))
+#define CLKOUT_CMU_FSYS	((void *)(CMU_FSYS_BASE + 0x0D00))
+#define CLKOUT_CMU_FSYS_DIV_STAT	((void *)(CMU_FSYS_BASE + 0x0D04))
+#define CMU_FSYS_SPARE0	((void *)(CMU_FSYS_BASE + 0x0D08))
+#define CMU_FSYS_SPARE1	((void *)(CMU_FSYS_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_FSYS	((void *)(CMU_FSYS_BASE + 0x0E00))
+#define FSYS_SFR_IGNORE_REQ_SYSCLK	((void *)(CMU_FSYS_BASE + 0x0F00))
+
+#define CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL_USER	((void *)(CMU_MFCMSCL_BASE + 0x0200))
+#define CLK_CON_MUX_CLKCMU_MFCMSCL_MFC_USER	((void *)(CMU_MFCMSCL_BASE + 0x0204))
+#define CLK_CON_DIV_CLK_MFCMSCL_APB	((void *)(CMU_MFCMSCL_BASE + 0x0400))
+#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MSCL_USER	((void *)(CMU_MFCMSCL_BASE + 0x0600))
+#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MFC_USER	((void *)(CMU_MFCMSCL_BASE + 0x0604))
+#define CLK_ENABLE_CLK_MFCMSCL_OSCCLK	((void *)(CMU_MFCMSCL_BASE + 0x0800))
+#define CLK_ENABLE_CLK_MFCMSCL_MSCL	((void *)(CMU_MFCMSCL_BASE + 0x0804))
+#define CLK_ENABLE_CLK_MFCMSCL_MFC	((void *)(CMU_MFCMSCL_BASE + 0x0808))
+#define CLK_ENABLE_CLK_MFCMSCL_APB	((void *)(CMU_MFCMSCL_BASE + 0x080C))
+#define CLK_ENABLE_CLK_MFCMSCL_SECURE_CFW_MSCL	((void *)(CMU_MFCMSCL_BASE + 0x0810))
+#define CLKOUT_CMU_MFCMSCL	((void *)(CMU_MFCMSCL_BASE + 0x0D00))
+#define CLKOUT_CMU_MFCMSCL_DIV_STAT	((void *)(CMU_MFCMSCL_BASE + 0x0D04))
+#define CMU_MFCMSCL_SPARE0	((void *)(CMU_MFCMSCL_BASE + 0x0D08))
+#define CMU_MFCMSCL_SPARE1	((void *)(CMU_MFCMSCL_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_MFCMSCL	((void *)(CMU_MFCMSCL_BASE + 0x0E00))
+#define MFCMSCL_SFR_IGNORE_REQ_SYSCLK	((void *)(CMU_MFCMSCL_BASE + 0x0F00))
+
+#define DISP_PLL_LOCK	((void *)(CMU_DISPAUD_BASE + 0x0000))
+#define AUD_PLL_LOCK	((void *)(CMU_DISPAUD_BASE + 0x00C0))
+#define DISP_PLL_CON0	((void *)(CMU_DISPAUD_BASE + 0x0100))
+#define DISP_PLL_CON1	((void *)(CMU_DISPAUD_BASE + 0x0104))
+#define AUD_PLL_CON0	((void *)(CMU_DISPAUD_BASE + 0x01C0))
+#define AUD_PLL_CON1	((void *)(CMU_DISPAUD_BASE + 0x01C4))
+#define AUD_PLL_CON2	((void *)(CMU_DISPAUD_BASE + 0x01C8))
+#define CLK_CON_MUX_DISP_PLL	((void *)(CMU_DISPAUD_BASE + 0x0200))
+#define CLK_CON_MUX_AUD_PLL	((void *)(CMU_DISPAUD_BASE + 0x0204))
+#define CLK_CON_MUX_CLKCMU_DISPAUD_BUS_USER	((void *)(CMU_DISPAUD_BASE + 0x0210))
+#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER	((void *)(CMU_DISPAUD_BASE + 0x0214))
+#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER	((void *)(CMU_DISPAUD_BASE + 0x0218))
+#define CLK_CON_MUX_CLK_DISPAUD_DECON_INT_VCLK	((void *)(CMU_DISPAUD_BASE + 0x021C))
+#define CLK_CON_MUX_CLK_DISPAUD_DECON_INT_ECLK	((void *)(CMU_DISPAUD_BASE + 0x0220))
+#define CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER	((void *)(CMU_DISPAUD_BASE + 0x0224))
+#define CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER	((void *)(CMU_DISPAUD_BASE + 0x0228))
+#define CLK_CON_MUX_CLK_DISPAUD_MI2S	((void *)(CMU_DISPAUD_BASE + 0x022C))
+#define CLK_CON_DIV_CLK_DISPAUD_APB	((void *)(CMU_DISPAUD_BASE + 0x0400))
+#define CLK_CON_DIV_CLK_DISPAUD_DECON_INT_VCLK	((void *)(CMU_DISPAUD_BASE + 0x0404))
+#define CLK_CON_DIV_CLK_DISPAUD_DECON_INT_ECLK	((void *)(CMU_DISPAUD_BASE + 0x0408))
+#define CLK_CON_DIV_CLK_DISPAUD_MI2S	((void *)(CMU_DISPAUD_BASE + 0x040C))
+#define CLK_CON_DIV_CLK_DISPAUD_MIXER	((void *)(CMU_DISPAUD_BASE + 0x0410))
+#define CLK_STAT_MUX_DISP_PLL	((void *)(CMU_DISPAUD_BASE + 0x0600))
+#define CLK_STAT_MUX_AUD_PLL	((void *)(CMU_DISPAUD_BASE + 0x0604))
+#define CLK_STAT_MUX_CLKCMU_DISPAUD_BUS_USER	((void *)(CMU_DISPAUD_BASE + 0x0610))
+#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER	((void *)(CMU_DISPAUD_BASE + 0x0614))
+#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER	((void *)(CMU_DISPAUD_BASE + 0x0618))
+#define CLK_STAT_MUX_CLK_DISPAUD_DECON_INT_VCLK	((void *)(CMU_DISPAUD_BASE + 0x061C))
+#define CLK_STAT_MUX_CLK_DISPAUD_DECON_INT_ECLK	((void *)(CMU_DISPAUD_BASE + 0x0620))
+#define CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER	((void *)(CMU_DISPAUD_BASE + 0x0624))
+#define CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER	((void *)(CMU_DISPAUD_BASE + 0x0628))
+#define CLK_ENABLE_CLK_DISPAUD_OSCCLK	((void *)(CMU_DISPAUD_BASE + 0x0800))
+#define CLK_ENABLE_CLK_DISPAUD_BUS	((void *)(CMU_DISPAUD_BASE + 0x0810))
+#define CLK_ENABLE_CLK_DISPAUD_APB	((void *)(CMU_DISPAUD_BASE + 0x0814))
+#define CLK_ENABLE_CLK_DISPAUD_SECURE_CFW_DISP	((void *)(CMU_DISPAUD_BASE + 0x0818))
+#define CLK_ENABLE_CLK_DISPAUD_DECON_INT_VCLK	((void *)(CMU_DISPAUD_BASE + 0x081C))
+#define CLK_ENABLE_CLK_DISPAUD_DECON_INT_ECLK	((void *)(CMU_DISPAUD_BASE + 0x0820))
+#define CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS	((void *)(CMU_DISPAUD_BASE + 0x0824))
+#define CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0	((void *)(CMU_DISPAUD_BASE + 0x0828))
+#define CLK_ENABLE_CLK_DISPAUD_MI2S	((void *)(CMU_DISPAUD_BASE + 0x082C))
+#define CLK_ENABLE_CLK_DISPAUD_MIXER	((void *)(CMU_DISPAUD_BASE + 0x0830))
+#define CLK_ENABLE_CLKIO_DISPAUD_MIXER_SCLK_AP	((void *)(CMU_DISPAUD_BASE + 0x0834))
+#define CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_BT	((void *)(CMU_DISPAUD_BASE + 0x0838))
+#define CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_CP	((void *)(CMU_DISPAUD_BASE + 0x083C))
+#define CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_FM	((void *)(CMU_DISPAUD_BASE + 0x0840))
+#define CLKOUT_CMU_DISPAUD	((void *)(CMU_DISPAUD_BASE + 0x0D00))
+#define CLKOUT_CMU_DISPAUD_DIV_STAT	((void *)(CMU_DISPAUD_BASE + 0x0D04))
+#define CMU_DISPAUD_SPARE0	((void *)(CMU_DISPAUD_BASE + 0x0D08))
+#define CMU_DISPAUD_SPARE1	((void *)(CMU_DISPAUD_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_DISPAUD	((void *)(CMU_DISPAUD_BASE + 0x0E00))
+#define DISPAUD_SFR_IGNORE_REQ_SYSCLK	((void *)(CMU_DISPAUD_BASE + 0x0F00))
+
+#define ISP_PLL_LOCK	((void *)(CMU_ISP_BASE + 0x0000))
+#define ISP_PLL_CON0	((void *)(CMU_ISP_BASE + 0x0100))
+#define ISP_PLL_CON1	((void *)(CMU_ISP_BASE + 0x0104))
+#define CLK_CON_MUX_ISP_PLL	((void *)(CMU_ISP_BASE + 0x0200))
+#define CLK_CON_MUX_CLKCMU_ISP_VRA_USER	((void *)(CMU_ISP_BASE + 0x0210))
+#define CLK_CON_MUX_CLKCMU_ISP_CAM_USER	((void *)(CMU_ISP_BASE + 0x0214))
+#define CLK_CON_MUX_CLKCMU_ISP_ISP_USER	((void *)(CMU_ISP_BASE + 0x0218))
+#define CLK_CON_MUX_CLK_ISP_VRA	((void *)(CMU_ISP_BASE + 0x0220))
+#define CLK_CON_MUX_CLK_ISP_CAM	((void *)(CMU_ISP_BASE + 0x0224))
+#define CLK_CON_MUX_CLK_ISP_ISP	((void *)(CMU_ISP_BASE + 0x0228))
+#define CLK_CON_MUX_CLK_ISP_ISPD	((void *)(CMU_ISP_BASE + 0x022C))
+#define CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER	((void *)(CMU_ISP_BASE + 0x0230))
+#define CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER	((void *)(CMU_ISP_BASE + 0x0234))
+#define CLK_CON_DIV_CLK_ISP_APB	((void *)(CMU_ISP_BASE + 0x0400))
+#define CLK_CON_DIV_CLK_ISP_CAM_HALF	((void *)(CMU_ISP_BASE + 0x0404))
+#define CLK_STAT_MUX_ISP_PLL	((void *)(CMU_ISP_BASE + 0x0600))
+#define CLK_STAT_MUX_CLKCMU_ISP_VRA_USER	((void *)(CMU_ISP_BASE + 0x0610))
+#define CLK_STAT_MUX_CLKCMU_ISP_CAM_USER	((void *)(CMU_ISP_BASE + 0x0614))
+#define CLK_STAT_MUX_CLKCMU_ISP_ISP_USER	((void *)(CMU_ISP_BASE + 0x0618))
+#define CLK_STAT_MUX_CLK_ISP_VRA	((void *)(CMU_ISP_BASE + 0x0620))
+#define CLK_STAT_MUX_CLK_ISP_ISP	((void *)(CMU_ISP_BASE + 0x0624))
+#define CLK_STAT_MUX_CLK_ISP_CAM	((void *)(CMU_ISP_BASE + 0x0628))
+#define CLK_STAT_MUX_CLK_ISP_ISPD	((void *)(CMU_ISP_BASE + 0x062C))
+#define CLK_STAT_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER	((void *)(CMU_ISP_BASE + 0x0630))
+#define CLK_STAT_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER	((void *)(CMU_ISP_BASE + 0x0634))
+#define CLK_ENABLE_CLK_ISP_OSCCLK	((void *)(CMU_ISP_BASE + 0x0800))
+#define CLK_ENABLE_CLK_ISP_VRA	((void *)(CMU_ISP_BASE + 0x0810))
+#define CLK_ENABLE_CLK_ISP_APB	((void *)(CMU_ISP_BASE + 0x0814))
+#define CLK_ENABLE_CLK_ISP_ISPD	((void *)(CMU_ISP_BASE + 0x0818))
+#define CLK_ENABLE_CLK_ISP_CAM	((void *)(CMU_ISP_BASE + 0x081C))
+#define CLK_ENABLE_CLK_ISP_CAM_HALF	((void *)(CMU_ISP_BASE + 0x0820))
+#define CLK_ENABLE_CLK_ISP_ISP	((void *)(CMU_ISP_BASE + 0x0824))
+#define CLK_ENABLE_CLKPHY_ISP_S_RXBYTECLKHS0_S4	((void *)(CMU_ISP_BASE + 0x0828))
+#define CLK_ENABLE_CLKPHY_ISP_S_RXBYTECLKHS0_S4S	((void *)(CMU_ISP_BASE + 0x082C))
+#define CLKOUT_CMU_ISP	((void *)(CMU_ISP_BASE + 0x0D00))
+#define CLKOUT_CMU_ISP_DIV_STAT	((void *)(CMU_ISP_BASE + 0x0D04))
+#define CMU_ISP_SPARE0	((void *)(CMU_ISP_BASE + 0x0D08))
+#define CMU_ISP_SPARE1	((void *)(CMU_ISP_BASE + 0x0D0C))
+#define CLK_ENABLE_PDN_ISP	((void *)(CMU_ISP_BASE + 0x0E00))
+#define ISP_SFR_IGNORE_REQ_SYSCLK	((void *)(CMU_ISP_BASE + 0x0F00))
+
+#define CPUCL0_EMA_CON	((void *)(SYSREG_CPUCL0_BASE + 0x0330))
+#define CPUCL1_EMA_CON	((void *)(SYSREG_CPUCL1_BASE + 0x0330))
+#define G3D_EMA_RA1_HS_CON	((void *)(SYSREG_G3D_BASE + 0x0304))
+#define G3D_EMA_RF1_HS_CON	((void *)(SYSREG_G3D_BASE + 0x0314))
+#define G3D_EMA_RF2_HS_CON	((void *)(SYSREG_G3D_BASE + 0x031C))
+
+#endif

drivers/soc/samsung/pwrcal/S5E7870/S5E7870-dfs.c

@@ -0,0 +1,564 @@
+#include "../pwrcal.h"
+#include "../pwrcal-env.h"
+#include "../pwrcal-clk.h"
+#include "../pwrcal-pmu.h"
+#include "../pwrcal-dfs.h"
+#include "../pwrcal-rae.h"
+#include "../pwrcal-asv.h"
+#include "S5E7870-cmusfr.h"
+#include "S5E7870-pmusfr.h"
+#include "S5E7870-cmu.h"
+#include "S5E7870-vclk-internal.h"
+
+#ifdef PWRCAL_TARGET_LINUX
+#include <soc/samsung/ect_parser.h>
+#else
+#include <mach/ect_parser.h>
+#endif
+
+static struct dfs_switch dfscpucl0_switches[] = {
+	{ 800000,	0,	0	},
+	{ 400000,	0,	1	},
+	{ 266000,	0,	2	},
+	{ 200000,	0,	3	},
+};
+
+static struct dfs_table dfscpucl0_table = {
+	.switches = dfscpucl0_switches,
+	.num_of_switches = ARRAY_SIZE(dfscpucl0_switches),
+	.switch_mux = CLK(CPUCL0_MUX_CLK_CPUCL0),
+	.switch_use = 1,
+	.switch_notuse = 0,
+	.switch_src_div = CLK(MIF_DIV_CLKCMU_CPUCL0_SWITCH),
+	.switch_src_gate = CLK(MIF_GATE_CLKCMU_CPUCL0_SWITCH),
+	.switch_src_usermux = CLK(CPUCL0_MUX_CLKCMU_CPUCL0_SWITCH_USER),
+};
+
+struct pwrcal_clk_set dfscpucl0_en_list[] = {
+	{CLK_NONE,	0,	-1},
+};
+
+static struct dfs_switch dfscpucl1_switches[] = {
+	{ 800000,	0,	0	},
+	{ 400000,	0,	1	},
+	{ 266000,	0,	2	},
+	{ 200000,	0,	3	},
+};
+
+static struct dfs_table dfscpucl1_table = {
+	.switches = dfscpucl1_switches,
+	.num_of_switches = ARRAY_SIZE(dfscpucl1_switches),
+	.switch_mux = CLK(CPUCL1_MUX_CLK_CPUCL1),
+	.switch_use = 1,
+	.switch_notuse = 0,
+	.switch_src_div = CLK(MIF_DIV_CLKCMU_CPUCL1_SWITCH),
+	.switch_src_gate = CLK(MIF_GATE_CLKCMU_CPUCL1_SWITCH),
+	.switch_src_usermux = CLK(CPUCL1_MUX_CLKCMU_CPUCL1_SWITCH_USER),
+};
+
+struct pwrcal_clk_set dfscpucl1_en_list[] = {
+	{CLK_NONE,	0,	-1},
+};
+
+static struct dfs_switch dfsg3d_switches[] = {
+	{ 800000,	0,	0	},
+	{ 400000,	0,	1	},
+	{ 266000,	0,	2	},
+	{ 200000,	0,	3	},
+};
+
+static struct dfs_table dfsg3d_table = {
+	.switches = dfsg3d_switches,
+	.num_of_switches = ARRAY_SIZE(dfsg3d_switches),
+	.switch_mux = CLK(G3D_MUX_CLK_G3D),
+	.switch_use = 1,
+	.switch_notuse = 0,
+	.switch_src_div = CLK(MIF_DIV_CLKCMU_G3D_SWITCH),
+	.switch_src_gate = CLK(MIF_GATE_CLKCMU_G3D_SWITCH),
+	.switch_src_usermux = CLK(G3D_MUX_CLKCMU_G3D_SWITCH_USER),
+};
+
+struct pwrcal_clk_set dfsg3d_en_list[] = {
+	{CLK_NONE,	0,	-1},
+};
+
+extern void pwrcal_dmc_set_dvfs(unsigned long long target_mif_freq, unsigned int timing_set_idx);
+extern void pwrcal_dmc_set_pre_dvfs(void);
+extern void pwrcal_dmc_set_post_dvfs(unsigned long long target_freq);
+extern void pwrcal_dmc_set_vtmon_on_swithing(void);
+extern void pwrcal_dmc_set_refresh_method_pre_dvfs(unsigned long long current_rate, unsigned long long target_rate);
+extern void pwrcal_dmc_set_refresh_method_post_dvfs(unsigned long long current_rate, unsigned long long target_rate);
+extern void pwrcal_dmc_set_dsref_cycle(unsigned long long target_rate);
+
+static int pwrcal_clk_set_mif_pause_enable(int enable)
+{
+	pwrcal_writel(PAUSE, (enable<<0)); /* CMU Pause enable */
+	return 0;
+}
+
+static int pwrcal_clk_wait_mif_pause(void)
+{
+	int timeout;
+	unsigned int status;
+
+	for (timeout = 0;; timeout++) {
+		status = pwrcal_getf(PAUSE, 16, 0x3);
+		if (status == 0x0)
+			break;
+
+		if (timeout > CLK_WAIT_CNT)
+			pr_err("PAUSE staus(0x%X) is not stable", status);
+
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+static int is_dll_on_status = 1;
+
+static void dfsmif_trans_pre(unsigned int rate_from, unsigned int rate_to)
+{
+	unsigned long long from, to;
+
+	is_dll_on_status = 1;
+
+	from = (unsigned long long)rate_from * 1000;
+	to = (unsigned long long)rate_to * 1000;
+
+	pwrcal_dmc_set_refresh_method_pre_dvfs(from, to);
+	pwrcal_clk_set_mif_pause_enable(1);
+
+	/* VTMON disable before MIF DFS sequence*/
+	pwrcal_dmc_set_pre_dvfs();
+}
+
+static void dfsmif_trans_post(unsigned int rate_from, unsigned int rate_to)
+{
+	unsigned long long from, to;
+
+	from = (unsigned long long)rate_from * 1000;
+	to = (unsigned long long)rate_to * 1000;
+
+	/* VTMON enable before MIF DFS sequence*/
+	pwrcal_dmc_set_post_dvfs(to);
+
+	pwrcal_dmc_set_refresh_method_post_dvfs(from, to);
+	pwrcal_dmc_set_dsref_cycle(to);
+
+	if (rate_to >= 416000)
+		is_dll_on_status = 1;
+	else
+		is_dll_on_status = 0;
+}
+
+static void dfsmif_switch_pre(unsigned int rate_from, unsigned int rate_to)
+{
+	static unsigned int paraset;
+	unsigned long long rate;
+
+	paraset = (paraset + 1) % 2;
+	rate = (unsigned long long)rate_to * 1000;
+	pwrcal_dmc_set_dvfs(rate, paraset);
+}
+
+static void dfsmif_switch_post(unsigned int rate_from, unsigned int rate_to)
+{
+	pwrcal_clk_wait_mif_pause();
+}
+
+static unsigned int cur_rate_switch;
+static int dfsmif_transition_switch(unsigned int rate_from, unsigned int rate_switch, struct dfs_table *table)
+{
+	int lv_from, lv_switch;
+
+	lv_from = dfs_get_lv(rate_from, table);
+
+	if (lv_from >= table->num_of_lv)
+		goto errorout;
+
+	lv_switch = dfs_get_lv(rate_switch, table);
+
+	dfsmif_trans_pre(rate_from, rate_switch);
+
+	if (dfs_trans_div(lv_from, lv_switch, table, TRANS_HIGH)) /* switching div setting */
+		goto errorout;
+
+	if (dfs_trans_mux(lv_from, lv_switch, table, TRANS_DIFF)) /* switching mux setting */
+		goto errorout;
+
+	dfsmif_switch_pre(rate_from, rate_switch); /* timing parameter setting for switching frequency */
+
+	if (dfs_use_switch(table))
+		goto errorout;
+
+	dfsmif_switch_post(rate_from, rate_switch); /* Switching mux setting */
+
+	if (dfs_trans_div(lv_from, lv_switch, table, TRANS_LOW)) /* waiting for idle status of pause */
+		goto errorout;
+
+	cur_rate_switch = rate_switch;
+
+	return 0;
+
+errorout:
+	return -1;
+}
+
+static int dfsmif_transition(unsigned int rate_switch, unsigned int rate_to, struct dfs_table *table)
+{
+	int lv_to, lv_switch;
+
+	lv_to = dfs_get_lv(rate_to, table);
+
+	if (lv_to >= table->num_of_lv)
+		goto errorout;
+
+	lv_switch = dfs_get_lv(cur_rate_switch, table);
+
+	if (dfs_trans_pll(lv_switch, lv_to, table, TRANS_FORCE))
+		goto errorout;
+
+	if (dfs_trans_div(lv_switch, lv_to, table, TRANS_HIGH))
+		goto errorout;
+	if (dfs_trans_mux(lv_switch, lv_to, table, TRANS_DIFF))
+		goto errorout;
+
+	dfsmif_switch_pre(rate_switch, rate_to);
+	if (dfs_not_use_switch(table))
+		goto errorout;
+	dfsmif_switch_post(rate_switch, rate_to);
+
+	if (dfs_trans_div(lv_switch, lv_to, table, TRANS_LOW))
+		goto errorout;
+
+	dfsmif_trans_post(lv_switch, rate_to);
+
+	return 0;
+
+errorout:
+	return -1;
+}
+
+static struct dfs_switch dfsmif_switches[] = {
+	{	1334000,	0,	0	},
+};
+
+static struct dfs_table dfsmif_table = {
+	.switches = dfsmif_switches,
+	.num_of_switches = ARRAY_SIZE(dfsmif_switches),
+	.switch_mux = CLK(MIF_MUX_CLK_MIF_PHY_CLK2X),
+	.switch_use = 1,
+	.switch_notuse = 0,
+	.private_trans = dfsmif_transition,
+	.private_switch = dfsmif_transition_switch,
+};
+
+struct pwrcal_clk_set dfsmif_en_list[] = {
+	{	CLK_NONE,	0,	-1},
+};
+
+static struct dfs_switch dfsint_switches[] = {
+};
+
+static struct dfs_table dfsint_table = {
+	.switches = dfsint_switches,
+	.num_of_switches = ARRAY_SIZE(dfsint_switches),
+	.switch_use = 1,
+	.switch_notuse = 0,
+};
+
+struct pwrcal_clk_set dfsint_en_list[] = {
+	{CLK_NONE,	0,	-1},
+};
+
+static struct dfs_switch dfsdisp_switches[] = {
+};
+
+static struct dfs_table dfsdisp_table = {
+	.switches = dfsdisp_switches,
+	.num_of_switches = ARRAY_SIZE(dfsdisp_switches),
+	.switch_use = 1,
+	.switch_notuse = 0,
+};
+
+struct pwrcal_clk_set dfsdisp_en_list[] = {
+	{CLK_NONE,	0,	-1},
+};
+
+static struct dfs_switch dfscam_switches[] = {
+};
+
+static struct dfs_table dfscam_table = {
+	.switches = dfscam_switches,
+	.num_of_switches = ARRAY_SIZE(dfscam_switches),
+	.switch_use = 1,
+	.switch_notuse = 0,
+};
+
+struct pwrcal_clk_set dfscam_en_list[] = {
+	{CLK_NONE,	0,	-1},
+};
+
+static int dfscpucl0_init_smpl(void)
+{
+	return 0;
+}
+
+static int dfscpucl0_set_smpl(void)
+{
+	return 0;
+}
+
+static int dfscpucl0_get_smpl(void)
+{
+	return 0;
+}
+
+static int dfscpucl0_get_rate_table(unsigned long *table)
+{
+	return dfs_get_rate_table(&dfscpucl1_table, table);
+}
+
+static int dfscpucl0_idle_clock_down(unsigned int enable)
+{
+	return 0;
+}
+static struct vclk_dfs_ops dfscpucl0_dfsops = {
+	.init_smpl = dfscpucl0_init_smpl,
+	.set_smpl = dfscpucl0_set_smpl,
+	.get_smpl = dfscpucl0_get_smpl,
+	.get_rate_table = dfscpucl0_get_rate_table,
+	.cpu_idle_clock_down = dfscpucl0_idle_clock_down,
+};
+
+static int dfscpucl1_get_rate_table(unsigned long *table)
+{
+	return dfs_get_rate_table(&dfscpucl1_table, table);
+}
+
+static int dfscpucl1_idle_clock_down(unsigned int enable)
+{
+	return 0;
+}
+
+static struct vclk_dfs_ops dfscpucl1_dfsops = {
+	.get_rate_table = dfscpucl1_get_rate_table,
+	.cpu_idle_clock_down = dfscpucl1_idle_clock_down,
+};
+
+static int dfsg3d_dvs(int on)
+{
+	return 0;
+}
+
+static int dfsg3d_get_rate_table(unsigned long *table)
+{
+	return dfs_get_rate_table(&dfsg3d_table, table);
+}
+
+static struct vclk_dfs_ops dfsg3d_dfsops = {
+	.dvs = dfsg3d_dvs,
+	.get_rate_table = dfsg3d_get_rate_table,
+};
+
+static int dfsmif_get_rate_table(unsigned long *table)
+{
+	return dfs_get_rate_table(&dfsmif_table, table);
+}
+
+static int dfsmif_is_dll_on(void)
+{
+	return 1;
+}
+
+static struct vclk_dfs_ops dfsmif_dfsops = {
+	.get_rate_table = dfsmif_get_rate_table,
+	.is_dll_on = dfsmif_is_dll_on,
+};
+
+static int dfsint_get_rate_table(unsigned long *table)
+{
+	return dfs_get_rate_table(&dfsint_table, table);
+}
+
+static struct vclk_dfs_ops dfsint_dfsops = {
+	.get_rate_table = dfsint_get_rate_table,
+};
+
+static int dfsdisp_get_rate_table(unsigned long *table)
+{
+	return dfs_get_rate_table(&dfsdisp_table, table);
+}
+
+static struct vclk_dfs_ops dfsdisp_dfsops = {
+	.get_rate_table = dfsdisp_get_rate_table,
+};
+
+static int dfscam_get_rate_table(unsigned long *table)
+{
+	return dfs_get_rate_table(&dfscam_table, table);
+}
+
+static struct vclk_dfs_ops dfscam_dfsops = {
+	.get_rate_table = dfscam_get_rate_table,
+};
+
+
+static DEFINE_SPINLOCK(dvfs_cpucl0_lock);
+static DEFINE_SPINLOCK(dvfs_cpucl1_lock);
+static DEFINE_SPINLOCK(dvfs_g3d_lock);
+static DEFINE_SPINLOCK(dvfs_mif_lock);
+static DEFINE_SPINLOCK(dvfs_int_lock);
+static DEFINE_SPINLOCK(dvfs_disp_lock);
+static DEFINE_SPINLOCK(dvfs_cam_lock);
+
+DFS(dvfs_cpucl0) = {
+	.vclk.type	= vclk_group_dfs,
+	.vclk.parent	= VCLK(pxmxdx_top),
+	.vclk.ref_count	= 1,
+	.vclk.vfreq	= 0,
+	.vclk.name	= "dvfs_cpucl0",
+	.vclk.ops	= &dfs_ops,
+	.lock		= &dvfs_cpucl0_lock,
+	.en_clks	= dfscpucl0_en_list,
+	.table		= &dfscpucl0_table,
+	.dfsops		= &dfscpucl0_dfsops,
+};
+
+DFS(dvfs_cpucl1) = {
+	.vclk.type	= vclk_group_dfs,
+	.vclk.parent	= VCLK(pxmxdx_top),
+	.vclk.ref_count	= 1,
+	.vclk.vfreq	= 0,
+	.vclk.name	= "dvfs_cpucl1",
+	.vclk.ops	= &dfs_ops,
+	.lock		= &dvfs_cpucl1_lock,
+	.en_clks	= dfscpucl1_en_list,
+	.table		= &dfscpucl1_table,
+	.dfsops		= &dfscpucl1_dfsops,
+};
+
+DFS(dvfs_g3d) = {
+	.vclk.type	= vclk_group_dfs,
+	.vclk.parent	= VCLK(pxmxdx_top),
+	.vclk.ref_count	= 0,
+	.vclk.vfreq	= 350000,
+	.vclk.name	= "dvfs_g3d",
+	.vclk.ops	= &dfs_ops,
+	.lock		= &dvfs_g3d_lock,
+	.en_clks	= dfsg3d_en_list,
+	.table		= &dfsg3d_table,
+	.dfsops		= &dfsg3d_dfsops,
+};
+
+DFS(dvfs_mif) = {
+	.vclk.type	= vclk_group_dfs,
+	.vclk.parent	= VCLK(pxmxdx_top),
+	.vclk.ref_count	= 1,
+	.vclk.vfreq	= 0,
+	.vclk.name	= "dvfs_mif",
+	.vclk.ops	= &dfs_ops,
+	.lock		= &dvfs_mif_lock,
+	.en_clks	= dfsmif_en_list,
+	.table		= &dfsmif_table,
+	.dfsops		= &dfsmif_dfsops,
+};
+
+DFS(dvfs_int) = {
+	.vclk.type	= vclk_group_dfs,
+	.vclk.parent	= VCLK(pxmxdx_top),
+	.vclk.ref_count	= 1,
+	.vclk.vfreq	= 0,
+	.vclk.name	= "dvfs_int",
+	.vclk.ops	= &dfs_ops,
+	.lock		= &dvfs_int_lock,
+	.en_clks	= dfsint_en_list,
+	.table		= &dfsint_table,
+	.dfsops		= &dfsint_dfsops,
+};
+
+DFS(dvfs_disp) = {
+	.vclk.type	= vclk_group_dfs,
+	.vclk.parent	= VCLK(pxmxdx_top),
+	.vclk.ref_count	= 0,
+	.vclk.vfreq	= 0,
+	.vclk.name	= "dvfs_disp",
+	.vclk.ops	= &dfs_ops,
+	.lock		= &dvfs_disp_lock,
+	.en_clks	= dfsdisp_en_list,
+	.table		= &dfsdisp_table,
+	.dfsops		= &dfsdisp_dfsops,
+};
+
+DFS(dvfs_cam) = {
+	.vclk.type	= vclk_group_dfs,
+	.vclk.parent	= VCLK(pxmxdx_top),
+	.vclk.ref_count	= 0,
+	.vclk.vfreq	= 533000,
+	.vclk.name	= "dvfs_cam",
+	.vclk.ops	= &dfs_ops,
+	.lock		= &dvfs_cam_lock,
+	.en_clks	= dfscam_en_list,
+	.table		= &dfscam_table,
+	.dfsops		= &dfscam_dfsops,
+};
+
+void dfs_set_clk_information(struct pwrcal_vclk_dfs *dfs)
+{
+	int i, j;
+	void *dvfs_block;
+	struct ect_dvfs_domain *dvfs_domain;
+	struct dfs_table *dvfs_table;
+
+	dvfs_block = ect_get_block("DVFS");
+	if (dvfs_block == NULL)
+		return;
+
+	dvfs_domain = ect_dvfs_get_domain(dvfs_block, dfs->vclk.name);
+	if (dvfs_domain == NULL)
+		return;
+
+	dvfs_table = dfs->table;
+	dvfs_table->num_of_lv = dvfs_domain->num_of_level;
+	dvfs_table->num_of_members = dvfs_domain->num_of_clock + 1;
+	dvfs_table->max_freq = dvfs_domain->max_frequency;
+	dvfs_table->min_freq = dvfs_domain->min_frequency;
+
+	dvfs_table->members = kzalloc(sizeof(struct pwrcal_clk *) * (dvfs_domain->num_of_clock + 1), GFP_KERNEL);
+	if (dvfs_table->members == NULL)
+		return;
+
+	dvfs_table->members[0] = REPRESENT_RATE;
+	for (i = 0; i < dvfs_domain->num_of_clock; ++i) {
+		dvfs_table->members[i + 1] = clk_find(dvfs_domain->list_clock[i]);
+		if (dvfs_table->members[i] == NULL)
+			return;
+	}
+
+	dvfs_table->rate_table = kzalloc(sizeof(unsigned int) * (dvfs_domain->num_of_clock + 1) * dvfs_domain->num_of_level, GFP_KERNEL);
+	if (dvfs_table->rate_table == NULL)
+		return;
+
+	for (i = 0; i < dvfs_domain->num_of_level; ++i) {
+
+		dvfs_table->rate_table[i * (dvfs_domain->num_of_clock + 1)] = dvfs_domain->list_level[i].level;
+		for (j = 0; j <= dvfs_domain->num_of_clock; ++j) {
+			dvfs_table->rate_table[i * (dvfs_domain->num_of_clock + 1) + j + 1] =
+				dvfs_domain->list_dvfs_value[i * dvfs_domain->num_of_clock + j];
+		}
+	}
+
+}
+void dfs_init(void)
+{
+	dfs_set_clk_information(&vclk_dvfs_cpucl0);
+	dfs_set_clk_information(&vclk_dvfs_cpucl1);
+	dfs_set_clk_information(&vclk_dvfs_g3d);
+	dfs_set_clk_information(&vclk_dvfs_mif);
+	dfs_set_clk_information(&vclk_dvfs_int);
+	dfs_set_clk_information(&vclk_dvfs_cam);
+	dfs_set_clk_information(&vclk_dvfs_disp);
+
+	dfs_dram_init();
+}

drivers/soc/samsung/pwrcal/S5E7870/S5E7870-drampara.c

@@ -0,0 +1,566 @@
+#include "../pwrcal-env.h"
+#include "../pwrcal-rae.h"
+#include "S5E7870-sfrbase.h"
+#include "S5E7870-vclk-internal.h"
+#include "S5E7870-pmusfr.h"
+
+#ifdef PWRCAL_TARGET_LINUX
+#include <soc/samsung/ect_parser.h>
+#else
+#include <mach/ect_parser.h>
+#endif
+
+#ifndef MHZ
+#define MHZ		((unsigned long long)1000000)
+#endif
+
+#define DMC_WAIT_CNT 10000
+
+#if 1 /// joshua¿ëÀ¸·Î ¼öÁ¤ ÇÊ¿ä
+
+#define DREX0_MEMORY_CONTROL0			((void *)(DREX0_BASE + 0x0010))
+#define DREX0_POWER_DOWN_CONFIG			((void *)(DREX0_BASE + 0x0014))
+#define DREX0_CG_CONTROL			((void *)(DREX0_BASE + 0x0018))
+
+#define DREX0_TICK_GRANULARITY_S0		((void *)(DREX0_BASE + 0x0100))
+#define DREX0_TEMP_SENSING_S0					((void *)(DREX0_BASE + 0x0108))
+#define DREX0_DQS_OSC_CON1_S0					((void *)(DREX0_BASE + 0x0110))
+#define DREX0_TERMINATION_CONTROL_S0			((void *)(DREX0_BASE + 0x0114))
+#define DREX0_WINCONFIG_WRITE_ODT_S0			((void *)(DREX0_BASE + 0x0118))
+#define DREX0_TIMING_ROW0_S0		((void *)(DREX0_BASE + 0x0140))
+#define DREX0_TIMING_ROW1_S0		((void *)(DREX0_BASE + 0x0144))
+#define DREX0_TIMING_DATA_ACLK_S0		((void *)(DREX0_BASE + 0x0148))
+#define DREX0_TIMING_DATA_MCLK_S0			((void *)(DREX0_BASE + 0x014C))
+#define DREX0_TIMING_POWER0_S0		((void *)(DREX0_BASE + 0x0150))
+#define DREX0_TIMING_POWER1_S0		((void *)(DREX0_BASE + 0x0154))
+#define DREX0_TIMING_ETC1_S0	((void *)(DREX0_BASE + 0x015c))
+
+#define DREX0_TICK_GRANULARITY_S1		((void *)(DREX0_BASE + 0x0180))
+#define DREX0_TEMP_SENSING_S1					((void *)(DREX0_BASE + 0x0188))
+#define DREX0_DQS_OSC_CON1_S1					((void *)(DREX0_BASE + 0x0190))
+#define DREX0_TERMINATION_CONTROL_S1			((void *)(DREX0_BASE + 0x0194))
+#define DREX0_WINCONFIG_WRITE_ODT_S1			((void *)(DREX0_BASE + 0x0198))
+#define DREX0_TIMING_ROW0_S1		((void *)(DREX0_BASE + 0x01c0))
+#define DREX0_TIMING_ROW1_S1		((void *)(DREX0_BASE + 0x01c4))
+#define DREX0_TIMING_DATA_ACLK_S1		((void *)(DREX0_BASE + 0x01c8))
+#define DREX0_TIMING_DATA_MCLK_S1			((void *)(DREX0_BASE + 0x01cC))
+#define DREX0_TIMING_POWER0_S1		((void *)(DREX0_BASE + 0x01d0))
+#define DREX0_TIMING_POWER1_S1		((void *)(DREX0_BASE + 0x01d4))
+#define DREX0_TIMING_ETC1_S1	((void *)(DREX0_BASE + 0x01dc))
+
+#define PHY0_CAL_CON0		((void *)(DREXPHY0_BASE + 0x0004))
+#define PHY0_DVFS_CON0		((void *)(DREXPHY0_BASE + 0x00B8))
+#define PHY0_DVFS_CON1		((void *)(DREXPHY0_BASE + 0x00E0))
+#define PHY0_DVFS_CON2		((void *)(DREXPHY0_BASE + 0x00BC))
+#define PHY0_DVFS_CON3		((void *)(DREXPHY0_BASE + 0x00C0))
+#define PHY0_DVFS_CON4		((void *)(DREXPHY0_BASE + 0x00C4))
+#define PHY0_DVFS_CON5		((void *)(DREXPHY0_BASE + 0x00C8))
+#define PHY0_DVFS_CON6		((void *)(DREXPHY0_BASE + 0x00CC))
+#define PHY0_ZQ_CON9	((void *)(DREXPHY0_BASE + 0x03EC))
+
+#define DREX0_PAUSE_MRS0	((void *)(DREX0_BASE + 0x0080))
+#define DREX0_PAUSE_MRS1	((void *)(DREX0_BASE + 0x0084))
+#define DREX0_PAUSE_MRS2	((void *)(DREX0_BASE + 0x0088))
+#define DREX0_PAUSE_MRS3	((void *)(DREX0_BASE + 0x008C))
+#define DREX0_PAUSE_MRS4	((void *)(DREX0_BASE + 0x0090))
+
+#define DREX0_TIMING_SET_SW	((void *)(DREX0_BASE + 0x0020))
+
+#define DREX0_PORT_TICK_GRANULARITY_S0	((void *)(DREX0_PF_BASE + 0x0010))
+#define DREX0_PORT_TICK_GRANULARITY_S1	((void *)(DREX0_PF_BASE + 0x0014))
+
+// PHY DVFS CON SFR BIT DEFINITION /
+#define PHY_DVFS_CON0_SET1_MASK	((0x0)|(1<<31)|(1<<29)|(0x0<<24))
+#define PHY_DVFS_CON0_SET0_MASK	((0x0)|(1<<30)|(1<<28)|(0x0<<24)|(0x7<<21)|(0x7<<18)|(0x7<<15)|(0x7<<12)|(0x7<<9)|(0x7<<6)|(0x7<<3)|(0x7<<0))
+#define PHY_DVFS_CON0_DVFS_MODE_MASK	((0x0)|(0x3<<24))
+#define PHY_DVFS_CON0_DVFS_MODE_POSITION	24
+
+#define PHY_DVFS_CON1_SET1_MASK	((0x7<<21)|(0x7<<18)|(0x7<<15)|(0x7<<12)|(0x7<<9)|(0x7<<6)|(0x7<<3)|(0x7<<0))
+#define PHY_DVFS_CON1_SET0_MASK	((0x0))
+#define PHY_DVFS_CON2_SET1_MASK	((0x0)|(0x1<<31)|(0x1F<<24)|(0xF<<12)|(0xF<<8))
+#define PHY_DVFS_CON2_SET0_MASK	((0x0)|(0x1<<30)|(0x1F<<16)|(0xF<<7)|(0xF<<0))
+#define PHY_DVFS_CON3_SET1_MASK	((0x0)|(0x1<<30)|(0x1<<29)|(0x7<<23)|(0x1<<17)|(0xf<<12)|(0xf<<8))
+#define PHY_DVFS_CON3_SET0_MASK	((0x0)|(0x1<<31)|(0x1<<28)|(0x7<<20)|(0x1<<16)|(0xf<<4)|(0xf<<0))
+#define PHY_DVFS_CON4_SET1_MASK	((0x0)|(0x3F<<18)|(0x3F<<12))
+#define PHY_DVFS_CON4_SET0_MASK	((0x0)|(0x3F<<6)|(0x3F<<0))
+#define PHY_DVFS_CON5_SET1_MASK	((0x0)|(0x7<<24)|(0x7<<16)|(0x7<<8)|(0x7<<0))
+#define PHY_DVFS_CON5_SET0_MASK	((0x0))
+#define PHY_DVFS_CON6_SET1_MASK	((0x0))
+#define PHY_DVFS_CON6_SET0_MASK	((0x0)|(0x7<<24)|(0x7<<16)|(0x7<<8)|(0x7<<0))
+
+#define DREX0_DIRECTCMD		((void *)(DREX0_BASE + 0x001C))
+
+
+#define DREX0_timing_set_sw_con 0 /* Pause triggered from CMU */
+
+#define DQS_OSC_UPDATE_EN 0
+#define PERIODIC_WR_TRAIN 0
+
+#if DQS_OSC_UPDATE_EN
+#define dvfs_dqs_osc_en 1
+#else
+#define dvfs_dqs_osc_en 0
+#endif
+
+#if PERIODIC_WR_TRAIN
+#define dvfs_offset 16
+#else
+#define dvfs_offset 0
+#endif
+
+
+enum dmc_dvfs_mif_level_idx {
+	DMC_DVFS_MIF_L0,
+	DMC_DVFS_MIF_L1,
+	DMC_DVFS_MIF_L2,
+	DMC_DVFS_MIF_L3,
+	DMC_DVFS_MIF_L4,
+	DMC_DVFS_MIF_L5,
+	DMC_DVFS_MIF_L6,
+	DMC_DVFS_MIF_L7,
+	DMC_DVFS_MIF_L8,
+	COUNT_OF_CMU_DVFS_MIF_LEVEL,
+	CMU_DVFS_MIF_INVALID = 0xFF,
+};
+
+enum dmc_timing_set_idx {
+	DMC_TIMING_SET_0 = 0,
+	DMC_TIMING_SET_1
+};
+
+enum phy_timing_set_idx {
+	PHY_Normal_mode = 0 ,
+	PHY_DVFS0_mode,
+	PHY_DVFS1_mode
+};
+
+enum timing_parameter_column {
+	drex_Tick_Granularity,
+	drex_mr4_sensing_cyc,
+	drex_dqs_osc_start_cyc,
+	drex_Termination_Control,
+	drex_Winconfig_Write_Odt,
+	drex_Timing_Row0,
+	drex_Timing_Row1,
+	drex_Timing_Data_Aclk,
+	drex_Timing_Data_Mclk,
+	drex_Timing_Power0,
+	drex_Timing_Power1,
+	drex_Etcl,
+	drex_Puase_MRS0,
+	drex_Puase_MRS1,
+	drex_Puase_MRS2,
+	drex_Puase_MRS3,
+	drex_Puase_MRS4,
+	phy_Dvfs_Con0_set1,
+	phy_Dvfs_Con0_set0,
+	phy_Dvfs_Con0_set1_mask,
+	phy_Dvfs_Con0_set0_mask,
+	phy_Dvfs_Con1_set1,
+	phy_Dvfs_Con1_set0,
+	phy_Dvfs_Con1_set1_mask,
+	phy_Dvfs_Con1_set0_mask,
+	phy_Dvfs_Con2_set1,
+	phy_Dvfs_Con2_set0,
+	phy_Dvfs_Con2_set1_mask,
+	phy_Dvfs_Con2_set0_mask,
+	phy_Dvfs_Con3_set1,
+	phy_Dvfs_Con3_set0,
+	phy_Dvfs_Con3_set1_mask,
+	phy_Dvfs_Con3_set0_mask,
+	num_of_g_dmc_drex_dfs_mif_table_column = drex_Etcl - drex_Tick_Granularity + 1,
+	num_of_g_dmc_directcmd_dfs_mif_table_column = drex_Puase_MRS4 - drex_Puase_MRS0 + 1,
+	num_of_g_dmc_phy_dfs_mif_table_column = phy_Dvfs_Con3_set0_mask - phy_Dvfs_Con0_set1 + 1,
+	num_of_dram_parameter = num_of_g_dmc_drex_dfs_mif_table_column + num_of_g_dmc_directcmd_dfs_mif_table_column + num_of_g_dmc_phy_dfs_mif_table_column,
+};
+
+struct dmc_drex_dfs_mif_table {
+	unsigned int drex_Tick_Granularity;
+	unsigned int drex_mr4_sensing_cyc;
+	unsigned int drex_dqs_osc_start_cyc;
+	unsigned int drex_Termination_Control;
+	unsigned int drex_Winconfig_Write_Odt;
+	unsigned int drex_Timing_Row0;
+	unsigned int drex_Timing_Row1;
+	unsigned int drex_Timing_Data_Aclk;
+	unsigned int drex_Timing_Data_Mclk;
+	unsigned int drex_Timing_Power0;
+	unsigned int drex_Timing_Power1;
+	unsigned int drex_Etcl;
+};
+
+
+struct dmc_directcmd_dfs_mif_table {
+	unsigned int drex_Puase_MRS0;
+	unsigned int drex_Puase_MRS1;
+	unsigned int drex_Puase_MRS2;
+	unsigned int drex_Puase_MRS3;
+	unsigned int drex_Puase_MRS4;
+};
+
+struct dmc_phy_dfs_mif_table {
+	unsigned int phy_Dvfs_Con0_set1;
+	unsigned int phy_Dvfs_Con0_set0;
+	unsigned int phy_Dvfs_Con0_set1_mask;
+	unsigned int phy_Dvfs_Con0_set0_mask;
+	unsigned int phy_Dvfs_Con1_set1;
+	unsigned int phy_Dvfs_Con1_set0;
+	unsigned int phy_Dvfs_Con1_set1_mask;
+	unsigned int phy_Dvfs_Con1_set0_mask;
+	unsigned int phy_Dvfs_Con2_set1;
+	unsigned int phy_Dvfs_Con2_set0;
+	unsigned int phy_Dvfs_Con2_set1_mask;
+	unsigned int phy_Dvfs_Con2_set0_mask;
+	unsigned int phy_Dvfs_Con3_set1;
+	unsigned int phy_Dvfs_Con3_set0;
+	unsigned int phy_Dvfs_Con3_set1_mask;
+	unsigned int phy_Dvfs_Con3_set0_mask;
+	unsigned int phy_Dvfs_Con4_set1;
+	unsigned int phy_Dvfs_Con4_set0;
+	unsigned int phy_Dvfs_Con4_set1_mask;
+	unsigned int phy_Dvfs_Con4_set0_mask;
+	unsigned int phy_Dvfs_Con5_set1;
+	unsigned int phy_Dvfs_Con5_set0;
+	unsigned int phy_Dvfs_Con5_set1_mask;
+	unsigned int phy_Dvfs_Con5_set0_mask;
+	unsigned int phy_Dvfs_Con6_set1;
+	unsigned int phy_Dvfs_Con6_set0;
+	unsigned int phy_Dvfs_Con6_set1_mask;
+	unsigned int phy_Dvfs_Con6_set0_mask;
+};
+
+enum dmc_dvfs_mif_switching_level_idx {
+	DMC_DVFS_MIF__switching_L0,
+	DMC_DVFS_MIF__switching_L1,
+};
+
+#define LP4_RL 12
+#define LP4_WL 6
+#define LP4_RL_L10 6
+#define LP4_WL_L10 4
+#define DRAM_RLWL 0x09
+#define DRAM_RLWL_L10 0x00
+
+static struct dmc_drex_dfs_mif_table *pwrcal_dfs_drex_mif_table;
+static struct dmc_directcmd_dfs_mif_table *pwrcal_pause_directcmd_dfs_mif_table;
+static struct dmc_phy_dfs_mif_table *pwrcal_dfs_phy_mif_table;
+
+
+static unsigned long long *mif_freq_to_level;
+static int num_mif_freq_to_level;
+
+
+static unsigned int convert_to_level(unsigned long long freq)
+{
+	int idx;
+	int tablesize = num_mif_freq_to_level;
+
+	for (idx = tablesize - 1; idx >= 0; idx--)
+		if (freq <= mif_freq_to_level[idx])
+			return (unsigned int)idx;
+
+	return 0;
+}
+
+
+void pwrcal_dmc_set_dvfs(unsigned long long target_mif_freq, unsigned int timing_set_idx)
+{
+	unsigned int uReg;
+//	unsigned int soc_vref[4];
+	unsigned int target_mif_level_idx, target_mif_level_switch_idx;
+	unsigned int offset;
+
+
+	target_mif_level_idx = convert_to_level(target_mif_freq);
+	target_mif_level_switch_idx = convert_to_level(target_mif_freq);
+
+	if (timing_set_idx == DMC_TIMING_SET_0) {
+		for (offset = 0; offset < 0x100000; offset += 0x100000) {
+
+			/* Phy & DREX Mode setting */
+			if (target_mif_level_idx != 0) {
+				uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
+				uReg &= ~(PHY_DVFS_CON0_DVFS_MODE_MASK);
+				uReg |= (PHY_DVFS0_mode<<PHY_DVFS_CON0_DVFS_MODE_POSITION);
+				pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
+			} else {
+				uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
+				uReg &= ~(PHY_DVFS_CON0_DVFS_MODE_MASK);
+				uReg |= (PHY_Normal_mode<<PHY_DVFS_CON0_DVFS_MODE_POSITION);
+				pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
+			}
+
+			pwrcal_writel(offset + DREX0_TIMING_SET_SW, DREX0_timing_set_sw_con);
+			pwrcal_writel((void *)CMU_MIF_BASE + 0x1004,  DMC_TIMING_SET_0); /*cmu pause setting */
+
+			#define PHY_DVFS_CON0_DVFS_MODE_MASK	((0x0)|(0x3<<24))
+			#define PHY_DVFS_CON0_DVFS_MODE_POSITION	24
+
+			pwrcal_writel(offset + DREX0_TICK_GRANULARITY_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Tick_Granularity);
+			pwrcal_writel(offset + DREX0_PORT_TICK_GRANULARITY_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Tick_Granularity);
+			pwrcal_writel(offset + DREX0_TEMP_SENSING_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_mr4_sensing_cyc);
+			pwrcal_writel(offset + DREX0_DQS_OSC_CON1_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_dqs_osc_start_cyc);
+			pwrcal_writel(offset + DREX0_TERMINATION_CONTROL_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Termination_Control);
+			pwrcal_writel(offset + DREX0_WINCONFIG_WRITE_ODT_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Winconfig_Write_Odt);
+			pwrcal_writel(offset + DREX0_TIMING_ROW0_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Row0);
+			pwrcal_writel(offset + DREX0_TIMING_ROW1_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Row1);
+			pwrcal_writel(offset + DREX0_TIMING_DATA_ACLK_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Data_Aclk);
+			pwrcal_writel(offset + DREX0_TIMING_DATA_MCLK_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Data_Mclk);
+			pwrcal_writel(offset + DREX0_TIMING_POWER0_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Power0);
+			pwrcal_writel(offset + DREX0_TIMING_POWER1_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Power1);
+			pwrcal_writel(offset + DREX0_TIMING_ETC1_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Etcl);
+
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
+			uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con0_set0_mask);
+			uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con0_set0;
+			pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
+
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON1);
+			uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con1_set0_mask);
+			uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con1_set0;
+			pwrcal_writel(offset + PHY0_DVFS_CON1, uReg);
+
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON2);
+			uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con2_set0_mask);
+			uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con2_set0;
+			pwrcal_writel(offset + PHY0_DVFS_CON2, uReg);
+
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON3);
+			uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con3_set0_mask);
+			uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con3_set0;
+			pwrcal_writel(offset + PHY0_DVFS_CON3, uReg);
+
+			pwrcal_writel(offset + DREX0_PAUSE_MRS0, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS0);
+			pwrcal_writel(offset + DREX0_PAUSE_MRS1, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS1);
+			pwrcal_writel(offset + DREX0_PAUSE_MRS2, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS2);
+			pwrcal_writel(offset + DREX0_PAUSE_MRS3, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS3);
+			pwrcal_writel(offset + DREX0_PAUSE_MRS4, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS4);
+		}
+
+	} else if (timing_set_idx == DMC_TIMING_SET_1) {
+		for (offset = 0; offset < 0x100000; offset += 0x100000) {
+
+			/* Phy & DREX Mode setting */
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
+			uReg &= ~(PHY_DVFS_CON0_DVFS_MODE_MASK);
+			uReg |= (PHY_DVFS1_mode<<PHY_DVFS_CON0_DVFS_MODE_POSITION);
+			pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
+
+			pwrcal_writel(offset + DREX0_TIMING_SET_SW,  DREX0_timing_set_sw_con);
+			pwrcal_writel((void *)CMU_MIF_BASE + 0x1004,  DMC_TIMING_SET_1); /*cmu pause setting */
+
+			pwrcal_writel(offset + DREX0_TICK_GRANULARITY_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Tick_Granularity);
+			pwrcal_writel(offset + DREX0_PORT_TICK_GRANULARITY_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Tick_Granularity);
+			pwrcal_writel(offset + DREX0_TEMP_SENSING_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_mr4_sensing_cyc);
+			pwrcal_writel(offset + DREX0_DQS_OSC_CON1_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_dqs_osc_start_cyc);
+			pwrcal_writel(offset + DREX0_TERMINATION_CONTROL_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Termination_Control);
+			pwrcal_writel(offset + DREX0_WINCONFIG_WRITE_ODT_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Winconfig_Write_Odt);
+			pwrcal_writel(offset + DREX0_TIMING_ROW0_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Row0);
+			pwrcal_writel(offset + DREX0_TIMING_ROW1_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Row1);
+			pwrcal_writel(offset + DREX0_TIMING_DATA_ACLK_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Data_Aclk);
+			pwrcal_writel(offset + DREX0_TIMING_DATA_MCLK_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Data_Mclk);
+			pwrcal_writel(offset + DREX0_TIMING_POWER0_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Power0);
+			pwrcal_writel(offset + DREX0_TIMING_POWER1_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Power1);
+			pwrcal_writel(offset + DREX0_TIMING_ETC1_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Etcl);
+
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
+			uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con0_set1_mask);
+			uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con0_set1;
+			pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
+
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON1);
+			uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con1_set1_mask);
+			uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con1_set1;
+			pwrcal_writel(offset + PHY0_DVFS_CON1, uReg);
+
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON2);
+			uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con2_set1_mask);
+			uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con2_set1;
+			pwrcal_writel(offset + PHY0_DVFS_CON2, uReg);
+
+			uReg = pwrcal_readl(offset + PHY0_DVFS_CON3);
+			uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con3_set1_mask);
+			uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con3_set1;
+			pwrcal_writel(offset + PHY0_DVFS_CON3, uReg);
+
+			pwrcal_writel(offset + DREX0_PAUSE_MRS0, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS0);
+			pwrcal_writel(offset + DREX0_PAUSE_MRS1, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS1);
+			pwrcal_writel(offset + DREX0_PAUSE_MRS2, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS2);
+			pwrcal_writel(offset + DREX0_PAUSE_MRS3, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS3);
+			pwrcal_writel(offset + DREX0_PAUSE_MRS4, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS4);
+		}
+	} else {
+		pr_err("wrong DMC timing set selection on DVFS\n");
+		return;
+	}
+}
+
+//static unsigned int per_mrs_en;
+
+void pwrcal_dmc_set_pre_dvfs(void)
+{
+
+}
+
+void pwrcal_dmc_set_post_dvfs(unsigned long long target_freq)
+{
+
+}
+
+
+
+void pwrcal_dmc_set_refresh_method_pre_dvfs(unsigned long long current_rate, unsigned long long target_rate)
+{
+	/* target_rate is MIF clock rate */
+	unsigned int uReg;
+	uReg = pwrcal_readl(DREX0_CG_CONTROL);
+	uReg = ((uReg & ~(1 << 24)) | (0 << 24));
+	pwrcal_writel(DREX0_CG_CONTROL, uReg);	//External Clock Gating - PHY Clock Gating disable
+}
+
+void pwrcal_dmc_set_refresh_method_post_dvfs(unsigned long long current_rate, unsigned long long target_rate)
+{
+	/* target_rate is MIF clock rate */
+	unsigned int uReg;
+	uReg = pwrcal_readl(DREX0_CG_CONTROL);
+	uReg = ((uReg & ~(1 << 24)) | (1 << 24));
+	pwrcal_writel(DREX0_CG_CONTROL, uReg);	//External Clock Gating - PHY Clock Gating enable
+}
+
+void pwrcal_dmc_set_dsref_cycle(unsigned long long target_rate)
+{
+	unsigned int  uReg, cycle;
+
+	/* target_rate is MIF clock rate */
+	if (target_rate > 800 * MHZ)
+		cycle = 0x3ff;
+	else if (target_rate > 400 * MHZ)
+		cycle = 0x1ff;
+	else if (target_rate > 200 * MHZ)
+		cycle = 0x90;
+	else
+		cycle = 0x90;
+
+
+	/* dsref disable */
+	uReg = pwrcal_readl(DREX0_MEMORY_CONTROL0);
+	uReg &= ~(1 << 4);
+	pwrcal_writel(DREX0_MEMORY_CONTROL0, uReg);
+
+	uReg = pwrcal_readl(DREX0_POWER_DOWN_CONFIG);
+	uReg = ((uReg & ~(0xffff << 16)) | (cycle << 16));
+	pwrcal_writel(DREX0_POWER_DOWN_CONFIG, uReg);
+
+	/* dsref enable */
+	uReg = pwrcal_readl(DREX0_MEMORY_CONTROL0);
+	uReg |= (1 << 4);
+	pwrcal_writel(DREX0_MEMORY_CONTROL0, uReg);
+
+}
+
+
+
+void dfs_dram_param_init(void)
+{
+	int i;
+	void *dram_block;
+	u32 uMem_type;
+//	int memory_size = 2; // means 3GB
+	struct ect_timing_param_size *size;
+
+	uMem_type = (pwrcal_readl(PMU_DREX_CALIBRATION2) & 0xFFFF);
+
+	dram_block = ect_get_block(BLOCK_TIMING_PARAM);
+	if (dram_block == NULL)
+		return;
+
+	size = ect_timing_param_get_size(dram_block, uMem_type);
+	if (size == NULL)
+		return;
+
+	if (num_of_dram_parameter != size->num_of_timing_param)
+		return;
+
+	pwrcal_dfs_drex_mif_table = kzalloc(sizeof(struct dmc_drex_dfs_mif_table) * num_of_g_dmc_drex_dfs_mif_table_column * size->num_of_level, GFP_KERNEL);
+	if (pwrcal_dfs_drex_mif_table == NULL)
+		return;
+
+	pwrcal_pause_directcmd_dfs_mif_table = kzalloc(sizeof(struct dmc_directcmd_dfs_mif_table) * num_of_g_dmc_directcmd_dfs_mif_table_column * size->num_of_level, GFP_KERNEL);
+	if (pwrcal_pause_directcmd_dfs_mif_table == NULL)
+		return;
+
+	pwrcal_dfs_phy_mif_table = kzalloc(sizeof(struct dmc_phy_dfs_mif_table) * num_of_g_dmc_phy_dfs_mif_table_column * size->num_of_level, GFP_KERNEL);
+	if (pwrcal_dfs_phy_mif_table == NULL)
+		return;
+
+	for (i = 0; i < size->num_of_level; ++i) {
+		pwrcal_dfs_drex_mif_table[i].drex_Tick_Granularity = size->timing_parameter[i * num_of_dram_parameter + drex_Tick_Granularity];
+		pwrcal_dfs_drex_mif_table[i].drex_mr4_sensing_cyc = size->timing_parameter[i * num_of_dram_parameter + drex_mr4_sensing_cyc];
+		pwrcal_dfs_drex_mif_table[i].drex_dqs_osc_start_cyc = size->timing_parameter[i * num_of_dram_parameter + drex_dqs_osc_start_cyc];
+		pwrcal_dfs_drex_mif_table[i].drex_Termination_Control = size->timing_parameter[i * num_of_dram_parameter + drex_Termination_Control];
+		pwrcal_dfs_drex_mif_table[i].drex_Winconfig_Write_Odt = size->timing_parameter[i * num_of_dram_parameter + drex_Winconfig_Write_Odt];
+		pwrcal_dfs_drex_mif_table[i].drex_Timing_Row0 = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Row0];
+		pwrcal_dfs_drex_mif_table[i].drex_Timing_Row1 = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Row1];
+		pwrcal_dfs_drex_mif_table[i].drex_Timing_Data_Aclk = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Data_Aclk];
+		pwrcal_dfs_drex_mif_table[i].drex_Timing_Data_Mclk = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Data_Mclk];
+		pwrcal_dfs_drex_mif_table[i].drex_Timing_Power0 = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Power0];
+		pwrcal_dfs_drex_mif_table[i].drex_Timing_Power1 = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Power1];
+		pwrcal_dfs_drex_mif_table[i].drex_Etcl = size->timing_parameter[i * num_of_dram_parameter + drex_Etcl];
+
+		pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS0 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS0];
+		pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS1 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS1];
+		pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS2 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS2];
+		pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS3 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS3];
+		pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS4 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS4];
+
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con0_set1 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con0_set1];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con0_set0 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con0_set0];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con0_set1_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con0_set1_mask];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con0_set0_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con0_set0_mask];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con1_set1 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con1_set1];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con1_set0 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con1_set0];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con1_set1_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con1_set1_mask];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con1_set0_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con1_set0_mask];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con2_set1 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con2_set1];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con2_set0 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con2_set0];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con2_set1_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con2_set1_mask];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con2_set0_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con2_set0_mask];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con3_set1 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con3_set1];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con3_set0 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con3_set0];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con3_set1_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con3_set1_mask];
+		pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con3_set0_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con3_set0_mask];
+	}
+}
+
+void dfs_mif_level_init(void)
+{
+	int i;
+	void *dvfs_block;
+	struct ect_dvfs_domain *domain;
+
+	dvfs_block = ect_get_block(BLOCK_DVFS);
+	if (dvfs_block == NULL)
+		return;
+
+	domain = ect_dvfs_get_domain(dvfs_block, vclk_dvfs_mif.vclk.name);
+	if (domain == NULL)
+		return;
+
+	mif_freq_to_level = kzalloc(sizeof(unsigned long long) * domain->num_of_level, GFP_KERNEL);
+	if (mif_freq_to_level == NULL)
+		return;
+
+	num_mif_freq_to_level = domain->num_of_level;
+
+	for (i = 0; i < domain->num_of_level; ++i)
+		mif_freq_to_level[i] = (unsigned long long) domain->list_level[i].level * KHZ;
+}
+
+void dfs_dram_init(void)
+{
+	dfs_dram_param_init();
+	dfs_mif_level_init();
+}
+
+
+#endif

drivers/soc/samsung/pwrcal/S5E7870/S5E7870-pll.c

@@ -0,0 +1,537 @@
+#include "../pwrcal.h"
+#include "../pwrcal-clk.h"
+#include "../pwrcal-env.h"
+#include "../pwrcal-rae.h"
+#include "../pwrcal-pmu.h"
+#include "S5E7870-cmusfr.h"
+#include "S5E7870-pmusfr.h"
+#include "S5E7870-cmu.h"
+
+
+/*
+	PLLs
+*/
+/* PLL141XX Clock Type */
+#define PLL141XX_MDIV_SHIFT		16
+#define PLL141XX_PDIV_SHIFT		8
+#define PLL141XX_SDIV_SHIFT		0
+#define PLL141XX_MDIV_MASK		0x3FF
+#define PLL141XX_PDIV_MASK		0x3F
+#define PLL141XX_SDIV_MASK		0x7
+#define PLL141XX_ENABLE			31
+#define PLL141XX_LOCKED			29
+#define PLL141XX_BYPASS			22
+
+/* PLL1431X Clock Type */
+#define PLL1431X_MDIV_SHIFT		16
+#define PLL1431X_PDIV_SHIFT		8
+#define PLL1431X_SDIV_SHIFT		0
+#define PLL1431X_K_SHIFT		0
+#define PLL1431X_MDIV_MASK		0x3FF
+#define PLL1431X_PDIV_MASK		0x3F
+#define PLL1431X_SDIV_MASK		0x7
+#define PLL1431X_K_MASK		0xFFFF
+#define PLL1431X_ENABLE			31
+#define PLL1431X_LOCKED			29
+#define PLL1431X_BYPASS			4
+
+#define FIN_HZ_26M		(26*MHZ)
+
+static const struct pwrcal_pll_rate_table *_clk_get_pll_settings(
+	struct pwrcal_pll *pll_clk,
+	unsigned long long rate)
+{
+	int i;
+	const struct pwrcal_pll_rate_table  *prate_table = pll_clk->rate_table;
+
+	for (i = 0; i < pll_clk->rate_count; i++) {
+		if (rate == prate_table[i].rate)
+			return &prate_table[i];
+	}
+
+	return NULL;
+}
+
+static int _clk_pll141xx_find_pms(struct pll_spec *pll_spec,
+								  struct pwrcal_pll_rate_table *rate_table,
+								  unsigned long long rate)
+{
+	unsigned int p, m, s;
+	unsigned long long fref, fvco, fout;
+	unsigned long long tmprate, tmpfout;
+	unsigned long long mindiffrate = 0xFFFFFFFFFFFFFFFF;
+	unsigned int min_p, min_m, min_s, min_fout;
+
+	for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
+		fref = FIN_HZ_26M / p;
+		if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
+			continue;
+
+		for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
+			tmprate = rate;
+			do_div(tmprate, MHZ);
+			tmprate = tmprate * p * (1 << s);
+			do_div(tmprate, (FIN_HZ_26M / MHZ));
+			m = (unsigned int)tmprate;
+
+			if ((m < pll_spec->mdiv_min)
+					|| (m > pll_spec->mdiv_max))
+				continue;
+
+			fvco = ((unsigned long long)FIN_HZ_26M) * m;
+			do_div(fvco, p);
+			if ((fvco < pll_spec->fvco_min)
+					|| (fvco > pll_spec->fvco_max))
+				continue;
+
+			fout = fvco >> s;
+			if ((fout >= pll_spec->fout_min)
+					&& (fout <= pll_spec->fout_max)) {
+				tmprate = rate;
+				do_div(tmprate, KHZ);
+				tmpfout = fout;
+				do_div(tmpfout, KHZ);
+				if (tmprate == tmpfout) {
+					rate_table->rate = fout;
+					rate_table->pdiv = p;
+					rate_table->mdiv = m;
+					rate_table->sdiv = s;
+					rate_table->kdiv = 0;
+					return 0;
+				}
+				if (tmpfout < tmprate && mindiffrate > tmprate - tmpfout) {
+					mindiffrate = tmprate - tmpfout;
+					min_fout = fout;
+					min_p = p;
+					min_m = m;
+					min_s = s;
+				}
+			}
+		}
+	}
+
+	if (mindiffrate != 0xFFFFFFFFFFFFFFFF) {
+		rate_table->rate = min_fout;
+		rate_table->pdiv = min_p;
+		rate_table->mdiv = min_m;
+		rate_table->sdiv = min_s;
+		rate_table->kdiv = 0;
+		return 0;
+	}
+	return -1;
+}
+
+static int _clk_pll141xx_is_enabled(struct pwrcal_clk *clk)
+{
+	return (int)(pwrcal_getbit(clk->offset, PLL141XX_ENABLE));
+}
+
+static int _clk_pll141xx_enable(struct pwrcal_clk *clk)
+{
+	int timeout;
+
+	pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 1);
+
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+
+static int _clk_pll141xx_disable(struct pwrcal_clk *clk)
+{
+	pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 0);
+
+	return 0;
+}
+
+int _clk_pll141xx_is_disabled_bypass(struct pwrcal_clk *clk)
+{
+	if (pwrcal_getbit(clk->offset + 1, PLL141XX_BYPASS))
+		return 0;
+
+	return 1;
+}
+
+
+int _clk_pll141xx_set_bypass(struct pwrcal_clk *clk, int bypass_disable)
+{
+	if (bypass_disable == 0)
+		pwrcal_setbit(clk + 1, PLL141XX_BYPASS, 1);
+	else
+		pwrcal_setbit(clk + 1, PLL141XX_BYPASS, 0);
+
+	return 0;
+}
+
+static int _clk_pll141xx_set_pms(struct pwrcal_clk *clk,
+								 const struct pwrcal_pll_rate_table  *rate_table)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0;
+
+	int timeout;
+
+	pdiv = rate_table->pdiv;
+	mdiv = rate_table->mdiv;
+	sdiv = rate_table->sdiv;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	pll_con0 &= ~((PLL141XX_MDIV_MASK << PLL141XX_MDIV_SHIFT)
+				  | (PLL141XX_PDIV_MASK << PLL141XX_PDIV_SHIFT)
+				  | (PLL141XX_SDIV_MASK << PLL141XX_SDIV_SHIFT));
+	pll_con0 |= (mdiv << PLL141XX_MDIV_SHIFT)
+				| (pdiv << PLL141XX_PDIV_SHIFT)
+				| (sdiv << PLL141XX_SDIV_SHIFT);
+	pll_con0 &= ~(1 << 26);
+	pll_con0 |= (1 << 5);
+
+	pwrcal_writel(clk->status, pdiv * 150);
+	pwrcal_writel(clk->offset, pll_con0);
+
+	if (pll_con0 & (1 << PLL141XX_ENABLE)) {
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+	}
+
+	return 0;
+
+}
+
+
+static int _clk_pll141xx_set_rate(struct pwrcal_clk *clk,
+								  unsigned long long rate)
+{
+	struct pwrcal_pll *pll = to_pll(clk);
+	struct pll_spec *pll_spec;
+	struct pwrcal_pll_rate_table  tmp_rate_table;
+	const struct pwrcal_pll_rate_table  *rate_table;
+
+	if (rate == 0) {
+		if (_clk_pll141xx_is_enabled(clk) != 0)
+			if (_clk_pll141xx_disable(clk))
+				goto errorout;
+		return 0;
+	}
+
+	rate_table = _clk_get_pll_settings(pll, rate);
+	if (rate_table == NULL) {
+		pll_spec = clk_pll_get_spec(clk);
+		if (pll_spec == NULL)
+			goto errorout;
+
+		if (_clk_pll141xx_find_pms(pll_spec, &tmp_rate_table, rate)) {
+			pr_err("can't find pms value for rate(%lldHz) of \'%s\'",
+				   rate,
+				   clk->name);
+			goto errorout;
+		}
+
+		rate_table = &tmp_rate_table;
+
+		pr_warn("not exist in rate table, p(%d), m(%d), s(%d), fout(%lldHz) %s",
+				rate_table->pdiv,
+				rate_table->mdiv,
+				rate_table->sdiv,
+				rate,
+				clk->name);
+	}
+
+	if (_clk_pll141xx_set_pms(clk, rate_table))
+		goto errorout;
+
+	if (rate != 0) {
+		if (_clk_pll141xx_is_enabled(clk) == 0)
+			_clk_pll141xx_enable(clk);
+	}
+	return 0;
+
+errorout:
+	return -1;
+}
+
+
+static unsigned long long _clk_pll141xx_get_rate(struct pwrcal_clk *clk)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0;
+	unsigned long long fout;
+
+	if (_clk_pll141xx_is_enabled(clk) == 0)
+		return 0;
+	pll_con0 = pwrcal_readl(clk->offset);
+	mdiv = (pll_con0 >> PLL141XX_MDIV_SHIFT) & PLL141XX_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL141XX_PDIV_SHIFT) & PLL141XX_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL141XX_SDIV_SHIFT) & PLL141XX_SDIV_MASK;
+
+	if (pdiv == 0) {
+		pr_err("pdiv is 0, id(%s)", clk->name);
+		return 0;
+	}
+	fout = FIN_HZ_26M * mdiv;
+	do_div(fout, (pdiv << sdiv));
+	return (unsigned long long)fout;
+}
+
+static int _clk_pll1431x_find_pms(struct pll_spec *pll_spec,
+								  struct pwrcal_pll_rate_table *rate_table,
+								  unsigned long long rate)
+{
+	unsigned int p, m, s;
+	signed short k;
+	unsigned long long fref, fvco, fout;
+	unsigned long long tmprate, tmpfout;
+
+	for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
+		fref = FIN_HZ_26M / p;
+		if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
+			continue;
+
+		for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
+			tmprate = rate;
+			do_div(tmprate, MHZ);
+			tmprate = tmprate * p * (1 << s);
+			do_div(tmprate, (FIN_HZ_26M / MHZ));
+			m = (unsigned int)tmprate;
+
+			if ((m < pll_spec->mdiv_min)
+					|| (m > pll_spec->mdiv_max))
+				continue;
+
+			tmprate = rate;
+			do_div(tmprate, MHZ);
+			tmprate = tmprate * p * (1 << s);
+			do_div(tmprate, (FIN_HZ_26M / MHZ));
+			tmprate = (tmprate - m) * 65536;
+			k = (unsigned int)tmprate;
+			if ((k < pll_spec->kdiv_min)
+					|| (k > pll_spec->kdiv_max))
+				continue;
+
+			fvco = FIN_HZ_26M * ((m << 16) + k);
+			do_div(fvco, p);
+			fvco >>= 16;
+			if ((fvco < pll_spec->fvco_min)
+					|| (fvco > pll_spec->fvco_max))
+				continue;
+
+			fout = fvco >> s;
+			if ((fout >= pll_spec->fout_min)
+					&& (fout <= pll_spec->fout_max)) {
+				tmprate = rate;
+				do_div(tmprate, KHZ);
+				tmpfout = fout;
+				do_div(tmpfout, KHZ);
+				if (tmprate == tmpfout) {
+					rate_table->rate = fout;
+					rate_table->pdiv = p;
+					rate_table->mdiv = m;
+					rate_table->sdiv = s;
+					rate_table->kdiv = k;
+					return 0;
+				}
+			}
+		}
+	}
+
+	return -1;
+}
+
+static int _clk_pll1431x_is_enabled(struct pwrcal_clk *clk)
+{
+	return (int)(pwrcal_getbit(clk->offset, PLL1431X_ENABLE));
+}
+
+static int _clk_pll1431x_enable(struct pwrcal_clk *clk)
+{
+	int timeout;
+
+	pwrcal_setbit(clk->offset, PLL1431X_ENABLE, 1);
+
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(clk->offset, PLL1431X_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+static int _clk_pll1431x_disable(struct pwrcal_clk *clk)
+{
+	pwrcal_setbit(clk->offset, PLL1431X_ENABLE, 0);
+
+	return 0;
+}
+
+int _clk_pll1431x_is_disabled_bypass(struct pwrcal_clk *clk)
+{
+	if (pwrcal_getbit(clk->offset + 2, PLL1431X_BYPASS))
+		return 0;
+
+	return 1;
+}
+
+int _clk_pll1431x_set_bypass(struct pwrcal_clk *clk, int bypass_disable)
+{
+	if (bypass_disable == 0)
+		pwrcal_setbit(clk->offset + 2, PLL1431X_BYPASS, 1);
+	else
+		pwrcal_setbit(clk->offset + 2, PLL1431X_BYPASS, 0);
+
+	return 0;
+}
+
+static int _clk_pll1431x_set_pms(struct pwrcal_clk *clk,
+								 const struct pwrcal_pll_rate_table  *rate_table)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0, pll_con1;
+	signed short kdiv;
+	int timeout;
+
+	pdiv = rate_table->pdiv;
+	mdiv = rate_table->mdiv;
+	sdiv = rate_table->sdiv;
+	kdiv = rate_table->kdiv;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	pll_con1 = pwrcal_readl(clk->offset + 1);
+	pll_con0 &= ~((PLL1431X_MDIV_MASK << PLL1431X_MDIV_SHIFT)
+				  | (PLL1431X_PDIV_MASK << PLL1431X_PDIV_SHIFT)
+				  | (PLL1431X_SDIV_MASK << PLL1431X_SDIV_SHIFT));
+	pll_con0 |= (mdiv << PLL1431X_MDIV_SHIFT)
+				| (pdiv << PLL1431X_PDIV_SHIFT)
+				| (sdiv << PLL1431X_SDIV_SHIFT);
+	pll_con0 &= ~(1 << 26);
+	pll_con0 |= (1 << 5);
+
+	pll_con1 &= ~(PLL1431X_K_MASK << PLL1431X_K_SHIFT);
+	pll_con1 |= (kdiv << PLL1431X_K_SHIFT);
+
+	if (kdiv == 0)
+		pwrcal_writel(clk->status, pdiv * 3000);
+	else
+		pwrcal_writel(clk->status, pdiv * 3000);
+	pwrcal_writel(clk->offset, pll_con0);
+	pwrcal_writel(clk->offset + 1, pll_con1);
+
+	if (pll_con0 & (1 << PLL1431X_ENABLE)) {
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(clk->offset, PLL1431X_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+	}
+
+	return 0;
+}
+
+static int _clk_pll1431x_set_rate(struct pwrcal_clk *clk,
+								  unsigned long long rate)
+{
+	struct pwrcal_pll *pll = to_pll(clk);
+	struct pwrcal_pll_rate_table  tmp_rate_table;
+	const struct pwrcal_pll_rate_table  *rate_table;
+	struct pll_spec *pll_spec;
+
+	if (rate == 0) {
+		if (_clk_pll1431x_is_enabled(clk) != 0)
+			if (_clk_pll1431x_disable(clk))
+				goto errorout;
+		return 0;
+	}
+
+	rate_table = _clk_get_pll_settings(pll, rate);
+	if (rate_table == NULL) {
+		pll_spec = clk_pll_get_spec(clk);
+		if (pll_spec == NULL)
+			goto errorout;
+
+		if (_clk_pll1431x_find_pms(pll_spec, &tmp_rate_table, rate) < 0) {
+			pr_err("can't find pms value for rate(%lldHz) of %s",
+				   rate,
+				   clk->name);
+			goto errorout;
+		}
+
+		rate_table = &tmp_rate_table;
+		pr_warn("not exist in rate table, p(%d) m(%d) s(%d) k(%d) fout(%lld Hz) of %s",
+				rate_table->pdiv,
+				rate_table->mdiv,
+				rate_table->sdiv,
+				rate_table->kdiv,
+				rate,
+				clk->name);
+	}
+
+	if (_clk_pll1431x_set_pms(clk, rate_table))
+		goto errorout;
+
+	if (rate != 0) {
+		if (_clk_pll1431x_is_enabled(clk) == 0)
+			_clk_pll1431x_enable(clk);
+	}
+
+	return 0;
+
+errorout:
+	return -1;
+}
+
+static unsigned long long _clk_pll1431x_get_rate(struct pwrcal_clk *clk)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0, pll_con1;
+	signed short kdiv;
+	unsigned long long fout;
+
+	if (_clk_pll1431x_is_enabled(clk) == 0)
+		return 0;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	pll_con1 = pwrcal_readl(clk->offset + 1);
+	mdiv = (pll_con0 >> PLL1431X_MDIV_SHIFT) & PLL1431X_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL1431X_PDIV_SHIFT) & PLL1431X_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL1431X_SDIV_SHIFT) & PLL1431X_SDIV_MASK;
+
+	kdiv = (short)(pll_con1 >> PLL1431X_K_SHIFT) & PLL1431X_K_MASK;
+
+	if (pdiv == 0) {
+		pr_err("pdiv is 0, id(%s)", clk->name);
+		return 0;
+	}
+
+	fout = FIN_HZ_26M * ((mdiv << 16) + kdiv);
+	do_div(fout, (pdiv << sdiv));
+	fout >>= 16;
+
+	return (unsigned long long)fout;
+}
+
+struct pwrcal_pll_ops pll141xx_ops = {
+	.is_enabled = _clk_pll141xx_is_enabled,
+	.enable = _clk_pll141xx_enable,
+	.disable = _clk_pll141xx_disable,
+	.set_rate = _clk_pll141xx_set_rate,
+	.get_rate = _clk_pll141xx_get_rate,
+};
+
+struct pwrcal_pll_ops pll1431x_ops = {
+	.is_enabled = _clk_pll1431x_is_enabled,
+	.enable = _clk_pll1431x_enable,
+	.disable = _clk_pll1431x_disable,
+	.set_rate = _clk_pll1431x_set_rate,
+	.get_rate = _clk_pll1431x_get_rate,
+};

drivers/soc/samsung/pwrcal/S5E7870/S5E7870-pmu.c

@@ -0,0 +1,198 @@
+#include "../pwrcal.h"
+#include "../pwrcal-env.h"
+#include "../pwrcal-rae.h"
+#include "../pwrcal-pmu.h"
+#include "S5E7870-cmusfr.h"
+#include "S5E7870-pmusfr.h"
+#include "S5E7870-cmu.h"
+
+
+static void dispaud_prev(int enable)
+{
+	if (enable == 0) {
+		pwrcal_setf(CLK_ENABLE_CLK_DISPAUD_BUS, 0, 0x7, 0x7);
+		pwrcal_setf(CLK_ENABLE_CLK_DISPAUD_APB, 0, 0x1, 0x1);
+		pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER,	27,	1);
+	}
+
+	pwrcal_setf(PMU_CLKRUN_CMU_DISPAUD_SYS_PWR_REG, 0, 0x1, 0x0);
+	pwrcal_setf(PMU_CLKSTOP_CMU_DISPAUD_SYS_PWR_REG, 0, 0x1, 0x0);
+	pwrcal_setf(PMU_DISABLE_PLL_CMU_DISPAUD_SYS_PWR_REG, 0, 0x1, 0x0);
+	pwrcal_setf(PMU_RESET_LOGIC_DISPAUD_SYS_PWR_REG, 0, 0x1, 0x0);
+	pwrcal_setf(PMU_RESET_CMU_DISPAUD_SYS_PWR_REG, 0, 0x1, 0x0);
+}
+
+static void g3d_prev(int enable)
+{
+	if (enable == 0) {
+		pwrcal_setf(CLK_ENABLE_CLK_G3D_BUS, 1, 0x3, 0x3);
+		pwrcal_setf(CLK_ENABLE_CLK_G3D_APB, 1, 0x1, 0x1);
+	}
+
+	pwrcal_setf(PMU_CLKRUN_CMU_G3D_SYS_PWR_REG, 0, 0x1, 0x0);
+	pwrcal_setf(PMU_CLKSTOP_CMU_G3D_SYS_PWR_REG, 0, 0x1, 0x0);
+	pwrcal_setf(PMU_DISABLE_PLL_CMU_G3D_SYS_PWR_REG, 0, 0x1, 0x0);
+	pwrcal_setf(PMU_RESET_LOGIC_G3D_SYS_PWR_REG, 0, 0x1, 0x0);
+	pwrcal_setf(PMU_RESET_CMU_G3D_SYS_PWR_REG, 0, 0x1, 0x0);
+
+}
+
+static void isp_prev(int enable)
+{
+	if (enable == 0) {
+		pwrcal_setf(CLK_ENABLE_CLK_ISP_VRA, 0, 0x1, 0x1);
+		pwrcal_setf(CLK_ENABLE_CLK_ISP_APB, 0, 0x1, 0x1);
+		pwrcal_setf(CLK_ENABLE_CLK_ISP_ISPD, 0, 0x1, 0x1);
+		pwrcal_setf(CLK_ENABLE_CLK_ISP_CAM, 0, 0x1, 0x1);
+		pwrcal_setf(CLK_ENABLE_CLK_ISP_ISP, 0, 0x1, 0x1);
+		pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER,	27,	1);
+
+#if 0 // plz, check the sfr name first
+		while (pwrcal_getf((void *)0x14403020, 0, 0x1) != 0x0);
+		while (pwrcal_getf((void *)0x14443010, 0, 0x1) != 0x0);
+		while (pwrcal_getf((void *)0x1444B010, 0, 0x1) != 0x0);
+#endif
+	}
+
+	pwrcal_setf(PMU_CLKRUN_CMU_ISP_SYS_PWR_REG, 0, 0x1, 0x0);
+	pwrcal_setf(PMU_CLKSTOP_CMU_ISP_SYS_PWR_REG, 0, 0x1, 0x0);
+	pwrcal_setf(PMU_DISABLE_PLL_CMU_ISP_SYS_PWR_REG, 0, 0x1, 0x0);
+	pwrcal_setf(PMU_RESET_LOGIC_ISP_SYS_PWR_REG, 0, 0x1, 0x0);
+	pwrcal_setf(PMU_RESET_CMU_ISP_SYS_PWR_REG, 0, 0x1, 0x0);
+}
+
+static void mfcmscl_prev(int enable)
+{
+	if (enable == 0) {
+		pwrcal_setf(CLK_ENABLE_CLK_MFCMSCL_MSCL, 0, 0x1D, 0x1D);
+		pwrcal_setf(CLK_ENABLE_CLK_MFCMSCL_APB, 0, 0x1, 0x1);
+		pwrcal_setf(CLK_ENABLE_CLK_MFCMSCL_MFC, 0, 0x1, 0x1);
+	}
+
+	pwrcal_setf(PMU_CLKRUN_CMU_MFCMSCL_SYS_PWR_REG, 0, 0x1, 0x0);
+	pwrcal_setf(PMU_CLKSTOP_CMU_MFCMSCL_SYS_PWR_REG, 0, 0x1, 0x0);
+	pwrcal_setf(PMU_DISABLE_PLL_CMU_MFCMSCL_SYS_PWR_REG, 0, 0x1, 0x0);
+	pwrcal_setf(PMU_RESET_LOGIC_MFCMSCL_SYS_PWR_REG, 0, 0x1, 0x0);
+	pwrcal_setf(PMU_RESET_CMU_MFCMSCL_SYS_PWR_REG, 0, 0x1, 0x0);
+
+}
+
+static void dispaud_post(int enable)
+{
+	if (enable == 1) {
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU));
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP));
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS));
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP));
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_EXT2AUD_BCK_gpio_I2S));
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_BT_IN));
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK));
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_FM_IN));
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK));
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_ECLK));
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK));
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD));
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI));
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP));
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI));
+
+		/*non used disable*/
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_VPP));
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM1_IPCLKPORT_I_TXBYTECLKHS));
+		pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM1_IPCLKPORT_I_RXCLKESC0));
+	}
+}
+
+static void g3d_post(int enable)
+{
+	if (enable == 1) {
+		pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK));
+		pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK));
+		pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_ACLK));
+		pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK));
+		pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK));
+		pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM));
+		pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK));
+		pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_PCLK));
+	}
+}
+
+static void isp_post(int enable)
+{
+	if (enable == 1) {
+		pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD_PPMU));
+		pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD));
+		pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM));
+		pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM_HALF));
+		pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA));
+
+		/*non used disable*/
+		pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISP));
+	}
+}
+
+static void mfcmscl_post(int enable)
+{
+	if (enable == 1) {
+		pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_PPMU));
+		pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_D));
+		pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL));
+		pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI));
+		pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_POLY));
+		pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_JPEG));
+		pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC));
+	}
+}
+
+static void dispaud_config(int enable)
+{
+	pwrcal_setf(PMU_DISPAUD_OPTION, 0, 0x3, 0x2);
+	pwrcal_setf(PMU_PAD_RETENTION_AUD_OPTION, 0, 0xFFFFFFFF, 0x10000000);
+}
+
+static void g3d_config(int enable)
+{
+	pwrcal_setf(PMU_G3D_OPTION, 0, 0x1, 0x1);
+	pwrcal_setf(PMU_G3D_DURATION0, 4, 0xFF, 0x0);
+}
+
+static void isp_config(int enable)
+{
+	pwrcal_setf(PMU_ISP_OPTION, 0, 0x3, 0x2);
+}
+
+static void mfcmscl_config(int enable)
+{
+	pwrcal_setf(PMU_MFCMSCL_OPTION, 0, 0x3, 0x2);
+}
+
+BLKPWR(blkpwr_dispaud, PMU_DISPAUD_CONFIGURATION, 0, 0xF, PMU_DISPAUD_STATUS, 0, 0xF, dispaud_config, dispaud_prev, dispaud_post);
+BLKPWR(blkpwr_g3d, PMU_G3D_CONFIGURATION, 0, 0xF, PMU_G3D_STATUS, 0, 0xF, g3d_config, g3d_prev, g3d_post);
+BLKPWR(blkpwr_isp, PMU_ISP_CONFIGURATION, 0, 0xF, PMU_ISP_STATUS, 0, 0xF, isp_config, isp_prev, isp_post);
+BLKPWR(blkpwr_mfcmscl, PMU_MFCMSCL_CONFIGURATION, 0, 0xF, PMU_MFCMSCL_STATUS, 0, 0xF, mfcmscl_config, mfcmscl_prev, mfcmscl_post);
+
+
+struct cal_pd *pwrcal_blkpwr_list[4];
+unsigned int pwrcal_blkpwr_size = 4;
+
+static int blkpwr_init(void)
+{
+	pwrcal_blkpwr_list[0] = &blkpwr_blkpwr_dispaud;
+	pwrcal_blkpwr_list[1] = &blkpwr_blkpwr_g3d;
+	pwrcal_blkpwr_list[2] = &blkpwr_blkpwr_isp;
+	pwrcal_blkpwr_list[3] = &blkpwr_blkpwr_mfcmscl;
+
+	return 0;
+}
+
+struct cal_pd_ops cal_pd_ops = {
+	.pd_control = blkpwr_control,
+	.pd_status = blkpwr_status,
+	.pd_init = blkpwr_init,
+};

drivers/soc/samsung/pwrcal/S5E7870/S5E7870-rae.c

@@ -0,0 +1,40 @@
+#include "../pwrcal-rae.h"
+#include "S5E7870-sfrbase.h"
+
+#ifdef PWRCAL_TARGET_LINUX
+
+struct v2p_sfr v2psfrmap[] = {
+	DEFINE_V2P(CMU_CPUCL0_BASE,	0x10900000),
+	DEFINE_V2P(CMU_CPUCL1_BASE,	0x10800000),
+	DEFINE_V2P(CMU_FSYS_BASE,	0x13730000),
+	DEFINE_V2P(CMU_G3D_BASE,	0x11460000),
+	DEFINE_V2P(CMU_ISP_BASE,	0x144D0000),
+	DEFINE_V2P(CMU_MFCMSCL_BASE,	0x12CB0000),
+	DEFINE_V2P(CMU_MIF_BASE,	0x10460000),
+	DEFINE_V2P(CMU_PERI_BASE,	0x101F0000),
+	DEFINE_V2P(CMU_DISPAUD_BASE,	0x148D0000),
+
+	DEFINE_V2P(PMU_CPUCL0_BASE,	0x10920000),
+	DEFINE_V2P(PMU_CPUCL1_BASE,	0x10820000),
+	DEFINE_V2P(PMU_FSYS_BASE,	0x13740000),
+	DEFINE_V2P(PMU_G3D_BASE,	0x11470000),
+	DEFINE_V2P(PMU_ISP_BASE,	0x144E0000),
+	DEFINE_V2P(PMU_MFCMSCL_BASE,	0x12CC0000),
+	DEFINE_V2P(PMU_MIF_BASE,	0x10470000),
+	DEFINE_V2P(PMU_PERI_BASE,	0x101E0000),
+	DEFINE_V2P(PMU_ALIVE_BASE,	0x10480000),
+
+	DEFINE_V2P(DREX0_BASE,	0x10400000),
+	DEFINE_V2P(DREX0_PF_BASE,	0x10410000),
+	DEFINE_V2P(DREX0_SECURE_BASE,	0x10420000),
+	DEFINE_V2P(DREX0_PF_SECURE_BASE,	0x10430000),
+	DEFINE_V2P(DREXPHY0_BASE,	0x10440000),
+
+	DEFINE_V2P(SYSREG_CPUCL0_BASE,	0x10910000),
+	DEFINE_V2P(SYSREG_CPUCL1_BASE,	0x10810000),
+	DEFINE_V2P(SYSREG_G3D_BASE,	0x11450000),
+};
+
+int num_of_v2psfrmap = sizeof(v2psfrmap) / sizeof(v2psfrmap[0]);
+void *spinlock_enable_offset = (void *)PMU_CPUCL0_BASE;
+#endif

drivers/soc/samsung/pwrcal/S5E7870/S5E7870-sfrbase.h

@@ -0,0 +1,75 @@
+#ifndef __EXYNOS7870_SFRBASE_H__
+#define __EXYNOS7870_SFRBASE_H__
+
+#include "../pwrcal-env.h"
+
+#ifdef PWRCAL_TARGET_FW
+
+#define CMU_CPUCL0_BASE		0x10900000
+#define CMU_CPUCL1_BASE		0x10800000
+#define CMU_FSYS_BASE		0x13730000
+#define CMU_G3D_BASE		0x11460000
+#define CMU_ISP_BASE		0x144D0000
+#define CMU_MFCMSCL_BASE	0x12CB0000
+#define CMU_MIF_BASE		0x10460000
+#define CMU_PERI_BASE		0x101F0000
+#define CMU_DISPAUD_BASE	0x148D0000
+
+#define PMU_CPUCL0_BASE		0x10920000
+#define PMU_CPUCL1_BASE		0x10820000
+#define PMU_FSYS_BASE		0x13740000
+#define PMU_G3D_BASE		0x11470000
+#define PMU_ISP_BASE		0x144E0000
+#define PMU_MFCMSCL_BASE	0x12CC0000
+#define PMU_MIF_BASE		0x10470000
+#define PMU_PERI_BASE		0x101E0000
+#define PMU_ALIVE_BASE		0x10480000
+
+#define DREX0_BASE			0x10400000
+#define DREX0_PF_BASE		0x10410000
+#define DREX0_SECURE_BASE	0x10420000
+#define DREX0_PF_SECURE_BASE	0x10430000
+#define DREXPHY0_BASE		0x10440000
+
+#define SYSREG_CPUCL0_BASE	0x10910000
+#define SYSREG_CPUCL1_BASE	0x10810000
+#define SYSREG_G3D_BASE	0x11450000
+
+#endif
+
+
+#ifdef PWRCAL_TARGET_LINUX
+
+#define CMU_CPUCL0_BASE	0x00010000
+#define CMU_CPUCL1_BASE	0x00020000
+#define CMU_FSYS_BASE	0x00030000
+#define CMU_G3D_BASE	0x00040000
+#define CMU_ISP_BASE	0x00050000
+#define CMU_MFCMSCL_BASE	0x00060000
+#define CMU_MIF_BASE	0x00070000
+#define CMU_PERI_BASE	0x00080000
+#define CMU_DISPAUD_BASE	0x00090000
+
+#define PMU_CPUCL0_BASE	0x00100000
+#define PMU_CPUCL1_BASE	0x00110000
+#define PMU_FSYS_BASE	0x00120000
+#define PMU_G3D_BASE	0x00130000
+#define PMU_ISP_BASE	0x00140000
+#define PMU_MFCMSCL_BASE	0x00150000
+#define PMU_MIF_BASE	0x00160000
+#define PMU_PERI_BASE	0x00170000
+#define PMU_ALIVE_BASE	0x00180000
+
+#define DREX0_BASE	0x00190000
+#define DREX0_PF_BASE	0x00200000
+#define DREX0_SECURE_BASE	0x00210000
+#define DREX0_PF_SECURE_BASE	0x00220000
+#define DREXPHY0_BASE	0x00230000
+
+#define SYSREG_CPUCL0_BASE	0x00240000
+#define SYSREG_CPUCL1_BASE	0x00250000
+#define SYSREG_G3D_BASE	0X00260000
+
+#endif
+
+#endif

drivers/soc/samsung/pwrcal/S5E7870/S5E7870-sysreg.h

@@ -0,0 +1,13 @@
+#ifndef __EXYNOS7870_H__
+#define __EXYNOS7870_H__
+
+#include "S5E7870-sfrbase.h"
+
+#define CPUCL0_EMA_CON		((void *)(SYSREG_CPUCL0_BASE + 0x0330))
+#define CPUCL0_EMA_REG1		((void *)(SYSREG_CPUCL0_BASE + 0x0004))
+#define CPUCL1_EMA_CON		((void *)(SYSREG_CPUCL1_BASE + 0x0330))
+#define CPUCL1_EMA_REG1		((void *)(SYSREG_CPUCL1_BASE + 0x0004))
+#define GPU_EMA_RF2_UHD_CON	((void *)(SYSREG_G3D_BASE + 0x0318))
+#define CAM_EMA_RF2_UHD_CON	((void *)(SYSREG_ISP_BASE + 0x0318))
+#define CAM_EMA_RF2_HS_CON	((void *)(SYSREG_ISP_BASE + 0x2718))
+#endif

drivers/soc/samsung/pwrcal/S5E7870/S5E7870-vclk-internal.h

@@ -0,0 +1,168 @@
+#ifndef __EXYNOS7870_VCLKS_H__
+#define __EXYNOS7870_VCLKS_H__
+
+#include "../pwrcal-vclk.h"
+#include "../pwrcal-pmu.h"
+#include "S5E7870-vclk.h"
+
+M1D1G1_EXTERN(sclk_decon_vclk)
+M1D1G1_EXTERN(sclk_decon_vclk_local)
+M1D1G1_EXTERN(sclk_decon_eclk)
+M1D1G1_EXTERN(sclk_decon_eclk_local)
+M1D1G1_EXTERN(sclk_mmc0)
+M1D1G1_EXTERN(sclk_mmc1)
+M1D1G1_EXTERN(sclk_mmc2)
+M1D1G1_EXTERN(sclk_ufsunipro)
+M1D1G1_EXTERN(sclk_ufsunipro_cfg)
+M1D1G1_EXTERN(sclk_usb20drd)
+M1D1G1_EXTERN(sclk_uart_sensor)
+M1D1G1_EXTERN(sclk_uart_btwififm)
+M1D1G1_EXTERN(sclk_uart_debug)
+M1D1G1_EXTERN(sclk_spi_frontfrom)
+M1D1G1_EXTERN(sclk_spi_rearfrom)
+M1D1G1_EXTERN(sclk_spi_ese)
+M1D1G1_EXTERN(sclk_spi_voiceprocessor)
+M1D1G1_EXTERN(sclk_spi_sensorhub)
+M1D1G1_EXTERN(sclk_isp_sensor0)
+M1D1G1_EXTERN(sclk_isp_sensor1)
+M1D1G1_EXTERN(sclk_isp_sensor2)
+
+PXMXDX_EXTERN(pxmxdx_top)
+PXMXDX_EXTERN(pxmxdx_disp)
+PXMXDX_EXTERN(pxmxdx_mfcmscl)
+PXMXDX_EXTERN(pxmxdx_isp_vra)
+PXMXDX_EXTERN(pxmxdx_isp_cam)
+PXMXDX_EXTERN(pxmxdx_isp_isp)
+
+P1_EXTERN(p1_disp_pll)
+P1_EXTERN(p1_aud_pll)
+P1_EXTERN(p1_usb_pll)
+P1_EXTERN(p1_isp_pll)
+
+M1_EXTERN(m1_dummy)
+
+D1_EXTERN(d1_dispaud_mi2s)
+D1_EXTERN(d1_dispaud_mixer)
+
+GRPGATE_EXTERN(gate_cpucl0_ppmu)
+GRPGATE_EXTERN(gate_cpucl0_bts)
+GRPGATE_EXTERN(gate_cpucll_ppmu)
+GRPGATE_EXTERN(gate_cpucll_bts)
+GRPGATE_EXTERN(gate_mfcmscl_sysmmu_mscl)
+GRPGATE_EXTERN(gate_mfcmscl_sysmmu_mfc)
+GRPGATE_EXTERN(gate_mfcmscl_ppmu)
+GRPGATE_EXTERN(gate_mfcmscl_bts)
+GRPGATE_EXTERN(gate_mfcmscl_common)
+GRPGATE_EXTERN(gate_mfcmscl_common_mscl)
+GRPGATE_EXTERN(gate_mfcmscl_mscl_bi)
+GRPGATE_EXTERN(gate_mfcmscl_mscl_poly)
+GRPGATE_EXTERN(gate_mfcmscl_jpeg)
+GRPGATE_EXTERN(gate_mfcmscl_mfc)
+GRPGATE_EXTERN(gate_g3d_common)
+GRPGATE_EXTERN(gate_g3d_sysmmu)
+GRPGATE_EXTERN(gate_g3d_ppmu)
+GRPGATE_EXTERN(gate_g3d_bts)
+GRPGATE_EXTERN(gate_g3d_g3d)
+GRPGATE_EXTERN(gate_peri_peris0)
+GRPGATE_EXTERN(gate_peri_peric0)
+GRPGATE_EXTERN(gate_peri_peric1)
+GRPGATE_EXTERN(gate_peri_pwm_motor)
+GRPGATE_EXTERN(gate_peri_sclk_pwm_motor)
+GRPGATE_EXTERN(gate_peri_mct)
+GRPGATE_EXTERN(gate_peri_i2c_sensor2)
+GRPGATE_EXTERN(gate_peri_i2c_sensor1)
+GRPGATE_EXTERN(gate_peri_i2c_tsp)
+GRPGATE_EXTERN(gate_peri_i2c_touchkey)
+GRPGATE_EXTERN(gate_peri_i2c_fuelgauge)
+GRPGATE_EXTERN(gate_peri_i2c_spkamp)
+GRPGATE_EXTERN(gate_peri_i2c_nfc)
+GRPGATE_EXTERN(gate_peri_i2c_muic)
+GRPGATE_EXTERN(gate_peri_i2c_ifpmic)
+GRPGATE_EXTERN(gate_peri_hsi2c_frontcam)
+GRPGATE_EXTERN(gate_peri_hsi2c_maincam)
+GRPGATE_EXTERN(gate_peri_hsi2c_depthcam)
+GRPGATE_EXTERN(gate_peri_hsi2c_frontsensor)
+GRPGATE_EXTERN(gate_peri_hsi2c_rearaf)
+GRPGATE_EXTERN(gate_peri_hsi2c_rearsensor)
+GRPGATE_EXTERN(gate_peri_gpio_touch)
+GRPGATE_EXTERN(gate_peri_gpio_top)
+GRPGATE_EXTERN(gate_peri_gpio_nfc)
+GRPGATE_EXTERN(gate_peri_gpio_ese)
+GRPGATE_EXTERN(gate_peri_wdt_cpucl1)
+GRPGATE_EXTERN(gate_peri_wdt_cpucl0)
+GRPGATE_EXTERN(gate_peri_uart_debug)
+GRPGATE_EXTERN(gate_peri_uart_btwififm)
+GRPGATE_EXTERN(gate_peri_uart_sensor)
+GRPGATE_EXTERN(gate_peri_tmu_g3d)
+GRPGATE_EXTERN(gate_peri_tmu_cpucl1)
+GRPGATE_EXTERN(gate_peri_tmu_cpucl0)
+GRPGATE_EXTERN(gate_peri_spi_sensorhub)
+GRPGATE_EXTERN(gate_peri_spi_voiceprocessor)
+GRPGATE_EXTERN(gate_peri_spi_ese)
+GRPGATE_EXTERN(gate_peri_spi_rearfrom)
+GRPGATE_EXTERN(gate_peri_spi_frontfrom)
+GRPGATE_EXTERN(gate_peri_gpio_alive)
+GRPGATE_EXTERN(gate_peri_chipid)
+GRPGATE_EXTERN(gate_peri_otp_con_top)
+GRPGATE_EXTERN(gate_peri_rtc_alive)
+GRPGATE_EXTERN(gate_peri_rtc_top)
+GRPGATE_EXTERN(gate_fsys_common)
+GRPGATE_EXTERN(gate_fsys_common_sub1)
+GRPGATE_EXTERN(gate_fsys_common_sub2)
+GRPGATE_EXTERN(gate_fsys_sysmmu)
+GRPGATE_EXTERN(gate_fsys_ppmu)
+GRPGATE_EXTERN(gate_fsys_bts)
+GRPGATE_EXTERN(gate_fsys_usb20drd)
+GRPGATE_EXTERN(gate_fsys_mmc0)
+GRPGATE_EXTERN(gate_fsys_sclk_mmc0)
+GRPGATE_EXTERN(gate_fsys_mmc1)
+GRPGATE_EXTERN(gate_fsys_sclk_mmc1)
+GRPGATE_EXTERN(gate_fsys_mmc2)
+GRPGATE_EXTERN(gate_fsys_sclk_mmc2)
+GRPGATE_EXTERN(gate_fsys_sss)
+GRPGATE_EXTERN(gate_fsys_rtic)
+GRPGATE_EXTERN(gate_fsys_pdma0)
+GRPGATE_EXTERN(gate_fsys_pdma1)
+GRPGATE_EXTERN(gate_fsys_sromc)
+GRPGATE_EXTERN(gate_dispaud_disp)
+GRPGATE_EXTERN(gate_dispaud_aud)
+GRPGATE_EXTERN(gate_dispaud_sysmmu)
+GRPGATE_EXTERN(gate_dispaud_ppmu)
+GRPGATE_EXTERN(gate_dispaud_bts)
+GRPGATE_EXTERN(gate_dispaud_decon)
+GRPGATE_EXTERN(gate_dispaud_dsim0)
+GRPGATE_EXTERN(gate_dispaud_mixer)
+GRPGATE_EXTERN(gate_dispaud_mi2s_aud)
+GRPGATE_EXTERN(gate_dispaud_mi2s_amp)
+GRPGATE_EXTERN(gate_isp_common)
+GRPGATE_EXTERN(gate_isp_sysmmu)
+GRPGATE_EXTERN(gate_isp_ppmu)
+GRPGATE_EXTERN(gate_isp_bts)
+GRPGATE_EXTERN(gate_isp_cam)
+GRPGATE_EXTERN(gate_isp_isp)
+GRPGATE_EXTERN(gate_isp_vra)
+GRPGATE_EXTERN(gate_mif_adcif)
+GRPGATE_EXTERN(gate_mif_hsi2c_mif)
+GRPGATE_EXTERN(sclk_uart0)
+
+
+
+UMUX_EXTERN(umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user)
+UMUX_EXTERN(umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user)
+UMUX_EXTERN(umux_fsys_clkphy_fsys_usb20drd_phyclock_user)
+UMUX_EXTERN(umux_fsys_clkphy_fsys_ufs_tx0_symbol_user)
+UMUX_EXTERN(umux_fsys_clkphy_fsys_ufs_rx0_symbol_user)
+UMUX_EXTERN(umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user)
+UMUX_EXTERN(umux_isp_clkphy_isp_s_rxbyteclkhs0_s4s_user)
+
+
+DFS_EXTERN(dvfs_cpucl0)
+DFS_EXTERN(dvfs_cpucl1)
+DFS_EXTERN(dvfs_g3d)
+DFS_EXTERN(dvfs_mif)
+DFS_EXTERN(dvfs_int)
+DFS_EXTERN(dvfs_disp)
+DFS_EXTERN(dvfs_cam)
+
+
+#endif

drivers/soc/samsung/pwrcal/S5E7870/S5E7870-vclk.c

@@ -0,0 +1,970 @@
+#include "../pwrcal-pmu.h"
+#include "../pwrcal-clk.h"
+#include "../pwrcal-rae.h"
+#include "S5E7870-cmu.h"
+#include "S5E7870-cmusfr.h"
+#include "S5E7870-vclk.h"
+#include "S5E7870-vclk-internal.h"
+
+struct pwrcal_vclk_grpgate *vclk_grpgate_list[num_of_grpgate];
+struct pwrcal_vclk_m1d1g1 *vclk_m1d1g1_list[num_of_m1d1g1];
+struct pwrcal_vclk_p1 *vclk_p1_list[num_of_p1];
+struct pwrcal_vclk_m1 *vclk_m1_list[num_of_m1];
+struct pwrcal_vclk_d1 *vclk_d1_list[num_of_d1];
+struct pwrcal_vclk_pxmxdx *vclk_pxmxdx_list[num_of_pxmxdx];
+struct pwrcal_vclk_umux *vclk_umux_list[num_of_umux];
+struct pwrcal_vclk_dfs *vclk_dfs_list[num_of_dfs];
+unsigned int vclk_grpgate_list_size = num_of_grpgate;
+unsigned int vclk_m1d1g1_list_size = num_of_m1d1g1;
+unsigned int vclk_p1_list_size = num_of_p1;
+unsigned int vclk_m1_list_size = num_of_m1;
+unsigned int vclk_d1_list_size = num_of_d1;
+unsigned int vclk_pxmxdx_list_size = num_of_pxmxdx;
+unsigned int vclk_umux_list_size = num_of_umux;
+unsigned int vclk_dfs_list_size = num_of_dfs;
+
+
+#define ADD_LIST(to, x)		to[x & 0xFFFF] = &(vclk_##x)
+
+static struct pwrcal_clk_set pxmxdx_top_grp[] = {
+	{CLK_NONE,				0,	0},
+};
+static struct pwrcal_clk_set pxmxdx_disp_grp[] = {
+	{CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER), 1, 0},
+	{CLK(DISPAUD_DIV_CLK_DISPAUD_APB), 1, -1},
+	{CLK(MIF_MUXGATE_CLKCMU_DISPAUD_BUS),	1,	0},
+	{CLK_NONE,				0,	0},
+};
+static struct pwrcal_clk_set pxmxdx_mfcmscl_grp[] = {
+	{CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER), 1, 0},
+	{CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER), 1, 0},
+	{CLK(MFCMSCL_DIV_CLK_MFCMSCL_APB), 2, -1},
+	{CLK(MIF_MUXGATE_CLKCMU_MFCMSCL_MSCL),	1,	0},
+	{CLK(MIF_MUXGATE_CLKCMU_MFCMSCL_MFC),	1,	0},
+	{CLK_NONE,				0,	0},
+};
+static struct pwrcal_clk_set pxmxdx_isp_vra_grp[] = {
+	{CLK(ISP_MUX_CLKCMU_ISP_VRA_USER), 1, 0},
+	{CLK(ISP_DIV_CLK_ISP_APB), 3, -1},
+	{CLK(MIF_MUXGATE_CLKCMU_ISP_VRA),	1,	0},
+	{CLK_NONE,				0,	0},
+};
+static struct pwrcal_clk_set pxmxdx_isp_cam_grp[] = {
+	{CLK(ISP_MUX_CLKCMU_ISP_CAM_USER), 1, 0},
+	{CLK(ISP_DIV_CLK_ISP_CAM_HALF), 1, -1},
+	{CLK(MIF_MUXGATE_CLKCMU_ISP_CAM),	1,	0},
+	{CLK_NONE,				0,	0},
+};
+static struct pwrcal_clk_set pxmxdx_isp_isp_grp[] = {
+	{CLK(ISP_MUX_CLKCMU_ISP_ISP_USER), 1, 0},
+	{CLK(MIF_MUXGATE_CLKCMU_ISP_ISP),	1,	0},
+	{CLK_NONE,				0,	0},
+};
+
+PXMXDX(pxmxdx_top,	0,	pxmxdx_top_grp);
+PXMXDX(pxmxdx_disp,	dvfs_disp,	pxmxdx_disp_grp);
+PXMXDX(pxmxdx_mfcmscl,	0,	pxmxdx_mfcmscl_grp);
+PXMXDX(pxmxdx_isp_vra,	0,	pxmxdx_isp_vra_grp);
+PXMXDX(pxmxdx_isp_cam,	0,	pxmxdx_isp_cam_grp);
+PXMXDX(pxmxdx_isp_isp,	0,	pxmxdx_isp_isp_grp);
+
+P1(p1_disp_pll, 0, DISP_PLL);
+P1(p1_aud_pll, 0, AUD_PLL);
+P1(p1_usb_pll, 0, USB_PLL);
+P1(p1_isp_pll, 0, ISP_PLL);
+
+M1(m1_dummy, 0, 0);
+
+D1(d1_dispaud_mi2s, 0, DISPAUD_DIV_CLK_DISPAUD_MI2S);
+D1(d1_dispaud_mixer, 0, DISPAUD_DIV_CLK_DISPAUD_MIXER);
+
+
+M1D1G1(sclk_decon_vclk, 0, MIF_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK, MIF_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK, MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK, DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER);
+M1D1G1(sclk_decon_vclk_local, 0, DISPAUD_MUX_CLK_DISPAUD_DECON_INT_VCLK, DISPAUD_DIV_CLK_DISPAUD_DECON_INT_VCLK, DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK, 0);
+M1D1G1(sclk_decon_eclk, 0, MIF_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK, MIF_DIV_CLKCMU_DISPAUD_DECON_INT_ECLK, MIF_GATE_CLKCMU_DISPAUD_DECON_INT_ECLK, DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER);
+M1D1G1(sclk_decon_eclk_local, 0, DISPAUD_MUX_CLK_DISPAUD_DECON_INT_ECLK, DISPAUD_DIV_CLK_DISPAUD_DECON_INT_ECLK, DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_ECLK, 0);
+M1D1G1(sclk_mmc0, 0, MIF_MUX_CLKCMU_FSYS_MMC0, MIF_DIV_CLKCMU_FSYS_MMC0, MIF_GATE_CLKCMU_FSYS_MMC0, 0);
+M1D1G1(sclk_mmc1, 0, MIF_MUX_CLKCMU_FSYS_MMC1, MIF_DIV_CLKCMU_FSYS_MMC1, MIF_GATE_CLKCMU_FSYS_MMC1, 0);
+M1D1G1(sclk_mmc2, 0, MIF_MUX_CLKCMU_FSYS_MMC2, MIF_DIV_CLKCMU_FSYS_MMC2, MIF_GATE_CLKCMU_FSYS_MMC2, 0);
+M1D1G1(sclk_ufsunipro, 0, MIF_MUX_CLKCMU_FSYS_UFSUNIPRO, MIF_DIV_CLKCMU_FSYS_UFSUNIPRO, MIF_GATE_CLKCMU_FSYS_UFSUNIPRO, 0);
+M1D1G1(sclk_ufsunipro_cfg, 0, MIF_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG, MIF_DIV_CLKCMU_FSYS_UFSUNIPRO_CFG, MIF_GATE_CLKCMU_FSYS_UFSUNIPRO_CFG, 0);
+M1D1G1(sclk_usb20drd, 0, MIF_MUX_CLKCMU_FSYS_USB20DRD_REFCLK, MIF_DIV_CLKCMU_FSYS_USB20DRD_REFCLK, MIF_GATE_CLKCMU_FSYS_USB20DRD_REFCLK, 0);
+M1D1G1(sclk_uart_sensor, gate_peri_peric0, MIF_MUX_CLKCMU_PERI_UART_SENSOR, MIF_DIV_CLKCMU_PERI_UART_SENSOR, MIF_GATE_CLKCMU_PERI_UART_SENSOR, 0);
+M1D1G1(sclk_uart_btwififm, gate_peri_peric0, MIF_MUX_CLKCMU_PERI_UART_BTWIFIFM, MIF_DIV_CLKCMU_PERI_UART_BTWIFIFM, MIF_GATE_CLKCMU_PERI_UART_BTWIFIFM, 0);
+M1D1G1(sclk_uart_debug, gate_peri_peric0, MIF_MUX_CLKCMU_PERI_UART_DEBUG, MIF_DIV_CLKCMU_PERI_UART_DEBUG, MIF_GATE_CLKCMU_PERI_UART_DEBUG, 0);
+M1D1G1(sclk_spi_frontfrom, gate_peri_peric1, MIF_MUX_CLKCMU_PERI_SPI_FRONTFROM, MIF_DIV_CLKCMU_PERI_SPI_FRONTFROM, MIF_GATE_CLKCMU_PERI_SPI_FRONTFROM, 0);
+M1D1G1(sclk_spi_rearfrom, gate_peri_peric1, MIF_MUX_CLKCMU_PERI_SPI_REARFROM, MIF_DIV_CLKCMU_PERI_SPI_REARFROM, MIF_GATE_CLKCMU_PERI_SPI_REARFROM, 0);
+M1D1G1(sclk_spi_ese, gate_peri_peris0, MIF_MUX_CLKCMU_PERI_SPI_ESE, MIF_DIV_CLKCMU_PERI_SPI_ESE, MIF_GATE_CLKCMU_PERI_SPI_ESE, 0);
+M1D1G1(sclk_spi_voiceprocessor, gate_peri_peric1, MIF_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR, MIF_DIV_CLKCMU_PERI_SPI_VOICEPROCESSOR, MIF_GATE_CLKCMU_PERI_SPI_VOICEPROCESSOR, 0);
+M1D1G1(sclk_spi_sensorhub, gate_peri_peric1, MIF_MUX_CLKCMU_PERI_SPI_SENSORHUB, MIF_DIV_CLKCMU_PERI_SPI_SENSORHUB, MIF_GATE_CLKCMU_PERI_SPI_SENSORHUB, 0);
+M1D1G1(sclk_isp_sensor0, 0, MIF_MUX_CLKCMU_ISP_SENSOR0, MIF_DIV_CLKCMU_ISP_SENSOR0, MIF_GATE_CLKCMU_ISP_SENSOR0, 0);
+M1D1G1(sclk_isp_sensor1, 0, MIF_MUX_CLKCMU_ISP_SENSOR1, MIF_DIV_CLKCMU_ISP_SENSOR1, MIF_GATE_CLKCMU_ISP_SENSOR1, 0);
+M1D1G1(sclk_isp_sensor2, 0, MIF_MUX_CLKCMU_ISP_SENSOR2, MIF_DIV_CLKCMU_ISP_SENSOR2, MIF_GATE_CLKCMU_ISP_SENSOR2, 0);
+
+
+
+
+static struct pwrcal_clk *gategrp_cpucl0_ppmu[] = {
+	CLK(CPUCL0_DIV_CLK_CPUCL0_ACLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_cpucl0_bts[] = {
+	CLK(CPUCL0_DIV_CLK_CPUCL0_ACLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_cpucl1_ppmu[] = {
+	CLK(CPUCL1_DIV_CLK_CPUCL1_ACLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_cpucl1_bts[] = {
+	CLK(CPUCL1_DIV_CLK_CPUCL1_ACLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mfcmscl_sysmmu_mscl[] = {
+	CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mfcmscl_sysmmu_mfc[] = {
+	CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mfcmscl_ppmu[] = {
+	CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mfcmscl_bts[] = {
+	CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mfcmscl_common[] = {
+	CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_PPMU),
+	CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mfcmscl_common_mscl[] = {
+	CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_D),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mfcmscl_mscl_bi[] = {
+	CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mfcmscl_mscl_poly[] = {
+	CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_POLY),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mfcmscl_jpeg[] = {
+	CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_JPEG),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mfcmscl_mfc[] = {
+	CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_g3d_common[] = {
+	CLK(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK),
+	CLK(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK),
+	CLK(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_ACLK),
+	CLK(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_g3d_sysmmu[] = {
+	CLK(G3D_DIV_CLK_G3D_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_g3d_ppmu[] = {
+	CLK(G3D_DIV_CLK_G3D_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_g3d_bts[] = {
+	CLK(G3D_DIV_CLK_G3D_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_g3d_g3d[] = {
+	CLK(G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK),
+	CLK(G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK),
+	CLK(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM),
+	CLK(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_peris0[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_peric0[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC0_IPCLKPORT_HCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_peric1[] = {
+/*	CLK(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC1_IPCLKPORT_HCLK),*/
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_pwm_motor[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_sclk_pwm_motor[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_OSCCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_mct[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_MCT_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_i2c_sensor2[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_I2C_SENSOR2_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_i2c_sensor1[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_I2C_SENSOR1_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_i2c_tsp[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_I2C_TSP_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_i2c_touchkey[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_I2C_TOUCHKEY_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_i2c_fuelgauge[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_I2C_FUELGAUGE_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_i2c_spkamp[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_I2C_SPKAMP_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_i2c_nfc[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_I2C_NFC_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_i2c_muic[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_I2C_MUIC_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_i2c_ifpmic[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_I2C_IFPMIC_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_hsi2c_frontcam[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTCAM_IPCLKPORT_iPCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_hsi2c_maincam[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_HSI2C_MAINCAM_IPCLKPORT_iPCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_hsi2c_depthcam[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_HSI2C_DEPTHCAM_IPCLKPORT_iPCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_hsi2c_frontsensor[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTSENSOR_IPCLKPORT_iPCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_hsi2c_rearaf[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_HSI2C_REARAF_IPCLKPORT_iPCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_hsi2c_rearsensor[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_HSI2C_REARSENSOR_IPCLKPORT_iPCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_gpio_touch[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_GPIO_TOUCH_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_gpio_top[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_GPIO_TOP_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_gpio_nfc[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_GPIO_NFC_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_gpio_ese[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_GPIO_ESE_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_wdt_cpucl1[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_WDT_CPUCL1_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_wdt_cpucl0[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_WDT_CPUCL0_IPCLKPORT_PCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_uart_debug[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_PCLK),
+	CLK(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_EXT_UCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_uart_btwififm[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_UART_BTWIFIFM_IPCLKPORT_PCLK),
+	CLK(PERI_GATE_CLK_PERI_UID_UART_BTWIFIFM_IPCLKPORT_EXT_UCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_uart_sensor[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_PCLK),
+	CLK(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_EXT_UCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_tmu_g3d[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_G3D_IPCLKPORT_PCLK),
+	CLK(PERI_GATE_CLK_PERI_UID_TMU_G3D_IPCLKPORT_I_CLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_tmu_cpucl1[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL1_IPCLKPORT_PCLK),
+	CLK(PERI_GATE_CLK_PERI_UID_TMU_CPUCL1_IPCLKPORT_I_CLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_tmu_cpucl0[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL0_IPCLKPORT_PCLK),
+	CLK(PERI_GATE_CLK_PERI_UID_TMU_CPUCL0_IPCLKPORT_I_CLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_spi_sensorhub[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_SPI_SENSORHUB_IPCLKPORT_PCLK),
+	CLK(PERI_GATE_CLK_PERI_UID_SPI_SENSORHUB_IPCLKPORT_SPI_EXT_CLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_spi_voiceprocessor[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_SPI_VOICEPROCESSOR_IPCLKPORT_PCLK),
+	CLK(PERI_GATE_CLK_PERI_UID_SPI_VOICEPROCESSOR_IPCLKPORT_SPI_EXT_CLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_spi_ese[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_PCLK),
+	CLK(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_SPI_EXT_CLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_spi_rearfrom[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_PCLK),
+	CLK(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_SPI_EXT_CLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_spi_frontfrom[] = {
+	CLK(PERI_GATE_CLK_PERI_UID_SPI_FRONTFROM_IPCLKPORT_PCLK),
+	CLK(PERI_GATE_CLK_PERI_UID_SPI_FRONTFROM_IPCLKPORT_SPI_EXT_CLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_gpio_alive[] = {
+	CLK(MIF_DIV_CLKCMU_PERI_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_chipid[] = {
+	CLK(MIF_DIV_CLKCMU_PERI_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_otp_con_top[] = {
+	CLK(MIF_DIV_CLKCMU_PERI_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_rtc_alive[] = {
+	CLK(MIF_DIV_CLKCMU_PERI_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_peri_rtc_top[] = {
+	CLK(MIF_DIV_CLKCMU_PERI_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_common[] = {
+	CLK(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK),
+	CLK(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_common_sub1[] = {
+	CLK(FSYS_GATE_CLK_FSYS_UID_UPSIZER_BUS1_FSYS_IPCLKPORT_aclk),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_common_sub2[] = {
+	CLK(FSYS_GATE_CLK_FSYS_UID_BUSP3_FSYS_IPCLKPORT_HCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_sysmmu[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_ppmu[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_bts[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_usb20drd[] = {
+	CLK(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HCLK_USB20_CTRL),
+	CLK(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_HSDRD),
+	CLK(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_ref_clk),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_mmc0[] = {
+	CLK(FSYS_GATE_CLK_FSYS_UID_MMC0_IPCLKPORT_I_ACLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_sclk_mmc0[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_MMC0),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_mmc1[] = {
+	CLK(FSYS_GATE_CLK_FSYS_UID_MMC1_IPCLKPORT_I_ACLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_sclk_mmc1[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_MMC1),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_mmc2[] = {
+	CLK(FSYS_GATE_CLK_FSYS_UID_MMC2_IPCLKPORT_I_ACLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_sclk_mmc2[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_MMC2),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_sss[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_rtic[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_pdma0[] = {
+	CLK(FSYS_GATE_CLK_FSYS_UID_PDMA0_IPCLKPORT_ACLK_PDMA0),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_pdma1[] = {
+	CLK(MIF_DIV_CLKCMU_FSYS_BUS),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_fsys_sromc[] = {
+	CLK(FSYS_GATE_CLK_FSYS_UID_SROMC_IPCLKPORT_HCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_disp[] = {
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU),
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP),
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS),
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_aud[] = {
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_EXT2AUD_BCK_gpio_I2S),
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_BT_IN),
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK),
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_FM_IN),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_sysmmu[] = {
+	CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_ppmu[] = {
+	CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_bts[] = {
+	CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_decon[] = {
+	CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK),
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_ECLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_dsim0[] = {
+	CLK(DISPAUD_DIV_CLK_DISPAUD_APB),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_mixer[] = {
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_mi2s_aud[] = {
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD),
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_dispaud_mi2s_amp[] = {
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP),
+	CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_isp_common[] = {
+	CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD_PPMU),
+	CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD),
+	CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_isp_sysmmu[] = {
+	CLK(ISP_MUX_CLK_ISP_ISPD),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_isp_ppmu[] = {
+	CLK(ISP_MUX_CLK_ISP_ISPD),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_isp_bts[] = {
+	CLK(ISP_MUX_CLK_ISP_ISPD),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_isp_cam[] = {
+	CLK(ISP_MUX_CLK_ISP_CAM),
+	CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM_HALF),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_isp_isp[] = {
+	CLK(ISP_MUX_CLK_ISP_ISP),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_isp_vra[] = {
+	CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mif_adcif[] = {
+	CLK(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_I_OSC_SYS),
+	CLK(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1),
+	CLK(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_mif_hsi2c_mif[] = {
+	CLK(MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_CP_IPCLKPORT_PCLKS),
+	CLK(MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_AP_IPCLKPORT_PCLKS),
+	CLK(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C),
+	CLK(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C_BAT_1),
+	CLK(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C_BAT_0),
+	CLK(MIF_GATE_CLK_MIF_UID_HSI2C_MIF_IPCLKPORT_iTCLK),
+	CLK(MIF_GATE_CLK_MIF_UID_HSI2C_MIF_IPCLKPORT_iPCLK),
+	CLK(MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_CP_IPCLKPORT_PCLKM),
+	CLK(MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_AP_IPCLKPORT_PCLKM),
+	CLK_NONE,
+};
+static struct pwrcal_clk *gategrp_sclk_uart0[] = {
+	CLK(FIN_TEMP),
+	CLK_NONE,
+};
+
+
+
+
+GRPGATE(gate_cpucl0_ppmu, 0, gategrp_cpucl0_ppmu);
+GRPGATE(gate_cpucl0_bts, 0, gategrp_cpucl0_bts);
+GRPGATE(gate_cpucll_ppmu, 0, gategrp_cpucl1_ppmu);
+GRPGATE(gate_cpucll_bts, 0, gategrp_cpucl1_bts);
+
+GRPGATE(gate_mfcmscl_common, pxmxdx_mfcmscl, gategrp_mfcmscl_common);
+GRPGATE(gate_mfcmscl_common_mscl, gate_mfcmscl_common, gategrp_mfcmscl_common_mscl);
+GRPGATE(gate_mfcmscl_sysmmu_mfc, gate_mfcmscl_mfc, gategrp_mfcmscl_sysmmu_mfc);
+GRPGATE(gate_mfcmscl_sysmmu_mscl, gate_mfcmscl_common_mscl, gategrp_mfcmscl_sysmmu_mscl);
+GRPGATE(gate_mfcmscl_ppmu, gate_mfcmscl_common, gategrp_mfcmscl_ppmu);
+GRPGATE(gate_mfcmscl_bts, gate_mfcmscl_common, gategrp_mfcmscl_bts);
+GRPGATE(gate_mfcmscl_mscl_bi, gate_mfcmscl_common_mscl, gategrp_mfcmscl_mscl_bi);
+GRPGATE(gate_mfcmscl_mscl_poly, gate_mfcmscl_common_mscl, gategrp_mfcmscl_mscl_poly);
+GRPGATE(gate_mfcmscl_jpeg, gate_mfcmscl_common_mscl, gategrp_mfcmscl_jpeg);
+GRPGATE(gate_mfcmscl_mfc, gate_mfcmscl_common, gategrp_mfcmscl_mfc);
+
+GRPGATE(gate_g3d_common, dvfs_g3d, gategrp_g3d_common);
+GRPGATE(gate_g3d_sysmmu, gate_g3d_common, gategrp_g3d_sysmmu);
+GRPGATE(gate_g3d_ppmu, gate_g3d_common, gategrp_g3d_ppmu);
+GRPGATE(gate_g3d_bts, gate_g3d_common, gategrp_g3d_bts);
+GRPGATE(gate_g3d_g3d, gate_g3d_common, gategrp_g3d_g3d);
+
+GRPGATE(gate_peri_peris0, 0, gategrp_peri_peris0);
+GRPGATE(gate_peri_peric0, 0, gategrp_peri_peric0);
+GRPGATE(gate_peri_peric1, 0, gategrp_peri_peric1);
+GRPGATE(gate_peri_pwm_motor, gate_peri_peric1, gategrp_peri_pwm_motor);
+GRPGATE(gate_peri_sclk_pwm_motor, 0, gategrp_peri_sclk_pwm_motor);
+GRPGATE(gate_peri_mct, 0, gategrp_peri_mct);
+GRPGATE(gate_peri_i2c_sensor2, gate_peri_peric0, gategrp_peri_i2c_sensor2);
+GRPGATE(gate_peri_i2c_sensor1, gate_peri_peric0, gategrp_peri_i2c_sensor1);
+GRPGATE(gate_peri_i2c_tsp, gate_peri_peric0, gategrp_peri_i2c_tsp);
+GRPGATE(gate_peri_i2c_touchkey, gate_peri_peric0, gategrp_peri_i2c_touchkey);
+GRPGATE(gate_peri_i2c_fuelgauge, gate_peri_peric0, gategrp_peri_i2c_fuelgauge);
+GRPGATE(gate_peri_i2c_spkamp, gate_peri_peric0, gategrp_peri_i2c_spkamp);
+GRPGATE(gate_peri_i2c_nfc, gate_peri_peric0, gategrp_peri_i2c_nfc);
+GRPGATE(gate_peri_i2c_muic, gate_peri_peric0, gategrp_peri_i2c_muic);
+GRPGATE(gate_peri_i2c_ifpmic, gate_peri_peric0, gategrp_peri_i2c_ifpmic);
+GRPGATE(gate_peri_hsi2c_frontcam, gate_peri_peric1, gategrp_peri_hsi2c_frontcam);
+GRPGATE(gate_peri_hsi2c_maincam, gate_peri_peric1, gategrp_peri_hsi2c_maincam);
+GRPGATE(gate_peri_hsi2c_depthcam, gate_peri_peric0, gategrp_peri_hsi2c_depthcam);
+GRPGATE(gate_peri_hsi2c_frontsensor, gate_peri_peric0, gategrp_peri_hsi2c_frontsensor);
+GRPGATE(gate_peri_hsi2c_rearaf, gate_peri_peric0, gategrp_peri_hsi2c_rearaf);
+GRPGATE(gate_peri_hsi2c_rearsensor, gate_peri_peric0, gategrp_peri_hsi2c_rearsensor);
+GRPGATE(gate_peri_gpio_touch, gate_peri_peric1, gategrp_peri_gpio_touch);
+GRPGATE(gate_peri_gpio_top, gate_peri_peric1, gategrp_peri_gpio_top);
+GRPGATE(gate_peri_gpio_nfc, gate_peri_peric1, gategrp_peri_gpio_nfc);
+GRPGATE(gate_peri_gpio_ese, gate_peri_peric1, gategrp_peri_gpio_ese);
+GRPGATE(gate_peri_wdt_cpucl1, 0, gategrp_peri_wdt_cpucl1);
+GRPGATE(gate_peri_wdt_cpucl0, 0, gategrp_peri_wdt_cpucl0);
+GRPGATE(gate_peri_uart_debug, sclk_uart_debug, gategrp_peri_uart_debug);
+GRPGATE(gate_peri_uart_btwififm, sclk_uart_btwififm, gategrp_peri_uart_btwififm);
+GRPGATE(gate_peri_uart_sensor, sclk_uart_sensor, gategrp_peri_uart_sensor);
+GRPGATE(gate_peri_tmu_g3d, 0, gategrp_peri_tmu_g3d);
+GRPGATE(gate_peri_tmu_cpucl1, 0, gategrp_peri_tmu_cpucl1);
+GRPGATE(gate_peri_tmu_cpucl0, 0, gategrp_peri_tmu_cpucl0);
+GRPGATE(gate_peri_spi_sensorhub, sclk_spi_sensorhub, gategrp_peri_spi_sensorhub);
+GRPGATE(gate_peri_spi_voiceprocessor, sclk_spi_voiceprocessor, gategrp_peri_spi_voiceprocessor);
+GRPGATE(gate_peri_spi_ese, sclk_spi_ese, gategrp_peri_spi_ese);
+GRPGATE(gate_peri_spi_rearfrom, sclk_spi_rearfrom, gategrp_peri_spi_rearfrom);
+GRPGATE(gate_peri_spi_frontfrom, sclk_spi_frontfrom, gategrp_peri_spi_frontfrom);
+GRPGATE(gate_peri_gpio_alive, gate_peri_peric1, gategrp_peri_gpio_alive);
+GRPGATE(gate_peri_chipid, 0, gategrp_peri_chipid);
+GRPGATE(gate_peri_otp_con_top, gate_peri_peris0, gategrp_peri_otp_con_top);
+GRPGATE(gate_peri_rtc_alive, 0, gategrp_peri_rtc_alive);
+GRPGATE(gate_peri_rtc_top, 0, gategrp_peri_rtc_top);
+
+GRPGATE(gate_fsys_common, 0, gategrp_fsys_common);
+GRPGATE(gate_fsys_common_sub1, gate_fsys_common, gategrp_fsys_common_sub1);
+GRPGATE(gate_fsys_common_sub2, gate_fsys_common, gategrp_fsys_common_sub2);
+GRPGATE(gate_fsys_sysmmu, gate_fsys_common, gategrp_fsys_sysmmu);
+GRPGATE(gate_fsys_ppmu, gate_fsys_common, gategrp_fsys_ppmu);
+GRPGATE(gate_fsys_bts, gate_fsys_common, gategrp_fsys_bts);
+GRPGATE(gate_fsys_usb20drd, gate_fsys_common_sub2, gategrp_fsys_usb20drd);
+GRPGATE(gate_fsys_mmc0, gate_fsys_common_sub2, gategrp_fsys_mmc0);
+GRPGATE(gate_fsys_sclk_mmc0, sclk_mmc0, gategrp_fsys_sclk_mmc0);
+GRPGATE(gate_fsys_mmc1, gate_fsys_common_sub2, gategrp_fsys_mmc1);
+GRPGATE(gate_fsys_sclk_mmc1, sclk_mmc1, gategrp_fsys_sclk_mmc1);
+GRPGATE(gate_fsys_mmc2, gate_fsys_common_sub2, gategrp_fsys_mmc2);
+GRPGATE(gate_fsys_sclk_mmc2, sclk_mmc2, gategrp_fsys_sclk_mmc2);
+GRPGATE(gate_fsys_sss, gate_fsys_common_sub1, gategrp_fsys_sss);
+GRPGATE(gate_fsys_rtic, gate_fsys_common_sub1, gategrp_fsys_rtic);
+GRPGATE(gate_fsys_pdma0, gate_fsys_common_sub1, gategrp_fsys_pdma0);
+GRPGATE(gate_fsys_pdma1, gate_fsys_common_sub1, gategrp_fsys_pdma1);
+GRPGATE(gate_fsys_sromc, gate_fsys_common_sub2, gategrp_fsys_sromc);
+
+GRPGATE(gate_dispaud_disp, pxmxdx_disp, gategrp_dispaud_disp);
+GRPGATE(gate_dispaud_aud, pxmxdx_disp, gategrp_dispaud_aud);
+GRPGATE(gate_dispaud_sysmmu, gate_dispaud_disp, gategrp_dispaud_sysmmu);
+GRPGATE(gate_dispaud_ppmu, gate_dispaud_disp, gategrp_dispaud_ppmu);
+GRPGATE(gate_dispaud_bts, gate_dispaud_disp, gategrp_dispaud_bts);
+GRPGATE(gate_dispaud_decon, gate_dispaud_disp, gategrp_dispaud_decon);
+GRPGATE(gate_dispaud_dsim0, gate_dispaud_disp, gategrp_dispaud_dsim0);
+GRPGATE(gate_dispaud_mixer, gate_dispaud_aud, gategrp_dispaud_mixer);
+GRPGATE(gate_dispaud_mi2s_aud, gate_dispaud_aud, gategrp_dispaud_mi2s_aud);
+GRPGATE(gate_dispaud_mi2s_amp, gate_dispaud_aud, gategrp_dispaud_mi2s_amp);
+
+GRPGATE(gate_isp_common, dvfs_cam, gategrp_isp_common);
+GRPGATE(gate_isp_sysmmu, gate_isp_common, gategrp_isp_sysmmu);
+GRPGATE(gate_isp_ppmu, gate_isp_common, gategrp_isp_ppmu);
+GRPGATE(gate_isp_bts, gate_isp_common, gategrp_isp_bts);
+GRPGATE(gate_isp_cam, gate_isp_common, gategrp_isp_cam);
+GRPGATE(gate_isp_isp, gate_isp_common, gategrp_isp_isp);
+GRPGATE(gate_isp_vra, gate_isp_common, gategrp_isp_vra);
+
+GRPGATE(gate_mif_adcif, 0, gategrp_mif_adcif);
+GRPGATE(gate_mif_hsi2c_mif, 0, gategrp_mif_hsi2c_mif);
+
+GRPGATE(sclk_uart0, 0, gategrp_sclk_uart0);
+
+
+UMUX(umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user, 0, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER);
+UMUX(umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user, 0, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER);
+UMUX(umux_fsys_clkphy_fsys_usb20drd_phyclock_user, 0, FSYS_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER);
+UMUX(umux_fsys_clkphy_fsys_ufs_tx0_symbol_user, 0, FSYS_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER);
+UMUX(umux_fsys_clkphy_fsys_ufs_rx0_symbol_user, 0, FSYS_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER);
+UMUX(umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user, 0, ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER);
+UMUX(umux_isp_clkphy_isp_s_rxbyteclkhs0_s4s_user, 0, ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER);
+
+
+void vclk_unused_disable(void)
+{
+	vclk_disable(VCLK(gate_cpucl0_ppmu));
+	vclk_disable(VCLK(gate_cpucl0_bts));
+	vclk_disable(VCLK(gate_cpucll_ppmu));
+	vclk_disable(VCLK(gate_cpucll_bts));
+	vclk_disable(VCLK(gate_mfcmscl_sysmmu_mscl));
+	vclk_disable(VCLK(gate_mfcmscl_sysmmu_mfc));
+	vclk_disable(VCLK(gate_mfcmscl_ppmu));
+	vclk_disable(VCLK(gate_mfcmscl_bts));
+	vclk_disable(VCLK(gate_mfcmscl_common));
+	vclk_disable(VCLK(gate_mfcmscl_mscl_bi));
+	vclk_disable(VCLK(gate_mfcmscl_mscl_poly));
+	vclk_disable(VCLK(gate_mfcmscl_jpeg));
+	vclk_disable(VCLK(gate_mfcmscl_mfc));
+	vclk_disable(VCLK(gate_g3d_common));
+	vclk_disable(VCLK(gate_g3d_sysmmu));
+	vclk_disable(VCLK(gate_g3d_ppmu));
+	vclk_disable(VCLK(gate_g3d_bts));
+	vclk_disable(VCLK(gate_g3d_g3d));
+//	vclk_disable(VCLK(gate_peri_pwm_motor));
+//	vclk_disable(VCLK(gate_peri_sclk_pwm_motor));
+	vclk_disable(VCLK(gate_peri_i2c_sensor2));
+	vclk_disable(VCLK(gate_peri_i2c_sensor1));
+	vclk_disable(VCLK(gate_peri_i2c_tsp));
+	vclk_disable(VCLK(gate_peri_i2c_touchkey));
+	vclk_disable(VCLK(gate_peri_i2c_fuelgauge));
+	vclk_disable(VCLK(gate_peri_i2c_spkamp));
+	vclk_disable(VCLK(gate_peri_i2c_nfc));
+	vclk_disable(VCLK(gate_peri_i2c_muic));
+	vclk_disable(VCLK(gate_peri_i2c_ifpmic));
+	vclk_disable(VCLK(gate_peri_hsi2c_frontcam));
+	vclk_disable(VCLK(gate_peri_hsi2c_maincam));
+	vclk_disable(VCLK(gate_peri_hsi2c_depthcam));
+	vclk_disable(VCLK(gate_peri_hsi2c_frontsensor));
+	vclk_disable(VCLK(gate_peri_hsi2c_rearaf));
+	vclk_disable(VCLK(gate_peri_hsi2c_rearsensor));
+//	vclk_disable(VCLK(gate_peri_uart_debug));
+//	vclk_disable(VCLK(gate_peri_uart_btwififm));
+//	vclk_disable(VCLK(gate_peri_uart_sensor));
+//	vclk_disable(VCLK(gate_peri_tmu_g3d));
+//	vclk_disable(VCLK(gate_peri_tmu_cpucl1));
+//	vclk_disable(VCLK(gate_peri_tmu_cpucl0));
+	vclk_disable(VCLK(gate_peri_spi_sensorhub));
+	vclk_disable(VCLK(gate_peri_spi_voiceprocessor));
+	vclk_disable(VCLK(gate_peri_spi_ese));
+	vclk_disable(VCLK(gate_peri_spi_rearfrom));
+	vclk_disable(VCLK(gate_peri_spi_frontfrom));
+	vclk_disable(VCLK(gate_peri_chipid));
+	vclk_disable(VCLK(gate_peri_otp_con_top));
+	vclk_disable(VCLK(gate_peri_rtc_alive));
+	vclk_disable(VCLK(gate_peri_rtc_top));
+
+	vclk_disable(VCLK(gate_fsys_sysmmu));
+	vclk_disable(VCLK(gate_fsys_ppmu));
+	vclk_disable(VCLK(gate_fsys_bts));
+	vclk_disable(VCLK(gate_fsys_usb20drd));
+	vclk_disable(VCLK(gate_fsys_mmc0));
+	vclk_disable(VCLK(gate_fsys_mmc1));
+	vclk_disable(VCLK(gate_fsys_mmc2));
+	vclk_disable(VCLK(gate_fsys_sss));
+	vclk_disable(VCLK(gate_fsys_rtic));
+	vclk_disable(VCLK(gate_fsys_pdma0));
+	vclk_disable(VCLK(gate_fsys_pdma1));
+	vclk_disable(VCLK(gate_fsys_sromc));
+	vclk_disable(VCLK(gate_dispaud_sysmmu));
+	vclk_disable(VCLK(gate_dispaud_ppmu));
+	vclk_disable(VCLK(gate_dispaud_bts));
+	vclk_disable(VCLK(gate_dispaud_decon));
+	vclk_disable(VCLK(gate_dispaud_dsim0));
+	vclk_disable(VCLK(gate_dispaud_mixer));
+	vclk_disable(VCLK(gate_dispaud_mi2s_aud));
+	vclk_disable(VCLK(gate_dispaud_mi2s_amp));
+	vclk_disable(VCLK(gate_dispaud_disp));
+	vclk_disable(VCLK(gate_dispaud_aud));
+	vclk_disable(VCLK(gate_isp_sysmmu));
+	vclk_disable(VCLK(gate_isp_ppmu));
+	vclk_disable(VCLK(gate_isp_bts));
+	vclk_disable(VCLK(gate_isp_cam));
+	vclk_disable(VCLK(gate_isp_isp));
+	vclk_disable(VCLK(gate_isp_vra));
+	vclk_disable(VCLK(gate_mif_adcif));
+	vclk_disable(VCLK(gate_mif_hsi2c_mif));
+
+
+	vclk_disable(VCLK(sclk_decon_vclk));
+	vclk_disable(VCLK(sclk_decon_vclk_local));
+	vclk_disable(VCLK(sclk_decon_eclk));
+	vclk_disable(VCLK(sclk_decon_eclk_local));
+	vclk_disable(VCLK(sclk_mmc0));
+	vclk_disable(VCLK(sclk_mmc1));
+	vclk_disable(VCLK(sclk_mmc2));
+	vclk_disable(VCLK(sclk_ufsunipro));
+	vclk_disable(VCLK(sclk_ufsunipro_cfg));
+	vclk_disable(VCLK(sclk_usb20drd));
+//	vclk_disable(VCLK(sclk_uart_sensor));
+//	vclk_disable(VCLK(sclk_uart_btwififm));
+//	vclk_disable(VCLK(sclk_uart_debug));
+	vclk_disable(VCLK(sclk_spi_frontfrom));
+	vclk_disable(VCLK(sclk_spi_rearfrom));
+	vclk_disable(VCLK(sclk_spi_ese));
+	vclk_disable(VCLK(sclk_spi_voiceprocessor));
+	vclk_disable(VCLK(sclk_spi_sensorhub));
+	vclk_disable(VCLK(sclk_isp_sensor0));
+	vclk_disable(VCLK(sclk_isp_sensor1));
+	vclk_disable(VCLK(sclk_isp_sensor2));
+
+	vclk_disable(VCLK(p1_disp_pll));
+	vclk_disable(VCLK(p1_aud_pll));
+	vclk_disable(VCLK(p1_usb_pll));
+	vclk_disable(VCLK(p1_isp_pll));
+
+	vclk_disable(VCLK(pxmxdx_top));
+	vclk_disable(VCLK(pxmxdx_disp));
+	vclk_disable(VCLK(pxmxdx_mfcmscl));
+	vclk_disable(VCLK(pxmxdx_isp_vra));
+	vclk_disable(VCLK(pxmxdx_isp_cam));
+	vclk_disable(VCLK(pxmxdx_isp_isp));
+
+	vclk_disable(VCLK(umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user));
+	vclk_disable(VCLK(umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user));
+	vclk_disable(VCLK(umux_fsys_clkphy_fsys_usb20drd_phyclock_user));
+	vclk_disable(VCLK(umux_fsys_clkphy_fsys_ufs_tx0_symbol_user));
+	vclk_disable(VCLK(umux_fsys_clkphy_fsys_ufs_rx0_symbol_user));
+	vclk_disable(VCLK(umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user));
+	vclk_disable(VCLK(umux_isp_clkphy_isp_s_rxbyteclkhs0_s4s_user));
+
+}
+
+void vclk_init(void)
+{
+	ADD_LIST(vclk_pxmxdx_list, pxmxdx_top);
+	ADD_LIST(vclk_pxmxdx_list, pxmxdx_disp);
+	ADD_LIST(vclk_pxmxdx_list, pxmxdx_mfcmscl);
+	ADD_LIST(vclk_pxmxdx_list, pxmxdx_isp_vra);
+	ADD_LIST(vclk_pxmxdx_list, pxmxdx_isp_cam);
+	ADD_LIST(vclk_pxmxdx_list, pxmxdx_isp_isp);
+
+	ADD_LIST(vclk_p1_list, p1_disp_pll);
+	ADD_LIST(vclk_p1_list, p1_aud_pll);
+	ADD_LIST(vclk_p1_list, p1_usb_pll);
+	ADD_LIST(vclk_p1_list, p1_isp_pll);
+
+	ADD_LIST(vclk_m1_list, m1_dummy);
+
+	ADD_LIST(vclk_d1_list, d1_dispaud_mi2s);
+	ADD_LIST(vclk_d1_list, d1_dispaud_mixer);
+
+
+	ADD_LIST(vclk_m1d1g1_list, sclk_decon_vclk);
+	ADD_LIST(vclk_m1d1g1_list, sclk_decon_vclk_local);
+	ADD_LIST(vclk_m1d1g1_list, sclk_decon_eclk);
+	ADD_LIST(vclk_m1d1g1_list, sclk_decon_eclk_local);
+	ADD_LIST(vclk_m1d1g1_list, sclk_mmc0);
+	ADD_LIST(vclk_m1d1g1_list, sclk_mmc1);
+	ADD_LIST(vclk_m1d1g1_list, sclk_mmc2);
+	ADD_LIST(vclk_m1d1g1_list, sclk_ufsunipro);
+	ADD_LIST(vclk_m1d1g1_list, sclk_ufsunipro_cfg);
+	ADD_LIST(vclk_m1d1g1_list, sclk_usb20drd);
+	ADD_LIST(vclk_m1d1g1_list, sclk_uart_sensor);
+	ADD_LIST(vclk_m1d1g1_list, sclk_uart_btwififm);
+	ADD_LIST(vclk_m1d1g1_list, sclk_uart_debug);
+	ADD_LIST(vclk_m1d1g1_list, sclk_spi_frontfrom);
+	ADD_LIST(vclk_m1d1g1_list, sclk_spi_rearfrom);
+	ADD_LIST(vclk_m1d1g1_list, sclk_spi_ese);
+	ADD_LIST(vclk_m1d1g1_list, sclk_spi_voiceprocessor);
+	ADD_LIST(vclk_m1d1g1_list, sclk_spi_sensorhub);
+	ADD_LIST(vclk_m1d1g1_list, sclk_isp_sensor0);
+	ADD_LIST(vclk_m1d1g1_list, sclk_isp_sensor1);
+	ADD_LIST(vclk_m1d1g1_list, sclk_isp_sensor2);
+
+
+	ADD_LIST(vclk_grpgate_list, gate_cpucl0_ppmu);
+	ADD_LIST(vclk_grpgate_list, gate_cpucl0_bts);
+	ADD_LIST(vclk_grpgate_list, gate_cpucll_ppmu);
+	ADD_LIST(vclk_grpgate_list, gate_cpucll_bts);
+
+	ADD_LIST(vclk_grpgate_list, gate_mfcmscl_common);
+	ADD_LIST(vclk_grpgate_list, gate_mfcmscl_common_mscl);
+	ADD_LIST(vclk_grpgate_list, gate_mfcmscl_sysmmu_mscl);
+	ADD_LIST(vclk_grpgate_list, gate_mfcmscl_sysmmu_mfc);
+	ADD_LIST(vclk_grpgate_list, gate_mfcmscl_ppmu);
+	ADD_LIST(vclk_grpgate_list, gate_mfcmscl_bts);
+	ADD_LIST(vclk_grpgate_list, gate_mfcmscl_mscl_bi);
+	ADD_LIST(vclk_grpgate_list, gate_mfcmscl_mscl_poly);
+	ADD_LIST(vclk_grpgate_list, gate_mfcmscl_jpeg);
+	ADD_LIST(vclk_grpgate_list, gate_mfcmscl_mfc);
+
+	ADD_LIST(vclk_grpgate_list, gate_g3d_common);
+	ADD_LIST(vclk_grpgate_list, gate_g3d_sysmmu);
+	ADD_LIST(vclk_grpgate_list, gate_g3d_ppmu);
+	ADD_LIST(vclk_grpgate_list, gate_g3d_bts);
+	ADD_LIST(vclk_grpgate_list, gate_g3d_g3d);
+
+	ADD_LIST(vclk_grpgate_list, gate_peri_peris0);
+	ADD_LIST(vclk_grpgate_list, gate_peri_peric0);
+	ADD_LIST(vclk_grpgate_list, gate_peri_peric1);
+	ADD_LIST(vclk_grpgate_list, gate_peri_pwm_motor);
+	ADD_LIST(vclk_grpgate_list, gate_peri_sclk_pwm_motor);
+	ADD_LIST(vclk_grpgate_list, gate_peri_mct);
+	ADD_LIST(vclk_grpgate_list, gate_peri_i2c_sensor2);
+	ADD_LIST(vclk_grpgate_list, gate_peri_i2c_sensor1);
+	ADD_LIST(vclk_grpgate_list, gate_peri_i2c_tsp);
+	ADD_LIST(vclk_grpgate_list, gate_peri_i2c_touchkey);
+	ADD_LIST(vclk_grpgate_list, gate_peri_i2c_fuelgauge);
+	ADD_LIST(vclk_grpgate_list, gate_peri_i2c_spkamp);
+	ADD_LIST(vclk_grpgate_list, gate_peri_i2c_nfc);
+	ADD_LIST(vclk_grpgate_list, gate_peri_i2c_muic);
+	ADD_LIST(vclk_grpgate_list, gate_peri_i2c_ifpmic);
+	ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_frontcam);
+	ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_maincam);
+	ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_depthcam);
+	ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_frontsensor);
+	ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_rearaf);
+	ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_rearsensor);
+	ADD_LIST(vclk_grpgate_list, gate_peri_gpio_touch);
+	ADD_LIST(vclk_grpgate_list, gate_peri_gpio_top);
+	ADD_LIST(vclk_grpgate_list, gate_peri_gpio_nfc);
+	ADD_LIST(vclk_grpgate_list, gate_peri_gpio_ese);
+	ADD_LIST(vclk_grpgate_list, gate_peri_wdt_cpucl1);
+	ADD_LIST(vclk_grpgate_list, gate_peri_wdt_cpucl0);
+	ADD_LIST(vclk_grpgate_list, gate_peri_uart_debug);
+	ADD_LIST(vclk_grpgate_list, gate_peri_uart_btwififm);
+	ADD_LIST(vclk_grpgate_list, gate_peri_uart_sensor);
+	ADD_LIST(vclk_grpgate_list, gate_peri_tmu_g3d);
+	ADD_LIST(vclk_grpgate_list, gate_peri_tmu_cpucl1);
+	ADD_LIST(vclk_grpgate_list, gate_peri_tmu_cpucl0);
+	ADD_LIST(vclk_grpgate_list, gate_peri_spi_sensorhub);
+	ADD_LIST(vclk_grpgate_list, gate_peri_spi_voiceprocessor);
+	ADD_LIST(vclk_grpgate_list, gate_peri_spi_ese);
+	ADD_LIST(vclk_grpgate_list, gate_peri_spi_rearfrom);
+	ADD_LIST(vclk_grpgate_list, gate_peri_spi_frontfrom);
+	ADD_LIST(vclk_grpgate_list, gate_peri_gpio_alive);
+	ADD_LIST(vclk_grpgate_list, gate_peri_chipid);
+	ADD_LIST(vclk_grpgate_list, gate_peri_otp_con_top);
+	ADD_LIST(vclk_grpgate_list, gate_peri_rtc_alive);
+	ADD_LIST(vclk_grpgate_list, gate_peri_rtc_top);
+
+	ADD_LIST(vclk_grpgate_list, gate_fsys_common);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_common_sub1);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_common_sub2);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_sysmmu);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_ppmu);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_bts);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_usb20drd);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_mmc0);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_sclk_mmc0);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_mmc1);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_sclk_mmc1);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_mmc2);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_sclk_mmc2);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_sss);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_rtic);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_pdma0);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_pdma1);
+	ADD_LIST(vclk_grpgate_list, gate_fsys_sromc);
+
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_disp);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_aud);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_sysmmu);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_ppmu);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_bts);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_decon);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_dsim0);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_mixer);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_mi2s_aud);
+	ADD_LIST(vclk_grpgate_list, gate_dispaud_mi2s_amp);
+
+	ADD_LIST(vclk_grpgate_list, gate_isp_common);
+	ADD_LIST(vclk_grpgate_list, gate_isp_sysmmu);
+	ADD_LIST(vclk_grpgate_list, gate_isp_ppmu);
+	ADD_LIST(vclk_grpgate_list, gate_isp_bts);
+	ADD_LIST(vclk_grpgate_list, gate_isp_cam);
+	ADD_LIST(vclk_grpgate_list, gate_isp_isp);
+	ADD_LIST(vclk_grpgate_list, gate_isp_vra);
+	ADD_LIST(vclk_grpgate_list, gate_mif_adcif);
+	ADD_LIST(vclk_grpgate_list, gate_mif_hsi2c_mif);
+	ADD_LIST(vclk_grpgate_list, sclk_uart0);
+
+	ADD_LIST(vclk_umux_list, umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user);
+	ADD_LIST(vclk_umux_list, umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user);
+	ADD_LIST(vclk_umux_list, umux_fsys_clkphy_fsys_usb20drd_phyclock_user);
+	ADD_LIST(vclk_umux_list, umux_fsys_clkphy_fsys_ufs_tx0_symbol_user);
+	ADD_LIST(vclk_umux_list, umux_fsys_clkphy_fsys_ufs_rx0_symbol_user);
+	ADD_LIST(vclk_umux_list, umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user);
+	ADD_LIST(vclk_umux_list, umux_isp_clkphy_isp_s_rxbyteclkhs0_s4s_user);
+
+	ADD_LIST(vclk_dfs_list, dvfs_cpucl0);
+	ADD_LIST(vclk_dfs_list, dvfs_cpucl1);
+	ADD_LIST(vclk_dfs_list, dvfs_g3d);
+	ADD_LIST(vclk_dfs_list, dvfs_mif);
+	ADD_LIST(vclk_dfs_list, dvfs_int);
+	ADD_LIST(vclk_dfs_list, dvfs_disp);
+	ADD_LIST(vclk_dfs_list, dvfs_cam);
+
+	return;
+}

drivers/soc/samsung/pwrcal/S5E7870/S5E7870-vclk.h

@@ -0,0 +1,182 @@
+#ifndef __EXYNOS7870_VCLK_H__
+#define __EXYNOS7870_VCLK_H__
+
+
+enum {
+
+	gate_cpucl0_ppmu = 0x0A000000,
+	gate_cpucl0_bts,
+	gate_cpucll_ppmu,
+	gate_cpucll_bts,
+	gate_mfcmscl_sysmmu_mscl,
+	gate_mfcmscl_sysmmu_mfc,
+	gate_mfcmscl_ppmu,
+	gate_mfcmscl_bts,
+	gate_mfcmscl_common,
+	gate_mfcmscl_common_mscl,
+	gate_mfcmscl_mscl_bi,
+	gate_mfcmscl_mscl_poly,
+	gate_mfcmscl_jpeg,
+	gate_mfcmscl_mfc,
+	gate_g3d_common,
+	gate_g3d_sysmmu,
+	gate_g3d_ppmu,
+	gate_g3d_bts,
+	gate_g3d_g3d,
+	gate_peri_peris0,
+	gate_peri_peric0,
+	gate_peri_peric1,
+	gate_peri_pwm_motor,
+	gate_peri_sclk_pwm_motor,
+	gate_peri_mct,
+	gate_peri_i2c_sensor2,
+	gate_peri_i2c_sensor1,
+	gate_peri_i2c_tsp,
+	gate_peri_i2c_touchkey,
+	gate_peri_i2c_fuelgauge,
+	gate_peri_i2c_spkamp,
+	gate_peri_i2c_nfc,
+	gate_peri_i2c_muic,
+	gate_peri_i2c_ifpmic,
+	gate_peri_hsi2c_frontcam,
+	gate_peri_hsi2c_maincam,
+	gate_peri_hsi2c_depthcam,
+	gate_peri_hsi2c_frontsensor,
+	gate_peri_hsi2c_rearaf,
+	gate_peri_hsi2c_rearsensor,
+	gate_peri_gpio_touch,
+	gate_peri_gpio_top,
+	gate_peri_gpio_nfc,
+	gate_peri_gpio_ese,
+	gate_peri_wdt_cpucl1,
+	gate_peri_wdt_cpucl0,
+	gate_peri_uart_debug,
+	gate_peri_uart_btwififm,
+	gate_peri_uart_sensor,
+	gate_peri_tmu_g3d,
+	gate_peri_tmu_cpucl1,
+	gate_peri_tmu_cpucl0,
+	gate_peri_spi_sensorhub,
+	gate_peri_spi_voiceprocessor,
+	gate_peri_spi_ese,
+	gate_peri_spi_rearfrom,
+	gate_peri_spi_frontfrom,
+	gate_peri_gpio_alive,
+	gate_peri_chipid,
+	gate_peri_otp_con_top,
+	gate_peri_rtc_alive,
+	gate_peri_rtc_top,
+
+	gate_fsys_common,
+	gate_fsys_common_sub1,
+	gate_fsys_common_sub2,
+	gate_fsys_sysmmu,
+	gate_fsys_ppmu,
+	gate_fsys_bts,
+	gate_fsys_usb20drd,
+	gate_fsys_mmc0,
+	gate_fsys_sclk_mmc0,
+	gate_fsys_mmc1,
+	gate_fsys_sclk_mmc1,
+	gate_fsys_mmc2,
+	gate_fsys_sclk_mmc2,
+	gate_fsys_sss,
+	gate_fsys_rtic,
+	gate_fsys_pdma0,
+	gate_fsys_pdma1,
+	gate_fsys_sromc,
+	gate_dispaud_disp,
+	gate_dispaud_aud,
+	gate_dispaud_sysmmu,
+	gate_dispaud_ppmu,
+	gate_dispaud_bts,
+	gate_dispaud_decon,
+	gate_dispaud_dsim0,
+	gate_dispaud_mixer,
+	gate_dispaud_mi2s_aud,
+	gate_dispaud_mi2s_amp,
+	gate_isp_common,
+	gate_isp_sysmmu,
+	gate_isp_ppmu,
+	gate_isp_bts,
+	gate_isp_cam,
+	gate_isp_isp,
+	gate_isp_vra,
+	gate_mif_adcif,
+	gate_mif_hsi2c_mif,
+	sclk_uart0,
+	vclk_group_grpgate_end,
+	num_of_grpgate = vclk_group_grpgate_end - 0x0A000000,
+
+
+	sclk_decon_vclk = 0x0A010000,
+	sclk_decon_vclk_local,
+	sclk_decon_eclk,
+	sclk_decon_eclk_local,
+	sclk_mmc0,
+	sclk_mmc1,
+	sclk_mmc2,
+	sclk_ufsunipro,
+	sclk_ufsunipro_cfg,
+	sclk_usb20drd,
+	sclk_uart_sensor,
+	sclk_uart_btwififm,
+	sclk_uart_debug,
+	sclk_spi_frontfrom,
+	sclk_spi_rearfrom,
+	sclk_spi_ese,
+	sclk_spi_voiceprocessor,
+	sclk_spi_sensorhub,
+	sclk_isp_sensor0,
+	sclk_isp_sensor1,
+	sclk_isp_sensor2,
+	vclk_group_m1d1g1_end,
+	num_of_m1d1g1 = vclk_group_m1d1g1_end - 0x0A010000,
+
+	p1_disp_pll = 0x0A020000,
+	p1_aud_pll,
+	p1_usb_pll,
+	p1_isp_pll,
+	vclk_group_p1_end,
+	num_of_p1 = vclk_group_p1_end - 0x0A020000,
+
+	m1_dummy = 0x0A030000,
+	vclk_group_m1_end,
+	num_of_m1 = vclk_group_m1_end - 0x0A030000,
+
+	d1_dispaud_mi2s = 0x0A040000,
+	d1_dispaud_mixer,
+	vclk_group_d1_end,
+	num_of_d1 = vclk_group_d1_end - 0x0A040000,
+
+	pxmxdx_top = 0x0A050000,
+	pxmxdx_disp,
+	pxmxdx_mfcmscl,
+	pxmxdx_isp_vra,
+	pxmxdx_isp_cam,
+	pxmxdx_isp_isp,
+	vclk_group_pxmxdx_end,
+	num_of_pxmxdx = vclk_group_pxmxdx_end - 0x0A050000,
+
+	umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user = 0x0A060000,
+	umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user,
+	umux_fsys_clkphy_fsys_usb20drd_phyclock_user,
+	umux_fsys_clkphy_fsys_ufs_tx0_symbol_user,
+	umux_fsys_clkphy_fsys_ufs_rx0_symbol_user,
+	umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user,
+	umux_isp_clkphy_isp_s_rxbyteclkhs0_s4s_user,
+	vclk_group_umux_end,
+	num_of_umux = vclk_group_umux_end - 0x0A060000,
+
+	dvfs_cpucl0 = 0x0A070000,
+	dvfs_cpucl1,
+	dvfs_g3d,
+	dvfs_mif,
+	dvfs_int,
+	dvfs_disp,
+	dvfs_cam,
+	vclk_group_dfs_end,
+	num_of_dfs = vclk_group_dfs_end - 0x0A070000,
+};
+
+#endif

drivers/soc/samsung/pwrcal/S5E8890/S5E8890-asv.c

@@ -0,0 +1,886 @@
+#include "../pwrcal-env.h"
+#include "../pwrcal-rae.h"
+#include "../pwrcal-asv.h"
+#include "S5E8890-cmusfr.h"
+#include "S5E8890-cmu.h"
+#include "S5E8890-vclk.h"
+#include "S5E8890-vclk-internal.h"
+
+#ifdef PWRCAL_TARGET_LINUX
+#include <linux/io.h>
+#include <asm/map.h>
+#include <soc/samsung/ect_parser.h>
+#endif
+#ifdef PWRCAL_TARGET_FW
+#include <mach/ect_parser.h>
+#define S5P_VA_APM_SRAM			((void *)0x11200000)
+#endif
+
+#define EXYNOS_MAILBOX_RCC_MIN_MAX(x)	(S5P_VA_APM_SRAM + (0x3700) + (x * 0x4))
+#define EXYNOS_MAILBOX_ATLAS_RCC(x)	(S5P_VA_APM_SRAM + (0x3730) + (x * 0x4))
+#define EXYNOS_MAILBOX_APOLLO_RCC(x)	(S5P_VA_APM_SRAM + (0x3798) + (x * 0x4))
+#define EXYNOS_MAILBOX_G3D_RCC(x)	(S5P_VA_APM_SRAM + (0x37EC) + (x * 0x4))
+#define EXYNOS_MAILBOX_MIF_RCC(x)	(S5P_VA_APM_SRAM + (0x381C) + (x * 0x4))
+
+
+enum dvfs_id {
+	cal_asv_dvfs_big,
+	cal_asv_dvfs_little,
+	cal_asv_dvfs_g3d,
+	cal_asv_dvfs_mif,
+	cal_asv_dvfs_int,
+	cal_asv_dvfs_cam,
+	cal_asv_dvfs_disp,
+	num_of_dvfs,
+};
+
+#define MAX_ASV_GROUP	16
+#define NUM_OF_ASVTABLE	1
+#define PWRCAL_ASV_LIST(table)	{table, sizeof(table) / sizeof(table[0])}
+
+struct asv_table_entry {
+	unsigned int index;
+	unsigned int *voltage;
+};
+
+struct asv_table_list {
+	struct asv_table_entry *table;
+	unsigned int table_size;
+	unsigned int voltage_count;
+};
+
+#define FORCE_ASV_MAGIC		0x57E90000
+static unsigned int force_asv_group[num_of_dvfs];
+
+#define APM_OTP_ADDRESS		0x101E9018
+#define APM_TABLE_BASE		0x11203700
+#define APM_FUSE_TABLE_BASE	APM_TABLE_BASE
+#define APM_RCC_TABLE_BASE	(APM_TABLE_BASE + 0x0030)
+static void *apm_sram_base;
+
+struct asv_tbl_info {
+	unsigned mngs_asv_group:4;
+	int mngs_modified_group:4;
+	unsigned mngs_ssa10:2;
+	unsigned mngs_ssa11:2;
+	unsigned mngs_ssa0:4;
+	unsigned apollo_asv_group:4;
+	int apollo_modified_group:4;
+	unsigned apollo_ssa10:2;
+	unsigned apollo_ssa11:2;
+	unsigned apollo_ssa0:4;
+
+	unsigned g3d_asv_group:4;
+	int g3d_modified_group:4;
+	unsigned g3d_ssa10:2;
+	unsigned g3d_ssa11:2;
+	unsigned g3d_ssa0:4;
+	unsigned mif_asv_group:4;
+	int mif_modified_group:4;
+	unsigned mif_ssa10:2;
+	unsigned mif_ssa11:2;
+	unsigned mif_ssa0:4;
+
+	unsigned int_asv_group:4;
+	int int_modified_group:4;
+	unsigned int_ssa10:2;
+	unsigned int_ssa11:2;
+	unsigned int_ssa0:4;
+	unsigned disp_asv_group:4;
+	int disp_modified_group:4;
+	unsigned disp_ssa10:2;
+	unsigned disp_ssa11:2;
+	unsigned disp_ssa0:4;
+
+	unsigned asv_table_ver:7;
+	unsigned fused_grp:1;
+	unsigned reserved_0:12;
+	unsigned g3d_mcs0:4;
+	unsigned g3d_mcs1:4;
+};
+#define ASV_INFO_ADDR_BASE	(0x101E9000)
+#define ASV_INFO_ADDR_CNT	(sizeof(struct asv_tbl_info) / 4)
+
+static struct asv_tbl_info asv_tbl_info;
+
+static struct asv_table_list *pwrcal_big_asv_table;
+static struct asv_table_list *pwrcal_little_asv_table;
+static struct asv_table_list *pwrcal_g3d_asv_table;
+static struct asv_table_list *pwrcal_mif_asv_table;
+static struct asv_table_list *pwrcal_int_asv_table;
+static struct asv_table_list *pwrcal_cam_asv_table;
+static struct asv_table_list *pwrcal_disp_asv_table;
+
+static struct asv_table_list *pwrcal_big_rcc_table;
+static struct asv_table_list *pwrcal_little_rcc_table;
+static struct asv_table_list *pwrcal_g3d_rcc_table;
+static struct asv_table_list *pwrcal_mif_rcc_table;
+
+static struct pwrcal_vclk_dfs *asv_dvfs_big;
+static struct pwrcal_vclk_dfs *asv_dvfs_little;
+static struct pwrcal_vclk_dfs *asv_dvfs_g3d;
+static struct pwrcal_vclk_dfs *asv_dvfs_mif;
+static struct pwrcal_vclk_dfs *asv_dvfs_int;
+static struct pwrcal_vclk_dfs *asv_dvfs_cam;
+static struct pwrcal_vclk_dfs *asv_dvfs_disp;
+
+
+static void asv_set_grp(unsigned int id, unsigned int asvgrp)
+{
+	force_asv_group[id & 0x0000FFFF] = FORCE_ASV_MAGIC | asvgrp;
+}
+
+static void asv_set_tablever(unsigned int version)
+{
+	asv_tbl_info.asv_table_ver = version;
+
+	return;
+}
+
+static int get_max_freq_lv(struct ect_voltage_domain *domain, unsigned int version)
+{
+	int i;
+	int ret = -1;
+
+	for (i = 0; i < domain->num_of_level; i++) {
+		if (domain->table_list[version].level_en[i]) {
+			ret = i;
+			break;
+		}
+	}
+
+	return ret;
+}
+static int get_min_freq_lv(struct ect_voltage_domain *domain, unsigned int version)
+{
+	int i;
+	int ret = -1;
+
+	for (i = domain->num_of_level - 1; i >= 0; i--) {
+		if (domain->table_list[version].level_en[i]) {
+			ret = i;
+			break;
+		}
+	}
+
+	return ret;
+}
+static void asv_set_freq_limit(void)
+{
+	void *asv_block;
+	struct ect_voltage_domain *domain;
+	int lv;
+
+	asv_block = ect_get_block("ASV");
+	if (asv_block == NULL)
+		BUG();
+
+	if (!asv_tbl_info.fused_grp)
+		goto notfused;
+
+	domain = ect_asv_get_domain(asv_block, "dvfs_big");
+	if (!domain)
+		BUG();
+	lv = get_max_freq_lv(domain, asv_tbl_info.asv_table_ver);
+	if (lv >= 0)
+		asv_dvfs_big->table->max_freq = domain->level_list[lv] * 1000;
+	lv = get_min_freq_lv(domain, asv_tbl_info.asv_table_ver);
+	if (lv >= 0)
+		asv_dvfs_big->table->min_freq = domain->level_list[lv] * 1000;
+
+	domain = ect_asv_get_domain(asv_block, "dvfs_little");
+	if (!domain)
+		BUG();
+	lv = get_max_freq_lv(domain, asv_tbl_info.asv_table_ver);
+	if (lv >= 0)
+		asv_dvfs_little->table->max_freq = domain->level_list[lv] * 1000;
+	lv = get_min_freq_lv(domain, asv_tbl_info.asv_table_ver);
+	if (lv >= 0)
+		asv_dvfs_little->table->min_freq = domain->level_list[lv] * 1000;
+
+	domain = ect_asv_get_domain(asv_block, "dvfs_g3d");
+	if (!domain)
+		BUG();
+	lv = get_max_freq_lv(domain, asv_tbl_info.asv_table_ver);
+	if (lv >= 0)
+		asv_dvfs_g3d->table->max_freq = domain->level_list[lv] * 1000;
+	lv = get_min_freq_lv(domain, asv_tbl_info.asv_table_ver);
+	if (lv >= 0)
+		asv_dvfs_g3d->table->min_freq = domain->level_list[lv] * 1000;
+
+	domain = ect_asv_get_domain(asv_block, "dvfs_mif");
+	if (!domain)
+		BUG();
+	lv = get_max_freq_lv(domain, asv_tbl_info.asv_table_ver);
+	if (lv >= 0)
+		asv_dvfs_mif->table->max_freq = domain->level_list[lv] * 1000;
+	lv = get_min_freq_lv(domain, asv_tbl_info.asv_table_ver);
+	if (lv >= 0)
+		asv_dvfs_mif->table->min_freq = domain->level_list[lv] * 1000;
+
+	domain = ect_asv_get_domain(asv_block, "dvfs_int");
+	if (!domain)
+		BUG();
+	lv = get_max_freq_lv(domain, asv_tbl_info.asv_table_ver);
+	if (lv >= 0)
+		asv_dvfs_int->table->max_freq = domain->level_list[lv] * 1000;
+	lv = get_min_freq_lv(domain, asv_tbl_info.asv_table_ver);
+	if (lv >= 0)
+		asv_dvfs_int->table->min_freq = domain->level_list[lv] * 1000;
+
+	domain = ect_asv_get_domain(asv_block, "dvfs_disp");
+	if (!domain)
+		BUG();
+	lv = get_max_freq_lv(domain, asv_tbl_info.asv_table_ver);
+	if (lv >= 0)
+		asv_dvfs_disp->table->max_freq = domain->level_list[lv] * 1000;
+	lv = get_min_freq_lv(domain, asv_tbl_info.asv_table_ver);
+	if (lv >= 0)
+		asv_dvfs_disp->table->min_freq = domain->level_list[lv] * 1000;
+
+	domain = ect_asv_get_domain(asv_block, "dvfs_cam");
+	if (!domain)
+		BUG();
+	lv = get_max_freq_lv(domain, asv_tbl_info.asv_table_ver);
+	if (lv >= 0)
+		asv_dvfs_cam->table->max_freq = domain->level_list[lv] * 1000;
+	lv = get_min_freq_lv(domain, asv_tbl_info.asv_table_ver);
+	if (lv >= 0)
+		asv_dvfs_cam->table->min_freq = domain->level_list[lv] * 1000;
+
+
+	return;
+
+
+notfused:
+
+#ifdef PWRCAL_TARGET_LINUX
+	asv_dvfs_big->table->max_freq = 728000;
+	asv_dvfs_little->table->max_freq = 1274000;
+	asv_dvfs_g3d->table->max_freq = 260000;
+	asv_dvfs_mif->table->max_freq = 1539000;
+#endif
+	return;
+}
+
+static void asv_get_asvinfo(void)
+{
+	int i;
+	unsigned int *pasv_table;
+	unsigned long tmp;
+
+	pasv_table = (unsigned int *)&asv_tbl_info;
+	for (i = 0; i < ASV_INFO_ADDR_CNT; i++) {
+#ifdef PWRCAL_TARGET_LINUX
+		exynos_smc_readsfr((unsigned long)(ASV_INFO_ADDR_BASE + 0x4 * i), &tmp);
+#else
+#if (CONFIG_STARTUP_EL_MODE == STARTUP_EL3)
+		tmp = *((volatile unsigned int *)(unsigned long)(ASV_INFO_ADDR_BASE + 0x4 * i));
+#else
+		smc_readsfr((unsigned long)(ASV_INFO_ADDR_BASE + 0x4 * i), &tmp);
+#endif
+#endif
+		*(pasv_table + i) = (unsigned int)tmp;
+	}
+
+	if (!asv_tbl_info.fused_grp) {
+		asv_tbl_info.mngs_asv_group = 0;
+		asv_tbl_info.mngs_modified_group = 0;
+		asv_tbl_info.mngs_ssa10 = 0;
+		asv_tbl_info.mngs_ssa11 = 0;
+		asv_tbl_info.mngs_ssa0 = 0;
+		asv_tbl_info.apollo_asv_group = 0;
+		asv_tbl_info.apollo_modified_group = 0;
+		asv_tbl_info.apollo_ssa10 = 0;
+		asv_tbl_info.apollo_ssa11 = 0;
+		asv_tbl_info.apollo_ssa0 = 0;
+
+		asv_tbl_info.g3d_asv_group = 0;
+		asv_tbl_info.g3d_modified_group = 0;
+		asv_tbl_info.g3d_ssa10 = 0;
+		asv_tbl_info.g3d_ssa11 = 0;
+		asv_tbl_info.g3d_ssa0 = 0;
+		asv_tbl_info.mif_asv_group = 0;
+		asv_tbl_info.mif_modified_group = 0;
+		asv_tbl_info.mif_ssa10 = 0;
+		asv_tbl_info.mif_ssa11 = 0;
+		asv_tbl_info.mif_ssa0 = 0;
+
+		asv_tbl_info.int_asv_group = 0;
+		asv_tbl_info.int_modified_group = 0;
+		asv_tbl_info.int_ssa10 = 0;
+		asv_tbl_info.int_ssa11 = 0;
+		asv_tbl_info.int_ssa0 = 0;
+		asv_tbl_info.disp_asv_group = 0;
+		asv_tbl_info.disp_modified_group = 0;
+		asv_tbl_info.disp_ssa10 = 0;
+		asv_tbl_info.disp_ssa11 = 0;
+		asv_tbl_info.disp_ssa0 = 0;
+
+		asv_tbl_info.asv_table_ver = 0;
+		asv_tbl_info.fused_grp = 0;
+		asv_tbl_info.reserved_0 = 0;
+		asv_tbl_info.g3d_mcs0 = 0;
+		asv_tbl_info.g3d_mcs1 = 0;
+	}
+
+	if (asv_tbl_info.g3d_mcs0 == 0)
+		asv_tbl_info.g3d_mcs0 = 0x5;
+	if (asv_tbl_info.g3d_mcs1 == 0)
+		asv_tbl_info.g3d_mcs1 = 0xE;
+
+	asv_set_freq_limit();
+}
+
+static int get_asv_group(enum dvfs_id domain, unsigned int lv)
+{
+	int asv = 0;
+	int mod = 0;
+
+	switch (domain) {
+	case cal_asv_dvfs_big:
+		asv = asv_tbl_info.mngs_asv_group;
+		mod = asv_tbl_info.mngs_modified_group;
+		break;
+	case cal_asv_dvfs_little:
+		asv = asv_tbl_info.apollo_asv_group;
+		mod = asv_tbl_info.apollo_modified_group;
+		break;
+	case cal_asv_dvfs_g3d:
+		asv = asv_tbl_info.g3d_asv_group;
+		mod = asv_tbl_info.g3d_modified_group;
+		break;
+	case cal_asv_dvfs_mif:
+		asv = asv_tbl_info.mif_asv_group;
+		mod = asv_tbl_info.mif_modified_group;
+		break;
+	case cal_asv_dvfs_int:
+		asv = asv_tbl_info.int_asv_group;
+		mod = asv_tbl_info.int_modified_group;
+		break;
+	case cal_asv_dvfs_cam:
+		asv = asv_tbl_info.disp_asv_group;
+		mod = asv_tbl_info.disp_modified_group;
+		break;
+	case cal_asv_dvfs_disp:
+		asv = asv_tbl_info.disp_asv_group;
+		mod = asv_tbl_info.disp_modified_group;
+		break;
+	default:
+		BUG();	/* Never reach */
+		break;
+	}
+
+	if ((force_asv_group[domain & 0x0000FFFF] & 0xFFFF0000) != FORCE_ASV_MAGIC) {
+		if (mod)
+			asv += mod;
+	} else {
+		asv = force_asv_group[domain & 0x0000FFFF] & 0x0000FFFF;
+	}
+
+	if (asv < 0 || asv >= MAX_ASV_GROUP)
+		BUG();	/* Never reach */
+
+	return asv;
+}
+
+static unsigned int get_asv_voltage(enum dvfs_id domain, unsigned int lv)
+{
+	int asv;
+	unsigned int ssa10, ssa11;
+	unsigned int ssa0;
+	unsigned int subgrp_index;
+	const unsigned int *table;
+	unsigned int volt;
+
+	switch (domain) {
+	case cal_asv_dvfs_big:
+		asv = get_asv_group(cal_asv_dvfs_big, lv);
+		ssa10 = asv_tbl_info.mngs_ssa10;
+		ssa11 = asv_tbl_info.mngs_ssa11;
+		ssa0 = asv_tbl_info.mngs_ssa0;
+		subgrp_index = 16;
+		table = pwrcal_big_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
+		break;
+	case cal_asv_dvfs_little:
+		asv = get_asv_group(cal_asv_dvfs_little, lv);
+		ssa10 = asv_tbl_info.apollo_ssa10;
+		ssa11 = asv_tbl_info.apollo_ssa11;
+		ssa0 = asv_tbl_info.apollo_ssa0;
+		subgrp_index = 10;
+		table = pwrcal_little_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
+		break;
+	case cal_asv_dvfs_g3d:
+		asv = get_asv_group(cal_asv_dvfs_g3d, lv);
+		ssa10 = asv_tbl_info.g3d_ssa10;
+		ssa11 = asv_tbl_info.g3d_ssa11;
+		ssa0 = asv_tbl_info.g3d_ssa0;
+		subgrp_index = 7;
+		table = pwrcal_g3d_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
+		break;
+	case cal_asv_dvfs_mif:
+		asv = get_asv_group(cal_asv_dvfs_mif, lv);
+		ssa10 = asv_tbl_info.mif_ssa10;
+		ssa11 = asv_tbl_info.mif_ssa11;
+		ssa0 = asv_tbl_info.mif_ssa0;
+		subgrp_index = 8;
+		table = pwrcal_mif_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
+		break;
+	case cal_asv_dvfs_int:
+		asv = get_asv_group(cal_asv_dvfs_int, lv);
+		ssa10 = asv_tbl_info.int_ssa10;
+		ssa11 = asv_tbl_info.int_ssa11;
+		ssa0 = asv_tbl_info.int_ssa0;
+		subgrp_index = 15;
+		table = pwrcal_int_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
+		break;
+	case cal_asv_dvfs_cam:
+		asv = get_asv_group(cal_asv_dvfs_cam, lv);
+		ssa10 = asv_tbl_info.disp_ssa10;
+		ssa11 = asv_tbl_info.disp_ssa11;
+		ssa0 = asv_tbl_info.disp_ssa0;
+		subgrp_index = 5;
+		table = pwrcal_cam_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
+		break;
+	case cal_asv_dvfs_disp:
+		asv = get_asv_group(cal_asv_dvfs_disp, lv);
+		ssa10 = asv_tbl_info.disp_ssa10;
+		ssa11 = asv_tbl_info.disp_ssa11;
+		ssa0 = asv_tbl_info.disp_ssa0;
+		subgrp_index = 2;
+		table = pwrcal_disp_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
+		break;
+	default:
+		BUG();	/* Never reach */
+		break;
+	}
+
+	volt = table[asv];
+	if (lv < subgrp_index) {
+		volt += 12500 * ssa10;
+		if (ssa10 == 3)
+			volt += 12500;
+	} else {
+		volt += 12500 * ssa11;
+		if (ssa11 == 3)
+			volt += 12500;
+	}
+
+	if (volt < 575000 + ssa0 * 25000)
+		volt = 575000 + ssa0 * 25000;
+
+	return volt;
+}
+
+static int dvfsbig_get_asv_table(unsigned int *table)
+{
+	int lv, max_lv;
+
+	max_lv = asv_dvfs_big->table->num_of_lv;
+
+	for (lv = 0; lv < max_lv; lv++)
+		table[lv] = get_asv_voltage(cal_asv_dvfs_big, lv);
+
+	return max_lv;
+}
+
+static int dvfslittle_get_asv_table(unsigned int *table)
+{
+	int lv, max_lv;
+
+	max_lv = asv_dvfs_little->table->num_of_lv;
+
+	for (lv = 0; lv < max_lv; lv++)
+		table[lv] = get_asv_voltage(cal_asv_dvfs_little, lv);
+
+	return max_lv;
+}
+
+static int dvfsg3d_get_asv_table(unsigned int *table)
+{
+	int lv, max_lv;
+
+	max_lv = asv_dvfs_g3d->table->num_of_lv;
+
+	for (lv = 0; lv < max_lv; lv++)
+		table[lv] = get_asv_voltage(cal_asv_dvfs_g3d, lv);
+
+	return max_lv;
+}
+
+static int dvfsmif_get_asv_table(unsigned int *table)
+{
+	int lv, max_lv;
+
+	max_lv = asv_dvfs_mif->table->num_of_lv;
+
+	for (lv = 0; lv < max_lv; lv++)
+		table[lv] = get_asv_voltage(cal_asv_dvfs_mif, lv);
+
+	return max_lv;
+}
+
+static int dvfsint_get_asv_table(unsigned int *table)
+{
+	int lv, max_lv;
+
+	max_lv = asv_dvfs_int->table->num_of_lv;
+
+	for (lv = 0; lv < max_lv; lv++)
+		table[lv] = get_asv_voltage(cal_asv_dvfs_int, lv);
+
+	return max_lv;
+}
+
+static int dvfscam_get_asv_table(unsigned int *table)
+{
+	int lv, max_lv;
+
+	max_lv = asv_dvfs_cam->table->num_of_lv;
+
+	for (lv = 0; lv < max_lv; lv++)
+		table[lv] = get_asv_voltage(cal_asv_dvfs_cam, lv);
+
+	return max_lv;
+}
+
+static int dvfsdisp_get_asv_table(unsigned int *table)
+{
+	int lv, max_lv;
+
+	max_lv = asv_dvfs_disp->table->num_of_lv;
+
+	for (lv = 0; lv < max_lv; lv++)
+		table[lv] = get_asv_voltage(cal_asv_dvfs_disp, lv);
+
+	return max_lv;
+}
+
+static int dfsg3d_set_ema(unsigned int volt)
+{
+	if (volt > 750000)
+		pwrcal_writel(EMA_RF2_UHD_CON, asv_tbl_info.g3d_mcs0);
+	else
+		pwrcal_writel(EMA_RF2_UHD_CON, asv_tbl_info.g3d_mcs1);
+
+	return 0;
+}
+
+static int asv_rcc_set_table(void)
+{
+	int i;
+	int lv, max_lv, asv;
+	unsigned int *p;
+	unsigned long tmp;
+
+	if (!apm_sram_base) {
+#ifdef PWRCAL_TARGET_LINUX
+		apm_sram_base = (void *)ioremap(APM_TABLE_BASE, SZ_4K);
+#else
+		apm_sram_base = (void *)APM_TABLE_BASE;
+#endif
+	}
+
+	p = (unsigned int *)(apm_sram_base);
+	for (i = 0; i < 8; i++) {
+#ifdef PWRCAL_TARGET_LINUX
+		exynos_smc_readsfr((unsigned long)(APM_OTP_ADDRESS + 0x4 * i), &tmp);
+#else
+#if (CONFIG_STARTUP_EL_MODE == STARTUP_EL3)
+		tmp = *((volatile unsigned int *)(unsigned long)(APM_OTP_ADDRESS + 0x4 * i));
+#else
+		smc_readsfr((unsigned long)(APM_OTP_ADDRESS + 0x4 * i), &tmp);
+#endif
+#endif
+		*(p + i) = (unsigned int)tmp;
+	}
+
+	p = (unsigned int *)(apm_sram_base + 0x0030);
+	max_lv = asv_dvfs_big->table->num_of_lv;
+	if (max_lv > 25)
+		max_lv = 25;
+	for (lv = 0; lv < max_lv; lv++) {
+		asv = get_asv_group(cal_asv_dvfs_big, lv);
+		*(p + lv) = pwrcal_big_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv];
+	}
+
+	p = (unsigned int *)(apm_sram_base + 0x0098);
+	max_lv = asv_dvfs_little->table->num_of_lv;
+	if (max_lv > 20)
+		max_lv = 20;
+	for (lv = 0; lv < max_lv; lv++) {
+		asv = get_asv_group(cal_asv_dvfs_little, lv);
+		*(p + lv) = pwrcal_little_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv];
+	}
+
+	p = (unsigned int *)(apm_sram_base + 0x00EC);
+	max_lv = asv_dvfs_g3d->table->num_of_lv;
+	if (max_lv > 11)
+		max_lv = 11;
+	for (lv = 0; lv < max_lv; lv++) {
+		asv = get_asv_group(cal_asv_dvfs_g3d, lv);
+		*(p + lv) = pwrcal_g3d_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv];
+	}
+
+	p = (unsigned int *)(apm_sram_base + 0x011C);
+	max_lv = asv_dvfs_mif->table->num_of_lv;
+	if (max_lv > 16)
+		max_lv = 16;
+	for (lv = 0; lv < max_lv; lv++) {
+		asv = get_asv_group(cal_asv_dvfs_mif, lv);
+		*(p + lv) = pwrcal_mif_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv];
+	}
+
+	return 0;
+}
+
+static void asv_voltage_init_table(struct asv_table_list **asv_table, struct pwrcal_vclk_dfs *dfs)
+{
+	int i, j, k;
+	void *asv_block, *margin_block;
+	struct ect_voltage_domain *domain;
+	struct ect_voltage_table *table;
+	struct asv_table_entry *asv_entry;
+	struct ect_margin_domain *margin_domain = NULL;
+
+	asv_block = ect_get_block("ASV");
+	if (asv_block == NULL)
+		return;
+
+	margin_block = ect_get_block("MARGIN");
+
+	domain = ect_asv_get_domain(asv_block, dfs->vclk.name);
+	if (domain == NULL)
+		return;
+
+	if (asv_tbl_info.asv_table_ver >= domain->num_of_table)
+		BUG();
+
+	if (margin_block)
+		margin_domain = ect_margin_get_domain(margin_block, dfs->vclk.name);
+
+	*asv_table = kzalloc(sizeof(struct asv_table_list) * domain->num_of_table, GFP_KERNEL);
+	if (*asv_table == NULL)
+		return;
+
+	for (i = 0; i < domain->num_of_table; ++i) {
+		table = &domain->table_list[i];
+
+		(*asv_table)[i].table_size = domain->num_of_table;
+		(*asv_table)[i].table = kzalloc(sizeof(struct asv_table_entry) * domain->num_of_level, GFP_KERNEL);
+		if ((*asv_table)[i].table == NULL)
+			return;
+
+		for (j = 0; j < domain->num_of_level; ++j) {
+			asv_entry = &(*asv_table)[i].table[j];
+
+			asv_entry->index = domain->level_list[j];
+			asv_entry->voltage = kzalloc(sizeof(unsigned int) * domain->num_of_group, GFP_KERNEL);
+
+			for (k = 0; k < domain->num_of_group; ++k) {
+				if (table->voltages != NULL)
+					asv_entry->voltage[k] = table->voltages[j * domain->num_of_group + k];
+				else if (table->voltages_step != NULL)
+					asv_entry->voltage[k] = table->voltages_step[j * domain->num_of_group + k] * table->volt_step;
+
+				if (margin_domain != NULL) {
+					if (margin_domain->offset != NULL)
+						asv_entry->voltage[k] += margin_domain->offset[j * margin_domain->num_of_group + k];
+					else
+						asv_entry->voltage[k] += margin_domain->offset_compact[j * margin_domain->num_of_group + k] * margin_domain->volt_step;
+				}
+			}
+		}
+	}
+}
+
+static void asv_rcc_init_table(struct asv_table_list **rcc_table, struct pwrcal_vclk_dfs *dfs)
+
+{
+	int i, j, k;
+	void *rcc_block;
+	struct ect_rcc_domain *domain;
+	struct ect_rcc_table *table;
+	struct asv_table_entry *rcc_entry;
+
+	rcc_block = ect_get_block("RCC");
+	if (rcc_block == NULL)
+		return;
+
+	domain = ect_rcc_get_domain(rcc_block, dfs->vclk.name);
+	if (domain == NULL)
+		return;
+
+	*rcc_table = kzalloc(sizeof(struct asv_table_list) * domain->num_of_table, GFP_KERNEL);
+	if (*rcc_table == NULL)
+		return;
+
+	for (i = 0; i < domain->num_of_table; ++i) {
+		table = &domain->table_list[i];
+
+		(*rcc_table)[i].table_size = domain->num_of_table;
+		(*rcc_table)[i].table = kzalloc(sizeof(struct asv_table_entry) * domain->num_of_level, GFP_KERNEL);
+		if ((*rcc_table)[i].table == NULL)
+			return;
+
+		for (j = 0; j < domain->num_of_level; ++j) {
+			rcc_entry = &(*rcc_table)[i].table[j];
+
+			rcc_entry->index = domain->level_list[j];
+			rcc_entry->voltage = kzalloc(sizeof(unsigned int) * domain->num_of_group, GFP_KERNEL);
+
+			for (k = 0; k < domain->num_of_group; ++k) {
+				if (table->rcc != NULL)
+					rcc_entry->voltage[k] = table->rcc[j * domain->num_of_group + k];
+				else
+					rcc_entry->voltage[k] = table->rcc_compact[j * domain->num_of_group + k];
+			}
+		}
+	}
+}
+
+static void asv_voltage_table_init(void)
+{
+	asv_voltage_init_table(&pwrcal_big_asv_table, asv_dvfs_big);
+	asv_voltage_init_table(&pwrcal_little_asv_table, asv_dvfs_little);
+	asv_voltage_init_table(&pwrcal_g3d_asv_table, asv_dvfs_g3d);
+	asv_voltage_init_table(&pwrcal_mif_asv_table, asv_dvfs_mif);
+	asv_voltage_init_table(&pwrcal_int_asv_table, asv_dvfs_int);
+	asv_voltage_init_table(&pwrcal_cam_asv_table, asv_dvfs_cam);
+	asv_voltage_init_table(&pwrcal_disp_asv_table, asv_dvfs_disp);
+}
+
+static void asv_rcc_table_init(void)
+{
+	asv_rcc_init_table(&pwrcal_big_rcc_table, asv_dvfs_big);
+	asv_rcc_init_table(&pwrcal_little_rcc_table, asv_dvfs_little);
+	asv_rcc_init_table(&pwrcal_g3d_rcc_table, asv_dvfs_g3d);
+	asv_rcc_init_table(&pwrcal_mif_rcc_table, asv_dvfs_mif);
+}
+
+static int asv_init(void)
+{
+	struct vclk *vclk;
+
+	vclk = cal_get_vclk(dvfs_big);
+	asv_dvfs_big = to_dfs(vclk);
+	asv_dvfs_big->dfsops->get_asv_table = dvfsbig_get_asv_table;
+/*	asv_dvfs_big->dfsops->set_ema = dvfsbig_set_ema;
+*/
+	vclk = cal_get_vclk(dvfs_little);
+	asv_dvfs_little = to_dfs(vclk);
+	asv_dvfs_little->dfsops->get_asv_table = dvfslittle_get_asv_table;
+/*	asv_dvfs_little->dfsops->set_ema = dvfslittle_set_ema;
+*/
+	vclk = cal_get_vclk(dvfs_g3d);
+	asv_dvfs_g3d = to_dfs(vclk);
+	asv_dvfs_g3d->dfsops->get_asv_table = dvfsg3d_get_asv_table;
+	asv_dvfs_g3d->dfsops->set_ema = dfsg3d_set_ema;
+
+	vclk = cal_get_vclk(dvfs_mif);
+	asv_dvfs_mif = to_dfs(vclk);
+	asv_dvfs_mif->dfsops->get_asv_table = dvfsmif_get_asv_table;
+
+	vclk = cal_get_vclk(dvfs_int);
+	asv_dvfs_int = to_dfs(vclk);
+	asv_dvfs_int->dfsops->get_asv_table = dvfsint_get_asv_table;
+/*	asv_dvfs_int->dfsops->set_ema = dvfsint_set_ema;
+*/
+	vclk = cal_get_vclk(dvfs_cam);
+	asv_dvfs_cam = to_dfs(vclk);
+	asv_dvfs_cam->dfsops->get_asv_table = dvfscam_get_asv_table;
+
+	vclk = cal_get_vclk(dvfs_disp);
+	asv_dvfs_disp = to_dfs(vclk);
+	asv_dvfs_disp->dfsops->get_asv_table = dvfsdisp_get_asv_table;
+
+	pwrcal_big_asv_table = NULL;
+	pwrcal_little_asv_table = NULL;
+	pwrcal_g3d_asv_table = NULL;
+	pwrcal_mif_asv_table = NULL;
+	pwrcal_int_asv_table = NULL;
+	pwrcal_cam_asv_table = NULL;
+	pwrcal_disp_asv_table = NULL;
+
+	pwrcal_big_rcc_table = NULL;
+	pwrcal_little_rcc_table = NULL;
+	pwrcal_g3d_rcc_table = NULL;
+	pwrcal_mif_rcc_table = NULL;
+
+	asv_get_asvinfo();
+	asv_voltage_table_init();
+	asv_rcc_table_init();
+
+	return 0;
+}
+
+static void asv_print_info(void)
+{
+	pr_info("asv_table_ver : %d\n", asv_tbl_info.asv_table_ver);
+	pr_info("fused_grp : %d\n", asv_tbl_info.fused_grp);
+
+	pr_info("mngs_asv_group : %d\n", asv_tbl_info.mngs_asv_group);
+	pr_info("mngs_modified_group : %d\n", asv_tbl_info.mngs_modified_group);
+	pr_info("apollo_asv_group : %d\n", asv_tbl_info.apollo_asv_group);
+	pr_info("apollo_modified_group : %d\n", asv_tbl_info.apollo_modified_group);
+
+	pr_info("g3d_asv_group : %d\n", asv_tbl_info.g3d_asv_group);
+	pr_info("g3d_modified_group : %d\n", asv_tbl_info.g3d_modified_group);
+	pr_info("mif_asv_group : %d\n", asv_tbl_info.mif_asv_group);
+	pr_info("mif_modified_group : %d\n", asv_tbl_info.mif_modified_group);
+
+	pr_info("int_asv_group : %d\n", asv_tbl_info.int_asv_group);
+	pr_info("int_modified_group : %d\n", asv_tbl_info.int_modified_group);
+	pr_info("disp_asv_group : %d\n", asv_tbl_info.disp_asv_group);
+	pr_info("disp_modified_group : %d\n", asv_tbl_info.disp_modified_group);
+
+	pr_info("g3d_mcs0 : %d\n", asv_tbl_info.g3d_mcs0);
+	pr_info("g3d_mcs1 : %d\n", asv_tbl_info.g3d_mcs1);
+}
+
+static void rcc_print_info(void)
+{
+	int lv, max_lv, asv;
+
+	pr_info("==== RCC Table ====\n");
+	max_lv = asv_dvfs_big->table->num_of_lv;
+	if (max_lv > 25)
+		max_lv = 25;
+	for (lv = 0; lv < max_lv; lv++) {
+		asv = get_asv_group(cal_asv_dvfs_big, lv);
+		pr_info("big rcc [%d] : %d\n", lv, pwrcal_big_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv]);
+	}
+
+	max_lv = asv_dvfs_little->table->num_of_lv;
+	if (max_lv > 20)
+		max_lv = 20;
+	for (lv = 0; lv < max_lv; lv++) {
+		asv = get_asv_group(cal_asv_dvfs_little, lv);
+		pr_info("little rcc [%d] : %d\n", lv, pwrcal_little_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv]);
+	}
+
+	max_lv = asv_dvfs_g3d->table->num_of_lv;
+	if (max_lv > 11)
+		max_lv = 11;
+	for (lv = 0; lv < max_lv; lv++) {
+		asv = get_asv_group(cal_asv_dvfs_g3d, lv);
+		pr_info("g3d rcc [%d] : %d\n", lv, pwrcal_g3d_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv]);
+	}
+
+	max_lv = asv_dvfs_mif->table->num_of_lv;
+	if (max_lv > 16)
+		max_lv = 16;
+	for (lv = 0; lv < max_lv; lv++) {
+		asv = get_asv_group(cal_asv_dvfs_mif, lv);
+		pr_info("mif rcc [%d] : %d\n", lv, pwrcal_mif_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv]);
+	}
+}
+
+struct cal_asv_ops cal_asv_ops = {
+	.print_asv_info = asv_print_info,
+	.print_rcc_info = rcc_print_info,
+	.set_grp = asv_set_grp,
+	.set_tablever = asv_set_tablever,
+	.set_rcc_table = asv_rcc_set_table,
+	.asv_init = asv_init,
+};

drivers/soc/samsung/pwrcal/S5E8890/S5E8890-drampara.c

@@ -0,0 +1,502 @@
+#include "../pwrcal-env.h"
+#include "../pwrcal-rae.h"
+#include "S5E8890-sfrbase.h"
+#include "S5E8890-vclk-internal.h"
+
+#ifdef PWRCAL_TARGET_LINUX
+#include <soc/samsung/ect_parser.h>
+#else
+#include <mach/ect_parser.h>
+#endif
+
+#ifndef MHZ
+#define MHZ		((unsigned long long)1000000)
+#endif
+
+#define __SMC_ALL				(DMC_MISC_CCORE_BASE + 0x8000)
+#define __PHY_ALL				(DMC_MISC_CCORE_BASE + 0x4000)
+#define __DMC_MISC_ALL			(DMC_MISC_CCORE_BASE + 0x0000)
+
+#define ModeRegAddr				((void *)(__SMC_ALL + 0x0000))
+#define MprMrCtl				((void *)(__SMC_ALL + 0x0004))
+#define ModeRegWrData			((void *)(__SMC_ALL + 0x0008))
+
+#define DramTiming0_0			((void *)(__SMC_ALL + 0x0058))
+#define DramTiming1_0			((void *)(__SMC_ALL + 0x005C))
+#define DramTiming2_0			((void *)(__SMC_ALL + 0x0060))
+#define DramTiming3_0			((void *)(__SMC_ALL + 0x0064))
+#define DramTiming4_0			((void *)(__SMC_ALL + 0x0068))
+#define DramTiming5_0			((void *)(__SMC_ALL + 0x006C))
+#define DramTiming6_0			((void *)(__SMC_ALL + 0x0070))
+#define DramTiming7_0			((void *)(__SMC_ALL + 0x0074))
+#define DramTiming8_0			((void *)(__SMC_ALL + 0x0078))
+#define DramTiming9_0			((void *)(__SMC_ALL + 0x007C))
+#define DramDerateTiming0_0		((void *)(__SMC_ALL + 0x0088))
+#define DramDerateTiming1_0		((void *)(__SMC_ALL + 0x008C))
+#define Dimm0AutoRefTiming1_0	((void *)(__SMC_ALL + 0x009C))
+#define Dimm1AutoRefTiming1_0	((void *)(__SMC_ALL + 0x00A4))
+#define AutoRefTiming2_0		((void *)(__SMC_ALL + 0x00A8))
+#define PwrMgmtTiming0_0		((void *)(__SMC_ALL + 0x00B8))
+#define PwrMgmtTiming1_0		((void *)(__SMC_ALL + 0x00BC))
+#define PwrMgmtTiming2_0		((void *)(__SMC_ALL + 0x00C0))
+#define PwrMgmtTiming3_0		((void *)(__SMC_ALL + 0x00C4))
+#define TmrTrnInterval_0		((void *)(__SMC_ALL + 0x00C8))
+#define DvfsTrnCtl_0			((void *)(__SMC_ALL + 0x00CC))
+#define TrnTiming0_0			((void *)(__SMC_ALL + 0x00D0))
+#define TrnTiming1_0			((void *)(__SMC_ALL + 0x00D4))
+#define TrnTiming2_0			((void *)(__SMC_ALL + 0x00D8))
+#define DFIDelay1_0				((void *)(__SMC_ALL + 0x00E0))
+#define DFIDelay2_0				((void *)(__SMC_ALL + 0x00E4))
+
+#define DramTiming0_1			((void *)(__SMC_ALL + 0x0108))
+#define DramTiming1_1			((void *)(__SMC_ALL + 0x010C))
+#define DramTiming2_1			((void *)(__SMC_ALL + 0x0110))
+#define DramTiming3_1			((void *)(__SMC_ALL + 0x0114))
+#define DramTiming4_1			((void *)(__SMC_ALL + 0x0118))
+#define DramTiming5_1			((void *)(__SMC_ALL + 0x011C))
+#define DramTiming6_1			((void *)(__SMC_ALL + 0x0120))
+#define DramTiming7_1			((void *)(__SMC_ALL + 0x0124))
+#define DramTiming8_1			((void *)(__SMC_ALL + 0x0128))
+#define DramTiming9_1			((void *)(__SMC_ALL + 0x012C))
+#define DramDerateTiming0_1		((void *)(__SMC_ALL + 0x0138))
+#define DramDerateTiming1_1		((void *)(__SMC_ALL + 0x013C))
+#define Dimm0AutoRefTiming1_1	((void *)(__SMC_ALL + 0x014C))
+#define Dimm1AutoRefTiming1_1	((void *)(__SMC_ALL + 0x0154))
+#define AutoRefTiming2_1		((void *)(__SMC_ALL + 0x0158))
+#define PwrMgmtTiming0_1		((void *)(__SMC_ALL + 0x0168))
+#define PwrMgmtTiming1_1		((void *)(__SMC_ALL + 0x016C))
+#define PwrMgmtTiming2_1		((void *)(__SMC_ALL + 0x0170))
+#define PwrMgmtTiming3_1		((void *)(__SMC_ALL + 0x0174))
+#define TmrTrnInterval_1		((void *)(__SMC_ALL + 0x0178))
+#define DvfsTrnCtl_1			((void *)(__SMC_ALL + 0x017C))
+#define TrnTiming0_1			((void *)(__SMC_ALL + 0x0180))
+#define TrnTiming1_1			((void *)(__SMC_ALL + 0x0184))
+#define TrnTiming2_1			((void *)(__SMC_ALL + 0x0188))
+#define DFIDelay1_1				((void *)(__SMC_ALL + 0x0190))
+#define DFIDelay2_1				((void *)(__SMC_ALL + 0x0194))
+
+#define PHY_DVFS_CON_CH0		((void *)(LPDDR4_PHY0_BASE + 0x00B8))
+#define PHY_DVFS_CON			((void *)(__PHY_ALL + 0x00B8))
+#define PHY_DVFS0_CON0			((void *)(__PHY_ALL + 0x00BC))
+#define PHY_DVFS0_CON1			((void *)(__PHY_ALL + 0x00C4))
+#define PHY_DVFS0_CON2			((void *)(__PHY_ALL + 0x00CC))
+#define PHY_DVFS0_CON3			((void *)(__PHY_ALL + 0x00D4))
+#define PHY_DVFS0_CON4			((void *)(__PHY_ALL + 0x00DC))
+
+#define PHY_DVFS1_CON0			((void *)(__PHY_ALL + 0x00C0))
+#define PHY_DVFS1_CON1			((void *)(__PHY_ALL + 0x00C8))
+#define PHY_DVFS1_CON2			((void *)(__PHY_ALL + 0x00D0))
+#define PHY_DVFS1_CON3			((void *)(__PHY_ALL + 0x00D8))
+#define PHY_DVFS1_CON4			((void *)(__PHY_ALL + 0x00E0))
+
+#define DMC_MISC_CON0			((void *)(__DMC_MISC_ALL + 0x0014))
+#define DMC_MISC_CON1			((void *)(__DMC_MISC_ALL + 0x003C))
+#define MRS_DATA1				((void *)(__DMC_MISC_ALL + 0x0054))
+
+enum mif_timing_set_idx {
+	MIF_TIMING_SET_0,
+	MIF_TIMING_SET_1
+};
+
+enum smc_dram_mode_register {
+	DRAM_MR0,
+	DRAM_MR1,
+	DRAM_MR2,
+	DRAM_MR3,
+	DRAM_MR4,
+	DRAM_MR5,
+	DRAM_MR6,
+	DRAM_MR7,
+	DRAM_MR8,
+	DRAM_MR9,
+	DRAM_MR10,
+	DRAM_MR11,
+	DRAM_MR12,
+	DRAM_MR13,
+	DRAM_MR14,
+	DRAM_MR15,
+	DRAM_MR16,
+	DRAM_MR17,
+	DRAM_MR18,
+	DRAM_MR19,
+	DRAM_MR20,
+	DRAM_MR21,
+	DRAM_MR22,
+	DRAM_MR23,
+	DRAM_MR24,
+	DRAM_MR25,
+	DRAM_MR32 = 32,
+	DRAM_MR40 = 40,
+};
+
+enum timing_parameter_column {
+	DramTiming0,
+	DramTiming1,
+	DramTiming2,
+	DramTiming3,
+	DramTiming4,
+	DramTiming5,
+	DramTiming6,
+	DramTiming7,
+	DramTiming8,
+	DramTiming9,
+	DramDerateTiming0,
+	DramDerateTiming1,
+	Dimm0AutoRefTiming1,
+	Dimm1AutoRefTiming1,
+	AutoRefTiming2,
+	PwrMgmtTiming0,
+	PwrMgmtTiming1,
+	PwrMgmtTiming2,
+	PwrMgmtTiming3,
+	TmrTrnInterval,
+	DFIDelay1,
+	DFIDelay2,
+	DvfsTrnCtl,
+	TrnTiming0,
+	TrnTiming1,
+	TrnTiming2,
+	DVFSn_CON0,
+	DVFSn_CON1,
+	DVFSn_CON2,
+	DVFSn_CON3,
+	DVFSn_CON4,
+	DirectCmd_MR1,
+	DirectCmd_MR2,
+	DirectCmd_MR3,
+	DirectCmd_MR11,
+	DirectCmd_MR12,
+	DirectCmd_MR14,
+	DirectCmd_MR22,
+
+	num_of_g_smc_dfs_table_column = TrnTiming2 - DramTiming0 + 1,
+	num_of_g_phy_dfs_table_column = DVFSn_CON4 - DVFSn_CON0 + 1,
+	num_of_g_dram_dfs_table_column = DirectCmd_MR22 - DirectCmd_MR1 + 1,
+	num_of_dram_parameter = num_of_g_smc_dfs_table_column + num_of_g_phy_dfs_table_column + num_of_g_dram_dfs_table_column,
+};
+
+struct smc_dfs_table {
+	unsigned int DramTiming0;
+	unsigned int DramTiming1;
+	unsigned int DramTiming2;
+	unsigned int DramTiming3;
+	unsigned int DramTiming4;
+	unsigned int DramTiming5;
+	unsigned int DramTiming6;
+	unsigned int DramTiming7;
+	unsigned int DramTiming8;
+	unsigned int DramTiming9;
+	unsigned int DramDerateTiming0;
+	unsigned int DramDerateTiming1;
+	unsigned int Dimm0AutoRefTiming1;
+	unsigned int Dimm1AutoRefTiming1;
+	unsigned int AutoRefTiming2;
+	unsigned int PwrMgmtTiming0;
+	unsigned int PwrMgmtTiming1;
+	unsigned int PwrMgmtTiming2;
+	unsigned int PwrMgmtTiming3;
+	unsigned int TmrTrnInterval;
+	unsigned int DFIDelay1;
+	unsigned int DFIDelay2;
+	unsigned int DvfsTrnCtl;
+	unsigned int TrnTiming0;
+	unsigned int TrnTiming1;
+	unsigned int TrnTiming2;
+};
+
+struct phy_dfs_table {
+	unsigned int DVFSn_CON0;
+	unsigned int DVFSn_CON1;
+	unsigned int DVFSn_CON2;
+	unsigned int DVFSn_CON3;
+	unsigned int DVFSn_CON4;
+};
+
+struct dram_dfs_table {
+	unsigned int DirectCmd_MR1;
+	unsigned int DirectCmd_MR2;
+	unsigned int DirectCmd_MR3;
+	unsigned int DirectCmd_MR11;
+	unsigned int DirectCmd_MR12;
+	unsigned int DirectCmd_MR14;
+	unsigned int DirectCmd_MR22;
+};
+
+static struct smc_dfs_table *g_smc_dfs_table;
+static struct phy_dfs_table *g_phy_dfs_table;
+static struct dram_dfs_table *g_dram_dfs_table;
+static unsigned long long *mif_freq_to_level;
+static int num_mif_freq_to_level;
+
+
+static const unsigned long long mif_freq_to_level_switch[] = {
+/* BUS3_PLL SW 936 */	936 * MHZ,
+/* BUS0_PLL SW 468 */	468 * MHZ
+};
+
+void dmc_misc_direct_dmc_enable(int enable)
+{
+	pwrcal_writel(DMC_MISC_CON0, (enable<<24)|(0x2<<20));
+}
+
+void smc_mode_register_write(int mr, int op)
+{
+	pwrcal_writel(ModeRegAddr, ((0x3<<28)|(mr<<20)));
+	pwrcal_writel(ModeRegWrData, op);
+	pwrcal_writel(MprMrCtl, 0x10);
+}
+
+static unsigned int convert_to_level(unsigned long long freq)
+{
+	int idx;
+	int tablesize = num_mif_freq_to_level;
+
+	for (idx = tablesize - 1; idx >= 0; idx--)
+		if (freq <= mif_freq_to_level[idx])
+			return (unsigned int)idx;
+
+	return 0;
+}
+
+static unsigned int convert_to_level_switch(unsigned long long freq)
+{
+	int idx;
+	int tablesize = sizeof(mif_freq_to_level_switch) / sizeof(mif_freq_to_level_switch[0]);
+
+	for (idx = tablesize - 1; idx >= 0; idx--)
+		if (freq <= mif_freq_to_level_switch[idx])
+			return (unsigned int)idx;
+
+	return 0;
+}
+
+void pwrcal_dmc_set_dvfs(unsigned long long target_mif_freq, unsigned int timing_set_idx)
+{
+	unsigned int uReg;
+	unsigned int target_mif_level_idx, target_mif_level_switch_idx;
+	unsigned int mr13;
+
+	target_mif_level_idx = convert_to_level(target_mif_freq);
+
+	target_mif_level_switch_idx = convert_to_level_switch(target_mif_freq);
+
+	target_mif_level_switch_idx += num_mif_freq_to_level;
+
+	/* 1. Configure parameter */
+	if (timing_set_idx == MIF_TIMING_SET_0) {
+		pwrcal_writel(DMC_MISC_CON1, 0x0);	//timing_set_sw_r=0x0
+
+		pwrcal_writel(DramTiming0_0, g_smc_dfs_table[target_mif_level_idx].DramTiming0);
+		pwrcal_writel(DramTiming1_0, g_smc_dfs_table[target_mif_level_idx].DramTiming1);
+		pwrcal_writel(DramTiming2_0, g_smc_dfs_table[target_mif_level_idx].DramTiming2);
+		pwrcal_writel(DramTiming3_0, g_smc_dfs_table[target_mif_level_idx].DramTiming3);
+		pwrcal_writel(DramTiming4_0, g_smc_dfs_table[target_mif_level_idx].DramTiming4);
+		pwrcal_writel(DramTiming5_0, g_smc_dfs_table[target_mif_level_idx].DramTiming5);
+		pwrcal_writel(DramTiming6_0, g_smc_dfs_table[target_mif_level_idx].DramTiming6);
+		pwrcal_writel(DramTiming7_0, g_smc_dfs_table[target_mif_level_idx].DramTiming7);
+		pwrcal_writel(DramTiming8_0, g_smc_dfs_table[target_mif_level_idx].DramTiming8);
+		pwrcal_writel(DramTiming9_0, g_smc_dfs_table[target_mif_level_idx].DramTiming9);
+		pwrcal_writel(DramDerateTiming0_0, g_smc_dfs_table[target_mif_level_idx].DramDerateTiming0);
+		pwrcal_writel(DramDerateTiming1_0, g_smc_dfs_table[target_mif_level_idx].DramDerateTiming1);
+		pwrcal_writel(Dimm0AutoRefTiming1_0, g_smc_dfs_table[target_mif_level_idx].Dimm0AutoRefTiming1);
+		pwrcal_writel(Dimm1AutoRefTiming1_0, g_smc_dfs_table[target_mif_level_idx].Dimm1AutoRefTiming1);
+		pwrcal_writel(AutoRefTiming2_0, g_smc_dfs_table[target_mif_level_idx].AutoRefTiming2);
+		pwrcal_writel(PwrMgmtTiming0_0, g_smc_dfs_table[target_mif_level_idx].PwrMgmtTiming0);
+		pwrcal_writel(PwrMgmtTiming1_0, g_smc_dfs_table[target_mif_level_idx].PwrMgmtTiming1);
+		pwrcal_writel(PwrMgmtTiming2_0, g_smc_dfs_table[target_mif_level_idx].PwrMgmtTiming2);
+		pwrcal_writel(PwrMgmtTiming3_0, g_smc_dfs_table[target_mif_level_idx].PwrMgmtTiming3);
+		pwrcal_writel(TmrTrnInterval_0, g_smc_dfs_table[target_mif_level_idx].TmrTrnInterval);
+		pwrcal_writel(DFIDelay1_0, g_smc_dfs_table[target_mif_level_idx].DFIDelay1);
+		pwrcal_writel(DFIDelay2_0, g_smc_dfs_table[target_mif_level_idx].DFIDelay2);
+		pwrcal_writel(DvfsTrnCtl_0, g_smc_dfs_table[target_mif_level_idx].DvfsTrnCtl);
+		pwrcal_writel(TrnTiming0_0, g_smc_dfs_table[target_mif_level_idx].TrnTiming0);
+		pwrcal_writel(TrnTiming1_0, g_smc_dfs_table[target_mif_level_idx].TrnTiming1);
+		pwrcal_writel(TrnTiming2_0, g_smc_dfs_table[target_mif_level_idx].TrnTiming2);
+
+		uReg = pwrcal_readl((void *)PHY_DVFS_CON_CH0);
+		uReg &= ~(0x3<<30);
+		uReg |= (0x1<<30);	//0x1 = DVFS 1 mode
+		pwrcal_writel(PHY_DVFS_CON, uReg);
+
+		pwrcal_writel(PHY_DVFS0_CON0, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON0);
+		pwrcal_writel(PHY_DVFS0_CON1, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON1);
+		pwrcal_writel(PHY_DVFS0_CON2, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON2);
+		pwrcal_writel(PHY_DVFS0_CON3, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON3);
+		pwrcal_writel(PHY_DVFS0_CON4, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON4);
+
+		mr13 = (0x1<<7)|(0x0<<6)|(0x0<<5)|(0x1<<3);	//FSP-OP=0x1, FSP-WR=0x0, DMD=0x0, VRCG=0x1
+		smc_mode_register_write(DRAM_MR13, mr13);
+		smc_mode_register_write(DRAM_MR1, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR1);
+		smc_mode_register_write(DRAM_MR2, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR2);
+		smc_mode_register_write(DRAM_MR3, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR3);
+		smc_mode_register_write(DRAM_MR11, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR11);
+		smc_mode_register_write(DRAM_MR12, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR12);
+		smc_mode_register_write(DRAM_MR14, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR14);
+		smc_mode_register_write(DRAM_MR22, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR22);
+
+		mr13 &= ~(0x1<<7);	// clear FSP-OP[7]
+		pwrcal_writel(MRS_DATA1, mr13);
+	} else if (timing_set_idx == MIF_TIMING_SET_1) {
+		pwrcal_writel(DMC_MISC_CON1, 0x1);	//timing_set_sw_r=0x1
+
+		pwrcal_writel(DramTiming0_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming0);
+		pwrcal_writel(DramTiming1_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming1);
+		pwrcal_writel(DramTiming2_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming2);
+		pwrcal_writel(DramTiming3_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming3);
+		pwrcal_writel(DramTiming4_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming4);
+		pwrcal_writel(DramTiming5_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming5);
+		pwrcal_writel(DramTiming6_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming6);
+		pwrcal_writel(DramTiming7_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming7);
+		pwrcal_writel(DramTiming8_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming8);
+		pwrcal_writel(DramTiming9_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming9);
+		pwrcal_writel(DramDerateTiming0_1, g_smc_dfs_table[target_mif_level_switch_idx].DramDerateTiming0);
+		pwrcal_writel(DramDerateTiming1_1, g_smc_dfs_table[target_mif_level_switch_idx].DramDerateTiming1);
+		pwrcal_writel(Dimm0AutoRefTiming1_1, g_smc_dfs_table[target_mif_level_switch_idx].Dimm0AutoRefTiming1);
+		pwrcal_writel(Dimm1AutoRefTiming1_1, g_smc_dfs_table[target_mif_level_switch_idx].Dimm1AutoRefTiming1);
+		pwrcal_writel(AutoRefTiming2_1, g_smc_dfs_table[target_mif_level_switch_idx].AutoRefTiming2);
+		pwrcal_writel(PwrMgmtTiming0_1, g_smc_dfs_table[target_mif_level_switch_idx].PwrMgmtTiming0);
+		pwrcal_writel(PwrMgmtTiming1_1, g_smc_dfs_table[target_mif_level_switch_idx].PwrMgmtTiming1);
+		pwrcal_writel(PwrMgmtTiming2_1, g_smc_dfs_table[target_mif_level_switch_idx].PwrMgmtTiming2);
+		pwrcal_writel(PwrMgmtTiming3_1, g_smc_dfs_table[target_mif_level_switch_idx].PwrMgmtTiming3);
+		pwrcal_writel(TmrTrnInterval_1, g_smc_dfs_table[target_mif_level_switch_idx].TmrTrnInterval);
+		pwrcal_writel(DFIDelay1_1, g_smc_dfs_table[target_mif_level_switch_idx].DFIDelay1);
+		pwrcal_writel(DFIDelay2_1, g_smc_dfs_table[target_mif_level_switch_idx].DFIDelay2);
+		pwrcal_writel(DvfsTrnCtl_1, g_smc_dfs_table[target_mif_level_switch_idx].DvfsTrnCtl);
+		pwrcal_writel(TrnTiming0_1, g_smc_dfs_table[target_mif_level_switch_idx].TrnTiming0);
+		pwrcal_writel(TrnTiming1_1, g_smc_dfs_table[target_mif_level_switch_idx].TrnTiming1);
+		pwrcal_writel(TrnTiming2_1, g_smc_dfs_table[target_mif_level_switch_idx].TrnTiming2);
+
+		uReg = pwrcal_readl(PHY_DVFS_CON_CH0);
+		uReg &= ~(0x3<<30);
+		uReg |= (0x2<<30);	//0x2 = DVFS 2 mode
+		pwrcal_writel(PHY_DVFS_CON, uReg);
+
+		pwrcal_writel(PHY_DVFS1_CON0, g_phy_dfs_table[target_mif_level_switch_idx].DVFSn_CON0);
+		pwrcal_writel(PHY_DVFS1_CON1, g_phy_dfs_table[target_mif_level_switch_idx].DVFSn_CON1);
+		pwrcal_writel(PHY_DVFS1_CON2, g_phy_dfs_table[target_mif_level_switch_idx].DVFSn_CON2);
+		pwrcal_writel(PHY_DVFS1_CON3, g_phy_dfs_table[target_mif_level_switch_idx].DVFSn_CON3);
+		pwrcal_writel(PHY_DVFS1_CON4, g_phy_dfs_table[target_mif_level_switch_idx].DVFSn_CON4);
+
+		mr13 = (0x0<<7)|(0x1<<6)|(0x0<<5)|(0x1<<3);	//FSP-OP=0x0, FSP-WR=0x1, DMD=0x0, VRCG=0x1
+		smc_mode_register_write(DRAM_MR13, mr13);
+		smc_mode_register_write(DRAM_MR1, g_dram_dfs_table[target_mif_level_switch_idx].DirectCmd_MR1);
+		smc_mode_register_write(DRAM_MR2, g_dram_dfs_table[target_mif_level_switch_idx].DirectCmd_MR2);
+		smc_mode_register_write(DRAM_MR3, g_dram_dfs_table[target_mif_level_switch_idx].DirectCmd_MR3);
+		smc_mode_register_write(DRAM_MR11, g_dram_dfs_table[target_mif_level_switch_idx].DirectCmd_MR11);
+		smc_mode_register_write(DRAM_MR12, g_dram_dfs_table[target_mif_level_switch_idx].DirectCmd_MR12);
+		smc_mode_register_write(DRAM_MR14, g_dram_dfs_table[target_mif_level_switch_idx].DirectCmd_MR14);
+		smc_mode_register_write(DRAM_MR22, g_dram_dfs_table[target_mif_level_switch_idx].DirectCmd_MR22);
+
+		mr13 &= ~(0x1<<7);	// clear FSP-OP[7]
+		mr13 |= (0x1<<7);	// set FSP-OP[7]=0x1
+		pwrcal_writel(MRS_DATA1, mr13);
+	}	 else {
+		pr_err("wrong DMC timing set selection on DVFS\n");
+		return;
+	}
+}
+
+
+void dfs_dram_param_init(void)
+{
+	int i;
+	void *dram_block;
+	int memory_size = 3; // means 3GB
+	struct ect_timing_param_size *size;
+
+	dram_block = ect_get_block(BLOCK_TIMING_PARAM);
+	if (dram_block == NULL)
+		return;
+
+	size = ect_timing_param_get_size(dram_block, memory_size);
+	if (size == NULL)
+		return;
+
+	if (num_of_g_smc_dfs_table_column + num_of_g_phy_dfs_table_column + num_of_g_dram_dfs_table_column != size->num_of_timing_param)
+		return;
+
+	g_smc_dfs_table = kzalloc(sizeof(struct smc_dfs_table) * num_of_g_smc_dfs_table_column * size->num_of_level, GFP_KERNEL);
+	if (g_smc_dfs_table == NULL)
+		return;
+
+	g_phy_dfs_table = kzalloc(sizeof(struct phy_dfs_table) * num_of_g_phy_dfs_table_column * size->num_of_level, GFP_KERNEL);
+	if (g_phy_dfs_table == NULL)
+		return;
+
+	g_dram_dfs_table = kzalloc(sizeof(struct dram_dfs_table) * num_of_g_dram_dfs_table_column * size->num_of_level, GFP_KERNEL);
+	if (g_dram_dfs_table == NULL)
+		return;
+
+	for (i = 0; i < size->num_of_level; ++i) {
+		g_smc_dfs_table[i].DramTiming0 = size->timing_parameter[i * num_of_dram_parameter + DramTiming0];
+		g_smc_dfs_table[i].DramTiming1 = size->timing_parameter[i * num_of_dram_parameter + DramTiming1];
+		g_smc_dfs_table[i].DramTiming2 = size->timing_parameter[i * num_of_dram_parameter + DramTiming2];
+		g_smc_dfs_table[i].DramTiming3 = size->timing_parameter[i * num_of_dram_parameter + DramTiming3];
+		g_smc_dfs_table[i].DramTiming4 = size->timing_parameter[i * num_of_dram_parameter + DramTiming4];
+		g_smc_dfs_table[i].DramTiming5 = size->timing_parameter[i * num_of_dram_parameter + DramTiming5];
+		g_smc_dfs_table[i].DramTiming6 = size->timing_parameter[i * num_of_dram_parameter + DramTiming6];
+		g_smc_dfs_table[i].DramTiming7 = size->timing_parameter[i * num_of_dram_parameter + DramTiming7];
+		g_smc_dfs_table[i].DramTiming8 = size->timing_parameter[i * num_of_dram_parameter + DramTiming8];
+		g_smc_dfs_table[i].DramTiming9 = size->timing_parameter[i * num_of_dram_parameter + DramTiming9];
+		g_smc_dfs_table[i].DramDerateTiming0 = size->timing_parameter[i * num_of_dram_parameter + DramDerateTiming0];
+		g_smc_dfs_table[i].DramDerateTiming1 = size->timing_parameter[i * num_of_dram_parameter + DramDerateTiming1];
+		g_smc_dfs_table[i].Dimm0AutoRefTiming1 = size->timing_parameter[i * num_of_dram_parameter + Dimm0AutoRefTiming1];
+		g_smc_dfs_table[i].Dimm1AutoRefTiming1 = size->timing_parameter[i * num_of_dram_parameter + Dimm1AutoRefTiming1];
+		g_smc_dfs_table[i].AutoRefTiming2 = size->timing_parameter[i * num_of_dram_parameter + AutoRefTiming2];
+		g_smc_dfs_table[i].PwrMgmtTiming0 = size->timing_parameter[i * num_of_dram_parameter + PwrMgmtTiming0];
+		g_smc_dfs_table[i].PwrMgmtTiming1 = size->timing_parameter[i * num_of_dram_parameter + PwrMgmtTiming1];
+		g_smc_dfs_table[i].PwrMgmtTiming2 = size->timing_parameter[i * num_of_dram_parameter + PwrMgmtTiming2];
+		g_smc_dfs_table[i].PwrMgmtTiming3 = size->timing_parameter[i * num_of_dram_parameter + PwrMgmtTiming3];
+		g_smc_dfs_table[i].TmrTrnInterval = size->timing_parameter[i * num_of_dram_parameter + TmrTrnInterval];
+		g_smc_dfs_table[i].DFIDelay1 = size->timing_parameter[i * num_of_dram_parameter + DFIDelay1];
+		g_smc_dfs_table[i].DFIDelay2 = size->timing_parameter[i * num_of_dram_parameter + DFIDelay2];
+		g_smc_dfs_table[i].DvfsTrnCtl = size->timing_parameter[i * num_of_dram_parameter + DvfsTrnCtl];
+		g_smc_dfs_table[i].TrnTiming0 = size->timing_parameter[i * num_of_dram_parameter + TrnTiming0];
+		g_smc_dfs_table[i].TrnTiming1 = size->timing_parameter[i * num_of_dram_parameter + TrnTiming1];
+		g_smc_dfs_table[i].TrnTiming2 = size->timing_parameter[i * num_of_dram_parameter + TrnTiming2];
+
+		g_phy_dfs_table[i].DVFSn_CON0 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON0];
+		g_phy_dfs_table[i].DVFSn_CON1 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON1];
+		g_phy_dfs_table[i].DVFSn_CON2 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON2];
+		g_phy_dfs_table[i].DVFSn_CON3 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON3];
+		g_phy_dfs_table[i].DVFSn_CON4 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON4];
+
+		g_dram_dfs_table[i].DirectCmd_MR1 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR1];
+		g_dram_dfs_table[i].DirectCmd_MR2 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR2];
+		g_dram_dfs_table[i].DirectCmd_MR3 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR3];
+		g_dram_dfs_table[i].DirectCmd_MR11 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR11];
+		g_dram_dfs_table[i].DirectCmd_MR12 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR12];
+		g_dram_dfs_table[i].DirectCmd_MR14 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR14];
+		g_dram_dfs_table[i].DirectCmd_MR22 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR22];
+	}
+}
+
+void dfs_mif_level_init(void)
+{
+	int i;
+	void *dvfs_block;
+	struct ect_dvfs_domain *domain;
+
+	dvfs_block = ect_get_block(BLOCK_DVFS);
+	if (dvfs_block == NULL)
+		return;
+
+	domain = ect_dvfs_get_domain(dvfs_block, vclk_dvfs_mif.vclk.name);
+	if (domain == NULL)
+		return;
+
+	mif_freq_to_level = kzalloc(sizeof(unsigned long long) * domain->num_of_level, GFP_KERNEL);
+	if (mif_freq_to_level == NULL)
+		return;
+
+	num_mif_freq_to_level = domain->num_of_level;
+
+	for (i = 0; i < domain->num_of_level; ++i)
+		mif_freq_to_level[i] = domain->list_level[i].level * KHZ;
+}
+
+void dfs_dram_init(void)
+{
+	dfs_dram_param_init();
+	dfs_mif_level_init();
+}

drivers/soc/samsung/pwrcal/S5E8890/S5E8890-pll.c

@@ -0,0 +1,798 @@
+#include "../pwrcal.h"
+#include "../pwrcal-clk.h"
+#include "../pwrcal-env.h"
+#include "../pwrcal-rae.h"
+#include "../pwrcal-pmu.h"
+#include "S5E8890-cmusfr.h"
+#include "S5E8890-pmusfr.h"
+#include "S5E8890-cmu.h"
+
+
+/*
+	PLLs
+*/
+/* PLL141XX Clock Type */
+#define PLL141XX_MDIV_SHIFT		16
+#define PLL141XX_PDIV_SHIFT		8
+#define PLL141XX_SDIV_SHIFT		0
+#define PLL141XX_MDIV_MASK		0x3FF
+#define PLL141XX_PDIV_MASK		0x3F
+#define PLL141XX_SDIV_MASK		0x7
+#define PLL141XX_ENABLE			31
+#define PLL141XX_LOCKED			29
+#define PLL141XX_BYPASS			22
+
+/* PLL1431X Clock Type */
+#define PLL1431X_MDIV_SHIFT		16
+#define PLL1431X_PDIV_SHIFT		8
+#define PLL1431X_SDIV_SHIFT		0
+#define PLL1431X_K_SHIFT		0
+#define PLL1431X_MDIV_MASK		0x3FF
+#define PLL1431X_PDIV_MASK		0x3F
+#define PLL1431X_SDIV_MASK		0x7
+#define PLL1431X_K_MASK		0xFFFF
+#define PLL1431X_ENABLE			31
+#define PLL1431X_LOCKED			29
+#define PLL1431X_BYPASS			4
+
+#define FIN_HZ_26M		(26*MHZ)
+
+static const struct pwrcal_pll_rate_table *_clk_get_pll_settings(
+					struct pwrcal_pll *pll_clk,
+					unsigned long long rate)
+{
+	int i;
+	const struct pwrcal_pll_rate_table  *prate_table = pll_clk->rate_table;
+
+	for (i = 0; i < pll_clk->rate_count; i++) {
+		if (rate == prate_table[i].rate)
+			return &prate_table[i];
+	}
+
+	return NULL;
+}
+
+static int _clk_pll141xx_find_pms(struct pll_spec *pll_spec,
+				struct pwrcal_pll_rate_table *rate_table,
+				unsigned long long rate)
+{
+	unsigned int p, m, s;
+	unsigned long long fref, fvco, fout;
+	unsigned long long tmprate, tmpfout;
+	unsigned long long mindiffrate = 0xFFFFFFFFFFFFFFFF;
+	unsigned int min_p, min_m, min_s, min_fout;
+
+	for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
+		fref = FIN_HZ_26M / p;
+		if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
+			continue;
+
+		for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
+			tmprate = rate;
+			do_div(tmprate, MHZ);
+			tmprate = tmprate * p * (1 << s);
+			do_div(tmprate, (FIN_HZ_26M / MHZ));
+			m = (unsigned int)tmprate;
+
+			if ((m < pll_spec->mdiv_min)
+					|| (m > pll_spec->mdiv_max))
+				continue;
+
+			fvco = ((unsigned long long)FIN_HZ_26M) * m;
+			do_div(fvco, p);
+			if ((fvco < pll_spec->fvco_min)
+					|| (fvco > pll_spec->fvco_max))
+				continue;
+
+			fout = fvco >> s;
+			if ((fout >= pll_spec->fout_min)
+					&& (fout <= pll_spec->fout_max)) {
+				tmprate = rate;
+				do_div(tmprate, KHZ);
+				tmpfout = fout;
+				do_div(tmpfout, KHZ);
+				if (tmprate == tmpfout) {
+					rate_table->rate = fout;
+					rate_table->pdiv = p;
+					rate_table->mdiv = m;
+					rate_table->sdiv = s;
+					rate_table->kdiv = 0;
+					return 0;
+				}
+				if (tmpfout < tmprate && mindiffrate > tmprate - tmpfout) {
+					mindiffrate = tmprate - tmpfout;
+					min_fout = fout;
+					min_p = p;
+					min_m = m;
+					min_s = s;
+				}
+			}
+		}
+	}
+
+	if (mindiffrate != 0xFFFFFFFFFFFFFFFF) {
+		rate_table->rate = min_fout;
+		rate_table->pdiv = min_p;
+		rate_table->mdiv = min_m;
+		rate_table->sdiv = min_s;
+		rate_table->kdiv = 0;
+		return 0;
+	}
+	return -1;
+}
+
+
+static int _clk_pll1419x_find_pms(struct pll_spec *pll_spec,
+				struct pwrcal_pll_rate_table *rate_table,
+				unsigned long long rate)
+{
+	unsigned int p, m, s;
+	unsigned long long fref, fvco, fout;
+	unsigned long long tmprate, tmpfout;
+	unsigned long long mindiffrate = 0xFFFFFFFFFFFFFFFF;
+	unsigned int min_p, min_m, min_s, min_fout;
+
+	for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
+		fref = FIN_HZ_26M / p;
+		if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
+			continue;
+
+		for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
+			/*tmprate = rate;*/
+			tmprate = rate/2; /*for PLL1419*/
+			do_div(tmprate, MHZ);
+			tmprate = tmprate * p * (1 << s);
+			do_div(tmprate, (FIN_HZ_26M / MHZ));
+			m = (unsigned int)tmprate;
+
+			if ((m < pll_spec->mdiv_min)
+					|| (m > pll_spec->mdiv_max))
+				continue;
+
+			fvco = ((unsigned long long)FIN_HZ_26M) * m;
+			do_div(fvco, p);
+			if ((fvco < pll_spec->fvco_min)
+					|| (fvco > pll_spec->fvco_max))
+				continue;
+
+			fout = fvco >> s;
+			if ((fout >= pll_spec->fout_min)
+					&& (fout <= pll_spec->fout_max)) {
+				tmprate = rate;
+				do_div(tmprate, KHZ);
+				tmpfout = fout;
+				do_div(tmpfout, KHZ);
+				if (tmprate == tmpfout) {
+					rate_table->rate = fout;
+					rate_table->pdiv = p;
+					rate_table->mdiv = m;
+					rate_table->sdiv = s;
+					rate_table->kdiv = 0;
+					return 0;
+				}
+			}
+			if (tmpfout < tmprate && mindiffrate > tmprate - tmpfout) {
+				mindiffrate = tmprate - tmpfout;
+				min_fout = fout;
+				min_p = p;
+				min_m = m;
+				min_s = s;
+			}
+		}
+	}
+
+	if (mindiffrate != 0xFFFFFFFFFFFFFFFF) {
+		rate_table->rate = min_fout;
+		rate_table->pdiv = min_p;
+		rate_table->mdiv = min_m;
+		rate_table->sdiv = min_s;
+		rate_table->kdiv = 0;
+		return 0;
+	}
+	return -1;
+}
+
+static int _clk_pll141xx_is_enabled(struct pwrcal_clk *clk)
+{
+	return (int)(pwrcal_getbit(clk->offset, PLL141XX_ENABLE));
+}
+
+static int _clk_pll141xx_enable(struct pwrcal_clk *clk)
+{
+	int timeout;
+
+	if (pwrcal_getbit(clk->offset, PLL141XX_ENABLE))
+		return 0;
+
+	pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 1);
+
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+static int _clk_pll1419x_enable(struct pwrcal_clk *clk)
+{
+	int timeout;
+
+	if (pwrcal_getbit(clk->offset, PLL141XX_ENABLE))
+		return 0;
+
+	pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 1);
+
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(MIF0_PLL_CON0, PLL141XX_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(MIF1_PLL_CON0, PLL141XX_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(MIF2_PLL_CON0, PLL141XX_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(MIF3_PLL_CON0, PLL141XX_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+
+static int _clk_pll141xx_disable(struct pwrcal_clk *clk)
+{
+	pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 0);
+
+	return 0;
+}
+
+int _clk_pll141xx_is_disabled_bypass(struct pwrcal_clk *clk)
+{
+	if (pwrcal_getbit(clk->offset + 1, PLL141XX_BYPASS))
+		return 0;
+
+	return 1;
+}
+
+
+int _clk_pll141xx_set_bypass(struct pwrcal_clk *clk, int bypass_disable)
+{
+	if (bypass_disable == 0)
+		pwrcal_setbit(clk + 1, PLL141XX_BYPASS, 1);
+	else
+		pwrcal_setbit(clk + 1, PLL141XX_BYPASS, 0);
+
+	return 0;
+}
+
+static int _clk_pll141xx_set_pms(struct pwrcal_clk *clk,
+				const struct pwrcal_pll_rate_table  *rate_table)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0;
+
+	int timeout;
+
+	pdiv = rate_table->pdiv;
+	mdiv = rate_table->mdiv;
+	sdiv = rate_table->sdiv;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	pll_con0 &= ~((PLL141XX_MDIV_MASK << PLL141XX_MDIV_SHIFT)
+			| (PLL141XX_PDIV_MASK << PLL141XX_PDIV_SHIFT)
+			| (PLL141XX_SDIV_MASK << PLL141XX_SDIV_SHIFT));
+	pll_con0 |=  (mdiv << PLL141XX_MDIV_SHIFT)
+			| (pdiv << PLL141XX_PDIV_SHIFT)
+			| (sdiv << PLL141XX_SDIV_SHIFT);
+	pll_con0 &= ~(1<<26);
+	pll_con0 |= (1<<5);
+
+	pwrcal_writel(clk->status, pdiv*150);
+	pwrcal_writel(clk->offset, pll_con0);
+
+	if (pll_con0 & (1 << PLL141XX_ENABLE)) {
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+	}
+
+	return 0;
+
+}
+
+static int _clk_pll1419x_set_pms(struct pwrcal_clk *clk,
+				const struct pwrcal_pll_rate_table  *rate_table)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0;
+
+	int timeout;
+
+	pdiv = rate_table->pdiv;
+	mdiv = rate_table->mdiv;
+	sdiv = rate_table->sdiv;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	pll_con0 &= ~((PLL141XX_MDIV_MASK << PLL141XX_MDIV_SHIFT)
+			| (PLL141XX_PDIV_MASK << PLL141XX_PDIV_SHIFT)
+			| (PLL141XX_SDIV_MASK << PLL141XX_SDIV_SHIFT));
+	pll_con0 |=  (mdiv << PLL141XX_MDIV_SHIFT)
+			| (pdiv << PLL141XX_PDIV_SHIFT)
+			| (sdiv << PLL141XX_SDIV_SHIFT);
+
+	pwrcal_writel(MIF0_PLL_LOCK, pdiv*150);
+	pwrcal_writel(MIF1_PLL_LOCK, pdiv*150);
+	pwrcal_writel(MIF2_PLL_LOCK, pdiv*150);
+	pwrcal_writel(MIF3_PLL_LOCK, pdiv*150);
+	pwrcal_writel(clk->offset, pll_con0);
+
+	if (pll_con0 & (1 << PLL141XX_ENABLE)) {
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(MIF0_PLL_CON0, PLL141XX_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(MIF1_PLL_CON0, PLL141XX_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(MIF2_PLL_CON0, PLL141XX_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(MIF3_PLL_CON0, PLL141XX_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+	}
+
+	return 0;
+
+}
+
+
+static int _clk_pll141xx_set_rate(struct pwrcal_clk *clk,
+					unsigned long long rate)
+{
+	struct pwrcal_pll *pll = to_pll(clk);
+	struct pll_spec *pll_spec;
+	struct pwrcal_pll_rate_table  tmp_rate_table;
+	const struct pwrcal_pll_rate_table  *rate_table;
+
+	if (rate == 0) {
+		if (_clk_pll141xx_is_enabled(clk) != 0)
+			if (_clk_pll141xx_disable(clk))
+				goto errorout;
+		return 0;
+	}
+
+	rate_table = _clk_get_pll_settings(pll, rate);
+	if (rate_table == NULL) {
+		pll_spec = clk_pll_get_spec(clk);
+		if (pll_spec == NULL)
+			goto errorout;
+
+		if (_clk_pll141xx_find_pms(pll_spec, &tmp_rate_table, rate)) {
+			pr_err("can't find pms value for rate(%lldHz) of \'%s\'",
+				rate,
+				clk->name);
+			goto errorout;
+		}
+
+		rate_table = &tmp_rate_table;
+
+		pr_warn("not exist in rate table, p(%d), m(%d), s(%d), fout(%lldHz) %s",
+				rate_table->pdiv,
+				rate_table->mdiv,
+				rate_table->sdiv,
+				rate,
+				clk->name);
+	}
+
+	if (_clk_pll141xx_set_pms(clk, rate_table))
+		goto errorout;
+
+	if (rate != 0) {
+		if (_clk_pll141xx_is_enabled(clk) == 0)
+			_clk_pll141xx_enable(clk);
+	}
+	return 0;
+
+errorout:
+	return -1;
+}
+
+static int _clk_pll1419x_set_rate(struct pwrcal_clk *clk,
+					unsigned long long rate)
+{
+	struct pwrcal_pll *pll = to_pll(clk);
+	struct pll_spec *pll_spec;
+	struct pwrcal_pll_rate_table  tmp_rate_table;
+	const struct pwrcal_pll_rate_table  *rate_table;
+
+	if (rate == 0) {
+		if (_clk_pll141xx_is_enabled(clk) != 0)
+			if (_clk_pll141xx_disable(clk))
+				goto errorout;
+		return 0;
+	}
+
+	rate_table = _clk_get_pll_settings(pll, rate);
+	if (rate_table == NULL) {
+		pll_spec = clk_pll_get_spec(clk);
+		if (pll_spec == NULL)
+			goto errorout;
+
+		if (_clk_pll1419x_find_pms(pll_spec, &tmp_rate_table, rate)) {
+			pr_err("can't find pms value for rate(%lldHz) of \'%s\'",
+				rate,
+				clk->name);
+			goto errorout;
+		}
+
+		rate_table = &tmp_rate_table;
+
+		pr_warn("not exist in rate table, p(%d), m(%d), s(%d), fout(%lldHz) %s",
+				rate_table->pdiv,
+				rate_table->mdiv,
+				rate_table->sdiv,
+				rate,
+				clk->name);
+	}
+
+	_clk_pll141xx_disable(clk);
+
+	if (_clk_pll1419x_set_pms(clk, rate_table))
+		goto errorout;
+
+	if (rate != 0) {
+		if (_clk_pll141xx_is_enabled(clk) == 0)
+			_clk_pll1419x_enable(clk);
+	}
+	return 0;
+
+errorout:
+	return -1;
+}
+
+
+static unsigned long long _clk_pll141xx_get_rate(struct pwrcal_clk *clk)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0;
+	unsigned long long fout;
+
+	if (_clk_pll141xx_is_enabled(clk) == 0)
+		return 0;
+	pll_con0 = pwrcal_readl(clk->offset);
+	mdiv = (pll_con0 >> PLL141XX_MDIV_SHIFT) & PLL141XX_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL141XX_PDIV_SHIFT) & PLL141XX_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL141XX_SDIV_SHIFT) & PLL141XX_SDIV_MASK;
+
+	if (pdiv == 0) {
+		pr_err("pdiv is 0, id(%s)", clk->name);
+		return 0;
+	}
+	fout = FIN_HZ_26M * mdiv;
+	do_div(fout, (pdiv << sdiv));
+	return (unsigned long long)fout;
+}
+
+static unsigned long long _clk_pll1419x_get_rate(struct pwrcal_clk *clk)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0;
+	unsigned long long fout;
+
+	if (_clk_pll141xx_is_enabled(clk) == 0)
+		return 0;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	mdiv = (pll_con0 >> PLL141XX_MDIV_SHIFT) & PLL141XX_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL141XX_PDIV_SHIFT) & PLL141XX_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL141XX_SDIV_SHIFT) & PLL141XX_SDIV_MASK;
+
+	if (pdiv == 0) {
+		pr_err("pdiv is 0, id(%s)", clk->name);
+		return 0;
+	}
+	fout = FIN_HZ_26M * 2 * mdiv;
+	do_div(fout, (pdiv << sdiv));
+	return (unsigned long long)fout;
+}
+
+static int _clk_pll1431x_find_pms(struct pll_spec *pll_spec,
+					struct pwrcal_pll_rate_table *rate_table,
+					unsigned long long rate)
+{
+	unsigned int p, m, s;
+	signed short k;
+	unsigned long long fref, fvco, fout;
+	unsigned long long tmprate, tmpfout;
+
+	for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
+		fref = FIN_HZ_26M / p;
+		if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
+			continue;
+
+		for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
+			tmprate = rate;
+			do_div(tmprate, MHZ);
+			tmprate = tmprate * p * (1 << s);
+			do_div(tmprate, (FIN_HZ_26M / MHZ));
+			m = (unsigned int)tmprate;
+
+			if ((m < pll_spec->mdiv_min)
+					|| (m > pll_spec->mdiv_max))
+				continue;
+
+			tmprate = rate;
+			do_div(tmprate, MHZ);
+			tmprate = tmprate * p * (1 << s);
+			do_div(tmprate, (FIN_HZ_26M / MHZ));
+			tmprate = (tmprate - m) * 65536;
+			k = (unsigned int)tmprate;
+			if ((k < pll_spec->kdiv_min)
+					|| (k > pll_spec->kdiv_max))
+				continue;
+
+			fvco = FIN_HZ_26M * ((m << 16) + k);
+			do_div(fvco, p);
+			fvco >>= 16;
+			if ((fvco < pll_spec->fvco_min)
+					|| (fvco > pll_spec->fvco_max))
+				continue;
+
+			fout = fvco >> s;
+			if ((fout >= pll_spec->fout_min)
+				&& (fout <= pll_spec->fout_max)) {
+				tmprate = rate;
+				do_div(tmprate, KHZ);
+				tmpfout = fout;
+				do_div(tmpfout, KHZ);
+				if (tmprate == tmpfout) {
+					rate_table->rate = fout;
+					rate_table->pdiv = p;
+					rate_table->mdiv = m;
+					rate_table->sdiv = s;
+					rate_table->kdiv = k;
+					return 0;
+				}
+			}
+		}
+	}
+
+	return -1;
+}
+
+static int _clk_pll1431x_is_enabled(struct pwrcal_clk *clk)
+{
+	return (int)(pwrcal_getbit(clk->offset, PLL1431X_ENABLE));
+}
+
+static int _clk_pll1431x_enable(struct pwrcal_clk *clk)
+{
+	int timeout;
+
+	if (pwrcal_getbit(clk->offset, PLL1431X_ENABLE))
+		return 0;
+
+	pwrcal_setbit(clk->offset, PLL1431X_ENABLE, 1);
+
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(clk->offset, PLL1431X_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+static int _clk_pll1431x_disable(struct pwrcal_clk *clk)
+{
+	pwrcal_setbit(clk->offset, PLL1431X_ENABLE, 0);
+
+	return 0;
+}
+
+int _clk_pll1431x_is_disabled_bypass(struct pwrcal_clk *clk)
+{
+	if (pwrcal_getbit(clk->offset + 2, PLL1431X_BYPASS))
+		return 0;
+
+	return 1;
+}
+
+int _clk_pll1431x_set_bypass(struct pwrcal_clk *clk, int bypass_disable)
+{
+	if (bypass_disable == 0)
+		pwrcal_setbit(clk->offset + 2, PLL1431X_BYPASS, 1);
+	else
+		pwrcal_setbit(clk->offset + 2, PLL1431X_BYPASS, 0);
+
+	return 0;
+}
+
+static int _clk_pll1431x_set_pms(struct pwrcal_clk *clk,
+			const struct pwrcal_pll_rate_table  *rate_table)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0, pll_con1;
+	signed short kdiv;
+	int timeout;
+
+	pdiv = rate_table->pdiv;
+	mdiv = rate_table->mdiv;
+	sdiv = rate_table->sdiv;
+	kdiv = rate_table->kdiv;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	pll_con1 = pwrcal_readl(clk->offset + 1);
+	pll_con0 &= ~((PLL1431X_MDIV_MASK << PLL1431X_MDIV_SHIFT)
+			| (PLL1431X_PDIV_MASK << PLL1431X_PDIV_SHIFT)
+			| (PLL1431X_SDIV_MASK << PLL1431X_SDIV_SHIFT));
+	pll_con0 |=  (mdiv << PLL1431X_MDIV_SHIFT)
+			| (pdiv << PLL1431X_PDIV_SHIFT)
+			| (sdiv << PLL1431X_SDIV_SHIFT);
+	pll_con0 &= ~(1<<26);
+	pll_con0 |= (1<<5);
+
+	pll_con1 &= ~(PLL1431X_K_MASK << PLL1431X_K_SHIFT);
+	pll_con1 |=  (kdiv << PLL1431X_K_SHIFT);
+
+	if (kdiv == 0)
+		pwrcal_writel(clk->status, pdiv*3000);
+	else
+		pwrcal_writel(clk->status, pdiv*3000);
+	pwrcal_writel(clk->offset, pll_con0);
+	pwrcal_writel(clk->offset + 1, pll_con1);
+
+	if (pll_con0 & (1 << PLL1431X_ENABLE)) {
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(clk->offset, PLL1431X_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+	}
+
+	return 0;
+}
+
+static int _clk_pll1431x_set_rate(struct pwrcal_clk *clk,
+					unsigned long long rate)
+{
+	struct pwrcal_pll *pll = to_pll(clk);
+	struct pwrcal_pll_rate_table  tmp_rate_table;
+	const struct pwrcal_pll_rate_table  *rate_table;
+	struct pll_spec *pll_spec;
+
+	if (rate == 0) {
+		if (_clk_pll1431x_is_enabled(clk) != 0)
+			if (_clk_pll1431x_disable(clk))
+				goto errorout;
+		return 0;
+	}
+
+	rate_table = _clk_get_pll_settings(pll, rate);
+	if (rate_table == NULL) {
+		pll_spec = clk_pll_get_spec(clk);
+		if (pll_spec == NULL)
+			goto errorout;
+
+		if (_clk_pll1431x_find_pms(pll_spec, &tmp_rate_table, rate) < 0) {
+			pr_err("can't find pms value for rate(%lldHz) of %s",
+				rate,
+				clk->name);
+			goto errorout;
+		}
+
+		rate_table = &tmp_rate_table;
+		pr_warn("not exist in rate table, p(%d) m(%d) s(%d) k(%d) fout(%lld Hz) of %s",
+				rate_table->pdiv,
+				rate_table->mdiv,
+				rate_table->sdiv,
+				rate_table->kdiv,
+				rate,
+				clk->name);
+	}
+
+	if (_clk_pll1431x_set_pms(clk, rate_table))
+		goto errorout;
+
+	if (rate != 0) {
+		if (_clk_pll1431x_is_enabled(clk) == 0)
+			_clk_pll1431x_enable(clk);
+	}
+
+	return 0;
+
+errorout:
+	return -1;
+}
+
+static unsigned long long _clk_pll1431x_get_rate(struct pwrcal_clk *clk)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0, pll_con1;
+	signed short kdiv;
+	unsigned long long fout;
+
+	if (_clk_pll1431x_is_enabled(clk) == 0)
+		return 0;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	pll_con1 = pwrcal_readl(clk->offset + 1);
+	mdiv = (pll_con0 >> PLL1431X_MDIV_SHIFT) & PLL1431X_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL1431X_PDIV_SHIFT) & PLL1431X_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL1431X_SDIV_SHIFT) & PLL1431X_SDIV_MASK;
+
+	kdiv = (short)(pll_con1 >> PLL1431X_K_SHIFT) & PLL1431X_K_MASK;
+
+	if (pdiv == 0) {
+		pr_err("pdiv is 0, id(%s)", clk->name);
+		return 0;
+	}
+
+	fout = FIN_HZ_26M * ((mdiv << 16) + kdiv);
+	do_div(fout, (pdiv << sdiv));
+	fout >>= 16;
+
+	return (unsigned long long)fout;
+}
+
+struct pwrcal_pll_ops pll141xx_ops = {
+	.is_enabled = _clk_pll141xx_is_enabled,
+	.enable = _clk_pll141xx_enable,
+	.disable = _clk_pll141xx_disable,
+	.set_rate = _clk_pll141xx_set_rate,
+	.get_rate = _clk_pll141xx_get_rate,
+};
+
+struct pwrcal_pll_ops pll1419x_ops = {
+	.is_enabled = _clk_pll141xx_is_enabled,
+	.enable = _clk_pll1419x_enable,
+	.disable = _clk_pll141xx_disable,
+	.set_rate = _clk_pll1419x_set_rate,
+	.get_rate = _clk_pll1419x_get_rate,
+};
+
+struct pwrcal_pll_ops pll1431x_ops = {
+	.is_enabled = _clk_pll1431x_is_enabled,
+	.enable = _clk_pll1431x_enable,
+	.disable = _clk_pll1431x_disable,
+	.set_rate = _clk_pll1431x_set_rate,
+	.get_rate = _clk_pll1431x_get_rate,
+};

drivers/soc/samsung/pwrcal/S5E8890/S5E8890-pmu.c

@@ -0,0 +1,949 @@
+#include "../pwrcal.h"
+#include "../pwrcal-env.h"
+#include "../pwrcal-rae.h"
+#include "../pwrcal-pmu.h"
+#include "S5E8890-cmusfr.h"
+#include "S5E8890-pmusfr.h"
+#include "S5E8890-cmu.h"
+#include "S5E8890-vclk-internal.h"
+
+#define PAD_INITIATE_WAKEUP	(0x1 << 28)
+
+static void cam0_prev(int enable)
+{
+	if (pwrcal_getf(CAM1_STATUS, 0, 0xF) == 0xF) {
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM1_CSIS2_414_CAM1, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM1_CSIS2_414_LOCAL, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM1_CSIS3_132_CAM1, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM1_CSIS3_132_LOCAL, 0, 1);
+	}
+	if (pwrcal_getf(ISP0_STATUS, 0, 0xF) == 0xF) {
+		pwrcal_setbit(CLK_ENABLE_ACLK_ISP0, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_ISP0_LOCAL, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_ISP0_TPU, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_ISP0_TPU_LOCAL, 0, 1);
+	}
+	if (pwrcal_getf(ISP1_STATUS, 0, 0xF) == 0xF) {
+		pwrcal_setbit(CLK_ENABLE_ACLK_ISP1, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_ISP1_LOCAL, 0, 1);
+	}
+
+	if (enable == 0) {
+		vclk_disable(VCLK(dvfs_cam));
+
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS0_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS0_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS1_CSIS0_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS1_CSIS0_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS2_CSIS0_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS2_CSIS0_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS3_CSIS0_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS3_CSIS0_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS1_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS1_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS1_CSIS1_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS1_CSIS1_USER, 27, 1);
+	}
+}
+
+static void cam1_prev(int enable)
+{
+	if (pwrcal_getf(CAM0_STATUS, 0, 0xF) == 0xF) {
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_CSIS0_414, 1, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_CSIS0_414_LOCAL, 1, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_CSIS2_234_CAM0, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_CSIS2_234_LOCAL, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_CSIS3_132_CAM0, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_CSIS3_132_LOCAL, 0, 1);
+	}
+	if (pwrcal_getf(ISP0_STATUS, 0, 0xF) == 0xF) {
+		pwrcal_setbit(CLK_ENABLE_ACLK_ISP0, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_ISP0_LOCAL, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_ISP0_TPU, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_ISP0_TPU_LOCAL, 0, 1);
+	}
+	if (enable == 0) {
+		vclk_disable(VCLK(dvfs_cam));
+
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS2_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS2_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS1_CSIS2_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS1_CSIS2_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS2_CSIS2_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS2_CSIS2_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS3_CSIS2_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS3_CSIS2_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS3_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS3_USER, 27, 1);
+	}
+}
+
+static void isp0_prev(int enable)
+{
+	if (pwrcal_getf(CAM0_STATUS, 0, 0xF) == 0xF) {
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_CSIS2_234_CAM0, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_CSIS2_234_LOCAL, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_CSIS3_132_CAM0, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_CSIS3_132_LOCAL, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_3AA0_414_CAM0, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_3AA0_414_LOCAL, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_3AA1_414_CAM0, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_3AA1_414_LOCAL, 0, 1);
+	}
+	if (pwrcal_getf(CAM1_STATUS, 0, 0xF) == 0xF) {
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM1_SCL_566_CAM1, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM1_SCL_566_LOCAL, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM1_TREX_VRA_528_CAM1, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM1_TREX_VRA_528_LOCAL, 0, 1);
+	}
+}
+
+static void isp1_prev(int enable)
+{
+	if (pwrcal_getf(CAM0_STATUS, 0, 0xF) == 0xF) {
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_CSIS2_234_CAM0, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_CSIS2_234_LOCAL, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_CSIS3_132_CAM0, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_CSIS3_132_LOCAL, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_3AA0_414_CAM0, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_3AA0_414_LOCAL, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_3AA1_414_CAM0, 0, 1);
+		pwrcal_setbit(CLK_ENABLE_ACLK_CAM0_3AA1_414_LOCAL, 0, 1);
+	}
+}
+
+static void disp0_prev(int enable)
+{
+	if (enable == 0) {
+		pwrcal_setbit(QCH_CTRL_AXI_LH_ASYNC_MI_DISP0SFR, 0, 1);
+		pwrcal_setbit(QCH_CTRL_CMU_DISP0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PMU_DISP0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SYSREG_DISP0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_DECON0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_VPP0_G0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_VPP0_G1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_DSIM0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_DSIM1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_DSIM2, 0, 1);
+		pwrcal_setbit(QCH_CTRL_HDMI, 0, 1);
+		pwrcal_setbit(QCH_CTRL_DP, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PPMU_DISP0_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PPMU_DISP0_1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SMMU_DISP0_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SMMU_DISP0_1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SFW_DISP0_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SFW_DISP0_1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_LH_ASYNC_SI_R_TOP_DISP, 0, 1);
+		pwrcal_setbit(QCH_CTRL_LH_ASYNC_SI_TOP_DISP, 0, 1);
+
+		pwrcal_setbit(CLK_CON_MUX_DISP_PLL,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_DISP_PLL,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_ACLK_DISP0_0_400_USER,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_ACLK_DISP0_0_400_USER,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_ACLK_DISP0_1_400_USER,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_ACLK_DISP0_1_400_USER,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP0_DECON0_ECLK0_USER,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP0_DECON0_ECLK0_USER,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK0_USER,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK0_USER,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK1_USER,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK1_USER,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP0_HDMI_AUDIO_USER,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP0_HDMI_AUDIO_USER,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_ACLK_DISP0_1_400_DISP0,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_ACLK_DISP0_1_400_DISP0,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP0_DECON0_ECLK0_DISP0,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP0_DECON0_ECLK0_DISP0,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK0_DISP0,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK0_DISP0,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK1_DISP0,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK1_DISP0,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP0_HDMI_AUDIO_DISP0,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP0_HDMI_AUDIO_DISP0,	27,	1);
+
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER_DISP0, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER_DISP0, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER_DISP0, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER_DISP0, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER_DISP0, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER_DISP0, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_HDMIPHY_PIXEL_CLKO_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_HDMIPHY_PIXEL_CLKO_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_HDMIPHY_TMDS_CLKO_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_HDMIPHY_TMDS_CLKO_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY0_RXCLKESC0_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY0_RXCLKESC0_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY1_RXCLKESC0_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY1_RXCLKESC0_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY2_RXCLKESC0_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY2_RXCLKESC0_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV8_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV8_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_DPPHY_CH0_TXD_CLK_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_DPPHY_CH0_TXD_CLK_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_DPPHY_CH1_TXD_CLK_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_DPPHY_CH1_TXD_CLK_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_DPPHY_CH2_TXD_CLK_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_DPPHY_CH2_TXD_CLK_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_DPPHY_CH3_TXD_CLK_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_DPPHY_CH3_TXD_CLK_USER, 27, 1);
+	}
+}
+
+static void disp1_prev(int enable)
+{
+	if (enable == 0) {
+		pwrcal_setbit(QCH_CTRL_AXI_LH_ASYNC_MI_DISP1SFR, 0, 1);
+		pwrcal_setbit(QCH_CTRL_CMU_DISP1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PMU_DISP1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SYSREG_DISP1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_VPP1_G2, 0, 1);
+		pwrcal_setbit(QCH_CTRL_VPP1_G3, 0, 1);
+		pwrcal_setbit(QCH_CTRL_DECON1_PCLK_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_DECON1_PCLK_1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PPMU_DISP1_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PPMU_DISP1_1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SMMU_DISP1_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SMMU_DISP1_1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SFW_DISP1_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SFW_DISP1_1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_AXI_LH_ASYNC_SI_DISP1_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_AXI_LH_ASYNC_SI_DISP1_1, 0, 1);
+
+		pwrcal_setbit(CLK_CON_MUX_ACLK_DISP1_0_400_USER,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_ACLK_DISP1_0_400_USER,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_ACLK_DISP1_1_400_USER,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_ACLK_DISP1_1_400_USER,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK0_USER,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK0_USER,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK1_USER,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK1_USER,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP1_600_USER,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP1_600_USER,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_ACLK_DISP1_1_400_DISP1,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_ACLK_DISP1_1_400_DISP1,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK0_DISP1,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK0_DISP1,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK1_DISP1,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK1_DISP1,	27,	1);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DECON1_ECLK1,	12,	0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_DECON1_ECLK1,	27,	1);
+
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER_DISP1, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER_DISP1, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER_DISP1, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER_DISP1, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER_DISP1, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER_DISP1, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_USER, 27, 1);
+	}
+}
+
+static void aud_prev(int enable)
+{
+}
+
+static void fsys0_prev(int enable)
+{
+	if (enable == 0) {
+		pwrcal_writel(QSTATE_CTRL_USBDRD30,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_UFS_LINK_EMBEDDED,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_USBHOST20,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_USBHOST20_PHY,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_GPIO_FSYS0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_HPM_APBIF_FSYS0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PROMISE_FSYS0,	HWACG_QSTATE_CLOCK_ENABLE);
+
+		pwrcal_writel(CG_CTRL_MAN_ACLK_FSYS0_200,	0xFFFFFFFF);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_HPM_APBIF_FSYS0,	0xFFFFFFFF);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_USBDRD30_SUSPEND_CLK,	0xFFFFFFFF);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_MMC0,	0xFFFFFFFF);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_UFSUNIPRO_EMBEDDED,	0xFFFFFFFF);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_USBDRD30_REF_CLK,	0xFFFFFFFF);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,	0xFFFFFFFF);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,	0xFFFFFFFF);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_UFS_TX0_SYMBOL,	0xFFFFFFFF);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_UFS_RX0_SYMBOL,	0xFFFFFFFF);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_USBHOST20_PHYCLOCK,	0xFFFFFFFF);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_USBHOST20_FREECLK,	0xFFFFFFFF);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_PROMISE_FSYS0,	0xFFFFFFFF);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_USBHOST20PHY_REF_CLK,	0xFFFFFFFF);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_UFSUNIPRO_EMBEDDED_CFG,	0xFFFFFFFF);
+
+		pwrcal_setbit(QCH_CTRL_AXI_LH_ASYNC_MI_TOP_FSYS0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_AXI_LH_ASYNC_MI_ETR_USB_FSYS0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_ETR_USB_FSYS0_ACLK, 0, 1);
+		pwrcal_setbit(QCH_CTRL_ETR_USB_FSYS0_PCLK, 0, 1);
+		pwrcal_setbit(QCH_CTRL_CMU_FSYS0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PMU_FSYS0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SYSREG_FSYS0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_USBDRD30, 0, 1);
+		pwrcal_setbit(QCH_CTRL_MMC0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_UFS_LINK_EMBEDDED, 0, 1);
+		pwrcal_setbit(QCH_CTRL_USBHOST20, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PDMA0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PDMAS, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PPMU_FSYS0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_ACEL_LH_ASYNC_SI_TOP_FSYS0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_USBDRD30_PHYCTRL, 0, 1);
+		pwrcal_setbit(QCH_CTRL_USBHOST20_PHYCTRL, 0, 1);
+
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_UFS_TX0_SYMBOL_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_UFS_TX0_SYMBOL_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_UFS_RX0_SYMBOL_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_UFS_RX0_SYMBOL_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_USBHOST20_PHYCLOCK_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_USBHOST20_PHYCLOCK_USER, 27, 1);
+
+		pwrcal_setbit(CLK_CON_MUX_ACLK_FSYS0_200_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_FSYS0_USBDRD30_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_FSYS0_MMC0_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_CFG_USER, 12, 0);
+
+		pwrcal_setf(RESET_SLEEP_FSYS0_SYS_PWR_REG, 0, 0x3, 0x3);
+		pwrcal_setf(RESET_CMU_FSYS0_SYS_PWR_REG, 0, 0x3, 0x3);
+	}
+}
+
+static void fsys1_prev(int enable)
+{
+	if (enable == 0) {
+		pwrcal_writel(QSTATE_CTRL_SROMC_FSYS1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_GPIO_FSYS1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_HPM_APBIF_FSYS1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PROMISE_FSYS1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PCIE_RC_LINK_WIFI0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PCIE_RC_LINK_WIFI1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PCIE_PCS_WIFI0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PCIE_PCS_WIFI1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PCIE_PHY_FSYS1_WIFI0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PCIE_PHY_FSYS1_WIFI1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_UFS_LINK_SDCARD,	HWACG_QSTATE_CLOCK_ENABLE);
+
+		pwrcal_setbit(QCH_CTRL_AXI_LH_ASYNC_MI_TOP_FSYS1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_CMU_FSYS1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PMU_FSYS1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SYSREG_FSYS1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_MMC2, 0, 1);
+		pwrcal_setbit(QCH_CTRL_UFS_LINK_SDCARD, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PPMU_FSYS1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_ACEL_LH_ASYNC_SI_TOP_FSYS1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PCIE_RC_LINK_WIFI0_SLV, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PCIE_RC_LINK_WIFI0_DBI, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PCIE_RC_LINK_WIFI1_SLV, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PCIE_RC_LINK_WIFI1_DBI, 0, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI0_TX0_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI0_TX0_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI0_RX0_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI0_RX0_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI1_TX0_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI1_TX0_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI1_RX0_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI1_RX0_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI0_DIG_REFCLK_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI0_DIG_REFCLK_USER, 27, 1);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI1_DIG_REFCLK_USER, 12, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI1_DIG_REFCLK_USER, 27, 1);
+
+		pwrcal_setf(RESET_SLEEP_FSYS1_SYS_PWR_REG, 0, 0x3, 0x3);
+		pwrcal_setf(RESET_CMU_FSYS1_SYS_PWR_REG, 0, 0x3, 0x3);
+	}
+}
+
+static void mscl_prev(int enable)
+{
+	if (enable == 0) {
+		pwrcal_setbit(QCH_CTRL_LH_ASYNC_MI_MSCLSFR, 0, 1);
+		pwrcal_setbit(QCH_CTRL_CMU_MSCL, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PMU_MSCL, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SYSREG_MSCL, 0, 1);
+		pwrcal_setbit(QCH_CTRL_MSCL_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_MSCL_1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_JPEG, 0, 1);
+		pwrcal_setbit(QCH_CTRL_G2D, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SMMU_MSCL_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SMMU_MSCL_1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SMMU_JPEG, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SMMU_G2D, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PPMU_MSCL_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PPMU_MSCL_1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SFW_MSCL_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SFW_MSCL_1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_LH_ASYNC_SI_MSCL_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_LH_ASYNC_SI_MSCL_1, 0, 1);
+	}
+}
+
+static void mfc_prev(int enable)
+{
+	if (enable == 0) {
+		pwrcal_setbit(QCH_CTRL_MFC, 0, 1);
+		pwrcal_setbit(QCH_CTRL_LH_M_MFC, 0, 1);
+		pwrcal_setbit(QCH_CTRL_CMU_MFC, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PMU_MFC, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SYSREG_MFC, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PPMU_MFC_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_PPMU_MFC_1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SFW_MFC_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SFW_MFC_1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SMMU_MFC_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_SMMU_MFC_1, 0, 1);
+		pwrcal_setbit(QCH_CTRL_LH_S_MFC_0, 0, 1);
+		pwrcal_setbit(QCH_CTRL_LH_S_MFC_1, 0, 1);
+	}
+}
+
+
+static void g3d_prev(int enable)
+{
+}
+
+
+
+static void cam0_post(int enable)
+{
+	if (enable == 1) {
+		vclk_enable(VCLK(dvfs_cam));
+
+		pwrcal_writel(CAM0_DRCG_EN, 0x1F);
+
+		pwrcal_gate_disable(CLK(CAM0_GATE_ACLK_CSIS0));
+		pwrcal_gate_disable(CLK(CAM0_GATE_PCLK_CSIS0));
+		pwrcal_gate_disable(CLK(CAM0_GATE_ACLK_CSIS1));
+		pwrcal_gate_disable(CLK(CAM0_GATE_PCLK_CSIS1));
+		pwrcal_gate_disable(CLK(CAM0_GATE_ACLK_PXL_ASBS_CSIS2_int));
+		pwrcal_gate_disable(CLK(CAM0_GATE_ACLK_3AA0));
+		pwrcal_gate_disable(CLK(CAM0_GATE_PCLK_3AA0));
+		pwrcal_gate_disable(CLK(CAM0_GATE_ACLK_3AA1));
+		pwrcal_gate_disable(CLK(CAM0_GATE_PCLK_3AA1));
+		pwrcal_gate_disable(CLK(CAM0_GATE_PCLK_HPM_APBIF_CAM0));
+		pwrcal_gate_disable(CLK(CAM0_GATE_SCLK_PROMISE_CAM0));
+	}
+}
+static void mscl_post(int enable)
+{
+	if (enable == 1) {
+		pwrcal_writel(MSCL_DRCG_EN, 0x3FF);
+
+		pwrcal_writel(CG_CTRL_MAN_ACLK_MSCL0_528,	0);
+		pwrcal_writel(CG_CTRL_MAN_ACLK_MSCL0_528_SECURE_SFW_MSCL_0,	0);
+		pwrcal_writel(CG_CTRL_MAN_ACLK_MSCL1_528,	0);
+		pwrcal_writel(CG_CTRL_MAN_ACLK_MSCL1_528_SECURE_SFW_MSCL_1,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_MSCL,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_MSCL_SECURE_SFW_MSCL_0,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_MSCL_SECURE_SFW_MSCL_1,	0);
+
+		pwrcal_writel(QCH_CTRL_LH_ASYNC_MI_MSCLSFR,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_CMU_MSCL,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PMU_MSCL,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SYSREG_MSCL,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_MSCL_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_MSCL_1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_JPEG,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_G2D,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SMMU_MSCL_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SMMU_MSCL_1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SMMU_JPEG,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SMMU_G2D,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PPMU_MSCL_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PPMU_MSCL_1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SFW_MSCL_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SFW_MSCL_1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_LH_ASYNC_SI_MSCL_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_LH_ASYNC_SI_MSCL_1,	HWACG_QCH_ENABLE);
+	}
+}
+static void g3d_post(int enable)
+{
+	if (enable == 1) {
+		udelay(40);
+
+		pwrcal_writel(G3D_DRCG_EN, 0x3F);
+
+		pwrcal_gate_disable(CLK(G3D_GATE_ACLK_PPMU_G3D0));
+		pwrcal_gate_disable(CLK(G3D_GATE_ACLK_PPMU_G3D1));
+		pwrcal_gate_disable(CLK(G3D_GATE_PCLK_PPMU_G3D0));
+		pwrcal_gate_disable(CLK(G3D_GATE_PCLK_PPMU_G3D1));
+		pwrcal_gate_disable(CLK(G3D_GATE_ACLK_G3D));
+		pwrcal_gate_disable(CLK(G3D_GATE_ACLK_ASYNCAPBM_G3D));
+		pwrcal_gate_disable(CLK(G3D_GATE_ACLK_XIU_G3D));
+		pwrcal_gate_disable(CLK(G3D_GATE_ACLK_GRAY_DEC));
+		pwrcal_gate_disable(CLK(G3D_GATE_ACLK_ASYNCAPBS_G3D));
+		pwrcal_gate_disable(CLK(G3D_GATE_ACLK_ACEL_LH_ASYNC_SI_G3D0));
+		pwrcal_gate_disable(CLK(G3D_GATE_ACLK_ACEL_LH_ASYNC_SI_G3D1));
+		pwrcal_gate_disable(CLK(G3D_GATE_PCLK_SYSREG_G3D));
+		pwrcal_gate_disable(CLK(G3D_GATE_ACLK_AXI_DS_G3D));
+		pwrcal_gate_disable(CLK(G3D_GATE_ACLK_ASYNCAXI_G3D));
+		pwrcal_gate_disable(CLK(G3D_GATE_SCLK_ASYNCAXI_G3D));
+		pwrcal_gate_disable(CLK(G3D_GATE_SCLK_AXI_LH_ASYNC_SI_G3DIRAM));
+	}
+	if (enable == 0)
+		udelay(90);
+}
+static void disp0_post(int enable)
+{
+	if (enable == 1) {
+		pwrcal_writel(DISP0_DRCG_EN, 0x3f);
+
+		pwrcal_writel(CG_CTRL_MAN_ACLK_DISP0_0_400,	0);
+		pwrcal_writel(CG_CTRL_MAN_ACLK_DISP0_1_400,	0);
+		pwrcal_writel(CG_CTRL_MAN_ACLK_DISP0_0_400_SECURE_SFW_DISP0_0,	0);
+		pwrcal_writel(CG_CTRL_MAN_ACLK_DISP0_1_400_SECURE_SFW_DISP0_1,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_DISP0_0_133,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_DISP0_0_133_HPM_APBIF_DISP0,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_DISP0_0_133_SECURE_DECON0,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_DISP0_0_133_SECURE_VPP0,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_DISP0_0_133_SECURE_SFW_DISP0_0,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_DISP0_0_133_SECURE_SFW_DISP0_1,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_DISP1_400,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_DECON0_ECLK0,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_DECON0_VCLK0,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_DECON0_VCLK1,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_HDMI_AUDIO,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_DISP0_PROMISE,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_HDMIPHY,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_MIPIDPHY0,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_MIPIDPHY1,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_MIPIDPHY2,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_DPPHY,	0);
+		pwrcal_writel(CG_CTRL_MAN_OSCCLK,	0);
+
+		pwrcal_writel(QCH_CTRL_AXI_LH_ASYNC_MI_DISP0SFR,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_CMU_DISP0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PMU_DISP0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SYSREG_DISP0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_DECON0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_VPP0_G0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_VPP0_G1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_DSIM0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_DSIM1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_DSIM2,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_HDMI,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_DP,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PPMU_DISP0_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PPMU_DISP0_1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SMMU_DISP0_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SMMU_DISP0_1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SFW_DISP0_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SFW_DISP0_1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_LH_ASYNC_SI_R_TOP_DISP,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_LH_ASYNC_SI_TOP_DISP,	HWACG_QCH_ENABLE);
+
+		pwrcal_writel(QSTATE_CTRL_DSIM0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_DSIM1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_DSIM2,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_HDMI,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_HDMI_AUDIO,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_DP,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_DISP0_MUX,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_HDMI_PHY,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_DISP1_400,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_DECON0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_HPM_APBIF_DISP0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PROMISE_DISP0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_DPTX_PHY,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_MIPI_DPHY_M1S0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_MIPI_DPHY_M4S0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_MIPI_DPHY_M4S4,	HWACG_QSTATE_CLOCK_ENABLE);
+	}
+}
+static void cam1_post(int enable)
+{
+	if (enable == 1) {
+		vclk_enable(VCLK(dvfs_cam));
+
+		pwrcal_writel(CAM1_DRCG_EN, 0x7FFFF);
+
+		pwrcal_gate_disable(CLK(CAM1_GATE_ACLK_SMMU_VRA));
+		pwrcal_gate_disable(CLK(CAM1_GATE_ACLK_SMMU_ISPCPU));
+		pwrcal_gate_disable(CLK(CAM1_GATE_ACLK_SMMU_IS_B));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_SMMU_IS_B));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_SMMU_VRA));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_SMMU_ISPCPU));
+		pwrcal_gate_disable(CLK(CAM1_GATE_ACLK_SMMU_MC_SC));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_SMMU_MC_SC));
+		pwrcal_gate_disable(CLK(CAM1_GATE_ACLK_ARM));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_ARM));
+		pwrcal_gate_disable(CLK(CAM1_GATE_ACLK_ASYNC_CA7_TO_DRAM));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_CSIS2));
+		pwrcal_gate_disable(CLK(CAM1_GATE_ACLK_CSIS2));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_CSIS3));
+		pwrcal_gate_disable(CLK(CAM1_GATE_ACLK_CSIS3));
+		pwrcal_gate_disable(CLK(CAM1_GATE_ACLK_VRA));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_VRA));
+		pwrcal_gate_disable(CLK(CAM1_GATE_ACLK_MC_SC));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_I2C0));
+		pwrcal_gate_disable(CLK(CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C0_ISP));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_I2C1));
+		pwrcal_gate_disable(CLK(CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C1_ISP));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_I2C2));
+		pwrcal_gate_disable(CLK(CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C2_ISP));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_I2C3));
+		pwrcal_gate_disable(CLK(CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C3_ISP));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_WDT));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_MCUCTL));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_UART));
+		pwrcal_gate_disable(CLK(CAM1_GATE_SCLK_ISP_PERI_IS_B_UART_EXT_CLK_ISP));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_SPI0));
+		pwrcal_gate_disable(CLK(CAM1_GATE_SCLK_ISP_PERI_IS_B_SPI0_EXT_CLK_ISP));
+		pwrcal_gate_disable(CLK(CAM1_GATE_SCLK_ISP_PERI_IS_B_SPI1_EXT_CLK_ISP));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_SPI1));
+		pwrcal_gate_disable(CLK(CAM1_GATE_ACLK_TREX_B));
+		pwrcal_gate_disable(CLK(CAM1_GATE_ACLK_TREX_CAM1));
+		pwrcal_gate_disable(CLK(CAM1_GATE_ACLK_LH_SI));
+		pwrcal_gate_disable(CLK(CAM1_GATE_ACLK_PDMA));
+		pwrcal_gate_disable(CLK(CAM1_GATE_PCLK_PWM));
+		pwrcal_gate_disable(CLK(CAM1_GATE_SCLK_ISP_PERI_IS_B_PWM_ISP));
+	}
+}
+static void aud_post(int enable)
+{
+	if (enable == 1) {
+		pwrcal_writel(AUD_DRCG_EN, 0xF);
+
+		pwrcal_gate_disable(CLK(AUD_GATE_SCLK_CA5));
+		pwrcal_gate_disable(CLK(AUD_GATE_ACLK_DMAC));
+		pwrcal_gate_disable(CLK(AUD_GATE_ACLK_SRAMC));
+		pwrcal_gate_disable(CLK(AUD_GATE_ACLK_AXI_LH_ASYNC_SI_TOP));
+		pwrcal_gate_disable(CLK(AUD_GATE_ACLK_SMMU));
+		pwrcal_gate_disable(CLK(AUD_GATE_ACLK_INTR));
+		pwrcal_gate_disable(CLK(AUD_GATE_PCLK_SMMU));
+		pwrcal_gate_disable(CLK(AUD_GATE_PCLK_SFR1));
+		pwrcal_gate_disable(CLK(AUD_GATE_PCLK_TIMER));
+		pwrcal_gate_disable(CLK(AUD_GATE_PCLK_DBG));
+		pwrcal_gate_disable(CLK(AUD_GATE_ACLK_ATCLK_AUD));
+		pwrcal_gate_disable(CLK(AUD_GATE_PCLK_I2S));
+		pwrcal_gate_disable(CLK(AUD_GATE_PCLK_PCM));
+		pwrcal_gate_disable(CLK(AUD_GATE_PCLK_SLIMBUS));
+		pwrcal_gate_disable(CLK(AUD_GATE_SCLK_I2S));
+		pwrcal_gate_disable(CLK(AUD_GATE_SCLK_I2S_BCLK));
+		pwrcal_gate_disable(CLK(AUD_GATE_SCLK_PCM));
+		pwrcal_gate_disable(CLK(AUD_GATE_SCLK_ASRC));
+		pwrcal_gate_disable(CLK(AUD_GATE_SCLK_SLIMBUS));
+		pwrcal_gate_disable(CLK(AUD_GATE_SCLK_SLIMBUS_CLKIN));
+	}
+}
+static void fsys0_post(int enable)
+{
+	if (enable == 1) {
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER, 27, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER, 27, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_UFS_TX0_SYMBOL_USER, 27, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_UFS_RX0_SYMBOL_USER, 27, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_USBHOST20_PHYCLOCK_USER, 27, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_USBHOST20PHY_REF_CLK, 27, 0);
+
+		pwrcal_writel(CG_CTRL_MAN_ACLK_FSYS0_200,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_HPM_APBIF_FSYS0,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_USBDRD30_SUSPEND_CLK,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_MMC0,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_UFSUNIPRO_EMBEDDED,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_USBDRD30_REF_CLK,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_UFS_TX0_SYMBOL,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_UFS_RX0_SYMBOL,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_USBHOST20_PHYCLOCK,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_USBHOST20_REF_CLK,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_PROMISE_FSYS0,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_USBHOST20PHY_REF_CLK,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_UFSUNIPRO_EMBEDDED_CFG,	0);
+
+		pwrcal_writel(QCH_CTRL_AXI_LH_ASYNC_MI_TOP_FSYS0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_AXI_LH_ASYNC_MI_ETR_USB_FSYS0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_ETR_USB_FSYS0_ACLK,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_ETR_USB_FSYS0_PCLK,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_CMU_FSYS0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PMU_FSYS0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SYSREG_FSYS0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_USBDRD30,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_MMC0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_UFS_LINK_EMBEDDED,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_USBHOST20,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PDMA0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PDMAS,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PPMU_FSYS0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_ACEL_LH_ASYNC_SI_TOP_FSYS0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_USBDRD30_PHYCTRL,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_USBHOST20_PHYCTRL,	HWACG_QCH_ENABLE);
+
+		pwrcal_writel(QSTATE_CTRL_USBDRD30,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_UFS_LINK_EMBEDDED,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_USBHOST20,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_USBHOST20_PHY,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_GPIO_FSYS0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_HPM_APBIF_FSYS0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PROMISE_FSYS0,	HWACG_QSTATE_CLOCK_ENABLE);
+
+		pwrcal_writel(PAD_RETENTION_MMC0_OPTION, PAD_INITIATE_WAKEUP);
+		pwrcal_writel(PAD_RETENTION_UFS_OPTION, PAD_INITIATE_WAKEUP);
+		pwrcal_writel(PAD_RETENTION_USB_OPTION, PAD_INITIATE_WAKEUP);
+	}
+}
+static void isp0_post(int enable)
+{
+	if (enable == 1) {
+		pwrcal_writel(ISP0_DRCG_EN, 0x7);
+
+		pwrcal_gate_disable(CLK(ISP0_GATE_CLK_AXI_LH_ASYNC_SI_TOP_ISP0));
+		pwrcal_gate_disable(CLK(ISP0_GATE_CLK_C_TREX_C));
+		pwrcal_gate_disable(CLK(ISP0_GATE_ACLK_SysMMU601));
+		pwrcal_gate_disable(CLK(ISP0_GATE_PCLK_HPM_APBIF_ISP0));
+		pwrcal_gate_disable(CLK(ISP0_GATE_PCLK_TREX_C));
+		pwrcal_gate_disable(CLK(ISP0_GATE_PCLK_SysMMU601));
+		pwrcal_gate_disable(CLK(ISP0_GATE_ACLK_FIMC_ISP0));
+		pwrcal_gate_disable(CLK(ISP0_GATE_PCLK_FIMC_ISP0));
+		pwrcal_gate_disable(CLK(ISP0_GATE_ACLK_FIMC_TPU));
+		pwrcal_gate_disable(CLK(ISP0_GATE_PCLK_FIMC_TPU));
+		pwrcal_gate_disable(CLK(ISP0_GATE_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D));
+	}
+}
+static void isp1_post(int enable)
+{
+	if (enable == 1) {
+		pwrcal_writel(ISP1_DRCG_EN, 0x3);
+
+		pwrcal_gate_disable(CLK(ISP1_GATE_ACLK_FIMC_ISP1));
+		pwrcal_gate_disable(CLK(ISP1_GATE_ACLK_XIU_N_ASYNC_SI));
+		pwrcal_gate_disable(CLK(ISP1_GATE_PCLK_FIMC_ISP1));
+		pwrcal_gate_disable(CLK(ISP1_GATE_PCLK_SYSREG_ISP1));
+	}
+}
+static void mfc_post(int enable)
+{
+	if (enable == 1) {
+		pwrcal_writel(MFC_DRCG_EN, 0x7);
+
+		pwrcal_writel(CG_CTRL_MAN_ACLK_MFC_600,	0);
+		pwrcal_writel(CG_CTRL_MAN_ACLK_MFC_600_SECURE_SFW_MFC_0,	0);
+		pwrcal_writel(CG_CTRL_MAN_ACLK_MFC_600_SECURE_SFW_MFC_1,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_MFC_150,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_MFC_150_HPM_APBIF_MFC,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_MFC_150_SECURE_SFW_MFC_0,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_MFC_150_SECURE_SFW_MFC_1,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_MFC_PROMISE,	0);
+
+		pwrcal_writel(QCH_CTRL_MFC,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_LH_M_MFC,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_CMU_MFC,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PMU_MFC,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SYSREG_MFC,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PPMU_MFC_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PPMU_MFC_1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SFW_MFC_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SFW_MFC_1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SMMU_MFC_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SMMU_MFC_1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_LH_S_MFC_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_LH_S_MFC_1,	HWACG_QCH_ENABLE);
+
+		pwrcal_writel(QSTATE_CTRL_HPM_APBIF_MFC,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PROMISE_MFC,	HWACG_QSTATE_CLOCK_ENABLE);
+	}
+}
+static void disp1_post(int enable)
+{
+	if (enable == 1) {
+		pwrcal_writel(DISP1_DRCG_EN, 0x7F);
+
+		pwrcal_writel(CG_CTRL_MAN_ACLK_DISP1_0_400,	0);
+		pwrcal_writel(CG_CTRL_MAN_ACLK_DISP1_1_400,	0);
+		pwrcal_writel(CG_CTRL_MAN_ACLK_DISP1_0_400_SECURE_SFW_DISP1_0,	0);
+		pwrcal_writel(CG_CTRL_MAN_ACLK_DISP1_1_400_SECURE_SFW_DISP1_1,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_DISP1_0_133,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_DISP1_0_133_HPM_APBIF_DISP1,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_DISP1_0_133_SECURE_SFW_DISP1_0,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_DISP1_0_133_SECURE_SFW_DISP1_1,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_DECON1_ECLK_0,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_DECON1_ECLK_1,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_DISP1_PROMISE,	0);
+
+		pwrcal_writel(QCH_CTRL_AXI_LH_ASYNC_MI_DISP1SFR,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_CMU_DISP1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PMU_DISP1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SYSREG_DISP1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_VPP1_G2,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_VPP1_G3,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_DECON1_PCLK_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_DECON1_PCLK_1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PPMU_DISP1_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PPMU_DISP1_1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SMMU_DISP1_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SMMU_DISP1_1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SFW_DISP1_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SFW_DISP1_1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_AXI_LH_ASYNC_SI_DISP1_0,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_AXI_LH_ASYNC_SI_DISP1_1,	HWACG_QCH_ENABLE);
+
+		pwrcal_writel(QSTATE_CTRL_DECON1_ECLK_0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_DECON1_ECLK_1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_HPM_APBIF_DISP1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PROMISE_DISP1,	HWACG_QSTATE_CLOCK_ENABLE);
+	}
+}
+static void fsys1_post(int enable)
+{
+	if (enable == 1) {
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_USER, 27, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_USER, 27, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI0_TX0_USER, 27, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI0_RX0_USER, 27, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI1_TX0_USER, 27, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI1_RX0_USER, 27, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI0_DIG_REFCLK_USER, 27, 0);
+		pwrcal_setbit(CLK_CON_MUX_PHYCLK_PCIE_WIFI1_DIG_REFCLK_USER, 27, 0);
+
+		pwrcal_writel(CG_CTRL_MAN_ACLK_FSYS1_200,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_HPM_APBIF_FSYS1,	0);
+		pwrcal_writel(CG_CTRL_MAN_PCLK_COMBO_PHY_WIFI,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_MMC2,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_UFSUNIPRO_SDCARD,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_UFSUNIPRO_SDCARD_CFG,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_FSYS1_PCIE0_PHY,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_PCIE_WIFI0_TX0,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_PCIE_WIFI0_RX0,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_PCIE_WIFI1_TX0,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_PCIE_WIFI1_RX0,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_PCIE_WIFI0_DIG_REFCLK,	0);
+		pwrcal_writel(CG_CTRL_MAN_PHYCLK_PCIE_WIFI1_DIG_REFCLK,	0);
+		pwrcal_writel(CG_CTRL_MAN_SCLK_PROMISE_FSYS1,	0);
+
+		pwrcal_writel(QCH_CTRL_AXI_LH_ASYNC_MI_TOP_FSYS1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_CMU_FSYS1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PMU_FSYS1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_SYSREG_FSYS1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_MMC2,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_UFS_LINK_SDCARD,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PPMU_FSYS1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_ACEL_LH_ASYNC_SI_TOP_FSYS1,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PCIE_RC_LINK_WIFI0_SLV,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PCIE_RC_LINK_WIFI0_DBI,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PCIE_RC_LINK_WIFI1_SLV,	HWACG_QCH_ENABLE);
+		pwrcal_writel(QCH_CTRL_PCIE_RC_LINK_WIFI1_DBI,	HWACG_QCH_ENABLE);
+
+		pwrcal_writel(QSTATE_CTRL_SROMC_FSYS1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_GPIO_FSYS1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_HPM_APBIF_FSYS1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PROMISE_FSYS1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PCIE_RC_LINK_WIFI0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PCIE_RC_LINK_WIFI1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PCIE_PCS_WIFI0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PCIE_PCS_WIFI1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PCIE_PHY_FSYS1_WIFI0,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_PCIE_PHY_FSYS1_WIFI1,	HWACG_QSTATE_CLOCK_ENABLE);
+		pwrcal_writel(QSTATE_CTRL_UFS_LINK_SDCARD,	HWACG_QSTATE_CLOCK_ENABLE);
+
+		pwrcal_writel(PAD_RETENTION_MMC2_OPTION, PAD_INITIATE_WAKEUP);
+		pwrcal_writel(PAD_RETENTION_UFS_CARD_OPTION, PAD_INITIATE_WAKEUP);
+		pwrcal_writel(PAD_RETENTION_PCIE_OPTION, PAD_INITIATE_WAKEUP);
+	}
+}
+
+static void cam0_config(int enable)
+{
+	pwrcal_setf(CAM0_OPTION, 0, 0xFFFFFFFF, 0x2);
+}
+static void mscl_config(int enable)
+{
+	pwrcal_setf(MSCL_OPTION, 0, 0xFFFFFFFF, 0x2);
+}
+static void g3d_config(int enable)
+{
+	pwrcal_setf(G3D_OPTION, 0, 0xFFFFFFFF, 0x1);
+	pwrcal_setf(MEMORY_G3D_OPTION, 0, 0xFFFFFFFF, 0x1);
+}
+static void disp0_config(int enable)
+{
+	pwrcal_setf(DISP0_OPTION, 0, 0xFFFFFFFF, 0x2);
+}
+static void cam1_config(int enable)
+{
+	pwrcal_setf(CAM1_OPTION, 0, 0xFFFFFFFF, 0x2);
+}
+static void aud_config(int enable)
+{
+	pwrcal_setf(AUD_OPTION, 0, 0xFFFFFFFF, 0x2);
+	pwrcal_setf(PAD_RETENTION_AUD_OPTION, 0, 0xFFFFFFFF, 0x10000000);
+}
+static void fsys0_config(int enable)
+{
+	pwrcal_setf(FSYS0_OPTION, 0, 0xFFFFFFFF, 0x2);
+}
+static void isp0_config(int enable)
+{
+	pwrcal_setf(ISP0_OPTION, 0, 0xFFFFFFFF, 0x2);
+}
+static void isp1_config(int enable)
+{
+	pwrcal_setf(ISP1_OPTION, 0, 0xFFFFFFFF, 0x2);
+}
+static void mfc_config(int enable)
+{
+	pwrcal_setf(MFC_OPTION, 0, 0xFFFFFFFF, 0x2);
+}
+static void disp1_config(int enable)
+{
+	pwrcal_setf(DISP1_OPTION, 0, 0xFFFFFFFF, 0x2);
+}
+static void fsys1_config(int enable)
+{
+	pwrcal_setf(FSYS1_OPTION, 0, 0xFFFFFFFF, 0x2);
+}
+
+
+
+BLKPWR(blkpwr_cam0,	CAM0_CONFIGURATION,	0,	0xF,	CAM0_STATUS,	0,	0xF,	cam0_config,	cam0_prev,	cam0_post);
+BLKPWR(blkpwr_mscl,	MSCL_CONFIGURATION,	0,	0xF,	MSCL_STATUS,	0,	0xF,	mscl_config,	mscl_prev,	mscl_post);
+BLKPWR(blkpwr_g3d,	G3D_CONFIGURATION,	0,	0xF,	G3D_STATUS,	0,	0xF,	g3d_config,	g3d_prev,	g3d_post);
+BLKPWR(blkpwr_disp0,	DISP0_CONFIGURATION,	0,	0xF,	DISP0_STATUS,	0,	0xF,	disp0_config,	disp0_prev,	disp0_post);
+BLKPWR(blkpwr_cam1,	CAM1_CONFIGURATION,	0,	0xF,	CAM1_STATUS,	0,	0xF,	cam1_config,	cam1_prev,	cam1_post);
+BLKPWR(blkpwr_aud,	AUD_CONFIGURATION,	0,	0xF,	AUD_STATUS,	0,	0xF,	aud_config,	aud_prev,	aud_post);
+BLKPWR(blkpwr_fsys0,	FSYS0_CONFIGURATION,	0,	0xF,	FSYS0_STATUS,	0,	0xF,	fsys0_config,	fsys0_prev,	fsys0_post);
+BLKPWR(blkpwr_isp0,	ISP0_CONFIGURATION,	0,	0xF,	ISP0_STATUS,	0,	0xF,	isp0_config,	isp0_prev,	isp0_post);
+BLKPWR(blkpwr_isp1,	ISP1_CONFIGURATION,	0,	0xF,	ISP1_STATUS,	0,	0xF,	isp1_config,	isp1_prev,	isp1_post);
+BLKPWR(blkpwr_mfc,	MFC_CONFIGURATION,	0,	0xF,	MFC_STATUS,	0,	0xF,	mfc_config,	mfc_prev,	mfc_post);
+BLKPWR(blkpwr_disp1,	DISP1_CONFIGURATION,	0,	0xF,	DISP1_STATUS,	0,	0xF,	disp1_config,	disp1_prev,	disp1_post);
+BLKPWR(blkpwr_fsys1,	FSYS1_CONFIGURATION,	0,	0xF,	FSYS1_STATUS,	0,	0xF,	fsys1_config,	fsys1_prev,	fsys1_post);
+
+struct cal_pd *pwrcal_blkpwr_list[12];
+unsigned int pwrcal_blkpwr_size = 12;
+
+static int blkpwr_int(void)
+{
+	pwrcal_blkpwr_list[0] = &blkpwr_blkpwr_isp0;
+	pwrcal_blkpwr_list[1] = &blkpwr_blkpwr_isp1;
+	pwrcal_blkpwr_list[2] = &blkpwr_blkpwr_cam1;
+	pwrcal_blkpwr_list[3] = &blkpwr_blkpwr_cam0;
+	pwrcal_blkpwr_list[4] = &blkpwr_blkpwr_mscl;
+	pwrcal_blkpwr_list[5] = &blkpwr_blkpwr_g3d;
+	pwrcal_blkpwr_list[6] = &blkpwr_blkpwr_disp0;
+	pwrcal_blkpwr_list[7] = &blkpwr_blkpwr_aud;
+	pwrcal_blkpwr_list[8] = &blkpwr_blkpwr_fsys0;
+	pwrcal_blkpwr_list[9] = &blkpwr_blkpwr_mfc;
+	pwrcal_blkpwr_list[10] = &blkpwr_blkpwr_disp1;
+	pwrcal_blkpwr_list[11] = &blkpwr_blkpwr_fsys1;
+
+	return 0;
+}
+
+struct cal_pd_ops cal_pd_ops = {
+	.pd_control = blkpwr_control,
+	.pd_status = blkpwr_status,
+	.pd_init = blkpwr_int,
+};

drivers/soc/samsung/pwrcal/S5E8890/S5E8890-rae.c

@@ -0,0 +1,99 @@
+#include "../pwrcal-rae.h"
+#include "S5E8890-sfrbase.h"
+
+#ifdef PWRCAL_TARGET_LINUX
+
+struct v2p_sfr v2psfrmap[] = {
+	DEFINE_V2P(CMU_PERIS_BASE,	0x10040000),
+	DEFINE_V2P(CMU_TOP_BASE,	0x10570000),
+	DEFINE_V2P(CMU_CCORE_BASE,	0x105B0000),
+	DEFINE_V2P(CMU_MIF0_BASE,	0x10850000),
+	DEFINE_V2P(CMU_MIF1_BASE,	0x10950000),
+	DEFINE_V2P(CMU_MIF2_BASE,	0x10A50000),
+	DEFINE_V2P(CMU_MIF3_BASE,	0x10B50000),
+	DEFINE_V2P(CMU_FSYS0_BASE,	0x10E90000),
+	DEFINE_V2P(CMU_IMEM_BASE,	0x11060000),
+	DEFINE_V2P(CMU_AUD_BASE,	0x114C0000),
+	DEFINE_V2P(CMU_MNGS_BASE,	0x11800000),
+	DEFINE_V2P(CMU_APOLLO_BASE,	0x11900000),
+	DEFINE_V2P(CMU_BUS0_BASE,	0x13400000),
+	DEFINE_V2P(CMU_BUS1_BASE,	0x14800000),
+	DEFINE_V2P(CMU_PERIC0_BASE,	0x13610000),
+	DEFINE_V2P(CMU_DISP0_BASE,	0x13AD0000),
+	DEFINE_V2P(CMU_DISP1_BASE,	0x13F00000),
+	DEFINE_V2P(CMU_CAM0_LOCAL_BASE,	0x140F0000),
+	DEFINE_V2P(CMU_CAM0_BASE,	0x144D0000),
+	DEFINE_V2P(CMU_CAM1_LOCAL_BASE,	0x141F0000),
+	DEFINE_V2P(CMU_CAM1_BASE,	0x145D0000),
+	DEFINE_V2P(CMU_ISP0_LOCAL_BASE,	0x14290000),
+	DEFINE_V2P(CMU_ISP0_BASE,	0x146D0000),
+	DEFINE_V2P(CMU_ISP1_LOCAL_BASE,	0x142F0000),
+	DEFINE_V2P(CMU_ISP1_BASE,	0x147D0000),
+	DEFINE_V2P(CMU_G3D_BASE,	0x14AA0000),
+	DEFINE_V2P(CMU_PERIC1_BASE,	0x14C80000),
+	DEFINE_V2P(CMU_MSCL_BASE,	0x150D0000),
+	DEFINE_V2P(CMU_MFC_BASE,	0x15280000),
+	DEFINE_V2P(CMU_FSYS1_BASE,	0x156E0000),
+
+
+	DEFINE_V2P(PMU_PERIS_BASE,	0x10010000),
+	DEFINE_V2P(PMU_ALIVE_BASE,	0x105C0000),
+	DEFINE_V2P(PMU_CCORE_BASE,	0x105F0000),
+	DEFINE_V2P(PMU_MIF0_BASE,	0x10840000),
+	DEFINE_V2P(PMU_MIF1_BASE,	0x10940000),
+	DEFINE_V2P(PMU_MIF2_BASE,	0x10A40000),
+	DEFINE_V2P(PMU_MIF3_BASE,	0x10B40000),
+	DEFINE_V2P(PMU_FSYS0_BASE,	0x10E70000),
+	DEFINE_V2P(PMU_IMEM_BASE,	0x11070000),
+	DEFINE_V2P(PMU_AUD_BASE,	0x114D0000),
+	DEFINE_V2P(PMU_MNGS_BASE,	0x11820000),
+	DEFINE_V2P(PMU_APOLLO_BASE,	0x11920000),
+	DEFINE_V2P(PMU_BUS0_BASE,	0x13420000),
+	DEFINE_V2P(PMU_BUS1_BASE,	0x14820000),
+	DEFINE_V2P(PMU_PERIC0_BASE,	0x13600000),
+	DEFINE_V2P(PMU_DISP0_BASE,	0x13AE0000),
+	DEFINE_V2P(PMU_DISP1_BASE,	0x13F10000),
+	DEFINE_V2P(PMU_CAM0_BASE,	0x144E0000),
+	DEFINE_V2P(PMU_CAM1_BASE,	0x145E0000),
+	DEFINE_V2P(PMU_ISP0_BASE,	0x146E0000),
+	DEFINE_V2P(PMU_ISP1_BASE,	0x147E0000),
+	DEFINE_V2P(PMU_G3D_BASE,	0x14A40000),
+	DEFINE_V2P(PMU_PERIC1_BASE,	0x14C70000),
+	DEFINE_V2P(PMU_MSCL_BASE,	0x150F0000),
+	DEFINE_V2P(PMU_MFC_BASE,	0x15290000),
+	DEFINE_V2P(PMU_FSYS1_BASE,	0x156C0000),
+
+	DEFINE_V2P(DMC_MISC_CCORE_BASE,	0x10520000),
+	DEFINE_V2P(LPDDR4_PHY0_BASE,	0x10820000),
+
+	DEFINE_V2P(SYSREG_APOLLO_BASE,	0x11940000),
+	DEFINE_V2P(SYSREG_AUD_BASE,	0x11480000),
+	DEFINE_V2P(SYSREG_BUS0_BASE,	0x134C0000),
+	DEFINE_V2P(SYSREG_BUS1_BASE,	0x148C0000),
+	DEFINE_V2P(SYSREG_CAM0_BASE,	0x144F0000),
+	DEFINE_V2P(SYSREG_CAM1_BASE,	0x145F0000),
+	DEFINE_V2P(SYSREG_CCORE_BASE,	0x105D0000),
+	DEFINE_V2P(SYSREG_DISP0_BASE,	0x13A60000),
+	DEFINE_V2P(SYSREG_DISP1_BASE,	0x13F20000),
+	DEFINE_V2P(SYSREG_FSYS0_BASE,	0x10E50000),
+	DEFINE_V2P(SYSREG_FSYS1_BASE,	0x15600000),
+	DEFINE_V2P(SYSREG_G3D_BASE,	0x14AE0000),
+	DEFINE_V2P(SYSREG_IMEM_BASE,	0x11080000),
+	DEFINE_V2P(SYSREG_ISP0_BASE,	0x146F0000),
+	DEFINE_V2P(SYSREG_ISP1_BASE,	0x147F0000),
+	DEFINE_V2P(SYSREG_MFC_BASE,	0x152A0000),
+	DEFINE_V2P(SYSREG_MIF0_BASE,	0x10830000),
+	DEFINE_V2P(SYSREG_MIF1_BASE,	0x10930000),
+	DEFINE_V2P(SYSREG_MIF2_BASE,	0x10A30000),
+	DEFINE_V2P(SYSREG_MIF3_BASE,	0x10B30000),
+	DEFINE_V2P(SYSREG_MNGS_BASE,	0x11850000),
+	DEFINE_V2P(SYSREG_MSCL_BASE,	0x151C0000),
+	DEFINE_V2P(SYSREG_PERIC0_BASE,	0x136E0000),
+	DEFINE_V2P(SYSREG_PERIC1_BASE,	0x14C60000),
+	DEFINE_V2P(SYSREG_PERIS_BASE,	0x10050000),
+};
+
+int num_of_v2psfrmap = sizeof(v2psfrmap) / sizeof(v2psfrmap[0]);
+void *spinlock_enable_offset = (void *)PMU_PERIS_BASE;
+
+#endif

drivers/soc/samsung/pwrcal/S5E8890/S5E8890-sfrbase.h

@@ -0,0 +1,190 @@
+#ifndef __EXYNOS8890_SFRBASE_H__
+#define __EXYNOS8890_SFRBASE_H__
+
+#include "../pwrcal-env.h"
+
+#ifdef PWRCAL_TARGET_FW
+
+#define CMU_PERIS_BASE	0x10040000
+#define CMU_TOP_BASE	0x10570000
+#define CMU_CCORE_BASE	0x105B0000
+#define CMU_MIF0_BASE	0x10850000
+#define CMU_MIF1_BASE	0x10950000
+#define CMU_MIF2_BASE	0x10A50000
+#define CMU_MIF3_BASE	0x10B50000
+#define CMU_FSYS0_BASE	0x10E90000
+#define CMU_IMEM_BASE	0x11060000
+#define CMU_AUD_BASE	0x114C0000
+#define CMU_MNGS_BASE	0x11800000
+#define CMU_APOLLO_BASE	0x11900000
+#define CMU_BUS0_BASE	0x13400000
+#define CMU_BUS1_BASE	0x14800000
+#define CMU_PERIC0_BASE	0x13610000
+#define CMU_DISP0_BASE	0x13AD0000
+#define CMU_DISP1_BASE	0x13F00000
+#define CMU_CAM0_LOCAL_BASE	0x140F0000
+#define CMU_CAM0_BASE	0x144D0000
+#define CMU_CAM1_LOCAL_BASE	0x141F0000
+#define CMU_CAM1_BASE	0x145D0000
+#define CMU_ISP0_LOCAL_BASE	0x14290000
+#define CMU_ISP0_BASE	0x146D0000
+#define CMU_ISP1_LOCAL_BASE	0x142F0000
+#define CMU_ISP1_BASE	0x147D0000
+#define CMU_G3D_BASE	0x14AA0000
+#define CMU_PERIC1_BASE	0x14C80000
+#define CMU_MSCL_BASE	0x150D0000
+#define CMU_MFC_BASE	0x15280000
+#define CMU_FSYS1_BASE	0x156E0000
+
+
+#define PMU_PERIS_BASE	0x10010000
+#define PMU_ALIVE_BASE	0x105C0000
+#define PMU_CCORE_BASE	0x105F0000
+#define PMU_MIF0_BASE	0x10840000
+#define PMU_MIF1_BASE	0x10940000
+#define PMU_MIF2_BASE	0x10A40000
+#define PMU_MIF3_BASE	0x10B40000
+#define PMU_FSYS0_BASE	0x10E70000
+#define PMU_IMEM_BASE	0x11070000
+#define PMU_AUD_BASE	0x114D0000
+#define PMU_MNGS_BASE	0x11820000
+#define PMU_APOLLO_BASE	0x11920000
+#define PMU_BUS0_BASE	0x13420000
+#define PMU_BUS1_BASE	0x14820000
+#define PMU_PERIC0_BASE	0x13600000
+#define PMU_DISP0_BASE	0x13AE0000
+#define PMU_DISP1_BASE	0x13F10000
+#define PMU_CAM0_BASE	0x144E0000
+#define PMU_CAM1_BASE	0x145E0000
+#define PMU_ISP0_BASE	0x146E0000
+#define PMU_ISP1_BASE	0x147E0000
+#define PMU_G3D_BASE	0x14A40000
+#define PMU_PERIC1_BASE	0x14C70000
+#define PMU_MSCL_BASE	0x150F0000
+#define PMU_MFC_BASE	0x15290000
+#define PMU_FSYS1_BASE	0x156C0000
+
+#define DMC_MISC_CCORE_BASE	0x10520000
+#define LPDDR4_PHY0_BASE	0x10820000
+
+#define SYSREG_APOLLO_BASE	0x11940000
+#define SYSREG_AUD_BASE	0x11480000
+#define SYSREG_BUS0_BASE	0x134C0000
+#define SYSREG_BUS1_BASE	0x148C0000
+#define SYSREG_CAM0_BASE	0x144F0000
+#define SYSREG_CAM1_BASE	0x145F0000
+#define SYSREG_CCORE_BASE	0x105D0000
+#define SYSREG_DISP0_BASE	0x13A60000
+#define SYSREG_DISP1_BASE	0x13F20000
+#define SYSREG_FSYS0_BASE	0x10E50000
+#define SYSREG_FSYS1_BASE	0x15600000
+#define SYSREG_G3D_BASE	0x14AE0000
+#define SYSREG_IMEM_BASE	0x11080000
+#define SYSREG_ISP0_BASE	0x146F0000
+#define SYSREG_ISP1_BASE	0x147F0000
+#define SYSREG_MFC_BASE	0x152A0000
+#define SYSREG_MIF0_BASE	0x10830000
+#define SYSREG_MIF1_BASE	0x10930000
+#define SYSREG_MIF2_BASE	0x10A30000
+#define SYSREG_MIF3_BASE	0x10B30000
+#define SYSREG_MNGS_BASE	0x11850000
+#define SYSREG_MSCL_BASE	0x151C0000
+#define SYSREG_PERIC0_BASE	0x136E0000
+#define SYSREG_PERIC1_BASE	0x14C60000
+#define SYSREG_PERIS_BASE	0x10050000
+
+#endif
+
+#ifdef PWRCAL_TARGET_LINUX
+
+#define CMU_PERIS_BASE	0x00010000
+#define CMU_TOP_BASE	0x00020000
+#define CMU_CCORE_BASE	0x00030000
+#define CMU_MIF0_BASE	0x00040000
+#define CMU_MIF1_BASE	0x00050000
+#define CMU_MIF2_BASE	0x00060000
+#define CMU_MIF3_BASE	0x00070000
+#define CMU_FSYS0_BASE	0x00080000
+#define CMU_IMEM_BASE	0x00090000
+#define CMU_AUD_BASE	0x000A0000
+#define CMU_MNGS_BASE	0x000B0000
+#define CMU_APOLLO_BASE	0x000C0000
+#define CMU_BUS0_BASE	0x000D0000
+#define CMU_BUS1_BASE	0x000E0000
+#define CMU_PERIC0_BASE	0x000F0000
+#define CMU_DISP0_BASE	0x00100000
+#define CMU_DISP1_BASE	0x00110000
+#define CMU_CAM0_LOCAL_BASE	0x00120000
+#define CMU_CAM0_BASE	0x00130000
+#define CMU_CAM1_LOCAL_BASE	0x00140000
+#define CMU_CAM1_BASE	0x00150000
+#define CMU_ISP0_LOCAL_BASE	0x00160000
+#define CMU_ISP0_BASE	0x00170000
+#define CMU_ISP1_LOCAL_BASE	0x00180000
+#define CMU_ISP1_BASE	0x00190000
+#define CMU_G3D_BASE	0x001A0000
+#define CMU_PERIC1_BASE	0x001B0000
+#define CMU_MSCL_BASE	0x001C0000
+#define CMU_MFC_BASE	0x001D0000
+#define CMU_FSYS1_BASE	0x001E0000
+
+
+#define PMU_PERIS_BASE	0x001F0000
+#define PMU_ALIVE_BASE	0x00200000
+#define PMU_CCORE_BASE	0x00210000
+#define PMU_MIF0_BASE	0x00220000
+#define PMU_MIF1_BASE	0x00230000
+#define PMU_MIF2_BASE	0x00240000
+#define PMU_MIF3_BASE	0x00250000
+#define PMU_FSYS0_BASE	0x00260000
+#define PMU_IMEM_BASE	0x00270000
+#define PMU_AUD_BASE	0x00280000
+#define PMU_MNGS_BASE	0x00290000
+#define PMU_APOLLO_BASE	0x002A0000
+#define PMU_BUS0_BASE	0x002B0000
+#define PMU_BUS1_BASE	0x002C0000
+#define PMU_PERIC0_BASE	0x002D0000
+#define PMU_DISP0_BASE	0x002E0000
+#define PMU_DISP1_BASE	0x002F0000
+#define PMU_CAM0_BASE	0x00300000
+#define PMU_CAM1_BASE	0x00310000
+#define PMU_ISP0_BASE	0x00320000
+#define PMU_ISP1_BASE	0x00330000
+#define PMU_G3D_BASE	0x00340000
+#define PMU_PERIC1_BASE	0x00350000
+#define PMU_MSCL_BASE	0x00360000
+#define PMU_MFC_BASE	0x00370000
+#define PMU_FSYS1_BASE	0x00380000
+
+#define DMC_MISC_CCORE_BASE	0x00390000
+#define LPDDR4_PHY0_BASE	0x003A0000
+
+#define SYSREG_APOLLO_BASE	0x003B0000
+#define SYSREG_AUD_BASE	0x003C0000
+#define SYSREG_BUS0_BASE	0x003D0000
+#define SYSREG_BUS1_BASE	0x003E0000
+#define SYSREG_CAM0_BASE	0x003F0000
+#define SYSREG_CAM1_BASE	0x00400000
+#define SYSREG_CCORE_BASE	0x00410000
+#define SYSREG_DISP0_BASE	0x00420000
+#define SYSREG_DISP1_BASE	0x00430000
+#define SYSREG_FSYS0_BASE	0x00440000
+#define SYSREG_FSYS1_BASE	0x00450000
+#define SYSREG_G3D_BASE	0x00460000
+#define SYSREG_IMEM_BASE	0x00470000
+#define SYSREG_ISP0_BASE	0x00480000
+#define SYSREG_ISP1_BASE	0x00490000
+#define SYSREG_MFC_BASE	0x004A0000
+#define SYSREG_MIF0_BASE	0x004B0000
+#define SYSREG_MIF1_BASE	0x004C0000
+#define SYSREG_MIF2_BASE	0x004D0000
+#define SYSREG_MIF3_BASE	0x004E0000
+#define SYSREG_MNGS_BASE	0x004F0000
+#define SYSREG_MSCL_BASE	0x00500000
+#define SYSREG_PERIC0_BASE	0x00510000
+#define SYSREG_PERIC1_BASE	0x00520000
+#define SYSREG_PERIS_BASE	0x00530000
+
+#endif
+
+#endif

drivers/soc/samsung/pwrcal/S5E8890/S5E8890-vclk-internal.h

@@ -0,0 +1,407 @@
+#ifndef __EXYNOS8890_VCLKS_H__
+#define __EXYNOS8890_VCLKS_H__
+
+#include "../pwrcal-vclk.h"
+#include "../pwrcal-pmu.h"
+#include "S5E8890-vclk.h"
+
+
+GRPGATE_EXTERN(gate_apollo_ppmu)
+GRPGATE_EXTERN(gate_apollo_bts)
+GRPGATE_EXTERN(gate_mngs_ppmu)
+GRPGATE_EXTERN(gate_mngs_bts)
+GRPGATE_EXTERN(gate_aud_common)
+GRPGATE_EXTERN(gate_aud_lpass)
+GRPGATE_EXTERN(gate_aud_mi2s)
+GRPGATE_EXTERN(gate_aud_pcm)
+GRPGATE_EXTERN(gate_aud_uart)
+GRPGATE_EXTERN(gate_aud_dma)
+GRPGATE_EXTERN(gate_aud_slimbus)
+GRPGATE_EXTERN(gate_aud_sysmmu)
+GRPGATE_EXTERN(gate_aud_ppmu)
+GRPGATE_EXTERN(gate_aud_bts)
+GRPGATE_EXTERN(gate_aud_sclk_mi2s)
+GRPGATE_EXTERN(gate_aud_sclk_pcm)
+GRPGATE_EXTERN(gate_aud_sclk_slimbus)
+GRPGATE_EXTERN(gate_bus0_display)
+GRPGATE_EXTERN(gate_bus0_cam)
+GRPGATE_EXTERN(gate_bus0_fsys1)
+GRPGATE_EXTERN(gate_bus1_mfc)
+GRPGATE_EXTERN(gate_bus1_mscl)
+GRPGATE_EXTERN(gate_bus1_fsys0)
+GRPGATE_EXTERN(gate_cam0_common)
+GRPGATE_EXTERN(gate_cam0_csis0)
+GRPGATE_EXTERN(gate_cam0_csis1)
+GRPGATE_EXTERN(gate_cam0_fimc_bns)
+GRPGATE_EXTERN(gate_cam0_fimc_3aa0)
+GRPGATE_EXTERN(gate_cam0_fimc_3aa1)
+GRPGATE_EXTERN(gate_cam0_hpm)
+GRPGATE_EXTERN(gate_cam0_sysmmu)
+GRPGATE_EXTERN(gate_cam0_ppmu)
+GRPGATE_EXTERN(gate_cam0_bts)
+GRPGATE_EXTERN(gate_cam0_phyclk_hs0_csis0_rx_byte)
+GRPGATE_EXTERN(gate_cam0_phyclk_hs1_csis0_rx_byte)
+GRPGATE_EXTERN(gate_cam0_phyclk_hs2_csis0_rx_byte)
+GRPGATE_EXTERN(gate_cam0_phyclk_hs3_csis0_rx_byte)
+GRPGATE_EXTERN(gate_cam0_phyclk_hs0_csis1_rx_byte)
+GRPGATE_EXTERN(gate_cam0_phyclk_hs1_csis1_rx_byte)
+GRPGATE_EXTERN(gate_cam1_common)
+GRPGATE_EXTERN(gate_cam1_isp_cpu_gic_common)
+GRPGATE_EXTERN(gate_cam1_isp_cpu)
+GRPGATE_EXTERN(gate_cam1_gic_is)
+GRPGATE_EXTERN(gate_cam1_csis2)
+GRPGATE_EXTERN(gate_cam1_csis3)
+GRPGATE_EXTERN(gate_cam1_fimc_vra)
+GRPGATE_EXTERN(gate_cam1_mc_scaler)
+GRPGATE_EXTERN(gate_cam1_i2c0_isp)
+GRPGATE_EXTERN(gate_cam1_i2c1_isp)
+GRPGATE_EXTERN(gate_cam1_i2c2_isp)
+GRPGATE_EXTERN(gate_cam1_i2c3_isp)
+GRPGATE_EXTERN(gate_cam1_wdt_isp)
+GRPGATE_EXTERN(gate_cam1_mcuctl_isp)
+GRPGATE_EXTERN(gate_cam1_uart_isp)
+GRPGATE_EXTERN(gate_cam1_sclk_uart_isp)
+GRPGATE_EXTERN(gate_cam1_spi0_isp)
+GRPGATE_EXTERN(gate_cam1_spi1_isp)
+GRPGATE_EXTERN(gate_cam1_pdma_isp)
+GRPGATE_EXTERN(gate_cam1_pwm_isp)
+GRPGATE_EXTERN(gate_cam1_sclk_pwm_isp)
+GRPGATE_EXTERN(gate_cam1_sysmmu)
+GRPGATE_EXTERN(gate_cam1_ppmu)
+GRPGATE_EXTERN(gate_cam1_bts)
+GRPGATE_EXTERN(gate_cam1_phyclk_hs0_csis2_rx_byte)
+GRPGATE_EXTERN(gate_cam1_phyclk_hs1_csis2_rx_byte)
+GRPGATE_EXTERN(gate_cam1_phyclk_hs2_csis2_rx_byte)
+GRPGATE_EXTERN(gate_cam1_phyclk_hs3_csis2_rx_byte)
+GRPGATE_EXTERN(gate_cam1_phyclk_hs0_csis3_rx_byte)
+GRPGATE_EXTERN(gate_disp0_common)
+GRPGATE_EXTERN(gate_disp0_decon0)
+GRPGATE_EXTERN(gate_disp0_dsim0)
+GRPGATE_EXTERN(gate_disp0_dsim1)
+GRPGATE_EXTERN(gate_disp0_dsim2)
+GRPGATE_EXTERN(gate_disp0_hdmi)
+GRPGATE_EXTERN(gate_disp0_dp)
+GRPGATE_EXTERN(gate_disp0_hpm_apbif_disp0)
+GRPGATE_EXTERN(gate_disp0_sysmmu)
+GRPGATE_EXTERN(gate_disp0_ppmu)
+GRPGATE_EXTERN(gate_disp0_bts)
+GRPGATE_EXTERN(gate_disp0_phyclk_hdmiphy_tmds_20b_clko)
+GRPGATE_EXTERN(gate_disp0_phyclk_hdmiphy_tmds_10b_clko)
+GRPGATE_EXTERN(gate_disp0_phyclk_hdmiphy_pixel_clko)
+GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy0_rxclkesc0)
+GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy0_bitclkdiv8)
+GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy1_rxclkesc0)
+GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy1_bitclkdiv8)
+GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy2_rxclkesc0)
+GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy2_bitclkdiv8)
+GRPGATE_EXTERN(gate_disp0_phyclk_dpphy_ch0_txd_clk)
+GRPGATE_EXTERN(gate_disp0_phyclk_dpphy_ch1_txd_clk)
+GRPGATE_EXTERN(gate_disp0_phyclk_dpphy_ch2_txd_clk)
+GRPGATE_EXTERN(gate_disp0_phyclk_dpphy_ch3_txd_clk)
+GRPGATE_EXTERN(gate_disp0_oscclk_dp_i_clk_24m)
+GRPGATE_EXTERN(gate_disp0_oscclk_i_dptx_phy_i_ref_clk_24m)
+GRPGATE_EXTERN(gate_disp0_oscclk_i_mipi_dphy_m1s0_m_xi)
+GRPGATE_EXTERN(gate_disp0_oscclk_i_mipi_dphy_m4s0_m_xi)
+GRPGATE_EXTERN(gate_disp0_oscclk_i_mipi_dphy_m4s4_m_xi)
+GRPGATE_EXTERN(gate_disp1_common)
+GRPGATE_EXTERN(gate_disp1_decon1)
+GRPGATE_EXTERN(gate_disp1_hpmdisp1)
+GRPGATE_EXTERN(gate_disp1_sysmmu)
+GRPGATE_EXTERN(gate_disp1_ppmu)
+GRPGATE_EXTERN(gate_disp1_bts)
+GRPGATE_EXTERN(gate_fsys0_common)
+GRPGATE_EXTERN(gate_fsys0_usbdrd_etrusb_common)
+GRPGATE_EXTERN(gate_fsys0_usbdrd30)
+GRPGATE_EXTERN(gate_fsys0_etr_usb)
+GRPGATE_EXTERN(gate_fsys0_usbhost20)
+GRPGATE_EXTERN(gate_fsys0_mmc0_ufs_common)
+GRPGATE_EXTERN(gate_fsys0_mmc0)
+GRPGATE_EXTERN(gate_fsys0_ufs_linkemedded)
+GRPGATE_EXTERN(gate_fsys0_pdma_common)
+GRPGATE_EXTERN(gate_fsys0_pdma0)
+GRPGATE_EXTERN(gate_fsys0_pdmas)
+GRPGATE_EXTERN(gate_fsys0_ppmu)
+GRPGATE_EXTERN(gate_fsys0_bts)
+GRPGATE_EXTERN(gate_fsys0_hpm)
+GRPGATE_EXTERN(gate_fsys0_phyclk_usbdrd30_udrd30_phyclock)
+GRPGATE_EXTERN(gate_fsys0_phyclk_usbdrd30_udrd30_pipe_pclk)
+GRPGATE_EXTERN(gate_fsys0_phyclk_ufs_tx0_symbol)
+GRPGATE_EXTERN(gate_fsys0_phyclk_ufs_rx0_symbol)
+GRPGATE_EXTERN(gate_fsys0_phyclk_usbhost20_phyclock)
+GRPGATE_EXTERN(gate_fsys0_phyclk_usbhost20_freeclk)
+GRPGATE_EXTERN(gate_fsys0_phyclk_usbhost20_clk48mohci)
+GRPGATE_EXTERN(gate_fsys0_phyclk_usbhost20phy_ref_clk)
+GRPGATE_EXTERN(gate_fsys0_phyclk_ufs_rx_pwm_clk)
+GRPGATE_EXTERN(gate_fsys0_phyclk_ufs_tx_pwm_clk)
+GRPGATE_EXTERN(gate_fsys0_phyclk_ufs_refclk_out_soc)
+GRPGATE_EXTERN(gate_fsys1_common)
+GRPGATE_EXTERN(gate_fsys1_mmc2_ufs_common)
+GRPGATE_EXTERN(gate_fsys1_mmc2)
+GRPGATE_EXTERN(gate_fsys1_ufs20_sdcard)
+GRPGATE_EXTERN(gate_fsys1_sromc)
+GRPGATE_EXTERN(gate_fsys1_pciewifi0)
+GRPGATE_EXTERN(gate_fsys1_pciewifi1)
+GRPGATE_EXTERN(gate_fsys1_ppmu)
+GRPGATE_EXTERN(gate_fsys1_bts)
+GRPGATE_EXTERN(gate_fsys1_hpm)
+GRPGATE_EXTERN(gate_fsys1_phyclk_ufs_link_sdcard_tx0_symbol)
+GRPGATE_EXTERN(gate_fsys1_phyclk_ufs_link_sdcard_rx0_symbol)
+GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi0_tx0)
+GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi0_rx0)
+GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi1_tx0)
+GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi1_rx0)
+GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi0_dig_refclk)
+GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi1_dig_refclk)
+GRPGATE_EXTERN(gate_fsys1_phyclk_ufs_link_sdcard_rx_pwm_clk)
+GRPGATE_EXTERN(gate_fsys1_phyclk_ufs_link_sdcard_tx_pwm_clk)
+GRPGATE_EXTERN(gate_fsys1_phyclk_ufs_link_sdcard_refclk_out_soc)
+GRPGATE_EXTERN(gate_g3d_common)
+GRPGATE_EXTERN(gate_g3d_g3d_common)
+GRPGATE_EXTERN(gate_g3d_g3d)
+GRPGATE_EXTERN(gate_g3d_iram_path_test)
+GRPGATE_EXTERN(gate_g3d_ppmu)
+GRPGATE_EXTERN(gate_g3d_bts)
+GRPGATE_EXTERN(gate_imem_common)
+GRPGATE_EXTERN(gate_imem_apm_sss_rtic_mc_common)
+GRPGATE_EXTERN(gate_imem_apm)
+GRPGATE_EXTERN(gate_imem_sss)
+GRPGATE_EXTERN(gate_imem_rtic)
+GRPGATE_EXTERN(gate_imem_mc)
+GRPGATE_EXTERN(gate_imem_intmem)
+GRPGATE_EXTERN(gate_imem_intmem_alv)
+GRPGATE_EXTERN(gate_imem_gic400)
+GRPGATE_EXTERN(gate_imem_ppmu)
+GRPGATE_EXTERN(gate_isp0_common)
+GRPGATE_EXTERN(gate_isp0_fimc_isp0)
+GRPGATE_EXTERN(gate_isp0_fimc_tpu)
+GRPGATE_EXTERN(gate_isp0_sysmmu)
+GRPGATE_EXTERN(gate_isp0_ppmu)
+GRPGATE_EXTERN(gate_isp0_bts)
+GRPGATE_EXTERN(gate_isp1_fimc_isp1)
+GRPGATE_EXTERN(gate_isp1_sysmmu)
+GRPGATE_EXTERN(gate_isp1_ppmu)
+GRPGATE_EXTERN(gate_isp1_bts)
+GRPGATE_EXTERN(gate_mfc_common)
+GRPGATE_EXTERN(gate_mfc_mfc)
+GRPGATE_EXTERN(gate_mfc_hpm)
+GRPGATE_EXTERN(gate_mfc_sysmmu)
+GRPGATE_EXTERN(gate_mfc_ppmu)
+GRPGATE_EXTERN(gate_mscl_common)
+GRPGATE_EXTERN(gate_mscl_mscl0_jpeg_common)
+GRPGATE_EXTERN(gate_mscl_mscl0)
+GRPGATE_EXTERN(gate_mscl_jpeg)
+GRPGATE_EXTERN(gate_mscl_mscl1_g2d_common)
+GRPGATE_EXTERN(gate_mscl_mscl1)
+GRPGATE_EXTERN(gate_mscl_g2d)
+GRPGATE_EXTERN(gate_mscl_sysmmu)
+GRPGATE_EXTERN(gate_mscl_ppmu)
+GRPGATE_EXTERN(gate_mscl_bts)
+GRPGATE_EXTERN(gate_peric0_hsi2c0)
+GRPGATE_EXTERN(gate_peric0_hsi2c1)
+GRPGATE_EXTERN(gate_peric0_hsi2c4)
+GRPGATE_EXTERN(gate_peric0_hsi2c5)
+GRPGATE_EXTERN(gate_peric0_hsi2c9)
+GRPGATE_EXTERN(gate_peric0_hsi2c10)
+GRPGATE_EXTERN(gate_peric0_hsi2c11)
+GRPGATE_EXTERN(gate_peric0_uart0)
+GRPGATE_EXTERN(gate_peric0_adcif)
+GRPGATE_EXTERN(gate_peric0_pwm)
+GRPGATE_EXTERN(gate_peric0_sclk_pwm)
+GRPGATE_EXTERN(gate_peric1_hsi2c_common)
+GRPGATE_EXTERN(gate_peric1_hsi2c2)
+GRPGATE_EXTERN(gate_peric1_hsi2c3)
+GRPGATE_EXTERN(gate_peric1_hsi2c6)
+GRPGATE_EXTERN(gate_peric1_hsi2c7)
+GRPGATE_EXTERN(gate_peric1_hsi2c8)
+GRPGATE_EXTERN(gate_peric1_hsi2c12)
+GRPGATE_EXTERN(gate_peric1_hsi2c13)
+GRPGATE_EXTERN(gate_peric1_hsi2c14)
+GRPGATE_EXTERN(gate_peric1_spi_i2s_pcm1_spdif_common)
+GRPGATE_EXTERN(gate_peric1_uart1)
+GRPGATE_EXTERN(gate_peric1_uart2)
+GRPGATE_EXTERN(gate_peric1_uart3)
+GRPGATE_EXTERN(gate_peric1_uart4)
+GRPGATE_EXTERN(gate_peric1_uart5)
+GRPGATE_EXTERN(gate_peric1_spi0)
+GRPGATE_EXTERN(gate_peric1_spi1)
+GRPGATE_EXTERN(gate_peric1_spi2)
+GRPGATE_EXTERN(gate_peric1_spi3)
+GRPGATE_EXTERN(gate_peric1_spi4)
+GRPGATE_EXTERN(gate_peric1_spi5)
+GRPGATE_EXTERN(gate_peric1_spi6)
+GRPGATE_EXTERN(gate_peric1_spi7)
+GRPGATE_EXTERN(gate_peric1_i2s1)
+GRPGATE_EXTERN(gate_peric1_pcm1)
+GRPGATE_EXTERN(gate_peric1_spdif)
+GRPGATE_EXTERN(gate_peric1_gpio_nfc)
+GRPGATE_EXTERN(gate_peric1_gpio_touch)
+GRPGATE_EXTERN(gate_peric1_gpio_fp)
+GRPGATE_EXTERN(gate_peric1_gpio_ese)
+GRPGATE_EXTERN(gate_peris_sfr_apbif_hdmi_cec)
+GRPGATE_EXTERN(gate_peris_hpm)
+GRPGATE_EXTERN(gate_peris_mct)
+GRPGATE_EXTERN(gate_peris_wdt_mngs)
+GRPGATE_EXTERN(gate_peris_wdt_apollo)
+GRPGATE_EXTERN(gate_peris_sysreg_peris)
+GRPGATE_EXTERN(gate_peris_monocnt_apbif)
+GRPGATE_EXTERN(gate_peris_rtc_apbif)
+GRPGATE_EXTERN(gate_peris_top_rtc)
+GRPGATE_EXTERN(gate_peris_otp_con_top)
+GRPGATE_EXTERN(gate_peris_chipid)
+GRPGATE_EXTERN(gate_peris_tmu)
+
+M1D1G1_EXTERN(sclk_decon0_eclk0)
+M1D1G1_EXTERN(sclk_decon0_vclk0)
+M1D1G1_EXTERN(sclk_decon0_vclk1)
+M1D1G1_EXTERN(sclk_hdmi_audio)
+M1D1G1_EXTERN(sclk_decon1_eclk0)
+M1D1G1_EXTERN(sclk_decon1_eclk1)
+M1D1G1_EXTERN(sclk_usbdrd30)
+M1D1G1_EXTERN(sclk_mmc0)
+M1D1G1_EXTERN(sclk_ufsunipro20)
+M1D1G1_EXTERN(sclk_phy24m)
+M1D1G1_EXTERN(sclk_ufsunipro_cfg)
+M1D1G1_EXTERN(sclk_mmc2)
+M1D1G1_EXTERN(sclk_ufsunipro20_sdcard)
+M1D1G1_EXTERN(sclk_pcie_phy)
+M1D1G1_EXTERN(sclk_ufsunipro_sdcard_cfg)
+M1D1G1_EXTERN(sclk_uart0)
+M1D1G1_EXTERN(sclk_spi0)
+M1D1G1_EXTERN(sclk_spi1)
+M1D1G1_EXTERN(sclk_spi2)
+M1D1G1_EXTERN(sclk_spi3)
+M1D1G1_EXTERN(sclk_spi4)
+M1D1G1_EXTERN(sclk_spi5)
+M1D1G1_EXTERN(sclk_spi6)
+M1D1G1_EXTERN(sclk_spi7)
+M1D1G1_EXTERN(sclk_uart1)
+M1D1G1_EXTERN(sclk_uart2)
+M1D1G1_EXTERN(sclk_uart3)
+M1D1G1_EXTERN(sclk_uart4)
+M1D1G1_EXTERN(sclk_uart5)
+M1D1G1_EXTERN(sclk_promise_int)
+M1D1G1_EXTERN(sclk_promise_disp)
+M1D1G1_EXTERN(sclk_ap2cp_mif_pll_out)
+M1D1G1_EXTERN(sclk_isp_spi0)
+M1D1G1_EXTERN(sclk_isp_spi1)
+M1D1G1_EXTERN(sclk_isp_uart)
+M1D1G1_EXTERN(sclk_isp_sensor0)
+M1D1G1_EXTERN(sclk_isp_sensor1)
+M1D1G1_EXTERN(sclk_isp_sensor2)
+M1D1G1_EXTERN(sclk_isp_sensor3)
+M1D1G1_EXTERN(sclk_decon0_eclk0_local)
+M1D1G1_EXTERN(sclk_decon0_vclk0_local)
+M1D1G1_EXTERN(sclk_decon0_vclk1_local)
+M1D1G1_EXTERN(sclk_decon1_eclk0_local)
+M1D1G1_EXTERN(sclk_decon1_eclk1_local)
+
+P1_EXTERN(p1_disp_pll)
+P1_EXTERN(p1_aud_pll)
+P1_EXTERN(p1_mfc_pll)
+
+D1_EXTERN(d1_sclk_i2s_local)
+D1_EXTERN(d1_sclk_pcm_local)
+D1_EXTERN(d1_sclk_slimbus)
+D1_EXTERN(d1_sclk_cp_i2s)
+D1_EXTERN(d1_sclk_asrc)
+
+PXMXDX_EXTERN(pxmxdx_top)
+PXMXDX_EXTERN(pxmxdx_mfc)
+PXMXDX_EXTERN(pxmxdx_mscl)
+PXMXDX_EXTERN(pxmxdx_imem)
+PXMXDX_EXTERN(pxmxdx_fsys0)
+PXMXDX_EXTERN(pxmxdx_fsys1)
+PXMXDX_EXTERN(pxmxdx_disp0)
+PXMXDX_EXTERN(pxmxdx_disp1)
+PXMXDX_EXTERN(pxmxdx_aud)
+PXMXDX_EXTERN(pxmxdx_aud_cp)
+PXMXDX_EXTERN(pxmxdx_isp0_isp0)
+PXMXDX_EXTERN(pxmxdx_isp0_tpu)
+PXMXDX_EXTERN(pxmxdx_isp0_trex)
+PXMXDX_EXTERN(pxmxdx_isp0_pxl_asbs)
+PXMXDX_EXTERN(pxmxdx_isp1_isp1)
+PXMXDX_EXTERN(pxmxdx_cam0_csis0)
+PXMXDX_EXTERN(pxmxdx_cam0_csis1)
+PXMXDX_EXTERN(pxmxdx_cam0_csis2)
+PXMXDX_EXTERN(pxmxdx_cam0_csis3)
+PXMXDX_EXTERN(pxmxdx_cam0_3aa0)
+PXMXDX_EXTERN(pxmxdx_cam0_3aa1)
+PXMXDX_EXTERN(pxmxdx_cam0_trex)
+PXMXDX_EXTERN(pxmxdx_cam1_arm)
+PXMXDX_EXTERN(pxmxdx_cam1_vra)
+PXMXDX_EXTERN(pxmxdx_cam1_trex)
+PXMXDX_EXTERN(pxmxdx_cam1_bus)
+PXMXDX_EXTERN(pxmxdx_cam1_peri)
+PXMXDX_EXTERN(pxmxdx_cam1_csis2)
+PXMXDX_EXTERN(pxmxdx_cam1_csis3)
+PXMXDX_EXTERN(pxmxdx_cam1_scl)
+PXMXDX_EXTERN(pxmxdx_oscclk_nfc)
+PXMXDX_EXTERN(pxmxdx_oscclk_aud)
+
+UMUX_EXTERN(umux_bus0_aclk_bus0_528)
+UMUX_EXTERN(umux_bus0_aclk_bus0_200)
+UMUX_EXTERN(umux_bus1_aclk_bus1_528)
+UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs0_csis0_user)
+UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs1_csis0_user)
+UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs2_csis0_user)
+UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs3_csis0_user)
+UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs0_csis1_user)
+UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs1_csis1_user)
+UMUX_EXTERN(umux_cam1_phyclk_rxbyteclkhs0_csis2_user)
+UMUX_EXTERN(umux_cam1_phyclk_rxbyteclkhs1_csis2_user)
+UMUX_EXTERN(umux_cam1_phyclk_rxbyteclkhs2_csis2_user)
+UMUX_EXTERN(umux_cam1_phyclk_rxbyteclkhs3_csis2_user)
+UMUX_EXTERN(umux_cam1_phyclk_rxbyteclkhs0_csis3_user)
+UMUX_EXTERN(umux_disp0_phyclk_hdmiphy_pixel_clko_user)
+UMUX_EXTERN(umux_disp0_phyclk_hdmiphy_tmds_clko_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy0_rxclkesc0_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy0_bitclkdiv2_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy0_bitclkdiv8_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy1_rxclkesc0_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy1_bitclkdiv2_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy1_bitclkdiv8_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy2_rxclkesc0_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy2_bitclkdiv2_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy2_bitclkdiv8_user)
+UMUX_EXTERN(umux_disp0_phyclk_dpphy_ch0_txd_clk_user)
+UMUX_EXTERN(umux_disp0_phyclk_dpphy_ch1_txd_clk_user)
+UMUX_EXTERN(umux_disp0_phyclk_dpphy_ch2_txd_clk_user)
+UMUX_EXTERN(umux_disp0_phyclk_dpphy_ch3_txd_clk_user)
+UMUX_EXTERN(umux_disp1_phyclk_mipidphy0_bitclkdiv2_user)
+UMUX_EXTERN(umux_disp1_phyclk_mipidphy1_bitclkdiv2_user)
+UMUX_EXTERN(umux_disp1_phyclk_mipidphy2_bitclkdiv2_user)
+UMUX_EXTERN(umux_disp1_phyclk_disp1_hdmiphy_pixel_clko_user)
+UMUX_EXTERN(umux_fsys0_phyclk_usbdrd30_udrd30_phyclock_user)
+UMUX_EXTERN(umux_fsys0_phyclk_usbdrd30_udrd30_pipe_pclk_user)
+UMUX_EXTERN(umux_fsys0_phyclk_ufs_tx0_symbol_user)
+UMUX_EXTERN(umux_fsys0_phyclk_ufs_rx0_symbol_user)
+UMUX_EXTERN(umux_fsys0_phyclk_usbhost20_phyclock_user)
+UMUX_EXTERN(umux_fsys0_phyclk_usbhost20_freeclk_user)
+UMUX_EXTERN(umux_fsys0_phyclk_usbhost20_clk48mohci_user)
+UMUX_EXTERN(umux_fsys0_phyclk_usbhost20phy_ref_clk)
+UMUX_EXTERN(umux_fsys0_phyclk_ufs_rx_pwm_clk_user)
+UMUX_EXTERN(umux_fsys0_phyclk_ufs_tx_pwm_clk_user)
+UMUX_EXTERN(umux_fsys0_phyclk_ufs_refclk_out_soc_user)
+UMUX_EXTERN(umux_fsys1_phyclk_ufs_link_sdcard_tx0_symbol_user)
+UMUX_EXTERN(umux_fsys1_phyclk_ufs_link_sdcard_rx0_symbol_user)
+UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi0_tx0_user)
+UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi0_rx0_user)
+UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi1_tx0_user)
+UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi1_rx0_user)
+UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi0_dig_refclk_user)
+UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi1_dig_refclk_user)
+UMUX_EXTERN(umux_fsys1_phyclk_ufs_link_sdcard_rx_pwm_clk_user)
+UMUX_EXTERN(umux_fsys1_phyclk_ufs_link_sdcard_tx_pwm_clk_user)
+UMUX_EXTERN(umux_fsys1_phyclk_ufs_link_sdcard_refclk_out_soc_user)
+
+DFS_EXTERN(dvfs_big)
+DFS_EXTERN(dvfs_little)
+DFS_EXTERN(dvfs_g3d)
+DFS_EXTERN(dvfs_mif)
+DFS_EXTERN(dvfs_int)
+DFS_EXTERN(dvfs_cam)
+DFS_EXTERN(dvfs_disp)
+
+
+
+#endif

drivers/soc/samsung/pwrcal/S5E8890/S5E8890-vclk.h

@@ -0,0 +1,424 @@
+#ifndef __EXYNOS8890_VCLK_H__
+#define __EXYNOS8890_VCLK_H__
+
+enum {
+	invalid_vclk_id = 0x00000FFF,
+
+	gate_apollo_ppmu = 0x0A000000,
+	gate_apollo_bts,
+	gate_mngs_ppmu,
+	gate_mngs_bts,
+	gate_aud_common,
+	gate_aud_lpass,
+	gate_aud_mi2s,
+	gate_aud_pcm,
+	gate_aud_uart,
+	gate_aud_dma,
+	gate_aud_slimbus,
+	gate_aud_sysmmu,
+	gate_aud_ppmu,
+	gate_aud_bts,
+	gate_aud_sclk_mi2s,
+	gate_aud_sclk_pcm,
+	gate_aud_sclk_slimbus,
+	gate_bus0_display,
+	gate_bus0_cam,
+	gate_bus0_fsys1,
+	gate_bus1_mfc,
+	gate_bus1_mscl,
+	gate_bus1_fsys0,
+	gate_cam0_common,
+	gate_cam0_csis0,
+	gate_cam0_csis1,
+	gate_cam0_fimc_bns,
+	gate_cam0_fimc_3aa0,
+	gate_cam0_fimc_3aa1,
+	gate_cam0_hpm,
+	gate_cam0_sysmmu,
+	gate_cam0_ppmu,
+	gate_cam0_bts,
+	gate_cam0_phyclk_hs0_csis0_rx_byte,
+	gate_cam0_phyclk_hs1_csis0_rx_byte,
+	gate_cam0_phyclk_hs2_csis0_rx_byte,
+	gate_cam0_phyclk_hs3_csis0_rx_byte,
+	gate_cam0_phyclk_hs0_csis1_rx_byte,
+	gate_cam0_phyclk_hs1_csis1_rx_byte,
+	gate_cam1_common,
+	gate_cam1_isp_cpu_gic_common,
+	gate_cam1_isp_cpu,
+	gate_cam1_gic_is,
+	gate_cam1_csis2,
+	gate_cam1_csis3,
+	gate_cam1_fimc_vra,
+	gate_cam1_mc_scaler,
+	gate_cam1_i2c0_isp,
+	gate_cam1_i2c1_isp,
+	gate_cam1_i2c2_isp,
+	gate_cam1_i2c3_isp,
+	gate_cam1_wdt_isp,
+	gate_cam1_mcuctl_isp,
+	gate_cam1_uart_isp,
+	gate_cam1_sclk_uart_isp,
+	gate_cam1_spi0_isp,
+	gate_cam1_spi1_isp,
+	gate_cam1_pdma_isp,
+	gate_cam1_pwm_isp,
+	gate_cam1_sclk_pwm_isp,
+	gate_cam1_sysmmu,
+	gate_cam1_ppmu,
+	gate_cam1_bts,
+	gate_cam1_phyclk_hs0_csis2_rx_byte,
+	gate_cam1_phyclk_hs1_csis2_rx_byte,
+	gate_cam1_phyclk_hs2_csis2_rx_byte,
+	gate_cam1_phyclk_hs3_csis2_rx_byte,
+	gate_cam1_phyclk_hs0_csis3_rx_byte,
+	gate_ccore_i2c,
+	gate_disp0_common,
+	gate_disp0_decon0,
+	gate_disp0_dsim0,
+	gate_disp0_dsim1,
+	gate_disp0_dsim2,
+	gate_disp0_hdmi,
+	gate_disp0_dp,
+	gate_disp0_hpm_apbif_disp0,
+	gate_disp0_sysmmu,
+	gate_disp0_ppmu,
+	gate_disp0_bts,
+	gate_disp0_phyclk_hdmiphy_tmds_20b_clko,
+	gate_disp0_phyclk_hdmiphy_tmds_10b_clko,
+	gate_disp0_phyclk_hdmiphy_pixel_clko,
+	gate_disp0_phyclk_mipidphy0_rxclkesc0,
+	gate_disp0_phyclk_mipidphy0_bitclkdiv8,
+	gate_disp0_phyclk_mipidphy1_rxclkesc0,
+	gate_disp0_phyclk_mipidphy1_bitclkdiv8,
+	gate_disp0_phyclk_mipidphy2_rxclkesc0,
+	gate_disp0_phyclk_mipidphy2_bitclkdiv8,
+	gate_disp0_phyclk_dpphy_ch0_txd_clk,
+	gate_disp0_phyclk_dpphy_ch1_txd_clk,
+	gate_disp0_phyclk_dpphy_ch2_txd_clk,
+	gate_disp0_phyclk_dpphy_ch3_txd_clk,
+	gate_disp0_oscclk_dp_i_clk_24m,
+	gate_disp0_oscclk_i_dptx_phy_i_ref_clk_24m,
+	gate_disp0_oscclk_i_mipi_dphy_m1s0_m_xi,
+	gate_disp0_oscclk_i_mipi_dphy_m4s0_m_xi,
+	gate_disp0_oscclk_i_mipi_dphy_m4s4_m_xi,
+	gate_disp1_common,
+	gate_disp1_decon1,
+	gate_disp1_hpmdisp1,
+	gate_disp1_sysmmu,
+	gate_disp1_ppmu,
+	gate_disp1_bts,
+	gate_fsys0_common,
+	gate_fsys0_usbdrd_etrusb_common,
+	gate_fsys0_usbdrd30,
+	gate_fsys0_etr_usb,
+	gate_fsys0_usbhost20,
+	gate_fsys0_mmc0_ufs_common,
+	gate_fsys0_mmc0,
+	gate_fsys0_ufs_linkemedded,
+	gate_fsys0_pdma_common,
+	gate_fsys0_pdma0,
+	gate_fsys0_pdmas,
+	gate_fsys0_ppmu,
+	gate_fsys0_bts,
+	gate_fsys0_hpm,
+	gate_fsys0_phyclk_usbdrd30_udrd30_phyclock,
+	gate_fsys0_phyclk_usbdrd30_udrd30_pipe_pclk,
+	gate_fsys0_phyclk_ufs_tx0_symbol,
+	gate_fsys0_phyclk_ufs_rx0_symbol,
+	gate_fsys0_phyclk_usbhost20_phyclock,
+	gate_fsys0_phyclk_usbhost20_freeclk,
+	gate_fsys0_phyclk_usbhost20_clk48mohci,
+	gate_fsys0_phyclk_usbhost20phy_ref_clk,
+	gate_fsys0_phyclk_ufs_rx_pwm_clk,
+	gate_fsys0_phyclk_ufs_tx_pwm_clk,
+	gate_fsys0_phyclk_ufs_refclk_out_soc,
+	gate_fsys1_common,
+	gate_fsys1_mmc2_ufs_common,
+	gate_fsys1_mmc2,
+	gate_fsys1_ufs20_sdcard,
+	gate_fsys1_sromc,
+	gate_fsys1_pciewifi0,
+	gate_fsys1_pciewifi1,
+	gate_fsys1_ppmu,
+	gate_fsys1_bts,
+	gate_fsys1_hpm,
+	gate_fsys1_phyclk_ufs_link_sdcard_tx0_symbol,
+	gate_fsys1_phyclk_ufs_link_sdcard_rx0_symbol,
+	gate_fsys1_phyclk_pcie_wifi0_tx0,
+	gate_fsys1_phyclk_pcie_wifi0_rx0,
+	gate_fsys1_phyclk_pcie_wifi1_tx0,
+	gate_fsys1_phyclk_pcie_wifi1_rx0,
+	gate_fsys1_phyclk_pcie_wifi0_dig_refclk,
+	gate_fsys1_phyclk_pcie_wifi1_dig_refclk,
+	gate_fsys1_phyclk_ufs_link_sdcard_rx_pwm_clk,
+	gate_fsys1_phyclk_ufs_link_sdcard_tx_pwm_clk,
+	gate_fsys1_phyclk_ufs_link_sdcard_refclk_out_soc,
+	gate_g3d_common,
+	gate_g3d_g3d_common,
+	gate_g3d_g3d,
+	gate_g3d_iram_path_test,
+	gate_g3d_ppmu,
+	gate_g3d_bts,
+	gate_imem_common,
+	gate_imem_apm_sss_rtic_mc_common,
+	gate_imem_apm,
+	gate_imem_sss,
+	gate_imem_rtic,
+	gate_imem_mc,
+	gate_imem_intmem,
+	gate_imem_intmem_alv,
+	gate_imem_gic400,
+	gate_imem_ppmu,
+	gate_isp0_common,
+	gate_isp0_fimc_isp0,
+	gate_isp0_fimc_tpu,
+	gate_isp0_sysmmu,
+	gate_isp0_ppmu,
+	gate_isp0_bts,
+	gate_isp1_fimc_isp1,
+	gate_isp1_sysmmu,
+	gate_isp1_ppmu,
+	gate_isp1_bts,
+	gate_mfc_common,
+	gate_mfc_mfc,
+	gate_mfc_hpm,
+	gate_mfc_sysmmu,
+	gate_mfc_ppmu,
+	gate_mscl_common,
+	gate_mscl_mscl0_jpeg_common,
+	gate_mscl_mscl0,
+	gate_mscl_jpeg,
+	gate_mscl_mscl1_g2d_common,
+	gate_mscl_mscl1,
+	gate_mscl_g2d,
+	gate_mscl_sysmmu,
+	gate_mscl_ppmu,
+	gate_mscl_bts,
+	gate_peric0_hsi2c0,
+	gate_peric0_hsi2c1,
+	gate_peric0_hsi2c4,
+	gate_peric0_hsi2c5,
+	gate_peric0_hsi2c9,
+	gate_peric0_hsi2c10,
+	gate_peric0_hsi2c11,
+	gate_peric0_uart0,
+	gate_peric0_adcif,
+	gate_peric0_pwm,
+	gate_peric0_sclk_pwm,
+	gate_peric1_hsi2c_common,
+	gate_peric1_hsi2c2,
+	gate_peric1_hsi2c3,
+	gate_peric1_hsi2c6,
+	gate_peric1_hsi2c7,
+	gate_peric1_hsi2c8,
+	gate_peric1_hsi2c12,
+	gate_peric1_hsi2c13,
+	gate_peric1_hsi2c14,
+	gate_peric1_spi_i2s_pcm1_spdif_common,
+	gate_peric1_uart1,
+	gate_peric1_uart2,
+	gate_peric1_uart3,
+	gate_peric1_uart4,
+	gate_peric1_uart5,
+	gate_peric1_spi0,
+	gate_peric1_spi1,
+	gate_peric1_spi2,
+	gate_peric1_spi3,
+	gate_peric1_spi4,
+	gate_peric1_spi5,
+	gate_peric1_spi6,
+	gate_peric1_spi7,
+	gate_peric1_i2s1,
+	gate_peric1_pcm1,
+	gate_peric1_spdif,
+	gate_peric1_gpio_nfc,
+	gate_peric1_gpio_touch,
+	gate_peric1_gpio_fp,
+	gate_peric1_gpio_ese,
+	gate_peris_sfr_apbif_hdmi_cec,
+	gate_peris_hpm,
+	gate_peris_mct,
+	gate_peris_wdt_mngs,
+	gate_peris_wdt_apollo,
+	gate_peris_sysreg_peris,
+	gate_peris_monocnt_apbif,
+	gate_peris_rtc_apbif,
+	gate_peris_top_rtc,
+	gate_peris_otp_con_top,
+	gate_peris_chipid,
+	gate_peris_tmu,
+	vclk_group_grpgate_end,
+	num_of_grpgate = vclk_group_grpgate_end - 0x0A000000,
+
+	sclk_decon0_eclk0 = 0x0A010000,
+	sclk_decon0_vclk0,
+	sclk_decon0_vclk1,
+	sclk_hdmi_audio,
+	sclk_decon1_eclk0,
+	sclk_decon1_eclk1,
+	sclk_usbdrd30,
+	sclk_mmc0,
+	sclk_ufsunipro20,
+	sclk_phy24m,
+	sclk_ufsunipro_cfg,
+	sclk_mmc2,
+	sclk_ufsunipro20_sdcard,
+	sclk_pcie_phy,
+	sclk_ufsunipro_sdcard_cfg,
+	sclk_uart0,
+	sclk_spi0,
+	sclk_spi1,
+	sclk_spi2,
+	sclk_spi3,
+	sclk_spi4,
+	sclk_spi5,
+	sclk_spi6,
+	sclk_spi7,
+	sclk_uart1,
+	sclk_uart2,
+	sclk_uart3,
+	sclk_uart4,
+	sclk_uart5,
+	sclk_promise_int,
+	sclk_promise_disp,
+	sclk_ap2cp_mif_pll_out,
+	sclk_isp_spi0,
+	sclk_isp_spi1,
+	sclk_isp_uart,
+	sclk_isp_sensor0,
+	sclk_isp_sensor1,
+	sclk_isp_sensor2,
+	sclk_isp_sensor3,
+	sclk_decon0_eclk0_local,
+	sclk_decon0_vclk0_local,
+	sclk_decon0_vclk1_local,
+	sclk_decon1_eclk0_local,
+	sclk_decon1_eclk1_local,
+	vclk_group_m1d1g1_end,
+	num_of_m1d1g1 = vclk_group_m1d1g1_end - 0x0A010000,
+
+	p1_disp_pll = 0x0A020000,
+	p1_aud_pll,
+	p1_mfc_pll,
+	vclk_group_p1_end,
+	num_of_p1 = vclk_group_p1_end - 0x0A020000,
+
+	m1_dummy = 0x0A030000,
+	vclk_group_m1_end,
+	num_of_m1 = vclk_group_m1_end - 0x0A030000,
+
+	d1_sclk_i2s_local = 0x0A040000,
+	d1_sclk_pcm_local,
+	d1_sclk_slimbus,
+	d1_sclk_cp_i2s,
+	d1_sclk_asrc,
+	vclk_group_d1_end,
+	num_of_d1 = vclk_group_d1_end - 0x0A040000,
+
+	pxmxdx_top = 0x0A050000,
+	pxmxdx_mfc,
+	pxmxdx_mscl,
+	pxmxdx_imem,
+	pxmxdx_fsys0,
+	pxmxdx_fsys0_qch_usbdrd30,
+	pxmxdx_fsys1,
+	pxmxdx_disp0,
+	pxmxdx_disp1,
+	pxmxdx_aud,
+	pxmxdx_aud_cp,
+	pxmxdx_isp0_isp0,
+	pxmxdx_isp0_tpu,
+	pxmxdx_isp0_trex,
+	pxmxdx_isp0_pxl_asbs,
+	pxmxdx_isp1_isp1,
+	pxmxdx_cam0_csis0,
+	pxmxdx_cam0_csis1,
+	pxmxdx_cam0_csis2,
+	pxmxdx_cam0_csis3,
+	pxmxdx_cam0_3aa0,
+	pxmxdx_cam0_3aa1,
+	pxmxdx_cam0_trex,
+	pxmxdx_cam1_arm,
+	pxmxdx_cam1_vra,
+	pxmxdx_cam1_trex,
+	pxmxdx_cam1_bus,
+	pxmxdx_cam1_peri,
+	pxmxdx_cam1_csis2,
+	pxmxdx_cam1_csis3,
+	pxmxdx_cam1_scl,
+	pxmxdx_oscclk_nfc,
+	pxmxdx_oscclk_aud,
+	vclk_group_pxmxdx_end,
+	num_of_pxmxdx = vclk_group_pxmxdx_end - 0x0A050000,
+
+	umux_bus0_aclk_bus0_528 = 0x0A060000,
+	umux_bus0_aclk_bus0_200,
+	umux_bus1_aclk_bus1_528,
+	umux_cam0_phyclk_rxbyteclkhs0_csis0_user,
+	umux_cam0_phyclk_rxbyteclkhs1_csis0_user,
+	umux_cam0_phyclk_rxbyteclkhs2_csis0_user,
+	umux_cam0_phyclk_rxbyteclkhs3_csis0_user,
+	umux_cam0_phyclk_rxbyteclkhs0_csis1_user,
+	umux_cam0_phyclk_rxbyteclkhs1_csis1_user,
+	umux_cam1_phyclk_rxbyteclkhs0_csis2_user,
+	umux_cam1_phyclk_rxbyteclkhs1_csis2_user,
+	umux_cam1_phyclk_rxbyteclkhs2_csis2_user,
+	umux_cam1_phyclk_rxbyteclkhs3_csis2_user,
+	umux_cam1_phyclk_rxbyteclkhs0_csis3_user,
+	umux_disp0_phyclk_hdmiphy_pixel_clko_user,
+	umux_disp0_phyclk_hdmiphy_tmds_clko_user,
+	umux_disp0_phyclk_mipidphy0_rxclkesc0_user,
+	umux_disp0_phyclk_mipidphy0_bitclkdiv2_user,
+	umux_disp0_phyclk_mipidphy0_bitclkdiv8_user,
+	umux_disp0_phyclk_mipidphy1_rxclkesc0_user,
+	umux_disp0_phyclk_mipidphy1_bitclkdiv2_user,
+	umux_disp0_phyclk_mipidphy1_bitclkdiv8_user,
+	umux_disp0_phyclk_mipidphy2_rxclkesc0_user,
+	umux_disp0_phyclk_mipidphy2_bitclkdiv2_user,
+	umux_disp0_phyclk_mipidphy2_bitclkdiv8_user,
+	umux_disp0_phyclk_dpphy_ch0_txd_clk_user,
+	umux_disp0_phyclk_dpphy_ch1_txd_clk_user,
+	umux_disp0_phyclk_dpphy_ch2_txd_clk_user,
+	umux_disp0_phyclk_dpphy_ch3_txd_clk_user,
+	umux_disp1_phyclk_mipidphy0_bitclkdiv2_user,
+	umux_disp1_phyclk_mipidphy1_bitclkdiv2_user,
+	umux_disp1_phyclk_mipidphy2_bitclkdiv2_user,
+	umux_disp1_phyclk_disp1_hdmiphy_pixel_clko_user,
+	umux_fsys0_phyclk_usbdrd30_udrd30_phyclock_user,
+	umux_fsys0_phyclk_usbdrd30_udrd30_pipe_pclk_user,
+	umux_fsys0_phyclk_ufs_tx0_symbol_user,
+	umux_fsys0_phyclk_ufs_rx0_symbol_user,
+	umux_fsys0_phyclk_usbhost20_phyclock_user,
+	umux_fsys0_phyclk_usbhost20_freeclk_user,
+	umux_fsys0_phyclk_usbhost20_clk48mohci_user,
+	umux_fsys0_phyclk_usbhost20phy_ref_clk,
+	umux_fsys0_phyclk_ufs_rx_pwm_clk_user,
+	umux_fsys0_phyclk_ufs_tx_pwm_clk_user,
+	umux_fsys0_phyclk_ufs_refclk_out_soc_user,
+	umux_fsys1_phyclk_ufs_link_sdcard_tx0_symbol_user,
+	umux_fsys1_phyclk_ufs_link_sdcard_rx0_symbol_user,
+	umux_fsys1_phyclk_pcie_wifi0_tx0_user,
+	umux_fsys1_phyclk_pcie_wifi0_rx0_user,
+	umux_fsys1_phyclk_pcie_wifi1_tx0_user,
+	umux_fsys1_phyclk_pcie_wifi1_rx0_user,
+	umux_fsys1_phyclk_pcie_wifi0_dig_refclk_user,
+	umux_fsys1_phyclk_pcie_wifi1_dig_refclk_user,
+	umux_fsys1_phyclk_ufs_link_sdcard_rx_pwm_clk_user,
+	umux_fsys1_phyclk_ufs_link_sdcard_tx_pwm_clk_user,
+	umux_fsys1_phyclk_ufs_link_sdcard_refclk_out_soc_user,
+	vclk_group_umux_end,
+	num_of_umux = vclk_group_umux_end - 0x0A060000,
+
+	dvfs_big = 0x0A070000,
+	dvfs_little,
+	dvfs_g3d,
+	dvfs_mif,
+	dvfs_int,
+	dvfs_cam,
+	dvfs_disp,
+	vclk_group_dfs_end,
+	num_of_dfs = vclk_group_dfs_end - 0x0A070000,
+};
+
+#endif

drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-asv.c

@@ -0,0 +1,796 @@
+#include "../pwrcal-env.h"
+#include "../pwrcal-rae.h"
+#include "../pwrcal-asv.h"
+#include "S5E8890-cmusfr.h"
+#include "S5E8890-cmu.h"
+#include "S5E8890-vclk.h"
+#include "S5E8890-vclk-internal.h"
+
+#include <soc/samsung/ect_parser.h>
+
+#ifdef PWRCAL_TARGET_LINUX
+#include <linux/io.h>
+#include <asm/map.h>
+#endif
+#ifdef PWRCAL_TARGET_FW
+#define S5P_VA_APM_SRAM			((void *)0x11200000)
+#endif
+
+#define EXYNOS_MAILBOX_RCC_MIN_MAX(x)	(S5P_VA_APM_SRAM + (0x3700) + (x * 0x4))
+#define EXYNOS_MAILBOX_ATLAS_RCC(x)	(S5P_VA_APM_SRAM + (0x3730) + (x * 0x4))
+#define EXYNOS_MAILBOX_APOLLO_RCC(x)	(S5P_VA_APM_SRAM + (0x3798) + (x * 0x4))
+#define EXYNOS_MAILBOX_G3D_RCC(x)	(S5P_VA_APM_SRAM + (0x37EC) + (x * 0x4))
+#define EXYNOS_MAILBOX_MIF_RCC(x)	(S5P_VA_APM_SRAM + (0x381C) + (x * 0x4))
+
+
+enum dvfs_id {
+	cal_asv_dvfs_big,
+	cal_asv_dvfs_little,
+	cal_asv_dvfs_g3d,
+	cal_asv_dvfs_mif,
+	cal_asv_dvfs_int,
+	cal_asv_dvfs_cam,
+	cal_asv_dvfs_disp,
+	num_of_dvfs,
+};
+
+#define MAX_ASV_GROUP	16
+#define NUM_OF_ASVTABLE	1
+#define PWRCAL_ASV_LIST(table)	{table, sizeof(table) / sizeof(table[0])}
+
+struct asv_table_entry {
+	unsigned int index;
+	unsigned int *voltage;
+};
+
+struct asv_table_list {
+	struct asv_table_entry *table;
+	unsigned int table_size;
+	unsigned int voltage_count;
+};
+
+#define FORCE_ASV_MAGIC		0x57E90000
+static unsigned int force_asv_group[num_of_dvfs];
+
+#define APM_OTP_ADDRESS		0x101E9018
+#define APM_TABLE_BASE		0x11203700
+#define APM_FUSE_TABLE_BASE	APM_TABLE_BASE
+#define APM_RCC_TABLE_BASE	(APM_TABLE_BASE + 0x0030)
+static void *apm_sram_base;
+
+struct asv_tbl_info {
+	unsigned mngs_asv_group:4;
+	int mngs_modified_group:4;
+	unsigned mngs_ssa10:2;
+	unsigned mngs_ssa11:2;
+	unsigned mngs_ssa0:4;
+	unsigned apollo_asv_group:4;
+	int apollo_modified_group:4;
+	unsigned apollo_ssa10:2;
+	unsigned apollo_ssa11:2;
+	unsigned apollo_ssa0:4;
+
+	unsigned g3d_asv_group:4;
+	int g3d_modified_group:4;
+	unsigned g3d_ssa10:2;
+	unsigned g3d_ssa11:2;
+	unsigned g3d_ssa0:4;
+	unsigned mif_asv_group:4;
+	int mif_modified_group:4;
+	unsigned mif_ssa10:2;
+	unsigned mif_ssa11:2;
+	unsigned mif_ssa0:4;
+
+	unsigned int_asv_group:4;
+	int int_modified_group:4;
+	unsigned int_ssa10:2;
+	unsigned int_ssa11:2;
+	unsigned int_ssa0:4;
+	unsigned disp_asv_group:4;
+	int disp_modified_group:4;
+	unsigned disp_ssa10:2;
+	unsigned disp_ssa11:2;
+	unsigned disp_ssa0:4;
+
+	unsigned asv_table_ver:7;
+	unsigned fused_grp:1;
+	unsigned reserved_0:12;
+	unsigned g3d_mcs0:4;
+	unsigned g3d_mcs1:4;
+};
+#define ASV_INFO_ADDR_BASE	(0x101E9000)
+#define ASV_INFO_ADDR_CNT	(sizeof(struct asv_tbl_info) / 4)
+
+static struct asv_tbl_info asv_tbl_info;
+
+static struct asv_table_list *pwrcal_big_asv_table;
+static struct asv_table_list *pwrcal_little_asv_table;
+static struct asv_table_list *pwrcal_g3d_asv_table;
+static struct asv_table_list *pwrcal_mif_asv_table;
+static struct asv_table_list *pwrcal_int_asv_table;
+static struct asv_table_list *pwrcal_cam_asv_table;
+static struct asv_table_list *pwrcal_disp_asv_table;
+
+static struct asv_table_list *pwrcal_big_rcc_table;
+static struct asv_table_list *pwrcal_little_rcc_table;
+static struct asv_table_list *pwrcal_g3d_rcc_table;
+static struct asv_table_list *pwrcal_mif_rcc_table;
+
+static struct pwrcal_vclk_dfs *asv_dvfs_big;
+static struct pwrcal_vclk_dfs *asv_dvfs_little;
+static struct pwrcal_vclk_dfs *asv_dvfs_g3d;
+static struct pwrcal_vclk_dfs *asv_dvfs_mif;
+static struct pwrcal_vclk_dfs *asv_dvfs_int;
+static struct pwrcal_vclk_dfs *asv_dvfs_cam;
+static struct pwrcal_vclk_dfs *asv_dvfs_disp;
+
+
+static void asv_set_grp(unsigned int id, unsigned int asvgrp)
+{
+	force_asv_group[id & 0x0000FFFF] = FORCE_ASV_MAGIC | asvgrp;
+}
+
+static void asv_set_tablever(unsigned int version)
+{
+	asv_tbl_info.asv_table_ver = version;
+
+	return;
+}
+
+static struct freq_limit {
+	unsigned int big_max;
+	unsigned int little_max;
+	unsigned int g3d_max;
+	unsigned int mif_max;
+	unsigned int int_max;
+	unsigned int cam_max;
+	unsigned int disp_max;
+} freq_limit_policy[] = {
+	[0] = {
+		.big_max = 1872000,
+		.little_max = 1378000,
+		.g3d_max = 600000,
+		.mif_max = 1539000,
+	},
+	[1] = {
+		.big_max = 1872000,
+		.little_max = 1378000,
+		.g3d_max = 600000,
+		.mif_max = 1539000,
+	},
+};
+static void asv_set_freq_limit(void)
+{
+	if (!asv_tbl_info.fused_grp) {
+		asv_dvfs_big->table->max_freq = 728000;
+		asv_dvfs_little->table->max_freq = 1274000;
+		asv_dvfs_g3d->table->max_freq = 260000;
+		asv_dvfs_mif->table->max_freq = 1144000;
+	} else {
+		if (freq_limit_policy[asv_tbl_info.asv_table_ver].big_max)
+			asv_dvfs_big->table->max_freq = freq_limit_policy[asv_tbl_info.asv_table_ver].big_max;
+		if (freq_limit_policy[asv_tbl_info.asv_table_ver].little_max)
+			asv_dvfs_little->table->max_freq = freq_limit_policy[asv_tbl_info.asv_table_ver].little_max;
+		if (freq_limit_policy[asv_tbl_info.asv_table_ver].g3d_max)
+			asv_dvfs_g3d->table->max_freq = freq_limit_policy[asv_tbl_info.asv_table_ver].g3d_max;
+		if (freq_limit_policy[asv_tbl_info.asv_table_ver].mif_max)
+			asv_dvfs_mif->table->max_freq = freq_limit_policy[asv_tbl_info.asv_table_ver].mif_max;
+		if (freq_limit_policy[asv_tbl_info.asv_table_ver].int_max)
+			asv_dvfs_int->table->max_freq = freq_limit_policy[asv_tbl_info.asv_table_ver].int_max;
+		if (freq_limit_policy[asv_tbl_info.asv_table_ver].cam_max)
+			asv_dvfs_cam->table->max_freq = freq_limit_policy[asv_tbl_info.asv_table_ver].cam_max;
+		if (freq_limit_policy[asv_tbl_info.asv_table_ver].disp_max)
+			asv_dvfs_disp->table->max_freq = freq_limit_policy[asv_tbl_info.asv_table_ver].disp_max;
+	}
+	return;
+}
+
+static void asv_get_asvinfo(void)
+{
+	int i;
+	unsigned int *pasv_table;
+	unsigned long tmp;
+
+	pasv_table = (unsigned int *)&asv_tbl_info;
+	for (i = 0; i < ASV_INFO_ADDR_CNT; i++) {
+#ifdef PWRCAL_TARGET_LINUX
+		exynos_smc_readsfr((unsigned long)(ASV_INFO_ADDR_BASE + 0x4 * i), &tmp);
+#else
+#if (CONFIG_STARTUP_EL_MODE == STARTUP_EL3)
+		tmp = *((volatile unsigned int *)(unsigned long)(ASV_INFO_ADDR_BASE + 0x4 * i));
+#else
+		smc_readsfr((unsigned long)(ASV_INFO_ADDR_BASE + 0x4 * i), &tmp);
+#endif
+#endif
+		*(pasv_table + i) = (unsigned int)tmp;
+	}
+
+	if (!asv_tbl_info.fused_grp) {
+		asv_tbl_info.mngs_asv_group = 0;
+		asv_tbl_info.mngs_modified_group = 0;
+		asv_tbl_info.mngs_ssa10 = 0;
+		asv_tbl_info.mngs_ssa11 = 0;
+		asv_tbl_info.mngs_ssa0 = 0;
+		asv_tbl_info.apollo_asv_group = 0;
+		asv_tbl_info.apollo_modified_group = 0;
+		asv_tbl_info.apollo_ssa10 = 0;
+		asv_tbl_info.apollo_ssa11 = 0;
+		asv_tbl_info.apollo_ssa0 = 0;
+
+		asv_tbl_info.g3d_asv_group = 0;
+		asv_tbl_info.g3d_modified_group = 0;
+		asv_tbl_info.g3d_ssa10 = 0;
+		asv_tbl_info.g3d_ssa11 = 0;
+		asv_tbl_info.g3d_ssa0 = 0;
+		asv_tbl_info.mif_asv_group = 0;
+		asv_tbl_info.mif_modified_group = 0;
+		asv_tbl_info.mif_ssa10 = 0;
+		asv_tbl_info.mif_ssa11 = 0;
+		asv_tbl_info.mif_ssa0 = 0;
+
+		asv_tbl_info.int_asv_group = 0;
+		asv_tbl_info.int_modified_group = 0;
+		asv_tbl_info.int_ssa10 = 0;
+		asv_tbl_info.int_ssa11 = 0;
+		asv_tbl_info.int_ssa0 = 0;
+		asv_tbl_info.disp_asv_group = 0;
+		asv_tbl_info.disp_modified_group = 0;
+		asv_tbl_info.disp_ssa10 = 0;
+		asv_tbl_info.disp_ssa11 = 0;
+		asv_tbl_info.disp_ssa0 = 0;
+
+		asv_tbl_info.asv_table_ver = 0;
+		asv_tbl_info.fused_grp = 0;
+		asv_tbl_info.reserved_0 = 0;
+		asv_tbl_info.g3d_mcs0 = 0;
+		asv_tbl_info.g3d_mcs1 = 0;
+	}
+
+	if (asv_tbl_info.g3d_mcs0 == 0)
+		asv_tbl_info.g3d_mcs0 = 0x5;
+	if (asv_tbl_info.g3d_mcs1 == 0)
+		asv_tbl_info.g3d_mcs1 = 0xE;
+
+	asv_set_freq_limit();
+}
+
+static int get_asv_group(enum dvfs_id domain, unsigned int lv)
+{
+	int asv = 0;
+	int mod = 0;
+
+	switch (domain) {
+	case cal_asv_dvfs_big:
+		asv = asv_tbl_info.mngs_asv_group;
+		mod = asv_tbl_info.mngs_modified_group;
+		break;
+	case cal_asv_dvfs_little:
+		asv = asv_tbl_info.apollo_asv_group;
+		mod = asv_tbl_info.apollo_modified_group;
+		break;
+	case cal_asv_dvfs_g3d:
+		asv = asv_tbl_info.g3d_asv_group;
+		mod = asv_tbl_info.g3d_modified_group;
+		break;
+	case cal_asv_dvfs_mif:
+		asv = asv_tbl_info.mif_asv_group;
+		mod = asv_tbl_info.mif_modified_group;
+		break;
+	case cal_asv_dvfs_int:
+		asv = asv_tbl_info.int_asv_group;
+		mod = asv_tbl_info.int_modified_group;
+		break;
+	case cal_asv_dvfs_cam:
+		asv = asv_tbl_info.disp_asv_group;
+		mod = asv_tbl_info.disp_modified_group;
+		break;
+	case cal_asv_dvfs_disp:
+		asv = asv_tbl_info.disp_asv_group;
+		mod = asv_tbl_info.disp_modified_group;
+		break;
+	default:
+		BUG();	/* Never reach */
+		break;
+	}
+
+	if ((force_asv_group[domain & 0x0000FFFF] & 0xFFFF0000) != FORCE_ASV_MAGIC) {
+		if (mod)
+			asv += mod;
+	} else {
+		asv = force_asv_group[domain & 0x0000FFFF] & 0x0000FFFF;
+	}
+
+	if (asv < 0 || asv >= MAX_ASV_GROUP)
+		BUG();	/* Never reach */
+
+	return asv;
+}
+
+static unsigned int get_asv_voltage(enum dvfs_id domain, unsigned int lv)
+{
+	int asv;
+	unsigned int ssa10, ssa11;
+	unsigned int ssa0;
+	unsigned int subgrp_index;
+	const unsigned int *table;
+	unsigned int volt;
+
+	switch (domain) {
+	case cal_asv_dvfs_big:
+		asv = get_asv_group(cal_asv_dvfs_big, lv);
+		ssa10 = asv_tbl_info.mngs_ssa10;
+		ssa11 = asv_tbl_info.mngs_ssa11;
+		ssa0 = asv_tbl_info.mngs_ssa0;
+		subgrp_index = 16;
+		table = pwrcal_big_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
+		break;
+	case cal_asv_dvfs_little:
+		asv = get_asv_group(cal_asv_dvfs_little, lv);
+		ssa10 = asv_tbl_info.apollo_ssa10;
+		ssa11 = asv_tbl_info.apollo_ssa11;
+		ssa0 = asv_tbl_info.apollo_ssa0;
+		subgrp_index = 10;
+		table = pwrcal_little_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
+		break;
+	case cal_asv_dvfs_g3d:
+		asv = get_asv_group(cal_asv_dvfs_g3d, lv);
+		ssa10 = asv_tbl_info.g3d_ssa10;
+		ssa11 = asv_tbl_info.g3d_ssa11;
+		ssa0 = asv_tbl_info.g3d_ssa0;
+		subgrp_index = 7;
+		table = pwrcal_g3d_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
+		break;
+	case cal_asv_dvfs_mif:
+		asv = get_asv_group(cal_asv_dvfs_mif, lv);
+		ssa10 = asv_tbl_info.mif_ssa10;
+		ssa11 = asv_tbl_info.mif_ssa11;
+		ssa0 = asv_tbl_info.mif_ssa0;
+		subgrp_index = 8;
+		table = pwrcal_mif_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
+		break;
+	case cal_asv_dvfs_int:
+		asv = get_asv_group(cal_asv_dvfs_int, lv);
+		ssa10 = asv_tbl_info.int_ssa10;
+		ssa11 = asv_tbl_info.int_ssa11;
+		ssa0 = asv_tbl_info.int_ssa0;
+		subgrp_index = 15;
+		table = pwrcal_int_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
+		break;
+	case cal_asv_dvfs_cam:
+		asv = get_asv_group(cal_asv_dvfs_cam, lv);
+		ssa10 = asv_tbl_info.disp_ssa10;
+		ssa11 = asv_tbl_info.disp_ssa11;
+		ssa0 = asv_tbl_info.disp_ssa0;
+		subgrp_index = 5;
+		table = pwrcal_cam_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
+		break;
+	case cal_asv_dvfs_disp:
+		asv = get_asv_group(cal_asv_dvfs_disp, lv);
+		ssa10 = asv_tbl_info.disp_ssa10;
+		ssa11 = asv_tbl_info.disp_ssa11;
+		ssa0 = asv_tbl_info.disp_ssa0;
+		subgrp_index = 2;
+		table = pwrcal_disp_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
+		break;
+	default:
+		BUG();	/* Never reach */
+		break;
+	}
+
+	volt = table[asv];
+	if (lv < subgrp_index) {
+		volt += 12500 * ssa10;
+		if (ssa10 == 3)
+			volt += 12500;
+	} else {
+		volt += 12500 * ssa11;
+		if (ssa11 == 3)
+			volt += 12500;
+	}
+
+	if (volt < 575000 + ssa0 * 25000)
+		volt = 575000 + ssa0 * 25000;
+
+	return volt;
+}
+
+static int dvfsbig_get_asv_table(unsigned int *table)
+{
+	int lv, max_lv;
+
+	max_lv = asv_dvfs_big->table->num_of_lv;
+
+	for (lv = 0; lv < max_lv; lv++)
+		table[lv] = get_asv_voltage(cal_asv_dvfs_big, lv);
+
+	return max_lv;
+}
+
+static int dvfslittle_get_asv_table(unsigned int *table)
+{
+	int lv, max_lv;
+
+	max_lv = asv_dvfs_little->table->num_of_lv;
+
+	for (lv = 0; lv < max_lv; lv++)
+		table[lv] = get_asv_voltage(cal_asv_dvfs_little, lv);
+
+	return max_lv;
+}
+
+static int dvfsg3d_get_asv_table(unsigned int *table)
+{
+	int lv, max_lv;
+
+	max_lv = asv_dvfs_g3d->table->num_of_lv;
+
+	for (lv = 0; lv < max_lv; lv++)
+		table[lv] = get_asv_voltage(cal_asv_dvfs_g3d, lv);
+
+	return max_lv;
+}
+
+static int dvfsmif_get_asv_table(unsigned int *table)
+{
+	int lv, max_lv;
+
+	max_lv = asv_dvfs_mif->table->num_of_lv;
+
+	for (lv = 0; lv < max_lv; lv++)
+		table[lv] = get_asv_voltage(cal_asv_dvfs_mif, lv);
+
+	return max_lv;
+}
+
+static int dvfsint_get_asv_table(unsigned int *table)
+{
+	int lv, max_lv;
+
+	max_lv = asv_dvfs_int->table->num_of_lv;
+
+	for (lv = 0; lv < max_lv; lv++)
+		table[lv] = get_asv_voltage(cal_asv_dvfs_int, lv);
+
+	return max_lv;
+}
+
+static int dvfscam_get_asv_table(unsigned int *table)
+{
+	int lv, max_lv;
+
+	max_lv = asv_dvfs_cam->table->num_of_lv;
+
+	for (lv = 0; lv < max_lv; lv++)
+		table[lv] = get_asv_voltage(cal_asv_dvfs_cam, lv);
+
+	return max_lv;
+}
+
+static int dvfsdisp_get_asv_table(unsigned int *table)
+{
+	int lv, max_lv;
+
+	max_lv = asv_dvfs_disp->table->num_of_lv;
+
+	for (lv = 0; lv < max_lv; lv++)
+		table[lv] = get_asv_voltage(cal_asv_dvfs_disp, lv);
+
+	return max_lv;
+}
+
+static int dfsg3d_set_ema(unsigned int volt)
+{
+	if (volt > 750000)
+		pwrcal_writel(EMA_RF2_UHD_CON, asv_tbl_info.g3d_mcs0);
+	else
+		pwrcal_writel(EMA_RF2_UHD_CON, asv_tbl_info.g3d_mcs1);
+
+	return 0;
+}
+
+static int asv_rcc_set_table(void)
+{
+	int i;
+	int lv, max_lv, asv;
+	unsigned int *p;
+	unsigned long tmp;
+
+	if (!apm_sram_base) {
+#ifdef PWRCAL_TARGET_LINUX
+		apm_sram_base = (void *)ioremap(APM_TABLE_BASE, SZ_4K);
+#else
+		apm_sram_base = (void *)APM_TABLE_BASE;
+#endif
+	}
+
+	p = (unsigned int *)(apm_sram_base);
+	for (i = 0; i < 8; i++) {
+#ifdef PWRCAL_TARGET_LINUX
+		exynos_smc_readsfr((unsigned long)(APM_OTP_ADDRESS + 0x4 * i), &tmp);
+#else
+#if (CONFIG_STARTUP_EL_MODE == STARTUP_EL3)
+		tmp = *((volatile unsigned int *)(unsigned long)(APM_OTP_ADDRESS + 0x4 * i));
+#else
+		smc_readsfr((unsigned long)(APM_OTP_ADDRESS + 0x4 * i), &tmp);
+#endif
+#endif
+		*(p + i) = (unsigned int)tmp;
+	}
+
+	p = (unsigned int *)(apm_sram_base + 0x0030);
+	max_lv = asv_dvfs_big->table->num_of_lv;
+	if (max_lv > 25)
+		max_lv = 25;
+	for (lv = 0; lv < max_lv; lv++) {
+		asv = get_asv_group(cal_asv_dvfs_big, lv);
+		*(p + lv) = pwrcal_big_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv];
+	}
+
+	p = (unsigned int *)(apm_sram_base + 0x0098);
+	max_lv = asv_dvfs_little->table->num_of_lv;
+	if (max_lv > 20)
+		max_lv = 20;
+	for (lv = 0; lv < max_lv; lv++) {
+		asv = get_asv_group(cal_asv_dvfs_little, lv);
+		*(p + lv) = pwrcal_little_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv];
+	}
+
+	p = (unsigned int *)(apm_sram_base + 0x00EC);
+	max_lv = asv_dvfs_g3d->table->num_of_lv;
+	if (max_lv > 11)
+		max_lv = 11;
+	for (lv = 0; lv < max_lv; lv++) {
+		asv = get_asv_group(cal_asv_dvfs_g3d, lv);
+		*(p + lv) = pwrcal_g3d_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv];
+	}
+
+	p = (unsigned int *)(apm_sram_base + 0x011C);
+	max_lv = asv_dvfs_mif->table->num_of_lv;
+	if (max_lv > 16)
+		max_lv = 16;
+	for (lv = 0; lv < max_lv; lv++) {
+		asv = get_asv_group(cal_asv_dvfs_mif, lv);
+		*(p + lv) = pwrcal_mif_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv];
+	}
+
+	return 0;
+}
+
+static void asv_voltage_init_table(struct asv_table_list **asv_table, struct pwrcal_vclk_dfs *dfs)
+{
+	int i, j, k;
+	void *asv_block, *margin_block;
+	struct ect_voltage_domain *domain;
+	struct ect_voltage_table *table;
+	struct asv_table_entry *asv_entry;
+	struct ect_margin_domain *margin_domain = NULL;
+
+	asv_block = ect_get_block("ASV");
+	if (asv_block == NULL)
+		return;
+
+	margin_block = ect_get_block("MARGIN");
+
+	domain = ect_asv_get_domain(asv_block, dfs->vclk.name);
+	if (domain == NULL)
+		return;
+
+	if (asv_tbl_info.asv_table_ver >= domain->num_of_table)
+		BUG();
+
+	if (margin_block)
+		margin_domain = ect_margin_get_domain(margin_block, dfs->vclk.name);
+
+	*asv_table = kzalloc(sizeof(struct asv_table_list) * domain->num_of_table, GFP_KERNEL);
+	if (*asv_table == NULL)
+		return;
+
+	for (i = 0; i < domain->num_of_table; ++i) {
+		table = &domain->table_list[i];
+
+		(*asv_table)[i].table_size = domain->num_of_table;
+		(*asv_table)[i].table = kzalloc(sizeof(struct asv_table_entry) * domain->num_of_level, GFP_KERNEL);
+		if ((*asv_table)[i].table == NULL)
+			return;
+
+		for (j = 0; j < domain->num_of_level; ++j) {
+			asv_entry = &(*asv_table)[i].table[j];
+
+			asv_entry->index = domain->level_list[j];
+			asv_entry->voltage = kzalloc(sizeof(unsigned int) * domain->num_of_group, GFP_KERNEL);
+
+			for (k = 0; k < domain->num_of_group; ++k) {
+				asv_entry->voltage[k] = table->voltages[j * domain->num_of_group + k];
+				if (margin_domain != NULL)
+					asv_entry->voltage[k] += margin_domain->offset[j * margin_domain->num_of_group + k];
+			}
+		}
+	}
+}
+
+static void asv_rcc_init_table(struct asv_table_list **rcc_table, struct pwrcal_vclk_dfs *dfs)
+
+{
+	int i, j, k;
+	void *rcc_block;
+	struct ect_rcc_domain *domain;
+	struct ect_rcc_table *table;
+	struct asv_table_entry *rcc_entry;
+
+	rcc_block = ect_get_block("RCC");
+	if (rcc_block == NULL)
+		return;
+
+	domain = ect_rcc_get_domain(rcc_block, dfs->vclk.name);
+	if (domain == NULL)
+		return;
+
+	*rcc_table = kzalloc(sizeof(struct asv_table_list) * domain->num_of_table, GFP_KERNEL);
+	if (*rcc_table == NULL)
+		return;
+
+	for (i = 0; i < domain->num_of_table; ++i) {
+		table = &domain->table_list[i];
+
+		(*rcc_table)[i].table_size = domain->num_of_table;
+		(*rcc_table)[i].table = kzalloc(sizeof(struct asv_table_entry) * domain->num_of_level, GFP_KERNEL);
+		if ((*rcc_table)[i].table == NULL)
+			return;
+
+		for (j = 0; j < domain->num_of_level; ++j) {
+			rcc_entry = &(*rcc_table)[i].table[j];
+
+			rcc_entry->index = domain->level_list[j];
+			rcc_entry->voltage = kzalloc(sizeof(unsigned int) * domain->num_of_group, GFP_KERNEL);
+
+			for (k = 0; k < domain->num_of_group; ++k)
+				rcc_entry->voltage[k] = table->rcc[j * domain->num_of_group + k];
+		}
+	}
+}
+
+static void asv_voltage_table_init(void)
+{
+	asv_voltage_init_table(&pwrcal_big_asv_table, asv_dvfs_big);
+	asv_voltage_init_table(&pwrcal_little_asv_table, asv_dvfs_little);
+	asv_voltage_init_table(&pwrcal_g3d_asv_table, asv_dvfs_g3d);
+	asv_voltage_init_table(&pwrcal_mif_asv_table, asv_dvfs_mif);
+	asv_voltage_init_table(&pwrcal_int_asv_table, asv_dvfs_int);
+	asv_voltage_init_table(&pwrcal_cam_asv_table, asv_dvfs_cam);
+	asv_voltage_init_table(&pwrcal_disp_asv_table, asv_dvfs_disp);
+}
+
+static void asv_rcc_table_init(void)
+{
+	asv_rcc_init_table(&pwrcal_big_rcc_table, asv_dvfs_big);
+	asv_rcc_init_table(&pwrcal_little_rcc_table, asv_dvfs_little);
+	asv_rcc_init_table(&pwrcal_g3d_rcc_table, asv_dvfs_g3d);
+	asv_rcc_init_table(&pwrcal_mif_rcc_table, asv_dvfs_mif);
+}
+
+static int asv_init(void)
+{
+	struct vclk *vclk;
+
+	vclk = cal_get_vclk(dvfs_big);
+	asv_dvfs_big = to_dfs(vclk);
+	asv_dvfs_big->dfsops->get_asv_table = dvfsbig_get_asv_table;
+/*	asv_dvfs_big->dfsops->set_ema = dvfsbig_set_ema;
+*/
+	vclk = cal_get_vclk(dvfs_little);
+	asv_dvfs_little = to_dfs(vclk);
+	asv_dvfs_little->dfsops->get_asv_table = dvfslittle_get_asv_table;
+/*	asv_dvfs_little->dfsops->set_ema = dvfslittle_set_ema;
+*/
+	vclk = cal_get_vclk(dvfs_g3d);
+	asv_dvfs_g3d = to_dfs(vclk);
+	asv_dvfs_g3d->dfsops->get_asv_table = dvfsg3d_get_asv_table;
+	asv_dvfs_g3d->dfsops->set_ema = dfsg3d_set_ema;
+
+	vclk = cal_get_vclk(dvfs_mif);
+	asv_dvfs_mif = to_dfs(vclk);
+	asv_dvfs_mif->dfsops->get_asv_table = dvfsmif_get_asv_table;
+
+	vclk = cal_get_vclk(dvfs_int);
+	asv_dvfs_int = to_dfs(vclk);
+	asv_dvfs_int->dfsops->get_asv_table = dvfsint_get_asv_table;
+/*	asv_dvfs_int->dfsops->set_ema = dvfsint_set_ema;
+*/
+	vclk = cal_get_vclk(dvfs_cam);
+	asv_dvfs_cam = to_dfs(vclk);
+	asv_dvfs_cam->dfsops->get_asv_table = dvfscam_get_asv_table;
+
+	vclk = cal_get_vclk(dvfs_disp);
+	asv_dvfs_disp = to_dfs(vclk);
+	asv_dvfs_disp->dfsops->get_asv_table = dvfsdisp_get_asv_table;
+
+	pwrcal_big_asv_table = NULL;
+	pwrcal_little_asv_table = NULL;
+	pwrcal_g3d_asv_table = NULL;
+	pwrcal_mif_asv_table = NULL;
+	pwrcal_int_asv_table = NULL;
+	pwrcal_cam_asv_table = NULL;
+	pwrcal_disp_asv_table = NULL;
+
+	pwrcal_big_rcc_table = NULL;
+	pwrcal_little_rcc_table = NULL;
+	pwrcal_g3d_rcc_table = NULL;
+	pwrcal_mif_rcc_table = NULL;
+
+	asv_get_asvinfo();
+	asv_voltage_table_init();
+	asv_rcc_table_init();
+
+	return 0;
+}
+
+static void asv_print_info(void)
+{
+	pr_info("asv_table_ver : %d\n", asv_tbl_info.asv_table_ver);
+	pr_info("fused_grp : %d\n", asv_tbl_info.fused_grp);
+
+	pr_info("mngs_asv_group : %d\n", asv_tbl_info.mngs_asv_group);
+	pr_info("mngs_modified_group : %d\n", asv_tbl_info.mngs_modified_group);
+	pr_info("apollo_asv_group : %d\n", asv_tbl_info.apollo_asv_group);
+	pr_info("apollo_modified_group : %d\n", asv_tbl_info.apollo_modified_group);
+
+	pr_info("g3d_asv_group : %d\n", asv_tbl_info.g3d_asv_group);
+	pr_info("g3d_modified_group : %d\n", asv_tbl_info.g3d_modified_group);
+	pr_info("mif_asv_group : %d\n", asv_tbl_info.mif_asv_group);
+	pr_info("mif_modified_group : %d\n", asv_tbl_info.mif_modified_group);
+
+	pr_info("int_asv_group : %d\n", asv_tbl_info.int_asv_group);
+	pr_info("int_modified_group : %d\n", asv_tbl_info.int_modified_group);
+	pr_info("disp_asv_group : %d\n", asv_tbl_info.disp_asv_group);
+	pr_info("disp_modified_group : %d\n", asv_tbl_info.disp_modified_group);
+
+	pr_info("g3d_mcs0 : %d\n", asv_tbl_info.g3d_mcs0);
+	pr_info("g3d_mcs1 : %d\n", asv_tbl_info.g3d_mcs1);
+}
+
+static void rcc_print_info(void)
+{
+	int lv, max_lv, asv;
+
+	pr_info("==== RCC Table ====\n");
+	max_lv = asv_dvfs_big->table->num_of_lv;
+	if (max_lv > 25)
+		max_lv = 25;
+	for (lv = 0; lv < max_lv; lv++) {
+		asv = get_asv_group(cal_asv_dvfs_big, lv);
+		pr_info("big rcc [%d] : %d\n", lv, pwrcal_big_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv]);
+	}
+
+	max_lv = asv_dvfs_little->table->num_of_lv;
+	if (max_lv > 20)
+		max_lv = 20;
+	for (lv = 0; lv < max_lv; lv++) {
+		asv = get_asv_group(cal_asv_dvfs_little, lv);
+		pr_info("little rcc [%d] : %d\n", lv, pwrcal_little_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv]);
+	}
+
+	max_lv = asv_dvfs_g3d->table->num_of_lv;
+	if (max_lv > 11)
+		max_lv = 11;
+	for (lv = 0; lv < max_lv; lv++) {
+		asv = get_asv_group(cal_asv_dvfs_g3d, lv);
+		pr_info("g3d rcc [%d] : %d\n", lv, pwrcal_g3d_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv]);
+	}
+
+	max_lv = asv_dvfs_mif->table->num_of_lv;
+	if (max_lv > 16)
+		max_lv = 16;
+	for (lv = 0; lv < max_lv; lv++) {
+		asv = get_asv_group(cal_asv_dvfs_mif, lv);
+		pr_info("mif rcc [%d] : %d\n", lv, pwrcal_mif_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv]);
+	}
+}
+
+struct cal_asv_ops cal_asv_ops = {
+	.print_asv_info = asv_print_info,
+	.print_rcc_info = rcc_print_info,
+	.set_grp = asv_set_grp,
+	.set_tablever = asv_set_tablever,
+	.set_rcc_table = asv_rcc_set_table,
+	.asv_init = asv_init,
+};

drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-drampara.c

@@ -0,0 +1,513 @@
+#include "../pwrcal-env.h"
+#include "../pwrcal-rae.h"
+#include "S5E8890-sfrbase.h"
+#include "S5E8890-vclk-internal.h"
+
+#include <soc/samsung/ect_parser.h>
+
+#ifndef MHZ
+#define MHZ		((unsigned long long)1000000)
+#endif
+
+#define __SMC_ALL				(DMC_MISC_CCORE_BASE + 0x8000)
+#define __PHY_ALL				(DMC_MISC_CCORE_BASE + 0x4000)
+#define __DMC_MISC_ALL			(DMC_MISC_CCORE_BASE + 0x0000)
+
+#define ModeRegAddr				((void *)(__SMC_ALL + 0x0000))
+#define MprMrCtl				((void *)(__SMC_ALL + 0x0004))
+#define ModeRegWrData			((void *)(__SMC_ALL + 0x0008))
+
+#define DramTiming0_0			((void *)(__SMC_ALL + 0x0058))
+#define DramTiming1_0			((void *)(__SMC_ALL + 0x005C))
+#define DramTiming2_0			((void *)(__SMC_ALL + 0x0060))
+#define DramTiming3_0			((void *)(__SMC_ALL + 0x0064))
+#define DramTiming4_0			((void *)(__SMC_ALL + 0x0068))
+#define DramTiming5_0			((void *)(__SMC_ALL + 0x006C))
+#define DramTiming6_0			((void *)(__SMC_ALL + 0x0070))
+#define DramTiming7_0			((void *)(__SMC_ALL + 0x0074))
+#define DramTiming8_0			((void *)(__SMC_ALL + 0x0078))
+#define DramTiming9_0			((void *)(__SMC_ALL + 0x007C))
+#define DramDerateTiming0_0		((void *)(__SMC_ALL + 0x0088))
+#define DramDerateTiming1_0		((void *)(__SMC_ALL + 0x008C))
+#define Dimm0AutoRefTiming1_0	((void *)(__SMC_ALL + 0x009C))
+#define Dimm1AutoRefTiming1_0	((void *)(__SMC_ALL + 0x00A4))
+#define AutoRefTiming2_0		((void *)(__SMC_ALL + 0x00A8))
+#define PwrMgmtTiming0_0		((void *)(__SMC_ALL + 0x00B8))
+#define PwrMgmtTiming1_0		((void *)(__SMC_ALL + 0x00BC))
+#define PwrMgmtTiming2_0		((void *)(__SMC_ALL + 0x00C0))
+#define PwrMgmtTiming3_0		((void *)(__SMC_ALL + 0x00C4))
+#define TmrTrnInterval_0		((void *)(__SMC_ALL + 0x00C8))
+#define DvfsTrnCtl_0			((void *)(__SMC_ALL + 0x00CC))
+#define TrnTiming0_0			((void *)(__SMC_ALL + 0x00D0))
+#define TrnTiming1_0			((void *)(__SMC_ALL + 0x00D4))
+#define TrnTiming2_0			((void *)(__SMC_ALL + 0x00D8))
+#define DFIDelay1_0				((void *)(__SMC_ALL + 0x00E0))
+#define DFIDelay2_0				((void *)(__SMC_ALL + 0x00E4))
+
+#define DramTiming0_1			((void *)(__SMC_ALL + 0x0108))
+#define DramTiming1_1			((void *)(__SMC_ALL + 0x010C))
+#define DramTiming2_1			((void *)(__SMC_ALL + 0x0110))
+#define DramTiming3_1			((void *)(__SMC_ALL + 0x0114))
+#define DramTiming4_1			((void *)(__SMC_ALL + 0x0118))
+#define DramTiming5_1			((void *)(__SMC_ALL + 0x011C))
+#define DramTiming6_1			((void *)(__SMC_ALL + 0x0120))
+#define DramTiming7_1			((void *)(__SMC_ALL + 0x0124))
+#define DramTiming8_1			((void *)(__SMC_ALL + 0x0128))
+#define DramTiming9_1			((void *)(__SMC_ALL + 0x012C))
+#define DramDerateTiming0_1		((void *)(__SMC_ALL + 0x0138))
+#define DramDerateTiming1_1		((void *)(__SMC_ALL + 0x013C))
+#define Dimm0AutoRefTiming1_1	((void *)(__SMC_ALL + 0x014C))
+#define Dimm1AutoRefTiming1_1	((void *)(__SMC_ALL + 0x0154))
+#define AutoRefTiming2_1		((void *)(__SMC_ALL + 0x0168))
+#define PwrMgmtTiming0_1		((void *)(__SMC_ALL + 0x0168))
+#define PwrMgmtTiming1_1		((void *)(__SMC_ALL + 0x016C))
+#define PwrMgmtTiming2_1		((void *)(__SMC_ALL + 0x0170))
+#define PwrMgmtTiming3_1		((void *)(__SMC_ALL + 0x0174))
+#define TmrTrnInterval_1		((void *)(__SMC_ALL + 0x0178))
+#define DvfsTrnCtl_1			((void *)(__SMC_ALL + 0x017C))
+#define TrnTiming0_1			((void *)(__SMC_ALL + 0x0180))
+#define TrnTiming1_1			((void *)(__SMC_ALL + 0x0184))
+#define TrnTiming2_1			((void *)(__SMC_ALL + 0x0188))
+#define DFIDelay1_1				((void *)(__SMC_ALL + 0x0190))
+#define DFIDelay2_1				((void *)(__SMC_ALL + 0x0194))
+
+#define PHY_DVFS_CON_CH0		((void *)(LPDDR4_PHY0_BASE + 0x00B8))
+#define PHY_DVFS_CON			((void *)(__PHY_ALL + 0x00B8))
+#define PHY_DVFS0_CON0			((void *)(__PHY_ALL + 0x00BC))
+#define PHY_DVFS0_CON1			((void *)(__PHY_ALL + 0x00C4))
+#define PHY_DVFS0_CON2			((void *)(__PHY_ALL + 0x00CC))
+#define PHY_DVFS0_CON3			((void *)(__PHY_ALL + 0x00D4))
+#define PHY_DVFS0_CON4			((void *)(__PHY_ALL + 0x00DC))
+
+#define PHY_DVFS1_CON0			((void *)(__PHY_ALL + 0x00C0))
+#define PHY_DVFS1_CON1			((void *)(__PHY_ALL + 0x00C8))
+#define PHY_DVFS1_CON2			((void *)(__PHY_ALL + 0x00D0))
+#define PHY_DVFS1_CON3			((void *)(__PHY_ALL + 0x00D8))
+#define PHY_DVFS1_CON4			((void *)(__PHY_ALL + 0x00E0))
+
+#define DMC_MISC_CON0			((void *)(__DMC_MISC_ALL + 0x0014))
+#define DMC_MISC_CON1			((void *)(__DMC_MISC_ALL + 0x003C))
+#define MRS_DATA1				((void *)(__DMC_MISC_ALL + 0x0054))
+
+enum mif_timing_set_idx {
+	MIF_TIMING_SET_0,
+	MIF_TIMING_SET_1
+};
+
+enum smc_dram_mode_register {
+	DRAM_MR0,
+	DRAM_MR1,
+	DRAM_MR2,
+	DRAM_MR3,
+	DRAM_MR4,
+	DRAM_MR5,
+	DRAM_MR6,
+	DRAM_MR7,
+	DRAM_MR8,
+	DRAM_MR9,
+	DRAM_MR10,
+	DRAM_MR11,
+	DRAM_MR12,
+	DRAM_MR13,
+	DRAM_MR14,
+	DRAM_MR15,
+	DRAM_MR16,
+	DRAM_MR17,
+	DRAM_MR18,
+	DRAM_MR19,
+	DRAM_MR20,
+	DRAM_MR21,
+	DRAM_MR22,
+	DRAM_MR23,
+	DRAM_MR24,
+	DRAM_MR25,
+	DRAM_MR32 = 32,
+	DRAM_MR40 = 40,
+};
+
+enum timing_parameter_column {
+	DramTiming0,
+	DramTiming1,
+	DramTiming2,
+	DramTiming3,
+	DramTiming4,
+	DramTiming5,
+	DramTiming6,
+	DramTiming7,
+	DramTiming8,
+	DramTiming9,
+	DramDerateTiming0,
+	DramDerateTiming1,
+	Dimm0AutoRefTiming1,
+	Dimm1AutoRefTiming1,
+	AutoRefTiming2,
+	PwrMgmtTiming0,
+	PwrMgmtTiming1,
+	PwrMgmtTiming2,
+	PwrMgmtTiming3,
+	TmrTrnInterval,
+	DFIDelay1,
+	DFIDelay2,
+	DvfsTrnCtl,
+	TrnTiming0,
+	TrnTiming1,
+	TrnTiming2,
+	DVFSn_CON0,
+	DVFSn_CON1,
+	DVFSn_CON2,
+	DVFSn_CON3,
+	DVFSn_CON4,
+	DirectCmd_MR1,
+	DirectCmd_MR2,
+	DirectCmd_MR3,
+	DirectCmd_MR11,
+	DirectCmd_MR12,
+	DirectCmd_MR14,
+	DirectCmd_MR22,
+
+	num_of_g_smc_dfs_table_column = TrnTiming2 - DramTiming0 + 1,
+	num_of_g_phy_dfs_table_column = DVFSn_CON4 - DVFSn_CON0 + 1,
+	num_of_g_dram_dfs_table_column = DirectCmd_MR22 - DirectCmd_MR1 + 1,
+	num_of_dram_parameter = num_of_g_smc_dfs_table_column + num_of_g_phy_dfs_table_column + num_of_g_dram_dfs_table_column,
+};
+
+struct smc_dfs_table {
+	unsigned int DramTiming0;
+	unsigned int DramTiming1;
+	unsigned int DramTiming2;
+	unsigned int DramTiming3;
+	unsigned int DramTiming4;
+	unsigned int DramTiming5;
+	unsigned int DramTiming6;
+	unsigned int DramTiming7;
+	unsigned int DramTiming8;
+	unsigned int DramTiming9;
+	unsigned int DramDerateTiming0;
+	unsigned int DramDerateTiming1;
+	unsigned int Dimm0AutoRefTiming1;
+	unsigned int Dimm1AutoRefTiming1;
+	unsigned int AutoRefTiming2;
+	unsigned int PwrMgmtTiming0;
+	unsigned int PwrMgmtTiming1;
+	unsigned int PwrMgmtTiming2;
+	unsigned int PwrMgmtTiming3;
+	unsigned int TmrTrnInterval;
+	unsigned int DFIDelay1;
+	unsigned int DFIDelay2;
+	unsigned int DvfsTrnCtl;
+	unsigned int TrnTiming0;
+	unsigned int TrnTiming1;
+	unsigned int TrnTiming2;
+};
+
+struct phy_dfs_table {
+	unsigned int DVFSn_CON0;
+	unsigned int DVFSn_CON1;
+	unsigned int DVFSn_CON2;
+	unsigned int DVFSn_CON3;
+	unsigned int DVFSn_CON4;
+};
+
+struct dram_dfs_table {
+	unsigned int DirectCmd_MR1;
+	unsigned int DirectCmd_MR2;
+	unsigned int DirectCmd_MR3;
+	unsigned int DirectCmd_MR11;
+	unsigned int DirectCmd_MR12;
+	unsigned int DirectCmd_MR14;
+	unsigned int DirectCmd_MR22;
+};
+
+static struct smc_dfs_table *g_smc_dfs_table;
+static struct phy_dfs_table *g_phy_dfs_table;
+static struct dram_dfs_table *g_dram_dfs_table;
+static unsigned long long *mif_freq_to_level;
+static int num_mif_freq_to_level;
+
+static const struct smc_dfs_table g_smc_dfs_table_switch[] = {
+	/* DramTiming0__n,	DramTiming1__n,	DramTiming2__n,	DramTiming3__n,	DramTiming4__n,	DramTiming5__n,	DramTiming6__n,	DramTiming7__n,	DramTiming8__n,	DramTiming9__n,	DramDerateTiming0__n,	DramDerateTiming1__n,	Dimm0AutoRefTiming1__n,	Dimm1AutoRefTiming1__n,	AutoRefTiming2__n,	PwmMgmtTiming0_n,	PwmMgmtTiming1__n,	PwmMgmtTiming2__n,	PwmMgmtTiming3__n,	TmrTrnIntvl,	DFIDelay1,	DFIDelay2,	DvfsTrnCtl,	TrnTiming0,	TrnTiming1,	TrnTiming2 */
+/* BUS3_PLL SW 936 */	{ 0x00050a09,	0x09041e14,	0x05000013,	0x00000100,	0x09050500,	0x00110805,	0x00070004,	0x00070004,	0x00001004,	0x0a132811,	0x20150b0a,	0x00000a06,	0x002b0055,	0x002b0055,	0x00000005,	0x04020604,	0x00000404,	0x0000005a,	0x00000492,	0x00000000,	0x00010510,	0x00001004,	0x00000303,	0x25180875,	0x16250f18,	0x00000014 },
+/* BUS0_PLL SW 468 */	{ 0x00030505,	0x05040f0a,	0x0400000a,	0x00000100,	0x05040400,	0x000a0605,	0x00070004,	0x00070004,	0x00000c04,	0x0a101c0a,	0x100b0605,	0x00000504,	0x0016002b,	0x0016002b,	0x00000004,	0x03020403,	0x00000404,	0x0000002e,	0x00000249,	0x00000000,	0x00010309,	0x00000902,	0x00000000,	0x1e18043b,	0x101e0c18,	0x00000014 }
+};
+
+static const struct phy_dfs_table g_phy_dfs_table_switch[] = {
+	/* DVFSn_CON0,	DVFSn_CON1,	DVFSn_CON2,	DVFSn_CON3,	DVFSn_CON4 */
+/* BUS3_PLL SW 936 */	{ 0x3a859800,	0x80100000,	0x4001a070,	0x7df3ffff,	0x00003f3f },
+/* BUS0_PLL SW 468 */	{ 0x1d430800,	0x80100000,	0x00004051,	0x7df3ffff,	0x00003f3f }
+};
+
+static const struct dram_dfs_table g_dram_dfs_table_switch[] = {
+	/* MR1OP,	MR2OP,	MR3OP,	MR11OP,	MR12OP,	MR14OP,	MR22OP */
+/* BUS3_PLL SW 936 */	{ 0x3e,	0x1b,	0xf1,	0x04,	0x5d,	0x17,	0x26 },
+/* BUS0_PLL SW 468 */	{ 0x16,	0x09,	0xf1,	0x04,	0x5d,	0x17,	0x26 }
+};
+
+static const unsigned long long mif_freq_to_level_switch[] = {
+/* BUS3_PLL SW 936 */	936 * MHZ,
+/* BUS0_PLL SW 468 */	468 * MHZ
+};
+
+void dmc_misc_direct_dmc_enable(int enable)
+{
+	pwrcal_writel(DMC_MISC_CON0, (enable<<24)|(0x2<<20));
+}
+
+void smc_mode_register_write(int mr, int op)
+{
+	pwrcal_writel(ModeRegAddr, ((0x3<<28)|(mr<<20)));
+	pwrcal_writel(ModeRegWrData, op);
+	pwrcal_writel(MprMrCtl, 0x10);
+}
+
+static unsigned int convert_to_level(unsigned long long freq)
+{
+	int idx;
+	int tablesize = num_mif_freq_to_level;
+
+	for (idx = tablesize - 1; idx >= 0; idx--)
+		if (freq <= mif_freq_to_level[idx])
+			return (unsigned int)idx;
+
+	return 0;
+}
+
+static unsigned int convert_to_level_switch(unsigned long long freq)
+{
+	int idx;
+	int tablesize = sizeof(mif_freq_to_level_switch) / sizeof(mif_freq_to_level_switch[0]);
+
+	for (idx = tablesize - 1; idx >= 0; idx--)
+		if (freq <= mif_freq_to_level_switch[idx])
+			return (unsigned int)idx;
+
+	return 0;
+}
+
+void pwrcal_dmc_set_dvfs(unsigned long long target_mif_freq, unsigned int timing_set_idx)
+{
+	unsigned int uReg;
+	unsigned int target_mif_level_idx, target_mif_level_switch_idx;
+	unsigned int mr13;
+
+	target_mif_level_idx = convert_to_level(target_mif_freq);
+
+	target_mif_level_switch_idx = convert_to_level_switch(target_mif_freq);
+
+	/* 1. Configure parameter */
+	if (timing_set_idx == MIF_TIMING_SET_0) {
+		pwrcal_writel(DMC_MISC_CON1, 0x0);	//timing_set_sw_r=0x0
+
+		pwrcal_writel(DramTiming0_0, g_smc_dfs_table[target_mif_level_idx].DramTiming0);
+		pwrcal_writel(DramTiming1_0, g_smc_dfs_table[target_mif_level_idx].DramTiming1);
+		pwrcal_writel(DramTiming2_0, g_smc_dfs_table[target_mif_level_idx].DramTiming2);
+		pwrcal_writel(DramTiming3_0, g_smc_dfs_table[target_mif_level_idx].DramTiming3);
+		pwrcal_writel(DramTiming4_0, g_smc_dfs_table[target_mif_level_idx].DramTiming4);
+		pwrcal_writel(DramTiming5_0, g_smc_dfs_table[target_mif_level_idx].DramTiming5);
+		pwrcal_writel(DramTiming6_0, g_smc_dfs_table[target_mif_level_idx].DramTiming6);
+		pwrcal_writel(DramTiming7_0, g_smc_dfs_table[target_mif_level_idx].DramTiming7);
+		pwrcal_writel(DramTiming8_0, g_smc_dfs_table[target_mif_level_idx].DramTiming8);
+		pwrcal_writel(DramTiming9_0, g_smc_dfs_table[target_mif_level_idx].DramTiming9);
+		pwrcal_writel(DramDerateTiming0_0, g_smc_dfs_table[target_mif_level_idx].DramDerateTiming0);
+		pwrcal_writel(DramDerateTiming1_0, g_smc_dfs_table[target_mif_level_idx].DramDerateTiming1);
+		pwrcal_writel(Dimm0AutoRefTiming1_0, g_smc_dfs_table[target_mif_level_idx].Dimm0AutoRefTiming1);
+		pwrcal_writel(Dimm1AutoRefTiming1_0, g_smc_dfs_table[target_mif_level_idx].Dimm1AutoRefTiming1);
+		pwrcal_writel(AutoRefTiming2_0, g_smc_dfs_table[target_mif_level_idx].AutoRefTiming2);
+		pwrcal_writel(PwrMgmtTiming0_0, g_smc_dfs_table[target_mif_level_idx].PwrMgmtTiming0);
+		pwrcal_writel(PwrMgmtTiming1_0, g_smc_dfs_table[target_mif_level_idx].PwrMgmtTiming1);
+		pwrcal_writel(PwrMgmtTiming2_0, g_smc_dfs_table[target_mif_level_idx].PwrMgmtTiming2);
+		pwrcal_writel(PwrMgmtTiming3_0, g_smc_dfs_table[target_mif_level_idx].PwrMgmtTiming3);
+		pwrcal_writel(TmrTrnInterval_0, g_smc_dfs_table[target_mif_level_idx].TmrTrnInterval);
+		pwrcal_writel(DFIDelay1_0, g_smc_dfs_table[target_mif_level_idx].DFIDelay1);
+		pwrcal_writel(DFIDelay2_0, g_smc_dfs_table[target_mif_level_idx].DFIDelay2);
+		pwrcal_writel(DvfsTrnCtl_0, g_smc_dfs_table[target_mif_level_idx].DvfsTrnCtl);
+		pwrcal_writel(TrnTiming0_0, g_smc_dfs_table[target_mif_level_idx].TrnTiming0);
+		pwrcal_writel(TrnTiming1_0, g_smc_dfs_table[target_mif_level_idx].TrnTiming1);
+		pwrcal_writel(TrnTiming2_0, g_smc_dfs_table[target_mif_level_idx].TrnTiming2);
+
+		uReg = pwrcal_readl((void *)PHY_DVFS_CON_CH0);
+		uReg &= ~(0x3<<30);
+		uReg |= (0x1<<30);	//0x1 = DVFS 1 mode
+		pwrcal_writel(PHY_DVFS_CON, uReg);
+
+		pwrcal_writel(PHY_DVFS0_CON0, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON0);
+		pwrcal_writel(PHY_DVFS0_CON1, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON1);
+		pwrcal_writel(PHY_DVFS0_CON2, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON2);
+		pwrcal_writel(PHY_DVFS0_CON3, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON3);
+		pwrcal_writel(PHY_DVFS0_CON4, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON4);
+
+		mr13 = (0x1<<7)|(0x0<<6)|(0x0<<5)|(0x1<<3);	//FSP-OP=0x1, FSP-WR=0x0, DMD=0x0, VRCG=0x1
+		smc_mode_register_write(DRAM_MR13, mr13);
+		smc_mode_register_write(DRAM_MR1, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR1);
+		smc_mode_register_write(DRAM_MR2, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR2);
+		smc_mode_register_write(DRAM_MR3, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR3);
+		smc_mode_register_write(DRAM_MR11, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR11);
+		smc_mode_register_write(DRAM_MR12, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR12);
+		smc_mode_register_write(DRAM_MR14, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR14);
+		smc_mode_register_write(DRAM_MR22, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR22);
+
+		mr13 &= ~(0x1<<7);	// clear FSP-OP[7]
+		pwrcal_writel(MRS_DATA1, mr13);
+	} else if (timing_set_idx == MIF_TIMING_SET_1) {
+		pwrcal_writel(DMC_MISC_CON1, 0x1);	//timing_set_sw_r=0x1
+
+		pwrcal_writel(DramTiming0_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming0);
+		pwrcal_writel(DramTiming1_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming1);
+		pwrcal_writel(DramTiming2_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming2);
+		pwrcal_writel(DramTiming3_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming3);
+		pwrcal_writel(DramTiming4_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming4);
+		pwrcal_writel(DramTiming5_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming5);
+		pwrcal_writel(DramTiming6_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming6);
+		pwrcal_writel(DramTiming7_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming7);
+		pwrcal_writel(DramTiming8_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming8);
+		pwrcal_writel(DramTiming9_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming9);
+		pwrcal_writel(DramDerateTiming0_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramDerateTiming0);
+		pwrcal_writel(DramDerateTiming1_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramDerateTiming1);
+		pwrcal_writel(Dimm0AutoRefTiming1_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].Dimm0AutoRefTiming1);
+		pwrcal_writel(Dimm1AutoRefTiming1_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].Dimm1AutoRefTiming1);
+		pwrcal_writel(AutoRefTiming2_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].AutoRefTiming2);
+		pwrcal_writel(PwrMgmtTiming0_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].PwrMgmtTiming0);
+		pwrcal_writel(PwrMgmtTiming1_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].PwrMgmtTiming1);
+		pwrcal_writel(PwrMgmtTiming2_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].PwrMgmtTiming2);
+		pwrcal_writel(PwrMgmtTiming3_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].PwrMgmtTiming3);
+		pwrcal_writel(TmrTrnInterval_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].TmrTrnInterval);
+		pwrcal_writel(DFIDelay1_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DFIDelay1);
+		pwrcal_writel(DFIDelay2_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DFIDelay2);
+		pwrcal_writel(DvfsTrnCtl_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DvfsTrnCtl);
+		pwrcal_writel(TrnTiming0_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].TrnTiming0);
+		pwrcal_writel(TrnTiming1_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].TrnTiming1);
+		pwrcal_writel(TrnTiming2_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].TrnTiming2);
+
+		uReg = pwrcal_readl(PHY_DVFS_CON_CH0);
+		uReg &= ~(0x3<<30);
+		uReg |= (0x2<<30);	//0x2 = DVFS 2 mode
+		pwrcal_writel(PHY_DVFS_CON, uReg);
+
+		pwrcal_writel(PHY_DVFS1_CON0, g_phy_dfs_table_switch[target_mif_level_switch_idx].DVFSn_CON0);
+		pwrcal_writel(PHY_DVFS1_CON1, g_phy_dfs_table_switch[target_mif_level_switch_idx].DVFSn_CON1);
+		pwrcal_writel(PHY_DVFS1_CON2, g_phy_dfs_table_switch[target_mif_level_switch_idx].DVFSn_CON2);
+		pwrcal_writel(PHY_DVFS1_CON3, g_phy_dfs_table_switch[target_mif_level_switch_idx].DVFSn_CON3);
+		pwrcal_writel(PHY_DVFS1_CON4, g_phy_dfs_table_switch[target_mif_level_switch_idx].DVFSn_CON4);
+
+		mr13 = (0x0<<7)|(0x1<<6)|(0x0<<5)|(0x1<<3);	//FSP-OP=0x0, FSP-WR=0x1, DMD=0x0, VRCG=0x1
+		smc_mode_register_write(DRAM_MR13, mr13);
+		smc_mode_register_write(DRAM_MR1, g_dram_dfs_table_switch[target_mif_level_switch_idx].DirectCmd_MR1);
+		smc_mode_register_write(DRAM_MR2, g_dram_dfs_table_switch[target_mif_level_switch_idx].DirectCmd_MR2);
+		smc_mode_register_write(DRAM_MR3, g_dram_dfs_table_switch[target_mif_level_switch_idx].DirectCmd_MR3);
+		smc_mode_register_write(DRAM_MR11, g_dram_dfs_table_switch[target_mif_level_switch_idx].DirectCmd_MR11);
+		smc_mode_register_write(DRAM_MR12, g_dram_dfs_table_switch[target_mif_level_switch_idx].DirectCmd_MR12);
+		smc_mode_register_write(DRAM_MR14, g_dram_dfs_table_switch[target_mif_level_switch_idx].DirectCmd_MR14);
+		smc_mode_register_write(DRAM_MR22, g_dram_dfs_table_switch[target_mif_level_switch_idx].DirectCmd_MR22);
+
+		mr13 &= ~(0x1<<7);	// clear FSP-OP[7]
+		mr13 |= (0x1<<7);	// set FSP-OP[7]=0x1
+		pwrcal_writel(MRS_DATA1, mr13);
+	}	 else {
+		pr_err("wrong DMC timing set selection on DVFS\n");
+		return;
+	}
+}
+
+
+void dfs_dram_param_init(void)
+{
+	int i;
+	void *dram_block;
+	int memory_size = 3; // means 3GB
+	struct ect_timing_param_size *size;
+
+	dram_block = ect_get_block(BLOCK_TIMING_PARAM);
+	if (dram_block == NULL)
+		return;
+
+	size = ect_timing_param_get_size(dram_block, memory_size);
+	if (size == NULL)
+		return;
+
+	if (num_of_g_smc_dfs_table_column + num_of_g_phy_dfs_table_column + num_of_g_dram_dfs_table_column != size->num_of_timing_param)
+		return;
+
+	g_smc_dfs_table = kzalloc(sizeof(struct smc_dfs_table) * num_of_g_smc_dfs_table_column * size->num_of_level, GFP_KERNEL);
+	if (g_smc_dfs_table == NULL)
+		return;
+
+	g_phy_dfs_table = kzalloc(sizeof(struct phy_dfs_table) * num_of_g_phy_dfs_table_column * size->num_of_level, GFP_KERNEL);
+	if (g_phy_dfs_table == NULL)
+		return;
+
+	g_dram_dfs_table = kzalloc(sizeof(struct dram_dfs_table) * num_of_g_dram_dfs_table_column * size->num_of_level, GFP_KERNEL);
+	if (g_dram_dfs_table == NULL)
+		return;
+
+	for (i = 0; i < size->num_of_level; ++i) {
+		g_smc_dfs_table[i].DramTiming0 = size->timing_parameter[i * num_of_dram_parameter + DramTiming0];
+		g_smc_dfs_table[i].DramTiming1 = size->timing_parameter[i * num_of_dram_parameter + DramTiming1];
+		g_smc_dfs_table[i].DramTiming2 = size->timing_parameter[i * num_of_dram_parameter + DramTiming2];
+		g_smc_dfs_table[i].DramTiming3 = size->timing_parameter[i * num_of_dram_parameter + DramTiming3];
+		g_smc_dfs_table[i].DramTiming4 = size->timing_parameter[i * num_of_dram_parameter + DramTiming4];
+		g_smc_dfs_table[i].DramTiming5 = size->timing_parameter[i * num_of_dram_parameter + DramTiming5];
+		g_smc_dfs_table[i].DramTiming6 = size->timing_parameter[i * num_of_dram_parameter + DramTiming6];
+		g_smc_dfs_table[i].DramTiming7 = size->timing_parameter[i * num_of_dram_parameter + DramTiming7];
+		g_smc_dfs_table[i].DramTiming8 = size->timing_parameter[i * num_of_dram_parameter + DramTiming8];
+		g_smc_dfs_table[i].DramTiming9 = size->timing_parameter[i * num_of_dram_parameter + DramTiming9];
+		g_smc_dfs_table[i].DramDerateTiming0 = size->timing_parameter[i * num_of_dram_parameter + DramDerateTiming0];
+		g_smc_dfs_table[i].DramDerateTiming1 = size->timing_parameter[i * num_of_dram_parameter + DramDerateTiming1];
+		g_smc_dfs_table[i].Dimm0AutoRefTiming1 = size->timing_parameter[i * num_of_dram_parameter + Dimm0AutoRefTiming1];
+		g_smc_dfs_table[i].Dimm1AutoRefTiming1 = size->timing_parameter[i * num_of_dram_parameter + Dimm1AutoRefTiming1];
+		g_smc_dfs_table[i].AutoRefTiming2 = size->timing_parameter[i * num_of_dram_parameter + AutoRefTiming2];
+		g_smc_dfs_table[i].PwrMgmtTiming0 = size->timing_parameter[i * num_of_dram_parameter + PwrMgmtTiming0];
+		g_smc_dfs_table[i].PwrMgmtTiming1 = size->timing_parameter[i * num_of_dram_parameter + PwrMgmtTiming1];
+		g_smc_dfs_table[i].PwrMgmtTiming2 = size->timing_parameter[i * num_of_dram_parameter + PwrMgmtTiming2];
+		g_smc_dfs_table[i].PwrMgmtTiming3 = size->timing_parameter[i * num_of_dram_parameter + PwrMgmtTiming3];
+		g_smc_dfs_table[i].TmrTrnInterval = size->timing_parameter[i * num_of_dram_parameter + TmrTrnInterval];
+		g_smc_dfs_table[i].DFIDelay1 = size->timing_parameter[i * num_of_dram_parameter + DFIDelay1];
+		g_smc_dfs_table[i].DFIDelay2 = size->timing_parameter[i * num_of_dram_parameter + DFIDelay2];
+		g_smc_dfs_table[i].DvfsTrnCtl = size->timing_parameter[i * num_of_dram_parameter + DvfsTrnCtl];
+		g_smc_dfs_table[i].TrnTiming0 = size->timing_parameter[i * num_of_dram_parameter + TrnTiming0];
+		g_smc_dfs_table[i].TrnTiming1 = size->timing_parameter[i * num_of_dram_parameter + TrnTiming1];
+		g_smc_dfs_table[i].TrnTiming2 = size->timing_parameter[i * num_of_dram_parameter + TrnTiming2];
+
+		g_phy_dfs_table[i].DVFSn_CON0 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON0];
+		g_phy_dfs_table[i].DVFSn_CON1 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON1];
+		g_phy_dfs_table[i].DVFSn_CON2 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON2];
+		g_phy_dfs_table[i].DVFSn_CON3 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON3];
+		g_phy_dfs_table[i].DVFSn_CON4 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON4];
+
+		g_dram_dfs_table[i].DirectCmd_MR1 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR1];
+		g_dram_dfs_table[i].DirectCmd_MR2 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR2];
+		g_dram_dfs_table[i].DirectCmd_MR3 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR3];
+		g_dram_dfs_table[i].DirectCmd_MR11 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR11];
+		g_dram_dfs_table[i].DirectCmd_MR12 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR12];
+		g_dram_dfs_table[i].DirectCmd_MR14 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR14];
+		g_dram_dfs_table[i].DirectCmd_MR22 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR22];
+	}
+}
+
+void dfs_mif_level_init(void)
+{
+	int i;
+	void *dvfs_block;
+	struct ect_dvfs_domain *domain;
+
+	dvfs_block = ect_get_block(BLOCK_DVFS);
+	if (dvfs_block == NULL)
+		return;
+
+	domain = ect_dvfs_get_domain(dvfs_block, vclk_dvfs_mif.vclk.name);
+	if (domain == NULL)
+		return;
+
+	mif_freq_to_level = kzalloc(sizeof(unsigned long long) * domain->num_of_level, GFP_KERNEL);
+	if (mif_freq_to_level == NULL)
+		return;
+
+	num_mif_freq_to_level = domain->num_of_level;
+
+	for (i = 0; i < domain->num_of_level; ++i)
+		mif_freq_to_level[i] = domain->list_level[i].level * KHZ;
+}
+
+void dfs_dram_init(void)
+{
+	dfs_dram_param_init();
+	dfs_mif_level_init();
+}

drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-pll.c

@@ -0,0 +1,798 @@
+#include "../pwrcal.h"
+#include "../pwrcal-clk.h"
+#include "../pwrcal-env.h"
+#include "../pwrcal-rae.h"
+#include "../pwrcal-pmu.h"
+#include "S5E8890-cmusfr.h"
+#include "S5E8890-pmusfr.h"
+#include "S5E8890-cmu.h"
+
+
+/*
+	PLLs
+*/
+/* PLL141XX Clock Type */
+#define PLL141XX_MDIV_SHIFT		16
+#define PLL141XX_PDIV_SHIFT		8
+#define PLL141XX_SDIV_SHIFT		0
+#define PLL141XX_MDIV_MASK		0x3FF
+#define PLL141XX_PDIV_MASK		0x3F
+#define PLL141XX_SDIV_MASK		0x7
+#define PLL141XX_ENABLE			31
+#define PLL141XX_LOCKED			29
+#define PLL141XX_BYPASS			22
+
+/* PLL1431X Clock Type */
+#define PLL1431X_MDIV_SHIFT		16
+#define PLL1431X_PDIV_SHIFT		8
+#define PLL1431X_SDIV_SHIFT		0
+#define PLL1431X_K_SHIFT		0
+#define PLL1431X_MDIV_MASK		0x3FF
+#define PLL1431X_PDIV_MASK		0x3F
+#define PLL1431X_SDIV_MASK		0x7
+#define PLL1431X_K_MASK		0xFFFF
+#define PLL1431X_ENABLE			31
+#define PLL1431X_LOCKED			29
+#define PLL1431X_BYPASS			4
+
+#define FIN_HZ_26M		(26*MHZ)
+
+static const struct pwrcal_pll_rate_table *_clk_get_pll_settings(
+					struct pwrcal_pll *pll_clk,
+					unsigned long long rate)
+{
+	int i;
+	const struct pwrcal_pll_rate_table  *prate_table = pll_clk->rate_table;
+
+	for (i = 0; i < pll_clk->rate_count; i++) {
+		if (rate == prate_table[i].rate)
+			return &prate_table[i];
+	}
+
+	return NULL;
+}
+
+static int _clk_pll141xx_find_pms(struct pll_spec *pll_spec,
+				struct pwrcal_pll_rate_table *rate_table,
+				unsigned long long rate)
+{
+	unsigned int p, m, s;
+	unsigned long long fref, fvco, fout;
+	unsigned long long tmprate, tmpfout;
+	unsigned long long mindiffrate = 0xFFFFFFFFFFFFFFFF;
+	unsigned int min_p, min_m, min_s, min_fout;
+
+	for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
+		fref = FIN_HZ_26M / p;
+		if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
+			continue;
+
+		for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
+			tmprate = rate;
+			do_div(tmprate, MHZ);
+			tmprate = tmprate * p * (1 << s);
+			do_div(tmprate, (FIN_HZ_26M / MHZ));
+			m = (unsigned int)tmprate;
+
+			if ((m < pll_spec->mdiv_min)
+					|| (m > pll_spec->mdiv_max))
+				continue;
+
+			fvco = ((unsigned long long)FIN_HZ_26M) * m;
+			do_div(fvco, p);
+			if ((fvco < pll_spec->fvco_min)
+					|| (fvco > pll_spec->fvco_max))
+				continue;
+
+			fout = fvco >> s;
+			if ((fout >= pll_spec->fout_min)
+					&& (fout <= pll_spec->fout_max)) {
+				tmprate = rate;
+				do_div(tmprate, KHZ);
+				tmpfout = fout;
+				do_div(tmpfout, KHZ);
+				if (tmprate == tmpfout) {
+					rate_table->rate = fout;
+					rate_table->pdiv = p;
+					rate_table->mdiv = m;
+					rate_table->sdiv = s;
+					rate_table->kdiv = 0;
+					return 0;
+				}
+				if (tmpfout < tmprate && mindiffrate > tmprate - tmpfout) {
+					mindiffrate = tmprate - tmpfout;
+					min_fout = fout;
+					min_p = p;
+					min_m = m;
+					min_s = s;
+				}
+			}
+		}
+	}
+
+	if (mindiffrate != 0xFFFFFFFFFFFFFFFF) {
+		rate_table->rate = min_fout;
+		rate_table->pdiv = min_p;
+		rate_table->mdiv = min_m;
+		rate_table->sdiv = min_s;
+		rate_table->kdiv = 0;
+		return 0;
+	}
+	return -1;
+}
+
+
+static int _clk_pll1419x_find_pms(struct pll_spec *pll_spec,
+				struct pwrcal_pll_rate_table *rate_table,
+				unsigned long long rate)
+{
+	unsigned int p, m, s;
+	unsigned long long fref, fvco, fout;
+	unsigned long long tmprate, tmpfout;
+	unsigned long long mindiffrate = 0xFFFFFFFFFFFFFFFF;
+	unsigned int min_p, min_m, min_s, min_fout;
+
+	for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
+		fref = FIN_HZ_26M / p;
+		if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
+			continue;
+
+		for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
+			/*tmprate = rate;*/
+			tmprate = rate/2; /*for PLL1419*/
+			do_div(tmprate, MHZ);
+			tmprate = tmprate * p * (1 << s);
+			do_div(tmprate, (FIN_HZ_26M / MHZ));
+			m = (unsigned int)tmprate;
+
+			if ((m < pll_spec->mdiv_min)
+					|| (m > pll_spec->mdiv_max))
+				continue;
+
+			fvco = ((unsigned long long)FIN_HZ_26M) * m;
+			do_div(fvco, p);
+			if ((fvco < pll_spec->fvco_min)
+					|| (fvco > pll_spec->fvco_max))
+				continue;
+
+			fout = fvco >> s;
+			if ((fout >= pll_spec->fout_min)
+					&& (fout <= pll_spec->fout_max)) {
+				tmprate = rate;
+				do_div(tmprate, KHZ);
+				tmpfout = fout;
+				do_div(tmpfout, KHZ);
+				if (tmprate == tmpfout) {
+					rate_table->rate = fout;
+					rate_table->pdiv = p;
+					rate_table->mdiv = m;
+					rate_table->sdiv = s;
+					rate_table->kdiv = 0;
+					return 0;
+				}
+			}
+			if (tmpfout < tmprate && mindiffrate > tmprate - tmpfout) {
+				mindiffrate = tmprate - tmpfout;
+				min_fout = fout;
+				min_p = p;
+				min_m = m;
+				min_s = s;
+			}
+		}
+	}
+
+	if (mindiffrate != 0xFFFFFFFFFFFFFFFF) {
+		rate_table->rate = min_fout;
+		rate_table->pdiv = min_p;
+		rate_table->mdiv = min_m;
+		rate_table->sdiv = min_s;
+		rate_table->kdiv = 0;
+		return 0;
+	}
+	return -1;
+}
+
+static int _clk_pll141xx_is_enabled(struct pwrcal_clk *clk)
+{
+	return (int)(pwrcal_getbit(clk->offset, PLL141XX_ENABLE));
+}
+
+static int _clk_pll141xx_enable(struct pwrcal_clk *clk)
+{
+	int timeout;
+
+	if (pwrcal_getbit(clk->offset, PLL141XX_ENABLE))
+		return 0;
+
+	pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 1);
+
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+static int _clk_pll1419x_enable(struct pwrcal_clk *clk)
+{
+	int timeout;
+
+	if (pwrcal_getbit(clk->offset, PLL141XX_ENABLE))
+		return 0;
+
+	pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 1);
+
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(MIF0_PLL_CON0, PLL141XX_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(MIF1_PLL_CON0, PLL141XX_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(MIF2_PLL_CON0, PLL141XX_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(MIF3_PLL_CON0, PLL141XX_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+
+static int _clk_pll141xx_disable(struct pwrcal_clk *clk)
+{
+	pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 0);
+
+	return 0;
+}
+
+int _clk_pll141xx_is_disabled_bypass(struct pwrcal_clk *clk)
+{
+	if (pwrcal_getbit(clk->offset + 1, PLL141XX_BYPASS))
+		return 0;
+
+	return 1;
+}
+
+
+int _clk_pll141xx_set_bypass(struct pwrcal_clk *clk, int bypass_disable)
+{
+	if (bypass_disable == 0)
+		pwrcal_setbit(clk + 1, PLL141XX_BYPASS, 1);
+	else
+		pwrcal_setbit(clk + 1, PLL141XX_BYPASS, 0);
+
+	return 0;
+}
+
+static int _clk_pll141xx_set_pms(struct pwrcal_clk *clk,
+				const struct pwrcal_pll_rate_table  *rate_table)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0;
+
+	int timeout;
+
+	pdiv = rate_table->pdiv;
+	mdiv = rate_table->mdiv;
+	sdiv = rate_table->sdiv;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	pll_con0 &= ~((PLL141XX_MDIV_MASK << PLL141XX_MDIV_SHIFT)
+			| (PLL141XX_PDIV_MASK << PLL141XX_PDIV_SHIFT)
+			| (PLL141XX_SDIV_MASK << PLL141XX_SDIV_SHIFT));
+	pll_con0 |=  (mdiv << PLL141XX_MDIV_SHIFT)
+			| (pdiv << PLL141XX_PDIV_SHIFT)
+			| (sdiv << PLL141XX_SDIV_SHIFT);
+	pll_con0 &= ~(1<<26);
+	pll_con0 |= (1<<5);
+
+	pwrcal_writel(clk->status, pdiv*150);
+	pwrcal_writel(clk->offset, pll_con0);
+
+	if (pll_con0 & (1 << PLL141XX_ENABLE)) {
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+	}
+
+	return 0;
+
+}
+
+static int _clk_pll1419x_set_pms(struct pwrcal_clk *clk,
+				const struct pwrcal_pll_rate_table  *rate_table)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0;
+
+	int timeout;
+
+	pdiv = rate_table->pdiv;
+	mdiv = rate_table->mdiv;
+	sdiv = rate_table->sdiv;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	pll_con0 &= ~((PLL141XX_MDIV_MASK << PLL141XX_MDIV_SHIFT)
+			| (PLL141XX_PDIV_MASK << PLL141XX_PDIV_SHIFT)
+			| (PLL141XX_SDIV_MASK << PLL141XX_SDIV_SHIFT));
+	pll_con0 |=  (mdiv << PLL141XX_MDIV_SHIFT)
+			| (pdiv << PLL141XX_PDIV_SHIFT)
+			| (sdiv << PLL141XX_SDIV_SHIFT);
+
+	pwrcal_writel(MIF0_PLL_LOCK, pdiv*150);
+	pwrcal_writel(MIF1_PLL_LOCK, pdiv*150);
+	pwrcal_writel(MIF2_PLL_LOCK, pdiv*150);
+	pwrcal_writel(MIF3_PLL_LOCK, pdiv*150);
+	pwrcal_writel(clk->offset, pll_con0);
+
+	if (pll_con0 & (1 << PLL141XX_ENABLE)) {
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(MIF0_PLL_CON0, PLL141XX_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(MIF1_PLL_CON0, PLL141XX_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(MIF2_PLL_CON0, PLL141XX_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(MIF3_PLL_CON0, PLL141XX_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+	}
+
+	return 0;
+
+}
+
+
+static int _clk_pll141xx_set_rate(struct pwrcal_clk *clk,
+					unsigned long long rate)
+{
+	struct pwrcal_pll *pll = to_pll(clk);
+	struct pll_spec *pll_spec;
+	struct pwrcal_pll_rate_table  tmp_rate_table;
+	const struct pwrcal_pll_rate_table  *rate_table;
+
+	if (rate == 0) {
+		if (_clk_pll141xx_is_enabled(clk) != 0)
+			if (_clk_pll141xx_disable(clk))
+				goto errorout;
+		return 0;
+	}
+
+	rate_table = _clk_get_pll_settings(pll, rate);
+	if (rate_table == NULL) {
+		pll_spec = clk_pll_get_spec(clk);
+		if (pll_spec == NULL)
+			goto errorout;
+
+		if (_clk_pll141xx_find_pms(pll_spec, &tmp_rate_table, rate)) {
+			pr_err("can't find pms value for rate(%lldHz) of \'%s\'",
+				rate,
+				clk->name);
+			goto errorout;
+		}
+
+		rate_table = &tmp_rate_table;
+
+		pr_warn("not exist in rate table, p(%d), m(%d), s(%d), fout(%lldHz) %s",
+				rate_table->pdiv,
+				rate_table->mdiv,
+				rate_table->sdiv,
+				rate,
+				clk->name);
+	}
+
+	if (_clk_pll141xx_set_pms(clk, rate_table))
+		goto errorout;
+
+	if (rate != 0) {
+		if (_clk_pll141xx_is_enabled(clk) == 0)
+			_clk_pll141xx_enable(clk);
+	}
+	return 0;
+
+errorout:
+	return -1;
+}
+
+static int _clk_pll1419x_set_rate(struct pwrcal_clk *clk,
+					unsigned long long rate)
+{
+	struct pwrcal_pll *pll = to_pll(clk);
+	struct pll_spec *pll_spec;
+	struct pwrcal_pll_rate_table  tmp_rate_table;
+	const struct pwrcal_pll_rate_table  *rate_table;
+
+	if (rate == 0) {
+		if (_clk_pll141xx_is_enabled(clk) != 0)
+			if (_clk_pll141xx_disable(clk))
+				goto errorout;
+		return 0;
+	}
+
+	rate_table = _clk_get_pll_settings(pll, rate);
+	if (rate_table == NULL) {
+		pll_spec = clk_pll_get_spec(clk);
+		if (pll_spec == NULL)
+			goto errorout;
+
+		if (_clk_pll1419x_find_pms(pll_spec, &tmp_rate_table, rate)) {
+			pr_err("can't find pms value for rate(%lldHz) of \'%s\'",
+				rate,
+				clk->name);
+			goto errorout;
+		}
+
+		rate_table = &tmp_rate_table;
+
+		pr_warn("not exist in rate table, p(%d), m(%d), s(%d), fout(%lldHz) %s",
+				rate_table->pdiv,
+				rate_table->mdiv,
+				rate_table->sdiv,
+				rate,
+				clk->name);
+	}
+
+	_clk_pll141xx_disable(clk);
+
+	if (_clk_pll1419x_set_pms(clk, rate_table))
+		goto errorout;
+
+	if (rate != 0) {
+		if (_clk_pll141xx_is_enabled(clk) == 0)
+			_clk_pll1419x_enable(clk);
+	}
+	return 0;
+
+errorout:
+	return -1;
+}
+
+
+static unsigned long long _clk_pll141xx_get_rate(struct pwrcal_clk *clk)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0;
+	unsigned long long fout;
+
+	if (_clk_pll141xx_is_enabled(clk) == 0)
+		return 0;
+	pll_con0 = pwrcal_readl(clk->offset);
+	mdiv = (pll_con0 >> PLL141XX_MDIV_SHIFT) & PLL141XX_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL141XX_PDIV_SHIFT) & PLL141XX_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL141XX_SDIV_SHIFT) & PLL141XX_SDIV_MASK;
+
+	if (pdiv == 0) {
+		pr_err("pdiv is 0, id(%s)", clk->name);
+		return 0;
+	}
+	fout = FIN_HZ_26M * mdiv;
+	do_div(fout, (pdiv << sdiv));
+	return (unsigned long long)fout;
+}
+
+static unsigned long long _clk_pll1419x_get_rate(struct pwrcal_clk *clk)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0;
+	unsigned long long fout;
+
+	if (_clk_pll141xx_is_enabled(clk) == 0)
+		return 0;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	mdiv = (pll_con0 >> PLL141XX_MDIV_SHIFT) & PLL141XX_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL141XX_PDIV_SHIFT) & PLL141XX_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL141XX_SDIV_SHIFT) & PLL141XX_SDIV_MASK;
+
+	if (pdiv == 0) {
+		pr_err("pdiv is 0, id(%s)", clk->name);
+		return 0;
+	}
+	fout = FIN_HZ_26M * 2 * mdiv;
+	do_div(fout, (pdiv << sdiv));
+	return (unsigned long long)fout;
+}
+
+static int _clk_pll1431x_find_pms(struct pll_spec *pll_spec,
+					struct pwrcal_pll_rate_table *rate_table,
+					unsigned long long rate)
+{
+	unsigned int p, m, s;
+	signed short k;
+	unsigned long long fref, fvco, fout;
+	unsigned long long tmprate, tmpfout;
+
+	for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
+		fref = FIN_HZ_26M / p;
+		if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
+			continue;
+
+		for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
+			tmprate = rate;
+			do_div(tmprate, MHZ);
+			tmprate = tmprate * p * (1 << s);
+			do_div(tmprate, (FIN_HZ_26M / MHZ));
+			m = (unsigned int)tmprate;
+
+			if ((m < pll_spec->mdiv_min)
+					|| (m > pll_spec->mdiv_max))
+				continue;
+
+			tmprate = rate;
+			do_div(tmprate, MHZ);
+			tmprate = tmprate * p * (1 << s);
+			do_div(tmprate, (FIN_HZ_26M / MHZ));
+			tmprate = (tmprate - m) * 65536;
+			k = (unsigned int)tmprate;
+			if ((k < pll_spec->kdiv_min)
+					|| (k > pll_spec->kdiv_max))
+				continue;
+
+			fvco = FIN_HZ_26M * ((m << 16) + k);
+			do_div(fvco, p);
+			fvco >>= 16;
+			if ((fvco < pll_spec->fvco_min)
+					|| (fvco > pll_spec->fvco_max))
+				continue;
+
+			fout = fvco >> s;
+			if ((fout >= pll_spec->fout_min)
+				&& (fout <= pll_spec->fout_max)) {
+				tmprate = rate;
+				do_div(tmprate, KHZ);
+				tmpfout = fout;
+				do_div(tmpfout, KHZ);
+				if (tmprate == tmpfout) {
+					rate_table->rate = fout;
+					rate_table->pdiv = p;
+					rate_table->mdiv = m;
+					rate_table->sdiv = s;
+					rate_table->kdiv = k;
+					return 0;
+				}
+			}
+		}
+	}
+
+	return -1;
+}
+
+static int _clk_pll1431x_is_enabled(struct pwrcal_clk *clk)
+{
+	return (int)(pwrcal_getbit(clk->offset, PLL1431X_ENABLE));
+}
+
+static int _clk_pll1431x_enable(struct pwrcal_clk *clk)
+{
+	int timeout;
+
+	if (pwrcal_getbit(clk->offset, PLL1431X_ENABLE))
+		return 0;
+
+	pwrcal_setbit(clk->offset, PLL1431X_ENABLE, 1);
+
+	for (timeout = 0;; timeout++) {
+		if (pwrcal_getbit(clk->offset, PLL1431X_LOCKED))
+			break;
+		if (timeout > CLK_WAIT_CNT)
+			return -1;
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+static int _clk_pll1431x_disable(struct pwrcal_clk *clk)
+{
+	pwrcal_setbit(clk->offset, PLL1431X_ENABLE, 0);
+
+	return 0;
+}
+
+int _clk_pll1431x_is_disabled_bypass(struct pwrcal_clk *clk)
+{
+	if (pwrcal_getbit(clk->offset + 2, PLL1431X_BYPASS))
+		return 0;
+
+	return 1;
+}
+
+int _clk_pll1431x_set_bypass(struct pwrcal_clk *clk, int bypass_disable)
+{
+	if (bypass_disable == 0)
+		pwrcal_setbit(clk->offset + 2, PLL1431X_BYPASS, 1);
+	else
+		pwrcal_setbit(clk->offset + 2, PLL1431X_BYPASS, 0);
+
+	return 0;
+}
+
+static int _clk_pll1431x_set_pms(struct pwrcal_clk *clk,
+			const struct pwrcal_pll_rate_table  *rate_table)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0, pll_con1;
+	signed short kdiv;
+	int timeout;
+
+	pdiv = rate_table->pdiv;
+	mdiv = rate_table->mdiv;
+	sdiv = rate_table->sdiv;
+	kdiv = rate_table->kdiv;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	pll_con1 = pwrcal_readl(clk->offset + 1);
+	pll_con0 &= ~((PLL1431X_MDIV_MASK << PLL1431X_MDIV_SHIFT)
+			| (PLL1431X_PDIV_MASK << PLL1431X_PDIV_SHIFT)
+			| (PLL1431X_SDIV_MASK << PLL1431X_SDIV_SHIFT));
+	pll_con0 |=  (mdiv << PLL1431X_MDIV_SHIFT)
+			| (pdiv << PLL1431X_PDIV_SHIFT)
+			| (sdiv << PLL1431X_SDIV_SHIFT);
+	pll_con0 &= ~(1<<26);
+	pll_con0 |= (1<<5);
+
+	pll_con1 &= ~(PLL1431X_K_MASK << PLL1431X_K_SHIFT);
+	pll_con1 |=  (kdiv << PLL1431X_K_SHIFT);
+
+	if (kdiv == 0)
+		pwrcal_writel(clk->status, pdiv*3000);
+	else
+		pwrcal_writel(clk->status, pdiv*3000);
+	pwrcal_writel(clk->offset, pll_con0);
+	pwrcal_writel(clk->offset + 1, pll_con1);
+
+	if (pll_con0 & (1 << PLL1431X_ENABLE)) {
+		for (timeout = 0;; timeout++) {
+			if (pwrcal_getbit(clk->offset, PLL1431X_LOCKED))
+				break;
+			if (timeout > CLK_WAIT_CNT)
+				return -1;
+			cpu_relax();
+		}
+	}
+
+	return 0;
+}
+
+static int _clk_pll1431x_set_rate(struct pwrcal_clk *clk,
+					unsigned long long rate)
+{
+	struct pwrcal_pll *pll = to_pll(clk);
+	struct pwrcal_pll_rate_table  tmp_rate_table;
+	const struct pwrcal_pll_rate_table  *rate_table;
+	struct pll_spec *pll_spec;
+
+	if (rate == 0) {
+		if (_clk_pll1431x_is_enabled(clk) != 0)
+			if (_clk_pll1431x_disable(clk))
+				goto errorout;
+		return 0;
+	}
+
+	rate_table = _clk_get_pll_settings(pll, rate);
+	if (rate_table == NULL) {
+		pll_spec = clk_pll_get_spec(clk);
+		if (pll_spec == NULL)
+			goto errorout;
+
+		if (_clk_pll1431x_find_pms(pll_spec, &tmp_rate_table, rate) < 0) {
+			pr_err("can't find pms value for rate(%lldHz) of %s",
+				rate,
+				clk->name);
+			goto errorout;
+		}
+
+		rate_table = &tmp_rate_table;
+		pr_warn("not exist in rate table, p(%d) m(%d) s(%d) k(%d) fout(%lld Hz) of %s",
+				rate_table->pdiv,
+				rate_table->mdiv,
+				rate_table->sdiv,
+				rate_table->kdiv,
+				rate,
+				clk->name);
+	}
+
+	if (_clk_pll1431x_set_pms(clk, rate_table))
+		goto errorout;
+
+	if (rate != 0) {
+		if (_clk_pll1431x_is_enabled(clk) == 0)
+			_clk_pll1431x_enable(clk);
+	}
+
+	return 0;
+
+errorout:
+	return -1;
+}
+
+static unsigned long long _clk_pll1431x_get_rate(struct pwrcal_clk *clk)
+{
+	unsigned int mdiv, pdiv, sdiv, pll_con0, pll_con1;
+	signed short kdiv;
+	unsigned long long fout;
+
+	if (_clk_pll1431x_is_enabled(clk) == 0)
+		return 0;
+
+	pll_con0 = pwrcal_readl(clk->offset);
+	pll_con1 = pwrcal_readl(clk->offset + 1);
+	mdiv = (pll_con0 >> PLL1431X_MDIV_SHIFT) & PLL1431X_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL1431X_PDIV_SHIFT) & PLL1431X_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL1431X_SDIV_SHIFT) & PLL1431X_SDIV_MASK;
+
+	kdiv = (short)(pll_con1 >> PLL1431X_K_SHIFT) & PLL1431X_K_MASK;
+
+	if (pdiv == 0) {
+		pr_err("pdiv is 0, id(%s)", clk->name);
+		return 0;
+	}
+
+	fout = FIN_HZ_26M * ((mdiv << 16) + kdiv);
+	do_div(fout, (pdiv << sdiv));
+	fout >>= 16;
+
+	return (unsigned long long)fout;
+}
+
+struct pwrcal_pll_ops pll141xx_ops = {
+	.is_enabled = _clk_pll141xx_is_enabled,
+	.enable = _clk_pll141xx_enable,
+	.disable = _clk_pll141xx_disable,
+	.set_rate = _clk_pll141xx_set_rate,
+	.get_rate = _clk_pll141xx_get_rate,
+};
+
+struct pwrcal_pll_ops pll1419x_ops = {
+	.is_enabled = _clk_pll141xx_is_enabled,
+	.enable = _clk_pll1419x_enable,
+	.disable = _clk_pll141xx_disable,
+	.set_rate = _clk_pll1419x_set_rate,
+	.get_rate = _clk_pll1419x_get_rate,
+};
+
+struct pwrcal_pll_ops pll1431x_ops = {
+	.is_enabled = _clk_pll1431x_is_enabled,
+	.enable = _clk_pll1431x_enable,
+	.disable = _clk_pll1431x_disable,
+	.set_rate = _clk_pll1431x_set_rate,
+	.get_rate = _clk_pll1431x_get_rate,
+};

drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-rae.c

@@ -0,0 +1,99 @@
+#include "../pwrcal-rae.h"
+#include "S5E8890-sfrbase.h"
+
+#ifdef PWRCAL_TARGET_LINUX
+
+struct v2p_sfr v2psfrmap[] = {
+	DEFINE_V2P(CMU_PERIS_BASE,	0x10040000),
+	DEFINE_V2P(CMU_TOP_BASE,	0x10570000),
+	DEFINE_V2P(CMU_CCORE_BASE,	0x105B0000),
+	DEFINE_V2P(CMU_MIF0_BASE,	0x10850000),
+	DEFINE_V2P(CMU_MIF1_BASE,	0x10950000),
+	DEFINE_V2P(CMU_MIF2_BASE,	0x10A50000),
+	DEFINE_V2P(CMU_MIF3_BASE,	0x10B50000),
+	DEFINE_V2P(CMU_FSYS0_BASE,	0x10E90000),
+	DEFINE_V2P(CMU_IMEM_BASE,	0x11060000),
+	DEFINE_V2P(CMU_AUD_BASE,	0x114C0000),
+	DEFINE_V2P(CMU_MNGS_BASE,	0x11800000),
+	DEFINE_V2P(CMU_APOLLO_BASE,	0x11900000),
+	DEFINE_V2P(CMU_BUS0_BASE,	0x13400000),
+	DEFINE_V2P(CMU_BUS1_BASE,	0x14800000),
+	DEFINE_V2P(CMU_PERIC0_BASE,	0x13610000),
+	DEFINE_V2P(CMU_DISP0_BASE,	0x13AD0000),
+	DEFINE_V2P(CMU_DISP1_BASE,	0x13F00000),
+	DEFINE_V2P(CMU_CAM0_LOCAL_BASE,	0x140F0000),
+	DEFINE_V2P(CMU_CAM0_BASE,	0x144D0000),
+	DEFINE_V2P(CMU_CAM1_LOCAL_BASE,	0x141F0000),
+	DEFINE_V2P(CMU_CAM1_BASE,	0x145D0000),
+	DEFINE_V2P(CMU_ISP0_LOCAL_BASE,	0x14290000),
+	DEFINE_V2P(CMU_ISP0_BASE,	0x146D0000),
+	DEFINE_V2P(CMU_ISP1_LOCAL_BASE,	0x142F0000),
+	DEFINE_V2P(CMU_ISP1_BASE,	0x147D0000),
+	DEFINE_V2P(CMU_G3D_BASE,	0x14AA0000),
+	DEFINE_V2P(CMU_PERIC1_BASE,	0x14C80000),
+	DEFINE_V2P(CMU_MSCL_BASE,	0x150D0000),
+	DEFINE_V2P(CMU_MFC_BASE,	0x15280000),
+	DEFINE_V2P(CMU_FSYS1_BASE,	0x156E0000),
+
+
+	DEFINE_V2P(PMU_PERIS_BASE,	0x10010000),
+	DEFINE_V2P(PMU_ALIVE_BASE,	0x105C0000),
+	DEFINE_V2P(PMU_CCORE_BASE,	0x105F0000),
+	DEFINE_V2P(PMU_MIF0_BASE,	0x10840000),
+	DEFINE_V2P(PMU_MIF1_BASE,	0x10940000),
+	DEFINE_V2P(PMU_MIF2_BASE,	0x10A40000),
+	DEFINE_V2P(PMU_MIF3_BASE,	0x10B40000),
+	DEFINE_V2P(PMU_FSYS0_BASE,	0x10E70000),
+	DEFINE_V2P(PMU_IMEM_BASE,	0x11070000),
+	DEFINE_V2P(PMU_AUD_BASE,	0x114D0000),
+	DEFINE_V2P(PMU_MNGS_BASE,	0x11820000),
+	DEFINE_V2P(PMU_APOLLO_BASE,	0x11920000),
+	DEFINE_V2P(PMU_BUS0_BASE,	0x13420000),
+	DEFINE_V2P(PMU_BUS1_BASE,	0x14820000),
+	DEFINE_V2P(PMU_PERIC0_BASE,	0x13600000),
+	DEFINE_V2P(PMU_DISP0_BASE,	0x13AE0000),
+	DEFINE_V2P(PMU_DISP1_BASE,	0x13F10000),
+	DEFINE_V2P(PMU_CAM0_BASE,	0x144E0000),
+	DEFINE_V2P(PMU_CAM1_BASE,	0x145E0000),
+	DEFINE_V2P(PMU_ISP0_BASE,	0x146E0000),
+	DEFINE_V2P(PMU_ISP1_BASE,	0x147E0000),
+	DEFINE_V2P(PMU_G3D_BASE,	0x14A40000),
+	DEFINE_V2P(PMU_PERIC1_BASE,	0x14C70000),
+	DEFINE_V2P(PMU_MSCL_BASE,	0x150F0000),
+	DEFINE_V2P(PMU_MFC_BASE,	0x15290000),
+	DEFINE_V2P(PMU_FSYS1_BASE,	0x156C0000),
+
+	DEFINE_V2P(DMC_MISC_CCORE_BASE,	0x10520000),
+	DEFINE_V2P(LPDDR4_PHY0_BASE,	0x10820000),
+
+	DEFINE_V2P(SYSREG_APOLLO_BASE,	0x11940000),
+	DEFINE_V2P(SYSREG_AUD_BASE,	0x11480000),
+	DEFINE_V2P(SYSREG_BUS0_BASE,	0x134C0000),
+	DEFINE_V2P(SYSREG_BUS1_BASE,	0x148C0000),
+	DEFINE_V2P(SYSREG_CAM0_BASE,	0x144F0000),
+	DEFINE_V2P(SYSREG_CAM1_BASE,	0x145F0000),
+	DEFINE_V2P(SYSREG_CCORE_BASE,	0x105D0000),
+	DEFINE_V2P(SYSREG_DISP0_BASE,	0x13A60000),
+	DEFINE_V2P(SYSREG_DISP1_BASE,	0x13F20000),
+	DEFINE_V2P(SYSREG_FSYS0_BASE,	0x10E50000),
+	DEFINE_V2P(SYSREG_FSYS1_BASE,	0x15600000),
+	DEFINE_V2P(SYSREG_G3D_BASE,	0x14AE0000),
+	DEFINE_V2P(SYSREG_IMEM_BASE,	0x11080000),
+	DEFINE_V2P(SYSREG_ISP0_BASE,	0x146F0000),
+	DEFINE_V2P(SYSREG_ISP1_BASE,	0x147F0000),
+	DEFINE_V2P(SYSREG_MFC_BASE,	0x152A0000),
+	DEFINE_V2P(SYSREG_MIF0_BASE,	0x10830000),
+	DEFINE_V2P(SYSREG_MIF1_BASE,	0x10930000),
+	DEFINE_V2P(SYSREG_MIF2_BASE,	0x10A30000),
+	DEFINE_V2P(SYSREG_MIF3_BASE,	0x10B30000),
+	DEFINE_V2P(SYSREG_MNGS_BASE,	0x11850000),
+	DEFINE_V2P(SYSREG_MSCL_BASE,	0x151C0000),
+	DEFINE_V2P(SYSREG_PERIC0_BASE,	0x136E0000),
+	DEFINE_V2P(SYSREG_PERIC1_BASE,	0x14C60000),
+	DEFINE_V2P(SYSREG_PERIS_BASE,	0x10050000),
+};
+
+int num_of_v2psfrmap = sizeof(v2psfrmap) / sizeof(v2psfrmap[0]);
+void *spinlock_enable_offset = (void *)PMU_PERIS_BASE;
+
+#endif

drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-sfrbase.h

@@ -0,0 +1,190 @@
+#ifndef __EXYNOS8890_SFRBASE_H__
+#define __EXYNOS8890_SFRBASE_H__
+
+#include "../pwrcal-env.h"
+
+#ifdef PWRCAL_TARGET_FW
+
+#define CMU_PERIS_BASE	0x10040000
+#define CMU_TOP_BASE	0x10570000
+#define CMU_CCORE_BASE	0x105B0000
+#define CMU_MIF0_BASE	0x10850000
+#define CMU_MIF1_BASE	0x10950000
+#define CMU_MIF2_BASE	0x10A50000
+#define CMU_MIF3_BASE	0x10B50000
+#define CMU_FSYS0_BASE	0x10E90000
+#define CMU_IMEM_BASE	0x11060000
+#define CMU_AUD_BASE	0x114C0000
+#define CMU_MNGS_BASE	0x11800000
+#define CMU_APOLLO_BASE	0x11900000
+#define CMU_BUS0_BASE	0x13400000
+#define CMU_BUS1_BASE	0x14800000
+#define CMU_PERIC0_BASE	0x13610000
+#define CMU_DISP0_BASE	0x13AD0000
+#define CMU_DISP1_BASE	0x13F00000
+#define CMU_CAM0_LOCAL_BASE	0x140F0000
+#define CMU_CAM0_BASE	0x144D0000
+#define CMU_CAM1_LOCAL_BASE	0x141F0000
+#define CMU_CAM1_BASE	0x145D0000
+#define CMU_ISP0_LOCAL_BASE	0x14290000
+#define CMU_ISP0_BASE	0x146D0000
+#define CMU_ISP1_LOCAL_BASE	0x142F0000
+#define CMU_ISP1_BASE	0x147D0000
+#define CMU_G3D_BASE	0x14AA0000
+#define CMU_PERIC1_BASE	0x14C80000
+#define CMU_MSCL_BASE	0x150D0000
+#define CMU_MFC_BASE	0x15280000
+#define CMU_FSYS1_BASE	0x156E0000
+
+
+#define PMU_PERIS_BASE	0x10010000
+#define PMU_ALIVE_BASE	0x105C0000
+#define PMU_CCORE_BASE	0x105F0000
+#define PMU_MIF0_BASE	0x10840000
+#define PMU_MIF1_BASE	0x10940000
+#define PMU_MIF2_BASE	0x10A40000
+#define PMU_MIF3_BASE	0x10B40000
+#define PMU_FSYS0_BASE	0x10E70000
+#define PMU_IMEM_BASE	0x11070000
+#define PMU_AUD_BASE	0x114D0000
+#define PMU_MNGS_BASE	0x11820000
+#define PMU_APOLLO_BASE	0x11920000
+#define PMU_BUS0_BASE	0x13420000
+#define PMU_BUS1_BASE	0x14820000
+#define PMU_PERIC0_BASE	0x13600000
+#define PMU_DISP0_BASE	0x13AE0000
+#define PMU_DISP1_BASE	0x13F10000
+#define PMU_CAM0_BASE	0x144E0000
+#define PMU_CAM1_BASE	0x145E0000
+#define PMU_ISP0_BASE	0x146E0000
+#define PMU_ISP1_BASE	0x147E0000
+#define PMU_G3D_BASE	0x14A40000
+#define PMU_PERIC1_BASE	0x14C70000
+#define PMU_MSCL_BASE	0x150F0000
+#define PMU_MFC_BASE	0x15290000
+#define PMU_FSYS1_BASE	0x156C0000
+
+#define DMC_MISC_CCORE_BASE	0x10520000
+#define LPDDR4_PHY0_BASE	0x10820000
+
+#define SYSREG_APOLLO_BASE	0x11940000
+#define SYSREG_AUD_BASE	0x11480000
+#define SYSREG_BUS0_BASE	0x134C0000
+#define SYSREG_BUS1_BASE	0x148C0000
+#define SYSREG_CAM0_BASE	0x144F0000
+#define SYSREG_CAM1_BASE	0x145F0000
+#define SYSREG_CCORE_BASE	0x105D0000
+#define SYSREG_DISP0_BASE	0x13A60000
+#define SYSREG_DISP1_BASE	0x13F20000
+#define SYSREG_FSYS0_BASE	0x10E50000
+#define SYSREG_FSYS1_BASE	0x15600000
+#define SYSREG_G3D_BASE	0x14AE0000
+#define SYSREG_IMEM_BASE	0x11080000
+#define SYSREG_ISP0_BASE	0x146F0000
+#define SYSREG_ISP1_BASE	0x147F0000
+#define SYSREG_MFC_BASE	0x152A0000
+#define SYSREG_MIF0_BASE	0x10830000
+#define SYSREG_MIF1_BASE	0x10930000
+#define SYSREG_MIF2_BASE	0x10A30000
+#define SYSREG_MIF3_BASE	0x10B30000
+#define SYSREG_MNGS_BASE	0x11850000
+#define SYSREG_MSCL_BASE	0x151C0000
+#define SYSREG_PERIC0_BASE	0x136E0000
+#define SYSREG_PERIC1_BASE	0x14C60000
+#define SYSREG_PERIS_BASE	0x10050000
+
+#endif
+
+#ifdef PWRCAL_TARGET_LINUX
+
+#define CMU_PERIS_BASE	0x00010000
+#define CMU_TOP_BASE	0x00020000
+#define CMU_CCORE_BASE	0x00030000
+#define CMU_MIF0_BASE	0x00040000
+#define CMU_MIF1_BASE	0x00050000
+#define CMU_MIF2_BASE	0x00060000
+#define CMU_MIF3_BASE	0x00070000
+#define CMU_FSYS0_BASE	0x00080000
+#define CMU_IMEM_BASE	0x00090000
+#define CMU_AUD_BASE	0x000A0000
+#define CMU_MNGS_BASE	0x000B0000
+#define CMU_APOLLO_BASE	0x000C0000
+#define CMU_BUS0_BASE	0x000D0000
+#define CMU_BUS1_BASE	0x000E0000
+#define CMU_PERIC0_BASE	0x000F0000
+#define CMU_DISP0_BASE	0x00100000
+#define CMU_DISP1_BASE	0x00110000
+#define CMU_CAM0_LOCAL_BASE	0x00120000
+#define CMU_CAM0_BASE	0x00130000
+#define CMU_CAM1_LOCAL_BASE	0x00140000
+#define CMU_CAM1_BASE	0x00150000
+#define CMU_ISP0_LOCAL_BASE	0x00160000
+#define CMU_ISP0_BASE	0x00170000
+#define CMU_ISP1_LOCAL_BASE	0x00180000
+#define CMU_ISP1_BASE	0x00190000
+#define CMU_G3D_BASE	0x001A0000
+#define CMU_PERIC1_BASE	0x001B0000
+#define CMU_MSCL_BASE	0x001C0000
+#define CMU_MFC_BASE	0x001D0000
+#define CMU_FSYS1_BASE	0x001E0000
+
+
+#define PMU_PERIS_BASE	0x001F0000
+#define PMU_ALIVE_BASE	0x00200000
+#define PMU_CCORE_BASE	0x00210000
+#define PMU_MIF0_BASE	0x00220000
+#define PMU_MIF1_BASE	0x00230000
+#define PMU_MIF2_BASE	0x00240000
+#define PMU_MIF3_BASE	0x00250000
+#define PMU_FSYS0_BASE	0x00260000
+#define PMU_IMEM_BASE	0x00270000
+#define PMU_AUD_BASE	0x00280000
+#define PMU_MNGS_BASE	0x00290000
+#define PMU_APOLLO_BASE	0x002A0000
+#define PMU_BUS0_BASE	0x002B0000
+#define PMU_BUS1_BASE	0x002C0000
+#define PMU_PERIC0_BASE	0x002D0000
+#define PMU_DISP0_BASE	0x002E0000
+#define PMU_DISP1_BASE	0x002F0000
+#define PMU_CAM0_BASE	0x00300000
+#define PMU_CAM1_BASE	0x00310000
+#define PMU_ISP0_BASE	0x00320000
+#define PMU_ISP1_BASE	0x00330000
+#define PMU_G3D_BASE	0x00340000
+#define PMU_PERIC1_BASE	0x00350000
+#define PMU_MSCL_BASE	0x00360000
+#define PMU_MFC_BASE	0x00370000
+#define PMU_FSYS1_BASE	0x00380000
+
+#define DMC_MISC_CCORE_BASE	0x00390000
+#define LPDDR4_PHY0_BASE	0x003A0000
+
+#define SYSREG_APOLLO_BASE	0x003B0000
+#define SYSREG_AUD_BASE	0x003C0000
+#define SYSREG_BUS0_BASE	0x003D0000
+#define SYSREG_BUS1_BASE	0x003E0000
+#define SYSREG_CAM0_BASE	0x003F0000
+#define SYSREG_CAM1_BASE	0x00400000
+#define SYSREG_CCORE_BASE	0x00410000
+#define SYSREG_DISP0_BASE	0x00420000
+#define SYSREG_DISP1_BASE	0x00430000
+#define SYSREG_FSYS0_BASE	0x00440000
+#define SYSREG_FSYS1_BASE	0x00450000
+#define SYSREG_G3D_BASE	0x00460000
+#define SYSREG_IMEM_BASE	0x00470000
+#define SYSREG_ISP0_BASE	0x00480000
+#define SYSREG_ISP1_BASE	0x00490000
+#define SYSREG_MFC_BASE	0x004A0000
+#define SYSREG_MIF0_BASE	0x004B0000
+#define SYSREG_MIF1_BASE	0x004C0000
+#define SYSREG_MIF2_BASE	0x004D0000
+#define SYSREG_MIF3_BASE	0x004E0000
+#define SYSREG_MNGS_BASE	0x004F0000
+#define SYSREG_MSCL_BASE	0x00500000
+#define SYSREG_PERIC0_BASE	0x00510000
+#define SYSREG_PERIC1_BASE	0x00520000
+#define SYSREG_PERIS_BASE	0x00530000
+
+#endif
+
+#endif

drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-vclk-internal.h

@@ -0,0 +1,406 @@
+#ifndef __EXYNOS8890_VCLKS_H__
+#define __EXYNOS8890_VCLKS_H__
+
+#include "../pwrcal-vclk.h"
+#include "../pwrcal-pmu.h"
+#include "S5E8890-vclk.h"
+
+
+GRPGATE_EXTERN(gate_apollo_ppmu)
+GRPGATE_EXTERN(gate_apollo_bts)
+GRPGATE_EXTERN(gate_mngs_ppmu)
+GRPGATE_EXTERN(gate_mngs_bts)
+GRPGATE_EXTERN(gate_aud_common)
+GRPGATE_EXTERN(gate_aud_lpass)
+GRPGATE_EXTERN(gate_aud_mi2s)
+GRPGATE_EXTERN(gate_aud_pcm)
+GRPGATE_EXTERN(gate_aud_uart)
+GRPGATE_EXTERN(gate_aud_dma)
+GRPGATE_EXTERN(gate_aud_slimbus)
+GRPGATE_EXTERN(gate_aud_sysmmu)
+GRPGATE_EXTERN(gate_aud_ppmu)
+GRPGATE_EXTERN(gate_aud_bts)
+GRPGATE_EXTERN(gate_aud_sclk_mi2s)
+GRPGATE_EXTERN(gate_aud_sclk_pcm)
+GRPGATE_EXTERN(gate_aud_sclk_slimbus)
+GRPGATE_EXTERN(gate_bus0_display)
+GRPGATE_EXTERN(gate_bus0_cam)
+GRPGATE_EXTERN(gate_bus0_fsys1)
+GRPGATE_EXTERN(gate_bus1_mfc)
+GRPGATE_EXTERN(gate_bus1_mscl)
+GRPGATE_EXTERN(gate_bus1_fsys0)
+GRPGATE_EXTERN(gate_cam0_common)
+GRPGATE_EXTERN(gate_cam0_csis0)
+GRPGATE_EXTERN(gate_cam0_csis1)
+GRPGATE_EXTERN(gate_cam0_fimc_bns)
+GRPGATE_EXTERN(gate_cam0_fimc_3aa0)
+GRPGATE_EXTERN(gate_cam0_fimc_3aa1)
+GRPGATE_EXTERN(gate_cam0_hpm)
+GRPGATE_EXTERN(gate_cam0_sysmmu)
+GRPGATE_EXTERN(gate_cam0_ppmu)
+GRPGATE_EXTERN(gate_cam0_bts)
+GRPGATE_EXTERN(gate_cam0_phyclk_hs0_csis0_rx_byte)
+GRPGATE_EXTERN(gate_cam0_phyclk_hs1_csis0_rx_byte)
+GRPGATE_EXTERN(gate_cam0_phyclk_hs2_csis0_rx_byte)
+GRPGATE_EXTERN(gate_cam0_phyclk_hs3_csis0_rx_byte)
+GRPGATE_EXTERN(gate_cam0_phyclk_hs0_csis1_rx_byte)
+GRPGATE_EXTERN(gate_cam0_phyclk_hs1_csis1_rx_byte)
+GRPGATE_EXTERN(gate_cam1_common)
+GRPGATE_EXTERN(gate_cam1_isp_cpu_gic_common)
+GRPGATE_EXTERN(gate_cam1_isp_cpu)
+GRPGATE_EXTERN(gate_cam1_gic_is)
+GRPGATE_EXTERN(gate_cam1_csis2)
+GRPGATE_EXTERN(gate_cam1_csis3)
+GRPGATE_EXTERN(gate_cam1_fimc_vra)
+GRPGATE_EXTERN(gate_cam1_mc_scaler)
+GRPGATE_EXTERN(gate_cam1_i2c0_isp)
+GRPGATE_EXTERN(gate_cam1_i2c1_isp)
+GRPGATE_EXTERN(gate_cam1_i2c2_isp)
+GRPGATE_EXTERN(gate_cam1_i2c3_isp)
+GRPGATE_EXTERN(gate_cam1_wdt_isp)
+GRPGATE_EXTERN(gate_cam1_mcuctl_isp)
+GRPGATE_EXTERN(gate_cam1_uart_isp)
+GRPGATE_EXTERN(gate_cam1_sclk_uart_isp)
+GRPGATE_EXTERN(gate_cam1_spi0_isp)
+GRPGATE_EXTERN(gate_cam1_spi1_isp)
+GRPGATE_EXTERN(gate_cam1_pdma_isp)
+GRPGATE_EXTERN(gate_cam1_pwm_isp)
+GRPGATE_EXTERN(gate_cam1_sclk_pwm_isp)
+GRPGATE_EXTERN(gate_cam1_sysmmu)
+GRPGATE_EXTERN(gate_cam1_ppmu)
+GRPGATE_EXTERN(gate_cam1_bts)
+GRPGATE_EXTERN(gate_cam1_phyclk_hs0_csis2_rx_byte)
+GRPGATE_EXTERN(gate_cam1_phyclk_hs1_csis2_rx_byte)
+GRPGATE_EXTERN(gate_cam1_phyclk_hs2_csis2_rx_byte)
+GRPGATE_EXTERN(gate_cam1_phyclk_hs3_csis2_rx_byte)
+GRPGATE_EXTERN(gate_cam1_phyclk_hs0_csis3_rx_byte)
+GRPGATE_EXTERN(gate_disp0_common)
+GRPGATE_EXTERN(gate_disp0_decon0)
+GRPGATE_EXTERN(gate_disp0_dsim0)
+GRPGATE_EXTERN(gate_disp0_dsim1)
+GRPGATE_EXTERN(gate_disp0_dsim2)
+GRPGATE_EXTERN(gate_disp0_hdmi)
+GRPGATE_EXTERN(gate_disp0_dp)
+GRPGATE_EXTERN(gate_disp0_hpm_apbif_disp0)
+GRPGATE_EXTERN(gate_disp0_sysmmu)
+GRPGATE_EXTERN(gate_disp0_ppmu)
+GRPGATE_EXTERN(gate_disp0_bts)
+GRPGATE_EXTERN(gate_disp0_phyclk_hdmiphy_tmds_20b_clko)
+GRPGATE_EXTERN(gate_disp0_phyclk_hdmiphy_tmds_10b_clko)
+GRPGATE_EXTERN(gate_disp0_phyclk_hdmiphy_pixel_clko)
+GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy0_rxclkesc0)
+GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy0_bitclkdiv8)
+GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy1_rxclkesc0)
+GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy1_bitclkdiv8)
+GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy2_rxclkesc0)
+GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy2_bitclkdiv8)
+GRPGATE_EXTERN(gate_disp0_phyclk_dpphy_ch0_txd_clk)
+GRPGATE_EXTERN(gate_disp0_phyclk_dpphy_ch1_txd_clk)
+GRPGATE_EXTERN(gate_disp0_phyclk_dpphy_ch2_txd_clk)
+GRPGATE_EXTERN(gate_disp0_phyclk_dpphy_ch3_txd_clk)
+GRPGATE_EXTERN(gate_disp0_oscclk_dp_i_clk_24m)
+GRPGATE_EXTERN(gate_disp0_oscclk_i_dptx_phy_i_ref_clk_24m)
+GRPGATE_EXTERN(gate_disp0_oscclk_i_mipi_dphy_m1s0_m_xi)
+GRPGATE_EXTERN(gate_disp0_oscclk_i_mipi_dphy_m4s0_m_xi)
+GRPGATE_EXTERN(gate_disp0_oscclk_i_mipi_dphy_m4s4_m_xi)
+GRPGATE_EXTERN(gate_disp1_common)
+GRPGATE_EXTERN(gate_disp1_decon1)
+GRPGATE_EXTERN(gate_disp1_hpmdisp1)
+GRPGATE_EXTERN(gate_disp1_sysmmu)
+GRPGATE_EXTERN(gate_disp1_ppmu)
+GRPGATE_EXTERN(gate_disp1_bts)
+GRPGATE_EXTERN(gate_fsys0_common)
+GRPGATE_EXTERN(gate_fsys0_usbdrd_etrusb_common)
+GRPGATE_EXTERN(gate_fsys0_usbdrd30)
+GRPGATE_EXTERN(gate_fsys0_etr_usb)
+GRPGATE_EXTERN(gate_fsys0_usbhost20)
+GRPGATE_EXTERN(gate_fsys0_mmc0_ufs_common)
+GRPGATE_EXTERN(gate_fsys0_mmc0)
+GRPGATE_EXTERN(gate_fsys0_ufs_linkemedded)
+GRPGATE_EXTERN(gate_fsys0_pdma_common)
+GRPGATE_EXTERN(gate_fsys0_pdma0)
+GRPGATE_EXTERN(gate_fsys0_pdmas)
+GRPGATE_EXTERN(gate_fsys0_ppmu)
+GRPGATE_EXTERN(gate_fsys0_bts)
+GRPGATE_EXTERN(gate_fsys0_hpm)
+GRPGATE_EXTERN(gate_fsys0_phyclk_usbdrd30_udrd30_phyclock)
+GRPGATE_EXTERN(gate_fsys0_phyclk_usbdrd30_udrd30_pipe_pclk)
+GRPGATE_EXTERN(gate_fsys0_phyclk_ufs_tx0_symbol)
+GRPGATE_EXTERN(gate_fsys0_phyclk_ufs_rx0_symbol)
+GRPGATE_EXTERN(gate_fsys0_phyclk_usbhost20_phyclock)
+GRPGATE_EXTERN(gate_fsys0_phyclk_usbhost20_freeclk)
+GRPGATE_EXTERN(gate_fsys0_phyclk_usbhost20_clk48mohci)
+GRPGATE_EXTERN(gate_fsys0_phyclk_usbhost20phy_ref_clk)
+GRPGATE_EXTERN(gate_fsys0_phyclk_ufs_rx_pwm_clk)
+GRPGATE_EXTERN(gate_fsys0_phyclk_ufs_tx_pwm_clk)
+GRPGATE_EXTERN(gate_fsys0_phyclk_ufs_refclk_out_soc)
+GRPGATE_EXTERN(gate_fsys1_common)
+GRPGATE_EXTERN(gate_fsys1_mmc2_ufs_common)
+GRPGATE_EXTERN(gate_fsys1_mmc2)
+GRPGATE_EXTERN(gate_fsys1_ufs20_sdcard)
+GRPGATE_EXTERN(gate_fsys1_sromc)
+GRPGATE_EXTERN(gate_fsys1_pciewifi0)
+GRPGATE_EXTERN(gate_fsys1_pciewifi1)
+GRPGATE_EXTERN(gate_fsys1_ppmu)
+GRPGATE_EXTERN(gate_fsys1_bts)
+GRPGATE_EXTERN(gate_fsys1_hpm)
+GRPGATE_EXTERN(gate_fsys1_phyclk_ufs_link_sdcard_tx0_symbol)
+GRPGATE_EXTERN(gate_fsys1_phyclk_ufs_link_sdcard_rx0_symbol)
+GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi0_tx0)
+GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi0_rx0)
+GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi1_tx0)
+GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi1_rx0)
+GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi0_dig_refclk)
+GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi1_dig_refclk)
+GRPGATE_EXTERN(gate_fsys1_phyclk_ufs_link_sdcard_rx_pwm_clk)
+GRPGATE_EXTERN(gate_fsys1_phyclk_ufs_link_sdcard_tx_pwm_clk)
+GRPGATE_EXTERN(gate_fsys1_phyclk_ufs_link_sdcard_refclk_out_soc)
+GRPGATE_EXTERN(gate_g3d_common)
+GRPGATE_EXTERN(gate_g3d_g3d_common)
+GRPGATE_EXTERN(gate_g3d_g3d)
+GRPGATE_EXTERN(gate_g3d_iram_path_test)
+GRPGATE_EXTERN(gate_g3d_ppmu)
+GRPGATE_EXTERN(gate_g3d_bts)
+GRPGATE_EXTERN(gate_imem_common)
+GRPGATE_EXTERN(gate_imem_apm_sss_rtic_mc_common)
+GRPGATE_EXTERN(gate_imem_apm)
+GRPGATE_EXTERN(gate_imem_sss)
+GRPGATE_EXTERN(gate_imem_rtic)
+GRPGATE_EXTERN(gate_imem_mc)
+GRPGATE_EXTERN(gate_imem_intmem)
+GRPGATE_EXTERN(gate_imem_intmem_alv)
+GRPGATE_EXTERN(gate_imem_gic400)
+GRPGATE_EXTERN(gate_imem_ppmu)
+GRPGATE_EXTERN(gate_isp0_common)
+GRPGATE_EXTERN(gate_isp0_fimc_isp0)
+GRPGATE_EXTERN(gate_isp0_fimc_tpu)
+GRPGATE_EXTERN(gate_isp0_sysmmu)
+GRPGATE_EXTERN(gate_isp0_ppmu)
+GRPGATE_EXTERN(gate_isp0_bts)
+GRPGATE_EXTERN(gate_isp1_fimc_isp1)
+GRPGATE_EXTERN(gate_isp1_sysmmu)
+GRPGATE_EXTERN(gate_isp1_ppmu)
+GRPGATE_EXTERN(gate_isp1_bts)
+GRPGATE_EXTERN(gate_mfc_common)
+GRPGATE_EXTERN(gate_mfc_mfc)
+GRPGATE_EXTERN(gate_mfc_hpm)
+GRPGATE_EXTERN(gate_mfc_sysmmu)
+GRPGATE_EXTERN(gate_mfc_ppmu)
+GRPGATE_EXTERN(gate_mscl_common)
+GRPGATE_EXTERN(gate_mscl_mscl0_jpeg_common)
+GRPGATE_EXTERN(gate_mscl_mscl0)
+GRPGATE_EXTERN(gate_mscl_jpeg)
+GRPGATE_EXTERN(gate_mscl_mscl1_g2d_common)
+GRPGATE_EXTERN(gate_mscl_mscl1)
+GRPGATE_EXTERN(gate_mscl_g2d)
+GRPGATE_EXTERN(gate_mscl_sysmmu)
+GRPGATE_EXTERN(gate_mscl_ppmu)
+GRPGATE_EXTERN(gate_mscl_bts)
+GRPGATE_EXTERN(gate_peric0_hsi2c0)
+GRPGATE_EXTERN(gate_peric0_hsi2c1)
+GRPGATE_EXTERN(gate_peric0_hsi2c4)
+GRPGATE_EXTERN(gate_peric0_hsi2c5)
+GRPGATE_EXTERN(gate_peric0_hsi2c9)
+GRPGATE_EXTERN(gate_peric0_hsi2c10)
+GRPGATE_EXTERN(gate_peric0_hsi2c11)
+GRPGATE_EXTERN(gate_peric0_uart0)
+GRPGATE_EXTERN(gate_peric0_adcif)
+GRPGATE_EXTERN(gate_peric0_pwm)
+GRPGATE_EXTERN(gate_peric0_sclk_pwm)
+GRPGATE_EXTERN(gate_peric1_hsi2c_common)
+GRPGATE_EXTERN(gate_peric1_hsi2c2)
+GRPGATE_EXTERN(gate_peric1_hsi2c3)
+GRPGATE_EXTERN(gate_peric1_hsi2c6)
+GRPGATE_EXTERN(gate_peric1_hsi2c7)
+GRPGATE_EXTERN(gate_peric1_hsi2c8)
+GRPGATE_EXTERN(gate_peric1_hsi2c12)
+GRPGATE_EXTERN(gate_peric1_hsi2c13)
+GRPGATE_EXTERN(gate_peric1_hsi2c14)
+GRPGATE_EXTERN(gate_peric1_spi_i2s_pcm1_spdif_common)
+GRPGATE_EXTERN(gate_peric1_uart1)
+GRPGATE_EXTERN(gate_peric1_uart2)
+GRPGATE_EXTERN(gate_peric1_uart3)
+GRPGATE_EXTERN(gate_peric1_uart4)
+GRPGATE_EXTERN(gate_peric1_uart5)
+GRPGATE_EXTERN(gate_peric1_spi0)
+GRPGATE_EXTERN(gate_peric1_spi1)
+GRPGATE_EXTERN(gate_peric1_spi2)
+GRPGATE_EXTERN(gate_peric1_spi3)
+GRPGATE_EXTERN(gate_peric1_spi4)
+GRPGATE_EXTERN(gate_peric1_spi5)
+GRPGATE_EXTERN(gate_peric1_spi6)
+GRPGATE_EXTERN(gate_peric1_spi7)
+GRPGATE_EXTERN(gate_peric1_i2s1)
+GRPGATE_EXTERN(gate_peric1_pcm1)
+GRPGATE_EXTERN(gate_peric1_spdif)
+GRPGATE_EXTERN(gate_peric1_gpio_nfc)
+GRPGATE_EXTERN(gate_peric1_gpio_touch)
+GRPGATE_EXTERN(gate_peric1_gpio_fp)
+GRPGATE_EXTERN(gate_peric1_gpio_ese)
+GRPGATE_EXTERN(gate_peris_sfr_apbif_hdmi_cec)
+GRPGATE_EXTERN(gate_peris_hpm)
+GRPGATE_EXTERN(gate_peris_mct)
+GRPGATE_EXTERN(gate_peris_wdt_mngs)
+GRPGATE_EXTERN(gate_peris_wdt_apollo)
+GRPGATE_EXTERN(gate_peris_sysreg_peris)
+GRPGATE_EXTERN(gate_peris_monocnt_apbif)
+GRPGATE_EXTERN(gate_peris_rtc_apbif)
+GRPGATE_EXTERN(gate_peris_top_rtc)
+GRPGATE_EXTERN(gate_peris_otp_con_top)
+GRPGATE_EXTERN(gate_peris_chipid)
+GRPGATE_EXTERN(gate_peris_tmu)
+
+M1D1G1_EXTERN(sclk_decon0_eclk0)
+M1D1G1_EXTERN(sclk_decon0_vclk0)
+M1D1G1_EXTERN(sclk_decon0_vclk1)
+M1D1G1_EXTERN(sclk_hdmi_audio)
+M1D1G1_EXTERN(sclk_decon1_eclk0)
+M1D1G1_EXTERN(sclk_decon1_eclk1)
+M1D1G1_EXTERN(sclk_usbdrd30)
+M1D1G1_EXTERN(sclk_mmc0)
+M1D1G1_EXTERN(sclk_ufsunipro20)
+M1D1G1_EXTERN(sclk_phy24m)
+M1D1G1_EXTERN(sclk_ufsunipro_cfg)
+M1D1G1_EXTERN(sclk_mmc2)
+M1D1G1_EXTERN(sclk_ufsunipro20_sdcard)
+M1D1G1_EXTERN(sclk_pcie_phy)
+M1D1G1_EXTERN(sclk_ufsunipro_sdcard_cfg)
+M1D1G1_EXTERN(sclk_uart0)
+M1D1G1_EXTERN(sclk_spi0)
+M1D1G1_EXTERN(sclk_spi1)
+M1D1G1_EXTERN(sclk_spi2)
+M1D1G1_EXTERN(sclk_spi3)
+M1D1G1_EXTERN(sclk_spi4)
+M1D1G1_EXTERN(sclk_spi5)
+M1D1G1_EXTERN(sclk_spi6)
+M1D1G1_EXTERN(sclk_spi7)
+M1D1G1_EXTERN(sclk_uart1)
+M1D1G1_EXTERN(sclk_uart2)
+M1D1G1_EXTERN(sclk_uart3)
+M1D1G1_EXTERN(sclk_uart4)
+M1D1G1_EXTERN(sclk_uart5)
+M1D1G1_EXTERN(sclk_promise_int)
+M1D1G1_EXTERN(sclk_promise_disp)
+M1D1G1_EXTERN(sclk_ap2cp_mif_pll_out)
+M1D1G1_EXTERN(sclk_isp_spi0)
+M1D1G1_EXTERN(sclk_isp_spi1)
+M1D1G1_EXTERN(sclk_isp_uart)
+M1D1G1_EXTERN(sclk_isp_sensor0)
+M1D1G1_EXTERN(sclk_isp_sensor1)
+M1D1G1_EXTERN(sclk_isp_sensor2)
+M1D1G1_EXTERN(sclk_isp_sensor3)
+M1D1G1_EXTERN(sclk_decon0_eclk0_local)
+M1D1G1_EXTERN(sclk_decon0_vclk0_local)
+M1D1G1_EXTERN(sclk_decon0_vclk1_local)
+M1D1G1_EXTERN(sclk_decon1_eclk0_local)
+M1D1G1_EXTERN(sclk_decon1_eclk1_local)
+
+P1_EXTERN(p1_disp_pll)
+P1_EXTERN(p1_aud_pll)
+P1_EXTERN(p1_mfc_pll)
+
+D1_EXTERN(d1_sclk_i2s_local)
+D1_EXTERN(d1_sclk_pcm_local)
+D1_EXTERN(d1_sclk_slimbus)
+D1_EXTERN(d1_sclk_cp_i2s)
+D1_EXTERN(d1_sclk_asrc)
+
+PXMXDX_EXTERN(pxmxdx_top)
+PXMXDX_EXTERN(pxmxdx_mfc)
+PXMXDX_EXTERN(pxmxdx_mscl)
+PXMXDX_EXTERN(pxmxdx_imem)
+PXMXDX_EXTERN(pxmxdx_fsys0)
+PXMXDX_EXTERN(pxmxdx_fsys1)
+PXMXDX_EXTERN(pxmxdx_disp0)
+PXMXDX_EXTERN(pxmxdx_disp1)
+PXMXDX_EXTERN(pxmxdx_aud)
+PXMXDX_EXTERN(pxmxdx_aud_cp)
+PXMXDX_EXTERN(pxmxdx_isp0_isp0)
+PXMXDX_EXTERN(pxmxdx_isp0_tpu)
+PXMXDX_EXTERN(pxmxdx_isp0_trex)
+PXMXDX_EXTERN(pxmxdx_isp1_isp1)
+PXMXDX_EXTERN(pxmxdx_cam0_csis0)
+PXMXDX_EXTERN(pxmxdx_cam0_csis1)
+PXMXDX_EXTERN(pxmxdx_cam0_csis2)
+PXMXDX_EXTERN(pxmxdx_cam0_csis3)
+PXMXDX_EXTERN(pxmxdx_cam0_3aa0)
+PXMXDX_EXTERN(pxmxdx_cam0_3aa1)
+PXMXDX_EXTERN(pxmxdx_cam0_trex)
+PXMXDX_EXTERN(pxmxdx_cam1_arm)
+PXMXDX_EXTERN(pxmxdx_cam1_vra)
+PXMXDX_EXTERN(pxmxdx_cam1_trex)
+PXMXDX_EXTERN(pxmxdx_cam1_bus)
+PXMXDX_EXTERN(pxmxdx_cam1_peri)
+PXMXDX_EXTERN(pxmxdx_cam1_csis2)
+PXMXDX_EXTERN(pxmxdx_cam1_csis3)
+PXMXDX_EXTERN(pxmxdx_cam1_scl)
+PXMXDX_EXTERN(pxmxdx_oscclk_nfc)
+PXMXDX_EXTERN(pxmxdx_oscclk_aud)
+
+UMUX_EXTERN(umux_bus0_aclk_bus0_528)
+UMUX_EXTERN(umux_bus0_aclk_bus0_200)
+UMUX_EXTERN(umux_bus1_aclk_bus1_528)
+UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs0_csis0_user)
+UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs1_csis0_user)
+UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs2_csis0_user)
+UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs3_csis0_user)
+UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs0_csis1_user)
+UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs1_csis1_user)
+UMUX_EXTERN(umux_cam1_phyclk_rxbyteclkhs0_csis2_user)
+UMUX_EXTERN(umux_cam1_phyclk_rxbyteclkhs1_csis2_user)
+UMUX_EXTERN(umux_cam1_phyclk_rxbyteclkhs2_csis2_user)
+UMUX_EXTERN(umux_cam1_phyclk_rxbyteclkhs3_csis2_user)
+UMUX_EXTERN(umux_cam1_phyclk_rxbyteclkhs0_csis3_user)
+UMUX_EXTERN(umux_disp0_phyclk_hdmiphy_pixel_clko_user)
+UMUX_EXTERN(umux_disp0_phyclk_hdmiphy_tmds_clko_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy0_rxclkesc0_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy0_bitclkdiv2_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy0_bitclkdiv8_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy1_rxclkesc0_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy1_bitclkdiv2_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy1_bitclkdiv8_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy2_rxclkesc0_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy2_bitclkdiv2_user)
+UMUX_EXTERN(umux_disp0_phyclk_mipidphy2_bitclkdiv8_user)
+UMUX_EXTERN(umux_disp0_phyclk_dpphy_ch0_txd_clk_user)
+UMUX_EXTERN(umux_disp0_phyclk_dpphy_ch1_txd_clk_user)
+UMUX_EXTERN(umux_disp0_phyclk_dpphy_ch2_txd_clk_user)
+UMUX_EXTERN(umux_disp0_phyclk_dpphy_ch3_txd_clk_user)
+UMUX_EXTERN(umux_disp1_phyclk_mipidphy0_bitclkdiv2_user)
+UMUX_EXTERN(umux_disp1_phyclk_mipidphy1_bitclkdiv2_user)
+UMUX_EXTERN(umux_disp1_phyclk_mipidphy2_bitclkdiv2_user)
+UMUX_EXTERN(umux_disp1_phyclk_disp1_hdmiphy_pixel_clko_user)
+UMUX_EXTERN(umux_fsys0_phyclk_usbdrd30_udrd30_phyclock_user)
+UMUX_EXTERN(umux_fsys0_phyclk_usbdrd30_udrd30_pipe_pclk_user)
+UMUX_EXTERN(umux_fsys0_phyclk_ufs_tx0_symbol_user)
+UMUX_EXTERN(umux_fsys0_phyclk_ufs_rx0_symbol_user)
+UMUX_EXTERN(umux_fsys0_phyclk_usbhost20_phyclock_user)
+UMUX_EXTERN(umux_fsys0_phyclk_usbhost20_freeclk_user)
+UMUX_EXTERN(umux_fsys0_phyclk_usbhost20_clk48mohci_user)
+UMUX_EXTERN(umux_fsys0_phyclk_usbhost20phy_ref_clk)
+UMUX_EXTERN(umux_fsys0_phyclk_ufs_rx_pwm_clk_user)
+UMUX_EXTERN(umux_fsys0_phyclk_ufs_tx_pwm_clk_user)
+UMUX_EXTERN(umux_fsys0_phyclk_ufs_refclk_out_soc_user)
+UMUX_EXTERN(umux_fsys1_phyclk_ufs_link_sdcard_tx0_symbol_user)
+UMUX_EXTERN(umux_fsys1_phyclk_ufs_link_sdcard_rx0_symbol_user)
+UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi0_tx0_user)
+UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi0_rx0_user)
+UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi1_tx0_user)
+UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi1_rx0_user)
+UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi0_dig_refclk_user)
+UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi1_dig_refclk_user)
+UMUX_EXTERN(umux_fsys1_phyclk_ufs_link_sdcard_rx_pwm_clk_user)
+UMUX_EXTERN(umux_fsys1_phyclk_ufs_link_sdcard_tx_pwm_clk_user)
+UMUX_EXTERN(umux_fsys1_phyclk_ufs_link_sdcard_refclk_out_soc_user)
+
+DFS_EXTERN(dvfs_big)
+DFS_EXTERN(dvfs_little)
+DFS_EXTERN(dvfs_g3d)
+DFS_EXTERN(dvfs_mif)
+DFS_EXTERN(dvfs_int)
+DFS_EXTERN(dvfs_cam)
+DFS_EXTERN(dvfs_disp)
+
+
+
+#endif

drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-vclk.h

@@ -0,0 +1,422 @@
+#ifndef __EXYNOS8890_VCLK_H__
+#define __EXYNOS8890_VCLK_H__
+
+enum {
+	invalid_vclk_id = 0x00000FFF,
+
+	gate_apollo_ppmu = 0x0A000000,
+	gate_apollo_bts,
+	gate_mngs_ppmu,
+	gate_mngs_bts,
+	gate_aud_common,
+	gate_aud_lpass,
+	gate_aud_mi2s,
+	gate_aud_pcm,
+	gate_aud_uart,
+	gate_aud_dma,
+	gate_aud_slimbus,
+	gate_aud_sysmmu,
+	gate_aud_ppmu,
+	gate_aud_bts,
+	gate_aud_sclk_mi2s,
+	gate_aud_sclk_pcm,
+	gate_aud_sclk_slimbus,
+	gate_bus0_display,
+	gate_bus0_cam,
+	gate_bus0_fsys1,
+	gate_bus1_mfc,
+	gate_bus1_mscl,
+	gate_bus1_fsys0,
+	gate_cam0_common,
+	gate_cam0_csis0,
+	gate_cam0_csis1,
+	gate_cam0_fimc_bns,
+	gate_cam0_fimc_3aa0,
+	gate_cam0_fimc_3aa1,
+	gate_cam0_hpm,
+	gate_cam0_sysmmu,
+	gate_cam0_ppmu,
+	gate_cam0_bts,
+	gate_cam0_phyclk_hs0_csis0_rx_byte,
+	gate_cam0_phyclk_hs1_csis0_rx_byte,
+	gate_cam0_phyclk_hs2_csis0_rx_byte,
+	gate_cam0_phyclk_hs3_csis0_rx_byte,
+	gate_cam0_phyclk_hs0_csis1_rx_byte,
+	gate_cam0_phyclk_hs1_csis1_rx_byte,
+	gate_cam1_common,
+	gate_cam1_isp_cpu_gic_common,
+	gate_cam1_isp_cpu,
+	gate_cam1_gic_is,
+	gate_cam1_csis2,
+	gate_cam1_csis3,
+	gate_cam1_fimc_vra,
+	gate_cam1_mc_scaler,
+	gate_cam1_i2c0_isp,
+	gate_cam1_i2c1_isp,
+	gate_cam1_i2c2_isp,
+	gate_cam1_i2c3_isp,
+	gate_cam1_wdt_isp,
+	gate_cam1_mcuctl_isp,
+	gate_cam1_uart_isp,
+	gate_cam1_sclk_uart_isp,
+	gate_cam1_spi0_isp,
+	gate_cam1_spi1_isp,
+	gate_cam1_pdma_isp,
+	gate_cam1_pwm_isp,
+	gate_cam1_sclk_pwm_isp,
+	gate_cam1_sysmmu,
+	gate_cam1_ppmu,
+	gate_cam1_bts,
+	gate_cam1_phyclk_hs0_csis2_rx_byte,
+	gate_cam1_phyclk_hs1_csis2_rx_byte,
+	gate_cam1_phyclk_hs2_csis2_rx_byte,
+	gate_cam1_phyclk_hs3_csis2_rx_byte,
+	gate_cam1_phyclk_hs0_csis3_rx_byte,
+	gate_ccore_i2c,
+	gate_disp0_common,
+	gate_disp0_decon0,
+	gate_disp0_dsim0,
+	gate_disp0_dsim1,
+	gate_disp0_dsim2,
+	gate_disp0_hdmi,
+	gate_disp0_dp,
+	gate_disp0_hpm_apbif_disp0,
+	gate_disp0_sysmmu,
+	gate_disp0_ppmu,
+	gate_disp0_bts,
+	gate_disp0_phyclk_hdmiphy_tmds_20b_clko,
+	gate_disp0_phyclk_hdmiphy_tmds_10b_clko,
+	gate_disp0_phyclk_hdmiphy_pixel_clko,
+	gate_disp0_phyclk_mipidphy0_rxclkesc0,
+	gate_disp0_phyclk_mipidphy0_bitclkdiv8,
+	gate_disp0_phyclk_mipidphy1_rxclkesc0,
+	gate_disp0_phyclk_mipidphy1_bitclkdiv8,
+	gate_disp0_phyclk_mipidphy2_rxclkesc0,
+	gate_disp0_phyclk_mipidphy2_bitclkdiv8,
+	gate_disp0_phyclk_dpphy_ch0_txd_clk,
+	gate_disp0_phyclk_dpphy_ch1_txd_clk,
+	gate_disp0_phyclk_dpphy_ch2_txd_clk,
+	gate_disp0_phyclk_dpphy_ch3_txd_clk,
+	gate_disp0_oscclk_dp_i_clk_24m,
+	gate_disp0_oscclk_i_dptx_phy_i_ref_clk_24m,
+	gate_disp0_oscclk_i_mipi_dphy_m1s0_m_xi,
+	gate_disp0_oscclk_i_mipi_dphy_m4s0_m_xi,
+	gate_disp0_oscclk_i_mipi_dphy_m4s4_m_xi,
+	gate_disp1_common,
+	gate_disp1_decon1,
+	gate_disp1_hpmdisp1,
+	gate_disp1_sysmmu,
+	gate_disp1_ppmu,
+	gate_disp1_bts,
+	gate_fsys0_common,
+	gate_fsys0_usbdrd_etrusb_common,
+	gate_fsys0_usbdrd30,
+	gate_fsys0_etr_usb,
+	gate_fsys0_usbhost20,
+	gate_fsys0_mmc0_ufs_common,
+	gate_fsys0_mmc0,
+	gate_fsys0_ufs_linkemedded,
+	gate_fsys0_pdma_common,
+	gate_fsys0_pdma0,
+	gate_fsys0_pdmas,
+	gate_fsys0_ppmu,
+	gate_fsys0_bts,
+	gate_fsys0_hpm,
+	gate_fsys0_phyclk_usbdrd30_udrd30_phyclock,
+	gate_fsys0_phyclk_usbdrd30_udrd30_pipe_pclk,
+	gate_fsys0_phyclk_ufs_tx0_symbol,
+	gate_fsys0_phyclk_ufs_rx0_symbol,
+	gate_fsys0_phyclk_usbhost20_phyclock,
+	gate_fsys0_phyclk_usbhost20_freeclk,
+	gate_fsys0_phyclk_usbhost20_clk48mohci,
+	gate_fsys0_phyclk_usbhost20phy_ref_clk,
+	gate_fsys0_phyclk_ufs_rx_pwm_clk,
+	gate_fsys0_phyclk_ufs_tx_pwm_clk,
+	gate_fsys0_phyclk_ufs_refclk_out_soc,
+	gate_fsys1_common,
+	gate_fsys1_mmc2_ufs_common,
+	gate_fsys1_mmc2,
+	gate_fsys1_ufs20_sdcard,
+	gate_fsys1_sromc,
+	gate_fsys1_pciewifi0,
+	gate_fsys1_pciewifi1,
+	gate_fsys1_ppmu,
+	gate_fsys1_bts,
+	gate_fsys1_hpm,
+	gate_fsys1_phyclk_ufs_link_sdcard_tx0_symbol,
+	gate_fsys1_phyclk_ufs_link_sdcard_rx0_symbol,
+	gate_fsys1_phyclk_pcie_wifi0_tx0,
+	gate_fsys1_phyclk_pcie_wifi0_rx0,
+	gate_fsys1_phyclk_pcie_wifi1_tx0,
+	gate_fsys1_phyclk_pcie_wifi1_rx0,
+	gate_fsys1_phyclk_pcie_wifi0_dig_refclk,
+	gate_fsys1_phyclk_pcie_wifi1_dig_refclk,
+	gate_fsys1_phyclk_ufs_link_sdcard_rx_pwm_clk,
+	gate_fsys1_phyclk_ufs_link_sdcard_tx_pwm_clk,
+	gate_fsys1_phyclk_ufs_link_sdcard_refclk_out_soc,
+	gate_g3d_common,
+	gate_g3d_g3d_common,
+	gate_g3d_g3d,
+	gate_g3d_iram_path_test,
+	gate_g3d_ppmu,
+	gate_g3d_bts,
+	gate_imem_common,
+	gate_imem_apm_sss_rtic_mc_common,
+	gate_imem_apm,
+	gate_imem_sss,
+	gate_imem_rtic,
+	gate_imem_mc,
+	gate_imem_intmem,
+	gate_imem_intmem_alv,
+	gate_imem_gic400,
+	gate_imem_ppmu,
+	gate_isp0_common,
+	gate_isp0_fimc_isp0,
+	gate_isp0_fimc_tpu,
+	gate_isp0_sysmmu,
+	gate_isp0_ppmu,
+	gate_isp0_bts,
+	gate_isp1_fimc_isp1,
+	gate_isp1_sysmmu,
+	gate_isp1_ppmu,
+	gate_isp1_bts,
+	gate_mfc_common,
+	gate_mfc_mfc,
+	gate_mfc_hpm,
+	gate_mfc_sysmmu,
+	gate_mfc_ppmu,
+	gate_mscl_common,
+	gate_mscl_mscl0_jpeg_common,
+	gate_mscl_mscl0,
+	gate_mscl_jpeg,
+	gate_mscl_mscl1_g2d_common,
+	gate_mscl_mscl1,
+	gate_mscl_g2d,
+	gate_mscl_sysmmu,
+	gate_mscl_ppmu,
+	gate_mscl_bts,
+	gate_peric0_hsi2c0,
+	gate_peric0_hsi2c1,
+	gate_peric0_hsi2c4,
+	gate_peric0_hsi2c5,
+	gate_peric0_hsi2c9,
+	gate_peric0_hsi2c10,
+	gate_peric0_hsi2c11,
+	gate_peric0_uart0,
+	gate_peric0_adcif,
+	gate_peric0_pwm,
+	gate_peric0_sclk_pwm,
+	gate_peric1_hsi2c_common,
+	gate_peric1_hsi2c2,
+	gate_peric1_hsi2c3,
+	gate_peric1_hsi2c6,
+	gate_peric1_hsi2c7,
+	gate_peric1_hsi2c8,
+	gate_peric1_hsi2c12,
+	gate_peric1_hsi2c13,
+	gate_peric1_hsi2c14,
+	gate_peric1_spi_i2s_pcm1_spdif_common,
+	gate_peric1_uart1,
+	gate_peric1_uart2,
+	gate_peric1_uart3,
+	gate_peric1_uart4,
+	gate_peric1_uart5,
+	gate_peric1_spi0,
+	gate_peric1_spi1,
+	gate_peric1_spi2,
+	gate_peric1_spi3,
+	gate_peric1_spi4,
+	gate_peric1_spi5,
+	gate_peric1_spi6,
+	gate_peric1_spi7,
+	gate_peric1_i2s1,
+	gate_peric1_pcm1,
+	gate_peric1_spdif,
+	gate_peric1_gpio_nfc,
+	gate_peric1_gpio_touch,
+	gate_peric1_gpio_fp,
+	gate_peric1_gpio_ese,
+	gate_peris_sfr_apbif_hdmi_cec,
+	gate_peris_hpm,
+	gate_peris_mct,
+	gate_peris_wdt_mngs,
+	gate_peris_wdt_apollo,
+	gate_peris_sysreg_peris,
+	gate_peris_monocnt_apbif,
+	gate_peris_rtc_apbif,
+	gate_peris_top_rtc,
+	gate_peris_otp_con_top,
+	gate_peris_chipid,
+	gate_peris_tmu,
+	vclk_group_grpgate_end,
+	num_of_grpgate = vclk_group_grpgate_end - 0x0A000000,
+
+	sclk_decon0_eclk0 = 0x0A010000,
+	sclk_decon0_vclk0,
+	sclk_decon0_vclk1,
+	sclk_hdmi_audio,
+	sclk_decon1_eclk0,
+	sclk_decon1_eclk1,
+	sclk_usbdrd30,
+	sclk_mmc0,
+	sclk_ufsunipro20,
+	sclk_phy24m,
+	sclk_ufsunipro_cfg,
+	sclk_mmc2,
+	sclk_ufsunipro20_sdcard,
+	sclk_pcie_phy,
+	sclk_ufsunipro_sdcard_cfg,
+	sclk_uart0,
+	sclk_spi0,
+	sclk_spi1,
+	sclk_spi2,
+	sclk_spi3,
+	sclk_spi4,
+	sclk_spi5,
+	sclk_spi6,
+	sclk_spi7,
+	sclk_uart1,
+	sclk_uart2,
+	sclk_uart3,
+	sclk_uart4,
+	sclk_uart5,
+	sclk_promise_int,
+	sclk_promise_disp,
+	sclk_ap2cp_mif_pll_out,
+	sclk_isp_spi0,
+	sclk_isp_spi1,
+	sclk_isp_uart,
+	sclk_isp_sensor0,
+	sclk_isp_sensor1,
+	sclk_isp_sensor2,
+	sclk_isp_sensor3,
+	sclk_decon0_eclk0_local,
+	sclk_decon0_vclk0_local,
+	sclk_decon0_vclk1_local,
+	sclk_decon1_eclk0_local,
+	sclk_decon1_eclk1_local,
+	vclk_group_m1d1g1_end,
+	num_of_m1d1g1 = vclk_group_m1d1g1_end - 0x0A010000,
+
+	p1_disp_pll = 0x0A020000,
+	p1_aud_pll,
+	p1_mfc_pll,
+	vclk_group_p1_end,
+	num_of_p1 = vclk_group_p1_end - 0x0A020000,
+
+	m1_dummy = 0x0A030000,
+	vclk_group_m1_end,
+	num_of_m1 = vclk_group_m1_end - 0x0A030000,
+
+	d1_sclk_i2s_local = 0x0A040000,
+	d1_sclk_pcm_local,
+	d1_sclk_slimbus,
+	d1_sclk_cp_i2s,
+	d1_sclk_asrc,
+	vclk_group_d1_end,
+	num_of_d1 = vclk_group_d1_end - 0x0A040000,
+
+	pxmxdx_top = 0x0A050000,
+	pxmxdx_mfc,
+	pxmxdx_mscl,
+	pxmxdx_imem,
+	pxmxdx_fsys0,
+	pxmxdx_fsys1,
+	pxmxdx_disp0,
+	pxmxdx_disp1,
+	pxmxdx_aud,
+	pxmxdx_aud_cp,
+	pxmxdx_isp0_isp0,
+	pxmxdx_isp0_tpu,
+	pxmxdx_isp0_trex,
+	pxmxdx_isp1_isp1,
+	pxmxdx_cam0_csis0,
+	pxmxdx_cam0_csis1,
+	pxmxdx_cam0_csis2,
+	pxmxdx_cam0_csis3,
+	pxmxdx_cam0_3aa0,
+	pxmxdx_cam0_3aa1,
+	pxmxdx_cam0_trex,
+	pxmxdx_cam1_arm,
+	pxmxdx_cam1_vra,
+	pxmxdx_cam1_trex,
+	pxmxdx_cam1_bus,
+	pxmxdx_cam1_peri,
+	pxmxdx_cam1_csis2,
+	pxmxdx_cam1_csis3,
+	pxmxdx_cam1_scl,
+	pxmxdx_oscclk_nfc,
+	pxmxdx_oscclk_aud,
+	vclk_group_pxmxdx_end,
+	num_of_pxmxdx = vclk_group_pxmxdx_end - 0x0A050000,
+
+	umux_bus0_aclk_bus0_528 = 0x0A060000,
+	umux_bus0_aclk_bus0_200,
+	umux_bus1_aclk_bus1_528,
+	umux_cam0_phyclk_rxbyteclkhs0_csis0_user,
+	umux_cam0_phyclk_rxbyteclkhs1_csis0_user,
+	umux_cam0_phyclk_rxbyteclkhs2_csis0_user,
+	umux_cam0_phyclk_rxbyteclkhs3_csis0_user,
+	umux_cam0_phyclk_rxbyteclkhs0_csis1_user,
+	umux_cam0_phyclk_rxbyteclkhs1_csis1_user,
+	umux_cam1_phyclk_rxbyteclkhs0_csis2_user,
+	umux_cam1_phyclk_rxbyteclkhs1_csis2_user,
+	umux_cam1_phyclk_rxbyteclkhs2_csis2_user,
+	umux_cam1_phyclk_rxbyteclkhs3_csis2_user,
+	umux_cam1_phyclk_rxbyteclkhs0_csis3_user,
+	umux_disp0_phyclk_hdmiphy_pixel_clko_user,
+	umux_disp0_phyclk_hdmiphy_tmds_clko_user,
+	umux_disp0_phyclk_mipidphy0_rxclkesc0_user,
+	umux_disp0_phyclk_mipidphy0_bitclkdiv2_user,
+	umux_disp0_phyclk_mipidphy0_bitclkdiv8_user,
+	umux_disp0_phyclk_mipidphy1_rxclkesc0_user,
+	umux_disp0_phyclk_mipidphy1_bitclkdiv2_user,
+	umux_disp0_phyclk_mipidphy1_bitclkdiv8_user,
+	umux_disp0_phyclk_mipidphy2_rxclkesc0_user,
+	umux_disp0_phyclk_mipidphy2_bitclkdiv2_user,
+	umux_disp0_phyclk_mipidphy2_bitclkdiv8_user,
+	umux_disp0_phyclk_dpphy_ch0_txd_clk_user,
+	umux_disp0_phyclk_dpphy_ch1_txd_clk_user,
+	umux_disp0_phyclk_dpphy_ch2_txd_clk_user,
+	umux_disp0_phyclk_dpphy_ch3_txd_clk_user,
+	umux_disp1_phyclk_mipidphy0_bitclkdiv2_user,
+	umux_disp1_phyclk_mipidphy1_bitclkdiv2_user,
+	umux_disp1_phyclk_mipidphy2_bitclkdiv2_user,
+	umux_disp1_phyclk_disp1_hdmiphy_pixel_clko_user,
+	umux_fsys0_phyclk_usbdrd30_udrd30_phyclock_user,
+	umux_fsys0_phyclk_usbdrd30_udrd30_pipe_pclk_user,
+	umux_fsys0_phyclk_ufs_tx0_symbol_user,
+	umux_fsys0_phyclk_ufs_rx0_symbol_user,
+	umux_fsys0_phyclk_usbhost20_phyclock_user,
+	umux_fsys0_phyclk_usbhost20_freeclk_user,
+	umux_fsys0_phyclk_usbhost20_clk48mohci_user,
+	umux_fsys0_phyclk_usbhost20phy_ref_clk,
+	umux_fsys0_phyclk_ufs_rx_pwm_clk_user,
+	umux_fsys0_phyclk_ufs_tx_pwm_clk_user,
+	umux_fsys0_phyclk_ufs_refclk_out_soc_user,
+	umux_fsys1_phyclk_ufs_link_sdcard_tx0_symbol_user,
+	umux_fsys1_phyclk_ufs_link_sdcard_rx0_symbol_user,
+	umux_fsys1_phyclk_pcie_wifi0_tx0_user,
+	umux_fsys1_phyclk_pcie_wifi0_rx0_user,
+	umux_fsys1_phyclk_pcie_wifi1_tx0_user,
+	umux_fsys1_phyclk_pcie_wifi1_rx0_user,
+	umux_fsys1_phyclk_pcie_wifi0_dig_refclk_user,
+	umux_fsys1_phyclk_pcie_wifi1_dig_refclk_user,
+	umux_fsys1_phyclk_ufs_link_sdcard_rx_pwm_clk_user,
+	umux_fsys1_phyclk_ufs_link_sdcard_tx_pwm_clk_user,
+	umux_fsys1_phyclk_ufs_link_sdcard_refclk_out_soc_user,
+	vclk_group_umux_end,
+	num_of_umux = vclk_group_umux_end - 0x0A060000,
+
+	dvfs_big = 0x0A070000,
+	dvfs_little,
+	dvfs_g3d,
+	dvfs_mif,
+	dvfs_int,
+	dvfs_cam,
+	dvfs_disp,
+	vclk_group_dfs_end,
+	num_of_dfs = vclk_group_dfs_end - 0x0A070000,
+};
+
+#endif

drivers/soc/samsung/pwrcal/pmucal_mod/S5E7570/pmucal_cpu_exynos7570.h

@@ -0,0 +1,96 @@
+/* individual sequence descriptor for each core - on, off, status */
+static struct pmucal_seq core0_on[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_CPU0_CONFIGURATION", 0x11C80000, 0x2000, (0xf << 0), (0xF << 0), 0, 0, 0xffffffff, 0),
+};
+static struct pmucal_seq core0_off[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_CPU0_CONFIGURATION", 0x11C80000, 0x2000, (0xf << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+};
+static struct pmucal_seq core0_status[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_READ, "CPUCL0_CPU0_STATUS", 0x11C80000, 0x2004, (0xf << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+};
+static struct pmucal_seq core1_on[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_CPU1_CONFIGURATION", 0x11C80000, 0x2080, (0xf << 0), (0xF << 0), 0, 0, 0xffffffff, 0),
+};
+static struct pmucal_seq core1_off[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_CPU1_CONFIGURATION", 0x11C80000, 0x2080, (0xf << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+};
+static struct pmucal_seq core1_status[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_READ, "CPUCL0_CPU1_STATUS", 0x11C80000, 0x2084, (0xf << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+};
+static struct pmucal_seq core2_on[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_CPU2_CONFIGURATION", 0x11C80000, 0x2100, (0xf << 0), (0xF << 0), 0, 0, 0xffffffff, 0),
+};
+static struct pmucal_seq core2_off[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_CPU2_CONFIGURATION", 0x11C80000, 0x2100, (0xf << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+};
+static struct pmucal_seq core2_status[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_READ, "CPUCL0_CPU2_STATUS", 0x11C80000, 0x2104, (0xf << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+};
+static struct pmucal_seq core3_on[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_CPU3_CONFIGURATION", 0x11C80000, 0x2180, (0xf << 0), (0xF << 0), 0, 0, 0xffffffff, 0),
+};
+static struct pmucal_seq core3_off[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_CPU3_CONFIGURATION", 0x11C80000, 0x2180, (0xf << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+};
+static struct pmucal_seq core3_status[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_READ, "CPUCL0_CPU3_STATUS", 0x11C80000, 0x2184, (0xf << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+};
+static struct pmucal_seq cluster0_on[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_CPUSEQUENCER_OPTION", 0x11C80000, 0x2488, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x10910000, 0x0200, (0xffffffff << 0), (0xFFFFFFFF << 0), 0, 0, 0xffffffff, 0),
+};
+static struct pmucal_seq cluster0_off[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_CPUSEQUENCER_OPTION", 0x11C80000, 0x2488, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+};
+static struct pmucal_seq cluster0_status[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_READ, "CPUCL0_CPUSQUENCER_STATUS", 0x11C80000, 0x2484, (0xf << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+};
+static struct pmucal_cpu pmucal_cpu_list[PMUCAL_NUM_CORES] = {
+	[CPU_CORE0] = {
+		.id = CPU_CORE0,
+		.on = core0_on,
+		.off = core0_off,
+		.status = core0_status,
+		.num_on = ARRAY_SIZE(core0_on),
+		.num_off = ARRAY_SIZE(core0_off),
+		.num_status = ARRAY_SIZE(core0_status),
+	},
+	[CPU_CORE1] = {
+		.id = CPU_CORE1,
+		.on = core1_on,
+		.off = core1_off,
+		.status = core1_status,
+		.num_on = ARRAY_SIZE(core1_on),
+		.num_off = ARRAY_SIZE(core1_off),
+		.num_status = ARRAY_SIZE(core1_status),
+	},
+	[CPU_CORE2] = {
+		.id = CPU_CORE2,
+		.on = core2_on,
+		.off = core2_off,
+		.status = core2_status,
+		.num_on = ARRAY_SIZE(core2_on),
+		.num_off = ARRAY_SIZE(core2_off),
+		.num_status = ARRAY_SIZE(core2_status),
+	},
+	[CPU_CORE3] = {
+		.id = CPU_CORE3,
+		.on = core3_on,
+		.off = core3_off,
+		.status = core3_status,
+		.num_on = ARRAY_SIZE(core3_on),
+		.num_off = ARRAY_SIZE(core3_off),
+		.num_status = ARRAY_SIZE(core3_status),
+	},
+};
+static struct pmucal_cpu pmucal_cluster_list[PMUCAL_NUM_CLUSTERS] = {
+	[CPU_CLUSTER0] = {
+		.id = CPU_CLUSTER0,
+		.on = cluster0_on,
+		.off = cluster0_off,
+		.status = cluster0_status,
+		.num_on = ARRAY_SIZE(cluster0_on),
+		.num_off = ARRAY_SIZE(cluster0_off),
+		.num_status = ARRAY_SIZE(cluster0_status),
+	},
+};

drivers/soc/samsung/pwrcal/pmucal_mod/S5E7570/pmucal_local_exynos7570.h

@@ -0,0 +1,264 @@
+static struct pmucal_seq g3d_on[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKCMU_G3D", 0x10460000, 0x0228, (0x1 << 21), (0x1 << 21), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G3D_CONFIGURATION", 0x11C80000, 0x4000, (0xf << 0), (0xF << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WAIT, "G3D_STATUS", 0x11C80000, 0x4004, (0xf << 0), (0xF << 0), 0x11C80000, 0x4004, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G3D_BUS_D_DRCG_EN", 0x11450000, 0x0200, (0xffffffff << 0), (0xFFFFFFFF << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G3D_BUS_P_DRCG_EN", 0x11450000, 0x0204, (0xffffffff << 0), (0xFFFFFFFF << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G3D_QE_DRCG_EN", 0x11450000, 0x0208, (0xffffffff << 0), (0xFFFFFFFF << 0), 0, 0, 0xffffffff, 0),
+};
+
+static struct pmucal_seq g3d_save[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLK_G3D_APB", 0x11460000, 0x0404, 0xffffffff, 0, 0x11C80000, 0x4004, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLK_G3D_BUS", 0x11460000, 0x0400, 0xffffffff, 0, 0x11C80000, 0x4004, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_PDN_G3D", 0x11460000, 0x0E00, 0xffffffff, 0, 0x11C80000, 0x4004, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_G3D_APB", 0x11460000, 0x0808, 0xffffffff, 0, 0x11C80000, 0x4004, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_G3D_BUS", 0x11460000, 0x0804, 0xffffffff, 0, 0x11C80000, 0x4004, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_G3D_OSCCLK", 0x11460000, 0x0800, 0xffffffff, 0, 0x11C80000, 0x4004, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_CLKCMU_G3D_USER", 0x11460000, 0x0204, 0xffffffff, 0, 0x11C80000, 0x4004, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_STAT_MUX_CLKCMU_G3D_USER", 0x11460000, 0x0604, 0xffffffff, 0, 0x11C80000, 0x4004, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CMU_G3D", 0x11460000, 0x0D00, 0xffffffff, 0, 0x11C80000, 0x4004, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CMU_G3D_DIV_STAT", 0x11460000, 0x0D04, 0xffffffff, 0, 0x11C80000, 0x4004, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CMU_G3D_SPARE0", 0x11460000, 0x0D08, 0xffffffff, 0, 0x11C80000, 0x4004, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CMU_G3D_SPARE1", 0x11460000, 0x0D0C, 0xffffffff, 0, 0x11C80000, 0x4004, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "G3D_SFR_IGNORE_REQ_SYSCLK", 0x11460000, 0x0F00, 0xffffffff, 0, 0x11C80000, 0x4004, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_STOPCTRL", 0x11460000, 0x1000, 0xffffffff, 0, 0x11C80000, 0x4004, (0xf << 0), (0xF << 0)),
+};
+
+static struct pmucal_seq g3d_off[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLKSTOP_OPEN_CMU_G3D_SYS_PWR_REG", 0x11C80000, 0x1388, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLKRUN_CMU_G3D_SYS_PWR_REG", 0x11C80000, 0x1440, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLKSTOP_CMU_G3D_SYS_PWR_REG", 0x11C80000, 0x1480, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DISABLE_PLL_CMU_G3D_SYS_PWR_REG", 0x11C80000, 0x14C0, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "RESET_LOGIC_G3D_SYS_PWR_REG", 0x11C80000, 0x1500, (0x3 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MEMORY_G3D_SYS_PWR_REG", 0x11C80000, 0x1540, (0x3 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "RESET_CMU_G3D_SYS_PWR_REG", 0x11C80000, 0x1580, (0x3 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G3D_CONFIGURATION", 0x11C80000, 0x4000, (0xf << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WAIT, "G3D_STATUS", 0x11C80000, 0x4004, (0xf << 0), (0x0 << 0), 0x11C80000, 0x4004, (0xf << 0), (0x0 << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKCMU_G3D", 0x10460000, 0x0228, (0x1 << 21), (0x0 << 21), 0, 0, 0xffffffff, 0),
+};
+
+static struct pmucal_seq g3d_status[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_READ, "G3D_STATUS", 0x11C80000, 0x4004, (0xf << 0), (0xF << 0), 0x11C80000, 0x4004, (0xf << 0), (0xF << 0)),
+};
+
+static struct pmucal_seq isp_on[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKCMU_ISP_VRA", 0x10460000, 0x022C, (0x1 << 21), (0x1 << 21), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKCMU_ISP_CAM", 0x10460000, 0x0230, (0x1 << 21), (0x1 << 21), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKCMU_ISP_SENSOR0", 0x10460000, 0x0280, (0x1 << 21), (0x1 << 21), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "ISP_CONFIGURATION", 0x11C80000, 0x4040, (0xf << 0), (0xF << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WAIT, "ISP_STATUS", 0x11C80000, 0x4044, (0xf << 0), (0xF << 0), 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x144F0000, 0x0204, (0xffffffff << 0), (0xFFFFFFFF << 0), 0, 0, 0xffffffff, 0),
+};
+
+static struct pmucal_seq isp_save[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLK_ISP_CAM_HALF", 0x144D0000, 0x0404, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_PDN_ISP", 0x144D0000, 0x0E00, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLKPHY_ISP_S_RXBYTECLKHS0_S4", 0x144D0000, 0x0828, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_ISP_CAM", 0x144D0000, 0x081C, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_ISP_VRA", 0x144D0000, 0x0810, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_ISP_OSCCLK", 0x144D0000, 0x0800, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER", 0x144D0000, 0x0230, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_CLKCMU_ISP_CAM_USER", 0x144D0000, 0x0214, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_CLKCMU_ISP_VRA_USER", 0x144D0000, 0x0210, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_STAT_MUX_CLKCMU_ISP_VRA_USER", 0x144D0000, 0x0610, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_STAT_MUX_CLKCMU_ISP_CAM_USER", 0x144D0000, 0x0614, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_STAT_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER", 0x144D0000, 0x0630, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CMU_ISP", 0x144D0000, 0x0D00, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CMU_ISP_DIV_STAT", 0x144D0000, 0x0D04, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CMU_ISP_SPARE0", 0x144D0000, 0x0D08, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CMU_ISP_SPARE1", 0x144D0000, 0x0D0C, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "ISP_SFR_IGNORE_REQ_SYSCLK", 0x144D0000, 0x0F00, 0xffffffff, 0, 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+};
+
+static struct pmucal_seq isp_off[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER", 0x144D0000, 0x0230, (0x1 << 12), (0x0 << 12), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER", 0x144D0000, 0x0230, (0x1 << 27), (0x1 << 27), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLKSTOP_OPEN_CMU_ISP_SYS_PWR_REG", 0x11C80000, 0x1390, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLKRUN_CMU_ISP_SYS_PWR_REG", 0x11C80000, 0x1448, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLKSTOP_CMU_ISP_SYS_PWR_REG", 0x11C80000, 0x1488, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DISABLE_PLL_CMU_ISP_SYS_PWR_REG", 0x11C80000, 0x14C8, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "RESET_LOGIC_ISP_SYS_PWR_REG", 0x11C80000, 0x1508, (0x3 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MEMORY_ISP_SYS_PWR_REG", 0x11C80000, 0x1548, (0x3 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "RESET_CMU_ISP_SYS_PWR_REG", 0x11C80000, 0x1588, (0x3 << 0), 0, 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "ISP_CONFIGURATION", 0x11C80000, 0x4040, (0xf << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WAIT, "ISP_STATUS", 0x11C80000, 0x4044, (0xf << 0), (0x0 << 0), 0x11C80000, 0x4044, (0xf << 0), (0x0 << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKCMU_ISP_VRA", 0x10460000, 0x022C, (0x1 << 21), (0x0 << 21), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKCMU_ISP_CAM", 0x10460000, 0x0230, (0x1 << 21), (0x0 << 21), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKCMU_ISP_SENSOR0", 0x10460000, 0x0280, (0x1 << 21), (0x0 << 21), 0, 0, 0xffffffff, 0),
+};
+
+static struct pmucal_seq isp_status[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_READ, "ISP_STATUS", 0x11C80000, 0x4044, (0xf << 0), (0xF << 0), 0x11C80000, 0x4044, (0xf << 0), (0xF << 0)),
+};
+
+static struct pmucal_seq mfcmscl_on[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL", 0x10460000, 0x0240, (0x1 << 21), (0x1 << 21), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKCMU_MFCMSCL_MFC", 0x10460000, 0x0244, (0x1 << 21), (0x1 << 21), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MFCMSCL_CONFIGURATION", 0x11C80000, 0x4060, (0xf << 0), (0xF << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WAIT, "MFCMSCL_STATUS", 0x11C80000, 0x4064, (0xf << 0), (0xF << 0), 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "SCALER_CFG", 0x12C10000, 0x0004, (0x1 << 31), (0x1 << 31), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "SCALER_CFG", 0x12C10000, 0x0004, (0x1 << 28), (0x1 << 28), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MFCMSCL_AUTOCG_EN", 0x12CA0000, 0x0504, (0xffffffff << 0), (0xFFFFFFFF << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MFCMSCL_BUS_DRCG_EN", 0x12CA0000, 0x0508, (0xffffffff << 0), (0xFFFFFFFF << 0), 0, 0, 0xffffffff, 0),
+};
+
+static struct pmucal_seq mfcmscl_save[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLK_MFCMSCL_APB", 0x12CB0000, 0x0400, 0xffffffff, 0, 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_PDN_MFCMSCL", 0x12CB0000, 0x0E00, 0xffffffff, 0, 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_MFCMSCL_MFC", 0x12CB0000, 0x0808, 0xffffffff, 0, 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_MFCMSCL_MSCL", 0x12CB0000, 0x0804, 0xffffffff, 0, 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_MFCMSCL_OSCCLK", 0x12CB0000, 0x0800, 0xffffffff, 0, 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_CLKCMU_MFCMSCL_MFC_USER", 0x12CB0000, 0x0204, 0xffffffff, 0, 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL_USER", 0x12CB0000, 0x0200, 0xffffffff, 0, 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_STAT_MUX_CLKCMU_MFCMSCL_MSCL_USER", 0x12CB0000, 0x0600, 0xffffffff, 0, 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_STAT_MUX_CLKCMU_MFCMSCL_MFC_USER", 0x12CB0000, 0x0604, 0xffffffff, 0, 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "SECURE_ENABLE_SMMU_MSCL", 0x12CB0000, 0x0814, 0xffffffff, 0, 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CMU_MFCMSCL", 0x12CB0000, 0x0D00, 0xffffffff, 0, 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CMU_MFCMSCL_DIV_STAT", 0x12CB0000, 0x0D04, 0xffffffff, 0, 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CMU_MFCMSCL_SPARE0", 0x12CB0000, 0x0D08, 0xffffffff, 0, 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CMU_MFCMSCL_SPARE1", 0x12CB0000, 0x0D0C, 0xffffffff, 0, 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MFCMSCL_SFR_IGNORE_REQ_SYSCLK", 0x12CB0000, 0x0F00, 0xffffffff, 0, 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+};
+
+static struct pmucal_seq mfcmscl_off[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLKSTOP_OPEN_CMU_MFCMSCL_SYS_PWR_REG", 0x11C80000, 0x1394, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLKRUN_CMU_MFCMSCL_SYS_PWR_REG", 0x11C80000, 0x144C, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLKSTOP_CMU_MFCMSCL_SYS_PWR_REG", 0x11C80000, 0x148C, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DISABLE_PLL_CMU_MFCMSCL_SYS_PWR_REG", 0x11C80000, 0x14CC, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "RESET_LOGIC_MFCMSCL_SYS_PWR_REG", 0x11C80000, 0x150C, (0x3 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MEMORY_MFCMSCL_SYS_PWR_REG", 0x11C80000, 0x154C, (0x3 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "RESET_CMU_MFCMSCL_SYS_PWR_REG", 0x11C80000, 0x158C, (0x3 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MFCMSCL_CONFIGURATION", 0x11C80000, 0x4060, (0xf << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WAIT, "MFCMSCL_STATUS", 0x11C80000, 0x4064, (0xf << 0), (0x0 << 0), 0x11C80000, 0x4064, (0xf << 0), (0x0 << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL", 0x10460000, 0x0240, (0x1 << 21), (0x0 << 21), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKCMU_MFCMSCL_MFC", 0x10460000, 0x0244, (0x1 << 21), (0x0 << 21), 0, 0, 0xffffffff, 0),
+};
+
+static struct pmucal_seq mfcmscl_status[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_READ, "MFCMSCL_STATUS", 0x11C80000, 0x4064, (0xf << 0), (0xF << 0), 0x11C80000, 0x4064, (0xf << 0), (0xF << 0)),
+};
+
+static struct pmucal_seq dispaud_on[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKCMU_DISPAUD_BUS", 0x10460000, 0x0234, (0x1 << 21), (0x1 << 21), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK", 0x10460000, 0x0238, (0x1 << 21), (0x1 << 21), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DISPAUD_CONFIGURATION", 0x11C80000, 0x4020, (0xf << 0), (0xF << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WAIT, "DISPAUD_STATUS", 0x11C80000, 0x4024, (0xf << 0), (0xF << 0), 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "VCLKCON0", 0x14830000, 0x0010, (0x1 << 12), (0x1 << 12), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DISPAUD_XIU_TOP_DRCG_EN", 0x148F0000, 0x0204, (0xffffffff << 0), (0xFFFFFFFF << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DISPAUD_SYSMMU_CON", 0x148F0000, 0x0210, (0xffffffff << 0), (0xFFFFFFFF << 0), 0, 0, 0xffffffff, 0),
+};
+
+static struct pmucal_seq dispaud_save[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "AUD_PLL_LOCK", 0x148D0000, 0x00C0, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "AUD_PLL_CON0", 0x148D0000, 0x01C0, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "AUD_PLL_CON1", 0x148D0000, 0x01C4, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "AUD_PLL_CON2", 0x148D0000, 0x01C8, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLK_DISPAUD_OSCCLK_FM_52M_DIV", 0x148D0000, 0x0414, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLK_DISPAUD_MIXER", 0x148D0000, 0x0410, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLK_DISPAUD_MI2S", 0x148D0000, 0x040C, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLK_DISPAUD_DECON_INT_VCLK", 0x148D0000, 0x0404, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLK_DISPAUD_APB", 0x148D0000, 0x0400, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_PDN_DISPAUD", 0x148D0000, 0x0E00, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_OSCCLK_FM_52M_DIV", 0x148D0000, 0x0848, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_OSCCLK_FM_52M", 0x148D0000, 0x0844, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_CP", 0x148D0000, 0x083C, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_DISPAUD_MIXER", 0x148D0000, 0x0830, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_DISPAUD_MI2S", 0x148D0000, 0x082C, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0", 0x148D0000, 0x0828, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS", 0x148D0000, 0x0824, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_DISPAUD_DECON_INT_VCLK", 0x148D0000, 0x0820, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_DISPAUD_APB", 0x148D0000, 0x0814, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_DISPAUD_BUS", 0x148D0000, 0x0810, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_ENABLE_CLK_DISPAUD_OSCCLK", 0x148D0000, 0x0800, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_CLKCMU_DISPAUD_BUS_USER", 0x148D0000, 0x0210, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER", 0x148D0000, 0x0214, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER", 0x148D0000, 0x0224, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER", 0x148D0000, 0x0228, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_AUD_PLL", 0x148D0000, 0x0204, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_STAT_MUX_AUD_PLL", 0x148D0000, 0x0604, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_STAT_MUX_CLKCMU_DISPAUD_BUS_USER", 0x148D0000, 0x0610, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER", 0x148D0000, 0x0614, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER", 0x148D0000, 0x0624, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER", 0x148D0000, 0x0628, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CMU_DISPAUD", 0x148D0000, 0x0D00, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CMU_DISPAUD_DIV_STAT", 0x148D0000, 0x0D04, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CMU_DISPAUD_SPARE0", 0x148D0000, 0x0D08, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CMU_DISPAUD_SPARE1", 0x148D0000, 0x0D0C, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DISPAUD_SFR_IGNORE_REQ_SYSCLK", 0x148D0000, 0x0F00, 0xffffffff, 0, 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_CHECK_SKIP, "AUD_PLL_CON0", 0x148D0000, 0x01C0, (0x1 << 31), (0x0 << 31), 0x148D0000, 0x01C0, (0x1 << 31), (0x0 << 31)),
+	PMUCAL_SEQ_DESC(PMUCAL_WAIT, "AUD_PLL_CON0", 0x148D0000, 0x01C0, (0x1 << 29), (0x1 << 29), 0x148D0000, 0x01C0, (0x1 << 29), (0x1 << 29)),
+};
+
+static struct pmucal_seq dispaud_off[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKPHY_DISPAUD_MIPIDPHY_TXBYTECLKHS_USER", 0x148D0000, 0x0224, (0x1 << 12), (0x0 << 12), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKPHY_DISPAUD_MIPIDPHY_RXCLKESC0_USER", 0x148D0000, 0x0228, (0x1 << 12), (0x0 << 12), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKPHY_DISPAUD_MIPIDPHY_TXBYTECLKHS_USER", 0x148D0000, 0x0224, (0x1 << 27), (0x1 << 27), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKPHY_DISPAUD_MIPIDPHY_RXCLKESC0_USER", 0x148D0000, 0x0228, (0x1 << 27), (0x1 << 27), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GPIO_MODE_DISPAUD_SYS_PWR_REG", 0x11C80000, 0x1340, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLKSTOP_OPEN_CMU_DISPAUD_SYS_PWR_REG", 0x11C80000, 0x138C, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLKRUN_CMU_DISPAUD_SYS_PWR_REG", 0x11C80000, 0x1444, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLKSTOP_CMU_DISPAUD_SYS_PWR_REG", 0x11C80000, 0x1484, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DISABLE_PLL_CMU_DISPAUD_SYS_PWR_REG", 0x11C80000, 0x14C4, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "RESET_LOGIC_DISPAUD_SYS_PWR_REG", 0x11C80000, 0x1504, (0x3 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MEMORY_DISPAUD_SYS_PWR_REG", 0x11C80000, 0x1544, (0x3 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "RESET_CMU_DISPAUD_SYS_PWR_REG", 0x11C80000, 0x1584, (0x3 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DISPAUD_CONFIGURATION", 0x11C80000, 0x4020, (0xf << 0), (0x0 << 0), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WAIT, "DISPAUD_STATUS", 0x11C80000, 0x4024, (0xf << 0), (0x0 << 0), 0x11C80000, 0x4024, (0xf << 0), (0x0 << 0)),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKCMU_DISPAUD_BUS", 0x10460000, 0x0234, (0x1 << 21), (0x0 << 21), 0, 0, 0xffffffff, 0),
+	PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK", 0x10460000, 0x0238, (0x1 << 21), (0x0 << 21), 0, 0, 0xffffffff, 0),
+};
+
+static struct pmucal_seq dispaud_status[] = {
+	PMUCAL_SEQ_DESC(PMUCAL_READ, "DISPAUD_STATUS", 0x11C80000, 0x4024, (0xf << 0), (0xF << 0), 0x11C80000, 0x4024, (0xf << 0), (0xF << 0)),
+};
+
+static struct pmucal_pd pmucal_pd_list[PMUCAL_NUM_PDS] = {
+	[PD_G3D] = {
+		.id = PD_G3D,
+		.name = "blkpwr_g3d",
+		.on = g3d_on,
+		.save = g3d_save,
+		.off = g3d_off,
+		.status = g3d_status,
+		.num_on = ARRAY_SIZE(g3d_on),
+		.num_save = ARRAY_SIZE(g3d_save),
+		.num_off = ARRAY_SIZE(g3d_off),
+		.num_status = ARRAY_SIZE(g3d_status),
+	},
+	[PD_ISP] = {
+		.id = PD_ISP,
+		.name = "blkpwr_isp",
+		.on = isp_on,
+		.save = isp_save,
+		.off = isp_off,
+		.status = isp_status,
+		.num_on = ARRAY_SIZE(isp_on),
+		.num_save = ARRAY_SIZE(isp_save),
+		.num_off = ARRAY_SIZE(isp_off),
+		.num_status = ARRAY_SIZE(isp_status),
+	},
+	[PD_MFCMSCL] = {
+		.id = PD_MFCMSCL,
+		.name = "blkpwr_mfcmscl",
+		.on = mfcmscl_on,
+		.save = mfcmscl_save,
+		.off = mfcmscl_off,
+		.status = mfcmscl_status,
+		.num_on = ARRAY_SIZE(mfcmscl_on),
+		.num_save = ARRAY_SIZE(mfcmscl_save),
+		.num_off = ARRAY_SIZE(mfcmscl_off),
+		.num_status = ARRAY_SIZE(mfcmscl_status),
+	},
+	[PD_DISPAUD] = {
+		.id = PD_DISPAUD,
+		.name = "blkpwr_dispaud",
+		.on = dispaud_on,
+		.save = dispaud_save,
+		.off = dispaud_off,
+		.status = dispaud_status,
+		.num_on = ARRAY_SIZE(dispaud_on),
+		.num_save = ARRAY_SIZE(dispaud_save),
+		.num_off = ARRAY_SIZE(dispaud_off),
+		.num_status = ARRAY_SIZE(dispaud_status),
+	},
+};

drivers/soc/samsung/pwrcal/pmucal_mod/S5E7570/pmucal_p2vmap_exynos7570.h

@@ -0,0 +1,23 @@
+static struct p2v_map pmucal_p2v_list[] = {
+	DEFINE_PHY(0x148D0000),
+	DEFINE_PHY(0x144D0000),
+	DEFINE_PHY(0x13730000),
+	DEFINE_PHY(0x12CB0000),
+	DEFINE_PHY(0x10900000),
+	DEFINE_PHY(0x11460000),
+	DEFINE_PHY(0x101F0000),
+	DEFINE_PHY(0x10460000),
+	DEFINE_PHY(0x11CE0000),
+	DEFINE_PHY(0x11C80000),
+	DEFINE_PHY(0x101D0000),
+	DEFINE_PHY(0x13720000),
+	DEFINE_PHY(0x10400000),
+	DEFINE_PHY(0x10450000),
+	DEFINE_PHY(0x148F0000),
+	DEFINE_PHY(0x14830000),
+	DEFINE_PHY(0x12C10000),
+	DEFINE_PHY(0x12CA0000),
+	DEFINE_PHY(0x144F0000),
+	DEFINE_PHY(0x11450000),
+	DEFINE_PHY(0x10910000),
+};

drivers/soc/samsung/pwrcal/pmucal_mod/pmucal_common.h

@@ -0,0 +1,66 @@
+#ifndef __PMUCAL_COMMON_H__
+#define __PMUCAL_COMMON_H__
+
+#include "../pwrcal-env.h"
+
+#ifdef PWRCAL_TARGET_LINUX
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sizes.h>
+#include <linux/exynos-ss.h>
+#include <linux/delay.h>
+#endif
+
+#define PMUCAL_PREFIX		"PMUCAL:  "
+
+/* represents the value in access_type column in guide */
+enum pmucal_seq_acctype {
+	PMUCAL_READ = 0,
+	PMUCAL_WRITE,
+	PMUCAL_COND_READ,
+	PMUCAL_COND_WRITE,
+	PMUCAL_SAVE_RESTORE,
+	PMUCAL_COND_SAVE_RESTORE,
+	PMUCAL_WAIT,
+	PMUCAL_CHECK_SKIP,
+	PMUCAL_COND_CHECK_SKIP,
+};
+
+/* represents each row in the PMU sequence guide */
+struct pmucal_seq {
+	u32 access_type;
+	char *sfr_name;
+	phys_addr_t base_pa;
+	void __iomem *base_va;
+	u32 offset;
+	u32 mask;
+	u32 value;
+	phys_addr_t cond_base_pa;
+	void __iomem *cond_base_va;
+	u32 cond_offset;
+	u32 cond_mask;
+	u32 cond_value;
+	bool need_restore;
+	bool need_skip;
+};
+
+#define PMUCAL_SEQ_DESC(_access_type, _sfr_name, _base_pa, _offset,	\
+			_mask, _value, _cond_base_pa, _cond_offset,	\
+			_cond_mask, _cond_value) {			\
+	.access_type = _access_type,					\
+	.sfr_name = _sfr_name,						\
+	.base_pa = _base_pa,						\
+	.base_va = NULL,						\
+	.offset = _offset,						\
+	.mask = _mask,							\
+	.value = _value,						\
+	.cond_base_pa = _cond_base_pa,					\
+	.cond_base_va = NULL,						\
+	.cond_offset = _cond_offset,					\
+	.cond_mask = _cond_mask,					\
+	.cond_value = _cond_value,					\
+	.need_restore = false,						\
+	.need_skip = false,						\
+}
+
+#endif

drivers/soc/samsung/pwrcal/pmucal_mod/pmucal_cpu.c

@@ -0,0 +1,306 @@
+#include "pmucal_cpu.h"
+#include "pmucal_rae.h"
+#ifdef CONFIG_SOC_EXYNOS7570
+#include "./S5E7570/pmucal_cpu_exynos7570.h"
+#endif
+
+/**
+ *  pmucal_cpu_enable - enables a core.
+ *		        exposed to PWRCAL interface.
+ *
+ *  @cpu: cpu core index.
+ *
+ *  Returns 0 on success. Otherwise, negative error code.
+ */
+int pmucal_cpu_enable(unsigned int cpu)
+{
+	int ret;
+
+	if (cpu >= PMUCAL_NUM_CORES) {
+		pr_err("%s core index(%d) is out of supported range (0~%d).\n",
+				PMUCAL_PREFIX, cpu, PMUCAL_NUM_CORES);
+		return -EINVAL;
+	}
+
+	if (!pmucal_cpu_list[cpu].on) {
+		pr_err("%s there is no sequence element for core(%d) power-on.\n",
+				PMUCAL_PREFIX, cpu);
+		return -ENOENT;
+	}
+
+	ret = pmucal_rae_handle_seq(pmucal_cpu_list[cpu].on,
+				pmucal_cpu_list[cpu].num_on);
+	if (ret) {
+		pr_err("%s %s: error on handling enable sequence. (cpu : %d)\n",
+				PMUCAL_PREFIX, __func__, cpu);
+		return ret;
+	}
+
+	return 0;
+}
+
+/**
+ *  pmucal_cpu_disable - disables a core.
+ *		        exposed to PWRCAL interface.
+ *
+ *  @cpu: cpu core index.
+ *
+ *  Returns 0 on success. Otherwise, negative error code.
+ */
+int pmucal_cpu_disable(unsigned int cpu)
+{
+	int ret;
+
+	if (cpu >= PMUCAL_NUM_CORES) {
+		pr_err("%s core index(%d) is out of supported range (0~%d).\n",
+				PMUCAL_PREFIX, cpu, PMUCAL_NUM_CORES);
+		return -EINVAL;
+	}
+
+	if (!pmucal_cpu_list[cpu].off) {
+		pr_err("%s there is no sequence element for core(%d) power-off.\n",
+				PMUCAL_PREFIX, cpu);
+		return -ENOENT;
+	}
+
+	ret = pmucal_rae_handle_seq(pmucal_cpu_list[cpu].off,
+				pmucal_cpu_list[cpu].num_off);
+	if (ret) {
+		pr_err("%s %s: error on handling disable sequence. (cpu : %d)\n",
+				PMUCAL_PREFIX, __func__, cpu);
+		return ret;
+	}
+
+	return 0;
+}
+
+/**
+ *  pmucal_cpu_is_enabled - checks whether a core is enabled or not.
+ *		            exposed to PWRCAL interface.
+ *
+ *  @cpu: cpu core index.
+ *
+ *  Returns 1 when the core is enabled, 0 when the core is disabled.
+ *  Otherwise, negative error code.
+ */
+int pmucal_cpu_is_enabled(unsigned int cpu)
+{
+	int i;
+
+	if (cpu >= PMUCAL_NUM_CORES) {
+		pr_err("%s core index(%d) is out of supported range (0~%d).\n",
+				PMUCAL_PREFIX, cpu, PMUCAL_NUM_CORES);
+		return -EINVAL;
+	}
+
+	if (!pmucal_cpu_list[cpu].status) {
+		pr_err("%s there is no sequence element for core(%d) status.\n",
+				PMUCAL_PREFIX, cpu);
+		return -ENOENT;
+	}
+
+	pmucal_rae_handle_seq(pmucal_cpu_list[cpu].status,
+				pmucal_cpu_list[cpu].num_status);
+
+	for (i = 0; i < pmucal_cpu_list[cpu].num_status; i++) {
+		if (pmucal_cpu_list[cpu].status[i].value !=
+				pmucal_cpu_list[cpu].status[i].mask)
+			break;
+	}
+
+	if (i == pmucal_cpu_list[cpu].num_status)
+		return 1;
+	else
+		return 0;
+}
+
+/**
+ *  pmucal_cpu_cluster_enable - enables a cluster.
+ *		            exposed to PWRCAL interface.
+ *
+ *  @cluster: cpu cluster index.
+ *
+ *  Returns 0 on success. Otherwise, negative error code.
+ */
+int pmucal_cpu_cluster_enable(unsigned int cluster)
+{
+	int ret;
+
+	if (cluster >= PMUCAL_NUM_CLUSTERS) {
+		pr_err("%s cluster index(%d) is out of supported range (0~%d).\n",
+				PMUCAL_PREFIX, cluster, PMUCAL_NUM_CLUSTERS);
+		return -EINVAL;
+	}
+
+	if (!pmucal_cluster_list[cluster].on) {
+		pr_err("%s there is no sequence element for cluster(%d) power-on.\n",
+				PMUCAL_PREFIX, cluster);
+		return -ENOENT;
+	}
+
+	ret = pmucal_rae_handle_seq(pmucal_cluster_list[cluster].on,
+				pmucal_cluster_list[cluster].num_on);
+	if (ret) {
+		pr_err("%s %s: error on handling enable sequence. (cluster : %d)\n",
+				PMUCAL_PREFIX, __func__, cluster);
+		return ret;
+	}
+
+	return 0;
+}
+
+/**
+ *  pmucal_cpu_cluster_disable - disables a cluster.
+ *		             exposed to PWRCAL interface.
+ *
+ *  @cluster: cpu cluster index.
+ *
+ *  Returns 0 on success. Otherwise, negative error code.
+ */
+int pmucal_cpu_cluster_disable(unsigned int cluster)
+{
+	int ret;
+
+	if (cluster >= PMUCAL_NUM_CLUSTERS) {
+		pr_err("%s cluster index(%d) is out of supported range (0~%d).\n",
+				PMUCAL_PREFIX, cluster, PMUCAL_NUM_CLUSTERS);
+		return -EINVAL;
+	}
+
+	if (!pmucal_cluster_list[cluster].off) {
+		pr_err("%s there is no sequence element for cluster(%d) power-off.\n",
+				PMUCAL_PREFIX, cluster);
+		return -ENOENT;
+	}
+
+	ret = pmucal_rae_handle_seq(pmucal_cluster_list[cluster].off,
+				pmucal_cluster_list[cluster].num_off);
+	if (ret) {
+		pr_err("%s %s: error on handling disable sequence. (cluster : %d)\n",
+				PMUCAL_PREFIX, __func__, cluster);
+		return ret;
+	}
+
+	return 0;
+}
+
+/**
+ *  pmucal_cpu_cluster_is_enabled - checks whether a cluster is enabled or not.
+ *		                exposed to PWRCAL interface.
+ *
+ *  @cluster: cpu cluster index.
+ *
+ *  Returns 1 when the cluster is enabled, 0 when disabled.
+ *  Otherwise, negative error code.
+ */
+int pmucal_cpu_cluster_is_enabled(unsigned int cluster)
+{
+	int i;
+
+	if (cluster >= PMUCAL_NUM_CLUSTERS) {
+		pr_err("%s cluster index(%d) is out of supported range (0~%d).\n",
+				PMUCAL_PREFIX, cluster, PMUCAL_NUM_CLUSTERS);
+		return -EINVAL;
+	}
+
+	if (!pmucal_cluster_list[cluster].status) {
+		pr_err("%s there is no sequence element for cluster(%d) status.\n",
+				PMUCAL_PREFIX, cluster);
+		return -ENOENT;
+	}
+
+	pmucal_rae_handle_seq(pmucal_cluster_list[cluster].status,
+				pmucal_cluster_list[cluster].num_status);
+
+	for (i = 0; i < pmucal_cluster_list[cluster].num_status; i++) {
+		if (pmucal_cluster_list[cluster].status[i].value !=
+				pmucal_cluster_list[cluster].status[i].mask)
+			break;
+	}
+
+	if (i == pmucal_cluster_list[cluster].num_status)
+		return 1;
+	else
+		return 0;
+}
+
+/**
+ *  pmucal_cpu_init - Init function of PMUCAL CPU common logic.
+ *		            exposed to PWRCAL interface.
+ *
+ *  Returns 0 on success. Otherwise, negative error code.
+ */
+int __init pmucal_cpu_init(void)
+{
+	int ret = 0, i;
+
+	if (!ARRAY_SIZE(pmucal_cpu_list) || !ARRAY_SIZE(pmucal_cluster_list)) {
+		pr_err("%s %s: there is no cpu/cluster list. aborting init...\n",
+				PMUCAL_PREFIX, __func__);
+		return -ENOENT;
+	}
+
+	/* convert physical base address to virtual addr */
+	for (i = 0; i < ARRAY_SIZE(pmucal_cpu_list); i++) {
+		/* skip non-existing cores */
+		if (!pmucal_cpu_list[i].num_on && !pmucal_cpu_list[i].num_off && !pmucal_cpu_list[i].num_status)
+			continue;
+
+		ret = pmucal_rae_phy2virt(pmucal_cpu_list[i].on,
+					pmucal_cpu_list[i].num_on);
+		if (ret) {
+			pr_err("%s %s: error on PA2VA conversion. seq:enable, core_id:%d. aborting init...\n",
+					PMUCAL_PREFIX, __func__, i);
+			goto out;
+		}
+
+		ret = pmucal_rae_phy2virt(pmucal_cpu_list[i].off,
+					pmucal_cpu_list[i].num_off);
+		if (ret) {
+			pr_err("%s %s: error on PA2VA conversion. seq:disable, core_id:%d. aborting init...\n",
+					PMUCAL_PREFIX, __func__, i);
+			goto out;
+		}
+
+		ret = pmucal_rae_phy2virt(pmucal_cpu_list[i].status,
+					pmucal_cpu_list[i].num_status);
+		if (ret) {
+			pr_err("%s %s: error on PA2VA conversion. seq:status, core_id:%d. aborting init...\n",
+					PMUCAL_PREFIX, __func__, i);
+			goto out;
+		}
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pmucal_cluster_list); i++) {
+		/* skip non-existing clusters */
+		if (!pmucal_cluster_list[i].num_on && !pmucal_cluster_list[i].num_off && !pmucal_cluster_list[i].num_status)
+			continue;
+
+		ret = pmucal_rae_phy2virt(pmucal_cluster_list[i].on,
+					pmucal_cluster_list[i].num_on);
+		if (ret) {
+			pr_err("%s %s: error on PA2VA conversion. seq:enable, cluster_id:%d. aborting init...\n",
+					PMUCAL_PREFIX, __func__, i);
+			goto out;
+		}
+
+		ret = pmucal_rae_phy2virt(pmucal_cluster_list[i].off,
+					pmucal_cluster_list[i].num_off);
+		if (ret) {
+			pr_err("%s %s: error on PA2VA conversion. seq:disable, cluster_id:%d. aborting init...\n",
+					PMUCAL_PREFIX, __func__, i);
+			goto out;
+		}
+
+		ret = pmucal_rae_phy2virt(pmucal_cluster_list[i].status,
+					pmucal_cluster_list[i].num_status);
+		if (ret) {
+			pr_err("%s %s: error on PA2VA conversion. seq:status, cluster_id:%d. aborting init...\n",
+					PMUCAL_PREFIX, __func__, i);
+			goto out;
+		}
+	}
+
+out:
+	return ret;
+}

drivers/soc/samsung/pwrcal/pmucal_mod/pmucal_cpu.h

@@ -0,0 +1,47 @@
+#ifndef __PMUCAL_CPU_H__
+#define __PMUCAL_CPU_H__
+#include "pmucal_common.h"
+
+struct pmucal_cpu {
+	u32 id;
+	struct pmucal_seq *on;
+	struct pmucal_seq *off;
+	struct pmucal_seq *status;
+	u32 num_on;
+	u32 num_off;
+	u32 num_status;
+};
+
+/* Chip-independent enumeration for CPU core.
+ * All cores should be described in here.
+ */
+enum pmucal_cpu_corenum {
+	CPU_CORE0 = 0,
+	CPU_CORE1,
+	CPU_CORE2,
+	CPU_CORE3,
+	CPU_CORE4,
+	CPU_CORE5,
+	CPU_CORE6,
+	CPU_CORE7,
+	PMUCAL_NUM_CORES,
+};
+
+/* Chip-independent enumeration for CPU cluster
+ * All clusters should be described in here.
+ */
+enum pmucal_cpu_clusternum {
+	CPU_CLUSTER0 = 0,
+	CPU_CLUSTER1,
+	PMUCAL_NUM_CLUSTERS,
+};
+
+/* APIs to be supported to PWRCAL interface */
+extern int pmucal_cpu_enable(unsigned int cpu);
+extern int pmucal_cpu_disable(unsigned int cpu);
+extern int pmucal_cpu_is_enabled(unsigned int cpu);
+extern int pmucal_cpu_cluster_enable(unsigned int cluster);
+extern int pmucal_cpu_cluster_disable(unsigned int cluster);
+extern int pmucal_cpu_cluster_is_enabled(unsigned int cluster);
+extern int pmucal_cpu_init(void);
+#endif

drivers/soc/samsung/pwrcal/pmucal_mod/pmucal_local.c

@@ -0,0 +1,201 @@
+#include "pmucal_local.h"
+#include "pmucal_rae.h"
+#ifdef CONFIG_SOC_EXYNOS7570
+#include "./S5E7570/pmucal_local_exynos7570.h"
+#endif
+
+#ifndef PWRCAL_TARGET_LINUX
+struct pmucal_pd *pmucal_blkpwr_list[PMUCAL_NUM_PDS];
+#endif
+
+/**
+ *  pmucal_local_enable - enables a power domain.
+ *		        exposed to PWRCAL interface.
+ *
+ *  @pd_id: power domain index.
+ *
+ *  Returns 0 on success. Otherwise, negative error code.
+ */
+int pmucal_local_enable(unsigned int pd_id)
+{
+	int ret;
+
+	exynos_ss_printk("%s %s+\n", PMUCAL_PREFIX, __func__);
+	trace_printk("%s %s+\n", PMUCAL_PREFIX, __func__);
+
+	if (pd_id >= PMUCAL_NUM_PDS) {
+		pr_err("%s pd index(%d) is out of supported range (0~%d).\n",
+				PMUCAL_PREFIX, pd_id, PMUCAL_NUM_PDS);
+		return -EINVAL;
+	}
+
+	if (!pmucal_pd_list[pd_id].on) {
+		pr_err("%s there is no sequence element for pd(%d) power-on.\n",
+				PMUCAL_PREFIX, pd_id);
+		return -ENOENT;
+	}
+
+	ret = pmucal_rae_handle_seq(pmucal_pd_list[pd_id].on,
+				pmucal_pd_list[pd_id].num_on);
+	if (ret) {
+		pr_err("%s %s: error on handling enable sequence. (pd_id : %d)\n",
+				PMUCAL_PREFIX, __func__, pd_id);
+		return ret;
+	}
+
+	ret = pmucal_rae_restore_seq(pmucal_pd_list[pd_id].save,
+				pmucal_pd_list[pd_id].num_save);
+	if (ret) {
+		pr_err("%s %s: error on handling restore sequence. (pd_id : %d)\n",
+				PMUCAL_PREFIX, __func__, pd_id);
+		return ret;
+	}
+
+	exynos_ss_printk("%s %s-\n", PMUCAL_PREFIX, __func__);
+	trace_printk("%s %s-\n", PMUCAL_PREFIX, __func__);
+
+	return 0;
+}
+
+/**
+ *  pmucal_local_disable - disables a power domain.
+ *		        exposed to PWRCAL interface.
+ *
+ *  @pd_id: power domain index.
+ *
+ *  Returns 0 on success. Otherwise, negative error code.
+ */
+int pmucal_local_disable(unsigned int pd_id)
+{
+	int ret;
+
+	exynos_ss_printk("%s %s+\n", PMUCAL_PREFIX, __func__);
+	trace_printk("%s %s+\n", PMUCAL_PREFIX, __func__);
+
+	if (pd_id >= PMUCAL_NUM_PDS) {
+		pr_err("%s pd index(%d) is out of supported range (0~%d).\n",
+				PMUCAL_PREFIX, pd_id, PMUCAL_NUM_PDS);
+		return -EINVAL;
+	}
+
+	if (!pmucal_pd_list[pd_id].off) {
+		pr_err("%s there is no sequence element for pd(%d) power-off.\n",
+				PMUCAL_PREFIX, pd_id);
+		return -ENOENT;
+	}
+
+	pmucal_rae_save_seq(pmucal_pd_list[pd_id].save,
+				pmucal_pd_list[pd_id].num_save);
+
+	ret = pmucal_rae_handle_seq(pmucal_pd_list[pd_id].off,
+				pmucal_pd_list[pd_id].num_off);
+	if (ret) {
+		pr_err("%s %s: error on handling disable sequence. (pd_id : %d)\n",
+				PMUCAL_PREFIX, __func__, pd_id);
+		return ret;
+	}
+
+	exynos_ss_printk("%s %s-\n", PMUCAL_PREFIX, __func__);
+	trace_printk("%s %s-\n", PMUCAL_PREFIX, __func__);
+
+	return 0;
+}
+
+/**
+ *  pmucal_local_is_enabled - checks whether a power domain is enabled or not.
+ *		            exposed to PWRCAL interface.
+ *
+ *  @pd_id: power domain index.
+ *
+ *  Returns 1 when the pd is enabled, 0 when disabled.
+ *  Otherwise, negative error code.
+ */
+int pmucal_local_is_enabled(unsigned int pd_id)
+{
+	int i;
+
+	if (pd_id >= PMUCAL_NUM_PDS) {
+		pr_err("%s pd index(%d) is out of supported range (0~%d).\n",
+				PMUCAL_PREFIX, pd_id, PMUCAL_NUM_PDS);
+		return -EINVAL;
+	}
+
+	if (!pmucal_pd_list[pd_id].status) {
+		pr_err("%s there is no sequence element for pd(%d) status.\n",
+				PMUCAL_PREFIX, pd_id);
+		return -ENOENT;
+	}
+
+	pmucal_rae_handle_seq(pmucal_pd_list[pd_id].status,
+				pmucal_pd_list[pd_id].num_status);
+
+	for (i = 0; i < pmucal_pd_list[pd_id].num_status; i++) {
+		if (pmucal_pd_list[pd_id].status[i].value !=
+				pmucal_pd_list[pd_id].status[i].mask)
+			break;
+	}
+
+	if (i == pmucal_pd_list[pd_id].num_status)
+		return 1;
+	else
+		return 0;
+}
+
+/**
+ *  pmucal_local_init - Init function of PMUCAL LOCAL common logic.
+ *		            exposed to PWRCAL interface.
+ *
+ *  Returns 0 on success. Otherwise, negative error code.
+ */
+int __init pmucal_local_init(void)
+{
+	int ret = 0, i;
+
+	if (!ARRAY_SIZE(pmucal_pd_list)) {
+		pr_err("%s %s: there is no pd list. aborting init...\n",
+				PMUCAL_PREFIX, __func__);
+		return -ENOENT;
+	}
+
+	/* convert physical base address to virtual addr */
+	for (i = 0; i < ARRAY_SIZE(pmucal_pd_list); i++) {
+		/* skip non-existing pd */
+		if (!pmucal_pd_list[i].num_on && !pmucal_pd_list[i].num_off && !pmucal_pd_list[i].num_status)
+			continue;
+
+		ret = pmucal_rae_phy2virt(pmucal_pd_list[i].on,
+					pmucal_pd_list[i].num_on);
+		if (ret) {
+			pr_err("%s %s: error on PA2VA conversion. seq:on, pd_id:%d. aborting init...\n",
+					PMUCAL_PREFIX, __func__, i);
+			goto out;
+		}
+
+		ret = pmucal_rae_phy2virt(pmucal_pd_list[i].save,
+					pmucal_pd_list[i].num_save);
+		if (ret) {
+			pr_err("%s %s: error on PA2VA conversion. seq:save, pd_id:%d. aborting init...\n",
+					PMUCAL_PREFIX, __func__, i);
+			goto out;
+		}
+
+		ret = pmucal_rae_phy2virt(pmucal_pd_list[i].off,
+					pmucal_pd_list[i].num_off);
+		if (ret) {
+			pr_err("%s %s: error on PA2VA conversion. seq:off, pd_id:%d. aborting init...\n",
+					PMUCAL_PREFIX, __func__, i);
+			goto out;
+		}
+
+		ret = pmucal_rae_phy2virt(pmucal_pd_list[i].status,
+					pmucal_pd_list[i].num_status);
+		if (ret) {
+			pr_err("%s %s: error on PA2VA conversion. seq:status, pd_id:%d. aborting init...\n",
+					PMUCAL_PREFIX, __func__, i);
+			goto out;
+		}
+	}
+
+out:
+	return ret;
+}

drivers/soc/samsung/pwrcal/pmucal_mod/pmucal_local.h

@@ -0,0 +1,49 @@
+#ifndef __PMUCAL_LOCAL_H__
+#define __PMUCAL_LOCAL_H__
+#include "pmucal_common.h"
+
+/* In Exynos, the number of MAX_POWER_DOMAIN is less than 15 */
+#define PMUCAL_MAX_PARENT_PD		15
+
+/* will be a member of struct exynos_pm_domain */
+struct pmucal_pd {
+	u32 id;
+	char *name;
+	struct pmucal_seq *on;
+	struct pmucal_seq *save;
+	struct pmucal_seq *off;
+	struct pmucal_seq *status;
+	u32 num_on;
+	u32 num_save;
+	u32 num_off;
+	u32 num_status;
+};
+
+/* Chip-independent enumeration for local power domains
+ * All power domains should be described in here.
+ */
+enum pmucal_local_pdnum {
+	PD_G3D = 0,
+	PD_CAM0,
+	PD_CAM1,
+	PD_ISP,
+	PD_ISP0,
+	PD_ISP1,
+	PD_MFC,
+	PD_MSCL,
+	PD_MFCMSCL,
+	PD_AUD,
+	PD_DISP,
+	PD_DISP0,
+	PD_DISP1,
+	PD_DISPAUD,
+	PMUCAL_NUM_PDS,
+};
+
+/* APIs to be supported to PWRCAL interface */
+extern int pmucal_local_enable(unsigned int pd_id);
+extern int pmucal_local_disable(unsigned int pd_id);
+extern int pmucal_local_is_enabled(unsigned int pd_id);
+extern int pmucal_local_init(void);
+
+#endif

drivers/soc/samsung/pwrcal/pmucal_mod/pmucal_rae.c

@@ -0,0 +1,293 @@
+#include "../pwrcal-env.h"
+#include "pmucal_common.h"
+#include "pmucal_rae.h"
+#ifdef CONFIG_SOC_EXYNOS7570
+#include "./S5E7570/pmucal_p2vmap_exynos7570.h"
+#endif
+
+/**
+ * A global index for pmucal_rae_handle_seq.
+ * it should be helpful in ramdump.
+ */
+static unsigned int pmucal_rae_seq_idx;
+
+/**
+ *  pmucal_rae_phy2virt - converts a sequence's PA to VA described in pmucal_p2v_list.
+ *			  exposed to PMUCAL common logics.(CPU/System/Local)
+ *
+ *  @seq: Sequence array to be converted.
+ *  @seq_size: Array size of seq.
+ *
+ *  Returns 0 on success. Otherwise, negative error code.
+ */
+int pmucal_rae_phy2virt(struct pmucal_seq *seq, unsigned int seq_size)
+{
+	int i, j;
+
+	for (i = 0; i < seq_size; i++) {
+		if (!seq[i].base_pa && !seq[i].cond_base_pa) {
+			pr_err("%s %s: PA absent in seq element (idx:%d)\n",
+					PMUCAL_PREFIX, __func__, i);
+			return -ENOENT;
+		}
+
+		if (seq[i].base_pa) {
+			for (j = 0; j < ARRAY_SIZE(pmucal_p2v_list); j++)
+				if (pmucal_p2v_list[j].pa == (phys_addr_t)seq[i].base_pa)
+					break;
+
+			if (j == ARRAY_SIZE(pmucal_p2v_list)) {
+				pr_err("%s %s: there is no such PA in p2v_list (idx:%d)\n",
+						PMUCAL_PREFIX, __func__, i);
+				return -ENOENT;
+			} else {
+				seq[i].base_va = pmucal_p2v_list[j].va;
+			}
+		}
+		if (seq[i].cond_base_pa) {
+			for (j = 0; j < ARRAY_SIZE(pmucal_p2v_list); j++)
+				if (pmucal_p2v_list[j].pa == (phys_addr_t)seq[i].cond_base_pa)
+					break;
+
+			if (j == ARRAY_SIZE(pmucal_p2v_list)) {
+				pr_err("%s %s: there is no such PA in p2v_list (idx:%d)\n",
+						PMUCAL_PREFIX, __func__, i);
+				return -ENOENT;
+			} else {
+				seq[i].cond_base_va = pmucal_p2v_list[j].va;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static inline bool pmucal_rae_check_condition(struct pmucal_seq *seq)
+{
+	u32 reg;
+	reg = __raw_readl(seq->cond_base_va + seq->cond_offset);
+	reg &= seq->cond_mask;
+	if (reg == seq->cond_value)
+		return true;
+	else
+		return false;
+}
+
+static inline bool pmucal_rae_check_value(struct pmucal_seq *seq)
+{
+	u32 reg;
+	reg = __raw_readl(seq->base_va + seq->offset);
+	reg &= seq->mask;
+	if (reg == seq->value)
+		return true;
+	else
+		return false;
+}
+
+static int pmucal_rae_wait(struct pmucal_seq *seq)
+{
+	u32 timeout = 0;
+
+	while (1) {
+		if (pmucal_rae_check_value(seq))
+			break;
+		timeout++;
+		udelay(1);
+		if (timeout > 1000) {
+			u32 reg;
+			reg = __raw_readl(seq->base_va + seq->offset);
+			reg &= seq->mask;
+			pr_err("%s %s:timed out during wait. (value:0x%x, seq_idx = %d)\n",
+						PMUCAL_PREFIX, __func__, reg, pmucal_rae_seq_idx);
+			return -ETIMEDOUT;
+		}
+	}
+
+	return 0;
+}
+
+static inline void pmucal_rae_read(struct pmucal_seq *seq)
+{
+	u32 reg;
+	reg = __raw_readl(seq->base_va + seq->offset);
+	seq->value = (reg & seq->mask);
+}
+
+static inline void pmucal_rae_write(struct pmucal_seq *seq)
+{
+	if (seq->mask == U32_MAX)
+		__raw_writel(seq->value, seq->base_va + seq->offset);
+	else {
+		u32 reg;
+		reg = __raw_readl(seq->base_va + seq->offset);
+		reg = (reg & ~seq->mask) | seq->value;
+		__raw_writel(reg, seq->base_va + seq->offset);
+	}
+}
+
+void pmucal_rae_save_seq(struct pmucal_seq *seq, unsigned int seq_size)
+{
+	int i;
+
+	exynos_ss_printk("%s %s+\n", PMUCAL_PREFIX, __func__);
+	trace_printk("%s %s+\n", PMUCAL_PREFIX, __func__);
+
+	for (i = 0; i < seq_size; i++) {
+		switch (seq[i].access_type) {
+		case PMUCAL_COND_SAVE_RESTORE:
+			if (!pmucal_rae_check_condition(&seq[i]))
+				break;
+		case PMUCAL_SAVE_RESTORE:
+			pmucal_rae_read(&seq[i]);
+			seq[i].need_restore = true;
+			break;
+		case PMUCAL_CHECK_SKIP:
+		case PMUCAL_COND_CHECK_SKIP:
+		case PMUCAL_WAIT:
+			break;
+		default:
+			break;
+		}
+	}
+
+	exynos_ss_printk("%s %s-\n", PMUCAL_PREFIX, __func__);
+	trace_printk("%s %s-\n", PMUCAL_PREFIX, __func__);
+}
+
+int pmucal_rae_restore_seq(struct pmucal_seq *seq, unsigned int seq_size)
+{
+	int i, ret;
+
+	exynos_ss_printk("%s %s+\n", PMUCAL_PREFIX, __func__);
+	trace_printk("%s %s+\n", PMUCAL_PREFIX, __func__);
+
+	for (i = 0; i < seq_size; i++) {
+		if (seq[i].need_skip) {
+			seq[i].need_skip = false;
+			continue;
+		}
+
+		switch (seq[i].access_type) {
+		case PMUCAL_COND_SAVE_RESTORE:
+			if (!pmucal_rae_check_condition(&seq[i]))
+				break;
+		case PMUCAL_SAVE_RESTORE:
+			if (seq[i].need_restore) {
+				seq[i].need_restore = false;
+				pmucal_rae_write(&seq[i]);
+			}
+			break;
+		case PMUCAL_CHECK_SKIP:
+			if (pmucal_rae_check_value(&seq[i])) {
+				if ((i+1) < seq_size)
+					seq[i+1].need_skip = true;
+			} else {
+				if ((i+1) < seq_size)
+					seq[i+1].need_skip = false;
+			}
+			break;
+		case PMUCAL_COND_CHECK_SKIP:
+			if (pmucal_rae_check_condition(&seq[i])) {
+				if (pmucal_rae_check_value(&seq[i])) {
+					if ((i+1) < seq_size)
+						seq[i+1].need_skip = true;
+				} else {
+					if ((i+1) < seq_size)
+						seq[i+1].need_skip = false;
+				}
+			} else {
+				if ((i+1) < seq_size)
+					seq[i+1].need_skip = true;
+			}
+			break;
+		case PMUCAL_WAIT:
+			ret = pmucal_rae_wait(&seq[i]);
+			if (ret)
+				return ret;
+			break;
+		default:
+			break;
+		}
+	}
+
+	exynos_ss_printk("%s %s-\n", PMUCAL_PREFIX, __func__);
+	trace_printk("%s %s-\n", PMUCAL_PREFIX, __func__);
+
+	return 0;
+}
+
+/**
+ *  pmucal_rae_handle_seq - handles a sequence array based on each element's access_type.
+ *			    exposed to PMUCAL common logics.(CPU/System/Local)
+ *
+ *  @seq: Sequence array to be handled.
+ *  @seq_size: Array size of seq.
+ *
+ *  Returns 0 on success. Otherwise, negative error code.
+ */
+int pmucal_rae_handle_seq(struct pmucal_seq *seq, unsigned int seq_size)
+{
+	int ret, i;
+
+	for (i = 0; i < seq_size; i++) {
+		pmucal_rae_seq_idx = i;
+
+		switch (seq[i].access_type) {
+		case PMUCAL_READ:
+			pmucal_rae_read(&seq[i]);
+			break;
+		case PMUCAL_WRITE:
+			pmucal_rae_write(&seq[i]);
+			break;
+		case PMUCAL_COND_READ:
+			if (pmucal_rae_check_condition(&seq[i]))
+				pmucal_rae_read(&seq[i]);
+			break;
+		case PMUCAL_COND_WRITE:
+			if (pmucal_rae_check_condition(&seq[i]))
+				pmucal_rae_write(&seq[i]);
+			break;
+		case PMUCAL_WAIT:
+			ret = pmucal_rae_wait(&seq[i]);
+			if (ret)
+				return ret;
+			break;
+		default:
+			pr_err("%s %s:invalid PMUCAL access type\n", PMUCAL_PREFIX, __func__);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ *  pmucal_rae_init - Init function of PMUCAL Register Access Engine.
+ *	  	      exposed to PWRCAL interface.
+ *
+ *  Returns 0 on success. Otherwise, negative error code.
+ */
+int __init pmucal_rae_init(void)
+{
+	int i;
+
+	if (!ARRAY_SIZE(pmucal_p2v_list)) {
+		pr_err("%s %s: there is no p2vmap. aborting init...\n",
+				PMUCAL_PREFIX, __func__);
+		return -ENOENT;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pmucal_p2v_list); i++) {
+#ifdef PWRCAL_TARGET_LINUX
+		pmucal_p2v_list[i].va = ioremap(pmucal_p2v_list[i].pa, SZ_64K);
+		if (pmucal_p2v_list[i].va == NULL) {
+			pr_err("%s %s:ioremap failed.\n", PMUCAL_PREFIX, __func__);
+			return -ENOMEM;
+		}
+#else
+		pmucal_p2v_list[i].va = (void *)(pmucal_p2v_list[i].pa);
+#endif
+	}
+
+	return 0;
+}

drivers/soc/samsung/pwrcal/pmucal_mod/pmucal_rae.h

@@ -0,0 +1,21 @@
+#ifndef __PMUCAL_RAE_H__
+#define __PMUCAL_RAE_H__
+
+#include <asm/io.h>
+
+/* for phy2virt address mapping */
+struct p2v_map {
+	phys_addr_t pa;
+	void __iomem *va;
+};
+
+#define DEFINE_PHY(p) { .pa = p }
+
+/* APIs to be supported to PMUCAL common logics */
+extern int pmucal_rae_init(void);
+extern int pmucal_rae_handle_seq(struct pmucal_seq *seq, unsigned int seq_size);
+extern void pmucal_rae_save_seq(struct pmucal_seq *seq, unsigned int seq_size);
+extern int pmucal_rae_restore_seq(struct pmucal_seq *seq, unsigned int seq_size);
+extern int pmucal_rae_phy2virt(struct pmucal_seq *seq, unsigned int seq_size);
+
+#endif

drivers/soc/samsung/pwrcal/pmucal_mod/pmucal_system.c

@@ -0,0 +1,220 @@
+#include "pmucal_system.h"
+#include "pmucal_rae.h"
+#ifdef CONFIG_SOC_EXYNOS7570
+#include "./S5E7570/pmucal_system_exynos7570.h"
+#endif
+
+/**
+ *  pmucal_system_enter - prepares to enter a system power mode.
+ *		        exposed to PWRCAL interface.
+ *
+ *  @mode: index of system power mode described in pmucal_system.h.
+ *
+ *  Returns 0 on success. Otherwise, negative error code.
+ */
+int pmucal_system_enter(int mode)
+{
+	int ret;
+
+	exynos_ss_printk("%s %s+\n", PMUCAL_PREFIX, __func__);
+	trace_printk("%s %s+\n", PMUCAL_PREFIX, __func__);
+
+	if (mode >= NUM_SYS_POWERDOWN) {
+		pr_err("%s %s: mode index(%d) is out of supported range (0~%d).\n",
+				PMUCAL_PREFIX, __func__, mode, NUM_SYS_POWERDOWN);
+		return -EINVAL;
+	}
+
+	if (!pmucal_lpm_list[mode].enter) {
+		pr_err("%s %s: there is no sequence element for entering mode(%d).\n",
+				PMUCAL_PREFIX, __func__, mode);
+		return -ENOENT;
+	}
+
+	pmucal_rae_save_seq(pmucal_lpm_list[mode].save, pmucal_lpm_list[mode].num_save);
+
+	ret = pmucal_rae_handle_seq(pmucal_lpm_list[mode].enter,
+				pmucal_lpm_list[mode].num_enter);
+	if (ret) {
+		pr_err("%s %s: error on handling enter sequence. (mode : %d)\n",
+				PMUCAL_PREFIX, __func__, mode);
+		return ret;
+	}
+
+	exynos_ss_printk("%s %s-\n", PMUCAL_PREFIX, __func__);
+	trace_printk("%s %s-\n", PMUCAL_PREFIX, __func__);
+
+	return 0;
+}
+
+/**
+ *  pmucal_system_exit - prepares to exit a system power mode.
+ *		        exposed to PWRCAL interface.
+ *
+ *  @mode: index of system power mode described in pmucal_system.h.
+ *
+ *  Returns 0 on success. Otherwise, negative error code.
+ */
+int pmucal_system_exit(int mode)
+{
+	int ret;
+
+	exynos_ss_printk("%s %s+\n", PMUCAL_PREFIX, __func__);
+	trace_printk("%s %s+\n", PMUCAL_PREFIX, __func__);
+
+	if (mode >= NUM_SYS_POWERDOWN) {
+		pr_err("%s %s: mode index(%d) is out of supported range (0~%d).\n",
+				PMUCAL_PREFIX, __func__, mode, NUM_SYS_POWERDOWN);
+		return -EINVAL;
+	}
+
+	if (!pmucal_lpm_list[mode].exit) {
+		pr_err("%s %s: there is no sequence element for exiting mode(%d).\n",
+				PMUCAL_PREFIX, __func__, mode);
+		return -ENOENT;
+	}
+
+	ret = pmucal_rae_handle_seq(pmucal_lpm_list[mode].exit,
+				pmucal_lpm_list[mode].num_exit);
+	if (ret) {
+		pr_err("%s %s: error on handling exit sequence. (mode : %d)\n",
+				PMUCAL_PREFIX, __func__, mode);
+		return ret;
+	}
+
+	ret = pmucal_rae_restore_seq(pmucal_lpm_list[mode].save,
+				pmucal_lpm_list[mode].num_save);
+	if (ret) {
+		pr_err("%s %s: error on handling restore sequence. (mode : %d)\n",
+				PMUCAL_PREFIX, __func__, mode);
+		return ret;
+	}
+
+	exynos_ss_printk("%s %s-\n", PMUCAL_PREFIX, __func__);
+	trace_printk("%s %s-\n", PMUCAL_PREFIX, __func__);
+
+	return 0;
+}
+
+/**
+ *  pmucal_system_earlywakeup - prepares to early-wakeup from a system power mode.
+ *				exposed to PWRCAL interface.
+ *
+ *  @mode: index of system power mode described in pmucal_system.h.
+ *
+ *  Returns 0 on success. Otherwise, negative error code.
+ */
+int pmucal_system_earlywakeup(int mode)
+{
+	int ret;
+
+	exynos_ss_printk("%s %s+\n", PMUCAL_PREFIX, __func__);
+	trace_printk("%s %s+\n", PMUCAL_PREFIX, __func__);
+
+	if (mode >= NUM_SYS_POWERDOWN) {
+		pr_err("%s %s: mode index(%d) is out of supported range (0~%d).\n",
+				PMUCAL_PREFIX, __func__, mode, NUM_SYS_POWERDOWN);
+		return -EINVAL;
+	}
+
+	if (!pmucal_lpm_list[mode].early_wakeup) {
+		pr_err("%s %s: there is no sequence element for early_wkup mode(%d).\n",
+				PMUCAL_PREFIX, __func__, mode);
+		return -ENOENT;
+	}
+
+	ret = pmucal_rae_handle_seq(pmucal_lpm_list[mode].early_wakeup,
+				pmucal_lpm_list[mode].num_early_wakeup);
+	if (ret) {
+		pr_err("%s %s: error on handling elry_wkup sequence. (mode : %d)\n",
+				PMUCAL_PREFIX, __func__, mode);
+		return ret;
+	}
+
+	ret = pmucal_rae_restore_seq(pmucal_lpm_list[mode].save,
+				pmucal_lpm_list[mode].num_save);
+	if (ret) {
+		pr_err("%s %s: error on handling restore sequence. (mode : %d)\n",
+				PMUCAL_PREFIX, __func__, mode);
+		return ret;
+	}
+
+	exynos_ss_printk("%s %s-\n", PMUCAL_PREFIX, __func__);
+	trace_printk("%s %s-\n", PMUCAL_PREFIX, __func__);
+
+	return 0;
+}
+
+/**
+ *  pmucal_system_init - Init function of PMUCAL SYSTEM common logic.
+ *		            exposed to PWRCAL interface.
+ *
+ *  Returns 0 on success. Otherwise, negative error code.
+ */
+int __init pmucal_system_init(void)
+{
+	int ret = 0, i;
+
+	if (!ARRAY_SIZE(pmucal_lpm_init) || !ARRAY_SIZE(pmucal_lpm_list)) {
+		pr_err("%s %s: there is no lpm init seq or lpm list. aborting init...\n",
+				PMUCAL_PREFIX, __func__);
+		return -ENOENT;
+	}
+
+	/* convert physical base address to virtual addr */
+	for (i = 0; i < ARRAY_SIZE(pmucal_lpm_list); i++) {
+		/* skip non-existing power mode */
+		if (!pmucal_lpm_list[i].num_enter && !pmucal_lpm_list[i].num_exit && !pmucal_lpm_list[i].num_early_wakeup)
+			continue;
+
+		ret = pmucal_rae_phy2virt(pmucal_lpm_list[i].enter,
+					pmucal_lpm_list[i].num_enter);
+		if (ret) {
+			pr_err("%s %s: error on PA2VA conversion. seq:enter, mode_id:%d. aborting init...\n",
+					PMUCAL_PREFIX, __func__, i);
+			goto out;
+		}
+
+		ret = pmucal_rae_phy2virt(pmucal_lpm_list[i].save,
+					pmucal_lpm_list[i].num_save);
+		if (ret) {
+			pr_err("%s %s: error on PA2VA conversion. seq:save, mode_id:%d. aborting init...\n",
+					PMUCAL_PREFIX, __func__, i);
+			goto out;
+		}
+
+		ret = pmucal_rae_phy2virt(pmucal_lpm_list[i].exit,
+					pmucal_lpm_list[i].num_exit);
+		if (ret) {
+			pr_err("%s %s: error on PA2VA conversion. seq:exit, mode_id:%d. aborting init...\n",
+					PMUCAL_PREFIX, __func__, i);
+			goto out;
+		}
+
+		ret = pmucal_rae_phy2virt(pmucal_lpm_list[i].early_wakeup,
+					pmucal_lpm_list[i].num_early_wakeup);
+		if (ret) {
+			pr_err("%s %s: error on PA2VA conversion. seq:erlywkup, mode_id:%d. aborting init...\n",
+					PMUCAL_PREFIX, __func__, i);
+			goto out;
+		}
+	}
+
+	ret = pmucal_rae_phy2virt(pmucal_lpm_init, ARRAY_SIZE(pmucal_lpm_init));
+	if (ret) {
+		pr_err("%s %s: error on PA2VA conversion for lpm_init seq. aborting init...\n",
+				PMUCAL_PREFIX, __func__);
+		goto out;
+	}
+
+	/* do default settings for PMU */
+	ret = pmucal_rae_handle_seq(pmucal_lpm_init, ARRAY_SIZE(pmucal_lpm_init));
+	if (ret) {
+		pr_err("%s %s: error on handling lpm_init sequence.\n",
+				PMUCAL_PREFIX, __func__);
+		goto out;
+	}
+
+out:
+	return ret;
+}

drivers/soc/samsung/pwrcal/pmucal_mod/pmucal_system.h

@@ -0,0 +1,39 @@
+#ifndef __PMUCAL_SYSTEM_H__
+#define __PMUCAL_SYSTEM_H__
+#include "pmucal_common.h"
+
+struct pmucal_lpm {
+	u32 id;
+	struct pmucal_seq *enter;
+	struct pmucal_seq *save;
+	struct pmucal_seq *exit;
+	struct pmucal_seq *early_wakeup;
+	u32 num_enter;
+	u32 num_save;
+	u32 num_exit;
+	u32 num_early_wakeup;
+};
+
+/* Chip-independent enumeration for low-power mode
+ * All power modes should be described in here.
+ */
+enum sys_powerdown {
+	SYS_SICD,
+	SYS_SICD_CPD,
+	SYS_AFTR,
+	SYS_STOP,
+	SYS_LPD,
+	SYS_LPA,
+	SYS_ALPA,
+	SYS_DSTOP,
+	SYS_SLEEP,
+	NUM_SYS_POWERDOWN,
+};
+
+/* APIs to be supported to PWRCAL interface */
+extern int pmucal_system_enter(int mode);
+extern int pmucal_system_exit(int mode);
+extern int pmucal_system_earlywakeup(int mode);
+extern int pmucal_system_init(void);
+
+#endif